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9a82579f | 1 | /* Target-dependent code for GDB, the GNU debugger. |
8201327c | 2 | Copyright 2001, 2002 |
9a82579f JS |
3 | Free Software Foundation, Inc. |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef I386_TDEP_H | |
23 | #define I386_TDEP_H | |
24 | ||
8201327c MK |
25 | #include "osabi.h" |
26 | ||
96297dab MK |
27 | /* GDB's i386 target supports both the 32-bit Intel Architecture |
28 | (IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses | |
29 | a similar register layout for both. | |
30 | ||
31 | - General purpose registers | |
32 | - FPU data registers | |
33 | - FPU control registers | |
34 | - SSE data registers | |
35 | - SSE control register | |
36 | ||
37 | The general purpose registers for the x86-64 architecture are quite | |
38 | different from IA-32. Therefore, the FP0_REGNUM target macro | |
39 | determines the register number at which the FPU data registers | |
40 | start. The number of FPU data and control registers is the same | |
41 | for both architectures. The number of SSE registers however, | |
42 | differs and is determined by the num_xmm_regs member of `struct | |
43 | gdbarch_tdep'. */ | |
44 | ||
8201327c | 45 | /* Convention for returning structures. */ |
3ce1502b | 46 | |
8201327c MK |
47 | enum struct_return |
48 | { | |
49 | pcc_struct_return, /* Return "short" structures in memory. */ | |
50 | reg_struct_return /* Return "short" structures in registers. */ | |
3ce1502b MK |
51 | }; |
52 | ||
96297dab MK |
53 | /* i386 architecture specific information. */ |
54 | struct gdbarch_tdep | |
55 | { | |
3ce1502b | 56 | /* ABI. */ |
8201327c | 57 | enum gdb_osabi osabi; |
d2a7c97a | 58 | |
96297dab MK |
59 | /* Number of SSE registers. */ |
60 | int num_xmm_regs; | |
8201327c MK |
61 | |
62 | /* Offset of saved PC in jmp_buf. */ | |
63 | int jb_pc_offset; | |
64 | ||
65 | /* Convention for returning structures. */ | |
66 | enum struct_return struct_return; | |
67 | ||
68 | /* Get saved PC for sigtramp. */ | |
69 | CORE_ADDR (*sigtramp_saved_pc) (struct frame_info *); | |
70 | ||
71 | /* Address range where sigtramp lives. */ | |
72 | CORE_ADDR sigtramp_start; | |
73 | CORE_ADDR sigtramp_end; | |
74 | ||
75 | /* Offset of saved PC in `struct sigcontext'. */ | |
76 | int sc_pc_offset; | |
96297dab MK |
77 | }; |
78 | ||
79 | /* Floating-point registers. */ | |
80 | ||
9a82579f JS |
81 | #define FPU_REG_RAW_SIZE 10 |
82 | ||
96297dab MK |
83 | /* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit |
84 | (at most) in the FPU, but are zero-extended to 32 bits in GDB's | |
85 | register cache. */ | |
86 | ||
87 | /* "Generic" floating point control register. */ | |
88 | #define FPC_REGNUM (FP0_REGNUM + 8) | |
89 | ||
9a82579f | 90 | /* FPU control word. */ |
96297dab MK |
91 | #define FCTRL_REGNUM FPC_REGNUM |
92 | ||
9a82579f | 93 | /* FPU status word. */ |
96297dab MK |
94 | #define FSTAT_REGNUM (FPC_REGNUM + 1) |
95 | ||
9a82579f | 96 | /* FPU register tag word. */ |
96297dab MK |
97 | #define FTAG_REGNUM (FPC_REGNUM + 2) |
98 | ||
99 | /* FPU instruction's code segment selector, called "FPU Instruction | |
100 | Pointer Selector" in the IA-32 manuals. */ | |
101 | #define FISEG_REGNUM (FPC_REGNUM + 3) | |
102 | ||
103 | /* FPU instruction's offset within segment. */ | |
104 | #define FIOFF_REGNUM (FPC_REGNUM + 4) | |
105 | ||
9a82579f | 106 | /* FPU operand's data segment. */ |
96297dab MK |
107 | #define FOSEG_REGNUM (FPC_REGNUM + 5) |
108 | ||
109 | /* FPU operand's offset within segment */ | |
110 | #define FOOFF_REGNUM (FPC_REGNUM + 6) | |
111 | ||
9a82579f | 112 | /* FPU opcode, bottom eleven bits. */ |
96297dab | 113 | #define FOP_REGNUM (FPC_REGNUM + 7) |
9a82579f | 114 | |
96297dab MK |
115 | /* Return non-zero if N corresponds to a FPU data registers. */ |
116 | #define FP_REGNUM_P(n) (FP0_REGNUM <= (n) && (n) < FPC_REGNUM) | |
117 | ||
118 | /* Return non-zero if N corresponds to a FPU control register. */ | |
119 | #define FPC_REGNUM_P(n) (FPC_REGNUM <= (n) && (n) < XMM0_REGNUM) | |
120 | ||
121 | /* SSE registers. */ | |
122 | ||
123 | /* First SSE data register. */ | |
124 | #define XMM0_REGNUM (FPC_REGNUM + 8) | |
125 | ||
126 | /* SSE control/status register. */ | |
127 | #define MXCSR_REGNUM \ | |
128 | (XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs) | |
129 | ||
130 | /* Return non-zero if N corresponds to a SSE data register. */ | |
131 | #define SSE_REGNUM_P(n) (XMM0_REGNUM <= (n) && (n) < MXCSR_REGNUM) | |
132 | ||
133 | /* FIXME: kettenis/2001-11-24: Obsolete macro's. */ | |
134 | #define FCS_REGNUM FISEG_REGNUM | |
135 | #define FCOFF_REGNUM FIOFF_REGNUM | |
136 | #define FDS_REGNUM FOSEG_REGNUM | |
137 | #define FDOFF_REGNUM FOOFF_REGNUM | |
138 | #define IS_FP_REGNUM(n) FP_REGNUM_P (n) | |
139 | #define IS_FPU_CTRL_REGNUM(n) FPC_REGNUM_P (n) | |
140 | #define IS_SSE_REGNUM(n) SSE_REGNUM_P (n) | |
9a82579f | 141 | |
8201327c MK |
142 | #define I386_NUM_GREGS 16 |
143 | #define I386_NUM_FREGS 16 | |
144 | #define I386_NUM_XREGS 9 | |
145 | ||
146 | #define I386_SSE_NUM_REGS (I386_NUM_GREGS + I386_NUM_FREGS \ | |
147 | + I386_NUM_XREGS) | |
148 | ||
149 | /* Sizes of individual register sets. These cover the entire register | |
150 | file, so summing up the sizes of those portions actually present | |
151 | yields REGISTER_BYTES. */ | |
152 | #define I386_SIZEOF_GREGS (I386_NUM_GREGS * 4) | |
153 | #define I386_SIZEOF_FREGS (8 * 10 + 8 * 4) | |
154 | #define I386_SIZEOF_XREGS (8 * 16 + 4) | |
155 | ||
156 | #define I386_SSE_SIZEOF_REGS (I386_SIZEOF_GREGS + I386_SIZEOF_FREGS \ | |
157 | + I386_SIZEOF_XREGS) | |
158 | ||
159 | /* Return the name of register REG. */ | |
fa88f677 | 160 | extern char const *i386_register_name (int reg); |
8201327c MK |
161 | |
162 | /* Return the offset into the register array of the start of register | |
163 | number REG. */ | |
164 | extern int i386_register_byte (int reg); | |
165 | ||
166 | /* Return the number of bytes of storage in GDB's register array | |
167 | occupied by register REG. */ | |
168 | extern int i386_register_raw_size (int reg); | |
169 | ||
170 | /* Initialize a basic ELF architecture variant. */ | |
171 | extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *); | |
172 | ||
173 | /* Initialize a SVR4 architecture variant. */ | |
174 | extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *); | |
175 | ||
176 | /* Functions exported from i386bsd-tdep.c. */ | |
177 | ||
178 | extern CORE_ADDR i386bsd_sigtramp_saved_pc (struct frame_info *frame); | |
3ce1502b | 179 | |
96297dab | 180 | #endif /* i386-tdep.h */ |