[deliverable/binutils-gdb.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright (C) 2001-2014 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;
struct regcache;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, gdbarch_fp0_regnum
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* Floating-point registers.  */
  size_t sizeof_fpregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Number of MMX registers.  */
  int num_mmx_regs;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of pseudo YMM registers.  */
  int num_ymm_regs;

  /* Register number for %ymm0.  Set this to -1 to indicate the absence
     of pseudo YMM register support.  */
  int ymm0_regnum;

  /* Number of AVX512 OpMask registers (K-registers)  */
  int num_k_regs;

  /* Register number for %k0.  Set this to -1 to indicate the absence
     of AVX512 OpMask register support.  */
  int k0_regnum;

  /* Number of pseudo ZMM registers ($zmm0-$zmm31).  */
  int num_zmm_regs;

  /* Register number for %zmm0.  Set this to -1 to indicate the absence
     of pseudo ZMM register support.  */
  int zmm0_regnum;

  /* Number of byte registers.  */
  int num_byte_regs;

  /* Register pseudo number for %al.  */
  int al_regnum;

  /* Number of pseudo word registers.  */
  int num_word_regs;

  /* Register number for %ax.  */
  int ax_regnum;

  /* Number of pseudo dword registers.  */
  int num_dword_regs;

  /* Register number for %eax.  Set this to -1 to indicate the absence
     of pseudo dword register support.  */
  int eax_regnum;

  /* Number of core registers.  */
  int num_core_regs;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Number of SSE registers added in AVX512.  */
  int num_xmm_avx512_regs;

  /* Register number of XMM16, the first XMM register added in AVX512.  */
  int xmm16_regnum;

  /* Number of YMM registers added in AVX512.  */
  int num_ymm_avx512_regs;

  /* Register number of YMM16, the first YMM register added in AVX512.  */
  int ymm16_regnum;

  /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
     register), excluding the x87 bit, which are supported by this GDB.  */

  uint64_t xcr0;

  /* Offset of XCR0 in XSAVE extended state.  */
  int xsave_xcr0_offset;

  /* Register names.  */
  const char **register_names;

  /* Register number for %ymm0h.  Set this to -1 to indicate the absence
     of upper YMM register support.  */
  int ymm0h_regnum;

  /* Upper YMM register names.  Only used for tdesc_numbered_register.  */
  const char **ymmh_register_names;

  /* Register number for %ymm16h.  Set this to -1 to indicate the absence
  of support for YMM16-31.  */
  int ymm16h_regnum;

  /* YMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char **ymm16h_register_names;

  /* Register number for %bnd0r.  Set this to -1 to indicate the absence
     bound registers.  */
  int bnd0r_regnum;

  /* Register number for pseudo register %bnd0.  Set this to -1 to indicate the absence
     bound registers.  */
  int bnd0_regnum;

  /* Register number for %bndcfgu. Set this to -1 to indicate the absence
     bound control registers.  */
  int bndcfgu_regnum;

  /* MPX register names.  Only used for tdesc_numbered_register.  */
  const char **mpx_register_names;

  /* Register number for %zmm0h.  Set this to -1 to indicate the absence
     of ZMM_HI256 register support.  */
  int zmm0h_regnum;

  /* OpMask register names.  */
  const char **k_register_names;

  /* ZMM register names.  Only used for tdesc_numbered_register.  */
  const char **zmmh_register_names;

  /* XMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char **xmm_avx512_register_names;

  /* YMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char **ymm_avx512_register_names;

  /* Target description.  */
  const struct target_desc *tdesc;

  /* Register group function.  */
  const void *register_reggroup_p;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Detect sigtramp.  */
  int (*sigtramp_p) (struct frame_info *);

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;

  /* ISA-specific data types.  */
  struct type *i386_mmx_type;
  struct type *i386_ymm_type;
  struct type *i386_zmm_type;
  struct type *i387_ext_type;
  struct type *i386_bnd_type;

  /* Process record/replay target.  */
  /* The map for registers because the AMD64's registers order
     in GDB is not same as I386 instructions.  */
  const int *record_regmap;
  /* Parse intx80 args.  */
  int (*i386_intx80_record) (struct regcache *regcache);
  /* Parse sysenter args.  */
  int (*i386_sysenter_record) (struct regcache *regcache);
  /* Parse syscall args.  */
  int (*i386_syscall_record) (struct regcache *regcache);
};

/* Floating-point registers.  */

/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (struct gdbarch *, int);
extern int i386_fpc_regnum_p (struct gdbarch *, int);

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_CS_REGNUM,		/* %cs */
  I386_SS_REGNUM,		/* %ss */
  I386_DS_REGNUM,		/* %ds */
  I386_ES_REGNUM,		/* %es */
  I386_FS_REGNUM,		/* %fs */
  I386_GS_REGNUM,		/* %gs */
  I386_ST0_REGNUM,		/* %st(0) */
  I386_MXCSR_REGNUM = 40,	/* %mxcsr */ 
  I386_YMM0H_REGNUM,		/* %ymm0h */
  I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
  I386_BND0R_REGNUM,
  I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
  I386_BNDCFGU_REGNUM,
  I386_BNDSTATUS_REGNUM,
  I386_K0_REGNUM,		/* %k0 */
  I386_K7_REGNUM = I386_K0_REGNUM + 7,
  I386_ZMM0H_REGNUM,		/* %zmm0h */
  I386_ZMM7H_REGNUM = I386_ZMM0H_REGNUM + 7
};

/* Register numbers of RECORD_REGMAP.  */

enum record_i386_regnum
{
  X86_RECORD_REAX_REGNUM,
  X86_RECORD_RECX_REGNUM,
  X86_RECORD_REDX_REGNUM,
  X86_RECORD_REBX_REGNUM,
  X86_RECORD_RESP_REGNUM,
  X86_RECORD_REBP_REGNUM,
  X86_RECORD_RESI_REGNUM,
  X86_RECORD_REDI_REGNUM,
  X86_RECORD_R8_REGNUM,
  X86_RECORD_R9_REGNUM,
  X86_RECORD_R10_REGNUM,
  X86_RECORD_R11_REGNUM,
  X86_RECORD_R12_REGNUM,
  X86_RECORD_R13_REGNUM,
  X86_RECORD_R14_REGNUM,
  X86_RECORD_R15_REGNUM,
  X86_RECORD_REIP_REGNUM,
  X86_RECORD_EFLAGS_REGNUM,
  X86_RECORD_CS_REGNUM,
  X86_RECORD_SS_REGNUM,
  X86_RECORD_DS_REGNUM,
  X86_RECORD_ES_REGNUM,
  X86_RECORD_FS_REGNUM,
  X86_RECORD_GS_REGNUM,
};

#define I386_NUM_GREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_MXCSR_REGNUM + 1)
#define I386_AVX_NUM_REGS	(I386_YMM7H_REGNUM + 1)
#define I386_MPX_NUM_REGS	(I386_BNDSTATUS_REGNUM + 1)
#define I386_AVX512_NUM_REGS	(I386_ZMM7H_REGNUM + 1)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	64

/* Types for i386-specific registers.  */
extern struct type *i387_ext_type (struct gdbarch *gdbarch);

/* Checks of different pseudo-registers.  */
extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_avx512_regnum_p (struct gdbarch * gdbarch, int regnum);
extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_k_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum);

extern const char *i386_pseudo_register_name (struct gdbarch *gdbarch,
					      int regnum);
extern struct type *i386_pseudo_register_type (struct gdbarch *gdbarch,
					       int regnum);

extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
						  struct regcache *regcache,
						  int regnum,
						  struct value *result);

extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
					struct regcache *regcache,
					int regnum, const gdb_byte *buf);

/* Segment selectors.  */
#define I386_SEL_RPL	0x0003  /* Requester's Privilege Level mask.  */
#define I386_SEL_UPL	0x0003	/* User Privilige Level.  */
#define I386_SEL_KPL	0x0000	/* Kernel Privilige Level.  */

/* The length of the longest i386 instruction (according to
   include/asm-i386/kprobes.h in Linux 2.6.  */
#define I386_MAX_INSN_LEN (16)

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
					       CORE_ADDR pc, char *name);
extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
					  CORE_ADDR pc);

/* Return whether the THIS_FRAME corresponds to a sigtramp routine.  */
extern int i386_sigtramp_p (struct frame_info *this_frame);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* General-purpose register set. */
extern const struct regset i386_gregset;

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */
extern const struct regset *
  i386_regset_from_core_section (struct gdbarch *gdbarch,
				 const char *sect_name, size_t sect_size);


extern struct displaced_step_closure *i386_displaced_step_copy_insn
  (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
   struct regcache *regs);
extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
				       struct displaced_step_closure *closure,
				       CORE_ADDR from, CORE_ADDR to,
				       struct regcache *regs);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);

extern int i386_process_record (struct gdbarch *gdbarch,
                                struct regcache *regcache, CORE_ADDR addr);

\f

/* Functions and variables exported from i386bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start_addr;
extern CORE_ADDR i386fbsd_sigtramp_end_addr;
extern CORE_ADDR i386obsd_sigtramp_start_addr;
extern CORE_ADDR i386obsd_sigtramp_end_addr;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386nbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

/* SystemTap related functions.  */

extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
					const char *s);

extern int i386_stap_parse_special_token (struct gdbarch *gdbarch,
					  struct stap_parse_info *p);

#endif /* i386-tdep.h */
Commit	Line	Data
5716833c MK	1	/* Target-dependent code for the i386.
5716833c MK	2
ecd75fc8	3	Copyright (C) 2001-2014 Free Software Foundation, Inc.
9a82579f JS	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9a82579f JS	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9a82579f JS	19
	20	#ifndef I386_TDEP_H
	21	#define I386_TDEP_H
	22
da3331ec	23	struct frame_info;
5716833c MK	24	struct gdbarch;
5716833c MK	25	struct reggroup;
c783cbd6	26	struct regset;
5439edaa	27	struct regcache;
da3331ec	28
96297dab MK	29	/* GDB's i386 target supports both the 32-bit Intel Architecture
	30	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	31	a similar register layout for both.
	32
	33	- General purpose registers
	34	- FPU data registers
	35	- FPU control registers
	36	- SSE data registers
	37	- SSE control register
	38
	39	The general purpose registers for the x86-64 architecture are quite
3e8c568d	40	different from IA-32. Therefore, gdbarch_fp0_regnum
96297dab MK	41	determines the register number at which the FPU data registers
	42	start. The number of FPU data and control registers is the same
	43	for both architectures. The number of SSE registers however,
	44	differs and is determined by the num_xmm_regs member of `struct
	45	gdbarch_tdep'. */
	46
8201327c	47	/* Convention for returning structures. */
3ce1502b	48
8201327c MK	49	enum struct_return
	50	{
	51	pcc_struct_return, /* Return "short" structures in memory. */
	52	reg_struct_return /* Return "short" structures in registers. */
3ce1502b MK	53	};
3ce1502b MK	54
96297dab MK	55	/* i386 architecture specific information. */
	56	struct gdbarch_tdep
	57	{
473f17b0	58	/* General-purpose registers. */
473f17b0 MK	59	int *gregset_reg_offset;
	60	int gregset_num_regs;
	61	size_t sizeof_gregset;
	62
	63	/* Floating-point registers. */
473f17b0 MK	64	size_t sizeof_fpregset;
473f17b0 MK	65
5716833c MK	66	/* Register number for %st(0). The register numbers for the other
	67	registers follow from this one. Set this to -1 to indicate the
	68	absence of an FPU. */
	69	int st0_regnum;
	70
1ba53b71 L	71	/* Number of MMX registers. */
	72	int num_mmx_regs;
	73
5716833c MK	74	/* Register number for %mm0. Set this to -1 to indicate the absence
	75	of MMX support. */
	76	int mm0_regnum;
	77
c131fcee L	78	/* Number of pseudo YMM registers. */
	79	int num_ymm_regs;
	80
	81	/* Register number for %ymm0. Set this to -1 to indicate the absence
	82	of pseudo YMM register support. */
	83	int ymm0_regnum;
	84
01f9f808 MS	85	/* Number of AVX512 OpMask registers (K-registers) */
	86	int num_k_regs;
	87
	88	/* Register number for %k0. Set this to -1 to indicate the absence
	89	of AVX512 OpMask register support. */
	90	int k0_regnum;
	91
	92	/* Number of pseudo ZMM registers ($zmm0-$zmm31). */
	93	int num_zmm_regs;
	94
	95	/* Register number for %zmm0. Set this to -1 to indicate the absence
	96	of pseudo ZMM register support. */
	97	int zmm0_regnum;
	98
1ba53b71 L	99	/* Number of byte registers. */
	100	int num_byte_regs;
	101
	102	/* Register pseudo number for %al. */
	103	int al_regnum;
	104
	105	/* Number of pseudo word registers. */
	106	int num_word_regs;
	107
	108	/* Register number for %ax. */
	109	int ax_regnum;
	110
	111	/* Number of pseudo dword registers. */
	112	int num_dword_regs;
	113
	114	/* Register number for %eax. Set this to -1 to indicate the absence
	115	of pseudo dword register support. */
	116	int eax_regnum;
	117
90884b2b L	118	/* Number of core registers. */
	119	int num_core_regs;
	120
96297dab MK	121	/* Number of SSE registers. */
96297dab MK	122	int num_xmm_regs;
8201327c	123
01f9f808 MS	124	/* Number of SSE registers added in AVX512. */
	125	int num_xmm_avx512_regs;
	126
	127	/* Register number of XMM16, the first XMM register added in AVX512. */
	128	int xmm16_regnum;
	129
	130	/* Number of YMM registers added in AVX512. */
	131	int num_ymm_avx512_regs;
	132
	133	/* Register number of YMM16, the first YMM register added in AVX512. */
	134	int ymm16_regnum;
	135
c131fcee	136	/* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
1777feb0 MS	137	register), excluding the x87 bit, which are supported by this GDB. */
1777feb0 MS	138
c131fcee L	139	uint64_t xcr0;
	140
	141	/* Offset of XCR0 in XSAVE extended state. */
	142	int xsave_xcr0_offset;
	143
90884b2b L	144	/* Register names. */
	145	const char **register_names;
	146
c131fcee L	147	/* Register number for %ymm0h. Set this to -1 to indicate the absence
	148	of upper YMM register support. */
	149	int ymm0h_regnum;
	150
	151	/* Upper YMM register names. Only used for tdesc_numbered_register. */
	152	const char **ymmh_register_names;
	153
01f9f808 MS	154	/* Register number for %ymm16h. Set this to -1 to indicate the absence
	155	of support for YMM16-31. */
	156	int ymm16h_regnum;
	157
	158	/* YMM16-31 register names. Only used for tdesc_numbered_register. */
	159	const char **ymm16h_register_names;
	160
1dbcd68c WT	161	/* Register number for %bnd0r. Set this to -1 to indicate the absence
	162	bound registers. */
	163	int bnd0r_regnum;
	164
	165	/* Register number for pseudo register %bnd0. Set this to -1 to indicate the absence
	166	bound registers. */
	167	int bnd0_regnum;
	168
	169	/* Register number for %bndcfgu. Set this to -1 to indicate the absence
	170	bound control registers. */
	171	int bndcfgu_regnum;
	172
	173	/* MPX register names. Only used for tdesc_numbered_register. */
	174	const char **mpx_register_names;
	175
01f9f808 MS	176	/* Register number for %zmm0h. Set this to -1 to indicate the absence
	177	of ZMM_HI256 register support. */
	178	int zmm0h_regnum;
	179
	180	/* OpMask register names. */
	181	const char **k_register_names;
	182
	183	/* ZMM register names. Only used for tdesc_numbered_register. */
	184	const char **zmmh_register_names;
	185
	186	/* XMM16-31 register names. Only used for tdesc_numbered_register. */
	187	const char **xmm_avx512_register_names;
	188
	189	/* YMM16-31 register names. Only used for tdesc_numbered_register. */
	190	const char **ymm_avx512_register_names;
	191
90884b2b L	192	/* Target description. */
	193	const struct target_desc *tdesc;
	194
	195	/* Register group function. */
	196	const void *register_reggroup_p;
	197
8201327c MK	198	/* Offset of saved PC in jmp_buf. */
	199	int jb_pc_offset;
	200
	201	/* Convention for returning structures. */
	202	enum struct_return struct_return;
	203
8201327c MK	204	/* Address range where sigtramp lives. */
	205	CORE_ADDR sigtramp_start;
	206	CORE_ADDR sigtramp_end;
	207
911bc6ee MK	208	/* Detect sigtramp. */
	209	int (sigtramp_p) (struct frame_info );
	210
21d0e8a4 MK	211	/* Get address of sigcontext for sigtramp. */
	212	CORE_ADDR (sigcontext_addr) (struct frame_info );
	213
a3386186 MK	214	/* Offset of registers in `struct sigcontext'. */
	215	int *sc_reg_offset;
	216	int sc_num_regs;
	217
	218	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	219	is deprecated, please use `sc_reg_offset' instead. */
8201327c	220	int sc_pc_offset;
21d0e8a4	221	int sc_sp_offset;
794ac428 UW	222
	223	/* ISA-specific data types. */
	224	struct type *i386_mmx_type;
c131fcee	225	struct type *i386_ymm_type;
01f9f808	226	struct type *i386_zmm_type;
27067745	227	struct type *i387_ext_type;
1dbcd68c	228	struct type *i386_bnd_type;
7ad10968 HZ	229
7ad10968 HZ	230	/* Process record/replay target. */
cf648174 HZ	231	/* The map for registers because the AMD64's registers order
	232	in GDB is not same as I386 instructions. */
	233	const int *record_regmap;
7ad10968 HZ	234	/* Parse intx80 args. */
	235	int (i386_intx80_record) (struct regcache regcache);
	236	/* Parse sysenter args. */
	237	int (i386_sysenter_record) (struct regcache regcache);
cf648174 HZ	238	/* Parse syscall args. */
cf648174 HZ	239	int (i386_syscall_record) (struct regcache regcache);
96297dab MK	240	};
	241
	242	/* Floating-point registers. */
	243
96297dab MK	244	/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
	245	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	246	register cache. */
	247
23a34459 AC	248	/* Return non-zero if REGNUM matches the FP register and the FP
23a34459 AC	249	register set is active. */
20a6ec49 MD	250	extern int i386_fp_regnum_p (struct gdbarch *, int);
20a6ec49 MD	251	extern int i386_fpc_regnum_p (struct gdbarch *, int);
96297dab	252
a3386186 MK	253	/* Register numbers of various important registers. */
a3386186 MK	254
bcf48cc7 MK	255	enum i386_regnum
	256	{
	257	I386_EAX_REGNUM, /* %eax */
	258	I386_ECX_REGNUM, /* %ecx */
	259	I386_EDX_REGNUM, /* %edx */
	260	I386_EBX_REGNUM, /* %ebx */
	261	I386_ESP_REGNUM, /* %esp */
	262	I386_EBP_REGNUM, /* %ebp */
	263	I386_ESI_REGNUM, /* %esi */
	264	I386_EDI_REGNUM, /* %edi */
	265	I386_EIP_REGNUM, /* %eip */
	266	I386_EFLAGS_REGNUM, /* %eflags */
2666fb59 MK	267	I386_CS_REGNUM, /* %cs */
2666fb59 MK	268	I386_SS_REGNUM, /* %ss */
e9ff708b AC	269	I386_DS_REGNUM, /* %ds */
	270	I386_ES_REGNUM, /* %es */
	271	I386_FS_REGNUM, /* %fs */
	272	I386_GS_REGNUM, /* %gs */
90884b2b	273	I386_ST0_REGNUM, /* %st(0) */
c131fcee L	274	I386_MXCSR_REGNUM = 40, /* %mxcsr */
c131fcee L	275	I386_YMM0H_REGNUM, /* %ymm0h */
1dbcd68c WT	276	I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
	277	I386_BND0R_REGNUM,
	278	I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
	279	I386_BNDCFGU_REGNUM,
01f9f808 MS	280	I386_BNDSTATUS_REGNUM,
	281	I386_K0_REGNUM, /* %k0 */
	282	I386_K7_REGNUM = I386_K0_REGNUM + 7,
	283	I386_ZMM0H_REGNUM, /* %zmm0h */
	284	I386_ZMM7H_REGNUM = I386_ZMM0H_REGNUM + 7
bcf48cc7	285	};
a3386186	286
cf648174 HZ	287	/* Register numbers of RECORD_REGMAP. */
	288
	289	enum record_i386_regnum
	290	{
	291	X86_RECORD_REAX_REGNUM,
	292	X86_RECORD_RECX_REGNUM,
	293	X86_RECORD_REDX_REGNUM,
	294	X86_RECORD_REBX_REGNUM,
	295	X86_RECORD_RESP_REGNUM,
	296	X86_RECORD_REBP_REGNUM,
	297	X86_RECORD_RESI_REGNUM,
	298	X86_RECORD_REDI_REGNUM,
	299	X86_RECORD_R8_REGNUM,
	300	X86_RECORD_R9_REGNUM,
	301	X86_RECORD_R10_REGNUM,
	302	X86_RECORD_R11_REGNUM,
	303	X86_RECORD_R12_REGNUM,
	304	X86_RECORD_R13_REGNUM,
	305	X86_RECORD_R14_REGNUM,
	306	X86_RECORD_R15_REGNUM,
	307	X86_RECORD_REIP_REGNUM,
	308	X86_RECORD_EFLAGS_REGNUM,
	309	X86_RECORD_CS_REGNUM,
	310	X86_RECORD_SS_REGNUM,
	311	X86_RECORD_DS_REGNUM,
	312	X86_RECORD_ES_REGNUM,
	313	X86_RECORD_FS_REGNUM,
	314	X86_RECORD_GS_REGNUM,
	315	};
	316
8201327c	317	#define I386_NUM_GREGS 16
8201327c MK	318	#define I386_NUM_XREGS 9
8201327c MK	319
90884b2b	320	#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
c131fcee	321	#define I386_AVX_NUM_REGS (I386_YMM7H_REGNUM + 1)
1dbcd68c	322	#define I386_MPX_NUM_REGS (I386_BNDSTATUS_REGNUM + 1)
01f9f808	323	#define I386_AVX512_NUM_REGS (I386_ZMM7H_REGNUM + 1)
8201327c	324
00f8375e	325	/* Size of the largest register. */
01f9f808	326	#define I386_MAX_REGISTER_SIZE 64
00f8375e	327
5ae96ec1	328	/* Types for i386-specific registers. */
27067745	329	extern struct type i387_ext_type (struct gdbarch gdbarch);
794ac428	330
1ba53b71 L	331	/* Checks of different pseudo-registers. */
	332	extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
	333	extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
	334	extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee	335	extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808	336	extern int i386_xmm_avx512_regnum_p (struct gdbarch * gdbarch, int regnum);
c131fcee	337	extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808	338	extern int i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum);
1dbcd68c	339	extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808 MS	340	extern int i386_k_regnum_p (struct gdbarch *gdbarch, int regnum);
	341	extern int i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum);
	342	extern int i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum);
1ba53b71 L	343
	344	extern const char i386_pseudo_register_name (struct gdbarch gdbarch,
	345	int regnum);
fff4548b MK	346	extern struct type i386_pseudo_register_type (struct gdbarch gdbarch,
fff4548b MK	347	int regnum);
1ba53b71	348
3543a589 TT	349	extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
	350	struct regcache *regcache,
	351	int regnum,
	352	struct value *result);
	353
1ba53b71 L	354	extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
	355	struct regcache *regcache,
	356	int regnum, const gdb_byte *buf);
	357
508fbfea MK	358	/* Segment selectors. */
508fbfea MK	359	#define I386_SEL_RPL 0x0003 /* Requester's Privilege Level mask. */
1777feb0 MS	360	#define I386_SEL_UPL 0x0003 /* User Privilige Level. */
1777feb0 MS	361	#define I386_SEL_KPL 0x0000 /* Kernel Privilige Level. */
508fbfea	362
237fc4c9 PA	363	/* The length of the longest i386 instruction (according to
	364	include/asm-i386/kprobes.h in Linux 2.6. */
	365	#define I386_MAX_INSN_LEN (16)
	366
1cce71eb	367	/* Functions exported from i386-tdep.c. */
e17a4113 UW	368	extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
e17a4113 UW	369	CORE_ADDR pc, char *name);
1777feb0 MS	370	extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
1777feb0 MS	371	CORE_ADDR pc);
1cce71eb	372
4bd207ef TG	373	/* Return whether the THIS_FRAME corresponds to a sigtramp routine. */
	374	extern int i386_sigtramp_p (struct frame_info *this_frame);
	375
38c968cf AC	376	/* Return non-zero if REGNUM is a member of the specified group. */
	377	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	378	struct reggroup *group);
	379
20187ed5 MK	380	/* Supply register REGNUM from the general-purpose register set REGSET
	381	to register cache REGCACHE. If REGNUM is -1, do this for all
	382	registers in REGSET. */
	383	extern void i386_supply_gregset (const struct regset *regset,
	384	struct regcache *regcache, int regnum,
	385	const void *gregs, size_t len);
3d171c85	386
ecc37a5a AA	387	/* General-purpose register set. */
ecc37a5a AA	388	extern const struct regset i386_gregset;
20187ed5	389
8446b36a MK	390	/* Return the appropriate register set for the core section identified
	391	by SECT_NAME and SECT_SIZE. */
	392	extern const struct regset *
	393	i386_regset_from_core_section (struct gdbarch *gdbarch,
	394	const char *sect_name, size_t sect_size);
	395
237fc4c9	396
b55078be DE	397	extern struct displaced_step_closure *i386_displaced_step_copy_insn
	398	(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
	399	struct regcache *regs);
237fc4c9 PA	400	extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
	401	struct displaced_step_closure *closure,
	402	CORE_ADDR from, CORE_ADDR to,
	403	struct regcache *regs);
	404
8201327c MK	405	/* Initialize a basic ELF architecture variant. */
	406	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	407
	408	/* Initialize a SVR4 architecture variant. */
	409	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
a6b808b4 HZ	410
	411	extern int i386_process_record (struct gdbarch *gdbarch,
	412	struct regcache *regcache, CORE_ADDR addr);
55aa24fb	413
de0b6abb	414	\f
8201327c	415
de0b6abb	416	/* Functions and variables exported from i386bsd-tdep.c. */
8201327c	417
3cac699e	418	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
5d93ae8c MK	419	extern CORE_ADDR i386fbsd_sigtramp_start_addr;
	420	extern CORE_ADDR i386fbsd_sigtramp_end_addr;
	421	extern CORE_ADDR i386obsd_sigtramp_start_addr;
	422	extern CORE_ADDR i386obsd_sigtramp_end_addr;
de0b6abb MK	423	extern int i386fbsd4_sc_reg_offset[];
	424	extern int i386fbsd_sc_reg_offset[];
	425	extern int i386nbsd_sc_reg_offset[];
	426	extern int i386obsd_sc_reg_offset[];
	427	extern int i386bsd_sc_reg_offset[];
3ce1502b	428
55aa24fb SDJ	429	/* SystemTap related functions. */
	430
	431	extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
	432	const char *s);
	433
	434	extern int i386_stap_parse_special_token (struct gdbarch *gdbarch,
	435	struct stap_parse_info *p);
	436
96297dab	437	#endif /* i386-tdep.h */