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9a82579f JS |
1 | /* Target-dependent code for GDB, the GNU debugger. |
2 | Copyright 2001 | |
3 | Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef I386_TDEP_H | |
23 | #define I386_TDEP_H | |
24 | ||
25 | #define FPU_REG_RAW_SIZE 10 | |
26 | ||
a62cc96e | 27 | #if !defined (XMM0_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 28 | #define XMM0_REGNUM FIRST_XMM_REGNUM |
a62cc96e AC |
29 | #endif |
30 | #if !defined (FIRST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 31 | #define FIRST_FPU_REGNUM FP0_REGNUM |
a62cc96e AC |
32 | #endif |
33 | #if !defined (LAST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 34 | #define LAST_FPU_REGNUM (gdbarch_tdep (current_gdbarch)->last_fpu_regnum) |
a62cc96e AC |
35 | #endif |
36 | #if !defined (FIRST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 37 | #define FIRST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->first_xmm_regnum) |
a62cc96e AC |
38 | #endif |
39 | #if !defined (LAST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 40 | #define LAST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->last_xmm_regnum) |
a62cc96e AC |
41 | #endif |
42 | #if !defined (MXCSR_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 43 | #define MXCSR_REGNUM (gdbarch_tdep (current_gdbarch)->mxcsr_regnum) |
a62cc96e AC |
44 | #endif |
45 | #if !defined (FIRST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 46 | #define FIRST_FPU_CTRL_REGNUM (gdbarch_tdep (current_gdbarch)->first_fpu_ctrl_regnum) |
a62cc96e AC |
47 | #endif |
48 | #if !defined (LAST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 49 | #define LAST_FPU_CTRL_REGNUM (FIRST_FPU_CTRL_REGNUM + 7) |
a62cc96e | 50 | #endif |
9a82579f JS |
51 | |
52 | /* All of these control registers (except for FCOFF and FDOFF) are | |
53 | sixteen bits long (at most) in the FPU, but are zero-extended to | |
54 | thirty-two bits in GDB's register file. This makes it easier to | |
55 | compute the size of the control register file, and somewhat easier | |
56 | to convert to and from the FSAVE instruction's 32-bit format. */ | |
57 | /* FPU control word. */ | |
a62cc96e | 58 | #if !defined (FCTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 59 | #define FCTRL_REGNUM (FIRST_FPU_CTRL_REGNUM) |
a62cc96e | 60 | #endif |
9a82579f | 61 | /* FPU status word. */ |
a62cc96e | 62 | #if !defined (FSTAT_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 63 | #define FSTAT_REGNUM (FIRST_FPU_CTRL_REGNUM + 1) |
a62cc96e | 64 | #endif |
9a82579f | 65 | /* FPU register tag word. */ |
a62cc96e | 66 | #if !defined (FTAG_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 67 | #define FTAG_REGNUM (FIRST_FPU_CTRL_REGNUM + 2) |
a62cc96e | 68 | #endif |
9a82579f JS |
69 | /* FPU instruction's code segment selector 16 bits, called "FPU Instruction |
70 | Pointer Selector" in the x86 manuals. */ | |
a62cc96e | 71 | #if !defined (FCS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 72 | #define FCS_REGNUM (FIRST_FPU_CTRL_REGNUM + 3) |
a62cc96e | 73 | #endif |
9a82579f | 74 | /* FPU instruction's offset within segment ("Fpu Code OFFset"). */ |
a62cc96e | 75 | #if !defined (FCOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 76 | #define FCOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 4) |
a62cc96e | 77 | #endif |
9a82579f | 78 | /* FPU operand's data segment. */ |
a62cc96e | 79 | #if !defined (FDS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 80 | #define FDS_REGNUM (FIRST_FPU_CTRL_REGNUM + 5) |
a62cc96e | 81 | #endif |
9a82579f | 82 | /* FPU operand's offset within segment. */ |
a62cc96e | 83 | #if !defined (FDOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 84 | #define FDOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 6) |
a62cc96e | 85 | #endif |
9a82579f | 86 | /* FPU opcode, bottom eleven bits. */ |
a62cc96e | 87 | #if !defined (FOP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 88 | #define FOP_REGNUM (FIRST_FPU_CTRL_REGNUM + 7) |
a62cc96e | 89 | #endif |
9a82579f JS |
90 | |
91 | /* i386 architecture specific information. */ | |
92 | struct gdbarch_tdep | |
93 | { | |
94 | int last_fpu_regnum; | |
95 | int first_xmm_regnum; | |
96 | int last_xmm_regnum; | |
97 | int mxcsr_regnum; /* Streaming SIMD Extension control/status. */ | |
98 | int first_fpu_ctrl_regnum; | |
99 | }; | |
100 | ||
a62cc96e | 101 | #if !defined (IS_FP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) |
9a82579f | 102 | #define IS_FP_REGNUM(n) (FIRST_FPU_REGNUM <= (n) && (n) <= LAST_FPU_REGNUM) |
a62cc96e AC |
103 | #endif |
104 | #if !defined (IS_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 105 | #define IS_FPU_CTRL_REGNUM(n) (FIRST_FPU_CTRL_REGNUM <= (n) && (n) <= LAST_FPU_CTRL_REGNUM) |
a62cc96e AC |
106 | #endif |
107 | #if !defined (IS_SSE_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
9a82579f | 108 | #define IS_SSE_REGNUM(n) (FIRST_XMM_REGNUM <= (n) && (n) <= LAST_XMM_REGNUM) |
a62cc96e | 109 | #endif |
9a82579f JS |
110 | |
111 | #endif |