Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 387 floating point stuff. |
38edeab8 | 2 | |
61baf725 | 3 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
786a90bb | 21 | #include "doublest.h" |
c906108c | 22 | #include "frame.h" |
786a90bb | 23 | #include "gdbcore.h" |
c906108c SS |
24 | #include "inferior.h" |
25 | #include "language.h" | |
4e052eda | 26 | #include "regcache.h" |
786a90bb MK |
27 | #include "value.h" |
28 | ||
9a82579f | 29 | #include "i386-tdep.h" |
42c466d7 | 30 | #include "i387-tdep.h" |
df7e5265 | 31 | #include "x86-xstate.h" |
c906108c | 32 | |
de57eccd | 33 | /* Print the floating point number specified by RAW. */ |
786a90bb | 34 | |
de57eccd | 35 | static void |
27067745 UW |
36 | print_i387_value (struct gdbarch *gdbarch, |
37 | const gdb_byte *raw, struct ui_file *file) | |
de57eccd | 38 | { |
de57eccd JM |
39 | /* We try to print 19 digits. The last digit may or may not contain |
40 | garbage, but we'd better print one too many. We need enough room | |
41 | to print the value, 1 position for the sign, 1 for the decimal | |
42 | point, 19 for the digits and 6 for the exponent adds up to 27. */ | |
8ba0dd51 UW |
43 | const struct floatformat *fmt |
44 | = floatformat_from_type (i387_ext_type (gdbarch)); | |
45 | std::string str = floatformat_to_string (fmt, raw, " %-+27.19g"); | |
46 | fprintf_filtered (file, "%s", str.c_str ()); | |
de57eccd JM |
47 | } |
48 | ||
49 | /* Print the classification for the register contents RAW. */ | |
786a90bb | 50 | |
de57eccd | 51 | static void |
27067745 UW |
52 | print_i387_ext (struct gdbarch *gdbarch, |
53 | const gdb_byte *raw, struct ui_file *file) | |
de57eccd JM |
54 | { |
55 | int sign; | |
56 | int integer; | |
57 | unsigned int exponent; | |
58 | unsigned long fraction[2]; | |
59 | ||
60 | sign = raw[9] & 0x80; | |
61 | integer = raw[7] & 0x80; | |
62 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); | |
63 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); | |
64 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) | |
65 | | (raw[5] << 8) | raw[4]); | |
66 | ||
67 | if (exponent == 0x7fff && integer) | |
68 | { | |
69 | if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000) | |
70 | /* Infinity. */ | |
61113f8b | 71 | fprintf_filtered (file, " %cInf", (sign ? '-' : '+')); |
de57eccd JM |
72 | else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000) |
73 | /* Real Indefinite (QNaN). */ | |
61113f8b | 74 | fputs_unfiltered (" Real Indefinite (QNaN)", file); |
de57eccd JM |
75 | else if (fraction[1] & 0x40000000) |
76 | /* QNaN. */ | |
61113f8b | 77 | fputs_filtered (" QNaN", file); |
de57eccd JM |
78 | else |
79 | /* SNaN. */ | |
61113f8b | 80 | fputs_filtered (" SNaN", file); |
de57eccd JM |
81 | } |
82 | else if (exponent < 0x7fff && exponent > 0x0000 && integer) | |
83 | /* Normal. */ | |
27067745 | 84 | print_i387_value (gdbarch, raw, file); |
de57eccd JM |
85 | else if (exponent == 0x0000) |
86 | { | |
87 | /* Denormal or zero. */ | |
27067745 | 88 | print_i387_value (gdbarch, raw, file); |
de57eccd JM |
89 | |
90 | if (integer) | |
91 | /* Pseudo-denormal. */ | |
61113f8b | 92 | fputs_filtered (" Pseudo-denormal", file); |
de57eccd JM |
93 | else if (fraction[0] || fraction[1]) |
94 | /* Denormal. */ | |
61113f8b | 95 | fputs_filtered (" Denormal", file); |
de57eccd JM |
96 | } |
97 | else | |
98 | /* Unsupported. */ | |
61113f8b | 99 | fputs_filtered (" Unsupported", file); |
de57eccd JM |
100 | } |
101 | ||
ad5f7d6e PA |
102 | /* Print the status word STATUS. If STATUS_P is false, then STATUS |
103 | was unavailable. */ | |
786a90bb | 104 | |
de57eccd | 105 | static void |
ad5f7d6e PA |
106 | print_i387_status_word (int status_p, |
107 | unsigned int status, struct ui_file *file) | |
de57eccd | 108 | { |
ad5f7d6e PA |
109 | fprintf_filtered (file, "Status Word: "); |
110 | if (!status_p) | |
111 | { | |
112 | fprintf_filtered (file, "%s\n", _("<unavailable>")); | |
113 | return; | |
114 | } | |
115 | ||
116 | fprintf_filtered (file, "%s", hex_string_custom (status, 4)); | |
61113f8b MK |
117 | fputs_filtered (" ", file); |
118 | fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " "); | |
119 | fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " "); | |
120 | fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " "); | |
121 | fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " "); | |
122 | fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " "); | |
123 | fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " "); | |
124 | fputs_filtered (" ", file); | |
125 | fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " "); | |
126 | fputs_filtered (" ", file); | |
127 | fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " "); | |
128 | fputs_filtered (" ", file); | |
129 | fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " "); | |
130 | fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " "); | |
131 | fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " "); | |
132 | fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " "); | |
133 | ||
134 | fputs_filtered ("\n", file); | |
135 | ||
136 | fprintf_filtered (file, | |
137 | " TOP: %d\n", ((status >> 11) & 7)); | |
de57eccd JM |
138 | } |
139 | ||
ad5f7d6e PA |
140 | /* Print the control word CONTROL. If CONTROL_P is false, then |
141 | CONTROL was unavailable. */ | |
786a90bb | 142 | |
de57eccd | 143 | static void |
ad5f7d6e PA |
144 | print_i387_control_word (int control_p, |
145 | unsigned int control, struct ui_file *file) | |
de57eccd | 146 | { |
ad5f7d6e PA |
147 | fprintf_filtered (file, "Control Word: "); |
148 | if (!control_p) | |
149 | { | |
150 | fprintf_filtered (file, "%s\n", _("<unavailable>")); | |
151 | return; | |
152 | } | |
153 | ||
154 | fprintf_filtered (file, "%s", hex_string_custom (control, 4)); | |
61113f8b MK |
155 | fputs_filtered (" ", file); |
156 | fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " "); | |
157 | fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " "); | |
158 | fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " "); | |
159 | fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " "); | |
160 | fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " "); | |
161 | fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " "); | |
de57eccd | 162 | |
61113f8b | 163 | fputs_filtered ("\n", file); |
de57eccd | 164 | |
61113f8b | 165 | fputs_filtered (" PC: ", file); |
de57eccd JM |
166 | switch ((control >> 8) & 3) |
167 | { | |
168 | case 0: | |
61113f8b | 169 | fputs_filtered ("Single Precision (24-bits)\n", file); |
de57eccd JM |
170 | break; |
171 | case 1: | |
61113f8b | 172 | fputs_filtered ("Reserved\n", file); |
de57eccd JM |
173 | break; |
174 | case 2: | |
61113f8b | 175 | fputs_filtered ("Double Precision (53-bits)\n", file); |
de57eccd JM |
176 | break; |
177 | case 3: | |
61113f8b | 178 | fputs_filtered ("Extended Precision (64-bits)\n", file); |
de57eccd JM |
179 | break; |
180 | } | |
181 | ||
61113f8b | 182 | fputs_filtered (" RC: ", file); |
de57eccd JM |
183 | switch ((control >> 10) & 3) |
184 | { | |
185 | case 0: | |
61113f8b | 186 | fputs_filtered ("Round to nearest\n", file); |
de57eccd JM |
187 | break; |
188 | case 1: | |
61113f8b | 189 | fputs_filtered ("Round down\n", file); |
de57eccd JM |
190 | break; |
191 | case 2: | |
61113f8b | 192 | fputs_filtered ("Round up\n", file); |
de57eccd JM |
193 | break; |
194 | case 3: | |
61113f8b | 195 | fputs_filtered ("Round toward zero\n", file); |
de57eccd JM |
196 | break; |
197 | } | |
198 | } | |
199 | ||
9b949a49 | 200 | /* Print out the i387 floating point state. Note that we ignore FRAME |
7d8d2918 MK |
201 | in the code below. That's OK since floating-point registers are |
202 | never saved on the stack. */ | |
203 | ||
de57eccd | 204 | void |
61113f8b | 205 | i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
8e186fd6 | 206 | struct frame_info *frame, const char *args) |
de57eccd | 207 | { |
5716833c | 208 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
1d70089a | 209 | ULONGEST fctrl; |
ad5f7d6e | 210 | int fctrl_p; |
1d70089a | 211 | ULONGEST fstat; |
ad5f7d6e | 212 | int fstat_p; |
1d70089a | 213 | ULONGEST ftag; |
ad5f7d6e | 214 | int ftag_p; |
1d70089a | 215 | ULONGEST fiseg; |
ad5f7d6e | 216 | int fiseg_p; |
1d70089a | 217 | ULONGEST fioff; |
ad5f7d6e | 218 | int fioff_p; |
1d70089a | 219 | ULONGEST foseg; |
ad5f7d6e | 220 | int foseg_p; |
1d70089a | 221 | ULONGEST fooff; |
ad5f7d6e | 222 | int fooff_p; |
1d70089a | 223 | ULONGEST fop; |
ad5f7d6e | 224 | int fop_p; |
de57eccd JM |
225 | int fpreg; |
226 | int top; | |
227 | ||
5716833c MK |
228 | gdb_assert (gdbarch == get_frame_arch (frame)); |
229 | ||
ad5f7d6e PA |
230 | fctrl_p = read_frame_register_unsigned (frame, |
231 | I387_FCTRL_REGNUM (tdep), &fctrl); | |
232 | fstat_p = read_frame_register_unsigned (frame, | |
233 | I387_FSTAT_REGNUM (tdep), &fstat); | |
234 | ftag_p = read_frame_register_unsigned (frame, | |
235 | I387_FTAG_REGNUM (tdep), &ftag); | |
236 | fiseg_p = read_frame_register_unsigned (frame, | |
237 | I387_FISEG_REGNUM (tdep), &fiseg); | |
238 | fioff_p = read_frame_register_unsigned (frame, | |
239 | I387_FIOFF_REGNUM (tdep), &fioff); | |
240 | foseg_p = read_frame_register_unsigned (frame, | |
241 | I387_FOSEG_REGNUM (tdep), &foseg); | |
242 | fooff_p = read_frame_register_unsigned (frame, | |
243 | I387_FOOFF_REGNUM (tdep), &fooff); | |
244 | fop_p = read_frame_register_unsigned (frame, | |
245 | I387_FOP_REGNUM (tdep), &fop); | |
246 | ||
247 | if (fstat_p) | |
de57eccd | 248 | { |
ad5f7d6e | 249 | top = ((fstat >> 11) & 7); |
de57eccd | 250 | |
ad5f7d6e | 251 | for (fpreg = 7; fpreg >= 0; fpreg--) |
de57eccd | 252 | { |
ad5f7d6e PA |
253 | struct value *regval; |
254 | int regnum; | |
255 | int i; | |
256 | int tag = -1; | |
257 | ||
258 | fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); | |
259 | ||
260 | if (ftag_p) | |
261 | { | |
262 | tag = (ftag >> (fpreg * 2)) & 3; | |
263 | ||
264 | switch (tag) | |
265 | { | |
266 | case 0: | |
267 | fputs_filtered ("Valid ", file); | |
268 | break; | |
269 | case 1: | |
270 | fputs_filtered ("Zero ", file); | |
271 | break; | |
272 | case 2: | |
273 | fputs_filtered ("Special ", file); | |
274 | break; | |
275 | case 3: | |
276 | fputs_filtered ("Empty ", file); | |
277 | break; | |
278 | } | |
279 | } | |
280 | else | |
281 | fputs_filtered ("Unknown ", file); | |
282 | ||
283 | regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep); | |
284 | regval = get_frame_register_value (frame, regnum); | |
285 | ||
286 | if (value_entirely_available (regval)) | |
287 | { | |
433730c9 | 288 | const gdb_byte *raw = value_contents (regval); |
ad5f7d6e PA |
289 | |
290 | fputs_filtered ("0x", file); | |
291 | for (i = 9; i >= 0; i--) | |
292 | fprintf_filtered (file, "%02x", raw[i]); | |
293 | ||
294 | if (tag != -1 && tag != 3) | |
295 | print_i387_ext (gdbarch, raw, file); | |
296 | } | |
297 | else | |
298 | fprintf_filtered (file, "%s", _("<unavailable>")); | |
299 | ||
300 | fputs_filtered ("\n", file); | |
de57eccd | 301 | } |
de57eccd JM |
302 | } |
303 | ||
f16a25ae | 304 | fputs_filtered ("\n", file); |
ad5f7d6e PA |
305 | print_i387_status_word (fstat_p, fstat, file); |
306 | print_i387_control_word (fctrl_p, fctrl, file); | |
61113f8b | 307 | fprintf_filtered (file, "Tag Word: %s\n", |
ad5f7d6e | 308 | ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>")); |
61113f8b | 309 | fprintf_filtered (file, "Instruction Pointer: %s:", |
ad5f7d6e PA |
310 | fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>")); |
311 | fprintf_filtered (file, "%s\n", | |
312 | fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>")); | |
61113f8b | 313 | fprintf_filtered (file, "Operand Pointer: %s:", |
ad5f7d6e PA |
314 | foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>")); |
315 | fprintf_filtered (file, "%s\n", | |
316 | fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>")); | |
61113f8b | 317 | fprintf_filtered (file, "Opcode: %s\n", |
ad5f7d6e PA |
318 | fop_p |
319 | ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4)) | |
320 | : _("<unavailable>")); | |
de57eccd | 321 | } |
d532c08f MK |
322 | \f |
323 | ||
83acabca DJ |
324 | /* Return nonzero if a value of type TYPE stored in register REGNUM |
325 | needs any special handling. */ | |
326 | ||
327 | int | |
1777feb0 MS |
328 | i387_convert_register_p (struct gdbarch *gdbarch, int regnum, |
329 | struct type *type) | |
83acabca | 330 | { |
20a6ec49 | 331 | if (i386_fp_regnum_p (gdbarch, regnum)) |
83acabca DJ |
332 | { |
333 | /* Floating point registers must be converted unless we are | |
8c8f9122 YQ |
334 | accessing them in their hardware type or TYPE is not float. */ |
335 | if (type == i387_ext_type (gdbarch) | |
336 | || TYPE_CODE (type) != TYPE_CODE_FLT) | |
83acabca DJ |
337 | return 0; |
338 | else | |
339 | return 1; | |
340 | } | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
d532c08f MK |
345 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
346 | return its contents in TO. */ | |
347 | ||
8dccd430 | 348 | int |
d532c08f | 349 | i387_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
350 | struct type *type, gdb_byte *to, |
351 | int *optimizedp, int *unavailablep) | |
d532c08f | 352 | { |
27067745 | 353 | struct gdbarch *gdbarch = get_frame_arch (frame); |
b4ad899f | 354 | gdb_byte from[I386_MAX_REGISTER_SIZE]; |
d532c08f | 355 | |
27067745 | 356 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
d532c08f MK |
357 | |
358 | /* We only support floating-point values. */ | |
359 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
360 | { | |
8a3fe4f8 AC |
361 | warning (_("Cannot convert floating-point register value " |
362 | "to non-floating-point type.")); | |
8dccd430 PA |
363 | *optimizedp = *unavailablep = 0; |
364 | return 0; | |
d532c08f MK |
365 | } |
366 | ||
83acabca | 367 | /* Convert to TYPE. */ |
d8e07dda YQ |
368 | if (!get_frame_register_bytes (frame, regnum, 0, |
369 | register_size (gdbarch, regnum), | |
8dccd430 PA |
370 | from, optimizedp, unavailablep)) |
371 | return 0; | |
372 | ||
27067745 | 373 | convert_typed_floating (from, i387_ext_type (gdbarch), to, type); |
8dccd430 PA |
374 | *optimizedp = *unavailablep = 0; |
375 | return 1; | |
d532c08f MK |
376 | } |
377 | ||
378 | /* Write the contents FROM of a value of type TYPE into register | |
379 | REGNUM in frame FRAME. */ | |
380 | ||
381 | void | |
382 | i387_value_to_register (struct frame_info *frame, int regnum, | |
42835c2b | 383 | struct type *type, const gdb_byte *from) |
d532c08f | 384 | { |
27067745 | 385 | struct gdbarch *gdbarch = get_frame_arch (frame); |
b4ad899f | 386 | gdb_byte to[I386_MAX_REGISTER_SIZE]; |
d532c08f | 387 | |
27067745 | 388 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
d532c08f MK |
389 | |
390 | /* We only support floating-point values. */ | |
391 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
392 | { | |
8a3fe4f8 AC |
393 | warning (_("Cannot convert non-floating-point type " |
394 | "to floating-point register value.")); | |
d532c08f MK |
395 | return; |
396 | } | |
397 | ||
83acabca | 398 | /* Convert from TYPE. */ |
27067745 | 399 | convert_typed_floating (from, type, to, i387_ext_type (gdbarch)); |
d532c08f MK |
400 | put_frame_register (frame, regnum, to); |
401 | } | |
402 | \f | |
e750d25e | 403 | |
786a90bb | 404 | /* Handle FSAVE and FXSAVE formats. */ |
e750d25e JT |
405 | |
406 | /* At fsave_offset[REGNUM] you'll find the offset to the location in | |
407 | the data structure used by the "fsave" instruction where GDB | |
408 | register REGNUM is stored. */ | |
409 | ||
410 | static int fsave_offset[] = | |
411 | { | |
5716833c MK |
412 | 28 + 0 * 10, /* %st(0) ... */ |
413 | 28 + 1 * 10, | |
414 | 28 + 2 * 10, | |
415 | 28 + 3 * 10, | |
416 | 28 + 4 * 10, | |
417 | 28 + 5 * 10, | |
418 | 28 + 6 * 10, | |
419 | 28 + 7 * 10, /* ... %st(7). */ | |
420 | 0, /* `fctrl' (16 bits). */ | |
421 | 4, /* `fstat' (16 bits). */ | |
422 | 8, /* `ftag' (16 bits). */ | |
423 | 16, /* `fiseg' (16 bits). */ | |
424 | 12, /* `fioff'. */ | |
425 | 24, /* `foseg' (16 bits). */ | |
426 | 20, /* `fooff'. */ | |
427 | 18 /* `fop' (bottom 11 bits). */ | |
e750d25e JT |
428 | }; |
429 | ||
20a6ec49 MD |
430 | #define FSAVE_ADDR(tdep, fsave, regnum) \ |
431 | (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)]) | |
e750d25e JT |
432 | \f |
433 | ||
41d041d6 MK |
434 | /* Fill register REGNUM in REGCACHE with the appropriate value from |
435 | *FSAVE. This function masks off any of the reserved bits in | |
436 | *FSAVE. */ | |
e750d25e JT |
437 | |
438 | void | |
41d041d6 | 439 | i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) |
e750d25e | 440 | { |
ac7936df | 441 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 UW |
442 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
443 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9a3c8263 | 444 | const gdb_byte *regs = (const gdb_byte *) fsave; |
e750d25e JT |
445 | int i; |
446 | ||
5716833c MK |
447 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
448 | ||
20a6ec49 | 449 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
ed504bdf MK |
450 | if (regnum == -1 || regnum == i) |
451 | { | |
452 | if (fsave == NULL) | |
453 | { | |
5716833c MK |
454 | regcache_raw_supply (regcache, i, NULL); |
455 | continue; | |
ed504bdf MK |
456 | } |
457 | ||
458 | /* Most of the FPU control registers occupy only 16 bits in the | |
459 | fsave area. Give those a special treatment. */ | |
20a6ec49 MD |
460 | if (i >= I387_FCTRL_REGNUM (tdep) |
461 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
ed504bdf | 462 | { |
b4ad899f | 463 | gdb_byte val[4]; |
ed504bdf | 464 | |
20a6ec49 | 465 | memcpy (val, FSAVE_ADDR (tdep, regs, i), 2); |
ed504bdf | 466 | val[2] = val[3] = 0; |
20a6ec49 | 467 | if (i == I387_FOP_REGNUM (tdep)) |
ed504bdf | 468 | val[1] &= ((1 << 3) - 1); |
5716833c | 469 | regcache_raw_supply (regcache, i, val); |
ed504bdf MK |
470 | } |
471 | else | |
20a6ec49 | 472 | regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i)); |
ed504bdf | 473 | } |
b87bc0d8 MK |
474 | |
475 | /* Provide dummy values for the SSE registers. */ | |
20a6ec49 | 476 | for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
b87bc0d8 MK |
477 | if (regnum == -1 || regnum == i) |
478 | regcache_raw_supply (regcache, i, NULL); | |
20a6ec49 | 479 | if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) |
b87bc0d8 | 480 | { |
b4ad899f | 481 | gdb_byte buf[4]; |
b87bc0d8 | 482 | |
e17a4113 | 483 | store_unsigned_integer (buf, 4, byte_order, 0x1f80); |
20a6ec49 | 484 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf); |
b87bc0d8 | 485 | } |
e750d25e JT |
486 | } |
487 | ||
488 | /* Fill register REGNUM (if it is a floating-point register) in *FSAVE | |
63b6c53f MK |
489 | with the value from REGCACHE. If REGNUM is -1, do this for all |
490 | registers. This function doesn't touch any of the reserved bits in | |
491 | *FSAVE. */ | |
e750d25e JT |
492 | |
493 | void | |
63b6c53f | 494 | i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) |
e750d25e | 495 | { |
ac7936df | 496 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
9a3c8263 | 497 | gdb_byte *regs = (gdb_byte *) fsave; |
e750d25e JT |
498 | int i; |
499 | ||
5716833c MK |
500 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
501 | ||
20a6ec49 | 502 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
e750d25e JT |
503 | if (regnum == -1 || regnum == i) |
504 | { | |
505 | /* Most of the FPU control registers occupy only 16 bits in | |
506 | the fsave area. Give those a special treatment. */ | |
20a6ec49 MD |
507 | if (i >= I387_FCTRL_REGNUM (tdep) |
508 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
e750d25e | 509 | { |
b4ad899f | 510 | gdb_byte buf[4]; |
e750d25e | 511 | |
5716833c | 512 | regcache_raw_collect (regcache, i, buf); |
e750d25e | 513 | |
20a6ec49 | 514 | if (i == I387_FOP_REGNUM (tdep)) |
e750d25e JT |
515 | { |
516 | /* The opcode occupies only 11 bits. Make sure we | |
517 | don't touch the other bits. */ | |
518 | buf[1] &= ((1 << 3) - 1); | |
20a6ec49 | 519 | buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
e750d25e | 520 | } |
20a6ec49 | 521 | memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); |
e750d25e JT |
522 | } |
523 | else | |
20a6ec49 | 524 | regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i)); |
e750d25e JT |
525 | } |
526 | } | |
527 | \f | |
528 | ||
529 | /* At fxsave_offset[REGNUM] you'll find the offset to the location in | |
530 | the data structure used by the "fxsave" instruction where GDB | |
531 | register REGNUM is stored. */ | |
532 | ||
533 | static int fxsave_offset[] = | |
534 | { | |
5716833c | 535 | 32, /* %st(0) through ... */ |
e750d25e JT |
536 | 48, |
537 | 64, | |
538 | 80, | |
539 | 96, | |
540 | 112, | |
541 | 128, | |
5716833c MK |
542 | 144, /* ... %st(7) (80 bits each). */ |
543 | 0, /* `fctrl' (16 bits). */ | |
544 | 2, /* `fstat' (16 bits). */ | |
545 | 4, /* `ftag' (16 bits). */ | |
546 | 12, /* `fiseg' (16 bits). */ | |
547 | 8, /* `fioff'. */ | |
548 | 20, /* `foseg' (16 bits). */ | |
549 | 16, /* `fooff'. */ | |
550 | 6, /* `fop' (bottom 11 bits). */ | |
551 | 160 + 0 * 16, /* %xmm0 through ... */ | |
04c8243f MK |
552 | 160 + 1 * 16, |
553 | 160 + 2 * 16, | |
554 | 160 + 3 * 16, | |
555 | 160 + 4 * 16, | |
556 | 160 + 5 * 16, | |
557 | 160 + 6 * 16, | |
558 | 160 + 7 * 16, | |
559 | 160 + 8 * 16, | |
560 | 160 + 9 * 16, | |
561 | 160 + 10 * 16, | |
562 | 160 + 11 * 16, | |
563 | 160 + 12 * 16, | |
564 | 160 + 13 * 16, | |
565 | 160 + 14 * 16, | |
5716833c | 566 | 160 + 15 * 16, /* ... %xmm15 (128 bits each). */ |
e750d25e JT |
567 | }; |
568 | ||
20a6ec49 MD |
569 | #define FXSAVE_ADDR(tdep, fxsave, regnum) \ |
570 | (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)]) | |
5716833c MK |
571 | |
572 | /* We made an unfortunate choice in putting %mxcsr after the SSE | |
573 | registers %xmm0-%xmm7 instead of before, since it makes supporting | |
574 | the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we | |
575 | don't include the offset for %mxcsr here above. */ | |
576 | ||
577 | #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24) | |
e750d25e | 578 | |
b4ad899f | 579 | static int i387_tag (const gdb_byte *raw); |
e750d25e JT |
580 | \f |
581 | ||
41d041d6 | 582 | /* Fill register REGNUM in REGCACHE with the appropriate |
ed504bdf MK |
583 | floating-point or SSE register value from *FXSAVE. This function |
584 | masks off any of the reserved bits in *FXSAVE. */ | |
e750d25e JT |
585 | |
586 | void | |
41d041d6 | 587 | i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) |
e750d25e | 588 | { |
ac7936df | 589 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
9a3c8263 | 590 | const gdb_byte *regs = (const gdb_byte *) fxsave; |
5716833c MK |
591 | int i; |
592 | ||
593 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
594 | gdb_assert (tdep->num_xmm_regs > 0); | |
dff95cc7 | 595 | |
20a6ec49 | 596 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
ed504bdf MK |
597 | if (regnum == -1 || regnum == i) |
598 | { | |
5716833c | 599 | if (regs == NULL) |
ed504bdf | 600 | { |
5716833c | 601 | regcache_raw_supply (regcache, i, NULL); |
ed504bdf MK |
602 | continue; |
603 | } | |
932bb524 | 604 | |
ed504bdf MK |
605 | /* Most of the FPU control registers occupy only 16 bits in |
606 | the fxsave area. Give those a special treatment. */ | |
20a6ec49 MD |
607 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
608 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
ed504bdf | 609 | { |
b4ad899f | 610 | gdb_byte val[4]; |
ed504bdf | 611 | |
20a6ec49 | 612 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); |
ed504bdf | 613 | val[2] = val[3] = 0; |
20a6ec49 | 614 | if (i == I387_FOP_REGNUM (tdep)) |
ed504bdf | 615 | val[1] &= ((1 << 3) - 1); |
20a6ec49 | 616 | else if (i== I387_FTAG_REGNUM (tdep)) |
ed504bdf MK |
617 | { |
618 | /* The fxsave area contains a simplified version of | |
619 | the tag word. We have to look at the actual 80-bit | |
620 | FP data to recreate the traditional i387 tag word. */ | |
621 | ||
622 | unsigned long ftag = 0; | |
623 | int fpreg; | |
624 | int top; | |
625 | ||
20a6ec49 MD |
626 | top = ((FXSAVE_ADDR (tdep, regs, |
627 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); | |
5716833c | 628 | top &= 0x7; |
ed504bdf MK |
629 | |
630 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
631 | { | |
632 | int tag; | |
633 | ||
634 | if (val[0] & (1 << fpreg)) | |
635 | { | |
6d5e094a MS |
636 | int thisreg = (fpreg + 8 - top) % 8 |
637 | + I387_ST0_REGNUM (tdep); | |
638 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); | |
ed504bdf MK |
639 | } |
640 | else | |
641 | tag = 3; /* Empty */ | |
642 | ||
643 | ftag |= tag << (2 * fpreg); | |
644 | } | |
645 | val[0] = ftag & 0xff; | |
646 | val[1] = (ftag >> 8) & 0xff; | |
647 | } | |
5716833c | 648 | regcache_raw_supply (regcache, i, val); |
ed504bdf MK |
649 | } |
650 | else | |
20a6ec49 | 651 | regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); |
ed504bdf | 652 | } |
5716833c | 653 | |
20a6ec49 | 654 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
5716833c MK |
655 | { |
656 | if (regs == NULL) | |
20a6ec49 | 657 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL); |
5716833c | 658 | else |
20a6ec49 | 659 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), |
5716833c MK |
660 | FXSAVE_MXCSR_ADDR (regs)); |
661 | } | |
e750d25e JT |
662 | } |
663 | ||
664 | /* Fill register REGNUM (if it is a floating-point or SSE register) in | |
80571bff MK |
665 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for |
666 | all registers. This function doesn't touch any of the reserved | |
667 | bits in *FXSAVE. */ | |
e750d25e JT |
668 | |
669 | void | |
80571bff | 670 | i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) |
e750d25e | 671 | { |
ac7936df | 672 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
9a3c8263 | 673 | gdb_byte *regs = (gdb_byte *) fxsave; |
5716833c MK |
674 | int i; |
675 | ||
676 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
677 | gdb_assert (tdep->num_xmm_regs > 0); | |
dff95cc7 | 678 | |
20a6ec49 | 679 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
e750d25e JT |
680 | if (regnum == -1 || regnum == i) |
681 | { | |
682 | /* Most of the FPU control registers occupy only 16 bits in | |
683 | the fxsave area. Give those a special treatment. */ | |
20a6ec49 MD |
684 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
685 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
e750d25e | 686 | { |
b4ad899f | 687 | gdb_byte buf[4]; |
e750d25e | 688 | |
5716833c | 689 | regcache_raw_collect (regcache, i, buf); |
e750d25e | 690 | |
31aeac78 L |
691 | if (i == I387_FOP_REGNUM (tdep)) |
692 | { | |
693 | /* The opcode occupies only 11 bits. Make sure we | |
694 | don't touch the other bits. */ | |
695 | buf[1] &= ((1 << 3) - 1); | |
696 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); | |
697 | } | |
698 | else if (i == I387_FTAG_REGNUM (tdep)) | |
699 | { | |
700 | /* Converting back is much easier. */ | |
701 | ||
702 | unsigned short ftag; | |
703 | int fpreg; | |
704 | ||
705 | ftag = (buf[1] << 8) | buf[0]; | |
706 | buf[0] = 0; | |
707 | buf[1] = 0; | |
708 | ||
709 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
710 | { | |
711 | int tag = (ftag >> (fpreg * 2)) & 3; | |
712 | ||
713 | if (tag != 3) | |
714 | buf[0] |= (1 << fpreg); | |
715 | } | |
716 | } | |
717 | memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); | |
718 | } | |
719 | else | |
720 | regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i)); | |
721 | } | |
722 | ||
723 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) | |
724 | regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep), | |
725 | FXSAVE_MXCSR_ADDR (regs)); | |
726 | } | |
727 | ||
728 | /* `xstate_bv' is at byte offset 512. */ | |
729 | #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) | |
730 | ||
731 | /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in | |
732 | the upper 128bit of AVX register data structure used by the "xsave" | |
733 | instruction where GDB register REGNUM is stored. */ | |
734 | ||
735 | static int xsave_avxh_offset[] = | |
736 | { | |
737 | 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */ | |
738 | 576 + 1 * 16, | |
739 | 576 + 2 * 16, | |
740 | 576 + 3 * 16, | |
741 | 576 + 4 * 16, | |
742 | 576 + 5 * 16, | |
743 | 576 + 6 * 16, | |
744 | 576 + 7 * 16, | |
745 | 576 + 8 * 16, | |
746 | 576 + 9 * 16, | |
747 | 576 + 10 * 16, | |
748 | 576 + 11 * 16, | |
749 | 576 + 12 * 16, | |
750 | 576 + 13 * 16, | |
751 | 576 + 14 * 16, | |
752 | 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ | |
753 | }; | |
754 | ||
01f9f808 MS |
755 | #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ |
756 | (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) | |
757 | ||
758 | /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in | |
759 | the upper 128bit of ZMM register data structure used by the "xsave" | |
760 | instruction where GDB register REGNUM is stored. */ | |
761 | ||
762 | static int xsave_ymm_avx512_offset[] = | |
763 | { | |
764 | /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */ | |
765 | 1664 + 16 + 0 * 64, /* %ymm16 through... */ | |
766 | 1664 + 16 + 1 * 64, | |
767 | 1664 + 16 + 2 * 64, | |
768 | 1664 + 16 + 3 * 64, | |
769 | 1664 + 16 + 4 * 64, | |
770 | 1664 + 16 + 5 * 64, | |
771 | 1664 + 16 + 6 * 64, | |
772 | 1664 + 16 + 7 * 64, | |
773 | 1664 + 16 + 8 * 64, | |
774 | 1664 + 16 + 9 * 64, | |
775 | 1664 + 16 + 10 * 64, | |
776 | 1664 + 16 + 11 * 64, | |
777 | 1664 + 16 + 12 * 64, | |
778 | 1664 + 16 + 13 * 64, | |
779 | 1664 + 16 + 14 * 64, | |
780 | 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ | |
781 | }; | |
782 | ||
783 | #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ | |
784 | (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) | |
785 | ||
786 | static int xsave_xmm_avx512_offset[] = | |
1dbcd68c | 787 | { |
01f9f808 MS |
788 | 1664 + 0 * 64, /* %ymm16 through... */ |
789 | 1664 + 1 * 64, | |
790 | 1664 + 2 * 64, | |
791 | 1664 + 3 * 64, | |
792 | 1664 + 4 * 64, | |
793 | 1664 + 5 * 64, | |
794 | 1664 + 6 * 64, | |
795 | 1664 + 7 * 64, | |
796 | 1664 + 8 * 64, | |
797 | 1664 + 9 * 64, | |
798 | 1664 + 10 * 64, | |
799 | 1664 + 11 * 64, | |
800 | 1664 + 12 * 64, | |
801 | 1664 + 13 * 64, | |
802 | 1664 + 14 * 64, | |
803 | 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */ | |
804 | }; | |
805 | ||
806 | #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ | |
807 | (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) | |
808 | ||
809 | static int xsave_mpx_offset[] = { | |
1dbcd68c WT |
810 | 960 + 0 * 16, /* bnd0r...bnd3r registers. */ |
811 | 960 + 1 * 16, | |
812 | 960 + 2 * 16, | |
813 | 960 + 3 * 16, | |
814 | 1024 + 0 * 8, /* bndcfg ... bndstatus. */ | |
815 | 1024 + 1 * 8, | |
816 | }; | |
817 | ||
1dbcd68c WT |
818 | #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ |
819 | (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) | |
820 | ||
01f9f808 MS |
821 | /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location |
822 | of the AVX512 opmask register data structure used by the "xsave" | |
823 | instruction where GDB register REGNUM is stored. */ | |
824 | ||
825 | static int xsave_avx512_k_offset[] = | |
826 | { | |
827 | 1088 + 0 * 8, /* %k0 through... */ | |
828 | 1088 + 1 * 8, | |
829 | 1088 + 2 * 8, | |
830 | 1088 + 3 * 8, | |
831 | 1088 + 4 * 8, | |
832 | 1088 + 5 * 8, | |
833 | 1088 + 6 * 8, | |
834 | 1088 + 7 * 8 /* %k7 (64 bits each). */ | |
835 | }; | |
836 | ||
837 | #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ | |
838 | (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) | |
839 | ||
840 | /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in | |
841 | the upper 256bit of AVX512 ZMMH register data structure used by the "xsave" | |
842 | instruction where GDB register REGNUM is stored. */ | |
843 | ||
844 | static int xsave_avx512_zmm_h_offset[] = | |
845 | { | |
846 | 1152 + 0 * 32, | |
847 | 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */ | |
848 | 1152 + 2 * 32, | |
849 | 1152 + 3 * 32, | |
850 | 1152 + 4 * 32, | |
851 | 1152 + 5 * 32, | |
852 | 1152 + 6 * 32, | |
853 | 1152 + 7 * 32, | |
854 | 1152 + 8 * 32, | |
855 | 1152 + 9 * 32, | |
856 | 1152 + 10 * 32, | |
857 | 1152 + 11 * 32, | |
858 | 1152 + 12 * 32, | |
859 | 1152 + 13 * 32, | |
860 | 1152 + 14 * 32, | |
861 | 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */ | |
862 | 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ | |
863 | 1664 + 32 + 1 * 64, | |
864 | 1664 + 32 + 2 * 64, | |
865 | 1664 + 32 + 3 * 64, | |
866 | 1664 + 32 + 4 * 64, | |
867 | 1664 + 32 + 5 * 64, | |
868 | 1664 + 32 + 6 * 64, | |
869 | 1664 + 32 + 7 * 64, | |
870 | 1664 + 32 + 8 * 64, | |
871 | 1664 + 32 + 9 * 64, | |
872 | 1664 + 32 + 10 * 64, | |
873 | 1664 + 32 + 11 * 64, | |
874 | 1664 + 32 + 12 * 64, | |
875 | 1664 + 32 + 13 * 64, | |
876 | 1664 + 32 + 14 * 64, | |
877 | 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ | |
878 | }; | |
879 | ||
880 | #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \ | |
881 | (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) | |
882 | ||
51547df6 MS |
883 | /* At xsave_pkeys_offset[REGNUM] you find the offset to the location |
884 | of the PKRU register data structure used by the "xsave" | |
885 | instruction where GDB register REGNUM is stored. */ | |
886 | ||
887 | static int xsave_pkeys_offset[] = | |
888 | { | |
889 | 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by | |
890 | instructions and applications). */ | |
891 | }; | |
892 | ||
893 | #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ | |
894 | (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) | |
895 | ||
31aeac78 L |
896 | /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ |
897 | ||
898 | void | |
899 | i387_supply_xsave (struct regcache *regcache, int regnum, | |
900 | const void *xsave) | |
901 | { | |
ac7936df | 902 | struct gdbarch *gdbarch = regcache->arch (); |
01f9f808 | 903 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 904 | const gdb_byte *regs = (const gdb_byte *) xsave; |
31aeac78 | 905 | int i; |
ff6527bb | 906 | ULONGEST clear_bv; |
975c21ab | 907 | static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 }; |
31aeac78 L |
908 | enum |
909 | { | |
910 | none = 0x0, | |
911 | x87 = 0x1, | |
912 | sse = 0x2, | |
913 | avxh = 0x4, | |
1dbcd68c | 914 | mpx = 0x8, |
01f9f808 MS |
915 | avx512_k = 0x10, |
916 | avx512_zmm_h = 0x20, | |
917 | avx512_ymmh_avx512 = 0x40, | |
918 | avx512_xmm_avx512 = 0x80, | |
51547df6 | 919 | pkeys = 0x100, |
01f9f808 | 920 | all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h |
51547df6 | 921 | | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys |
31aeac78 L |
922 | } regclass; |
923 | ||
275418ae | 924 | gdb_assert (regs != NULL); |
31aeac78 L |
925 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
926 | gdb_assert (tdep->num_xmm_regs > 0); | |
927 | ||
928 | if (regnum == -1) | |
929 | regclass = all; | |
51547df6 MS |
930 | else if (regnum >= I387_PKRU_REGNUM (tdep) |
931 | && regnum < I387_PKEYSEND_REGNUM (tdep)) | |
932 | regclass = pkeys; | |
01f9f808 MS |
933 | else if (regnum >= I387_ZMM0H_REGNUM (tdep) |
934 | && regnum < I387_ZMMENDH_REGNUM (tdep)) | |
935 | regclass = avx512_zmm_h; | |
936 | else if (regnum >= I387_K0_REGNUM (tdep) | |
937 | && regnum < I387_KEND_REGNUM (tdep)) | |
938 | regclass = avx512_k; | |
939 | else if (regnum >= I387_YMM16H_REGNUM (tdep) | |
940 | && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) | |
941 | regclass = avx512_ymmh_avx512; | |
942 | else if (regnum >= I387_XMM16_REGNUM (tdep) | |
943 | && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) | |
944 | regclass = avx512_xmm_avx512; | |
31aeac78 L |
945 | else if (regnum >= I387_YMM0H_REGNUM (tdep) |
946 | && regnum < I387_YMMENDH_REGNUM (tdep)) | |
947 | regclass = avxh; | |
1dbcd68c WT |
948 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
949 | && regnum < I387_MPXEND_REGNUM (tdep)) | |
950 | regclass = mpx; | |
01f9f808 | 951 | else if (regnum >= I387_XMM0_REGNUM (tdep) |
31aeac78 L |
952 | && regnum < I387_MXCSR_REGNUM (tdep)) |
953 | regclass = sse; | |
954 | else if (regnum >= I387_ST0_REGNUM (tdep) | |
955 | && regnum < I387_FCTRL_REGNUM (tdep)) | |
956 | regclass = x87; | |
957 | else | |
958 | regclass = none; | |
959 | ||
275418ae | 960 | if (regclass != none) |
31aeac78 | 961 | { |
ff6527bb MS |
962 | /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */ |
963 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
964 | ULONGEST xstate_bv = 0; | |
31aeac78 | 965 | |
ff6527bb MS |
966 | xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), |
967 | 8, byte_order); | |
968 | ||
969 | /* Clear part in vector registers if its bit in xstat_bv is zero. */ | |
970 | clear_bv = (~(xstate_bv)) & tdep->xcr0; | |
31aeac78 L |
971 | } |
972 | else | |
df7e5265 | 973 | clear_bv = X86_XSTATE_ALL_MASK; |
31aeac78 | 974 | |
b4d36fb8 PA |
975 | /* With the delayed xsave mechanism, in between the program |
976 | starting, and the program accessing the vector registers for the | |
977 | first time, the register's values are invalid. The kernel | |
978 | initializes register states to zero when they are set the first | |
979 | time in a program. This means that from the user-space programs' | |
980 | perspective, it's the same as if the registers have always been | |
981 | zero from the start of the program. Therefore, the debugger | |
275418ae | 982 | should provide the same illusion to the user. */ |
b4d36fb8 | 983 | |
31aeac78 L |
984 | switch (regclass) |
985 | { | |
986 | case none: | |
987 | break; | |
988 | ||
51547df6 MS |
989 | case pkeys: |
990 | if ((clear_bv & X86_XSTATE_PKRU)) | |
991 | regcache_raw_supply (regcache, regnum, zero); | |
992 | else | |
993 | regcache_raw_supply (regcache, regnum, | |
994 | XSAVE_PKEYS_ADDR (tdep, regs, regnum)); | |
995 | return; | |
996 | ||
01f9f808 | 997 | case avx512_zmm_h: |
df7e5265 | 998 | if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) |
01f9f808 MS |
999 | regcache_raw_supply (regcache, regnum, zero); |
1000 | else | |
1001 | regcache_raw_supply (regcache, regnum, | |
1002 | XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum)); | |
1003 | return; | |
1004 | ||
1005 | case avx512_k: | |
df7e5265 | 1006 | if ((clear_bv & X86_XSTATE_K)) |
01f9f808 MS |
1007 | regcache_raw_supply (regcache, regnum, zero); |
1008 | else | |
1009 | regcache_raw_supply (regcache, regnum, | |
1010 | XSAVE_AVX512_K_ADDR (tdep, regs, regnum)); | |
1011 | return; | |
1012 | ||
1013 | case avx512_ymmh_avx512: | |
df7e5265 | 1014 | if ((clear_bv & X86_XSTATE_ZMM)) |
01f9f808 MS |
1015 | regcache_raw_supply (regcache, regnum, zero); |
1016 | else | |
1017 | regcache_raw_supply (regcache, regnum, | |
1018 | XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); | |
1019 | return; | |
1020 | ||
1021 | case avx512_xmm_avx512: | |
df7e5265 | 1022 | if ((clear_bv & X86_XSTATE_ZMM)) |
01f9f808 MS |
1023 | regcache_raw_supply (regcache, regnum, zero); |
1024 | else | |
1025 | regcache_raw_supply (regcache, regnum, | |
1026 | XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum)); | |
1027 | return; | |
1028 | ||
31aeac78 | 1029 | case avxh: |
df7e5265 | 1030 | if ((clear_bv & X86_XSTATE_AVX)) |
275418ae | 1031 | regcache_raw_supply (regcache, regnum, zero); |
31aeac78 | 1032 | else |
b4d36fb8 PA |
1033 | regcache_raw_supply (regcache, regnum, |
1034 | XSAVE_AVXH_ADDR (tdep, regs, regnum)); | |
31aeac78 L |
1035 | return; |
1036 | ||
1dbcd68c | 1037 | case mpx: |
df7e5265 | 1038 | if ((clear_bv & X86_XSTATE_BNDREGS)) |
1dbcd68c WT |
1039 | regcache_raw_supply (regcache, regnum, zero); |
1040 | else | |
1041 | regcache_raw_supply (regcache, regnum, | |
1042 | XSAVE_MPX_ADDR (tdep, regs, regnum)); | |
1043 | return; | |
1044 | ||
31aeac78 | 1045 | case sse: |
df7e5265 | 1046 | if ((clear_bv & X86_XSTATE_SSE)) |
275418ae | 1047 | regcache_raw_supply (regcache, regnum, zero); |
31aeac78 | 1048 | else |
b4d36fb8 PA |
1049 | regcache_raw_supply (regcache, regnum, |
1050 | FXSAVE_ADDR (tdep, regs, regnum)); | |
31aeac78 L |
1051 | return; |
1052 | ||
1053 | case x87: | |
df7e5265 | 1054 | if ((clear_bv & X86_XSTATE_X87)) |
275418ae | 1055 | regcache_raw_supply (regcache, regnum, zero); |
31aeac78 | 1056 | else |
b4d36fb8 PA |
1057 | regcache_raw_supply (regcache, regnum, |
1058 | FXSAVE_ADDR (tdep, regs, regnum)); | |
31aeac78 L |
1059 | return; |
1060 | ||
1061 | case all: | |
51547df6 MS |
1062 | /* Handle PKEYS registers. */ |
1063 | if ((tdep->xcr0 & X86_XSTATE_PKRU)) | |
1064 | { | |
1065 | if ((clear_bv & X86_XSTATE_PKRU)) | |
1066 | { | |
1067 | for (i = I387_PKRU_REGNUM (tdep); | |
1068 | i < I387_PKEYSEND_REGNUM (tdep); | |
1069 | i++) | |
1070 | regcache_raw_supply (regcache, i, zero); | |
1071 | } | |
1072 | else | |
1073 | { | |
1074 | for (i = I387_PKRU_REGNUM (tdep); | |
1075 | i < I387_PKEYSEND_REGNUM (tdep); | |
1076 | i++) | |
1077 | regcache_raw_supply (regcache, i, | |
1078 | XSAVE_PKEYS_ADDR (tdep, regs, i)); | |
1079 | } | |
1080 | } | |
1081 | ||
01f9f808 | 1082 | /* Handle the upper ZMM registers. */ |
df7e5265 | 1083 | if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) |
01f9f808 | 1084 | { |
df7e5265 | 1085 | if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) |
01f9f808 MS |
1086 | { |
1087 | for (i = I387_ZMM0H_REGNUM (tdep); | |
1088 | i < I387_ZMMENDH_REGNUM (tdep); | |
1089 | i++) | |
1090 | regcache_raw_supply (regcache, i, zero); | |
1091 | } | |
1092 | else | |
1093 | { | |
1094 | for (i = I387_ZMM0H_REGNUM (tdep); | |
1095 | i < I387_ZMMENDH_REGNUM (tdep); | |
1096 | i++) | |
1097 | regcache_raw_supply (regcache, i, | |
1098 | XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | /* Handle AVX512 OpMask registers. */ | |
df7e5265 | 1103 | if ((tdep->xcr0 & X86_XSTATE_K)) |
01f9f808 | 1104 | { |
df7e5265 | 1105 | if ((clear_bv & X86_XSTATE_K)) |
01f9f808 MS |
1106 | { |
1107 | for (i = I387_K0_REGNUM (tdep); | |
1108 | i < I387_KEND_REGNUM (tdep); | |
1109 | i++) | |
1110 | regcache_raw_supply (regcache, i, zero); | |
1111 | } | |
1112 | else | |
1113 | { | |
1114 | for (i = I387_K0_REGNUM (tdep); | |
1115 | i < I387_KEND_REGNUM (tdep); | |
1116 | i++) | |
1117 | regcache_raw_supply (regcache, i, | |
1118 | XSAVE_AVX512_K_ADDR (tdep, regs, i)); | |
1119 | } | |
1120 | } | |
1121 | ||
1122 | /* Handle the YMM_AVX512 registers. */ | |
df7e5265 | 1123 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) |
01f9f808 | 1124 | { |
df7e5265 | 1125 | if ((clear_bv & X86_XSTATE_ZMM)) |
01f9f808 MS |
1126 | { |
1127 | for (i = I387_YMM16H_REGNUM (tdep); | |
1128 | i < I387_YMMH_AVX512_END_REGNUM (tdep); | |
1129 | i++) | |
1130 | regcache_raw_supply (regcache, i, zero); | |
1131 | for (i = I387_XMM16_REGNUM (tdep); | |
1132 | i < I387_XMM_AVX512_END_REGNUM (tdep); | |
1133 | i++) | |
1134 | regcache_raw_supply (regcache, i, zero); | |
1135 | } | |
1136 | else | |
1137 | { | |
1138 | for (i = I387_YMM16H_REGNUM (tdep); | |
1139 | i < I387_YMMH_AVX512_END_REGNUM (tdep); | |
1140 | i++) | |
1141 | regcache_raw_supply (regcache, i, | |
1142 | XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); | |
1143 | for (i = I387_XMM16_REGNUM (tdep); | |
1144 | i < I387_XMM_AVX512_END_REGNUM (tdep); | |
1145 | i++) | |
1146 | regcache_raw_supply (regcache, i, | |
1147 | XSAVE_XMM_AVX512_ADDR (tdep, regs, i)); | |
1148 | } | |
1149 | } | |
86d31898 | 1150 | /* Handle the upper YMM registers. */ |
df7e5265 | 1151 | if ((tdep->xcr0 & X86_XSTATE_AVX)) |
31aeac78 | 1152 | { |
df7e5265 | 1153 | if ((clear_bv & X86_XSTATE_AVX)) |
b4d36fb8 PA |
1154 | { |
1155 | for (i = I387_YMM0H_REGNUM (tdep); | |
1156 | i < I387_YMMENDH_REGNUM (tdep); | |
1157 | i++) | |
275418ae | 1158 | regcache_raw_supply (regcache, i, zero); |
b4d36fb8 | 1159 | } |
31aeac78 | 1160 | else |
31aeac78 | 1161 | { |
b4d36fb8 PA |
1162 | for (i = I387_YMM0H_REGNUM (tdep); |
1163 | i < I387_YMMENDH_REGNUM (tdep); | |
1164 | i++) | |
1165 | regcache_raw_supply (regcache, i, | |
1166 | XSAVE_AVXH_ADDR (tdep, regs, i)); | |
31aeac78 L |
1167 | } |
1168 | } | |
1169 | ||
1dbcd68c | 1170 | /* Handle the MPX registers. */ |
df7e5265 | 1171 | if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) |
1dbcd68c | 1172 | { |
df7e5265 | 1173 | if (clear_bv & X86_XSTATE_BNDREGS) |
1dbcd68c WT |
1174 | { |
1175 | for (i = I387_BND0R_REGNUM (tdep); | |
1176 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1177 | regcache_raw_supply (regcache, i, zero); | |
1178 | } | |
1179 | else | |
1180 | { | |
1181 | for (i = I387_BND0R_REGNUM (tdep); | |
1182 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1183 | regcache_raw_supply (regcache, i, | |
1184 | XSAVE_MPX_ADDR (tdep, regs, i)); | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | /* Handle the MPX registers. */ | |
df7e5265 | 1189 | if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) |
1dbcd68c | 1190 | { |
df7e5265 | 1191 | if (clear_bv & X86_XSTATE_BNDCFG) |
1dbcd68c WT |
1192 | { |
1193 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1194 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1195 | regcache_raw_supply (regcache, i, zero); | |
1196 | } | |
1197 | else | |
1198 | { | |
1199 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1200 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1201 | regcache_raw_supply (regcache, i, | |
1202 | XSAVE_MPX_ADDR (tdep, regs, i)); | |
1203 | } | |
1204 | } | |
1205 | ||
31aeac78 | 1206 | /* Handle the XMM registers. */ |
df7e5265 | 1207 | if ((tdep->xcr0 & X86_XSTATE_SSE)) |
31aeac78 | 1208 | { |
df7e5265 | 1209 | if ((clear_bv & X86_XSTATE_SSE)) |
b4d36fb8 PA |
1210 | { |
1211 | for (i = I387_XMM0_REGNUM (tdep); | |
1212 | i < I387_MXCSR_REGNUM (tdep); | |
1213 | i++) | |
275418ae | 1214 | regcache_raw_supply (regcache, i, zero); |
b4d36fb8 | 1215 | } |
31aeac78 | 1216 | else |
31aeac78 | 1217 | { |
b4d36fb8 PA |
1218 | for (i = I387_XMM0_REGNUM (tdep); |
1219 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1220 | regcache_raw_supply (regcache, i, | |
1221 | FXSAVE_ADDR (tdep, regs, i)); | |
31aeac78 L |
1222 | } |
1223 | } | |
1224 | ||
1225 | /* Handle the x87 registers. */ | |
df7e5265 | 1226 | if ((tdep->xcr0 & X86_XSTATE_X87)) |
31aeac78 | 1227 | { |
df7e5265 | 1228 | if ((clear_bv & X86_XSTATE_X87)) |
b4d36fb8 PA |
1229 | { |
1230 | for (i = I387_ST0_REGNUM (tdep); | |
1231 | i < I387_FCTRL_REGNUM (tdep); | |
1232 | i++) | |
275418ae | 1233 | regcache_raw_supply (regcache, i, zero); |
b4d36fb8 | 1234 | } |
31aeac78 | 1235 | else |
31aeac78 | 1236 | { |
b4d36fb8 PA |
1237 | for (i = I387_ST0_REGNUM (tdep); |
1238 | i < I387_FCTRL_REGNUM (tdep); | |
1239 | i++) | |
1240 | regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); | |
31aeac78 L |
1241 | } |
1242 | } | |
1243 | break; | |
1244 | } | |
1245 | ||
1246 | /* Only handle x87 control registers. */ | |
1247 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) | |
1248 | if (regnum == -1 || regnum == i) | |
1249 | { | |
31aeac78 L |
1250 | /* Most of the FPU control registers occupy only 16 bits in |
1251 | the xsave extended state. Give those a special treatment. */ | |
1252 | if (i != I387_FIOFF_REGNUM (tdep) | |
1253 | && i != I387_FOOFF_REGNUM (tdep)) | |
1254 | { | |
1255 | gdb_byte val[4]; | |
1256 | ||
1257 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); | |
1258 | val[2] = val[3] = 0; | |
1259 | if (i == I387_FOP_REGNUM (tdep)) | |
1260 | val[1] &= ((1 << 3) - 1); | |
1261 | else if (i== I387_FTAG_REGNUM (tdep)) | |
1262 | { | |
1263 | /* The fxsave area contains a simplified version of | |
1264 | the tag word. We have to look at the actual 80-bit | |
1265 | FP data to recreate the traditional i387 tag word. */ | |
1266 | ||
1267 | unsigned long ftag = 0; | |
1268 | int fpreg; | |
1269 | int top; | |
1270 | ||
1271 | top = ((FXSAVE_ADDR (tdep, regs, | |
1272 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); | |
1273 | top &= 0x7; | |
1274 | ||
1275 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
1276 | { | |
1277 | int tag; | |
1278 | ||
1279 | if (val[0] & (1 << fpreg)) | |
1280 | { | |
e5b3d7d6 | 1281 | int thisreg = (fpreg + 8 - top) % 8 |
31aeac78 | 1282 | + I387_ST0_REGNUM (tdep); |
e5b3d7d6 | 1283 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); |
31aeac78 L |
1284 | } |
1285 | else | |
1286 | tag = 3; /* Empty */ | |
1287 | ||
1288 | ftag |= tag << (2 * fpreg); | |
1289 | } | |
1290 | val[0] = ftag & 0xff; | |
1291 | val[1] = (ftag >> 8) & 0xff; | |
1292 | } | |
1293 | regcache_raw_supply (regcache, i, val); | |
1294 | } | |
1295 | else | |
1296 | regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); | |
1297 | } | |
1298 | ||
1299 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) | |
275418ae PA |
1300 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), |
1301 | FXSAVE_MXCSR_ADDR (regs)); | |
31aeac78 L |
1302 | } |
1303 | ||
1304 | /* Similar to i387_collect_fxsave, but use XSAVE extended state. */ | |
1305 | ||
1306 | void | |
1307 | i387_collect_xsave (const struct regcache *regcache, int regnum, | |
1308 | void *xsave, int gcore) | |
1309 | { | |
ac7936df | 1310 | struct gdbarch *gdbarch = regcache->arch (); |
01f9f808 | 1311 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 1312 | gdb_byte *regs = (gdb_byte *) xsave; |
31aeac78 L |
1313 | int i; |
1314 | enum | |
1315 | { | |
1316 | none = 0x0, | |
1317 | check = 0x1, | |
1318 | x87 = 0x2 | check, | |
1319 | sse = 0x4 | check, | |
1320 | avxh = 0x8 | check, | |
1dbcd68c | 1321 | mpx = 0x10 | check, |
01f9f808 MS |
1322 | avx512_k = 0x20 | check, |
1323 | avx512_zmm_h = 0x40 | check, | |
1324 | avx512_ymmh_avx512 = 0x80 | check, | |
1325 | avx512_xmm_avx512 = 0x100 | check, | |
51547df6 | 1326 | pkeys = 0x200 | check, |
01f9f808 | 1327 | all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h |
51547df6 | 1328 | | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys |
31aeac78 L |
1329 | } regclass; |
1330 | ||
1331 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
1332 | gdb_assert (tdep->num_xmm_regs > 0); | |
1333 | ||
1334 | if (regnum == -1) | |
1335 | regclass = all; | |
51547df6 MS |
1336 | else if (regnum >= I387_PKRU_REGNUM (tdep) |
1337 | && regnum < I387_PKEYSEND_REGNUM (tdep)) | |
1338 | regclass = pkeys; | |
01f9f808 MS |
1339 | else if (regnum >= I387_ZMM0H_REGNUM (tdep) |
1340 | && regnum < I387_ZMMENDH_REGNUM (tdep)) | |
1341 | regclass = avx512_zmm_h; | |
1342 | else if (regnum >= I387_K0_REGNUM (tdep) | |
1343 | && regnum < I387_KEND_REGNUM (tdep)) | |
1344 | regclass = avx512_k; | |
1345 | else if (regnum >= I387_YMM16H_REGNUM (tdep) | |
1346 | && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) | |
1347 | regclass = avx512_ymmh_avx512; | |
1348 | else if (regnum >= I387_XMM16_REGNUM (tdep) | |
1349 | && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) | |
1350 | regclass = avx512_xmm_avx512; | |
31aeac78 L |
1351 | else if (regnum >= I387_YMM0H_REGNUM (tdep) |
1352 | && regnum < I387_YMMENDH_REGNUM (tdep)) | |
1353 | regclass = avxh; | |
1dbcd68c WT |
1354 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
1355 | && regnum < I387_MPXEND_REGNUM (tdep)) | |
1356 | regclass = mpx; | |
1357 | else if (regnum >= I387_XMM0_REGNUM (tdep) | |
31aeac78 L |
1358 | && regnum < I387_MXCSR_REGNUM (tdep)) |
1359 | regclass = sse; | |
1360 | else if (regnum >= I387_ST0_REGNUM (tdep) | |
1361 | && regnum < I387_FCTRL_REGNUM (tdep)) | |
1362 | regclass = x87; | |
1363 | else | |
1364 | regclass = none; | |
1365 | ||
1366 | if (gcore) | |
1367 | { | |
1368 | /* Clear XSAVE extended state. */ | |
df7e5265 | 1369 | memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0)); |
31aeac78 L |
1370 | |
1371 | /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ | |
1372 | if (tdep->xsave_xcr0_offset != -1) | |
1373 | memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8); | |
1374 | memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); | |
1375 | } | |
1376 | ||
1377 | if ((regclass & check)) | |
1378 | { | |
1379 | gdb_byte raw[I386_MAX_REGISTER_SIZE]; | |
ff6527bb | 1380 | ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0; |
31aeac78 | 1381 | gdb_byte *p; |
ff6527bb MS |
1382 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1383 | ||
1384 | /* The supported bits in `xstat_bv' are 8 bytes. */ | |
1385 | initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), | |
1386 | 8, byte_order); | |
1387 | clear_bv = (~(initial_xstate_bv)) & tdep->xcr0; | |
31aeac78 L |
1388 | |
1389 | /* Clear register set if its bit in xstat_bv is zero. */ | |
1390 | if (clear_bv) | |
1391 | { | |
51547df6 MS |
1392 | if ((clear_bv & X86_XSTATE_PKRU)) |
1393 | for (i = I387_PKRU_REGNUM (tdep); | |
1394 | i < I387_PKEYSEND_REGNUM (tdep); i++) | |
1395 | memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4); | |
1396 | ||
df7e5265 | 1397 | if ((clear_bv & X86_XSTATE_BNDREGS)) |
1dbcd68c WT |
1398 | for (i = I387_BND0R_REGNUM (tdep); |
1399 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1400 | memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); | |
1401 | ||
df7e5265 | 1402 | if ((clear_bv & X86_XSTATE_BNDCFG)) |
1dbcd68c WT |
1403 | for (i = I387_BNDCFGU_REGNUM (tdep); |
1404 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1405 | memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); | |
1406 | ||
df7e5265 | 1407 | if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) |
01f9f808 MS |
1408 | for (i = I387_ZMM0H_REGNUM (tdep); |
1409 | i < I387_ZMMENDH_REGNUM (tdep); i++) | |
1410 | memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); | |
1411 | ||
df7e5265 | 1412 | if ((clear_bv & X86_XSTATE_K)) |
01f9f808 MS |
1413 | for (i = I387_K0_REGNUM (tdep); |
1414 | i < I387_KEND_REGNUM (tdep); i++) | |
1415 | memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8); | |
1416 | ||
df7e5265 | 1417 | if ((clear_bv & X86_XSTATE_ZMM)) |
01f9f808 MS |
1418 | { |
1419 | for (i = I387_YMM16H_REGNUM (tdep); | |
1420 | i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) | |
1421 | memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); | |
1422 | for (i = I387_XMM16_REGNUM (tdep); | |
1423 | i < I387_XMM_AVX512_END_REGNUM (tdep); i++) | |
1424 | memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); | |
1425 | } | |
1426 | ||
df7e5265 | 1427 | if ((clear_bv & X86_XSTATE_AVX)) |
31aeac78 L |
1428 | for (i = I387_YMM0H_REGNUM (tdep); |
1429 | i < I387_YMMENDH_REGNUM (tdep); i++) | |
1430 | memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); | |
1431 | ||
df7e5265 | 1432 | if ((clear_bv & X86_XSTATE_SSE)) |
31aeac78 L |
1433 | for (i = I387_XMM0_REGNUM (tdep); |
1434 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1435 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); | |
1436 | ||
df7e5265 | 1437 | if ((clear_bv & X86_XSTATE_X87)) |
31aeac78 L |
1438 | for (i = I387_ST0_REGNUM (tdep); |
1439 | i < I387_FCTRL_REGNUM (tdep); i++) | |
1440 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); | |
1441 | } | |
1442 | ||
1443 | if (regclass == all) | |
1444 | { | |
51547df6 MS |
1445 | /* Check if any PKEYS registers are changed. */ |
1446 | if ((tdep->xcr0 & X86_XSTATE_PKRU)) | |
1447 | for (i = I387_PKRU_REGNUM (tdep); | |
1448 | i < I387_PKEYSEND_REGNUM (tdep); i++) | |
1449 | { | |
1450 | regcache_raw_collect (regcache, i, raw); | |
1451 | p = XSAVE_PKEYS_ADDR (tdep, regs, i); | |
1452 | if (memcmp (raw, p, 4) != 0) | |
1453 | { | |
1454 | xstate_bv |= X86_XSTATE_PKRU; | |
1455 | memcpy (p, raw, 4); | |
1456 | } | |
1457 | } | |
1458 | ||
01f9f808 | 1459 | /* Check if any ZMMH registers are changed. */ |
df7e5265 | 1460 | if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) |
01f9f808 MS |
1461 | for (i = I387_ZMM0H_REGNUM (tdep); |
1462 | i < I387_ZMMENDH_REGNUM (tdep); i++) | |
1463 | { | |
1464 | regcache_raw_collect (regcache, i, raw); | |
1465 | p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i); | |
1466 | if (memcmp (raw, p, 32) != 0) | |
1467 | { | |
df7e5265 | 1468 | xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); |
01f9f808 MS |
1469 | memcpy (p, raw, 32); |
1470 | } | |
1471 | } | |
1472 | ||
1473 | /* Check if any K registers are changed. */ | |
df7e5265 | 1474 | if ((tdep->xcr0 & X86_XSTATE_K)) |
01f9f808 MS |
1475 | for (i = I387_K0_REGNUM (tdep); |
1476 | i < I387_KEND_REGNUM (tdep); i++) | |
1477 | { | |
1478 | regcache_raw_collect (regcache, i, raw); | |
1479 | p = XSAVE_AVX512_K_ADDR (tdep, regs, i); | |
1480 | if (memcmp (raw, p, 8) != 0) | |
1481 | { | |
df7e5265 | 1482 | xstate_bv |= X86_XSTATE_K; |
01f9f808 MS |
1483 | memcpy (p, raw, 8); |
1484 | } | |
1485 | } | |
1486 | ||
1487 | /* Check if any XMM or upper YMM registers are changed. */ | |
df7e5265 | 1488 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) |
01f9f808 MS |
1489 | { |
1490 | for (i = I387_YMM16H_REGNUM (tdep); | |
1491 | i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) | |
1492 | { | |
1493 | regcache_raw_collect (regcache, i, raw); | |
1494 | p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); | |
1495 | if (memcmp (raw, p, 16) != 0) | |
1496 | { | |
df7e5265 | 1497 | xstate_bv |= X86_XSTATE_ZMM; |
01f9f808 MS |
1498 | memcpy (p, raw, 16); |
1499 | } | |
1500 | } | |
1501 | for (i = I387_XMM16_REGNUM (tdep); | |
1502 | i < I387_XMM_AVX512_END_REGNUM (tdep); i++) | |
1503 | { | |
1504 | regcache_raw_collect (regcache, i, raw); | |
1505 | p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i); | |
1506 | if (memcmp (raw, p, 16) != 0) | |
1507 | { | |
df7e5265 | 1508 | xstate_bv |= X86_XSTATE_ZMM; |
01f9f808 MS |
1509 | memcpy (p, raw, 16); |
1510 | } | |
1511 | } | |
1512 | } | |
1513 | ||
31aeac78 | 1514 | /* Check if any upper YMM registers are changed. */ |
df7e5265 | 1515 | if ((tdep->xcr0 & X86_XSTATE_AVX)) |
31aeac78 L |
1516 | for (i = I387_YMM0H_REGNUM (tdep); |
1517 | i < I387_YMMENDH_REGNUM (tdep); i++) | |
1518 | { | |
1519 | regcache_raw_collect (regcache, i, raw); | |
1520 | p = XSAVE_AVXH_ADDR (tdep, regs, i); | |
1521 | if (memcmp (raw, p, 16)) | |
1522 | { | |
df7e5265 | 1523 | xstate_bv |= X86_XSTATE_AVX; |
31aeac78 L |
1524 | memcpy (p, raw, 16); |
1525 | } | |
1526 | } | |
1dbcd68c | 1527 | /* Check if any upper MPX registers are changed. */ |
df7e5265 | 1528 | if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) |
1dbcd68c WT |
1529 | for (i = I387_BND0R_REGNUM (tdep); |
1530 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1531 | { | |
1532 | regcache_raw_collect (regcache, i, raw); | |
1533 | p = XSAVE_MPX_ADDR (tdep, regs, i); | |
1534 | if (memcmp (raw, p, 16)) | |
1535 | { | |
df7e5265 | 1536 | xstate_bv |= X86_XSTATE_BNDREGS; |
1dbcd68c WT |
1537 | memcpy (p, raw, 16); |
1538 | } | |
1539 | } | |
1540 | ||
1541 | /* Check if any upper MPX registers are changed. */ | |
df7e5265 | 1542 | if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) |
1dbcd68c WT |
1543 | for (i = I387_BNDCFGU_REGNUM (tdep); |
1544 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1545 | { | |
1546 | regcache_raw_collect (regcache, i, raw); | |
1547 | p = XSAVE_MPX_ADDR (tdep, regs, i); | |
1548 | if (memcmp (raw, p, 8)) | |
1549 | { | |
df7e5265 | 1550 | xstate_bv |= X86_XSTATE_BNDCFG; |
1dbcd68c WT |
1551 | memcpy (p, raw, 8); |
1552 | } | |
1553 | } | |
31aeac78 L |
1554 | |
1555 | /* Check if any SSE registers are changed. */ | |
df7e5265 | 1556 | if ((tdep->xcr0 & X86_XSTATE_SSE)) |
31aeac78 L |
1557 | for (i = I387_XMM0_REGNUM (tdep); |
1558 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1559 | { | |
1560 | regcache_raw_collect (regcache, i, raw); | |
1561 | p = FXSAVE_ADDR (tdep, regs, i); | |
1562 | if (memcmp (raw, p, 16)) | |
1563 | { | |
df7e5265 | 1564 | xstate_bv |= X86_XSTATE_SSE; |
31aeac78 L |
1565 | memcpy (p, raw, 16); |
1566 | } | |
1567 | } | |
1568 | ||
1569 | /* Check if any X87 registers are changed. */ | |
df7e5265 | 1570 | if ((tdep->xcr0 & X86_XSTATE_X87)) |
31aeac78 L |
1571 | for (i = I387_ST0_REGNUM (tdep); |
1572 | i < I387_FCTRL_REGNUM (tdep); i++) | |
1573 | { | |
1574 | regcache_raw_collect (regcache, i, raw); | |
1575 | p = FXSAVE_ADDR (tdep, regs, i); | |
1576 | if (memcmp (raw, p, 10)) | |
1577 | { | |
df7e5265 | 1578 | xstate_bv |= X86_XSTATE_X87; |
31aeac78 L |
1579 | memcpy (p, raw, 10); |
1580 | } | |
1581 | } | |
1582 | } | |
1583 | else | |
1584 | { | |
1585 | /* Check if REGNUM is changed. */ | |
1586 | regcache_raw_collect (regcache, regnum, raw); | |
1587 | ||
1588 | switch (regclass) | |
1589 | { | |
1590 | default: | |
4e4d8374 L |
1591 | internal_error (__FILE__, __LINE__, |
1592 | _("invalid i387 regclass")); | |
31aeac78 | 1593 | |
51547df6 MS |
1594 | case pkeys: |
1595 | /* This is a PKEYS register. */ | |
1596 | p = XSAVE_PKEYS_ADDR (tdep, regs, regnum); | |
1597 | if (memcmp (raw, p, 4) != 0) | |
1598 | { | |
1599 | xstate_bv |= X86_XSTATE_PKRU; | |
1600 | memcpy (p, raw, 4); | |
1601 | } | |
1602 | break; | |
1603 | ||
01f9f808 MS |
1604 | case avx512_zmm_h: |
1605 | /* This is a ZMM register. */ | |
1606 | p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum); | |
1607 | if (memcmp (raw, p, 32) != 0) | |
1608 | { | |
df7e5265 | 1609 | xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); |
01f9f808 MS |
1610 | memcpy (p, raw, 32); |
1611 | } | |
1612 | break; | |
1613 | case avx512_k: | |
1614 | /* This is a AVX512 mask register. */ | |
1615 | p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); | |
1616 | if (memcmp (raw, p, 8) != 0) | |
1617 | { | |
df7e5265 | 1618 | xstate_bv |= X86_XSTATE_K; |
01f9f808 MS |
1619 | memcpy (p, raw, 8); |
1620 | } | |
1621 | break; | |
1622 | ||
1623 | case avx512_ymmh_avx512: | |
1624 | /* This is an upper YMM16-31 register. */ | |
1625 | p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); | |
1626 | if (memcmp (raw, p, 16) != 0) | |
1627 | { | |
df7e5265 | 1628 | xstate_bv |= X86_XSTATE_ZMM; |
01f9f808 MS |
1629 | memcpy (p, raw, 16); |
1630 | } | |
1631 | break; | |
1632 | ||
1633 | case avx512_xmm_avx512: | |
1634 | /* This is an upper XMM16-31 register. */ | |
1635 | p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum); | |
1636 | if (memcmp (raw, p, 16) != 0) | |
1637 | { | |
df7e5265 | 1638 | xstate_bv |= X86_XSTATE_ZMM; |
01f9f808 MS |
1639 | memcpy (p, raw, 16); |
1640 | } | |
1641 | break; | |
1642 | ||
40936b0d L |
1643 | case avxh: |
1644 | /* This is an upper YMM register. */ | |
1645 | p = XSAVE_AVXH_ADDR (tdep, regs, regnum); | |
1646 | if (memcmp (raw, p, 16)) | |
31aeac78 | 1647 | { |
df7e5265 | 1648 | xstate_bv |= X86_XSTATE_AVX; |
40936b0d L |
1649 | memcpy (p, raw, 16); |
1650 | } | |
1651 | break; | |
31aeac78 | 1652 | |
1dbcd68c WT |
1653 | case mpx: |
1654 | if (regnum < I387_BNDCFGU_REGNUM (tdep)) | |
1655 | { | |
1656 | regcache_raw_collect (regcache, regnum, raw); | |
1657 | p = XSAVE_MPX_ADDR (tdep, regs, regnum); | |
1658 | if (memcmp (raw, p, 16)) | |
1659 | { | |
df7e5265 | 1660 | xstate_bv |= X86_XSTATE_BNDREGS; |
1dbcd68c WT |
1661 | memcpy (p, raw, 16); |
1662 | } | |
1663 | } | |
1664 | else | |
1665 | { | |
1666 | p = XSAVE_MPX_ADDR (tdep, regs, regnum); | |
df7e5265 | 1667 | xstate_bv |= X86_XSTATE_BNDCFG; |
1dbcd68c WT |
1668 | memcpy (p, raw, 8); |
1669 | } | |
1670 | break; | |
1671 | ||
40936b0d L |
1672 | case sse: |
1673 | /* This is an SSE register. */ | |
1674 | p = FXSAVE_ADDR (tdep, regs, regnum); | |
1675 | if (memcmp (raw, p, 16)) | |
1676 | { | |
df7e5265 | 1677 | xstate_bv |= X86_XSTATE_SSE; |
40936b0d L |
1678 | memcpy (p, raw, 16); |
1679 | } | |
1680 | break; | |
31aeac78 | 1681 | |
40936b0d L |
1682 | case x87: |
1683 | /* This is an x87 register. */ | |
1684 | p = FXSAVE_ADDR (tdep, regs, regnum); | |
1685 | if (memcmp (raw, p, 10)) | |
1686 | { | |
df7e5265 | 1687 | xstate_bv |= X86_XSTATE_X87; |
40936b0d | 1688 | memcpy (p, raw, 10); |
31aeac78 | 1689 | } |
40936b0d | 1690 | break; |
31aeac78 | 1691 | } |
40936b0d L |
1692 | } |
1693 | ||
1694 | /* Update the corresponding bits in `xstate_bv' if any SSE/AVX | |
1695 | registers are changed. */ | |
1696 | if (xstate_bv) | |
1697 | { | |
ff6527bb MS |
1698 | /* The supported bits in `xstat_bv' are 8 bytes. */ |
1699 | initial_xstate_bv |= xstate_bv; | |
1700 | store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), | |
1701 | 8, byte_order, | |
1702 | initial_xstate_bv); | |
40936b0d L |
1703 | |
1704 | switch (regclass) | |
31aeac78 | 1705 | { |
40936b0d | 1706 | default: |
4e4d8374 L |
1707 | internal_error (__FILE__, __LINE__, |
1708 | _("invalid i387 regclass")); | |
40936b0d L |
1709 | |
1710 | case all: | |
1711 | break; | |
1712 | ||
1713 | case x87: | |
1714 | case sse: | |
1715 | case avxh: | |
1dbcd68c | 1716 | case mpx: |
01f9f808 MS |
1717 | case avx512_k: |
1718 | case avx512_zmm_h: | |
1719 | case avx512_ymmh_avx512: | |
1720 | case avx512_xmm_avx512: | |
51547df6 | 1721 | case pkeys: |
40936b0d L |
1722 | /* Register REGNUM has been updated. Return. */ |
1723 | return; | |
31aeac78 | 1724 | } |
40936b0d L |
1725 | } |
1726 | else | |
1727 | { | |
1728 | /* Return if REGNUM isn't changed. */ | |
1729 | if (regclass != all) | |
1730 | return; | |
1731 | } | |
31aeac78 L |
1732 | } |
1733 | ||
1734 | /* Only handle x87 control registers. */ | |
1735 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) | |
1736 | if (regnum == -1 || regnum == i) | |
1737 | { | |
1738 | /* Most of the FPU control registers occupy only 16 bits in | |
1739 | the xsave extended state. Give those a special treatment. */ | |
1740 | if (i != I387_FIOFF_REGNUM (tdep) | |
1741 | && i != I387_FOOFF_REGNUM (tdep)) | |
1742 | { | |
1743 | gdb_byte buf[4]; | |
1744 | ||
1745 | regcache_raw_collect (regcache, i, buf); | |
1746 | ||
20a6ec49 | 1747 | if (i == I387_FOP_REGNUM (tdep)) |
e750d25e JT |
1748 | { |
1749 | /* The opcode occupies only 11 bits. Make sure we | |
40936b0d | 1750 | don't touch the other bits. */ |
e750d25e | 1751 | buf[1] &= ((1 << 3) - 1); |
20a6ec49 | 1752 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
e750d25e | 1753 | } |
20a6ec49 | 1754 | else if (i == I387_FTAG_REGNUM (tdep)) |
e750d25e JT |
1755 | { |
1756 | /* Converting back is much easier. */ | |
1757 | ||
1758 | unsigned short ftag; | |
1759 | int fpreg; | |
1760 | ||
1761 | ftag = (buf[1] << 8) | buf[0]; | |
1762 | buf[0] = 0; | |
1763 | buf[1] = 0; | |
1764 | ||
1765 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
1766 | { | |
1767 | int tag = (ftag >> (fpreg * 2)) & 3; | |
1768 | ||
1769 | if (tag != 3) | |
1770 | buf[0] |= (1 << fpreg); | |
1771 | } | |
1772 | } | |
20a6ec49 | 1773 | memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); |
e750d25e JT |
1774 | } |
1775 | else | |
20a6ec49 | 1776 | regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i)); |
e750d25e | 1777 | } |
5716833c | 1778 | |
20a6ec49 MD |
1779 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
1780 | regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep), | |
5716833c | 1781 | FXSAVE_MXCSR_ADDR (regs)); |
e750d25e JT |
1782 | } |
1783 | ||
1784 | /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in | |
1785 | *RAW. */ | |
1786 | ||
1787 | static int | |
b4ad899f | 1788 | i387_tag (const gdb_byte *raw) |
e750d25e JT |
1789 | { |
1790 | int integer; | |
1791 | unsigned int exponent; | |
1792 | unsigned long fraction[2]; | |
1793 | ||
1794 | integer = raw[7] & 0x80; | |
1795 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); | |
1796 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); | |
1797 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) | |
1798 | | (raw[5] << 8) | raw[4]); | |
1799 | ||
1800 | if (exponent == 0x7fff) | |
1801 | { | |
1802 | /* Special. */ | |
1803 | return (2); | |
1804 | } | |
1805 | else if (exponent == 0x0000) | |
1806 | { | |
1807 | if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer) | |
1808 | { | |
1809 | /* Zero. */ | |
1810 | return (1); | |
1811 | } | |
1812 | else | |
1813 | { | |
1814 | /* Special. */ | |
1815 | return (2); | |
1816 | } | |
1817 | } | |
1818 | else | |
1819 | { | |
1820 | if (integer) | |
1821 | { | |
1822 | /* Valid. */ | |
1823 | return (0); | |
1824 | } | |
1825 | else | |
1826 | { | |
1827 | /* Special. */ | |
1828 | return (2); | |
1829 | } | |
1830 | } | |
1831 | } | |
efb1c01c MK |
1832 | |
1833 | /* Prepare the FPU stack in REGCACHE for a function return. */ | |
1834 | ||
1835 | void | |
1836 | i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) | |
1837 | { | |
1838 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1839 | ULONGEST fstat; | |
1840 | ||
efb1c01c MK |
1841 | /* Set the top of the floating-point register stack to 7. The |
1842 | actual value doesn't really matter, but 7 is what a normal | |
1843 | function return would end up with if the program started out with | |
1844 | a freshly initialized FPU. */ | |
20a6ec49 | 1845 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
efb1c01c | 1846 | fstat |= (7 << 11); |
20a6ec49 | 1847 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
efb1c01c MK |
1848 | |
1849 | /* Mark %st(1) through %st(7) as empty. Since we set the top of the | |
1850 | floating-point register stack to 7, the appropriate value for the | |
1851 | tag word is 0x3fff. */ | |
20a6ec49 | 1852 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
efb1c01c | 1853 | |
efb1c01c | 1854 | } |
4a612d6f WT |
1855 | |
1856 | /* See i387-tdep.h. */ | |
1857 | ||
1858 | void | |
1859 | i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache) | |
1860 | { | |
1861 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1862 | ||
1863 | if (I387_BND0R_REGNUM (tdep) > 0) | |
1864 | { | |
1865 | gdb_byte bnd_buf[16]; | |
1866 | ||
1867 | memset (bnd_buf, 0, 16); | |
1868 | for (int i = 0; i < I387_NUM_BND_REGS; i++) | |
1869 | regcache_raw_write (regcache, I387_BND0R_REGNUM (tdep) + i, bnd_buf); | |
1870 | } | |
1871 | } |