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75110a6f JG |
1 | /* Target-dependent code for the i860 for GDB, the GNU debugger. |
2 | Copyright is unclear on this module!!! | |
be9a2362 | 3 | Copyright (C) 1992 Free Software Foundation, Inc. |
75110a6f | 4 | SVR4 and ELF/DWARF changes Contributed by Peggy Fieland (pfieland@stratus.com) |
be9a2362 FF |
5 | |
6 | GDB is distributed in the hope that it will be useful, but WITHOUT ANY | |
7 | WARRANTY. No author or distributor accepts responsibility to anyone | |
8 | for the consequences of using it or for whether it serves any | |
9 | particular purpose or works at all, unless he says so in writing. | |
10 | Refer to the GDB General Public License for full details. | |
11 | ||
12 | Everyone is granted permission to copy, modify and redistribute GDB, | |
13 | but only under the conditions described in the GDB General Public | |
14 | License. A copy of this license is supposed to have been given to you | |
15 | along with GDB so you can know your rights and responsibilities. It | |
16 | should be in a file named COPYING. Among other things, the copyright | |
17 | notice and this notice must be preserved on all copies. | |
18 | ||
19 | In other words, go ahead and share GDB, but don't try to stop | |
20 | anyone else from sharing it farther. Help stamp out software hoarding! | |
21 | */ | |
d747e0af | 22 | #include "defs.h" |
2213b721 FF |
23 | #include <stdlib.h> |
24 | #include <stdarg.h> | |
25 | ||
be9a2362 | 26 | |
be9a2362 FF |
27 | #include "tm-i860.h" |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "obstack.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | ||
34 | #include "tm-i860.h" | |
35 | #include "i860-opcode.h" | |
36 | ||
be9a2362 | 37 | #include "break.h" |
2213b721 | 38 | #include "command.h" |
be9a2362 FF |
39 | |
40 | #ifdef notdef | |
be9a2362 FF |
41 | #include <sys/types.h> |
42 | #include <sys/param.h> | |
43 | #include <sys/dir.h> | |
be9a2362 FF |
44 | #endif |
45 | ||
46 | #include <signal.h> | |
47 | #include <sys/ioctl.h> | |
48 | #include <fcntl.h> | |
49 | ||
50 | /* #include <sys/reg.h> */ | |
51 | #include "i860_reg.h" | |
52 | ||
53 | #include <a.out.h> | |
54 | #include <sys/file.h> | |
be9a2362 FF |
55 | #include <core.h> |
56 | ||
57 | #include <sys/user.h> | |
be9a2362 FF |
58 | #include <elf.h> |
59 | #include <sys/elftypes.h> | |
60 | #include <sys/elf_860.h> | |
61 | #include <libelf.h> | |
62 | ||
63 | ||
2213b721 FF |
64 | extern int read_memory(); |
65 | extern int write_memory(); | |
66 | extern int read_memory_integer(); | |
67 | extern int print_insn(); | |
68 | extern void bzero(); | |
69 | extern void bcopy(); | |
70 | extern int store_inferior_registers(int); | |
71 | extern int outside_startup_file(); | |
72 | ||
be9a2362 FF |
73 | int btdebug = 0; /* change value to 1 to enable debugging code */ |
74 | ||
75 | #define BTDEBUG if (btdebug) btdebug_message | |
76 | ||
2213b721 FF |
77 | extern int errno; |
78 | extern int attach_flag; | |
be9a2362 | 79 | |
2213b721 FF |
80 | #define INSTRUCTION_LENGTH 4 |
81 | #define REGISTER_LENGTH 4 | |
be9a2362 | 82 | |
2213b721 FF |
83 | /* routine to print debugging messages */ |
84 | void btdebug_message(char *format, ...) | |
be9a2362 FF |
85 | { |
86 | va_list arglist; | |
87 | va_start( arglist, format ); | |
88 | ||
89 | if( btdebug ) | |
90 | vfprintf (stderr, format, arglist ); | |
91 | va_end ( arglist ); | |
92 | } | |
93 | ||
be9a2362 FF |
94 | \f |
95 | ||
96 | /* return nonzero if the routine containing pc has been | |
97 | * compiled with -g. We assume -g if the first instruction is | |
98 | * an addu|adds -X,sp and the second is st.l fp,XX(sp) | |
99 | * | |
100 | * based on skip_prologue(); | |
101 | */ | |
102 | ||
2213b721 | 103 | static int g_routine(pc) |
be9a2362 FF |
104 | CORE_ADDR pc; |
105 | { | |
2213b721 | 106 | CORE_ADDR instr; |
be9a2362 FF |
107 | CORE_ADDR top_pc; |
108 | ||
109 | top_pc = get_pc_function_start(pc); | |
2213b721 | 110 | if (top_pc != NULL) |
be9a2362 | 111 | { |
2213b721 | 112 | instr = (unsigned)( adj_read_memory_integer (top_pc)); |
be9a2362 FF |
113 | /* Recognize "addu|adds -X,sp,sp" insn. */ |
114 | ||
115 | if ((instr & 0xEFFF0000) == 0x84420000) | |
116 | { | |
2213b721 FF |
117 | top_pc += INSTRUCTION_LENGTH; |
118 | instr = (unsigned)(adj_read_memory_integer (top_pc)); | |
be9a2362 FF |
119 | |
120 | if( (instr & 0xFFE0F801) == 0x1C401801 ) /* st.l fp,X(sp) */ | |
121 | return(1); | |
122 | } | |
123 | } | |
124 | return(0); | |
125 | } | |
126 | ||
127 | ||
2213b721 FF |
128 | /* return the stack offset where the fp register is stored */ |
129 | static int find_fp_offset(pc) | |
be9a2362 FF |
130 | CORE_ADDR pc; |
131 | { | |
2213b721 FF |
132 | int fp_off,i; |
133 | CORE_ADDR instr; | |
be9a2362 | 134 | |
2213b721 | 135 | /* look for the instruction and examine the offset */ |
be9a2362 | 136 | |
2213b721 FF |
137 | for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH){ |
138 | instr = (unsigned)(adj_read_memory_integer(pc+i)); | |
139 | if( (instr & 0xFFE0F801) == 0x1C401801) { /* st.l fp,X(sp) */ | |
140 | ||
141 | fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | | |
142 | (instr&0x000007FE)); | |
143 | return(fp_off); | |
be9a2362 | 144 | } |
2213b721 FF |
145 | } |
146 | return(0); | |
147 | } | |
148 | ||
149 | /* return the stack offset where r1 (return linkage ) register is stored */ | |
150 | static int find_r1_offset(pc) | |
151 | CORE_ADDR pc; | |
152 | { | |
153 | int r1_off,i; | |
154 | CORE_ADDR instr; | |
be9a2362 | 155 | |
2213b721 | 156 | /* look for the instruction and examine the offset */ |
be9a2362 | 157 | |
2213b721 FF |
158 | for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH){ |
159 | instr = (unsigned)( adj_read_memory_integer(pc+i)); | |
160 | if ((instr & 0xFFE0F801) == 0x1C400801) { /* st.l r1,X(sp) */ | |
161 | ||
162 | r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | | |
163 | (instr&0x000007FE)); | |
164 | return(r1_off); | |
be9a2362 | 165 | } |
2213b721 FF |
166 | } |
167 | return(-1); | |
be9a2362 FF |
168 | } |
169 | ||
2213b721 | 170 | CORE_ADDR skip_prologue(CORE_ADDR); |
be9a2362 | 171 | |
2213b721 FF |
172 | /* does routine starting at pc build a stack frame of any kind?? */ |
173 | static int has_a_frame(pc) | |
174 | CORE_ADDR pc; | |
175 | { | |
176 | if( skip_prologue(pc) != pc )return(1); | |
177 | else return(0); | |
178 | } | |
be9a2362 FF |
179 | |
180 | ||
2213b721 FF |
181 | /* written by Peggy Fieland Margaret_Fieland@vos.stratus.com |
182 | Routine to validate the return register and the frame pointer | |
183 | This routine is called when the routine we are in doesn't have a frame | |
184 | In that case, we assume that the return address and frame pointer have | |
185 | not been touched. In the following routine, we try to range check them | |
186 | to see if they are valid. */ | |
187 | ||
188 | static int valid_regs (rp, fp) | |
189 | CORE_ADDR rp, fp; | |
be9a2362 | 190 | { |
2213b721 FF |
191 | if ( ( (rp % 4) != 0) | ( (fp % 16) != 0) ) |
192 | return (0); | |
193 | else | |
194 | return (1); | |
be9a2362 FF |
195 | } |
196 | ||
be9a2362 | 197 | |
2213b721 FF |
198 | |
199 | /* get the pc and frame pointer (or sp ) | |
200 | * for the routine that called us | |
201 | * when we (this_pc) is not within a -g routine | |
202 | * if caller is non g we return sp for fp | |
203 | */ | |
be9a2362 | 204 | |
2213b721 FF |
205 | /* note this is written for Metaware version R2.1d compiler */ |
206 | /* Modified by Peggy Fieland Margaret_Fieland@vos.stratus.com */ | |
207 | static int caller_pc(this_pc,this_sp,to_pc,to_fp) | |
208 | CORE_ADDR this_pc,this_sp; | |
209 | CORE_ADDR *to_pc, *to_fp; | |
be9a2362 | 210 | { |
2213b721 FF |
211 | CORE_ADDR func_start; |
212 | int sp_offset,offset; | |
213 | CORE_ADDR sp,pc,fp,instr; | |
be9a2362 | 214 | |
2213b721 | 215 | BTDEBUG("caller_pc %x sp = %x\n",this_pc,this_sp); |
be9a2362 | 216 | |
2213b721 FF |
217 | func_start = get_pc_function_start(this_pc); |
218 | ||
219 | BTDEBUG("caller_pc func_start %x\n", func_start); | |
220 | ||
221 | if (func_start!= NULL) | |
be9a2362 FF |
222 | { |
223 | if( has_a_frame(func_start) ){ | |
224 | ||
225 | BTDEBUG("has_a_frame\n"); | |
226 | ||
227 | /* if our caller has a preamble and | |
228 | * declares space for a stack frame | |
229 | * then we must work to find our return address | |
230 | */ | |
2213b721 | 231 | instr = (unsigned)( adj_read_memory_integer (func_start)); |
be9a2362 FF |
232 | /* Recognize "addu|adds -X,sp,sp" insn. */ |
233 | ||
234 | if ((instr & 0xEFFF0000) == 0x84420000) | |
235 | sp_offset=SIGN_EXT16(instr&0x0000FFFF); | |
236 | } | |
2213b721 FF |
237 | else |
238 | { | |
239 | /* if we get here, procedure doesn't have a frame. If we didn't | |
240 | do anything weird, the frame pointer and return register have | |
241 | the values we want. Check them to see if they are valid. */ | |
242 | ||
243 | CORE_ADDR temp_rp, temp_fp; | |
244 | ||
245 | temp_rp = read_register(RP_REGNUM); | |
246 | temp_fp = read_register(FP_REGNUM); | |
247 | ||
248 | if (!valid_regs(temp_rp, temp_fp)) | |
249 | { | |
250 | printf("error frame_chain\n"); | |
251 | return(0); | |
252 | } | |
253 | BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n", | |
254 | temp_rp, temp_fp); | |
255 | *to_pc = temp_rp; | |
256 | *to_fp = temp_fp; | |
257 | return (1); | |
258 | } | |
be9a2362 FF |
259 | |
260 | BTDEBUG("sp_offset = %d %x\n",sp_offset,sp_offset); | |
261 | ||
262 | offset = find_r1_offset(func_start); | |
263 | ||
264 | if( offset < 0 ){ | |
265 | printf("cant find return address for routine at %x\n", | |
266 | func_start); | |
267 | return(0); | |
268 | } | |
2213b721 | 269 | pc = read_memory_integer(this_sp+offset,sizeof(long)); |
be9a2362 FF |
270 | sp= this_sp - sp_offset; |
271 | ||
272 | BTDEBUG("callers pc = %x sp = %x\n",pc,sp); | |
273 | ||
274 | /* our caller a -g routine ? | |
275 | * if he is we have to find his real fp | |
276 | * else provide the sp as his fp | |
277 | */ | |
278 | ||
279 | if( g_routine(pc) ){ | |
280 | ||
281 | BTDEBUG("caller_a_g\n"); | |
282 | ||
283 | if( ! (offset = find_fp_offset(func_start)) ) { | |
284 | printf("error fp_offset\n"); | |
285 | return(0); | |
286 | } | |
287 | BTDEBUG("offset = %x %d\n",offset,offset); | |
288 | ||
2213b721 | 289 | fp = read_memory_integer(this_sp+offset,sizeof(long)); |
be9a2362 FF |
290 | *to_pc = CLEAN_PC(pc); |
291 | *to_fp = fp; | |
292 | return(1); | |
293 | }else | |
294 | *to_pc = CLEAN_PC(pc); | |
295 | *to_fp = sp; | |
296 | return(1); | |
297 | } else { | |
298 | /* pc = read_register(RP_REGNUM); */ | |
2213b721 FF |
299 | /* pc = 0; */ |
300 | /* if we get here, procedure doesn't have a frame. If we didn't | |
301 | do anything weird, the frame pointer and return register have | |
302 | the values we want. Check them to see if they are valid. */ | |
303 | ||
304 | CORE_ADDR temp_rp, temp_fp; | |
305 | ||
306 | temp_rp = read_register(RP_REGNUM); | |
307 | temp_fp = read_register(FP_REGNUM); | |
308 | ||
309 | if (!valid_regs(temp_rp, temp_fp)) | |
310 | { | |
311 | printf("error frame_chain\n"); | |
312 | return(0); | |
313 | } | |
314 | BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n", | |
315 | temp_rp, temp_fp); | |
316 | *to_pc = temp_rp; | |
317 | *to_fp = temp_fp; | |
318 | return (1); | |
be9a2362 FF |
319 | } |
320 | } | |
321 | ||
2213b721 FF |
322 | /* |
323 | ** Figure out address to place next breakpoint. Avoid tricky spots, | |
324 | ** ie. delayed instruction slots etc. | |
325 | ** Need to upgrade this later to allow delayed instruction breakpoints | |
326 | ** with fix-up work done AFTER breakpoint. | |
327 | ** Note that this routine DOES deal with dual instruction mode | |
328 | */ | |
329 | #define BIM 0x8008 | |
be9a2362 | 330 | |
2213b721 FF |
331 | static branch_type |
332 | place_brk (addr, mode, brk) | |
333 | CORE_ADDR addr; | |
334 | int mode; | |
335 | struct breakpoint *brk; | |
be9a2362 | 336 | { |
2213b721 FF |
337 | CORE_ADDR instr; |
338 | CORE_ADDR nextadr, prevadr; | |
be9a2362 FF |
339 | int val = not_branch; |
340 | long offset; /* Must be signed for sign-extend */ | |
341 | extern char registers[]; | |
342 | prevadr = nextadr = 0; | |
343 | ||
344 | brk->address1 = 0; | |
345 | ||
346 | if (mode == SINGLE_STEP_MODE) | |
347 | { | |
348 | if (INDIM || ENDIM) | |
349 | { | |
2213b721 FF |
350 | nextadr = brk->address = (addr + INSTRUCTION_LENGTH*2); |
351 | instr = (unsigned)(adj_read_memory_integer ((addr + INSTRUCTION_LENGTH))); | |
be9a2362 FF |
352 | brk->mode = DIM; |
353 | } | |
354 | else | |
355 | { | |
2213b721 FF |
356 | nextadr = brk->address = (addr + INSTRUCTION_LENGTH); |
357 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
be9a2362 FF |
358 | if (STDIM) |
359 | brk->mode = DIM; | |
360 | else | |
361 | brk->mode = SIM; | |
362 | } | |
363 | ||
364 | ||
365 | /* | |
366 | ** For br/call one more sequential instruction gets executed and then we | |
367 | ** continue at the current addr + offset. We are definitely going to | |
368 | ** the dest. We are NOT allowed to place a breakpoint in the "delay" | |
369 | ** slot - (the next sequential instruction) so we only place 1 breakpoint | |
370 | ** at the destination. | |
371 | ** For the bc/bnc the next instruction executed is EITHER the next sequential | |
372 | ** or the destination of the branch, we therefore place 2 breakpoints one | |
373 | ** at each location. | |
374 | ** For the bc.t/bnc.t either 1 more sequential instruction is performed | |
375 | ** followed by a branch (like br/call) OR we skip the sequential | |
376 | ** instruction and keep going. We therefore place a breakpoint at the | |
377 | ** destination of the branch AND the second sequential instruction after | |
378 | ** the branch. Again a breakpoint is NOT allowed in the "delay slot" | |
379 | */ | |
380 | if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */ | |
381 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
382 | { | |
383 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
384 | val = uncond_d; | |
385 | else if ((instr & 0xF4000000) == 0x74000000) /* bc.t/bnc.t */ | |
386 | val = cond_d; | |
387 | else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */ | |
388 | val = cond; | |
389 | offset = (instr & 0x03ffffff); | |
390 | if (offset & 0x02000000) /*?sign extend*/ | |
391 | offset |= 0xFC000000; | |
392 | if (val == uncond_d) /* br/call*/ | |
393 | prevadr = 0; | |
394 | else if (val == cond_d) /* bc.t/bnc.t */ | |
395 | { | |
396 | if ((INDIM) && !(ENDIM)) | |
2213b721 | 397 | prevadr = nextadr + (2*INSTRUCTION_LENGTH); |
be9a2362 | 398 | else |
2213b721 | 399 | prevadr = nextadr + INSTRUCTION_LENGTH; |
be9a2362 FF |
400 | } else { /* bc /bnc */ |
401 | if ((INDIM) && !(ENDIM)) | |
402 | prevadr = nextadr; | |
403 | else | |
404 | prevadr = nextadr; | |
405 | } | |
406 | nextadr += (offset << 2); | |
407 | } | |
408 | /* | |
409 | ** We treat the bri/calli the same way as the br/call case. | |
410 | */ | |
411 | else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */ | |
412 | (instr & 0xFC000000) == 0x40000000) /* bri */ | |
413 | { | |
414 | val = uncond_d; | |
415 | offset = ((instr & 0x0000F800) >> 11); | |
416 | nextadr = (read_register(offset + R0) & 0xFFFFFFFC); | |
417 | prevadr = 0; | |
418 | } | |
419 | /* | |
420 | ** We treat the bte/btne the same way as the bc/bnc case. | |
421 | */ | |
422 | else if ((instr & 0xF0000000) == 0x50000000) /* bte/btne */ | |
423 | { | |
424 | val = cond; | |
425 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | | |
426 | (instr & 0x000007FF)); | |
427 | if ((INDIM) && !(ENDIM)) | |
428 | prevadr = nextadr; | |
429 | else | |
430 | prevadr = nextadr; | |
431 | ||
432 | nextadr += (offset << 2); | |
433 | } | |
434 | /* | |
435 | ** We treat the bte/btne the same way as the bc/bnc case. | |
436 | ** With the caveat that the 2 breakpoints may turn out to be at the same | |
437 | ** address in which case we ignore one of them. | |
438 | */ | |
439 | else if ((instr & 0xFC000000) == 0xB4000000) /* bla */ | |
440 | { | |
441 | val = cond_d; | |
442 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | | |
443 | (instr & 0x000007FF)); | |
444 | if ((INDIM) && !(ENDIM)) | |
445 | { | |
2213b721 | 446 | prevadr = nextadr + 2*INSTRUCTION_LENGTH; |
be9a2362 | 447 | } else { |
2213b721 | 448 | prevadr = nextadr + INSTRUCTION_LENGTH; |
be9a2362 FF |
449 | } |
450 | nextadr += (offset << 2); | |
451 | if (prevadr == nextadr) prevadr = 0; | |
452 | } | |
453 | } else { | |
454 | int adjust = 0; | |
455 | ||
456 | nextadr = addr; | |
457 | ||
458 | if (ISDIM(FOPADR(addr))) | |
459 | { | |
2213b721 | 460 | if (ISDIM(FOPADR(nextadr- INSTRUCTION_LENGTH*2))) |
be9a2362 | 461 | { |
2213b721 FF |
462 | instr = (unsigned)(adj_read_memory_integer(CORADR(addr |
463 | -(INSTRUCTION_LENGTH*2)))); | |
be9a2362 FF |
464 | brk->mode = DIM; |
465 | } else { | |
2213b721 | 466 | instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH)); |
be9a2362 FF |
467 | brk->mode = RIM; |
468 | } | |
469 | } else { | |
2213b721 | 470 | if (ISDIM(addr-INSTRUCTION_LENGTH)) |
be9a2362 | 471 | { |
2213b721 | 472 | instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH)); |
be9a2362 FF |
473 | brk->mode = BIM; |
474 | } else { | |
2213b721 | 475 | instr = (unsigned)(adj_read_memory_integer (addr-INSTRUCTION_LENGTH)); |
be9a2362 FF |
476 | brk->mode = SIM; |
477 | } | |
478 | } | |
479 | ||
480 | /* examine the PREVIOUS instruction to determine if we are in a branch delay | |
481 | slot. If we are, dont set a break here -- set it on the previous instruction. | |
482 | This code also accounts for dual instruction mode */ | |
483 | if ((instr & 0xE0000000) == 0x60000000 && | |
484 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
485 | { | |
2213b721 FF |
486 | adjust++; |
487 | /* br /call */ | |
488 | /* bc /bnc */ | |
489 | /* bc.t /bnc.t*/ | |
490 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
491 | printf(" Breakpoint adjusted to avoid br/call delay slot and multiple breakpoints\n"); | |
492 | ||
493 | if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */ | |
494 | printf(" Breakpoint adjusted to avoid bc.t/bnc.t delay slot and multiple breakpoints\n"); | |
495 | /* it IS really OK to set a break on the instruction AFTER the conditional branch | |
496 | -- it DOESN't have a delay slot */ | |
497 | if ((instr & 0xF4000000) == 0x70000000) /* bc / bnc */ | |
498 | /* printf(" Breakpoint adjusted to avoid bc/bnc delay slot and multiple breakpoints\n"); */ | |
499 | adjust = 0; | |
500 | } else if | |
501 | ((instr & 0xFC00003F) == 0x4C000002 || /* bri/ calli */ | |
502 | (instr & 0xFC000000) == 0x40000000) | |
503 | { | |
504 | adjust++; | |
505 | printf(" Breakpoint adjusted to avoid calli/bri delay slot and multiple breakpoints\n"); | |
506 | } else if | |
507 | ((instr & 0xF0000000) == 0x50000000) /* bte - btne */ | |
508 | { | |
509 | /* it's OK to set a break here -- we are NOT in aa branch delay slot */ | |
510 | /* | |
511 | adjust++; | |
512 | printf(" Breakpoint adjusted to avoid bte/btne multiple breakpoints\n"); | |
513 | */ | |
514 | adjust = 0; | |
515 | } else if | |
516 | ((instr & 0xFC000000) == 0xB4000000) | |
517 | { | |
518 | adjust++; | |
519 | printf(" Breakpoint adjusted to avoid bla delay slot and multiple breakpoints\n"); | |
520 | } | |
521 | if (adjust != 0) | |
522 | { | |
523 | if (brk->mode == DIM) | |
524 | { | |
525 | nextadr -= INSTRUCTION_LENGTH*2; | |
526 | nextadr = CORADR(nextadr); | |
527 | } | |
528 | else | |
529 | nextadr -= INSTRUCTION_LENGTH; | |
530 | } | |
531 | ||
532 | } | |
533 | ||
534 | if (brk->mode == RIM) | |
535 | brk->mode = DIM; | |
536 | if (brk->mode == BIM) | |
537 | brk->mode = SIM; | |
538 | ||
539 | if (nextadr != NULL) | |
540 | { | |
541 | if (brk->mode == DIM) | |
542 | { | |
543 | brk->act_addr[0] = CORADR(nextadr); | |
544 | brk->act_addr[1] = FOPADR(nextadr); | |
545 | } else { | |
546 | brk->act_addr[0] = nextadr; | |
547 | brk->act_addr[1] = 0; | |
548 | } | |
549 | } | |
550 | ||
551 | if (prevadr != NULL) | |
552 | { | |
553 | brk->address1 = prevadr; | |
554 | if (brk->mode == DIM) | |
555 | { | |
556 | brk->act_addr[2] = CORADR(prevadr); | |
557 | brk->act_addr[3] = FOPADR(prevadr); | |
558 | } else { | |
559 | brk->act_addr[2] = prevadr; | |
560 | brk->act_addr[3] = 0; | |
561 | } | |
562 | } else { | |
563 | brk->act_addr[2] = brk->act_addr[3] = 0; | |
564 | } | |
565 | return val; | |
566 | } | |
567 | ||
568 | /* This routine checks to see if r1 has been stored into the frame between | |
569 | the addresses prologue_start and prologue_end. Recognize stores of r1 | |
570 | relative to both the sp and fp registers. */ | |
571 | static int has_stored_r1(CORE_ADDR prologue_start, CORE_ADDR prologue_end) | |
572 | { | |
573 | CORE_ADDR instr; | |
574 | CORE_ADDR addr; | |
575 | ||
576 | BTDEBUG("has_stored_r1, prologue_start %x, prologue_end %x\n", | |
577 | prologue_start, prologue_end); | |
578 | ||
579 | for (addr = prologue_start; addr <= prologue_end; addr += INSTRUCTION_LENGTH) | |
580 | { | |
581 | ||
582 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
583 | if ((instr & 0xFFE0F801) == 0x1C400801 /* st.l r1,X(sp) */ | |
584 | || (instr & 0xFFE0F801) == 0x1C600801) /* st.l r1,X(fp) */ | |
585 | return (1); | |
586 | } | |
587 | return 0; | |
588 | } | |
589 | /* This is used when GDB is exiting. It gives less chance of error.*/ | |
590 | ||
591 | ||
592 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
593 | Beihl (beihl@mcc.com). */ | |
594 | /* Modified for i860 by Jim Hanko (hanko@orc.olivetti.com) */ | |
595 | ||
596 | ||
597 | static struct breakpoint brk; | |
598 | typedef char binsn_quantum[sizeof break_insn]; | |
599 | ||
600 | /* Non-zero if we just simulated a single-step ptrace call. This is | |
601 | needed because we cannot remove the breakpoints in the inferior | |
602 | process until after the `wait' in `wait_for_inferior'. Used for | |
603 | i860. */ | |
604 | ||
605 | int one_stepped; | |
606 | ||
607 | /* single_step() is called just before we want to resume the inferior, | |
608 | if we want to single-step it but there is no hardware or kernel single-step | |
609 | support. We find all the possible targets of the coming instruction and | |
610 | breakpoint them. | |
611 | ||
612 | single_step is also called just after the inferior stops. If we had | |
613 | set up a simulated single-step, we undo our damage. */ | |
614 | /* Note that we don't need the parameter, but it's dictated as part of the interface. */ | |
615 | void | |
616 | single_step (signal) | |
617 | int signal; | |
618 | { | |
619 | CORE_ADDR pc; | |
620 | branch_type place_brk(); | |
621 | ||
622 | pc = read_register (PC_REGNUM); | |
623 | ||
624 | if (!one_stepped) | |
625 | { | |
626 | brk.address = pc; | |
627 | place_brk (pc, SINGLE_STEP_MODE, &brk); | |
628 | brk.shadow_contents[0] = brk.shadow_contents[1] = 0; | |
629 | brk.shadow_contents[2] = brk.shadow_contents[3] = 0; | |
630 | ||
631 | if (brk.mode == DIM) | |
632 | { | |
633 | if (btdebug != 0) | |
634 | { | |
635 | btdebug_message(" DIM1 -> %x : ", brk.act_addr[3]); | |
636 | print_insn( brk.act_addr[3], stderr); | |
637 | btdebug_message("\t -|- %x : ", brk.act_addr[2]); | |
638 | print_insn( brk.act_addr[2], stderr); | |
639 | btdebug_message("\n"); | |
640 | } | |
641 | if (( brk.address1 != NULL)) | |
642 | { | |
643 | adj_read_memory (brk.act_addr[2], &brk.shadow_contents[2], | |
644 | INSTRUCTION_LENGTH); | |
645 | adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH); | |
646 | adj_read_memory (brk.act_addr[3], &brk.shadow_contents[3], | |
647 | INSTRUCTION_LENGTH); | |
648 | /* adj_write_memory (brk.act_addr[3], float_insn, | |
649 | INSTRUCTION_LENGTH); */ | |
650 | ||
651 | } | |
652 | if (btdebug != 0) | |
653 | { | |
654 | if ( brk.address1 != 0) | |
655 | btdebug_message(" DIM2 ->"); | |
656 | else | |
657 | btdebug_message(" DIM1 ->"); | |
658 | ||
659 | btdebug_message(" %x : ", brk.act_addr[1]); | |
660 | print_insn( brk.act_addr[1], stderr); | |
661 | btdebug_message("\t -|- %x : ", brk.act_addr[0]); | |
662 | print_insn( brk.act_addr[0], stderr); | |
663 | btdebug_message("\n"); | |
664 | } | |
665 | ||
666 | adj_read_memory (brk.act_addr[0], &brk.shadow_contents[0], | |
667 | INSTRUCTION_LENGTH); | |
668 | adj_write_memory (brk.act_addr[0], break_insn, | |
669 | INSTRUCTION_LENGTH); | |
670 | adj_read_memory (brk.act_addr[1], &brk.shadow_contents[1], | |
671 | INSTRUCTION_LENGTH); | |
672 | /* adj_write_memory (brk.act_addr[1], float_insn, | |
673 | INSTRUCTION_LENGTH); */ | |
674 | ||
675 | } | |
676 | else { | |
677 | if (brk.address1 != NULL) | |
678 | { | |
679 | if (btdebug) | |
680 | { | |
681 | btdebug_message(" SIM1 ->"); | |
682 | btdebug_message(" %x : ", brk.act_addr[2]); | |
683 | print_insn( brk.act_addr[2], stderr); | |
684 | btdebug_message("\n"); | |
685 | } | |
686 | adj_read_memory (brk.act_addr[2], &brk.shadow_contents[2], | |
687 | INSTRUCTION_LENGTH); | |
688 | adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH); | |
689 | } | |
690 | if (btdebug) | |
691 | { | |
692 | if ( brk.address1 != NULL) | |
693 | btdebug_message(" SIM2 ->"); | |
694 | else | |
695 | btdebug_message(" SIM1 ->"); | |
696 | ||
697 | btdebug_message(" %x : ", brk.act_addr[0]); | |
698 | print_insn( brk.act_addr[0], stderr); | |
699 | btdebug_message("\n"); | |
700 | } | |
701 | adj_read_memory (brk.act_addr[0], &brk.shadow_contents[0], | |
702 | INSTRUCTION_LENGTH); | |
703 | adj_write_memory (brk.act_addr[0], break_insn,INSTRUCTION_LENGTH); | |
704 | } | |
705 | ||
706 | /* Let it go */ | |
707 | one_stepped = 1; | |
708 | return; | |
709 | } | |
710 | else | |
711 | { | |
712 | /* Remove breakpoints */ | |
713 | if (brk.mode == DIM) | |
714 | { | |
715 | adj_write_memory (brk.act_addr[0], &brk.shadow_contents[0], | |
716 | INSTRUCTION_LENGTH); | |
717 | adj_write_memory (brk.act_addr[1], &brk.shadow_contents[1], | |
718 | INSTRUCTION_LENGTH); | |
719 | } else { | |
720 | adj_write_memory (brk.act_addr[0], &brk.shadow_contents[0], | |
721 | INSTRUCTION_LENGTH); | |
722 | } | |
723 | ||
724 | if (brk.address1 != NULL) | |
725 | { | |
726 | if (brk.mode == DIM) | |
727 | { | |
728 | adj_write_memory (brk.act_addr[2], &brk.shadow_contents[2], | |
729 | INSTRUCTION_LENGTH); | |
730 | adj_write_memory (brk.act_addr[3], &brk.shadow_contents[3], | |
731 | INSTRUCTION_LENGTH); | |
732 | } else { | |
733 | adj_write_memory (brk.act_addr[2], &brk.shadow_contents[2], | |
734 | INSTRUCTION_LENGTH); | |
735 | } | |
736 | } | |
737 | one_stepped = 0; | |
738 | } | |
739 | } | |
740 | ||
741 | ||
742 | ||
743 | /* Written for i860 by Jim Hanko (hanko@orc.olivetti.com) */ | |
744 | /* This code was based on SPARC code written by Gary Beihl (beihl@mcc.com), | |
745 | by Michael Tiemann (tiemann@corto.inria.fr). */ | |
746 | /* This routine returns the first memory address following the prologue code, | |
747 | if there is a prologue. */ | |
748 | ||
749 | struct command_line *get_breakpoint_commands (); | |
750 | ||
751 | CORE_ADDR | |
752 | skip_prologue (pc) | |
753 | CORE_ADDR pc; | |
754 | { | |
755 | CORE_ADDR instr; | |
756 | int regno; | |
757 | ||
758 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
759 | ||
760 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
761 | if ((instr & 0xEFFF0000) == 0x84420000) | |
762 | { | |
763 | pc += INSTRUCTION_LENGTH; | |
764 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
765 | } | |
766 | else | |
767 | return(pc); /* No frame! */ | |
768 | ||
769 | /* Recognize store of return addr and frame pointer into frame */ | |
770 | for (; ;) | |
771 | { | |
772 | if ((instr & 0xFFE0F801) == 0x1C400801 || /* st.l r1,X(sp) */ | |
773 | (instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */ | |
774 | { | |
775 | pc += INSTRUCTION_LENGTH; | |
776 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
777 | } | |
778 | else | |
779 | break; | |
780 | } | |
781 | ||
782 | /* Recognize "addu|adds X,sp,fp" insn. */ | |
783 | if ((instr & 0xEFFF0000) == 0x84430000) | |
784 | { | |
785 | pc += INSTRUCTION_LENGTH; | |
786 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
787 | } | |
788 | ||
789 | /* Now recognize stores into the frame from the registers. */ | |
790 | ||
791 | for (; ;) | |
792 | { | |
793 | if ((instr & 0xFFA00003) == 0x1C200001 || /* st.l rn,X(fp|sp) */ | |
794 | (instr & 0xFFA00001) == 0x4C200000) /* fst.y fn,X(fp|sp) */ | |
795 | { | |
796 | regno = (instr >> 11) & 0x1f; | |
797 | if (regno == 0) /* source reg == 0? quit */ | |
798 | break; | |
799 | pc += INSTRUCTION_LENGTH; | |
800 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
801 | } | |
802 | else | |
803 | break; | |
804 | } | |
805 | ||
806 | return(pc); | |
807 | } | |
808 | ||
809 | #if 0 | |
810 | /* This routine is uncalled. Remove it sometime. */ | |
811 | /* Set *nextpc to branch target if we find a branch. If it is not a branch, | |
812 | set it to the next instruction (addr + 4) */ | |
813 | ||
814 | ||
815 | branch_type | |
816 | isabranch (addr, nextpc) | |
817 | CORE_ADDR addr, *nextpc; | |
818 | { | |
819 | CORE_ADDR instr; | |
820 | branch_type val = not_branch; | |
821 | long offset; /* Must be signed for sign-extend */ | |
822 | ||
823 | BTDEBUG(" isabranch\n"); | |
824 | *nextpc = addr; | |
825 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
826 | ||
827 | if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */ | |
828 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
829 | { | |
830 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
831 | val = uncond_d; | |
832 | else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */ | |
833 | val = cond_d; | |
834 | else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */ | |
835 | val = cond; | |
836 | ||
837 | offset = (instr & 0x03ffffff); | |
838 | if (offset & 0x02000000) /* sign extend? */ | |
839 | offset |= 0xFC000000; | |
840 | *nextpc = addr + 4 + (offset << 2); | |
841 | } | |
842 | else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */ | |
843 | (instr & 0xFC000000) == 0x40000000) /* bri */ | |
844 | { | |
845 | val = uncond_d; | |
846 | offset = ((instr & 0x0000F800) >> 11); | |
847 | *nextpc = (read_register(offset) & 0xFFFFFFFC); | |
848 | } | |
849 | else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */ | |
850 | { | |
851 | val = cond; | |
852 | ||
853 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
854 | *nextpc = addr + 4 + (offset << 2); | |
855 | } | |
856 | else if ((instr & 0xFC000000) == 0xB4000000) /* bla */ | |
857 | { | |
858 | val = cond_d; | |
859 | ||
860 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
861 | *nextpc = addr + 4 + (offset << 2); | |
862 | } | |
863 | ||
864 | BTDEBUG(" Final addr - %x\n", *nextpc); | |
865 | /*BTDEBUG("isabranch ret: %d\n",val); */ | |
866 | return val; | |
867 | } | |
868 | #endif | |
869 | ||
870 | /* set in call_function() [valops.c] to the address of the "call dummy" code | |
871 | so dummy frames can be easily recognized; also used in wait_for_inferior() | |
872 | [infrun.c]. When not used, it points into the ABI's 'reserved area' */ | |
873 | ||
874 | CORE_ADDR call_dummy_set = 0; /* true if dummy call being done */ | |
875 | CORE_ADDR call_dummy_start; /* address of call dummy code */ | |
876 | ||
877 | /* this routine routine gets the values of the registers stored in the frame | |
878 | and stores their values into the frame_saved_regs structure. */ | |
879 | ||
880 | void | |
881 | frame_find_saved_regs(frame_info, frame_saved_regs) | |
882 | struct frame_info *frame_info; | |
883 | struct frame_saved_regs *frame_saved_regs; | |
884 | { | |
885 | register CORE_ADDR pc; | |
886 | CORE_ADDR instr; | |
887 | long offset, spdelta = 0; | |
888 | int i, size, reg; | |
889 | int r1_off = -1, fp_off = -1; | |
890 | int framesize; | |
891 | ||
892 | bzero (frame_saved_regs, sizeof(*frame_saved_regs)); | |
893 | ||
894 | if (call_dummy_set && frame_info->pc >= call_dummy_start && | |
895 | frame_info->pc <= call_dummy_start + CALL_DUMMY_LENGTH) | |
896 | { | |
897 | /* DUMMY frame - all registers stored in order at fp; old sp is | |
898 | at fp + NUM_REGS*4 */ | |
899 | ||
900 | for (i = 1; i < NUM_REGS; i++) /* skip reg 0 */ | |
901 | if (i != SP_REGNUM && i != FP0_REGNUM && i != FP0_REGNUM + 1) | |
902 | /* the register numbers used in the instruction and the ones used to index | |
903 | the regs array are not the same -- compensate */ | |
904 | frame_saved_regs->regs[i+R0] = frame_info->frame + i*REGISTER_LENGTH; | |
905 | ||
906 | frame_saved_regs->regs[SP_REGNUM] = frame_info->frame + NUM_REGS*REGISTER_LENGTH; | |
907 | ||
908 | call_dummy_set = 0; | |
909 | return; | |
910 | } | |
911 | ||
912 | pc = get_pc_function_start (frame_info->pc); | |
913 | if (pc != NULL) | |
914 | { | |
915 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
916 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
917 | if ((instr & 0xEFFF0000) == 0x84420000) | |
918 | { | |
919 | framesize = -SIGN_EXT16(instr & 0x0000FFFF); | |
920 | pc += INSTRUCTION_LENGTH; | |
921 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
922 | } | |
923 | } | |
924 | else | |
925 | goto punt; /* No frame! */ | |
926 | ||
927 | /* Recognize store of return addr and frame pointer into frame */ | |
928 | for (; ;) | |
929 | { | |
930 | if ((instr & 0xFFE0F801) == 0x1C400801) /* st.l r1,X(sp) */ | |
931 | { | |
932 | r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE)); | |
933 | pc += INSTRUCTION_LENGTH; | |
934 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
935 | } | |
936 | else if ((instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */ | |
937 | { | |
938 | fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE)); | |
939 | pc += INSTRUCTION_LENGTH; | |
940 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
941 | } | |
942 | else | |
943 | break; | |
944 | } | |
945 | ||
946 | /* Recognize "addu|adds X,sp,fp" insn. */ | |
947 | if ((instr & 0xEFFF0000) == 0x84430000) | |
948 | { | |
949 | spdelta = SIGN_EXT16(instr & 0x0000FFFF); | |
950 | pc += INSTRUCTION_LENGTH; | |
951 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
952 | } | |
953 | ||
954 | /* Now recognize stores into the frame from the registers. */ | |
955 | ||
956 | for (; ;) | |
957 | { | |
958 | if ((instr & 0xFFC00003) == 0x1C400001) /* st.l rn,X(fp|sp) */ | |
959 | { | |
960 | offset = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE)); | |
961 | reg = (instr >> 11) & 0x1F; | |
962 | if (reg == 0) | |
963 | break; | |
964 | if ((instr & 0x00200000) == 0) /* was this using sp? */ | |
965 | if (spdelta != 0) /* and we know sp-fp delta */ | |
966 | offset -= spdelta; /* if so, adjust the offset */ | |
967 | else | |
968 | break; /* if not, give up */ | |
969 | ||
970 | ||
971 | /* Handle the case where the return address is stored after the fp | |
972 | is adjusted */ | |
973 | ||
974 | if (reg == 1) | |
975 | frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + offset; | |
976 | else | |
977 | frame_saved_regs->regs[reg+R0] = frame_info->frame + offset; | |
978 | ||
979 | pc += INSTRUCTION_LENGTH; | |
980 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
981 | } | |
982 | else if ((instr & 0xFFC00001) == 0x2C400000) /* fst.y fn,X(fp|sp) */ | |
983 | { | |
984 | /* | |
985 | * The number of words in a floating store based on 3 LSB of instr | |
986 | */ | |
987 | static int fst_sizes[] = {2, 0, 1, 0, 4, 0, 1, 0}; | |
988 | ||
989 | size = fst_sizes[instr & 7]; | |
990 | reg = ((instr >> 16) & 0x1F) + FP0_REGNUM; | |
991 | if (reg == 0) | |
992 | break; | |
993 | ||
994 | if (size > 1) /* align the offset */ | |
995 | offset = SIGN_EXT16(instr & 0x0000FFF8); /* drop 3 bits */ | |
996 | else | |
997 | offset = SIGN_EXT16(instr & 0x0000FFFC); /* drop 2 bits */ | |
998 | ||
999 | if ((instr & 0x00200000) == 0) /* was this using sp? */ | |
1000 | if (spdelta != 0) /* and we know sp-fp delta */ | |
1001 | offset -= spdelta; /* if so, adjust the offset */ | |
1002 | else | |
1003 | break; /* if not, give up */ | |
1004 | ||
1005 | for (i = 0; i < size; i++) | |
1006 | { | |
1007 | frame_saved_regs->regs[reg] = frame_info->frame + offset; | |
1008 | ||
1009 | offset += REGISTER_LENGTH; | |
1010 | reg++; | |
1011 | } | |
1012 | ||
1013 | pc += INSTRUCTION_LENGTH; | |
1014 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1015 | } | |
1016 | else | |
1017 | break; | |
1018 | } | |
1019 | ||
1020 | punt: ; | |
1021 | if (framesize != 0 && spdelta != 0) | |
1022 | frame_saved_regs->regs[SP_REGNUM] = frame_info->frame+(framesize-spdelta); | |
1023 | else | |
1024 | frame_saved_regs->regs[SP_REGNUM] = frame_info->frame + 8; | |
1025 | ||
1026 | if ((spdelta != 0) && fp_off != -1) | |
1027 | frame_saved_regs->regs[FP_REGNUM] = frame_info->frame - spdelta + fp_off; | |
1028 | else | |
1029 | frame_saved_regs->regs[FP_REGNUM] = frame_info->frame; | |
1030 | ||
1031 | if ((spdelta != 0) && r1_off != -1) | |
1032 | frame_saved_regs->regs[PC_REGNUM] = frame_info->frame - spdelta + r1_off; | |
1033 | else | |
1034 | frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + 4; | |
1035 | } | |
1036 | ||
1037 | ||
1038 | /* get the frame pointer of the caller. | |
1039 | * note that only routines that have been compiled with | |
1040 | * -g have full (XX)fp style stack frames | |
1041 | * if we are not returning to a non -g caller then we | |
1042 | * return the sp at entry to us as it is the caller's | |
1043 | * frame reference. | |
1044 | */ | |
1045 | ||
1046 | frame_chain(thisframe) | |
1047 | FRAME thisframe; | |
1048 | { | |
1049 | CORE_ADDR fp, pc; | |
1050 | CORE_ADDR func_start; | |
1051 | CORE_ADDR instr; | |
1052 | int offset; | |
1053 | CORE_ADDR thisfp = thisframe->frame; | |
1054 | ||
1055 | /* get the frame pointer actually sp for a non -g | |
1056 | * for the routine that called us routine | |
1057 | */ | |
1058 | ||
1059 | BTDEBUG("FRAME_CHAIN(%x)\n",thisframe); | |
1060 | ||
1061 | if ( !read_memory_integer (thisframe->frame,sizeof(long)) ) | |
1062 | { | |
1063 | return (0); | |
1064 | } | |
1065 | ||
1066 | if( ! g_routine(thisframe->pc) ){ | |
1067 | BTDEBUG( "non g at %x\n",thisframe->pc); | |
1068 | caller_pc(thisframe->pc,thisframe->sp,&pc,&fp); | |
1069 | BTDEBUG("caller_pc returned %x %x \n",pc,fp); | |
1070 | return(fp); | |
1071 | ||
1072 | }/* else a -g routine */ | |
1073 | ||
1074 | ||
1075 | fp = read_memory_integer (thisfp, sizeof(long)); | |
1076 | ||
1077 | if (fp < thisfp || fp > (unsigned) STACK_END_ADDR) | |
1078 | { | |
1079 | /* handle the Metaware-type pseudo-frame */ | |
1080 | ||
1081 | func_start = get_pc_function_start(thisframe->pc); | |
1082 | ||
1083 | if (func_start != NULL) | |
1084 | { | |
1085 | ||
1086 | instr = (unsigned)(adj_read_memory_integer (func_start)); | |
1087 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
1088 | if ((instr & 0xEFFF0000) == 0x84420000) | |
1089 | offset = SIGN_EXT16(instr & 0x0000FFFF); | |
be9a2362 | 1090 | |
be9a2362 FF |
1091 | } |
1092 | ||
2213b721 FF |
1093 | fp = 0; |
1094 | if (offset < 0) | |
1095 | fp = thisfp - offset; | |
be9a2362 | 1096 | } |
2213b721 FF |
1097 | BTDEBUG("frame_chain returned %d\n",fp); |
1098 | return(fp); | |
1099 | } | |
1100 | ||
1101 | /* This function returns 1 if there is no stored r1, 0 otherwise. | |
1102 | The function returns 1 if the pc is in a function prologue, | |
1103 | or the function prologue didn't save the return pointer in | |
1104 | the stack frame, 0 otherwise */ | |
1105 | ||
1106 | int no_stored_rp(CORE_ADDR pc) | |
1107 | { | |
1108 | CORE_ADDR func_start, prologue_end; | |
be9a2362 | 1109 | |
2213b721 FF |
1110 | func_start = get_pc_function_start(pc); |
1111 | if (func_start != NULL) | |
be9a2362 | 1112 | { |
2213b721 FF |
1113 | prologue_end = func_start; |
1114 | SKIP_PROLOGUE(prologue_end); | |
1115 | if ( (pc >= func_start) && (pc <= prologue_end)) | |
be9a2362 | 1116 | { |
2213b721 FF |
1117 | BTDEBUG("no_stored_rp: pc %x is in prologue \n",pc); |
1118 | return 1; | |
1119 | } | |
1120 | /* otherwise, see if the entry sequence stored the return pointer. | |
1121 | If it didn't, return 1 */ | |
1122 | /* Some procedures , at least, store the return pointer AFTER | |
1123 | the prologue sequence, so check for stores from function start to | |
1124 | present pc value. */ | |
1125 | if (!has_stored_r1(func_start, pc)) | |
1126 | { | |
1127 | BTDEBUG("no_stored_rp, for pc %x, prologue didn't store r1\n",pc); | |
1128 | return 1; | |
be9a2362 FF |
1129 | } |
1130 | } | |
2213b721 FF |
1131 | BTDEBUG("no_stored_rp for pc %x return pointer was stored \n", pc); |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | /* get the PC of the caller */ | |
1137 | CORE_ADDR frame_saved_pc(frame_struct) | |
1138 | FRAME frame_struct; | |
1139 | { | |
1140 | CORE_ADDR frame; | |
1141 | CORE_ADDR pc; | |
1142 | CORE_ADDR pc1; | |
1143 | CORE_ADDR sp ; | |
1144 | CORE_ADDR fp; | |
1145 | ||
1146 | frame = frame_struct->frame; | |
1147 | pc = frame_struct->pc; | |
1148 | sp = frame_struct->sp; | |
1149 | ||
1150 | BTDEBUG("frame_saved_pc input: frame %x, pc %x", | |
1151 | frame, pc); | |
1152 | ||
1153 | /* First see if this is the current frame. If it is, return the value in r1, | |
1154 | as it may not have been stored */ | |
1155 | ||
1156 | fp = read_register(FP_REGNUM); | |
1157 | ||
1158 | /* check to see if we are in an entry sequence, where the return pointer has not yet been stored */ | |
1159 | if (fp == frame && no_stored_rp(pc)) | |
1160 | { | |
1161 | pc = read_register(RP_REGNUM); | |
1162 | frame_struct->rp = pc; | |
1163 | } | |
1164 | else if( ! g_routine(pc) ) | |
1165 | { | |
1166 | caller_pc(pc,sp,&pc,&frame); | |
1167 | } | |
1168 | else | |
1169 | { | |
1170 | ||
1171 | pc = read_memory_integer (frame + 4, sizeof(long)); | |
1172 | ||
1173 | if (!outside_startup_file(pc)) | |
1174 | { | |
1175 | ||
1176 | BTDEBUG("pc %x outside startup file \n",pc); | |
1177 | ||
1178 | pc1 = read_memory_integer (frame, sizeof(long)); | |
1179 | ||
1180 | if (outside_startup_file(pc1)) | |
1181 | pc = pc1; | |
1182 | else | |
1183 | pc = 0; | |
1184 | } | |
1185 | } | |
1186 | BTDEBUG(" returning pc %x\n", CLEAN_PC(pc)); | |
1187 | return(CLEAN_PC(pc)); | |
1188 | ||
1189 | } | |
1190 | ||
1191 | /* Pass arguments to a function in the inferior process - ABI compliant | |
1192 | Note that this routine DOES NOT HANDLE memory argument lists, ie | |
1193 | it gives up if there are too many arguments to pass in registers.*/ | |
1194 | ||
1195 | void | |
1196 | pass_function_arguments(args, nargs, struct_return) | |
1197 | value *args; | |
1198 | int nargs; | |
1199 | int struct_return; | |
1200 | { | |
1201 | int ireg = (struct_return) ? 17 : 16; | |
1202 | int freg = FP0_REGNUM + 8; | |
1203 | int i; | |
1204 | struct type *type; | |
1205 | value arg; | |
1206 | long tmp; | |
1207 | value value_arg_coerce(); | |
be9a2362 | 1208 | |
2213b721 FF |
1209 | |
1210 | for (i = 0; i < nargs; i++) | |
be9a2362 | 1211 | { |
2213b721 FF |
1212 | arg = value_arg_coerce(args[i]); |
1213 | type = VALUE_TYPE(arg); | |
1214 | if (type == builtin_type_double) | |
be9a2362 | 1215 | { |
2213b721 FF |
1216 | write_register_bytes(REGISTER_BYTE(freg), VALUE_CONTENTS(arg), sizeof(double)); |
1217 | freg += 2; | |
1218 | } | |
1219 | else | |
1220 | { | |
1221 | bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long)); | |
1222 | write_register(ireg, tmp); | |
1223 | ireg++; | |
be9a2362 | 1224 | } |
be9a2362 | 1225 | } |
2213b721 FF |
1226 | if (ireg >= 28 || freg >= FP0_REGNUM + 16) |
1227 | error("Too many arguments to function"); | |
1228 | } | |
1229 | ||
1230 | ||
1231 | #define SPACES " " | |
1232 | #define P_SPACES " " | |
1233 | #define BYTE 0xff | |
1234 | ||
1235 | int screen_lines=24; | |
1236 | ||
1237 | char *spec_reg[] = { | |
1238 | "fsr", "db", "dirbase", "fir", "psr", "epsr", | |
1239 | }; | |
1240 | ||
1241 | char *doro_reg[] = { | |
1242 | "scp", "cbsp", "pt_cs", "intmsk", "intack", | |
1243 | }; | |
1244 | #define NREGS 32 | |
1245 | ||
1246 | #if 0 | |
1247 | /* This routine is uncalled -- remove this routine sometime */ | |
1248 | get_reg(regno) | |
1249 | { | |
1250 | char raw_buffer[32]; | |
1251 | int addr; | |
1252 | int virtual_buffer; | |
1253 | ||
1254 | read_relative_register_raw_bytes (regno, raw_buffer); | |
1255 | REGISTER_CONVERT_TO_VIRTUAL (addr, raw_buffer, &virtual_buffer); | |
1256 | return(virtual_buffer); | |
be9a2362 | 1257 | } |
2213b721 FF |
1258 | #endif |
1259 | ||
1260 | ||
1261 | #if 0 | |
1262 | /* This routine is uncalled. Remove it sometime. */ | |
be9a2362 FF |
1263 | |
1264 | /* | |
1265 | ** Figure out whether we are in a delayed slot and if so then take necessary | |
1266 | ** action to resume properly - remember trap pre-empts instruction | |
1267 | */ | |
1268 | int | |
1269 | wasabranch (addr, nextpc, ss) | |
1270 | CORE_ADDR addr, *nextpc; | |
1271 | int ss; | |
1272 | { | |
2213b721 | 1273 | CORE_ADDR nextadr, instr; |
be9a2362 FF |
1274 | int val = not_branch; |
1275 | long offset; /* Must be signed for sign-extend */ | |
1276 | ||
1277 | if (ss) | |
1278 | { | |
1279 | if (INDIM) | |
1280 | { | |
2213b721 FF |
1281 | nextadr = CORADR((int)(addr + INSTRUCTION_LENGTH*2)); |
1282 | instr = (unsigned)(adj_read_memory_integer (CORADR(addr))); | |
be9a2362 FF |
1283 | } |
1284 | else | |
1285 | { | |
2213b721 FF |
1286 | nextadr = addr + INSTRUCTION_LENGTH; |
1287 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
be9a2362 FF |
1288 | } |
1289 | } else { | |
1290 | if (ISDIM(addr)) | |
1291 | { | |
1292 | nextadr = CORADR(addr); | |
2213b721 | 1293 | instr = (unsigned)(adj_read_memory_integer (nextadr)); |
be9a2362 FF |
1294 | } |
1295 | else | |
1296 | { | |
1297 | nextadr = addr; | |
2213b721 | 1298 | instr = (unsigned)(adj_read_memory_integer (addr)); |
be9a2362 FF |
1299 | } |
1300 | } | |
1301 | ||
1302 | ||
1303 | if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */ | |
1304 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
1305 | { | |
1306 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
1307 | val = uncond_d; | |
1308 | else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */ | |
1309 | val = cond_d; | |
1310 | else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */ | |
1311 | val = cond; | |
1312 | ||
1313 | offset = (instr & 0x03ffffff); | |
1314 | if (offset & 0x02000000) /* sign extend? */ | |
1315 | offset |= 0xFC000000; | |
1316 | nextadr += (offset << 2); | |
1317 | } | |
1318 | else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */ | |
1319 | (instr & 0xFC000000) == 0x40000000) /* bri */ | |
1320 | { | |
1321 | if (ss) | |
1322 | { | |
1323 | val = uncond_d; | |
1324 | offset = ((instr & 0x0000F800) >> 11); | |
1325 | nextadr = (read_register(offset) & 0xFFFFFFFC); | |
1326 | } else { | |
1327 | val = uncond_d; | |
1328 | } | |
1329 | } | |
1330 | else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */ | |
1331 | { | |
1332 | val = cond; | |
1333 | ||
1334 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
1335 | nextadr += (offset << 2); | |
1336 | } | |
1337 | else if ((instr & 0xFC000000) == 0xB4000000) /* bla */ | |
1338 | { | |
1339 | val = cond_d; | |
1340 | ||
1341 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
1342 | nextadr += (offset << 2); | |
1343 | } | |
1344 | ||
1345 | *nextpc = nextadr; | |
1346 | return val; | |
1347 | } | |
2213b721 | 1348 | #endif |
be9a2362 FF |
1349 | |
1350 | extern char registers[]; | |
1351 | ||
2213b721 FF |
1352 | /* i860-specific routine to print the register set. Note that we ALWAYS print information |
1353 | on the floating point registers, so we ignore the parameter fpregs */ | |
1354 | void i860_do_registers_info(regnum,fpregs) | |
be9a2362 FF |
1355 | int regnum; |
1356 | int fpregs; | |
1357 | { | |
1358 | register int i; | |
1359 | unsigned int val; | |
1360 | unsigned int j,k; | |
1361 | ||
2213b721 | 1362 | |
be9a2362 FF |
1363 | if (regnum == -1) |
1364 | printf_filtered ( | |
1365 | "Register Contents (relative to selected stack frame)\n\n"); | |
1366 | ||
1367 | if (regnum != -1) /* print one register */ | |
1368 | { | |
1369 | if ((regnum >=F0 ) && (regnum <= F31)) | |
1370 | bcopy (®isters[ADJ_FREG(regnum)<<2], &val, sizeof (long)); | |
1371 | else | |
1372 | bcopy (®isters[regnum<<2], &val, sizeof (long)); | |
1373 | printf("%-4s 0x%08x\t", reg_names[regnum], val); | |
1374 | printf("\n\t"); fflush(stdout); | |
1375 | } | |
1376 | else /* print all registers */ | |
1377 | { | |
1378 | ||
1379 | printf("\n Control/Status Registers :- \n\t"); | |
1380 | for (j=0; j<=DB; j++) | |
1381 | { | |
1382 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1383 | printf("%-4s 0x%08x\t", reg_names[j], val); | |
1384 | } | |
1385 | printf("\n\t"); fflush(stdout); | |
1386 | ||
1387 | /* EPSR */ | |
1388 | bcopy (®isters[EPSR<<2], &val, sizeof (long)); | |
1389 | printf("%-4s 0x%08x\t", reg_names[EPSR], val); | |
1390 | ||
1391 | /* FSR */ | |
1392 | bcopy (®isters[FSR<<2], &val, sizeof (long)); | |
1393 | printf("%-4s 0x%08x\t", reg_names[FSR], val); | |
1394 | ||
1395 | /* CCR */ | |
1396 | bcopy (®isters[CCR<<2], &val, sizeof (long)); | |
1397 | printf("%-4s 0x%08x\t", reg_names[CCR], val); | |
1398 | /* BEAR*/ | |
1399 | bcopy (®isters[BEAR<<2], &val, sizeof (long)); | |
1400 | printf("%-4s 0x%08x\t", reg_names[BEAR], val); | |
1401 | ||
1402 | ||
1403 | #ifdef JIM_ADD_PRIV | |
1404 | for (j=P0; j<=P3; j++) | |
1405 | { | |
1406 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1407 | printf("%-4s 0x%08x\t", reg_names[j], val); | |
1408 | } | |
1409 | #endif | |
1410 | ||
1411 | printf("\n Integer Registers :- \n\t"); | |
1412 | for (j=R0; j<=R31; j++) | |
1413 | { | |
2213b721 | 1414 | if (j != IREGS && (j % REGISTER_LENGTH == 0)) |
be9a2362 FF |
1415 | { |
1416 | printf("\n\t"); fflush(stdout); | |
1417 | } | |
1418 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1419 | printf("%-4s 0x%08x\t", reg_names[j], val); | |
1420 | } | |
1421 | ||
1422 | printf("\n Floating Registers :- \n\t"); | |
1423 | for (j=F0; j<=F31; j++) | |
1424 | { | |
2213b721 | 1425 | if (j != FREGS && (j % REGISTER_LENGTH == 0)) |
be9a2362 FF |
1426 | { |
1427 | printf("\n\t"); fflush(stdout); | |
1428 | } | |
1429 | bcopy (®isters[ADJ_FREG(j)<<2], &val, sizeof (long)); | |
1430 | printf("%-4s 0x%08x\t", reg_names[j], val); | |
1431 | } | |
1432 | ||
1433 | printf("\n Special Registers :- \n\t"); | |
1434 | for (j=SPC_KI; j<=SPC_MERGE; j+=2) | |
1435 | { | |
1436 | unsigned int valh; | |
1437 | if (j == SPC_T) | |
1438 | { | |
1439 | printf("\n\t"); fflush(stdout); | |
1440 | } | |
1441 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1442 | bcopy (®isters[(j+1)<<2], &valh, sizeof (long)); | |
1443 | printf("%-6s 0x%08x %08x\t", reg_names[j], val,valh); | |
1444 | } | |
1445 | ||
1446 | printf("\n Graphics Pipeline :- \n"); | |
1447 | { | |
2213b721 | 1448 | unsigned int valh; |
be9a2362 FF |
1449 | j = PSV_I1; |
1450 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1451 | bcopy (®isters[(j+1)<<2], &valh, sizeof (long)); | |
1452 | printf("\t\t\t%-8s 0x%08x %08x \n", reg_names[j], val,valh); | |
1453 | } | |
1454 | ||
1455 | printf(" Memory Load Pipeline :- \n"); | |
2213b721 | 1456 | for (j=PSV_L1; j<=PSV_L3; j+=REGISTER_LENGTH) |
be9a2362 FF |
1457 | { |
1458 | unsigned int valh, val2,val3; | |
1459 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1460 | bcopy (®isters[(j+1)<<2], &valh, sizeof (long)); | |
1461 | bcopy (®isters[(j+2)<<2], &val2, sizeof (long)); | |
1462 | bcopy (®isters[(j+3)<<2], &val3, sizeof (long)); | |
1463 | printf("\t\t%-8s 0x%08x %08x %08x %08x\n", reg_names[j], | |
1464 | val,valh,val2,val3); | |
1465 | } | |
1466 | ||
1467 | printf("\n Adder Pipeline :-\t\tMultiplier Pipeline :-\t\tFSR results :-\n"); | |
1468 | for (i=PSV_FSR1,j=PSV_A1,k=PSV_M1; j<=PSV_A3; i++,j+=2,k+=2) | |
1469 | { | |
1470 | unsigned int valh,val2,val3,val4; | |
1471 | bcopy (®isters[i<<2], &val4, sizeof (long)); | |
1472 | bcopy (®isters[j<<2], &val, sizeof (long)); | |
1473 | bcopy (®isters[(j+1)<<2], &valh, sizeof (long)); | |
1474 | bcopy (®isters[k<<2], &val2, sizeof (long)); | |
1475 | bcopy (®isters[(k+1)<<2], &val3, sizeof (long)); | |
1476 | printf(" %-4s 0x%08x %08x\t", reg_names[j], val,valh); | |
1477 | printf("%-4s 0x%08x %08x\t", reg_names[k], val2,val3); | |
1478 | printf("%-4s 0x%08x\n", reg_names[i], val4); | |
1479 | } | |
1480 | ||
1481 | } | |
1482 | ||
1483 | ||
1484 | } | |
1485 | ||
be9a2362 | 1486 | |
be9a2362 FF |
1487 | |
1488 | /* The following set of routines was adapted from existing code previously | |
1489 | in an i860-specific version of breakpoint.c by Peggy Fieland | |
1490 | (Margaret_Fieland@vos.stratus.com) */ | |
2213b721 FF |
1491 | /* routines to set a data breakpoint by setting the value in the DB register. |
1492 | Note that "hitting" the breakpoint will generate a data access trap. We | |
1493 | do not have a special trap handler. */ | |
be9a2362 FF |
1494 | unsigned int dbrkval, dbrkmod; |
1495 | void i860_dbrk_breakpoint() | |
1496 | { | |
1497 | BTDEBUG("i860_dbrk_breakpoint was called , dbrkval %x\n", dbrkval); | |
1498 | ||
2213b721 | 1499 | if (dbrkval != 0) |
be9a2362 FF |
1500 | { |
1501 | *(int *)®isters[DB<<2] = dbrkval; | |
1502 | } | |
1503 | else | |
1504 | { | |
1505 | *(int *)®isters[DB<<2] = 0; | |
1506 | } | |
1507 | ||
1508 | *(int *)®isters[PSR<<2] &= ~3; | |
1509 | *(int *)®isters[PSR<<2] |= dbrkmod; | |
1510 | ||
1511 | store_inferior_registers(DB); | |
1512 | store_inferior_registers(PSR); | |
1513 | ||
1514 | } | |
1515 | ||
2213b721 | 1516 | /* set a "read" data breakpoint. */ |
be9a2362 FF |
1517 | void |
1518 | d_ro_break_command(arg) | |
1519 | char *arg; | |
1520 | { | |
1521 | dbrkval = strtoul(arg, NULL, 0); | |
1522 | dbrkmod = 0x01; | |
2213b721 | 1523 | BTDEBUG(" ro_dbreak - %x %x\n", dbrkval, dbrkmod); |
be9a2362 FF |
1524 | } |
1525 | ||
2213b721 | 1526 | /* set a "write" data breakpoint. */ |
be9a2362 FF |
1527 | void |
1528 | d_wo_break_command(arg) | |
1529 | char *arg; | |
1530 | { | |
1531 | dbrkval = strtoul(arg, NULL, 0); | |
1532 | dbrkmod = 0x02; | |
2213b721 | 1533 | BTDEBUG(" wo_dbreak - %x %x\n", dbrkval, dbrkmod); |
be9a2362 FF |
1534 | } |
1535 | ||
2213b721 | 1536 | /* set a "read/write" data breakpoint. */ |
be9a2362 FF |
1537 | void |
1538 | d_rw_break_command(arg) | |
1539 | char *arg; | |
1540 | { | |
1541 | dbrkval = strtoul(arg, NULL, 0); | |
1542 | dbrkmod = 0x03; | |
2213b721 | 1543 | BTDEBUG(" rw_dbreak - %x %x\n", dbrkval, dbrkmod); |
be9a2362 FF |
1544 | } |
1545 | ||
2213b721 | 1546 | /* clear data breakpoint. */ |
be9a2362 FF |
1547 | void |
1548 | clear_dbreak() | |
1549 | { | |
1550 | dbrkval = 0; | |
1551 | dbrkmod = 0; | |
1552 | } | |
1553 | ||
2213b721 FF |
1554 | /* i860-specific breakpoint initialization. Includes adding the i860-specific |
1555 | data breakpoint commands. */ | |
be9a2362 FF |
1556 | void |
1557 | i860_init_breakpoints() | |
1558 | { | |
1559 | dbrkval = dbrkmod = 0; | |
1560 | add_com ("dbro", class_breakpoint, d_ro_break_command, | |
1561 | "Set a data breakpoint READ ONLY, 32-bit data element."); | |
1562 | add_com ("dbwo", class_breakpoint, d_wo_break_command, | |
1563 | "Set a data breakpoint WRITE ONLY, 32-bit data element."); | |
1564 | add_com ("dbrw", class_breakpoint, d_rw_break_command, | |
1565 | "Set a data breakpoint READ/WRITE, 32-bit data element."); | |
1566 | add_com ("dclear", class_breakpoint, clear_dbreak, | |
1567 | "clear the current data breakpoint."); | |
1568 | add_com_alias ("dc", "dclear", class_breakpoint, 1); | |
1569 | ||
1570 | } | |
1571 | ||
2213b721 | 1572 | /* i860-specific code to insert a breakpoint. */ |
be9a2362 FF |
1573 | int i860_insert_breakpoint(b) |
1574 | struct breakpoint *b; | |
1575 | { | |
1576 | int val; | |
1577 | ||
1578 | place_brk( b->address, BREAK_MODE, b ); | |
1579 | if (b->mode == DIM) | |
1580 | { | |
1581 | ||
2213b721 FF |
1582 | adj_read_memory (b->act_addr[0], &b->shadow_contents[0], INSTRUCTION_LENGTH); |
1583 | val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH); | |
1584 | if (val != 0 ) return val; | |
1585 | adj_read_memory (b->act_addr[1], &b->shadow_contents[1], INSTRUCTION_LENGTH); | |
1586 | /* val = adj_write_memory (b->act_addr[1], float_insn, INSTRUCTION_LENGTH); */ | |
1587 | if (val != 0) return val; | |
be9a2362 FF |
1588 | } |
1589 | else | |
1590 | { | |
2213b721 FF |
1591 | adj_read_memory (b->act_addr[0], &b->shadow_contents[0], INSTRUCTION_LENGTH); |
1592 | val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH); | |
be9a2362 | 1593 | } |
2213b721 | 1594 | if (b->address1 != 0) |
be9a2362 FF |
1595 | { |
1596 | if (b->mode == DIM) | |
1597 | { | |
1598 | ||
2213b721 FF |
1599 | adj_read_memory (b->act_addr[2], &b->shadow_contents[2], INSTRUCTION_LENGTH); |
1600 | val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH); | |
be9a2362 | 1601 | if (val) return val; |
2213b721 FF |
1602 | adj_read_memory (b->act_addr[3], &b->shadow_contents[3], INSTRUCTION_LENGTH); |
1603 | /* val = adj_write_memory (b->act_addr[3], float_insn, INSTRUCTION_LENGTH); */ | |
1604 | if (val != 0) return val; | |
be9a2362 FF |
1605 | } |
1606 | else | |
1607 | { | |
2213b721 FF |
1608 | adj_read_memory (b->act_addr[2], &b->shadow_contents[0], INSTRUCTION_LENGTH); |
1609 | val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH); | |
be9a2362 FF |
1610 | } |
1611 | } | |
2213b721 | 1612 | if (val != 0) |
be9a2362 FF |
1613 | return val; |
1614 | BTDEBUG("Inserted breakpoint at 0x%x, shadow 0x%x, 0x%x.\n", | |
1615 | b->address, b->shadow_contents[0], b->shadow_contents[1]); | |
1616 | b->inserted = 1; | |
1617 | return 0; | |
1618 | } | |
1619 | ||
1620 | int i860_remove_breakpoint(b) | |
1621 | struct breakpoint *b; | |
1622 | { | |
1623 | int val; | |
1624 | ||
1625 | if (b->inserted) | |
1626 | { | |
1627 | if (b->mode == DIM) | |
1628 | { | |
2213b721 FF |
1629 | val =adj_write_memory (b->act_addr[0], &(b->shadow_contents[0]), |
1630 | INSTRUCTION_LENGTH); | |
1631 | val =adj_write_memory (b->act_addr[1], &(b->shadow_contents[1]), | |
1632 | INSTRUCTION_LENGTH); | |
1633 | if (b->address1 != NULL) | |
be9a2362 | 1634 | { |
2213b721 FF |
1635 | val =adj_write_memory (b->act_addr[2], &(b->shadow_contents[2]), |
1636 | INSTRUCTION_LENGTH); | |
1637 | val =adj_write_memory (b->act_addr[3], &(b->shadow_contents[3]), | |
1638 | INSTRUCTION_LENGTH); | |
be9a2362 FF |
1639 | } |
1640 | } | |
1641 | else | |
1642 | { | |
2213b721 FF |
1643 | val =adj_write_memory (b->act_addr[0], b->shadow_contents, |
1644 | INSTRUCTION_LENGTH); | |
1645 | if (b->address1 != NULL) | |
be9a2362 | 1646 | { |
2213b721 FF |
1647 | val =adj_write_memory (b->act_addr[2], b->shadow_contents, |
1648 | INSTRUCTION_LENGTH); | |
be9a2362 FF |
1649 | } |
1650 | } | |
2213b721 | 1651 | if (val != 0) |
be9a2362 FF |
1652 | return val; |
1653 | b->inserted = 0; | |
1654 | BTDEBUG( "Removed breakpoint at 0x%x, shadow 0x%x, 0x%x.\n", | |
1655 | b->address, b->shadow_contents[0], b->shadow_contents[1]); | |
1656 | } | |
1657 | ||
1658 | return 0; | |
1659 | ||
1660 | ||
1661 | } | |
1662 | ||
1663 | ||
1664 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ | |
1665 | ||
1666 | #include <sys/procfs.h> | |
1667 | ||
1668 | /* The following routines were added by Peggy Fieland (Margaret_Fieland@vos.stratus.com) | |
1669 | They were adapted from the m-68k versions of the routines .*/ | |
1670 | ||
1671 | /* Given a pointer to a floating point register set in /proc format | |
1672 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
1673 | idea of the current floating point register values. */ | |
1674 | ||
1675 | void | |
1676 | supply_fpregset (fpregsetp) | |
1677 | fpregset_t *fpregsetp; | |
1678 | { | |
1679 | register int regno; | |
1680 | ||
1681 | BTDEBUG("supply_fregset called \n"); | |
1682 | ||
1683 | for (regno = F0 ; regno <= F31 ; regno++) | |
1684 | { | |
1685 | supply_register (regno, (char *) &(fpregsetp -> fpu.r_freg[regno-F0])); | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | /* Given a pointer to a floating point register set in /proc format | |
1690 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
1691 | of the current floating point register set. If REGNO is -1, update | |
1692 | them all. */ | |
1693 | ||
1694 | void | |
1695 | fill_fpregset (fpregsetp, regno) | |
1696 | fpregset_t *fpregsetp; | |
1697 | int regno; | |
1698 | { | |
1699 | int regi; | |
1700 | char *to; | |
1701 | char *from; | |
1702 | extern char registers[]; | |
1703 | BTDEBUG("fill_fregset regno %d\n",regno); | |
1704 | ||
1705 | for (regi = F0 ; regi <= F31 ; regi++) | |
1706 | { | |
1707 | if ((regno == -1) || (regno == regi)) | |
1708 | { | |
1709 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
1710 | to = (char *) &(fpregsetp -> fpu.r_freg[regi-F0]); | |
1711 | bcopy (from, to, REGISTER_RAW_SIZE (regno)); | |
1712 | } | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | ||
1717 | /* Given a pointer to a general register set in /proc format (gregset_t *), | |
1718 | unpack the register contents and supply them as gdb's idea of the current | |
1719 | register values. */ | |
1720 | ||
1721 | void | |
1722 | supply_gregset (gregsetp) | |
1723 | gregset_t *gregsetp; | |
1724 | { | |
1725 | register int regno; | |
1726 | register greg_t *regp = (greg_t *) gregsetp; | |
1727 | ||
1728 | BTDEBUG("supply_gregset called \n"); | |
1729 | ||
1730 | for (regno = 0 ; regno <= R31 ; regno++) | |
1731 | { | |
1732 | supply_register (regno, (char *) (regp + regno)); | |
1733 | } | |
1734 | } | |
1735 | ||
2213b721 FF |
1736 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
1737 | update the register specified by REGNO from gdb's idea | |
1738 | of the current general register set. If REGNO is -1, update | |
1739 | them all. */ | |
1740 | ||
be9a2362 FF |
1741 | void |
1742 | fill_gregset (gregsetp, regno) | |
1743 | gregset_t *gregsetp; | |
1744 | int regno; | |
1745 | { | |
1746 | int regi; | |
1747 | extern char registers[]; | |
1748 | register greg_t *regp = (greg_t *) gregsetp; | |
1749 | BTDEBUG("fill_gregset regno %d \n",regno); | |
1750 | ||
1751 | for (regi = 0 ; regi <= R31 ; regi++) | |
1752 | { | |
1753 | if ((regno == -1) || (regno == regi)) | |
1754 | { | |
1755 | *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; | |
1756 | } | |
1757 | ||
1758 | } | |
1759 | } | |
1760 | #endif |