Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* Target-machine dependent code for the Intel 960 |
2 | Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. | |
3 | Contributed by Intel Corporation. | |
4 | examine_prologue and other parts contributed by Wind River Systems. | |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "symtab.h" | |
25 | #include "value.h" | |
26 | #include "frame.h" | |
27 | #include "floatformat.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | ||
31 | static CORE_ADDR next_insn PARAMS ((CORE_ADDR memaddr, | |
32 | unsigned int *pword1, | |
33 | unsigned int *pword2)); | |
34 | ||
35 | /* Does the specified function use the "struct returning" convention | |
36 | or the "value returning" convention? The "value returning" convention | |
37 | almost invariably returns the entire value in registers. The | |
38 | "struct returning" convention often returns the entire value in | |
39 | memory, and passes a pointer (out of or into the function) saying | |
40 | where the value (is or should go). | |
41 | ||
42 | Since this sometimes depends on whether it was compiled with GCC, | |
43 | this is also an argument. This is used in call_function to build a | |
44 | stack, and in value_being_returned to print return values. | |
45 | ||
46 | On i960, a structure is returned in registers g0-g3, if it will fit. | |
47 | If it's more than 16 bytes long, g13 pointed to it on entry. */ | |
48 | ||
49 | int | |
50 | i960_use_struct_convention (gcc_p, type) | |
51 | int gcc_p; | |
52 | struct type *type; | |
53 | { | |
54 | return (TYPE_LENGTH (type) > 16); | |
55 | } | |
56 | ||
57 | /* gdb960 is always running on a non-960 host. Check its characteristics. | |
58 | This routine must be called as part of gdb initialization. */ | |
59 | ||
60 | static void | |
c5aa993b | 61 | check_host () |
c906108c | 62 | { |
c5aa993b | 63 | int i; |
c906108c | 64 | |
c5aa993b JM |
65 | static struct typestruct |
66 | { | |
67 | int hostsize; /* Size of type on host */ | |
68 | int i960size; /* Size of type on i960 */ | |
69 | char *typename; /* Name of type, for error msg */ | |
70 | } | |
71 | types[] = | |
72 | { | |
73 | { | |
74 | sizeof (short), 2, "short" | |
75 | } | |
76 | , | |
77 | { | |
78 | sizeof (int), 4, "int" | |
79 | } | |
80 | , | |
81 | { | |
82 | sizeof (long), 4, "long" | |
83 | } | |
84 | , | |
85 | { | |
86 | sizeof (float), 4, "float" | |
87 | } | |
88 | , | |
89 | { | |
90 | sizeof (double), 8, "double" | |
91 | } | |
92 | , | |
93 | { | |
94 | sizeof (char *), 4, "pointer" | |
95 | } | |
96 | , | |
97 | }; | |
98 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) | |
c906108c | 99 | |
c5aa993b JM |
100 | /* Make sure that host type sizes are same as i960 |
101 | */ | |
102 | for (i = 0; i < TYPELEN; i++) | |
103 | { | |
104 | if (types[i].hostsize != types[i].i960size) | |
105 | { | |
106 | printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", | |
107 | types[i].typename, types[i].i960size); | |
c906108c | 108 | } |
c5aa993b JM |
109 | |
110 | } | |
c906108c SS |
111 | } |
112 | \f | |
113 | /* Examine an i960 function prologue, recording the addresses at which | |
114 | registers are saved explicitly by the prologue code, and returning | |
115 | the address of the first instruction after the prologue (but not | |
116 | after the instruction at address LIMIT, as explained below). | |
117 | ||
118 | LIMIT places an upper bound on addresses of the instructions to be | |
119 | examined. If the prologue code scan reaches LIMIT, the scan is | |
120 | aborted and LIMIT is returned. This is used, when examining the | |
121 | prologue for the current frame, to keep examine_prologue () from | |
122 | claiming that a given register has been saved when in fact the | |
123 | instruction that saves it has not yet been executed. LIMIT is used | |
124 | at other times to stop the scan when we hit code after the true | |
125 | function prologue (e.g. for the first source line) which might | |
126 | otherwise be mistaken for function prologue. | |
127 | ||
128 | The format of the function prologue matched by this routine is | |
129 | derived from examination of the source to gcc960 1.21, particularly | |
130 | the routine i960_function_prologue (). A "regular expression" for | |
131 | the function prologue is given below: | |
132 | ||
133 | (lda LRn, g14 | |
c5aa993b JM |
134 | mov g14, g[0-7] |
135 | (mov 0, g14) | (lda 0, g14))? | |
c906108c SS |
136 | |
137 | (mov[qtl]? g[0-15], r[4-15])* | |
138 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? | |
139 | (st[qtl]? g[0-15], n(fp))* | |
140 | ||
141 | (cmpobne 0, g14, LFn | |
c5aa993b JM |
142 | mov sp, g14 |
143 | lda 0x30(sp), sp | |
144 | LFn: stq g0, (g14) | |
145 | stq g4, 0x10(g14) | |
146 | stq g8, 0x20(g14))? | |
c906108c SS |
147 | |
148 | (st g14, n(fp))? | |
149 | (mov g13,r[4-15])? | |
c5aa993b | 150 | */ |
c906108c SS |
151 | |
152 | /* Macros for extracting fields from i960 instructions. */ | |
153 | ||
154 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) | |
155 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) | |
156 | ||
157 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) | |
158 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) | |
159 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
160 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
161 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) | |
162 | ||
163 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or | |
164 | is not the address of a valid instruction, the address of the next | |
165 | instruction beyond ADDR otherwise. *PWORD1 receives the first word | |
166 | of the instruction, and (for two-word instructions), *PWORD2 receives | |
167 | the second. */ | |
168 | ||
169 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ | |
170 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) | |
171 | ||
172 | static CORE_ADDR | |
173 | examine_prologue (ip, limit, frame_addr, fsr) | |
174 | register CORE_ADDR ip; | |
175 | register CORE_ADDR limit; | |
176 | CORE_ADDR frame_addr; | |
177 | struct frame_saved_regs *fsr; | |
178 | { | |
179 | register CORE_ADDR next_ip; | |
180 | register int src, dst; | |
181 | register unsigned int *pcode; | |
182 | unsigned int insn1, insn2; | |
183 | int size; | |
184 | int within_leaf_prologue; | |
185 | CORE_ADDR save_addr; | |
c5aa993b JM |
186 | static unsigned int varargs_prologue_code[] = |
187 | { | |
188 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ | |
189 | 0x5cf01601, /* mov sp, g14 */ | |
190 | 0x8c086030, /* lda 0x30(sp), sp */ | |
191 | 0xb2879000, /* LFn: stq g0, (g14) */ | |
192 | 0xb2a7a010, /* stq g4, 0x10(g14) */ | |
193 | 0xb2c7a020 /* stq g8, 0x20(g14) */ | |
194 | }; | |
c906108c SS |
195 | |
196 | /* Accept a leaf procedure prologue code fragment if present. | |
197 | Note that ip might point to either the leaf or non-leaf | |
198 | entry point; we look for the non-leaf entry point first: */ | |
199 | ||
200 | within_leaf_prologue = 0; | |
201 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
202 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ |
203 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ | |
c906108c SS |
204 | { |
205 | within_leaf_prologue = 1; | |
206 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); | |
207 | } | |
208 | ||
209 | /* Now look for the prologue code at a leaf entry point: */ | |
210 | ||
211 | if (next_ip | |
c5aa993b | 212 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
213 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) |
214 | { | |
215 | within_leaf_prologue = 1; | |
216 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
217 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ |
218 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ | |
c906108c SS |
219 | { |
220 | ip = next_ip; | |
221 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
222 | within_leaf_prologue = 0; | |
223 | } | |
224 | } | |
225 | ||
226 | /* If something that looks like the beginning of a leaf prologue | |
227 | has been seen, but the remainder of the prologue is missing, bail. | |
228 | We don't know what we've got. */ | |
229 | ||
230 | if (within_leaf_prologue) | |
231 | return (ip); | |
c5aa993b | 232 | |
c906108c SS |
233 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. |
234 | This may cause us to mistake the moving of a register | |
235 | parameter to a local register for the saving of a callee-saved | |
236 | register, but that can't be helped, since with the | |
237 | "-fcall-saved" flag, any register can be made callee-saved. */ | |
238 | ||
239 | while (next_ip | |
240 | && (insn1 & 0xfc802fb0) == 0x5c000610 | |
241 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
242 | { | |
243 | src = REG_SRC1 (insn1); | |
244 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; | |
245 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
246 | while (size--) | |
247 | { | |
248 | fsr->regs[src++] = save_addr; | |
249 | save_addr += 4; | |
250 | } | |
251 | ip = next_ip; | |
252 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
253 | } | |
254 | ||
255 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ | |
256 | ||
257 | if (next_ip && | |
258 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ | |
259 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ | |
260 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ | |
261 | { | |
262 | ip = next_ip; | |
263 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
264 | } | |
265 | ||
266 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". | |
267 | This may cause us to mistake the copying of a register | |
268 | parameter to the frame for the saving of a callee-saved | |
269 | register, but that can't be helped, since with the | |
270 | "-fcall-saved" flag, any register can be made callee-saved. | |
271 | We can, however, refuse to accept a save of register g14, | |
272 | since that is matched explicitly below. */ | |
273 | ||
274 | while (next_ip && | |
c5aa993b JM |
275 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ |
276 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ | |
277 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ | |
278 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ | |
c906108c SS |
279 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) |
280 | { | |
281 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) | |
282 | ? insn2 : MEMA_OFFSET (insn1)); | |
283 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) | |
c5aa993b | 284 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); |
c906108c SS |
285 | while (size--) |
286 | { | |
287 | fsr->regs[src++] = save_addr; | |
288 | save_addr += 4; | |
289 | } | |
290 | ip = next_ip; | |
291 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
292 | } | |
293 | ||
294 | /* Accept the varargs prologue code if present. */ | |
295 | ||
296 | size = sizeof (varargs_prologue_code) / sizeof (int); | |
297 | pcode = varargs_prologue_code; | |
298 | while (size-- && next_ip && *pcode++ == insn1) | |
299 | { | |
300 | ip = next_ip; | |
301 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
302 | } | |
303 | ||
304 | /* Accept an optional "st g14, n(fp)". */ | |
305 | ||
306 | if (next_ip && | |
c5aa993b JM |
307 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ |
308 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ | |
c906108c SS |
309 | { |
310 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) | |
c5aa993b | 311 | ? insn2 : MEMA_OFFSET (insn1)); |
c906108c SS |
312 | ip = next_ip; |
313 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
314 | } | |
315 | ||
316 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. | |
317 | This is saving the address where a struct should be returned. */ | |
318 | ||
319 | if (next_ip | |
320 | && (insn1 & 0xff802fbf) == 0x5c00061d | |
321 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
322 | { | |
323 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
c5aa993b | 324 | fsr->regs[G0_REGNUM + 13] = save_addr; |
c906108c | 325 | ip = next_ip; |
c5aa993b | 326 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ |
c906108c SS |
327 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
328 | #endif | |
329 | } | |
330 | ||
331 | return (ip); | |
332 | } | |
333 | ||
334 | /* Given an ip value corresponding to the start of a function, | |
335 | return the ip of the first instruction after the function | |
336 | prologue. */ | |
337 | ||
338 | CORE_ADDR | |
b83266a0 | 339 | i960_skip_prologue (ip) |
c5aa993b | 340 | CORE_ADDR (ip); |
c906108c SS |
341 | { |
342 | struct frame_saved_regs saved_regs_dummy; | |
343 | struct symtab_and_line sal; | |
344 | CORE_ADDR limit; | |
345 | ||
346 | sal = find_pc_line (ip, 0); | |
347 | limit = (sal.end) ? sal.end : 0xffffffff; | |
348 | ||
349 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy)); | |
350 | } | |
351 | ||
352 | /* Put here the code to store, into a struct frame_saved_regs, | |
353 | the addresses of the saved registers of frame described by FRAME_INFO. | |
354 | This includes special registers such as pc and fp saved in special | |
355 | ways in the stack frame. sp is even more special: | |
356 | the address we return for it IS the sp for the next frame. | |
357 | ||
358 | We cache the result of doing this in the frame_obstack, since it is | |
359 | fairly expensive. */ | |
360 | ||
361 | void | |
362 | frame_find_saved_regs (fi, fsr) | |
363 | struct frame_info *fi; | |
364 | struct frame_saved_regs *fsr; | |
365 | { | |
366 | register CORE_ADDR next_addr; | |
367 | register CORE_ADDR *saved_regs; | |
368 | register int regnum; | |
369 | register struct frame_saved_regs *cache_fsr; | |
370 | CORE_ADDR ip; | |
371 | struct symtab_and_line sal; | |
372 | CORE_ADDR limit; | |
373 | ||
374 | if (!fi->fsr) | |
375 | { | |
376 | cache_fsr = (struct frame_saved_regs *) | |
377 | frame_obstack_alloc (sizeof (struct frame_saved_regs)); | |
378 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); | |
379 | fi->fsr = cache_fsr; | |
380 | ||
381 | /* Find the start and end of the function prologue. If the PC | |
c5aa993b JM |
382 | is in the function prologue, we only consider the part that |
383 | has executed already. */ | |
384 | ||
c906108c SS |
385 | ip = get_pc_function_start (fi->pc); |
386 | sal = find_pc_line (ip, 0); | |
c5aa993b | 387 | limit = (sal.end && sal.end < fi->pc) ? sal.end : fi->pc; |
c906108c SS |
388 | |
389 | examine_prologue (ip, limit, fi->frame, cache_fsr); | |
390 | ||
391 | /* Record the addresses at which the local registers are saved. | |
c5aa993b JM |
392 | Strictly speaking, we should only do this for non-leaf procedures, |
393 | but no one will ever look at these values if it is a leaf procedure, | |
394 | since local registers are always caller-saved. */ | |
c906108c SS |
395 | |
396 | next_addr = (CORE_ADDR) fi->frame; | |
397 | saved_regs = cache_fsr->regs; | |
398 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) | |
399 | { | |
400 | *saved_regs++ = next_addr; | |
401 | next_addr += 4; | |
402 | } | |
403 | ||
404 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; | |
405 | } | |
406 | ||
407 | *fsr = *fi->fsr; | |
408 | ||
409 | /* Fetch the value of the sp from memory every time, since it | |
410 | is conceivable that it has changed since the cache was flushed. | |
411 | This unfortunately undoes much of the savings from caching the | |
412 | saved register values. I suggest adding an argument to | |
413 | get_frame_saved_regs () specifying the register number we're | |
414 | interested in (or -1 for all registers). This would be passed | |
415 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient | |
416 | computation of saved register addresses (e.g., on the i960, | |
417 | we don't have to examine the prologue to find local registers). | |
c5aa993b | 418 | -- markf@wrs.com |
c906108c SS |
419 | FIXME, we don't need to refetch this, since the cache is cleared |
420 | every time the child process is restarted. If GDB itself | |
421 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ | |
422 | ||
423 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); | |
424 | } | |
425 | ||
426 | /* Return the address of the argument block for the frame | |
427 | described by FI. Returns 0 if the address is unknown. */ | |
428 | ||
429 | CORE_ADDR | |
430 | frame_args_address (fi, must_be_correct) | |
431 | struct frame_info *fi; | |
432 | { | |
433 | struct frame_saved_regs fsr; | |
434 | CORE_ADDR ap; | |
435 | ||
436 | /* If g14 was saved in the frame by the function prologue code, return | |
437 | the saved value. If the frame is current and we are being sloppy, | |
438 | return the value of g14. Otherwise, return zero. */ | |
439 | ||
440 | get_frame_saved_regs (fi, &fsr); | |
441 | if (fsr.regs[G14_REGNUM]) | |
c5aa993b | 442 | ap = read_memory_integer (fsr.regs[G14_REGNUM], 4); |
c906108c SS |
443 | else |
444 | { | |
445 | if (must_be_correct) | |
c5aa993b | 446 | return 0; /* Don't cache this result */ |
c906108c SS |
447 | if (get_next_frame (fi)) |
448 | ap = 0; | |
449 | else | |
450 | ap = read_register (G14_REGNUM); | |
451 | if (ap == 0) | |
452 | ap = fi->frame; | |
453 | } | |
454 | fi->arg_pointer = ap; /* Cache it for next time */ | |
455 | return ap; | |
456 | } | |
457 | ||
458 | /* Return the address of the return struct for the frame | |
459 | described by FI. Returns 0 if the address is unknown. */ | |
460 | ||
461 | CORE_ADDR | |
462 | frame_struct_result_address (fi) | |
463 | struct frame_info *fi; | |
464 | { | |
465 | struct frame_saved_regs fsr; | |
466 | CORE_ADDR ap; | |
467 | ||
468 | /* If the frame is non-current, check to see if g14 was saved in the | |
469 | frame by the function prologue code; return the saved value if so, | |
470 | zero otherwise. If the frame is current, return the value of g14. | |
471 | ||
472 | FIXME, shouldn't this use the saved value as long as we are past | |
473 | the function prologue, and only use the current value if we have | |
474 | no saved value and are at TOS? -- gnu@cygnus.com */ | |
475 | ||
476 | if (get_next_frame (fi)) | |
477 | { | |
478 | get_frame_saved_regs (fi, &fsr); | |
479 | if (fsr.regs[G13_REGNUM]) | |
c5aa993b | 480 | ap = read_memory_integer (fsr.regs[G13_REGNUM], 4); |
c906108c SS |
481 | else |
482 | ap = 0; | |
483 | } | |
484 | else | |
485 | ap = read_register (G13_REGNUM); | |
486 | ||
487 | return ap; | |
488 | } | |
489 | ||
490 | /* Return address to which the currently executing leafproc will return, | |
491 | or 0 if ip is not in a leafproc (or if we can't tell if it is). | |
c5aa993b | 492 | |
c906108c SS |
493 | Do this by finding the starting address of the routine in which ip lies. |
494 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this | |
495 | is a leafproc and the return address is in register gx. Well, this is | |
496 | true unless the return address points at a RET instruction in the current | |
497 | procedure, which indicates that we have a 'dual entry' routine that | |
498 | has been entered through the CALL entry point. */ | |
499 | ||
500 | CORE_ADDR | |
501 | leafproc_return (ip) | |
c5aa993b | 502 | CORE_ADDR ip; /* ip from currently executing function */ |
c906108c SS |
503 | { |
504 | register struct minimal_symbol *msymbol; | |
505 | char *p; | |
506 | int dst; | |
507 | unsigned int insn1, insn2; | |
508 | CORE_ADDR return_addr; | |
509 | ||
510 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) | |
511 | { | |
c5aa993b | 512 | if ((p = strchr (SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
c906108c SS |
513 | { |
514 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) | |
c5aa993b | 515 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
516 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) |
517 | { | |
518 | /* Get the return address. If the "mov g14, gx" | |
c5aa993b JM |
519 | instruction hasn't been executed yet, read |
520 | the return address from g14; otherwise, read it | |
521 | from the register into which g14 was moved. */ | |
c906108c SS |
522 | |
523 | return_addr = | |
c5aa993b JM |
524 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) |
525 | ? G14_REGNUM : dst); | |
c906108c SS |
526 | |
527 | /* We know we are in a leaf procedure, but we don't know | |
c5aa993b JM |
528 | whether the caller actually did a "bal" to the ".lf" |
529 | entry point, or a normal "call" to the non-leaf entry | |
530 | point one instruction before. In the latter case, the | |
531 | return address will be the address of a "ret" | |
532 | instruction within the procedure itself. We test for | |
533 | this below. */ | |
c906108c SS |
534 | |
535 | if (!next_insn (return_addr, &insn1, &insn2) | |
c5aa993b JM |
536 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ |
537 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) | |
c906108c SS |
538 | return (return_addr); |
539 | } | |
540 | } | |
541 | } | |
c5aa993b | 542 | |
c906108c SS |
543 | return (0); |
544 | } | |
545 | ||
546 | /* Immediately after a function call, return the saved pc. | |
547 | Can't go through the frames for this because on some machines | |
548 | the new frame is not set up until the new function executes | |
549 | some instructions. | |
550 | On the i960, the frame *is* set up immediately after the call, | |
551 | unless the function is a leaf procedure. */ | |
552 | ||
553 | CORE_ADDR | |
554 | saved_pc_after_call (frame) | |
555 | struct frame_info *frame; | |
556 | { | |
557 | CORE_ADDR saved_pc; | |
558 | ||
559 | saved_pc = leafproc_return (get_frame_pc (frame)); | |
560 | if (!saved_pc) | |
561 | saved_pc = FRAME_SAVED_PC (frame); | |
562 | ||
563 | return saved_pc; | |
564 | } | |
565 | ||
566 | /* Discard from the stack the innermost frame, | |
567 | restoring all saved registers. */ | |
568 | ||
569 | void | |
570 | pop_frame () | |
571 | { | |
572 | register struct frame_info *current_fi, *prev_fi; | |
573 | register int i; | |
574 | CORE_ADDR save_addr; | |
575 | CORE_ADDR leaf_return_addr; | |
576 | struct frame_saved_regs fsr; | |
577 | char local_regs_buf[16 * 4]; | |
578 | ||
579 | current_fi = get_current_frame (); | |
580 | ||
581 | /* First, undo what the hardware does when we return. | |
582 | If this is a non-leaf procedure, restore local registers from | |
583 | the save area in the calling frame. Otherwise, load the return | |
584 | address obtained from leafproc_return () into the rip. */ | |
585 | ||
586 | leaf_return_addr = leafproc_return (current_fi->pc); | |
587 | if (!leaf_return_addr) | |
588 | { | |
589 | /* Non-leaf procedure. Restore local registers, incl IP. */ | |
590 | prev_fi = get_prev_frame (current_fi); | |
591 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); | |
c5aa993b JM |
592 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, |
593 | sizeof (local_regs_buf)); | |
c906108c SS |
594 | |
595 | /* Restore frame pointer. */ | |
596 | write_register (FP_REGNUM, prev_fi->frame); | |
597 | } | |
598 | else | |
599 | { | |
600 | /* Leaf procedure. Just restore the return address into the IP. */ | |
601 | write_register (RIP_REGNUM, leaf_return_addr); | |
602 | } | |
603 | ||
604 | /* Now restore any global regs that the current function had saved. */ | |
605 | get_frame_saved_regs (current_fi, &fsr); | |
606 | for (i = G0_REGNUM; i < G14_REGNUM; i++) | |
607 | { | |
7a292a7a SS |
608 | save_addr = fsr.regs[i]; |
609 | if (save_addr != 0) | |
c906108c SS |
610 | write_register (i, read_memory_integer (save_addr, 4)); |
611 | } | |
612 | ||
613 | /* Flush the frame cache, create a frame for the new innermost frame, | |
614 | and make it the current frame. */ | |
615 | ||
616 | flush_cached_frames (); | |
617 | } | |
618 | ||
619 | /* Given a 960 stop code (fault or trace), return the signal which | |
620 | corresponds. */ | |
621 | ||
622 | enum target_signal | |
623 | i960_fault_to_signal (fault) | |
c5aa993b | 624 | int fault; |
c906108c SS |
625 | { |
626 | switch (fault) | |
627 | { | |
c5aa993b JM |
628 | case 0: |
629 | return TARGET_SIGNAL_BUS; /* parallel fault */ | |
630 | case 1: | |
631 | return TARGET_SIGNAL_UNKNOWN; | |
632 | case 2: | |
633 | return TARGET_SIGNAL_ILL; /* operation fault */ | |
634 | case 3: | |
635 | return TARGET_SIGNAL_FPE; /* arithmetic fault */ | |
636 | case 4: | |
637 | return TARGET_SIGNAL_FPE; /* floating point fault */ | |
c906108c SS |
638 | |
639 | /* constraint fault. This appears not to distinguish between | |
c5aa993b JM |
640 | a range constraint fault (which should be SIGFPE) and a privileged |
641 | fault (which should be SIGILL). */ | |
642 | case 5: | |
643 | return TARGET_SIGNAL_ILL; | |
c906108c | 644 | |
c5aa993b JM |
645 | case 6: |
646 | return TARGET_SIGNAL_SEGV; /* virtual memory fault */ | |
c906108c SS |
647 | |
648 | /* protection fault. This is for an out-of-range argument to | |
c5aa993b JM |
649 | "calls". I guess it also could be SIGILL. */ |
650 | case 7: | |
651 | return TARGET_SIGNAL_SEGV; | |
652 | ||
653 | case 8: | |
654 | return TARGET_SIGNAL_BUS; /* machine fault */ | |
655 | case 9: | |
656 | return TARGET_SIGNAL_BUS; /* structural fault */ | |
657 | case 0xa: | |
658 | return TARGET_SIGNAL_ILL; /* type fault */ | |
659 | case 0xb: | |
660 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
661 | case 0xc: | |
662 | return TARGET_SIGNAL_BUS; /* process fault */ | |
663 | case 0xd: | |
664 | return TARGET_SIGNAL_SEGV; /* descriptor fault */ | |
665 | case 0xe: | |
666 | return TARGET_SIGNAL_BUS; /* event fault */ | |
667 | case 0xf: | |
668 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
669 | case 0x10: | |
670 | return TARGET_SIGNAL_TRAP; /* single-step trace */ | |
671 | case 0x11: | |
672 | return TARGET_SIGNAL_TRAP; /* branch trace */ | |
673 | case 0x12: | |
674 | return TARGET_SIGNAL_TRAP; /* call trace */ | |
675 | case 0x13: | |
676 | return TARGET_SIGNAL_TRAP; /* return trace */ | |
677 | case 0x14: | |
678 | return TARGET_SIGNAL_TRAP; /* pre-return trace */ | |
679 | case 0x15: | |
680 | return TARGET_SIGNAL_TRAP; /* supervisor call trace */ | |
681 | case 0x16: | |
682 | return TARGET_SIGNAL_TRAP; /* breakpoint trace */ | |
683 | default: | |
684 | return TARGET_SIGNAL_UNKNOWN; | |
c906108c SS |
685 | } |
686 | } | |
687 | ||
688 | /****************************************/ | |
c5aa993b | 689 | /* MEM format */ |
c906108c SS |
690 | /****************************************/ |
691 | ||
c5aa993b JM |
692 | struct tabent |
693 | { | |
694 | char *name; | |
695 | char numops; | |
c906108c SS |
696 | }; |
697 | ||
c5aa993b JM |
698 | static int /* returns instruction length: 4 or 8 */ |
699 | mem (memaddr, word1, word2, noprint) | |
700 | unsigned long memaddr; | |
701 | unsigned long word1, word2; | |
702 | int noprint; /* If TRUE, return instruction length, but | |
c906108c SS |
703 | don't output any text. */ |
704 | { | |
c5aa993b JM |
705 | int i, j; |
706 | int len; | |
707 | int mode; | |
708 | int offset; | |
709 | const char *reg1, *reg2, *reg3; | |
710 | ||
711 | /* This lookup table is too sparse to make it worth typing in, but not | |
712 | * so large as to make a sparse array necessary. We allocate the | |
713 | * table at runtime, initialize all entries to empty, and copy the | |
714 | * real ones in from an initialization table. | |
715 | * | |
716 | * NOTE: In this table, the meaning of 'numops' is: | |
717 | * 1: single operand | |
718 | * 2: 2 operands, load instruction | |
719 | * -2: 2 operands, store instruction | |
720 | */ | |
721 | static struct tabent *mem_tab = NULL; | |
c906108c SS |
722 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ |
723 | #define MEM_MIN 0x80 | |
724 | #define MEM_MAX 0xcf | |
725 | #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent)) | |
726 | ||
c5aa993b JM |
727 | static struct |
728 | { | |
729 | int opcode; | |
730 | char *name; | |
731 | char numops; | |
732 | } | |
733 | mem_init[] = | |
734 | { | |
735 | 0x80, "ldob", 2, | |
736 | 0x82, "stob", -2, | |
737 | 0x84, "bx", 1, | |
738 | 0x85, "balx", 2, | |
739 | 0x86, "callx", 1, | |
740 | 0x88, "ldos", 2, | |
741 | 0x8a, "stos", -2, | |
742 | 0x8c, "lda", 2, | |
743 | 0x90, "ld", 2, | |
744 | 0x92, "st", -2, | |
745 | 0x98, "ldl", 2, | |
746 | 0x9a, "stl", -2, | |
747 | 0xa0, "ldt", 2, | |
748 | 0xa2, "stt", -2, | |
749 | 0xb0, "ldq", 2, | |
750 | 0xb2, "stq", -2, | |
751 | 0xc0, "ldib", 2, | |
752 | 0xc2, "stib", -2, | |
753 | 0xc8, "ldis", 2, | |
754 | 0xca, "stis", -2, | |
755 | 0, NULL, 0 | |
756 | }; | |
757 | ||
758 | if (mem_tab == NULL) | |
759 | { | |
760 | mem_tab = (struct tabent *) xmalloc (MEM_SIZ); | |
761 | memset (mem_tab, '\0', MEM_SIZ); | |
762 | for (i = 0; mem_init[i].opcode != 0; i++) | |
763 | { | |
764 | j = mem_init[i].opcode - MEM_MIN; | |
765 | mem_tab[j].name = mem_init[i].name; | |
766 | mem_tab[j].numops = mem_init[i].numops; | |
c906108c | 767 | } |
c5aa993b | 768 | } |
c906108c | 769 | |
c5aa993b JM |
770 | i = ((word1 >> 24) & 0xff) - MEM_MIN; |
771 | mode = (word1 >> 10) & 0xf; | |
c906108c | 772 | |
c5aa993b JM |
773 | if ((mem_tab[i].name != NULL) /* Valid instruction */ |
774 | && ((mode == 5) || (mode >= 12))) | |
775 | { /* With 32-bit displacement */ | |
776 | len = 8; | |
777 | } | |
778 | else | |
779 | { | |
780 | len = 4; | |
781 | } | |
c906108c | 782 | |
c5aa993b JM |
783 | if (noprint) |
784 | { | |
785 | return len; | |
786 | } | |
787 | abort (); | |
c906108c SS |
788 | } |
789 | ||
790 | /* Read the i960 instruction at 'memaddr' and return the address of | |
791 | the next instruction after that, or 0 if 'memaddr' is not the | |
792 | address of a valid instruction. The first word of the instruction | |
793 | is stored at 'pword1', and the second word, if any, is stored at | |
794 | 'pword2'. */ | |
795 | ||
796 | static CORE_ADDR | |
797 | next_insn (memaddr, pword1, pword2) | |
798 | unsigned int *pword1, *pword2; | |
799 | CORE_ADDR memaddr; | |
800 | { | |
801 | int len; | |
802 | char buf[8]; | |
803 | ||
804 | /* Read the two (potential) words of the instruction at once, | |
805 | to eliminate the overhead of two calls to read_memory (). | |
806 | FIXME: Loses if the first one is readable but the second is not | |
807 | (e.g. last word of the segment). */ | |
808 | ||
809 | read_memory (memaddr, buf, 8); | |
810 | *pword1 = extract_unsigned_integer (buf, 4); | |
811 | *pword2 = extract_unsigned_integer (buf + 4, 4); | |
812 | ||
c5aa993b | 813 | /* Divide instruction set into classes based on high 4 bits of opcode */ |
c906108c SS |
814 | |
815 | switch ((*pword1 >> 28) & 0xf) | |
816 | { | |
817 | case 0x0: | |
c5aa993b | 818 | case 0x1: /* ctrl */ |
c906108c SS |
819 | |
820 | case 0x2: | |
c5aa993b | 821 | case 0x3: /* cobr */ |
c906108c SS |
822 | |
823 | case 0x5: | |
824 | case 0x6: | |
c5aa993b | 825 | case 0x7: /* reg */ |
c906108c SS |
826 | len = 4; |
827 | break; | |
828 | ||
829 | case 0x8: | |
830 | case 0x9: | |
831 | case 0xa: | |
832 | case 0xb: | |
833 | case 0xc: | |
834 | len = mem (memaddr, *pword1, *pword2, 1); | |
835 | break; | |
836 | ||
c5aa993b | 837 | default: /* invalid instruction */ |
c906108c SS |
838 | len = 0; |
839 | break; | |
840 | } | |
841 | ||
842 | if (len) | |
843 | return memaddr + len; | |
844 | else | |
845 | return 0; | |
846 | } | |
847 | ||
848 | /* 'start_frame' is a variable in the MON960 runtime startup routine | |
849 | that contains the frame pointer of the 'start' routine (the routine | |
850 | that calls 'main'). By reading its contents out of remote memory, | |
851 | we can tell where the frame chain ends: backtraces should halt before | |
852 | they display this frame. */ | |
853 | ||
854 | int | |
855 | mon960_frame_chain_valid (chain, curframe) | |
c5aa993b JM |
856 | CORE_ADDR chain; |
857 | struct frame_info *curframe; | |
c906108c | 858 | { |
c5aa993b JM |
859 | struct symbol *sym; |
860 | struct minimal_symbol *msymbol; | |
861 | ||
862 | /* crtmon960.o is an assembler module that is assumed to be linked | |
863 | * first in an i80960 executable. It contains the true entry point; | |
864 | * it performs startup up initialization and then calls 'main'. | |
865 | * | |
866 | * 'sf' is the name of a variable in crtmon960.o that is set | |
867 | * during startup to the address of the first frame. | |
868 | * | |
869 | * 'a' is the address of that variable in 80960 memory. | |
870 | */ | |
871 | static char sf[] = "start_frame"; | |
872 | CORE_ADDR a; | |
873 | ||
874 | ||
875 | chain &= ~0x3f; /* Zero low 6 bits because previous frame pointers | |
876 | contain return status info in them. */ | |
877 | if (chain == 0) | |
878 | { | |
879 | return 0; | |
880 | } | |
c906108c | 881 | |
c5aa993b JM |
882 | sym = lookup_symbol (sf, 0, VAR_NAMESPACE, (int *) NULL, |
883 | (struct symtab **) NULL); | |
884 | if (sym != 0) | |
885 | { | |
886 | a = SYMBOL_VALUE (sym); | |
887 | } | |
888 | else | |
889 | { | |
890 | msymbol = lookup_minimal_symbol (sf, NULL, NULL); | |
891 | if (msymbol == NULL) | |
892 | return 0; | |
893 | a = SYMBOL_VALUE_ADDRESS (msymbol); | |
894 | } | |
c906108c | 895 | |
c5aa993b | 896 | return (chain != read_memory_integer (a, 4)); |
c906108c SS |
897 | } |
898 | ||
899 | void | |
900 | _initialize_i960_tdep () | |
901 | { | |
902 | check_host (); | |
903 | ||
904 | tm_print_insn = print_insn_i960; | |
905 | } |