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1 | /* Functions specific to running gdb native on IA-64 running |
2 | GNU/Linux. | |
3 | ||
4 | Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. | |
16461d7d KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
e162d11b | 24 | #include "gdb_string.h" |
16461d7d KB |
25 | #include "inferior.h" |
26 | #include "target.h" | |
27 | #include "gdbcore.h" | |
4e052eda | 28 | #include "regcache.h" |
16461d7d KB |
29 | |
30 | #include <signal.h> | |
31 | #include <sys/ptrace.h> | |
32 | #include <sys/wait.h> | |
33 | #ifdef HAVE_SYS_REG_H | |
34 | #include <sys/reg.h> | |
35 | #endif | |
36 | #include <sys/user.h> | |
37 | ||
38 | #include <asm/ptrace_offsets.h> | |
39 | #include <sys/procfs.h> | |
40 | ||
c60c0f5f MS |
41 | /* Prototypes for supply_gregset etc. */ |
42 | #include "gregset.h" | |
43 | ||
16461d7d KB |
44 | /* These must match the order of the register names. |
45 | ||
46 | Some sort of lookup table is needed because the offsets associated | |
47 | with the registers are all over the board. */ | |
48 | ||
49 | static int u_offsets[] = | |
50 | { | |
51 | /* general registers */ | |
52 | -1, /* gr0 not available; i.e, it's always zero */ | |
53 | PT_R1, | |
54 | PT_R2, | |
55 | PT_R3, | |
56 | PT_R4, | |
57 | PT_R5, | |
58 | PT_R6, | |
59 | PT_R7, | |
60 | PT_R8, | |
61 | PT_R9, | |
62 | PT_R10, | |
63 | PT_R11, | |
64 | PT_R12, | |
65 | PT_R13, | |
66 | PT_R14, | |
67 | PT_R15, | |
68 | PT_R16, | |
69 | PT_R17, | |
70 | PT_R18, | |
71 | PT_R19, | |
72 | PT_R20, | |
73 | PT_R21, | |
74 | PT_R22, | |
75 | PT_R23, | |
76 | PT_R24, | |
77 | PT_R25, | |
78 | PT_R26, | |
79 | PT_R27, | |
80 | PT_R28, | |
81 | PT_R29, | |
82 | PT_R30, | |
83 | PT_R31, | |
84 | /* gr32 through gr127 not directly available via the ptrace interface */ | |
85 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
86 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
87 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
88 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
89 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
90 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
91 | /* Floating point registers */ | |
92 | -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */ | |
93 | PT_F2, | |
94 | PT_F3, | |
95 | PT_F4, | |
96 | PT_F5, | |
97 | PT_F6, | |
98 | PT_F7, | |
99 | PT_F8, | |
100 | PT_F9, | |
101 | PT_F10, | |
102 | PT_F11, | |
103 | PT_F12, | |
104 | PT_F13, | |
105 | PT_F14, | |
106 | PT_F15, | |
107 | PT_F16, | |
108 | PT_F17, | |
109 | PT_F18, | |
110 | PT_F19, | |
111 | PT_F20, | |
112 | PT_F21, | |
113 | PT_F22, | |
114 | PT_F23, | |
115 | PT_F24, | |
116 | PT_F25, | |
117 | PT_F26, | |
118 | PT_F27, | |
119 | PT_F28, | |
120 | PT_F29, | |
121 | PT_F30, | |
122 | PT_F31, | |
123 | PT_F32, | |
124 | PT_F33, | |
125 | PT_F34, | |
126 | PT_F35, | |
127 | PT_F36, | |
128 | PT_F37, | |
129 | PT_F38, | |
130 | PT_F39, | |
131 | PT_F40, | |
132 | PT_F41, | |
133 | PT_F42, | |
134 | PT_F43, | |
135 | PT_F44, | |
136 | PT_F45, | |
137 | PT_F46, | |
138 | PT_F47, | |
139 | PT_F48, | |
140 | PT_F49, | |
141 | PT_F50, | |
142 | PT_F51, | |
143 | PT_F52, | |
144 | PT_F53, | |
145 | PT_F54, | |
146 | PT_F55, | |
147 | PT_F56, | |
148 | PT_F57, | |
149 | PT_F58, | |
150 | PT_F59, | |
151 | PT_F60, | |
152 | PT_F61, | |
153 | PT_F62, | |
154 | PT_F63, | |
155 | PT_F64, | |
156 | PT_F65, | |
157 | PT_F66, | |
158 | PT_F67, | |
159 | PT_F68, | |
160 | PT_F69, | |
161 | PT_F70, | |
162 | PT_F71, | |
163 | PT_F72, | |
164 | PT_F73, | |
165 | PT_F74, | |
166 | PT_F75, | |
167 | PT_F76, | |
168 | PT_F77, | |
169 | PT_F78, | |
170 | PT_F79, | |
171 | PT_F80, | |
172 | PT_F81, | |
173 | PT_F82, | |
174 | PT_F83, | |
175 | PT_F84, | |
176 | PT_F85, | |
177 | PT_F86, | |
178 | PT_F87, | |
179 | PT_F88, | |
180 | PT_F89, | |
181 | PT_F90, | |
182 | PT_F91, | |
183 | PT_F92, | |
184 | PT_F93, | |
185 | PT_F94, | |
186 | PT_F95, | |
187 | PT_F96, | |
188 | PT_F97, | |
189 | PT_F98, | |
190 | PT_F99, | |
191 | PT_F100, | |
192 | PT_F101, | |
193 | PT_F102, | |
194 | PT_F103, | |
195 | PT_F104, | |
196 | PT_F105, | |
197 | PT_F106, | |
198 | PT_F107, | |
199 | PT_F108, | |
200 | PT_F109, | |
201 | PT_F110, | |
202 | PT_F111, | |
203 | PT_F112, | |
204 | PT_F113, | |
205 | PT_F114, | |
206 | PT_F115, | |
207 | PT_F116, | |
208 | PT_F117, | |
209 | PT_F118, | |
210 | PT_F119, | |
211 | PT_F120, | |
212 | PT_F121, | |
213 | PT_F122, | |
214 | PT_F123, | |
215 | PT_F124, | |
216 | PT_F125, | |
217 | PT_F126, | |
218 | PT_F127, | |
219 | /* predicate registers - we don't fetch these individually */ | |
220 | -1, -1, -1, -1, -1, -1, -1, -1, | |
221 | -1, -1, -1, -1, -1, -1, -1, -1, | |
222 | -1, -1, -1, -1, -1, -1, -1, -1, | |
223 | -1, -1, -1, -1, -1, -1, -1, -1, | |
224 | -1, -1, -1, -1, -1, -1, -1, -1, | |
225 | -1, -1, -1, -1, -1, -1, -1, -1, | |
226 | -1, -1, -1, -1, -1, -1, -1, -1, | |
227 | -1, -1, -1, -1, -1, -1, -1, -1, | |
228 | /* branch registers */ | |
229 | PT_B0, | |
230 | PT_B1, | |
231 | PT_B2, | |
232 | PT_B3, | |
233 | PT_B4, | |
234 | PT_B5, | |
235 | PT_B6, | |
236 | PT_B7, | |
237 | /* virtual frame pointer and virtual return address pointer */ | |
238 | -1, -1, | |
239 | /* other registers */ | |
240 | PT_PR, | |
241 | PT_CR_IIP, /* ip */ | |
242 | PT_CR_IPSR, /* psr */ | |
9ac12c35 | 243 | PT_CFM, /* cfm */ |
16461d7d KB |
244 | /* kernel registers not visible via ptrace interface (?) */ |
245 | -1, -1, -1, -1, -1, -1, -1, -1, | |
246 | /* hole */ | |
247 | -1, -1, -1, -1, -1, -1, -1, -1, | |
248 | PT_AR_RSC, | |
249 | PT_AR_BSP, | |
250 | PT_AR_BSPSTORE, | |
251 | PT_AR_RNAT, | |
252 | -1, | |
253 | -1, /* Not available: FCR, IA32 floating control register */ | |
254 | -1, -1, | |
255 | -1, /* Not available: EFLAG */ | |
256 | -1, /* Not available: CSD */ | |
257 | -1, /* Not available: SSD */ | |
258 | -1, /* Not available: CFLG */ | |
259 | -1, /* Not available: FSR */ | |
260 | -1, /* Not available: FIR */ | |
261 | -1, /* Not available: FDR */ | |
262 | -1, | |
263 | PT_AR_CCV, | |
264 | -1, -1, -1, | |
265 | PT_AR_UNAT, | |
266 | -1, -1, -1, | |
267 | PT_AR_FPSR, | |
268 | -1, -1, -1, | |
269 | -1, /* Not available: ITC */ | |
270 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
271 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
272 | PT_AR_PFS, | |
273 | PT_AR_LC, | |
274 | -1, /* Not available: EC, the Epilog Count register */ | |
275 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
276 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
277 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
278 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
279 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
280 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
281 | -1, | |
282 | /* nat bits - not fetched directly; instead we obtain these bits from | |
283 | either rnat or unat or from memory. */ | |
284 | -1, -1, -1, -1, -1, -1, -1, -1, | |
285 | -1, -1, -1, -1, -1, -1, -1, -1, | |
286 | -1, -1, -1, -1, -1, -1, -1, -1, | |
287 | -1, -1, -1, -1, -1, -1, -1, -1, | |
288 | -1, -1, -1, -1, -1, -1, -1, -1, | |
289 | -1, -1, -1, -1, -1, -1, -1, -1, | |
290 | -1, -1, -1, -1, -1, -1, -1, -1, | |
291 | -1, -1, -1, -1, -1, -1, -1, -1, | |
292 | -1, -1, -1, -1, -1, -1, -1, -1, | |
293 | -1, -1, -1, -1, -1, -1, -1, -1, | |
294 | -1, -1, -1, -1, -1, -1, -1, -1, | |
295 | -1, -1, -1, -1, -1, -1, -1, -1, | |
296 | -1, -1, -1, -1, -1, -1, -1, -1, | |
297 | -1, -1, -1, -1, -1, -1, -1, -1, | |
298 | -1, -1, -1, -1, -1, -1, -1, -1, | |
299 | -1, -1, -1, -1, -1, -1, -1, -1, | |
300 | }; | |
301 | ||
302 | CORE_ADDR | |
fba45db2 | 303 | register_addr (int regno, CORE_ADDR blockend) |
16461d7d KB |
304 | { |
305 | CORE_ADDR addr; | |
306 | ||
307 | if (regno < 0 || regno >= NUM_REGS) | |
308 | error ("Invalid register number %d.", regno); | |
309 | ||
310 | if (u_offsets[regno] == -1) | |
311 | addr = 0; | |
312 | else | |
313 | addr = (CORE_ADDR) u_offsets[regno]; | |
314 | ||
315 | return addr; | |
316 | } | |
317 | ||
318 | int ia64_cannot_fetch_register (regno) | |
319 | int regno; | |
320 | { | |
321 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1; | |
322 | } | |
323 | ||
324 | int ia64_cannot_store_register (regno) | |
325 | int regno; | |
326 | { | |
327 | /* Rationale behind not permitting stores to bspstore... | |
328 | ||
329 | The IA-64 architecture provides bspstore and bsp which refer | |
330 | memory locations in the RSE's backing store. bspstore is the | |
331 | next location which will be written when the RSE needs to write | |
332 | to memory. bsp is the address at which r32 in the current frame | |
333 | would be found if it were written to the backing store. | |
334 | ||
335 | The IA-64 architecture provides read-only access to bsp and | |
336 | read/write access to bspstore (but only when the RSE is in | |
337 | the enforced lazy mode). It should be noted that stores | |
338 | to bspstore also affect the value of bsp. Changing bspstore | |
339 | does not affect the number of dirty entries between bspstore | |
340 | and bsp, so changing bspstore by N words will also cause bsp | |
341 | to be changed by (roughly) N as well. (It could be N-1 or N+1 | |
342 | depending upon where the NaT collection bits fall.) | |
343 | ||
92362027 | 344 | OTOH, the Linux kernel provides read/write access to bsp (and |
16461d7d KB |
345 | currently read/write access to bspstore as well). But it |
346 | is definitely the case that if you change one, the other | |
347 | will change at the same time. It is more useful to gdb to | |
348 | be able to change bsp. So in order to prevent strange and | |
349 | undesirable things from happening when a dummy stack frame | |
350 | is popped (after calling an inferior function), we allow | |
351 | bspstore to be read, but not written. (Note that popping | |
352 | a (generic) dummy stack frame causes all registers that | |
353 | were previously read from the inferior process to be written | |
354 | back.) */ | |
355 | ||
356 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1 | |
357 | || regno == IA64_BSPSTORE_REGNUM; | |
358 | } | |
359 | ||
360 | void | |
fba45db2 | 361 | supply_gregset (gregset_t *gregsetp) |
16461d7d KB |
362 | { |
363 | int regi; | |
364 | greg_t *regp = (greg_t *) gregsetp; | |
365 | ||
366 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) | |
367 | { | |
368 | supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM))); | |
369 | } | |
370 | ||
371 | /* FIXME: NAT collection bits are at index 32; gotta deal with these | |
372 | somehow... */ | |
373 | ||
374 | supply_register (IA64_PR_REGNUM, (char *) (regp + 33)); | |
375 | ||
376 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) | |
377 | { | |
378 | supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM))); | |
379 | } | |
380 | ||
381 | supply_register (IA64_IP_REGNUM, (char *) (regp + 42)); | |
382 | supply_register (IA64_CFM_REGNUM, (char *) (regp + 43)); | |
383 | supply_register (IA64_PSR_REGNUM, (char *) (regp + 44)); | |
384 | supply_register (IA64_RSC_REGNUM, (char *) (regp + 45)); | |
385 | supply_register (IA64_BSP_REGNUM, (char *) (regp + 46)); | |
386 | supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47)); | |
387 | supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48)); | |
388 | supply_register (IA64_CCV_REGNUM, (char *) (regp + 49)); | |
389 | supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50)); | |
390 | supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51)); | |
391 | supply_register (IA64_PFS_REGNUM, (char *) (regp + 52)); | |
392 | supply_register (IA64_LC_REGNUM, (char *) (regp + 53)); | |
393 | supply_register (IA64_EC_REGNUM, (char *) (regp + 54)); | |
394 | } | |
395 | ||
396 | void | |
fba45db2 | 397 | fill_gregset (gregset_t *gregsetp, int regno) |
16461d7d | 398 | { |
76d689a6 KB |
399 | int regi; |
400 | greg_t *regp = (greg_t *) gregsetp; | |
401 | ||
402 | #define COPY_REG(_idx_,_regi_) \ | |
403 | if ((regno == -1) || regno == _regi_) \ | |
524d7c18 | 404 | memcpy (regp + _idx_, &deprecated_registers[REGISTER_BYTE (_regi_)], \ |
76d689a6 KB |
405 | REGISTER_RAW_SIZE (_regi_)) |
406 | ||
407 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) | |
408 | { | |
409 | COPY_REG (regi - IA64_GR0_REGNUM, regi); | |
410 | } | |
411 | ||
412 | /* FIXME: NAT collection bits at index 32? */ | |
413 | ||
414 | COPY_REG (33, IA64_PR_REGNUM); | |
415 | ||
416 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) | |
417 | { | |
418 | COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); | |
419 | } | |
420 | ||
421 | COPY_REG (42, IA64_IP_REGNUM); | |
422 | COPY_REG (43, IA64_CFM_REGNUM); | |
423 | COPY_REG (44, IA64_PSR_REGNUM); | |
424 | COPY_REG (45, IA64_RSC_REGNUM); | |
425 | COPY_REG (46, IA64_BSP_REGNUM); | |
426 | COPY_REG (47, IA64_BSPSTORE_REGNUM); | |
427 | COPY_REG (48, IA64_RNAT_REGNUM); | |
428 | COPY_REG (49, IA64_CCV_REGNUM); | |
429 | COPY_REG (50, IA64_UNAT_REGNUM); | |
430 | COPY_REG (51, IA64_FPSR_REGNUM); | |
431 | COPY_REG (52, IA64_PFS_REGNUM); | |
432 | COPY_REG (53, IA64_LC_REGNUM); | |
433 | COPY_REG (54, IA64_EC_REGNUM); | |
434 | } | |
435 | ||
436 | /* Given a pointer to a floating point register set in /proc format | |
437 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
438 | idea of the current floating point register values. */ | |
439 | ||
440 | void | |
fba45db2 | 441 | supply_fpregset (fpregset_t *fpregsetp) |
76d689a6 KB |
442 | { |
443 | register int regi; | |
444 | char *from; | |
445 | ||
446 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) | |
447 | { | |
448 | from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); | |
449 | supply_register (regi, from); | |
450 | } | |
451 | } | |
452 | ||
453 | /* Given a pointer to a floating point register set in /proc format | |
454 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
455 | of the current floating point register set. If REGNO is -1, update | |
456 | them all. */ | |
457 | ||
458 | void | |
fba45db2 | 459 | fill_fpregset (fpregset_t *fpregsetp, int regno) |
76d689a6 KB |
460 | { |
461 | int regi; | |
462 | char *to; | |
463 | char *from; | |
464 | ||
465 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) | |
466 | { | |
467 | if ((regno == -1) || (regno == regi)) | |
468 | { | |
524d7c18 | 469 | from = (char *) &deprecated_registers[REGISTER_BYTE (regi)]; |
76d689a6 KB |
470 | to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); |
471 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); | |
472 | } | |
473 | } | |
16461d7d | 474 | } |
acf7b9e1 KB |
475 | |
476 | #define IA64_PSR_DB (1UL << 24) | |
477 | #define IA64_PSR_DD (1UL << 39) | |
478 | ||
479 | static void | |
39f77062 | 480 | enable_watchpoints_in_psr (ptid_t ptid) |
acf7b9e1 KB |
481 | { |
482 | CORE_ADDR psr; | |
483 | ||
39f77062 | 484 | psr = read_register_pid (IA64_PSR_REGNUM, ptid); |
acf7b9e1 KB |
485 | if (!(psr & IA64_PSR_DB)) |
486 | { | |
487 | psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware | |
488 | watchpoints and breakpoints. */ | |
39f77062 | 489 | write_register_pid (IA64_PSR_REGNUM, psr, ptid); |
acf7b9e1 KB |
490 | } |
491 | } | |
492 | ||
493 | static long | |
39f77062 | 494 | fetch_debug_register (ptid_t ptid, int idx) |
acf7b9e1 KB |
495 | { |
496 | long val; | |
497 | int tid; | |
498 | ||
39f77062 | 499 | tid = TIDGET (ptid); |
acf7b9e1 | 500 | if (tid == 0) |
39f77062 | 501 | tid = PIDGET (ptid); |
acf7b9e1 KB |
502 | |
503 | val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0); | |
504 | ||
505 | return val; | |
506 | } | |
507 | ||
508 | static void | |
39f77062 | 509 | store_debug_register (ptid_t ptid, int idx, long val) |
acf7b9e1 KB |
510 | { |
511 | int tid; | |
512 | ||
39f77062 | 513 | tid = TIDGET (ptid); |
acf7b9e1 | 514 | if (tid == 0) |
39f77062 | 515 | tid = PIDGET (ptid); |
acf7b9e1 KB |
516 | |
517 | (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val); | |
518 | } | |
519 | ||
520 | static void | |
39f77062 | 521 | fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) |
acf7b9e1 KB |
522 | { |
523 | if (dbr_addr) | |
39f77062 | 524 | *dbr_addr = fetch_debug_register (ptid, 2 * idx); |
acf7b9e1 | 525 | if (dbr_mask) |
39f77062 | 526 | *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1); |
acf7b9e1 KB |
527 | } |
528 | ||
529 | static void | |
39f77062 | 530 | store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) |
acf7b9e1 KB |
531 | { |
532 | if (dbr_addr) | |
39f77062 | 533 | store_debug_register (ptid, 2 * idx, *dbr_addr); |
acf7b9e1 | 534 | if (dbr_mask) |
39f77062 | 535 | store_debug_register (ptid, 2 * idx + 1, *dbr_mask); |
acf7b9e1 KB |
536 | } |
537 | ||
538 | static int | |
539 | is_power_of_2 (int val) | |
540 | { | |
541 | int i, onecount; | |
542 | ||
543 | onecount = 0; | |
544 | for (i = 0; i < 8 * sizeof (val); i++) | |
545 | if (val & (1 << i)) | |
546 | onecount++; | |
547 | ||
548 | return onecount <= 1; | |
549 | } | |
550 | ||
551 | int | |
39f77062 | 552 | ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw) |
acf7b9e1 KB |
553 | { |
554 | int idx; | |
555 | long dbr_addr, dbr_mask; | |
556 | int max_watchpoints = 4; | |
557 | ||
558 | if (len <= 0 || !is_power_of_2 (len)) | |
559 | return -1; | |
560 | ||
561 | for (idx = 0; idx < max_watchpoints; idx++) | |
562 | { | |
39f77062 | 563 | fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask); |
acf7b9e1 KB |
564 | if ((dbr_mask & (0x3UL << 62)) == 0) |
565 | { | |
566 | /* Exit loop if both r and w bits clear */ | |
567 | break; | |
568 | } | |
569 | } | |
570 | ||
571 | if (idx == max_watchpoints) | |
572 | return -1; | |
573 | ||
574 | dbr_addr = (long) addr; | |
575 | dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ | |
576 | dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ | |
577 | switch (rw) | |
578 | { | |
579 | case hw_write: | |
580 | dbr_mask |= (1L << 62); /* Set w bit */ | |
581 | break; | |
582 | case hw_read: | |
583 | dbr_mask |= (1L << 63); /* Set r bit */ | |
584 | break; | |
585 | case hw_access: | |
586 | dbr_mask |= (3L << 62); /* Set both r and w bits */ | |
587 | break; | |
588 | default: | |
589 | return -1; | |
590 | } | |
591 | ||
39f77062 KB |
592 | store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); |
593 | enable_watchpoints_in_psr (ptid); | |
acf7b9e1 KB |
594 | |
595 | return 0; | |
596 | } | |
597 | ||
598 | int | |
39f77062 | 599 | ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len) |
acf7b9e1 KB |
600 | { |
601 | int idx; | |
602 | long dbr_addr, dbr_mask; | |
603 | int max_watchpoints = 4; | |
604 | ||
605 | if (len <= 0 || !is_power_of_2 (len)) | |
606 | return -1; | |
607 | ||
608 | for (idx = 0; idx < max_watchpoints; idx++) | |
609 | { | |
39f77062 | 610 | fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); |
acf7b9e1 KB |
611 | if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) |
612 | { | |
613 | dbr_addr = 0; | |
614 | dbr_mask = 0; | |
39f77062 | 615 | store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); |
acf7b9e1 KB |
616 | return 0; |
617 | } | |
618 | } | |
619 | return -1; | |
620 | } | |
621 | ||
622 | CORE_ADDR | |
39f77062 | 623 | ia64_linux_stopped_by_watchpoint (ptid_t ptid) |
acf7b9e1 KB |
624 | { |
625 | CORE_ADDR psr; | |
626 | int tid; | |
627 | struct siginfo siginfo; | |
628 | ||
39f77062 | 629 | tid = TIDGET(ptid); |
acf7b9e1 | 630 | if (tid == 0) |
39f77062 | 631 | tid = PIDGET (ptid); |
acf7b9e1 KB |
632 | |
633 | errno = 0; | |
634 | ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo); | |
635 | ||
1186f287 | 636 | if (errno != 0 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
acf7b9e1 KB |
637 | return 0; |
638 | ||
39f77062 | 639 | psr = read_register_pid (IA64_PSR_REGNUM, ptid); |
acf7b9e1 KB |
640 | psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint |
641 | for the next instruction */ | |
39f77062 | 642 | write_register_pid (IA64_PSR_REGNUM, psr, ptid); |
acf7b9e1 KB |
643 | |
644 | return (CORE_ADDR) siginfo.si_addr; | |
645 | } |