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[deliverable/binutils-gdb.git] / gdb / ia64-linux-nat.c
CommitLineData
ca557f44
AC		 1/* Functions specific to running gdb native on IA-64 running
2 GNU/Linux.
3
0fb0cc75 4 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
7b6bb8da 5 2009, 2010, 2011 Free Software Foundation, Inc.
16461d7d
KB		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
16461d7d
KB		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
16461d7d
KB		 21
22#include "defs.h"
e162d11b 23#include "gdb_string.h"
16461d7d
KB		 24#include "inferior.h"
25#include "target.h"
26#include "gdbcore.h"
4e052eda 27#include "regcache.h"
949df321 28#include "ia64-tdep.h"
10d6c8cd 29#include "linux-nat.h"
16461d7d
KB		 30
31#include <signal.h>
32#include <sys/ptrace.h>
2555fe1a 33#include "gdb_wait.h"
16461d7d
KB		 34#ifdef HAVE_SYS_REG_H
35#include <sys/reg.h>
36#endif
287a334e 37#include <sys/syscall.h>
16461d7d
KB		 38#include <sys/user.h>
39
40#include <asm/ptrace_offsets.h>
41#include <sys/procfs.h>
42
1777feb0 43/* Prototypes for supply_gregset etc. */
c60c0f5f
MS		 44#include "gregset.h"
45
16461d7d
KB		 46/* These must match the order of the register names.
47
48 Some sort of lookup table is needed because the offsets associated
49 with the registers are all over the board. */
50
51static int u_offsets[] =
52 {
53 /* general registers */
1777feb0 54 -1, /* gr0 not available; i.e, it's always zero. */
16461d7d
KB		 55 PT_R1,
56 PT_R2,
57 PT_R3,
58 PT_R4,
59 PT_R5,
60 PT_R6,
61 PT_R7,
62 PT_R8,
63 PT_R9,
64 PT_R10,
65 PT_R11,
66 PT_R12,
67 PT_R13,
68 PT_R14,
69 PT_R15,
70 PT_R16,
71 PT_R17,
72 PT_R18,
73 PT_R19,
74 PT_R20,
75 PT_R21,
76 PT_R22,
77 PT_R23,
78 PT_R24,
79 PT_R25,
80 PT_R26,
81 PT_R27,
82 PT_R28,
83 PT_R29,
84 PT_R30,
85 PT_R31,
1777feb0 86 /* gr32 through gr127 not directly available via the ptrace interface. */
16461d7d
KB		 87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 /* Floating point registers */
1777feb0 94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
16461d7d
KB		 95 PT_F2,
96 PT_F3,
97 PT_F4,
98 PT_F5,
99 PT_F6,
100 PT_F7,
101 PT_F8,
102 PT_F9,
103 PT_F10,
104 PT_F11,
105 PT_F12,
106 PT_F13,
107 PT_F14,
108 PT_F15,
109 PT_F16,
110 PT_F17,
111 PT_F18,
112 PT_F19,
113 PT_F20,
114 PT_F21,
115 PT_F22,
116 PT_F23,
117 PT_F24,
118 PT_F25,
119 PT_F26,
120 PT_F27,
121 PT_F28,
122 PT_F29,
123 PT_F30,
124 PT_F31,
125 PT_F32,
126 PT_F33,
127 PT_F34,
128 PT_F35,
129 PT_F36,
130 PT_F37,
131 PT_F38,
132 PT_F39,
133 PT_F40,
134 PT_F41,
135 PT_F42,
136 PT_F43,
137 PT_F44,
138 PT_F45,
139 PT_F46,
140 PT_F47,
141 PT_F48,
142 PT_F49,
143 PT_F50,
144 PT_F51,
145 PT_F52,
146 PT_F53,
147 PT_F54,
148 PT_F55,
149 PT_F56,
150 PT_F57,
151 PT_F58,
152 PT_F59,
153 PT_F60,
154 PT_F61,
155 PT_F62,
156 PT_F63,
157 PT_F64,
158 PT_F65,
159 PT_F66,
160 PT_F67,
161 PT_F68,
162 PT_F69,
163 PT_F70,
164 PT_F71,
165 PT_F72,
166 PT_F73,
167 PT_F74,
168 PT_F75,
169 PT_F76,
170 PT_F77,
171 PT_F78,
172 PT_F79,
173 PT_F80,
174 PT_F81,
175 PT_F82,
176 PT_F83,
177 PT_F84,
178 PT_F85,
179 PT_F86,
180 PT_F87,
181 PT_F88,
182 PT_F89,
183 PT_F90,
184 PT_F91,
185 PT_F92,
186 PT_F93,
187 PT_F94,
188 PT_F95,
189 PT_F96,
190 PT_F97,
191 PT_F98,
192 PT_F99,
193 PT_F100,
194 PT_F101,
195 PT_F102,
196 PT_F103,
197 PT_F104,
198 PT_F105,
199 PT_F106,
200 PT_F107,
201 PT_F108,
202 PT_F109,
203 PT_F110,
204 PT_F111,
205 PT_F112,
206 PT_F113,
207 PT_F114,
208 PT_F115,
209 PT_F116,
210 PT_F117,
211 PT_F118,
212 PT_F119,
213 PT_F120,
214 PT_F121,
215 PT_F122,
216 PT_F123,
217 PT_F124,
218 PT_F125,
219 PT_F126,
220 PT_F127,
1777feb0 221 /* Predicate registers - we don't fetch these individually. */
16461d7d
KB		 222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 /* branch registers */
231 PT_B0,
232 PT_B1,
233 PT_B2,
234 PT_B3,
235 PT_B4,
236 PT_B5,
237 PT_B6,
238 PT_B7,
1777feb0 239 /* Virtual frame pointer and virtual return address pointer. */
16461d7d
KB		 240 -1, -1,
241 /* other registers */
242 PT_PR,
243 PT_CR_IIP, /* ip */
244 PT_CR_IPSR, /* psr */
9ac12c35 245 PT_CFM, /* cfm */
1777feb0 246 /* kernel registers not visible via ptrace interface (?) */
16461d7d
KB		 247 -1, -1, -1, -1, -1, -1, -1, -1,
248 /* hole */
249 -1, -1, -1, -1, -1, -1, -1, -1,
250 PT_AR_RSC,
251 PT_AR_BSP,
252 PT_AR_BSPSTORE,
253 PT_AR_RNAT,
254 -1,
1777feb0 255 -1, /* Not available: FCR, IA32 floating control register. */
16461d7d
KB		 256 -1, -1,
257 -1, /* Not available: EFLAG */
258 -1, /* Not available: CSD */
259 -1, /* Not available: SSD */
260 -1, /* Not available: CFLG */
261 -1, /* Not available: FSR */
262 -1, /* Not available: FIR */
263 -1, /* Not available: FDR */
264 -1,
265 PT_AR_CCV,
266 -1, -1, -1,
267 PT_AR_UNAT,
268 -1, -1, -1,
269 PT_AR_FPSR,
270 -1, -1, -1,
271 -1, /* Not available: ITC */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1,
274 PT_AR_PFS,
275 PT_AR_LC,
1777feb0 276 -1, /* Not available: EC, the Epilog Count register. */
16461d7d
KB		 277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
283 -1,
284 /* nat bits - not fetched directly; instead we obtain these bits from
1777feb0 285 either rnat or unat or from memory. */
16461d7d
KB		 286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
302 };
303
74174d2e 304static CORE_ADDR
2685572f 305ia64_register_addr (struct gdbarch *gdbarch, int regno)
16461d7d
KB		 306{
307 CORE_ADDR addr;
308
2685572f 309 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
8a3fe4f8 310 error (_("Invalid register number %d."), regno);
16461d7d
KB		 311
312 if (u_offsets[regno] == -1)
313 addr = 0;
314 else
315 addr = (CORE_ADDR) u_offsets[regno];
316
317 return addr;
318}
319
74174d2e 320static int
2685572f 321ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
16461d7d 322{
f57d151a 323 return regno < 0
2685572f 324 || regno >= gdbarch_num_regs (gdbarch)
f57d151a 325 || u_offsets[regno] == -1;
16461d7d
KB		 326}
327
74174d2e 328static int
2685572f 329ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
16461d7d
KB		 330{
331 /* Rationale behind not permitting stores to bspstore...
332
333 The IA-64 architecture provides bspstore and bsp which refer
334 memory locations in the RSE's backing store. bspstore is the
335 next location which will be written when the RSE needs to write
336 to memory. bsp is the address at which r32 in the current frame
337 would be found if it were written to the backing store.
338
339 The IA-64 architecture provides read-only access to bsp and
340 read/write access to bspstore (but only when the RSE is in
341 the enforced lazy mode). It should be noted that stores
342 to bspstore also affect the value of bsp. Changing bspstore
343 does not affect the number of dirty entries between bspstore
344 and bsp, so changing bspstore by N words will also cause bsp
345 to be changed by (roughly) N as well. (It could be N-1 or N+1
346 depending upon where the NaT collection bits fall.)
347
92362027 348 OTOH, the Linux kernel provides read/write access to bsp (and
16461d7d
KB		 349 currently read/write access to bspstore as well). But it
350 is definitely the case that if you change one, the other
351 will change at the same time. It is more useful to gdb to
352 be able to change bsp. So in order to prevent strange and
353 undesirable things from happening when a dummy stack frame
354 is popped (after calling an inferior function), we allow
355 bspstore to be read, but not written. (Note that popping
356 a (generic) dummy stack frame causes all registers that
357 were previously read from the inferior process to be written
358 back.) */
359
f57d151a 360 return regno < 0
2685572f 361 || regno >= gdbarch_num_regs (gdbarch)
f57d151a 362 || u_offsets[regno] == -1
16461d7d
KB		 363 || regno == IA64_BSPSTORE_REGNUM;
364}
365
366void
7f7fe91e 367supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
16461d7d
KB		 368{
369 int regi;
7f7fe91e 370 const greg_t *regp = (const greg_t *) gregsetp;
16461d7d
KB		 371
372 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
373 {
7f7fe91e 374 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
16461d7d
KB		 375 }
376
377 /* FIXME: NAT collection bits are at index 32; gotta deal with these
1777feb0 378 somehow... */
16461d7d 379
7f7fe91e 380 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
16461d7d
KB		 381
382 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
383 {
7f7fe91e
UW		 384 regcache_raw_supply (regcache, regi,
385 regp + 34 + (regi - IA64_BR0_REGNUM));
16461d7d
KB		 386 }
387
7f7fe91e
UW		 388 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
389 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
390 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
391 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
392 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
393 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
394 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
395 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
396 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
397 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
398 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
399 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
400 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
16461d7d
KB		 401}
402
403void
7f7fe91e 404fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
16461d7d 405{
76d689a6
KB		 406 int regi;
407 greg_t *regp = (greg_t *) gregsetp;
408
409#define COPY_REG(_idx_,_regi_) \
410 if ((regno == -1) || regno == _regi_) \
7f7fe91e 411 regcache_raw_collect (regcache, _regi_, regp + _idx_)
76d689a6
KB		 412
413 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
414 {
415 COPY_REG (regi - IA64_GR0_REGNUM, regi);
416 }
417
1777feb0 418 /* FIXME: NAT collection bits at index 32? */
76d689a6
KB		 419
420 COPY_REG (33, IA64_PR_REGNUM);
421
422 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
423 {
424 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
425 }
426
427 COPY_REG (42, IA64_IP_REGNUM);
428 COPY_REG (43, IA64_CFM_REGNUM);
429 COPY_REG (44, IA64_PSR_REGNUM);
430 COPY_REG (45, IA64_RSC_REGNUM);
431 COPY_REG (46, IA64_BSP_REGNUM);
432 COPY_REG (47, IA64_BSPSTORE_REGNUM);
433 COPY_REG (48, IA64_RNAT_REGNUM);
434 COPY_REG (49, IA64_CCV_REGNUM);
435 COPY_REG (50, IA64_UNAT_REGNUM);
436 COPY_REG (51, IA64_FPSR_REGNUM);
437 COPY_REG (52, IA64_PFS_REGNUM);
438 COPY_REG (53, IA64_LC_REGNUM);
439 COPY_REG (54, IA64_EC_REGNUM);
440}
441
442/* Given a pointer to a floating point register set in /proc format
443 (fpregset_t *), unpack the register contents and supply them as gdb's
1777feb0 444 idea of the current floating point register values. */
76d689a6
KB		 445
446void
7f7fe91e 447supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
76d689a6 448{
52f0bd74 449 int regi;
7f7fe91e 450 const char *from;
76d689a6
KB		 451
452 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
453 {
7f7fe91e
UW		 454 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
455 regcache_raw_supply (regcache, regi, from);
76d689a6
KB		 456 }
457}
458
459/* Given a pointer to a floating point register set in /proc format
460 (fpregset_t *), update the register specified by REGNO from gdb's idea
461 of the current floating point register set. If REGNO is -1, update
1777feb0 462 them all. */
76d689a6
KB		 463
464void
7f7fe91e
UW		 465fill_fpregset (const struct regcache *regcache,
466 fpregset_t *fpregsetp, int regno)
76d689a6
KB		 467{
468 int regi;
76d689a6
KB		 469
470 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
471 {
472 if ((regno == -1) || (regno == regi))
7f7fe91e 473 regcache_raw_collect (regcache, regi,
e0e25c6c 474 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
76d689a6 475 }
16461d7d 476}
acf7b9e1
KB		 477
478#define IA64_PSR_DB (1UL << 24)
479#define IA64_PSR_DD (1UL << 39)
480
481static void
9f0bdab8 482enable_watchpoints_in_psr (ptid_t ptid)
acf7b9e1 483{
9f0bdab8 484 struct regcache *regcache = get_thread_regcache (ptid);
7b86a1b8 485 ULONGEST psr;
acf7b9e1 486
7b86a1b8 487 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1
KB		 488 if (!(psr & IA64_PSR_DB))
489 {
490 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
1777feb0 491 watchpoints and breakpoints. */
7b86a1b8 492 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1
KB		 493 }
494}
495
9f0bdab8 496static long debug_registers[8];
acf7b9e1
KB		 497
498static void
39f77062 499store_debug_register (ptid_t ptid, int idx, long val)
acf7b9e1
KB		 500{
501 int tid;
502
39f77062 503 tid = TIDGET (ptid);
acf7b9e1 504 if (tid == 0)
39f77062 505 tid = PIDGET (ptid);
acf7b9e1 506
c5fa4245 507 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
acf7b9e1
KB		 508}
509
acf7b9e1 510static void
1777feb0
MS		 511store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
512 long *dbr_mask)
acf7b9e1
KB		 513{
514 if (dbr_addr)
39f77062 515 store_debug_register (ptid, 2 * idx, *dbr_addr);
acf7b9e1 516 if (dbr_mask)
39f77062 517 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
acf7b9e1
KB		 518}
519
520static int
521is_power_of_2 (int val)
522{
523 int i, onecount;
524
525 onecount = 0;
526 for (i = 0; i < 8 * sizeof (val); i++)
527 if (val & (1 << i))
528 onecount++;
529
530 return onecount <= 1;
531}
532
74174d2e 533static int
0cf6dd15
TJB		 534ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
535 struct expression *cond)
acf7b9e1 536{
9f0bdab8 537 struct lwp_info *lp;
acf7b9e1
KB		 538 int idx;
539 long dbr_addr, dbr_mask;
540 int max_watchpoints = 4;
541
542 if (len <= 0 || !is_power_of_2 (len))
543 return -1;
544
545 for (idx = 0; idx < max_watchpoints; idx++)
546 {
9f0bdab8 547 dbr_mask = debug_registers[idx * 2 + 1];
acf7b9e1
KB		 548 if ((dbr_mask & (0x3UL << 62)) == 0)
549 {
1777feb0 550 /* Exit loop if both r and w bits clear. */
acf7b9e1
KB		 551 break;
552 }
553 }
554
555 if (idx == max_watchpoints)
556 return -1;
557
558 dbr_addr = (long) addr;
559 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
560 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
561 switch (rw)
562 {
563 case hw_write:
564 dbr_mask |= (1L << 62); /* Set w bit */
565 break;
566 case hw_read:
567 dbr_mask |= (1L << 63); /* Set r bit */
568 break;
569 case hw_access:
570 dbr_mask |= (3L << 62); /* Set both r and w bits */
571 break;
572 default:
573 return -1;
574 }
575
9f0bdab8
DJ		 576 debug_registers[2 * idx] = dbr_addr;
577 debug_registers[2 * idx + 1] = dbr_mask;
4c38200f 578 ALL_LWPS (lp)
9f0bdab8 579 {
4c38200f
PA		 580 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
581 enable_watchpoints_in_psr (lp->ptid);
9f0bdab8 582 }
acf7b9e1
KB		 583
584 return 0;
585}
586
74174d2e 587static int
0cf6dd15
TJB		 588ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
589 struct expression *cond)
acf7b9e1
KB		 590{
591 int idx;
592 long dbr_addr, dbr_mask;
593 int max_watchpoints = 4;
594
595 if (len <= 0 || !is_power_of_2 (len))
596 return -1;
597
598 for (idx = 0; idx < max_watchpoints; idx++)
599 {
9f0bdab8
DJ		 600 dbr_addr = debug_registers[2 * idx];
601 dbr_mask = debug_registers[2 * idx + 1];
acf7b9e1
KB		 602 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
603 {
9f0bdab8 604 struct lwp_info *lp;
9f0bdab8
DJ		 605
606 debug_registers[2 * idx] = 0;
607 debug_registers[2 * idx + 1] = 0;
acf7b9e1
KB		 608 dbr_addr = 0;
609 dbr_mask = 0;
9f0bdab8 610
4c38200f
PA		 611 ALL_LWPS (lp)
612 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
9f0bdab8 613
acf7b9e1
KB		 614 return 0;
615 }
616 }
617 return -1;
618}
619
9f0bdab8
DJ		 620static void
621ia64_linux_new_thread (ptid_t ptid)
622{
623 int i, any;
624
625 any = 0;
626 for (i = 0; i < 8; i++)
627 {
628 if (debug_registers[i] != 0)
629 any = 1;
630 store_debug_register (ptid, i, debug_registers[i]);
631 }
632
633 if (any)
634 enable_watchpoints_in_psr (ptid);
635}
636
74174d2e
UW		 637static int
638ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
acf7b9e1
KB		 639{
640 CORE_ADDR psr;
9f0bdab8 641 struct siginfo *siginfo_p;
594f7785 642 struct regcache *regcache = get_current_regcache ();
acf7b9e1 643
9f0bdab8 644 siginfo_p = linux_nat_get_siginfo (inferior_ptid);
acf7b9e1 645
9f0bdab8
DJ		 646 if (siginfo_p->si_signo != SIGTRAP
647 || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
acf7b9e1
KB		 648 return 0;
649
7b86a1b8 650 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1 651 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
1777feb0 652 for the next instruction. */
7b86a1b8 653 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1 654
9f0bdab8 655 *addr_p = (CORE_ADDR)siginfo_p->si_addr;
4aa7a7f5
JJ		 656 return 1;
657}
658
74174d2e 659static int
4aa7a7f5
JJ		 660ia64_linux_stopped_by_watchpoint (void)
661{
662 CORE_ADDR addr;
74174d2e
UW		 663 return ia64_linux_stopped_data_address (&current_target, &addr);
664}
665
666static int
667ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
668{
669 return 1;
670}
671
672
673/* Fetch register REGNUM from the inferior. */
674
675static void
56be3814 676ia64_linux_fetch_register (struct regcache *regcache, int regnum)
74174d2e 677{
088568da 678 struct gdbarch *gdbarch = get_regcache_arch (regcache);
74174d2e
UW		 679 CORE_ADDR addr;
680 size_t size;
681 PTRACE_TYPE_RET *buf;
682 int pid, i;
683
2685572f 684 if (ia64_cannot_fetch_register (gdbarch, regnum))
74174d2e 685 {
56be3814 686 regcache_raw_supply (regcache, regnum, NULL);
74174d2e
UW		 687 return;
688 }
689
690 /* Cater for systems like GNU/Linux, that implement threads as
691 separate processes. */
692 pid = ptid_get_lwp (inferior_ptid);
693 if (pid == 0)
694 pid = ptid_get_pid (inferior_ptid);
695
696 /* This isn't really an address, but ptrace thinks of it as one. */
2685572f 697 addr = ia64_register_addr (gdbarch, regnum);
088568da 698 size = register_size (gdbarch, regnum);
74174d2e
UW		 699
700 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
701 buf = alloca (size);
702
703 /* Read the register contents from the inferior a chunk at a time. */
704 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
705 {
706 errno = 0;
707 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
708 if (errno != 0)
709 error (_("Couldn't read register %s (#%d): %s."),
088568da 710 gdbarch_register_name (gdbarch, regnum),
c9f4d572 711 regnum, safe_strerror (errno));
74174d2e
UW		 712
713 addr += sizeof (PTRACE_TYPE_RET);
714 }
56be3814 715 regcache_raw_supply (regcache, regnum, buf);
74174d2e
UW		 716}
717
718/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
719 for all registers. */
720
721static void
28439f5e
PA		 722ia64_linux_fetch_registers (struct target_ops *ops,
723 struct regcache *regcache, int regnum)
74174d2e
UW		 724{
725 if (regnum == -1)
088568da
UW		 726 for (regnum = 0;
727 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
728 regnum++)
56be3814 729 ia64_linux_fetch_register (regcache, regnum);
74174d2e 730 else
56be3814 731 ia64_linux_fetch_register (regcache, regnum);
74174d2e
UW		 732}
733
734/* Store register REGNUM into the inferior. */
735
736static void
56be3814 737ia64_linux_store_register (const struct regcache *regcache, int regnum)
74174d2e 738{
088568da 739 struct gdbarch *gdbarch = get_regcache_arch (regcache);
74174d2e
UW		 740 CORE_ADDR addr;
741 size_t size;
742 PTRACE_TYPE_RET *buf;
743 int pid, i;
744
2685572f 745 if (ia64_cannot_store_register (gdbarch, regnum))
74174d2e
UW		 746 return;
747
748 /* Cater for systems like GNU/Linux, that implement threads as
749 separate processes. */
750 pid = ptid_get_lwp (inferior_ptid);
751 if (pid == 0)
752 pid = ptid_get_pid (inferior_ptid);
753
754 /* This isn't really an address, but ptrace thinks of it as one. */
2685572f 755 addr = ia64_register_addr (gdbarch, regnum);
088568da 756 size = register_size (gdbarch, regnum);
74174d2e
UW		 757
758 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
759 buf = alloca (size);
760
761 /* Write the register contents into the inferior a chunk at a time. */
56be3814 762 regcache_raw_collect (regcache, regnum, buf);
74174d2e
UW		 763 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
764 {
765 errno = 0;
766 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
767 if (errno != 0)
768 error (_("Couldn't write register %s (#%d): %s."),
088568da 769 gdbarch_register_name (gdbarch, regnum),
c9f4d572 770 regnum, safe_strerror (errno));
74174d2e
UW		 771
772 addr += sizeof (PTRACE_TYPE_RET);
773 }
acf7b9e1 774}
287a334e 775
74174d2e
UW		 776/* Store register REGNUM back into the inferior. If REGNUM is -1, do
777 this for all registers. */
778
779static void
28439f5e
PA		 780ia64_linux_store_registers (struct target_ops *ops,
781 struct regcache *regcache, int regnum)
74174d2e
UW		 782{
783 if (regnum == -1)
088568da
UW		 784 for (regnum = 0;
785 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
786 regnum++)
56be3814 787 ia64_linux_store_register (regcache, regnum);
74174d2e 788 else
56be3814 789 ia64_linux_store_register (regcache, regnum);
74174d2e
UW		 790}
791
792
10d6c8cd 793static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
1777feb0
MS		 794 const char *, gdb_byte *,
795 const gdb_byte *, ULONGEST, LONGEST);
10d6c8cd
DJ		 796
797static LONGEST
798ia64_linux_xfer_partial (struct target_ops *ops,
799 enum target_object object,
800 const char *annex,
801 gdb_byte *readbuf, const gdb_byte *writebuf,
802 ULONGEST offset, LONGEST len)
803{
804 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
805 return syscall (__NR_getunwind, readbuf, len);
806
807 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
808 offset, len);
809}
810
26ab7092
JK		 811/* For break.b instruction ia64 CPU forgets the immediate value and generates
812 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
813 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
814 difference for the signals here. */
815
816static int
817ia64_linux_status_is_event (int status)
818{
819 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
820 || WSTOPSIG (status) == SIGILL);
821}
822
10d6c8cd
DJ		 823void _initialize_ia64_linux_nat (void);
824
825void
826_initialize_ia64_linux_nat (void)
287a334e 827{
dde7c0a9 828 struct target_ops *t;
10d6c8cd
DJ		 829
830 /* Fill in the generic GNU/Linux methods. */
831 t = linux_target ();
832
74174d2e
UW		 833 /* Override the default fetch/store register routines. */
834 t->to_fetch_registers = ia64_linux_fetch_registers;
835 t->to_store_registers = ia64_linux_store_registers;
836
10d6c8cd
DJ		 837 /* Override the default to_xfer_partial. */
838 super_xfer_partial = t->to_xfer_partial;
839 t->to_xfer_partial = ia64_linux_xfer_partial;
840
74174d2e
UW		 841 /* Override watchpoint routines. */
842
843 /* The IA-64 architecture can step over a watch point (without triggering
844 it again) if the "dd" (data debug fault disable) bit in the processor
845 status word is set.
846
847 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
848 code there has determined that a hardware watchpoint has indeed
849 been hit. The CPU will then be able to execute one instruction
1777feb0 850 without triggering a watchpoint. */
74174d2e
UW		 851
852 t->to_have_steppable_watchpoint = 1;
853 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
854 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
855 t->to_stopped_data_address = ia64_linux_stopped_data_address;
856 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
857 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
858
10d6c8cd 859 /* Register the target. */
f973ed9c 860 linux_nat_add_target (t);
9f0bdab8 861 linux_nat_set_new_thread (t, ia64_linux_new_thread);
26ab7092 862 linux_nat_set_status_is_event (t, ia64_linux_status_is_event);
287a334e 863}
GDB Binutils - Deliverables
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