[deliverable/binutils-gdb.git] / gdb / ia64-linux-nat.c

/* Functions specific to running gdb native on IA-64 running
   GNU/Linux.

   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "defs.h"
#include "gdb_string.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"
#include "regcache.h"
#include "ia64-tdep.h"

#include <signal.h>
#include <sys/ptrace.h>
#include "gdb_wait.h"
#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif
#include <sys/syscall.h>
#include <sys/user.h>

#include <asm/ptrace_offsets.h>
#include <sys/procfs.h>

/* Prototypes for supply_gregset etc. */
#include "gregset.h"

/* These must match the order of the register names.

   Some sort of lookup table is needed because the offsets associated
   with the registers are all over the board.  */

static int u_offsets[] =
  {
    /* general registers */
    -1,		/* gr0 not available; i.e, it's always zero */
    PT_R1,
    PT_R2,
    PT_R3,
    PT_R4,
    PT_R5,
    PT_R6,
    PT_R7,
    PT_R8,
    PT_R9,
    PT_R10,
    PT_R11,
    PT_R12,
    PT_R13,
    PT_R14,
    PT_R15,
    PT_R16,
    PT_R17,
    PT_R18,
    PT_R19,
    PT_R20,
    PT_R21,
    PT_R22,
    PT_R23,
    PT_R24,
    PT_R25,
    PT_R26,
    PT_R27,
    PT_R28,
    PT_R29,
    PT_R30,
    PT_R31,
    /* gr32 through gr127 not directly available via the ptrace interface */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    /* Floating point registers */
    -1, -1,	/* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
    PT_F2,
    PT_F3,
    PT_F4,
    PT_F5,
    PT_F6,
    PT_F7,
    PT_F8,
    PT_F9,
    PT_F10,
    PT_F11,
    PT_F12,
    PT_F13,
    PT_F14,
    PT_F15,
    PT_F16,
    PT_F17,
    PT_F18,
    PT_F19,
    PT_F20,
    PT_F21,
    PT_F22,
    PT_F23,
    PT_F24,
    PT_F25,
    PT_F26,
    PT_F27,
    PT_F28,
    PT_F29,
    PT_F30,
    PT_F31,
    PT_F32,
    PT_F33,
    PT_F34,
    PT_F35,
    PT_F36,
    PT_F37,
    PT_F38,
    PT_F39,
    PT_F40,
    PT_F41,
    PT_F42,
    PT_F43,
    PT_F44,
    PT_F45,
    PT_F46,
    PT_F47,
    PT_F48,
    PT_F49,
    PT_F50,
    PT_F51,
    PT_F52,
    PT_F53,
    PT_F54,
    PT_F55,
    PT_F56,
    PT_F57,
    PT_F58,
    PT_F59,
    PT_F60,
    PT_F61,
    PT_F62,
    PT_F63,
    PT_F64,
    PT_F65,
    PT_F66,
    PT_F67,
    PT_F68,
    PT_F69,
    PT_F70,
    PT_F71,
    PT_F72,
    PT_F73,
    PT_F74,
    PT_F75,
    PT_F76,
    PT_F77,
    PT_F78,
    PT_F79,
    PT_F80,
    PT_F81,
    PT_F82,
    PT_F83,
    PT_F84,
    PT_F85,
    PT_F86,
    PT_F87,
    PT_F88,
    PT_F89,
    PT_F90,
    PT_F91,
    PT_F92,
    PT_F93,
    PT_F94,
    PT_F95,
    PT_F96,
    PT_F97,
    PT_F98,
    PT_F99,
    PT_F100,
    PT_F101,
    PT_F102,
    PT_F103,
    PT_F104,
    PT_F105,
    PT_F106,
    PT_F107,
    PT_F108,
    PT_F109,
    PT_F110,
    PT_F111,
    PT_F112,
    PT_F113,
    PT_F114,
    PT_F115,
    PT_F116,
    PT_F117,
    PT_F118,
    PT_F119,
    PT_F120,
    PT_F121,
    PT_F122,
    PT_F123,
    PT_F124,
    PT_F125,
    PT_F126,
    PT_F127,
    /* predicate registers - we don't fetch these individually */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* branch registers */
    PT_B0,
    PT_B1,
    PT_B2,
    PT_B3,
    PT_B4,
    PT_B5,
    PT_B6,
    PT_B7,
    /* virtual frame pointer and virtual return address pointer */
    -1, -1,
    /* other registers */
    PT_PR,
    PT_CR_IIP,	/* ip */
    PT_CR_IPSR, /* psr */
    PT_CFM,	/* cfm */
    /* kernel registers not visible via ptrace interface (?) */
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* hole */
    -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_RSC,
    PT_AR_BSP,
    PT_AR_BSPSTORE,
    PT_AR_RNAT,
    -1,
    -1,		/* Not available: FCR, IA32 floating control register */
    -1, -1,
    -1,		/* Not available: EFLAG */
    -1,		/* Not available: CSD */
    -1,		/* Not available: SSD */
    -1,		/* Not available: CFLG */
    -1,		/* Not available: FSR */
    -1,		/* Not available: FIR */
    -1,		/* Not available: FDR */
    -1,
    PT_AR_CCV,
    -1, -1, -1,
    PT_AR_UNAT,
    -1, -1, -1,
    PT_AR_FPSR,
    -1, -1, -1,
    -1,		/* Not available: ITC */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_PFS,
    PT_AR_LC,
    -1,		/* Not available: EC, the Epilog Count register */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1,
    /* nat bits - not fetched directly; instead we obtain these bits from
       either rnat or unat or from memory. */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
  };

CORE_ADDR
register_addr (int regno, CORE_ADDR blockend)
{
  CORE_ADDR addr;

  if (regno < 0 || regno >= NUM_REGS)
    error (_("Invalid register number %d."), regno);

  if (u_offsets[regno] == -1)
    addr = 0;
  else
    addr = (CORE_ADDR) u_offsets[regno];

  return addr;
}

int ia64_cannot_fetch_register (regno)
     int regno;
{
  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
}

int ia64_cannot_store_register (regno)
     int regno;
{
  /* Rationale behind not permitting stores to bspstore...
  
     The IA-64 architecture provides bspstore and bsp which refer
     memory locations in the RSE's backing store.  bspstore is the
     next location which will be written when the RSE needs to write
     to memory.  bsp is the address at which r32 in the current frame
     would be found if it were written to the backing store.

     The IA-64 architecture provides read-only access to bsp and
     read/write access to bspstore (but only when the RSE is in
     the enforced lazy mode).  It should be noted that stores
     to bspstore also affect the value of bsp.  Changing bspstore
     does not affect the number of dirty entries between bspstore
     and bsp, so changing bspstore by N words will also cause bsp
     to be changed by (roughly) N as well.  (It could be N-1 or N+1
     depending upon where the NaT collection bits fall.)

     OTOH, the Linux kernel provides read/write access to bsp (and
     currently read/write access to bspstore as well).  But it
     is definitely the case that if you change one, the other
     will change at the same time.  It is more useful to gdb to
     be able to change bsp.  So in order to prevent strange and
     undesirable things from happening when a dummy stack frame
     is popped (after calling an inferior function), we allow
     bspstore to be read, but not written.  (Note that popping
     a (generic) dummy stack frame causes all registers that
     were previously read from the inferior process to be written
     back.)  */

  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
         || regno == IA64_BSPSTORE_REGNUM;
}

void
supply_gregset (gregset_t *gregsetp)
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;

  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      regcache_raw_supply (current_regcache, regi,
			   (char *) (regp + (regi - IA64_GR0_REGNUM)));
    }

  /* FIXME: NAT collection bits are at index 32; gotta deal with these
     somehow... */

  regcache_raw_supply (current_regcache, IA64_PR_REGNUM, (char *) (regp + 33));

  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      regcache_raw_supply (current_regcache, regi,
			   (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
    }

  regcache_raw_supply (current_regcache, IA64_IP_REGNUM,
		       (char *) (regp + 42));
  regcache_raw_supply (current_regcache, IA64_CFM_REGNUM,
		       (char *) (regp + 43));
  regcache_raw_supply (current_regcache, IA64_PSR_REGNUM,
		       (char *) (regp + 44));
  regcache_raw_supply (current_regcache, IA64_RSC_REGNUM,
		       (char *) (regp + 45));
  regcache_raw_supply (current_regcache, IA64_BSP_REGNUM,
		       (char *) (regp + 46));
  regcache_raw_supply (current_regcache, IA64_BSPSTORE_REGNUM,
		       (char *) (regp + 47));
  regcache_raw_supply (current_regcache, IA64_RNAT_REGNUM,
		       (char *) (regp + 48));
  regcache_raw_supply (current_regcache, IA64_CCV_REGNUM,
		       (char *) (regp + 49));
  regcache_raw_supply (current_regcache, IA64_UNAT_REGNUM,
		       (char *) (regp + 50));
  regcache_raw_supply (current_regcache, IA64_FPSR_REGNUM,
		       (char *) (regp + 51));
  regcache_raw_supply (current_regcache, IA64_PFS_REGNUM,
		       (char *) (regp + 52));
  regcache_raw_supply (current_regcache, IA64_LC_REGNUM,
		       (char *) (regp + 53));
  regcache_raw_supply (current_regcache, IA64_EC_REGNUM,
		       (char *) (regp + 54));
}

void
fill_gregset (gregset_t *gregsetp, int regno)
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;

#define COPY_REG(_idx_,_regi_) \
  if ((regno == -1) || regno == _regi_) \
    regcache_raw_collect (current_regcache, _regi_, regp + _idx_)

  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      COPY_REG (regi - IA64_GR0_REGNUM, regi);
    }

  /* FIXME: NAT collection bits at index 32? */

  COPY_REG (33, IA64_PR_REGNUM);

  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
    }

  COPY_REG (42, IA64_IP_REGNUM);
  COPY_REG (43, IA64_CFM_REGNUM);
  COPY_REG (44, IA64_PSR_REGNUM);
  COPY_REG (45, IA64_RSC_REGNUM);
  COPY_REG (46, IA64_BSP_REGNUM);
  COPY_REG (47, IA64_BSPSTORE_REGNUM);
  COPY_REG (48, IA64_RNAT_REGNUM);
  COPY_REG (49, IA64_CCV_REGNUM);
  COPY_REG (50, IA64_UNAT_REGNUM);
  COPY_REG (51, IA64_FPSR_REGNUM);
  COPY_REG (52, IA64_PFS_REGNUM);
  COPY_REG (53, IA64_LC_REGNUM);
  COPY_REG (54, IA64_EC_REGNUM);
}

/*  Given a pointer to a floating point register set in /proc format
   (fpregset_t *), unpack the register contents and supply them as gdb's
   idea of the current floating point register values. */

void
supply_fpregset (fpregset_t *fpregsetp)
{
  int regi;
  char *from;

  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
    {
      from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
      regcache_raw_supply (current_regcache, regi, from);
    }
}

/*  Given a pointer to a floating point register set in /proc format
   (fpregset_t *), update the register specified by REGNO from gdb's idea
   of the current floating point register set.  If REGNO is -1, update
   them all. */

void
fill_fpregset (fpregset_t *fpregsetp, int regno)
{
  int regi;

  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
    {
      if ((regno == -1) || (regno == regi))
	regcache_raw_collect (current_regcache, regi,
			      &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
    }
}

#define IA64_PSR_DB (1UL << 24)
#define IA64_PSR_DD (1UL << 39)

static void
enable_watchpoints_in_psr (ptid_t ptid)
{
  CORE_ADDR psr;

  psr = read_register_pid (IA64_PSR_REGNUM, ptid);
  if (!(psr & IA64_PSR_DB))
    {
      psr |= IA64_PSR_DB;	/* Set the db bit - this enables hardware
			           watchpoints and breakpoints. */
      write_register_pid (IA64_PSR_REGNUM, psr, ptid);
    }
}

static long
fetch_debug_register (ptid_t ptid, int idx)
{
  long val;
  int tid;

  tid = TIDGET (ptid);
  if (tid == 0)
    tid = PIDGET (ptid);

  val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0);

  return val;
}

static void
store_debug_register (ptid_t ptid, int idx, long val)
{
  int tid;

  tid = TIDGET (ptid);
  if (tid == 0)
    tid = PIDGET (ptid);

  (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
}

static void
fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
{
  if (dbr_addr)
    *dbr_addr = fetch_debug_register (ptid, 2 * idx);
  if (dbr_mask)
    *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
}

static void
store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
{
  if (dbr_addr)
    store_debug_register (ptid, 2 * idx, *dbr_addr);
  if (dbr_mask)
    store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
}

static int
is_power_of_2 (int val)
{
  int i, onecount;

  onecount = 0;
  for (i = 0; i < 8 * sizeof (val); i++)
    if (val & (1 << i))
      onecount++;

  return onecount <= 1;
}

int
ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
{
  int idx;
  long dbr_addr, dbr_mask;
  int max_watchpoints = 4;

  if (len <= 0 || !is_power_of_2 (len))
    return -1;

  for (idx = 0; idx < max_watchpoints; idx++)
    {
      fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
      if ((dbr_mask & (0x3UL << 62)) == 0)
	{
	  /* Exit loop if both r and w bits clear */
	  break;
	}
    }

  if (idx == max_watchpoints)
    return -1;

  dbr_addr = (long) addr;
  dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
  dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
  switch (rw)
    {
    case hw_write:
      dbr_mask |= (1L << 62);			/* Set w bit */
      break;
    case hw_read:
      dbr_mask |= (1L << 63);			/* Set r bit */
      break;
    case hw_access:
      dbr_mask |= (3L << 62);			/* Set both r and w bits */
      break;
    default:
      return -1;
    }

  store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
  enable_watchpoints_in_psr (ptid);

  return 0;
}

int
ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
{
  int idx;
  long dbr_addr, dbr_mask;
  int max_watchpoints = 4;

  if (len <= 0 || !is_power_of_2 (len))
    return -1;

  for (idx = 0; idx < max_watchpoints; idx++)
    {
      fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
      if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
	{
	  dbr_addr = 0;
	  dbr_mask = 0;
	  store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
	  return 0;
	}
    }
  return -1;
}

int
ia64_linux_stopped_data_address (CORE_ADDR *addr_p)
{
  CORE_ADDR psr;
  int tid;
  struct siginfo siginfo;
  ptid_t ptid = inferior_ptid;

  tid = TIDGET(ptid);
  if (tid == 0)
    tid = PIDGET (ptid);
  
  errno = 0;
  ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);

  if (errno != 0 || siginfo.si_signo != SIGTRAP || 
      (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
    return 0;

  psr = read_register_pid (IA64_PSR_REGNUM, ptid);
  psr |= IA64_PSR_DD;	/* Set the dd bit - this will disable the watchpoint
                           for the next instruction */
  write_register_pid (IA64_PSR_REGNUM, psr, ptid);

  *addr_p = (CORE_ADDR)siginfo.si_addr;
  return 1;
}

int
ia64_linux_stopped_by_watchpoint (void)
{
  CORE_ADDR addr;
  return ia64_linux_stopped_data_address (&addr);
}

LONGEST 
ia64_linux_xfer_unwind_table (struct target_ops *ops,
			      enum target_object object,
			      const char *annex,
			      void *readbuf, const void *writebuf,
			      ULONGEST offset, LONGEST len)
{
  return syscall (__NR_getunwind, readbuf, len);
}
Commit	Line	Data
ca557f44 AC	1	/* Functions specific to running gdb native on IA-64 running
	2	GNU/Linux.
	3
949df321	4	Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
c5fa4245	5	Free Software Foundation, Inc.
16461d7d KB	6
	7	This file is part of GDB.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2 of the License, or
	12	(at your option) any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; if not, write to the Free Software
	21	Foundation, Inc., 59 Temple Place - Suite 330,
	22	Boston, MA 02111-1307, USA. */
	23
	24	#include "defs.h"
e162d11b	25	#include "gdb_string.h"
16461d7d KB	26	#include "inferior.h"
	27	#include "target.h"
	28	#include "gdbcore.h"
4e052eda	29	#include "regcache.h"
949df321	30	#include "ia64-tdep.h"
16461d7d KB	31
	32	#include <signal.h>
	33	#include <sys/ptrace.h>
2555fe1a	34	#include "gdb_wait.h"
16461d7d KB	35	#ifdef HAVE_SYS_REG_H
	36	#include <sys/reg.h>
	37	#endif
287a334e	38	#include <sys/syscall.h>
16461d7d KB	39	#include <sys/user.h>
	40
	41	#include <asm/ptrace_offsets.h>
	42	#include <sys/procfs.h>
	43
c60c0f5f MS	44	/* Prototypes for supply_gregset etc. */
	45	#include "gregset.h"
	46
16461d7d KB	47	/* These must match the order of the register names.
	48
	49	Some sort of lookup table is needed because the offsets associated
	50	with the registers are all over the board. */
	51
	52	static int u_offsets[] =
	53	{
	54	/* general registers */
	55	-1, /* gr0 not available; i.e, it's always zero */
	56	PT_R1,
	57	PT_R2,
	58	PT_R3,
	59	PT_R4,
	60	PT_R5,
	61	PT_R6,
	62	PT_R7,
	63	PT_R8,
	64	PT_R9,
	65	PT_R10,
	66	PT_R11,
	67	PT_R12,
	68	PT_R13,
	69	PT_R14,
	70	PT_R15,
	71	PT_R16,
	72	PT_R17,
	73	PT_R18,
	74	PT_R19,
	75	PT_R20,
	76	PT_R21,
	77	PT_R22,
	78	PT_R23,
	79	PT_R24,
	80	PT_R25,
	81	PT_R26,
	82	PT_R27,
	83	PT_R28,
	84	PT_R29,
	85	PT_R30,
	86	PT_R31,
	87	/* gr32 through gr127 not directly available via the ptrace interface */
	88	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	89	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	90	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	91	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	92	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	93	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	94	/* Floating point registers */
	95	-1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
	96	PT_F2,
	97	PT_F3,
	98	PT_F4,
	99	PT_F5,
	100	PT_F6,
	101	PT_F7,
	102	PT_F8,
	103	PT_F9,
	104	PT_F10,
	105	PT_F11,
	106	PT_F12,
	107	PT_F13,
	108	PT_F14,
	109	PT_F15,
	110	PT_F16,
111	PT_F17,
112	PT_F18,
113	PT_F19,
114	PT_F20,
115	PT_F21,
116	PT_F22,
117	PT_F23,
118	PT_F24,
119	PT_F25,
120	PT_F26,
121	PT_F27,
122	PT_F28,
123	PT_F29,
124	PT_F30,
125	PT_F31,
126	PT_F32,
127	PT_F33,
128	PT_F34,
129	PT_F35,
130	PT_F36,
131	PT_F37,
132	PT_F38,
133	PT_F39,
134	PT_F40,
135	PT_F41,
136	PT_F42,
137	PT_F43,
138	PT_F44,
139	PT_F45,
140	PT_F46,
141	PT_F47,
142	PT_F48,
143	PT_F49,
144	PT_F50,
145	PT_F51,
146	PT_F52,
147	PT_F53,
148	PT_F54,
149	PT_F55,
150	PT_F56,
151	PT_F57,
152	PT_F58,
153	PT_F59,
154	PT_F60,
155	PT_F61,
156	PT_F62,
157	PT_F63,
158	PT_F64,
159	PT_F65,
160	PT_F66,
161	PT_F67,
162	PT_F68,
163	PT_F69,
164	PT_F70,
165	PT_F71,
166	PT_F72,
167	PT_F73,
168	PT_F74,
169	PT_F75,
170	PT_F76,
171	PT_F77,
172	PT_F78,
173	PT_F79,
174	PT_F80,
175	PT_F81,
176	PT_F82,
177	PT_F83,
178	PT_F84,
179	PT_F85,
180	PT_F86,
181	PT_F87,
182	PT_F88,
183	PT_F89,
184	PT_F90,
185	PT_F91,
186	PT_F92,
187	PT_F93,
188	PT_F94,
189	PT_F95,
190	PT_F96,
191	PT_F97,
192	PT_F98,
193	PT_F99,
194	PT_F100,
195	PT_F101,
196	PT_F102,
197	PT_F103,
198	PT_F104,
199	PT_F105,
200	PT_F106,
201	PT_F107,
202	PT_F108,
203	PT_F109,
204	PT_F110,
205	PT_F111,
206	PT_F112,
207	PT_F113,
208	PT_F114,
209	PT_F115,
210	PT_F116,
211	PT_F117,
212	PT_F118,
213	PT_F119,
214	PT_F120,
215	PT_F121,
216	PT_F122,
217	PT_F123,
218	PT_F124,
219	PT_F125,
220	PT_F126,
221	PT_F127,
222	/* predicate registers - we don't fetch these individually */
223	-1, -1, -1, -1, -1, -1, -1, -1,
224	-1, -1, -1, -1, -1, -1, -1, -1,
225	-1, -1, -1, -1, -1, -1, -1, -1,
226	-1, -1, -1, -1, -1, -1, -1, -1,
227	-1, -1, -1, -1, -1, -1, -1, -1,
228	-1, -1, -1, -1, -1, -1, -1, -1,
229	-1, -1, -1, -1, -1, -1, -1, -1,
230	-1, -1, -1, -1, -1, -1, -1, -1,
231	/* branch registers */
232	PT_B0,
233	PT_B1,
234	PT_B2,
235	PT_B3,
236	PT_B4,
237	PT_B5,
238	PT_B6,
239	PT_B7,
240	/* virtual frame pointer and virtual return address pointer */
241	-1, -1,
242	/* other registers */
243	PT_PR,
244	PT_CR_IIP, /* ip */
245	PT_CR_IPSR, /* psr */
9ac12c35	246	PT_CFM, /* cfm */
16461d7d KB	247	/* kernel registers not visible via ptrace interface (?) */
	248	-1, -1, -1, -1, -1, -1, -1, -1,
	249	/* hole */
	250	-1, -1, -1, -1, -1, -1, -1, -1,
	251	PT_AR_RSC,
	252	PT_AR_BSP,
	253	PT_AR_BSPSTORE,
	254	PT_AR_RNAT,
	255	-1,
	256	-1, /* Not available: FCR, IA32 floating control register */
	257	-1, -1,
	258	-1, /* Not available: EFLAG */
	259	-1, /* Not available: CSD */
	260	-1, /* Not available: SSD */
	261	-1, /* Not available: CFLG */
	262	-1, /* Not available: FSR */
	263	-1, /* Not available: FIR */
	264	-1, /* Not available: FDR */
	265	-1,
	266	PT_AR_CCV,
	267	-1, -1, -1,
	268	PT_AR_UNAT,
	269	-1, -1, -1,
	270	PT_AR_FPSR,
	271	-1, -1, -1,
	272	-1, /* Not available: ITC */
	273	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	274	-1, -1, -1, -1, -1, -1, -1, -1, -1,
	275	PT_AR_PFS,
	276	PT_AR_LC,
	277	-1, /* Not available: EC, the Epilog Count register */
	278	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	279	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	280	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	281	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	282	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	283	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	284	-1,
	285	/* nat bits - not fetched directly; instead we obtain these bits from
	286	either rnat or unat or from memory. */
	287	-1, -1, -1, -1, -1, -1, -1, -1,
	288	-1, -1, -1, -1, -1, -1, -1, -1,
	289	-1, -1, -1, -1, -1, -1, -1, -1,
	290	-1, -1, -1, -1, -1, -1, -1, -1,
	291	-1, -1, -1, -1, -1, -1, -1, -1,
	292	-1, -1, -1, -1, -1, -1, -1, -1,
	293	-1, -1, -1, -1, -1, -1, -1, -1,
	294	-1, -1, -1, -1, -1, -1, -1, -1,
	295	-1, -1, -1, -1, -1, -1, -1, -1,
	296	-1, -1, -1, -1, -1, -1, -1, -1,
	297	-1, -1, -1, -1, -1, -1, -1, -1,
	298	-1, -1, -1, -1, -1, -1, -1, -1,
	299	-1, -1, -1, -1, -1, -1, -1, -1,
	300	-1, -1, -1, -1, -1, -1, -1, -1,
	301	-1, -1, -1, -1, -1, -1, -1, -1,
	302	-1, -1, -1, -1, -1, -1, -1, -1,
	303	};
	304
	305	CORE_ADDR
fba45db2	306	register_addr (int regno, CORE_ADDR blockend)
16461d7d KB	307	{
	308	CORE_ADDR addr;
	309
	310	if (regno < 0 \|\| regno >= NUM_REGS)
8a3fe4f8	311	error (_("Invalid register number %d."), regno);
16461d7d KB	312
	313	if (u_offsets[regno] == -1)
	314	addr = 0;
	315	else
	316	addr = (CORE_ADDR) u_offsets[regno];
	317
	318	return addr;
	319	}
	320
	321	int ia64_cannot_fetch_register (regno)
	322	int regno;
	323	{
	324	return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1;
	325	}
	326
	327	int ia64_cannot_store_register (regno)
	328	int regno;
	329	{
	330	/* Rationale behind not permitting stores to bspstore...
	331
	332	The IA-64 architecture provides bspstore and bsp which refer
	333	memory locations in the RSE's backing store. bspstore is the
	334	next location which will be written when the RSE needs to write
	335	to memory. bsp is the address at which r32 in the current frame
	336	would be found if it were written to the backing store.
	337
	338	The IA-64 architecture provides read-only access to bsp and
	339	read/write access to bspstore (but only when the RSE is in
	340	the enforced lazy mode). It should be noted that stores
	341	to bspstore also affect the value of bsp. Changing bspstore
	342	does not affect the number of dirty entries between bspstore
	343	and bsp, so changing bspstore by N words will also cause bsp
	344	to be changed by (roughly) N as well. (It could be N-1 or N+1
	345	depending upon where the NaT collection bits fall.)
	346
92362027	347	OTOH, the Linux kernel provides read/write access to bsp (and
16461d7d KB	348	currently read/write access to bspstore as well). But it
	349	is definitely the case that if you change one, the other
	350	will change at the same time. It is more useful to gdb to
	351	be able to change bsp. So in order to prevent strange and
	352	undesirable things from happening when a dummy stack frame
	353	is popped (after calling an inferior function), we allow
	354	bspstore to be read, but not written. (Note that popping
	355	a (generic) dummy stack frame causes all registers that
	356	were previously read from the inferior process to be written
	357	back.) */
	358
	359	return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1
	360	\|\| regno == IA64_BSPSTORE_REGNUM;
	361	}
	362
	363	void
fba45db2	364	supply_gregset (gregset_t *gregsetp)
16461d7d KB	365	{
	366	int regi;
	367	greg_t regp = (greg_t ) gregsetp;
	368
	369	for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
	370	{
23a6d369 AC	371	regcache_raw_supply (current_regcache, regi,
23a6d369 AC	372	(char *) (regp + (regi - IA64_GR0_REGNUM)));
16461d7d KB	373	}
	374
	375	/* FIXME: NAT collection bits are at index 32; gotta deal with these
	376	somehow... */
	377
23a6d369	378	regcache_raw_supply (current_regcache, IA64_PR_REGNUM, (char *) (regp + 33));
16461d7d KB	379
	380	for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
	381	{
23a6d369 AC	382	regcache_raw_supply (current_regcache, regi,
23a6d369 AC	383	(char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
16461d7d KB	384	}
16461d7d KB	385
23a6d369 AC	386	regcache_raw_supply (current_regcache, IA64_IP_REGNUM,
	387	(char *) (regp + 42));
	388	regcache_raw_supply (current_regcache, IA64_CFM_REGNUM,
	389	(char *) (regp + 43));
	390	regcache_raw_supply (current_regcache, IA64_PSR_REGNUM,
	391	(char *) (regp + 44));
	392	regcache_raw_supply (current_regcache, IA64_RSC_REGNUM,
	393	(char *) (regp + 45));
	394	regcache_raw_supply (current_regcache, IA64_BSP_REGNUM,
	395	(char *) (regp + 46));
	396	regcache_raw_supply (current_regcache, IA64_BSPSTORE_REGNUM,
	397	(char *) (regp + 47));
	398	regcache_raw_supply (current_regcache, IA64_RNAT_REGNUM,
	399	(char *) (regp + 48));
	400	regcache_raw_supply (current_regcache, IA64_CCV_REGNUM,
	401	(char *) (regp + 49));
	402	regcache_raw_supply (current_regcache, IA64_UNAT_REGNUM,
	403	(char *) (regp + 50));
	404	regcache_raw_supply (current_regcache, IA64_FPSR_REGNUM,
	405	(char *) (regp + 51));
	406	regcache_raw_supply (current_regcache, IA64_PFS_REGNUM,
	407	(char *) (regp + 52));
	408	regcache_raw_supply (current_regcache, IA64_LC_REGNUM,
	409	(char *) (regp + 53));
	410	regcache_raw_supply (current_regcache, IA64_EC_REGNUM,
	411	(char *) (regp + 54));
16461d7d KB	412	}
	413
	414	void
fba45db2	415	fill_gregset (gregset_t *gregsetp, int regno)
16461d7d	416	{
76d689a6 KB	417	int regi;
	418	greg_t regp = (greg_t ) gregsetp;
	419
	420	#define COPY_REG(_idx_,_regi_) \
	421	if ((regno == -1) \|\| regno == _regi_) \
e0e25c6c	422	regcache_raw_collect (current_regcache, _regi_, regp + _idx_)
76d689a6 KB	423
	424	for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
	425	{
	426	COPY_REG (regi - IA64_GR0_REGNUM, regi);
	427	}
	428
	429	/* FIXME: NAT collection bits at index 32? */
	430
	431	COPY_REG (33, IA64_PR_REGNUM);
	432
	433	for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
	434	{
	435	COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
	436	}
	437
	438	COPY_REG (42, IA64_IP_REGNUM);
	439	COPY_REG (43, IA64_CFM_REGNUM);
	440	COPY_REG (44, IA64_PSR_REGNUM);
	441	COPY_REG (45, IA64_RSC_REGNUM);
	442	COPY_REG (46, IA64_BSP_REGNUM);
	443	COPY_REG (47, IA64_BSPSTORE_REGNUM);
	444	COPY_REG (48, IA64_RNAT_REGNUM);
	445	COPY_REG (49, IA64_CCV_REGNUM);
	446	COPY_REG (50, IA64_UNAT_REGNUM);
	447	COPY_REG (51, IA64_FPSR_REGNUM);
	448	COPY_REG (52, IA64_PFS_REGNUM);
	449	COPY_REG (53, IA64_LC_REGNUM);
	450	COPY_REG (54, IA64_EC_REGNUM);
	451	}
	452
	453	/* Given a pointer to a floating point register set in /proc format
	454	(fpregset_t *), unpack the register contents and supply them as gdb's
	455	idea of the current floating point register values. */
	456
	457	void
fba45db2	458	supply_fpregset (fpregset_t *fpregsetp)
76d689a6	459	{
52f0bd74	460	int regi;
76d689a6 KB	461	char *from;
	462
	463	for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
	464	{
	465	from = (char ) &((fpregsetp)[regi - IA64_FR0_REGNUM]);
23a6d369	466	regcache_raw_supply (current_regcache, regi, from);
76d689a6 KB	467	}
	468	}
	469
	470	/* Given a pointer to a floating point register set in /proc format
	471	(fpregset_t *), update the register specified by REGNO from gdb's idea
	472	of the current floating point register set. If REGNO is -1, update
	473	them all. */
	474
	475	void
fba45db2	476	fill_fpregset (fpregset_t *fpregsetp, int regno)
76d689a6 KB	477	{
76d689a6 KB	478	int regi;
76d689a6 KB	479
	480	for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
	481	{
	482	if ((regno == -1) \|\| (regno == regi))
e0e25c6c KB	483	regcache_raw_collect (current_regcache, regi,
e0e25c6c KB	484	&((*fpregsetp)[regi - IA64_FR0_REGNUM]));
76d689a6	485	}
16461d7d	486	}
acf7b9e1 KB	487
	488	#define IA64_PSR_DB (1UL << 24)
	489	#define IA64_PSR_DD (1UL << 39)
	490
	491	static void
39f77062	492	enable_watchpoints_in_psr (ptid_t ptid)
acf7b9e1 KB	493	{
	494	CORE_ADDR psr;
	495
39f77062	496	psr = read_register_pid (IA64_PSR_REGNUM, ptid);
acf7b9e1 KB	497	if (!(psr & IA64_PSR_DB))
	498	{
	499	psr \|= IA64_PSR_DB; /* Set the db bit - this enables hardware
	500	watchpoints and breakpoints. */
39f77062	501	write_register_pid (IA64_PSR_REGNUM, psr, ptid);
acf7b9e1 KB	502	}
	503	}
	504
	505	static long
39f77062	506	fetch_debug_register (ptid_t ptid, int idx)
acf7b9e1 KB	507	{
	508	long val;
	509	int tid;
	510
39f77062	511	tid = TIDGET (ptid);
acf7b9e1	512	if (tid == 0)
39f77062	513	tid = PIDGET (ptid);
acf7b9e1	514
c5fa4245	515	val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0);
acf7b9e1 KB	516
	517	return val;
	518	}
	519
	520	static void
39f77062	521	store_debug_register (ptid_t ptid, int idx, long val)
acf7b9e1 KB	522	{
	523	int tid;
	524
39f77062	525	tid = TIDGET (ptid);
acf7b9e1	526	if (tid == 0)
39f77062	527	tid = PIDGET (ptid);
acf7b9e1	528
c5fa4245	529	(void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
acf7b9e1 KB	530	}
	531
	532	static void
39f77062	533	fetch_debug_register_pair (ptid_t ptid, int idx, long dbr_addr, long dbr_mask)
acf7b9e1 KB	534	{
acf7b9e1 KB	535	if (dbr_addr)
39f77062	536	dbr_addr = fetch_debug_register (ptid, 2 idx);
acf7b9e1	537	if (dbr_mask)
39f77062	538	dbr_mask = fetch_debug_register (ptid, 2 idx + 1);
acf7b9e1 KB	539	}
	540
	541	static void
39f77062	542	store_debug_register_pair (ptid_t ptid, int idx, long dbr_addr, long dbr_mask)
acf7b9e1 KB	543	{
acf7b9e1 KB	544	if (dbr_addr)
39f77062	545	store_debug_register (ptid, 2 * idx, *dbr_addr);
acf7b9e1	546	if (dbr_mask)
39f77062	547	store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
acf7b9e1 KB	548	}
	549
	550	static int
	551	is_power_of_2 (int val)
	552	{
	553	int i, onecount;
	554
	555	onecount = 0;
	556	for (i = 0; i < 8 * sizeof (val); i++)
	557	if (val & (1 << i))
	558	onecount++;
	559
	560	return onecount <= 1;
	561	}
	562
	563	int
39f77062	564	ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
acf7b9e1 KB	565	{
	566	int idx;
	567	long dbr_addr, dbr_mask;
	568	int max_watchpoints = 4;
	569
	570	if (len <= 0 \|\| !is_power_of_2 (len))
	571	return -1;
	572
	573	for (idx = 0; idx < max_watchpoints; idx++)
	574	{
39f77062	575	fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
acf7b9e1 KB	576	if ((dbr_mask & (0x3UL << 62)) == 0)
	577	{
	578	/* Exit loop if both r and w bits clear */
	579	break;
	580	}
	581	}
	582
	583	if (idx == max_watchpoints)
	584	return -1;
	585
	586	dbr_addr = (long) addr;
	587	dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
	588	dbr_mask \|= 0x0800000000000000L; /* Only match privilege level 3 */
	589	switch (rw)
	590	{
	591	case hw_write:
	592	dbr_mask \|= (1L << 62); /* Set w bit */
	593	break;
	594	case hw_read:
	595	dbr_mask \|= (1L << 63); /* Set r bit */
	596	break;
	597	case hw_access:
	598	dbr_mask \|= (3L << 62); /* Set both r and w bits */
	599	break;
	600	default:
	601	return -1;
	602	}
	603
39f77062 KB	604	store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
39f77062 KB	605	enable_watchpoints_in_psr (ptid);
acf7b9e1 KB	606
	607	return 0;
	608	}
	609
	610	int
39f77062	611	ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
acf7b9e1 KB	612	{
	613	int idx;
	614	long dbr_addr, dbr_mask;
	615	int max_watchpoints = 4;
	616
	617	if (len <= 0 \|\| !is_power_of_2 (len))
	618	return -1;
	619
	620	for (idx = 0; idx < max_watchpoints; idx++)
	621	{
39f77062	622	fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
acf7b9e1 KB	623	if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
	624	{
	625	dbr_addr = 0;
	626	dbr_mask = 0;
39f77062	627	store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
acf7b9e1 KB	628	return 0;
	629	}
	630	}
	631	return -1;
	632	}
	633
4aa7a7f5 JJ	634	int
4aa7a7f5 JJ	635	ia64_linux_stopped_data_address (CORE_ADDR *addr_p)
acf7b9e1 KB	636	{
	637	CORE_ADDR psr;
	638	int tid;
	639	struct siginfo siginfo;
4aa7a7f5	640	ptid_t ptid = inferior_ptid;
acf7b9e1	641
39f77062	642	tid = TIDGET(ptid);
acf7b9e1	643	if (tid == 0)
39f77062	644	tid = PIDGET (ptid);
acf7b9e1 KB	645
acf7b9e1 KB	646	errno = 0;
c5fa4245	647	ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);
acf7b9e1	648
705b278b JJ	649	if (errno != 0 \|\| siginfo.si_signo != SIGTRAP \|\|
705b278b JJ	650	(siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
acf7b9e1 KB	651	return 0;
acf7b9e1 KB	652
39f77062	653	psr = read_register_pid (IA64_PSR_REGNUM, ptid);
acf7b9e1 KB	654	psr \|= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
acf7b9e1 KB	655	for the next instruction */
39f77062	656	write_register_pid (IA64_PSR_REGNUM, psr, ptid);
acf7b9e1	657
4aa7a7f5 JJ	658	*addr_p = (CORE_ADDR)siginfo.si_addr;
	659	return 1;
	660	}
	661
	662	int
	663	ia64_linux_stopped_by_watchpoint (void)
	664	{
	665	CORE_ADDR addr;
	666	return ia64_linux_stopped_data_address (&addr);
acf7b9e1	667	}
287a334e JJ	668
	669	LONGEST
	670	ia64_linux_xfer_unwind_table (struct target_ops *ops,
	671	enum target_object object,
	672	const char *annex,
	673	void readbuf, const void writebuf,
	674	ULONGEST offset, LONGEST len)
	675	{
	676	return syscall (__NR_getunwind, readbuf, len);
	677	}