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2012-03-28 Pedro Alves <palves@redhat.com>
[deliverable/binutils-gdb.git] / gdb / ia64-linux-nat.c
CommitLineData
ca557f44
AC		 1/* Functions specific to running gdb native on IA-64 running
2 GNU/Linux.
3
0b302171 4 Copyright (C) 1999-2012 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
16461d7d
KB		 11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
16461d7d
KB		 20
21#include "defs.h"
e162d11b 22#include "gdb_string.h"
16461d7d
KB		 23#include "inferior.h"
24#include "target.h"
25#include "gdbcore.h"
4e052eda 26#include "regcache.h"
949df321 27#include "ia64-tdep.h"
10d6c8cd 28#include "linux-nat.h"
16461d7d
KB		 29
30#include <signal.h>
31#include <sys/ptrace.h>
2555fe1a 32#include "gdb_wait.h"
16461d7d
KB		 33#ifdef HAVE_SYS_REG_H
34#include <sys/reg.h>
35#endif
287a334e 36#include <sys/syscall.h>
16461d7d
KB		 37#include <sys/user.h>
38
39#include <asm/ptrace_offsets.h>
40#include <sys/procfs.h>
41
1777feb0 42/* Prototypes for supply_gregset etc. */
c60c0f5f
MS		 43#include "gregset.h"
44
16461d7d
KB		 45/* These must match the order of the register names.
46
47 Some sort of lookup table is needed because the offsets associated
48 with the registers are all over the board. */
49
50static int u_offsets[] =
51 {
52 /* general registers */
1777feb0 53 -1, /* gr0 not available; i.e, it's always zero. */
16461d7d
KB		 54 PT_R1,
55 PT_R2,
56 PT_R3,
57 PT_R4,
58 PT_R5,
59 PT_R6,
60 PT_R7,
61 PT_R8,
62 PT_R9,
63 PT_R10,
64 PT_R11,
65 PT_R12,
66 PT_R13,
67 PT_R14,
68 PT_R15,
69 PT_R16,
70 PT_R17,
71 PT_R18,
72 PT_R19,
73 PT_R20,
74 PT_R21,
75 PT_R22,
76 PT_R23,
77 PT_R24,
78 PT_R25,
79 PT_R26,
80 PT_R27,
81 PT_R28,
82 PT_R29,
83 PT_R30,
84 PT_R31,
1777feb0 85 /* gr32 through gr127 not directly available via the ptrace interface. */
16461d7d
KB		 86 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 /* Floating point registers */
1777feb0 93 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
16461d7d
KB		 94 PT_F2,
95 PT_F3,
96 PT_F4,
97 PT_F5,
98 PT_F6,
99 PT_F7,
100 PT_F8,
101 PT_F9,
102 PT_F10,
103 PT_F11,
104 PT_F12,
105 PT_F13,
106 PT_F14,
107 PT_F15,
108 PT_F16,
109 PT_F17,
110 PT_F18,
111 PT_F19,
112 PT_F20,
113 PT_F21,
114 PT_F22,
115 PT_F23,
116 PT_F24,
117 PT_F25,
118 PT_F26,
119 PT_F27,
120 PT_F28,
121 PT_F29,
122 PT_F30,
123 PT_F31,
124 PT_F32,
125 PT_F33,
126 PT_F34,
127 PT_F35,
128 PT_F36,
129 PT_F37,
130 PT_F38,
131 PT_F39,
132 PT_F40,
133 PT_F41,
134 PT_F42,
135 PT_F43,
136 PT_F44,
137 PT_F45,
138 PT_F46,
139 PT_F47,
140 PT_F48,
141 PT_F49,
142 PT_F50,
143 PT_F51,
144 PT_F52,
145 PT_F53,
146 PT_F54,
147 PT_F55,
148 PT_F56,
149 PT_F57,
150 PT_F58,
151 PT_F59,
152 PT_F60,
153 PT_F61,
154 PT_F62,
155 PT_F63,
156 PT_F64,
157 PT_F65,
158 PT_F66,
159 PT_F67,
160 PT_F68,
161 PT_F69,
162 PT_F70,
163 PT_F71,
164 PT_F72,
165 PT_F73,
166 PT_F74,
167 PT_F75,
168 PT_F76,
169 PT_F77,
170 PT_F78,
171 PT_F79,
172 PT_F80,
173 PT_F81,
174 PT_F82,
175 PT_F83,
176 PT_F84,
177 PT_F85,
178 PT_F86,
179 PT_F87,
180 PT_F88,
181 PT_F89,
182 PT_F90,
183 PT_F91,
184 PT_F92,
185 PT_F93,
186 PT_F94,
187 PT_F95,
188 PT_F96,
189 PT_F97,
190 PT_F98,
191 PT_F99,
192 PT_F100,
193 PT_F101,
194 PT_F102,
195 PT_F103,
196 PT_F104,
197 PT_F105,
198 PT_F106,
199 PT_F107,
200 PT_F108,
201 PT_F109,
202 PT_F110,
203 PT_F111,
204 PT_F112,
205 PT_F113,
206 PT_F114,
207 PT_F115,
208 PT_F116,
209 PT_F117,
210 PT_F118,
211 PT_F119,
212 PT_F120,
213 PT_F121,
214 PT_F122,
215 PT_F123,
216 PT_F124,
217 PT_F125,
218 PT_F126,
219 PT_F127,
1777feb0 220 /* Predicate registers - we don't fetch these individually. */
16461d7d
KB		 221 -1, -1, -1, -1, -1, -1, -1, -1,
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 /* branch registers */
230 PT_B0,
231 PT_B1,
232 PT_B2,
233 PT_B3,
234 PT_B4,
235 PT_B5,
236 PT_B6,
237 PT_B7,
1777feb0 238 /* Virtual frame pointer and virtual return address pointer. */
16461d7d
KB		 239 -1, -1,
240 /* other registers */
241 PT_PR,
242 PT_CR_IIP, /* ip */
243 PT_CR_IPSR, /* psr */
9ac12c35 244 PT_CFM, /* cfm */
1777feb0 245 /* kernel registers not visible via ptrace interface (?) */
16461d7d
KB		 246 -1, -1, -1, -1, -1, -1, -1, -1,
247 /* hole */
248 -1, -1, -1, -1, -1, -1, -1, -1,
249 PT_AR_RSC,
250 PT_AR_BSP,
251 PT_AR_BSPSTORE,
252 PT_AR_RNAT,
253 -1,
1777feb0 254 -1, /* Not available: FCR, IA32 floating control register. */
16461d7d
KB		 255 -1, -1,
256 -1, /* Not available: EFLAG */
257 -1, /* Not available: CSD */
258 -1, /* Not available: SSD */
259 -1, /* Not available: CFLG */
260 -1, /* Not available: FSR */
261 -1, /* Not available: FIR */
262 -1, /* Not available: FDR */
263 -1,
264 PT_AR_CCV,
265 -1, -1, -1,
266 PT_AR_UNAT,
267 -1, -1, -1,
268 PT_AR_FPSR,
269 -1, -1, -1,
270 -1, /* Not available: ITC */
271 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
272 -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 PT_AR_PFS,
274 PT_AR_LC,
4a6510ba 275 PT_AR_EC,
16461d7d
KB		 276 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1,
283 /* nat bits - not fetched directly; instead we obtain these bits from
1777feb0 284 either rnat or unat or from memory. */
16461d7d
KB		 285 -1, -1, -1, -1, -1, -1, -1, -1,
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 };
302
74174d2e 303static CORE_ADDR
2685572f 304ia64_register_addr (struct gdbarch *gdbarch, int regno)
16461d7d
KB		 305{
306 CORE_ADDR addr;
307
2685572f 308 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
8a3fe4f8 309 error (_("Invalid register number %d."), regno);
16461d7d
KB		 310
311 if (u_offsets[regno] == -1)
312 addr = 0;
313 else
314 addr = (CORE_ADDR) u_offsets[regno];
315
316 return addr;
317}
318
74174d2e 319static int
2685572f 320ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
16461d7d 321{
f57d151a 322 return regno < 0
2685572f 323 || regno >= gdbarch_num_regs (gdbarch)
f57d151a 324 || u_offsets[regno] == -1;
16461d7d
KB		 325}
326
74174d2e 327static int
2685572f 328ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
16461d7d
KB		 329{
330 /* Rationale behind not permitting stores to bspstore...
331
332 The IA-64 architecture provides bspstore and bsp which refer
333 memory locations in the RSE's backing store. bspstore is the
334 next location which will be written when the RSE needs to write
335 to memory. bsp is the address at which r32 in the current frame
336 would be found if it were written to the backing store.
337
338 The IA-64 architecture provides read-only access to bsp and
339 read/write access to bspstore (but only when the RSE is in
340 the enforced lazy mode). It should be noted that stores
341 to bspstore also affect the value of bsp. Changing bspstore
342 does not affect the number of dirty entries between bspstore
343 and bsp, so changing bspstore by N words will also cause bsp
344 to be changed by (roughly) N as well. (It could be N-1 or N+1
345 depending upon where the NaT collection bits fall.)
346
92362027 347 OTOH, the Linux kernel provides read/write access to bsp (and
16461d7d
KB		 348 currently read/write access to bspstore as well). But it
349 is definitely the case that if you change one, the other
350 will change at the same time. It is more useful to gdb to
351 be able to change bsp. So in order to prevent strange and
352 undesirable things from happening when a dummy stack frame
353 is popped (after calling an inferior function), we allow
354 bspstore to be read, but not written. (Note that popping
355 a (generic) dummy stack frame causes all registers that
356 were previously read from the inferior process to be written
357 back.) */
358
f57d151a 359 return regno < 0
2685572f 360 || regno >= gdbarch_num_regs (gdbarch)
f57d151a 361 || u_offsets[regno] == -1
16461d7d
KB		 362 || regno == IA64_BSPSTORE_REGNUM;
363}
364
365void
7f7fe91e 366supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
16461d7d
KB		 367{
368 int regi;
7f7fe91e 369 const greg_t *regp = (const greg_t *) gregsetp;
16461d7d
KB		 370
371 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
372 {
7f7fe91e 373 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
16461d7d
KB		 374 }
375
376 /* FIXME: NAT collection bits are at index 32; gotta deal with these
1777feb0 377 somehow... */
16461d7d 378
7f7fe91e 379 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
16461d7d
KB		 380
381 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
382 {
7f7fe91e
UW		 383 regcache_raw_supply (regcache, regi,
384 regp + 34 + (regi - IA64_BR0_REGNUM));
16461d7d
KB		 385 }
386
7f7fe91e
UW		 387 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
388 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
389 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
390 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
391 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
392 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
393 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
394 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
395 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
396 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
397 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
398 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
399 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
16461d7d
KB		 400}
401
402void
7f7fe91e 403fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
16461d7d 404{
76d689a6
KB		 405 int regi;
406 greg_t *regp = (greg_t *) gregsetp;
407
408#define COPY_REG(_idx_,_regi_) \
409 if ((regno == -1) || regno == _regi_) \
7f7fe91e 410 regcache_raw_collect (regcache, _regi_, regp + _idx_)
76d689a6
KB		 411
412 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
413 {
414 COPY_REG (regi - IA64_GR0_REGNUM, regi);
415 }
416
1777feb0 417 /* FIXME: NAT collection bits at index 32? */
76d689a6
KB		 418
419 COPY_REG (33, IA64_PR_REGNUM);
420
421 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
422 {
423 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
424 }
425
426 COPY_REG (42, IA64_IP_REGNUM);
427 COPY_REG (43, IA64_CFM_REGNUM);
428 COPY_REG (44, IA64_PSR_REGNUM);
429 COPY_REG (45, IA64_RSC_REGNUM);
430 COPY_REG (46, IA64_BSP_REGNUM);
431 COPY_REG (47, IA64_BSPSTORE_REGNUM);
432 COPY_REG (48, IA64_RNAT_REGNUM);
433 COPY_REG (49, IA64_CCV_REGNUM);
434 COPY_REG (50, IA64_UNAT_REGNUM);
435 COPY_REG (51, IA64_FPSR_REGNUM);
436 COPY_REG (52, IA64_PFS_REGNUM);
437 COPY_REG (53, IA64_LC_REGNUM);
438 COPY_REG (54, IA64_EC_REGNUM);
439}
440
441/* Given a pointer to a floating point register set in /proc format
442 (fpregset_t *), unpack the register contents and supply them as gdb's
1777feb0 443 idea of the current floating point register values. */
76d689a6
KB		 444
445void
7f7fe91e 446supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
76d689a6 447{
52f0bd74 448 int regi;
7f7fe91e 449 const char *from;
76d689a6
KB		 450
451 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
452 {
7f7fe91e
UW		 453 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
454 regcache_raw_supply (regcache, regi, from);
76d689a6
KB		 455 }
456}
457
458/* Given a pointer to a floating point register set in /proc format
459 (fpregset_t *), update the register specified by REGNO from gdb's idea
460 of the current floating point register set. If REGNO is -1, update
1777feb0 461 them all. */
76d689a6
KB		 462
463void
7f7fe91e
UW		 464fill_fpregset (const struct regcache *regcache,
465 fpregset_t *fpregsetp, int regno)
76d689a6
KB		 466{
467 int regi;
76d689a6
KB		 468
469 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
470 {
471 if ((regno == -1) || (regno == regi))
7f7fe91e 472 regcache_raw_collect (regcache, regi,
e0e25c6c 473 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
76d689a6 474 }
16461d7d 475}
acf7b9e1
KB		 476
477#define IA64_PSR_DB (1UL << 24)
478#define IA64_PSR_DD (1UL << 39)
479
480static void
9f0bdab8 481enable_watchpoints_in_psr (ptid_t ptid)
acf7b9e1 482{
9f0bdab8 483 struct regcache *regcache = get_thread_regcache (ptid);
7b86a1b8 484 ULONGEST psr;
acf7b9e1 485
7b86a1b8 486 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1
KB		 487 if (!(psr & IA64_PSR_DB))
488 {
489 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
1777feb0 490 watchpoints and breakpoints. */
7b86a1b8 491 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1
KB		 492 }
493}
494
9f0bdab8 495static long debug_registers[8];
acf7b9e1
KB		 496
497static void
39f77062 498store_debug_register (ptid_t ptid, int idx, long val)
acf7b9e1
KB		 499{
500 int tid;
501
39f77062 502 tid = TIDGET (ptid);
acf7b9e1 503 if (tid == 0)
39f77062 504 tid = PIDGET (ptid);
acf7b9e1 505
c5fa4245 506 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
acf7b9e1
KB		 507}
508
acf7b9e1 509static void
1777feb0
MS		 510store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
511 long *dbr_mask)
acf7b9e1
KB		 512{
513 if (dbr_addr)
39f77062 514 store_debug_register (ptid, 2 * idx, *dbr_addr);
acf7b9e1 515 if (dbr_mask)
39f77062 516 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
acf7b9e1
KB		 517}
518
519static int
520is_power_of_2 (int val)
521{
522 int i, onecount;
523
524 onecount = 0;
525 for (i = 0; i < 8 * sizeof (val); i++)
526 if (val & (1 << i))
527 onecount++;
528
529 return onecount <= 1;
530}
531
74174d2e 532static int
0cf6dd15
TJB		 533ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
534 struct expression *cond)
acf7b9e1 535{
9f0bdab8 536 struct lwp_info *lp;
acf7b9e1
KB		 537 int idx;
538 long dbr_addr, dbr_mask;
539 int max_watchpoints = 4;
540
541 if (len <= 0 || !is_power_of_2 (len))
542 return -1;
543
544 for (idx = 0; idx < max_watchpoints; idx++)
545 {
9f0bdab8 546 dbr_mask = debug_registers[idx * 2 + 1];
acf7b9e1
KB		 547 if ((dbr_mask & (0x3UL << 62)) == 0)
548 {
1777feb0 549 /* Exit loop if both r and w bits clear. */
acf7b9e1
KB		 550 break;
551 }
552 }
553
554 if (idx == max_watchpoints)
555 return -1;
556
557 dbr_addr = (long) addr;
558 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
559 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
560 switch (rw)
561 {
562 case hw_write:
563 dbr_mask |= (1L << 62); /* Set w bit */
564 break;
565 case hw_read:
566 dbr_mask |= (1L << 63); /* Set r bit */
567 break;
568 case hw_access:
569 dbr_mask |= (3L << 62); /* Set both r and w bits */
570 break;
571 default:
572 return -1;
573 }
574
9f0bdab8
DJ		 575 debug_registers[2 * idx] = dbr_addr;
576 debug_registers[2 * idx + 1] = dbr_mask;
4c38200f 577 ALL_LWPS (lp)
9f0bdab8 578 {
4c38200f
PA		 579 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
580 enable_watchpoints_in_psr (lp->ptid);
9f0bdab8 581 }
acf7b9e1
KB		 582
583 return 0;
584}
585
74174d2e 586static int
0cf6dd15
TJB		 587ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
588 struct expression *cond)
acf7b9e1
KB		 589{
590 int idx;
591 long dbr_addr, dbr_mask;
592 int max_watchpoints = 4;
593
594 if (len <= 0 || !is_power_of_2 (len))
595 return -1;
596
597 for (idx = 0; idx < max_watchpoints; idx++)
598 {
9f0bdab8
DJ		 599 dbr_addr = debug_registers[2 * idx];
600 dbr_mask = debug_registers[2 * idx + 1];
acf7b9e1
KB		 601 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
602 {
9f0bdab8 603 struct lwp_info *lp;
9f0bdab8
DJ		 604
605 debug_registers[2 * idx] = 0;
606 debug_registers[2 * idx + 1] = 0;
acf7b9e1
KB		 607 dbr_addr = 0;
608 dbr_mask = 0;
9f0bdab8 609
4c38200f
PA		 610 ALL_LWPS (lp)
611 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
9f0bdab8 612
acf7b9e1
KB		 613 return 0;
614 }
615 }
616 return -1;
617}
618
9f0bdab8 619static void
7b50312a 620ia64_linux_new_thread (struct lwp_info *lp)
9f0bdab8
DJ		 621{
622 int i, any;
623
624 any = 0;
625 for (i = 0; i < 8; i++)
626 {
627 if (debug_registers[i] != 0)
628 any = 1;
7b50312a 629 store_debug_register (lp->ptid, i, debug_registers[i]);
9f0bdab8
DJ		 630 }
631
632 if (any)
7b50312a 633 enable_watchpoints_in_psr (lp->ptid);
9f0bdab8
DJ		 634}
635
74174d2e
UW		 636static int
637ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
acf7b9e1
KB		 638{
639 CORE_ADDR psr;
a5362b9a 640 siginfo_t *siginfo_p;
594f7785 641 struct regcache *regcache = get_current_regcache ();
acf7b9e1 642
9f0bdab8 643 siginfo_p = linux_nat_get_siginfo (inferior_ptid);
acf7b9e1 644
9f0bdab8
DJ		 645 if (siginfo_p->si_signo != SIGTRAP
646 || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
acf7b9e1
KB		 647 return 0;
648
7b86a1b8 649 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1 650 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
1777feb0 651 for the next instruction. */
7b86a1b8 652 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1 653
9f0bdab8 654 *addr_p = (CORE_ADDR)siginfo_p->si_addr;
4aa7a7f5
JJ		 655 return 1;
656}
657
74174d2e 658static int
4aa7a7f5
JJ		 659ia64_linux_stopped_by_watchpoint (void)
660{
661 CORE_ADDR addr;
74174d2e
UW		 662 return ia64_linux_stopped_data_address (&current_target, &addr);
663}
664
665static int
666ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
667{
668 return 1;
669}
670
671
672/* Fetch register REGNUM from the inferior. */
673
674static void
56be3814 675ia64_linux_fetch_register (struct regcache *regcache, int regnum)
74174d2e 676{
088568da 677 struct gdbarch *gdbarch = get_regcache_arch (regcache);
74174d2e
UW		 678 CORE_ADDR addr;
679 size_t size;
680 PTRACE_TYPE_RET *buf;
681 int pid, i;
682
5a75128f
JB		 683 /* r0 cannot be fetched but is always zero. */
684 if (regnum == IA64_GR0_REGNUM)
685 {
686 const gdb_byte zero[8] = { 0 };
687
688 gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
689 regcache_raw_supply (regcache, regnum, zero);
690 return;
691 }
692
2685572f 693 if (ia64_cannot_fetch_register (gdbarch, regnum))
74174d2e 694 {
56be3814 695 regcache_raw_supply (regcache, regnum, NULL);
74174d2e
UW		 696 return;
697 }
698
699 /* Cater for systems like GNU/Linux, that implement threads as
700 separate processes. */
701 pid = ptid_get_lwp (inferior_ptid);
702 if (pid == 0)
703 pid = ptid_get_pid (inferior_ptid);
704
705 /* This isn't really an address, but ptrace thinks of it as one. */
2685572f 706 addr = ia64_register_addr (gdbarch, regnum);
088568da 707 size = register_size (gdbarch, regnum);
74174d2e
UW		 708
709 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
710 buf = alloca (size);
711
712 /* Read the register contents from the inferior a chunk at a time. */
713 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
714 {
715 errno = 0;
716 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
717 if (errno != 0)
718 error (_("Couldn't read register %s (#%d): %s."),
088568da 719 gdbarch_register_name (gdbarch, regnum),
c9f4d572 720 regnum, safe_strerror (errno));
74174d2e
UW		 721
722 addr += sizeof (PTRACE_TYPE_RET);
723 }
56be3814 724 regcache_raw_supply (regcache, regnum, buf);
74174d2e
UW		 725}
726
727/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
728 for all registers. */
729
730static void
28439f5e
PA		 731ia64_linux_fetch_registers (struct target_ops *ops,
732 struct regcache *regcache, int regnum)
74174d2e
UW		 733{
734 if (regnum == -1)
088568da
UW		 735 for (regnum = 0;
736 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
737 regnum++)
56be3814 738 ia64_linux_fetch_register (regcache, regnum);
74174d2e 739 else
56be3814 740 ia64_linux_fetch_register (regcache, regnum);
74174d2e
UW		 741}
742
743/* Store register REGNUM into the inferior. */
744
745static void
56be3814 746ia64_linux_store_register (const struct regcache *regcache, int regnum)
74174d2e 747{
088568da 748 struct gdbarch *gdbarch = get_regcache_arch (regcache);
74174d2e
UW		 749 CORE_ADDR addr;
750 size_t size;
751 PTRACE_TYPE_RET *buf;
752 int pid, i;
753
2685572f 754 if (ia64_cannot_store_register (gdbarch, regnum))
74174d2e
UW		 755 return;
756
757 /* Cater for systems like GNU/Linux, that implement threads as
758 separate processes. */
759 pid = ptid_get_lwp (inferior_ptid);
760 if (pid == 0)
761 pid = ptid_get_pid (inferior_ptid);
762
763 /* This isn't really an address, but ptrace thinks of it as one. */
2685572f 764 addr = ia64_register_addr (gdbarch, regnum);
088568da 765 size = register_size (gdbarch, regnum);
74174d2e
UW		 766
767 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
768 buf = alloca (size);
769
770 /* Write the register contents into the inferior a chunk at a time. */
56be3814 771 regcache_raw_collect (regcache, regnum, buf);
74174d2e
UW		 772 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
773 {
774 errno = 0;
775 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
776 if (errno != 0)
777 error (_("Couldn't write register %s (#%d): %s."),
088568da 778 gdbarch_register_name (gdbarch, regnum),
c9f4d572 779 regnum, safe_strerror (errno));
74174d2e
UW		 780
781 addr += sizeof (PTRACE_TYPE_RET);
782 }
acf7b9e1 783}
287a334e 784
74174d2e
UW		 785/* Store register REGNUM back into the inferior. If REGNUM is -1, do
786 this for all registers. */
787
788static void
28439f5e
PA		 789ia64_linux_store_registers (struct target_ops *ops,
790 struct regcache *regcache, int regnum)
74174d2e
UW		 791{
792 if (regnum == -1)
088568da
UW		 793 for (regnum = 0;
794 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
795 regnum++)
56be3814 796 ia64_linux_store_register (regcache, regnum);
74174d2e 797 else
56be3814 798 ia64_linux_store_register (regcache, regnum);
74174d2e
UW		 799}
800
801
10d6c8cd 802static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
1777feb0
MS		 803 const char *, gdb_byte *,
804 const gdb_byte *, ULONGEST, LONGEST);
10d6c8cd
DJ		 805
806static LONGEST
807ia64_linux_xfer_partial (struct target_ops *ops,
808 enum target_object object,
809 const char *annex,
810 gdb_byte *readbuf, const gdb_byte *writebuf,
811 ULONGEST offset, LONGEST len)
812{
813 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
814 return syscall (__NR_getunwind, readbuf, len);
815
816 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
817 offset, len);
818}
819
26ab7092
JK		 820/* For break.b instruction ia64 CPU forgets the immediate value and generates
821 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
822 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
823 difference for the signals here. */
824
825static int
826ia64_linux_status_is_event (int status)
827{
828 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
829 || WSTOPSIG (status) == SIGILL);
830}
831
10d6c8cd
DJ		 832void _initialize_ia64_linux_nat (void);
833
834void
835_initialize_ia64_linux_nat (void)
287a334e 836{
dde7c0a9 837 struct target_ops *t;
10d6c8cd
DJ		 838
839 /* Fill in the generic GNU/Linux methods. */
840 t = linux_target ();
841
74174d2e
UW		 842 /* Override the default fetch/store register routines. */
843 t->to_fetch_registers = ia64_linux_fetch_registers;
844 t->to_store_registers = ia64_linux_store_registers;
845
10d6c8cd
DJ		 846 /* Override the default to_xfer_partial. */
847 super_xfer_partial = t->to_xfer_partial;
848 t->to_xfer_partial = ia64_linux_xfer_partial;
849
74174d2e
UW		 850 /* Override watchpoint routines. */
851
852 /* The IA-64 architecture can step over a watch point (without triggering
853 it again) if the "dd" (data debug fault disable) bit in the processor
854 status word is set.
855
856 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
857 code there has determined that a hardware watchpoint has indeed
858 been hit. The CPU will then be able to execute one instruction
1777feb0 859 without triggering a watchpoint. */
74174d2e
UW		 860
861 t->to_have_steppable_watchpoint = 1;
862 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
863 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
864 t->to_stopped_data_address = ia64_linux_stopped_data_address;
865 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
866 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
867
10d6c8cd 868 /* Register the target. */
f973ed9c 869 linux_nat_add_target (t);
9f0bdab8 870 linux_nat_set_new_thread (t, ia64_linux_new_thread);
26ab7092 871 linux_nat_set_status_is_event (t, ia64_linux_status_is_event);
287a334e 872}
GDB Binutils - Deliverables
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