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* emulparams/msp430all.sh: Update ARCH names.
[deliverable/binutils-gdb.git] / gdb / ia64-linux-nat.c
CommitLineData
ca557f44
AC		 1/* Functions specific to running gdb native on IA-64 running
2 GNU/Linux.
3
28e7fd62 4 Copyright (C) 1999-2013 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
16461d7d
KB		 11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
16461d7d
KB		 20
21#include "defs.h"
e162d11b 22#include "gdb_string.h"
16461d7d
KB		 23#include "inferior.h"
24#include "target.h"
25#include "gdbcore.h"
4e052eda 26#include "regcache.h"
949df321 27#include "ia64-tdep.h"
10d6c8cd 28#include "linux-nat.h"
16461d7d
KB		 29
30#include <signal.h>
31#include <sys/ptrace.h>
2555fe1a 32#include "gdb_wait.h"
16461d7d
KB		 33#ifdef HAVE_SYS_REG_H
34#include <sys/reg.h>
35#endif
287a334e 36#include <sys/syscall.h>
16461d7d
KB		 37#include <sys/user.h>
38
39#include <asm/ptrace_offsets.h>
40#include <sys/procfs.h>
41
1777feb0 42/* Prototypes for supply_gregset etc. */
c60c0f5f
MS		 43#include "gregset.h"
44
16461d7d
KB		 45/* These must match the order of the register names.
46
47 Some sort of lookup table is needed because the offsets associated
48 with the registers are all over the board. */
49
50static int u_offsets[] =
51 {
52 /* general registers */
1777feb0 53 -1, /* gr0 not available; i.e, it's always zero. */
16461d7d
KB		 54 PT_R1,
55 PT_R2,
56 PT_R3,
57 PT_R4,
58 PT_R5,
59 PT_R6,
60 PT_R7,
61 PT_R8,
62 PT_R9,
63 PT_R10,
64 PT_R11,
65 PT_R12,
66 PT_R13,
67 PT_R14,
68 PT_R15,
69 PT_R16,
70 PT_R17,
71 PT_R18,
72 PT_R19,
73 PT_R20,
74 PT_R21,
75 PT_R22,
76 PT_R23,
77 PT_R24,
78 PT_R25,
79 PT_R26,
80 PT_R27,
81 PT_R28,
82 PT_R29,
83 PT_R30,
84 PT_R31,
1777feb0 85 /* gr32 through gr127 not directly available via the ptrace interface. */
16461d7d
KB		 86 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 /* Floating point registers */
1777feb0 93 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
16461d7d
KB		 94 PT_F2,
95 PT_F3,
96 PT_F4,
97 PT_F5,
98 PT_F6,
99 PT_F7,
100 PT_F8,
101 PT_F9,
102 PT_F10,
103 PT_F11,
104 PT_F12,
105 PT_F13,
106 PT_F14,
107 PT_F15,
108 PT_F16,
109 PT_F17,
110 PT_F18,
111 PT_F19,
112 PT_F20,
113 PT_F21,
114 PT_F22,
115 PT_F23,
116 PT_F24,
117 PT_F25,
118 PT_F26,
119 PT_F27,
120 PT_F28,
121 PT_F29,
122 PT_F30,
123 PT_F31,
124 PT_F32,
125 PT_F33,
126 PT_F34,
127 PT_F35,
128 PT_F36,
129 PT_F37,
130 PT_F38,
131 PT_F39,
132 PT_F40,
133 PT_F41,
134 PT_F42,
135 PT_F43,
136 PT_F44,
137 PT_F45,
138 PT_F46,
139 PT_F47,
140 PT_F48,
141 PT_F49,
142 PT_F50,
143 PT_F51,
144 PT_F52,
145 PT_F53,
146 PT_F54,
147 PT_F55,
148 PT_F56,
149 PT_F57,
150 PT_F58,
151 PT_F59,
152 PT_F60,
153 PT_F61,
154 PT_F62,
155 PT_F63,
156 PT_F64,
157 PT_F65,
158 PT_F66,
159 PT_F67,
160 PT_F68,
161 PT_F69,
162 PT_F70,
163 PT_F71,
164 PT_F72,
165 PT_F73,
166 PT_F74,
167 PT_F75,
168 PT_F76,
169 PT_F77,
170 PT_F78,
171 PT_F79,
172 PT_F80,
173 PT_F81,
174 PT_F82,
175 PT_F83,
176 PT_F84,
177 PT_F85,
178 PT_F86,
179 PT_F87,
180 PT_F88,
181 PT_F89,
182 PT_F90,
183 PT_F91,
184 PT_F92,
185 PT_F93,
186 PT_F94,
187 PT_F95,
188 PT_F96,
189 PT_F97,
190 PT_F98,
191 PT_F99,
192 PT_F100,
193 PT_F101,
194 PT_F102,
195 PT_F103,
196 PT_F104,
197 PT_F105,
198 PT_F106,
199 PT_F107,
200 PT_F108,
201 PT_F109,
202 PT_F110,
203 PT_F111,
204 PT_F112,
205 PT_F113,
206 PT_F114,
207 PT_F115,
208 PT_F116,
209 PT_F117,
210 PT_F118,
211 PT_F119,
212 PT_F120,
213 PT_F121,
214 PT_F122,
215 PT_F123,
216 PT_F124,
217 PT_F125,
218 PT_F126,
219 PT_F127,
1777feb0 220 /* Predicate registers - we don't fetch these individually. */
16461d7d
KB		 221 -1, -1, -1, -1, -1, -1, -1, -1,
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 /* branch registers */
230 PT_B0,
231 PT_B1,
232 PT_B2,
233 PT_B3,
234 PT_B4,
235 PT_B5,
236 PT_B6,
237 PT_B7,
1777feb0 238 /* Virtual frame pointer and virtual return address pointer. */
16461d7d
KB		 239 -1, -1,
240 /* other registers */
241 PT_PR,
242 PT_CR_IIP, /* ip */
243 PT_CR_IPSR, /* psr */
9ac12c35 244 PT_CFM, /* cfm */
1777feb0 245 /* kernel registers not visible via ptrace interface (?) */
16461d7d
KB		 246 -1, -1, -1, -1, -1, -1, -1, -1,
247 /* hole */
248 -1, -1, -1, -1, -1, -1, -1, -1,
249 PT_AR_RSC,
250 PT_AR_BSP,
251 PT_AR_BSPSTORE,
252 PT_AR_RNAT,
253 -1,
1777feb0 254 -1, /* Not available: FCR, IA32 floating control register. */
16461d7d
KB		 255 -1, -1,
256 -1, /* Not available: EFLAG */
257 -1, /* Not available: CSD */
258 -1, /* Not available: SSD */
259 -1, /* Not available: CFLG */
260 -1, /* Not available: FSR */
261 -1, /* Not available: FIR */
262 -1, /* Not available: FDR */
263 -1,
264 PT_AR_CCV,
265 -1, -1, -1,
266 PT_AR_UNAT,
267 -1, -1, -1,
268 PT_AR_FPSR,
269 -1, -1, -1,
270 -1, /* Not available: ITC */
271 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
272 -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 PT_AR_PFS,
274 PT_AR_LC,
4a6510ba 275 PT_AR_EC,
16461d7d
KB		 276 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1,
283 /* nat bits - not fetched directly; instead we obtain these bits from
1777feb0 284 either rnat or unat or from memory. */
16461d7d
KB		 285 -1, -1, -1, -1, -1, -1, -1, -1,
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 };
302
74174d2e 303static CORE_ADDR
2685572f 304ia64_register_addr (struct gdbarch *gdbarch, int regno)
16461d7d
KB		 305{
306 CORE_ADDR addr;
307
2685572f 308 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
8a3fe4f8 309 error (_("Invalid register number %d."), regno);
16461d7d
KB		 310
311 if (u_offsets[regno] == -1)
312 addr = 0;
313 else
314 addr = (CORE_ADDR) u_offsets[regno];
315
316 return addr;
317}
318
74174d2e 319static int
2685572f 320ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
16461d7d 321{
f57d151a 322 return regno < 0
2685572f 323 || regno >= gdbarch_num_regs (gdbarch)
f57d151a 324 || u_offsets[regno] == -1;
16461d7d
KB		 325}
326
74174d2e 327static int
2685572f 328ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
16461d7d
KB		 329{
330 /* Rationale behind not permitting stores to bspstore...
331
332 The IA-64 architecture provides bspstore and bsp which refer
333 memory locations in the RSE's backing store. bspstore is the
334 next location which will be written when the RSE needs to write
335 to memory. bsp is the address at which r32 in the current frame
336 would be found if it were written to the backing store.
337
338 The IA-64 architecture provides read-only access to bsp and
339 read/write access to bspstore (but only when the RSE is in
340 the enforced lazy mode). It should be noted that stores
341 to bspstore also affect the value of bsp. Changing bspstore
342 does not affect the number of dirty entries between bspstore
343 and bsp, so changing bspstore by N words will also cause bsp
344 to be changed by (roughly) N as well. (It could be N-1 or N+1
345 depending upon where the NaT collection bits fall.)
346
92362027 347 OTOH, the Linux kernel provides read/write access to bsp (and
16461d7d
KB		 348 currently read/write access to bspstore as well). But it
349 is definitely the case that if you change one, the other
350 will change at the same time. It is more useful to gdb to
351 be able to change bsp. So in order to prevent strange and
352 undesirable things from happening when a dummy stack frame
353 is popped (after calling an inferior function), we allow
354 bspstore to be read, but not written. (Note that popping
355 a (generic) dummy stack frame causes all registers that
356 were previously read from the inferior process to be written
357 back.) */
358
f57d151a 359 return regno < 0
2685572f 360 || regno >= gdbarch_num_regs (gdbarch)
f57d151a 361 || u_offsets[regno] == -1
16461d7d
KB		 362 || regno == IA64_BSPSTORE_REGNUM;
363}
364
365void
7f7fe91e 366supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
16461d7d
KB		 367{
368 int regi;
7f7fe91e 369 const greg_t *regp = (const greg_t *) gregsetp;
16461d7d
KB		 370
371 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
372 {
7f7fe91e 373 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
16461d7d
KB		 374 }
375
376 /* FIXME: NAT collection bits are at index 32; gotta deal with these
1777feb0 377 somehow... */
16461d7d 378
7f7fe91e 379 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
16461d7d
KB		 380
381 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
382 {
7f7fe91e
UW		 383 regcache_raw_supply (regcache, regi,
384 regp + 34 + (regi - IA64_BR0_REGNUM));
16461d7d
KB		 385 }
386
7f7fe91e
UW		 387 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
388 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
389 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
390 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
391 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
392 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
393 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
394 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
395 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
396 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
397 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
398 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
399 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
16461d7d
KB		 400}
401
402void
7f7fe91e 403fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
16461d7d 404{
76d689a6
KB		 405 int regi;
406 greg_t *regp = (greg_t *) gregsetp;
407
408#define COPY_REG(_idx_,_regi_) \
409 if ((regno == -1) || regno == _regi_) \
7f7fe91e 410 regcache_raw_collect (regcache, _regi_, regp + _idx_)
76d689a6
KB		 411
412 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
413 {
414 COPY_REG (regi - IA64_GR0_REGNUM, regi);
415 }
416
1777feb0 417 /* FIXME: NAT collection bits at index 32? */
76d689a6
KB		 418
419 COPY_REG (33, IA64_PR_REGNUM);
420
421 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
422 {
423 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
424 }
425
426 COPY_REG (42, IA64_IP_REGNUM);
427 COPY_REG (43, IA64_CFM_REGNUM);
428 COPY_REG (44, IA64_PSR_REGNUM);
429 COPY_REG (45, IA64_RSC_REGNUM);
430 COPY_REG (46, IA64_BSP_REGNUM);
431 COPY_REG (47, IA64_BSPSTORE_REGNUM);
432 COPY_REG (48, IA64_RNAT_REGNUM);
433 COPY_REG (49, IA64_CCV_REGNUM);
434 COPY_REG (50, IA64_UNAT_REGNUM);
435 COPY_REG (51, IA64_FPSR_REGNUM);
436 COPY_REG (52, IA64_PFS_REGNUM);
437 COPY_REG (53, IA64_LC_REGNUM);
438 COPY_REG (54, IA64_EC_REGNUM);
439}
440
441/* Given a pointer to a floating point register set in /proc format
442 (fpregset_t *), unpack the register contents and supply them as gdb's
1777feb0 443 idea of the current floating point register values. */
76d689a6
KB		 444
445void
7f7fe91e 446supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
76d689a6 447{
52f0bd74 448 int regi;
7f7fe91e 449 const char *from;
ca9b8b9c
PA		 450 const gdb_byte f_zero[16] = { 0 };
451 const gdb_byte f_one[16] =
452 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
76d689a6 453
ca9b8b9c
PA		 454 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
455 did the same. So ignore whatever might be recorded in fpregset_t
456 for fr0/fr1 and always supply their expected values. */
457
458 /* fr0 is always read as zero. */
459 regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero);
460 /* fr1 is always read as one (1.0). */
461 regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one);
462
463 for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
76d689a6 464 {
7f7fe91e
UW		 465 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
466 regcache_raw_supply (regcache, regi, from);
76d689a6
KB		 467 }
468}
469
470/* Given a pointer to a floating point register set in /proc format
471 (fpregset_t *), update the register specified by REGNO from gdb's idea
472 of the current floating point register set. If REGNO is -1, update
1777feb0 473 them all. */
76d689a6
KB		 474
475void
7f7fe91e
UW		 476fill_fpregset (const struct regcache *regcache,
477 fpregset_t *fpregsetp, int regno)
76d689a6
KB		 478{
479 int regi;
76d689a6
KB		 480
481 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
482 {
483 if ((regno == -1) || (regno == regi))
7f7fe91e 484 regcache_raw_collect (regcache, regi,
e0e25c6c 485 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
76d689a6 486 }
16461d7d 487}
acf7b9e1
KB		 488
489#define IA64_PSR_DB (1UL << 24)
490#define IA64_PSR_DD (1UL << 39)
491
492static void
9f0bdab8 493enable_watchpoints_in_psr (ptid_t ptid)
acf7b9e1 494{
9f0bdab8 495 struct regcache *regcache = get_thread_regcache (ptid);
7b86a1b8 496 ULONGEST psr;
acf7b9e1 497
7b86a1b8 498 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1
KB		 499 if (!(psr & IA64_PSR_DB))
500 {
501 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
1777feb0 502 watchpoints and breakpoints. */
7b86a1b8 503 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1
KB		 504 }
505}
506
9f0bdab8 507static long debug_registers[8];
acf7b9e1
KB		 508
509static void
39f77062 510store_debug_register (ptid_t ptid, int idx, long val)
acf7b9e1
KB		 511{
512 int tid;
513
39f77062 514 tid = TIDGET (ptid);
acf7b9e1 515 if (tid == 0)
39f77062 516 tid = PIDGET (ptid);
acf7b9e1 517
c5fa4245 518 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
acf7b9e1
KB		 519}
520
acf7b9e1 521static void
1777feb0
MS		 522store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
523 long *dbr_mask)
acf7b9e1
KB		 524{
525 if (dbr_addr)
39f77062 526 store_debug_register (ptid, 2 * idx, *dbr_addr);
acf7b9e1 527 if (dbr_mask)
39f77062 528 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
acf7b9e1
KB		 529}
530
531static int
532is_power_of_2 (int val)
533{
534 int i, onecount;
535
536 onecount = 0;
537 for (i = 0; i < 8 * sizeof (val); i++)
538 if (val & (1 << i))
539 onecount++;
540
541 return onecount <= 1;
542}
543
74174d2e 544static int
0cf6dd15
TJB		 545ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
546 struct expression *cond)
acf7b9e1 547{
9f0bdab8 548 struct lwp_info *lp;
acf7b9e1
KB		 549 int idx;
550 long dbr_addr, dbr_mask;
551 int max_watchpoints = 4;
552
553 if (len <= 0 || !is_power_of_2 (len))
554 return -1;
555
556 for (idx = 0; idx < max_watchpoints; idx++)
557 {
9f0bdab8 558 dbr_mask = debug_registers[idx * 2 + 1];
acf7b9e1
KB		 559 if ((dbr_mask & (0x3UL << 62)) == 0)
560 {
1777feb0 561 /* Exit loop if both r and w bits clear. */
acf7b9e1
KB		 562 break;
563 }
564 }
565
566 if (idx == max_watchpoints)
567 return -1;
568
569 dbr_addr = (long) addr;
570 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
571 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
572 switch (rw)
573 {
574 case hw_write:
575 dbr_mask |= (1L << 62); /* Set w bit */
576 break;
577 case hw_read:
578 dbr_mask |= (1L << 63); /* Set r bit */
579 break;
580 case hw_access:
581 dbr_mask |= (3L << 62); /* Set both r and w bits */
582 break;
583 default:
584 return -1;
585 }
586
9f0bdab8
DJ		 587 debug_registers[2 * idx] = dbr_addr;
588 debug_registers[2 * idx + 1] = dbr_mask;
4c38200f 589 ALL_LWPS (lp)
9f0bdab8 590 {
4c38200f
PA		 591 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
592 enable_watchpoints_in_psr (lp->ptid);
9f0bdab8 593 }
acf7b9e1
KB		 594
595 return 0;
596}
597
74174d2e 598static int
0cf6dd15
TJB		 599ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
600 struct expression *cond)
acf7b9e1
KB		 601{
602 int idx;
603 long dbr_addr, dbr_mask;
604 int max_watchpoints = 4;
605
606 if (len <= 0 || !is_power_of_2 (len))
607 return -1;
608
609 for (idx = 0; idx < max_watchpoints; idx++)
610 {
9f0bdab8
DJ		 611 dbr_addr = debug_registers[2 * idx];
612 dbr_mask = debug_registers[2 * idx + 1];
acf7b9e1
KB		 613 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
614 {
9f0bdab8 615 struct lwp_info *lp;
9f0bdab8
DJ		 616
617 debug_registers[2 * idx] = 0;
618 debug_registers[2 * idx + 1] = 0;
acf7b9e1
KB		 619 dbr_addr = 0;
620 dbr_mask = 0;
9f0bdab8 621
4c38200f
PA		 622 ALL_LWPS (lp)
623 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
9f0bdab8 624
acf7b9e1
KB		 625 return 0;
626 }
627 }
628 return -1;
629}
630
9f0bdab8 631static void
7b50312a 632ia64_linux_new_thread (struct lwp_info *lp)
9f0bdab8
DJ		 633{
634 int i, any;
635
636 any = 0;
637 for (i = 0; i < 8; i++)
638 {
639 if (debug_registers[i] != 0)
640 any = 1;
7b50312a 641 store_debug_register (lp->ptid, i, debug_registers[i]);
9f0bdab8
DJ		 642 }
643
644 if (any)
7b50312a 645 enable_watchpoints_in_psr (lp->ptid);
9f0bdab8
DJ		 646}
647
74174d2e
UW		 648static int
649ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
acf7b9e1
KB		 650{
651 CORE_ADDR psr;
f865ee35 652 siginfo_t siginfo;
594f7785 653 struct regcache *regcache = get_current_regcache ();
acf7b9e1 654
f865ee35
JK		 655 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
656 return 0;
acf7b9e1 657
f865ee35
JK		 658 if (siginfo.si_signo != SIGTRAP
659 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
acf7b9e1
KB		 660 return 0;
661
7b86a1b8 662 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1 663 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
1777feb0 664 for the next instruction. */
7b86a1b8 665 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1 666
f865ee35 667 *addr_p = (CORE_ADDR) siginfo.si_addr;
4aa7a7f5
JJ		 668 return 1;
669}
670
74174d2e 671static int
4aa7a7f5
JJ		 672ia64_linux_stopped_by_watchpoint (void)
673{
674 CORE_ADDR addr;
74174d2e
UW		 675 return ia64_linux_stopped_data_address (&current_target, &addr);
676}
677
678static int
679ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
680{
681 return 1;
682}
683
684
685/* Fetch register REGNUM from the inferior. */
686
687static void
56be3814 688ia64_linux_fetch_register (struct regcache *regcache, int regnum)
74174d2e 689{
088568da 690 struct gdbarch *gdbarch = get_regcache_arch (regcache);
74174d2e
UW		 691 CORE_ADDR addr;
692 size_t size;
693 PTRACE_TYPE_RET *buf;
694 int pid, i;
695
5a75128f
JB		 696 /* r0 cannot be fetched but is always zero. */
697 if (regnum == IA64_GR0_REGNUM)
698 {
699 const gdb_byte zero[8] = { 0 };
700
701 gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
702 regcache_raw_supply (regcache, regnum, zero);
703 return;
704 }
705
ca9b8b9c
PA		 706 /* fr0 cannot be fetched but is always zero. */
707 if (regnum == IA64_FR0_REGNUM)
708 {
709 const gdb_byte f_zero[16] = { 0 };
710
711 gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
712 regcache_raw_supply (regcache, regnum, f_zero);
713 return;
714 }
715
716 /* fr1 cannot be fetched but is always one (1.0). */
717 if (regnum == IA64_FR1_REGNUM)
718 {
719 const gdb_byte f_one[16] =
720 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
721
722 gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
723 regcache_raw_supply (regcache, regnum, f_one);
724 return;
725 }
726
2685572f 727 if (ia64_cannot_fetch_register (gdbarch, regnum))
74174d2e 728 {
56be3814 729 regcache_raw_supply (regcache, regnum, NULL);
74174d2e
UW		 730 return;
731 }
732
733 /* Cater for systems like GNU/Linux, that implement threads as
734 separate processes. */
735 pid = ptid_get_lwp (inferior_ptid);
736 if (pid == 0)
737 pid = ptid_get_pid (inferior_ptid);
738
739 /* This isn't really an address, but ptrace thinks of it as one. */
2685572f 740 addr = ia64_register_addr (gdbarch, regnum);
088568da 741 size = register_size (gdbarch, regnum);
74174d2e
UW		 742
743 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
744 buf = alloca (size);
745
746 /* Read the register contents from the inferior a chunk at a time. */
747 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
748 {
749 errno = 0;
750 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
751 if (errno != 0)
752 error (_("Couldn't read register %s (#%d): %s."),
088568da 753 gdbarch_register_name (gdbarch, regnum),
c9f4d572 754 regnum, safe_strerror (errno));
74174d2e
UW		 755
756 addr += sizeof (PTRACE_TYPE_RET);
757 }
56be3814 758 regcache_raw_supply (regcache, regnum, buf);
74174d2e
UW		 759}
760
761/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
762 for all registers. */
763
764static void
28439f5e
PA		 765ia64_linux_fetch_registers (struct target_ops *ops,
766 struct regcache *regcache, int regnum)
74174d2e
UW		 767{
768 if (regnum == -1)
088568da
UW		 769 for (regnum = 0;
770 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
771 regnum++)
56be3814 772 ia64_linux_fetch_register (regcache, regnum);
74174d2e 773 else
56be3814 774 ia64_linux_fetch_register (regcache, regnum);
74174d2e
UW		 775}
776
777/* Store register REGNUM into the inferior. */
778
779static void
56be3814 780ia64_linux_store_register (const struct regcache *regcache, int regnum)
74174d2e 781{
088568da 782 struct gdbarch *gdbarch = get_regcache_arch (regcache);
74174d2e
UW		 783 CORE_ADDR addr;
784 size_t size;
785 PTRACE_TYPE_RET *buf;
786 int pid, i;
787
2685572f 788 if (ia64_cannot_store_register (gdbarch, regnum))
74174d2e
UW		 789 return;
790
791 /* Cater for systems like GNU/Linux, that implement threads as
792 separate processes. */
793 pid = ptid_get_lwp (inferior_ptid);
794 if (pid == 0)
795 pid = ptid_get_pid (inferior_ptid);
796
797 /* This isn't really an address, but ptrace thinks of it as one. */
2685572f 798 addr = ia64_register_addr (gdbarch, regnum);
088568da 799 size = register_size (gdbarch, regnum);
74174d2e
UW		 800
801 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
802 buf = alloca (size);
803
804 /* Write the register contents into the inferior a chunk at a time. */
56be3814 805 regcache_raw_collect (regcache, regnum, buf);
74174d2e
UW		 806 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
807 {
808 errno = 0;
809 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
810 if (errno != 0)
811 error (_("Couldn't write register %s (#%d): %s."),
088568da 812 gdbarch_register_name (gdbarch, regnum),
c9f4d572 813 regnum, safe_strerror (errno));
74174d2e
UW		 814
815 addr += sizeof (PTRACE_TYPE_RET);
816 }
acf7b9e1 817}
287a334e 818
74174d2e
UW		 819/* Store register REGNUM back into the inferior. If REGNUM is -1, do
820 this for all registers. */
821
822static void
28439f5e
PA		 823ia64_linux_store_registers (struct target_ops *ops,
824 struct regcache *regcache, int regnum)
74174d2e
UW		 825{
826 if (regnum == -1)
088568da
UW		 827 for (regnum = 0;
828 regnum < gdbarch_num_regs (get_regcache_arch (regcache));
829 regnum++)
56be3814 830 ia64_linux_store_register (regcache, regnum);
74174d2e 831 else
56be3814 832 ia64_linux_store_register (regcache, regnum);
74174d2e
UW		 833}
834
835
10d6c8cd 836static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
1777feb0
MS		 837 const char *, gdb_byte *,
838 const gdb_byte *, ULONGEST, LONGEST);
10d6c8cd
DJ		 839
840static LONGEST
841ia64_linux_xfer_partial (struct target_ops *ops,
842 enum target_object object,
843 const char *annex,
844 gdb_byte *readbuf, const gdb_byte *writebuf,
845 ULONGEST offset, LONGEST len)
846{
847 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
848 return syscall (__NR_getunwind, readbuf, len);
849
850 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
851 offset, len);
852}
853
26ab7092
JK		 854/* For break.b instruction ia64 CPU forgets the immediate value and generates
855 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
856 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
857 difference for the signals here. */
858
859static int
860ia64_linux_status_is_event (int status)
861{
862 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
863 || WSTOPSIG (status) == SIGILL);
864}
865
10d6c8cd
DJ		 866void _initialize_ia64_linux_nat (void);
867
868void
869_initialize_ia64_linux_nat (void)
287a334e 870{
dde7c0a9 871 struct target_ops *t;
10d6c8cd
DJ		 872
873 /* Fill in the generic GNU/Linux methods. */
874 t = linux_target ();
875
74174d2e
UW		 876 /* Override the default fetch/store register routines. */
877 t->to_fetch_registers = ia64_linux_fetch_registers;
878 t->to_store_registers = ia64_linux_store_registers;
879
10d6c8cd
DJ		 880 /* Override the default to_xfer_partial. */
881 super_xfer_partial = t->to_xfer_partial;
882 t->to_xfer_partial = ia64_linux_xfer_partial;
883
74174d2e
UW		 884 /* Override watchpoint routines. */
885
886 /* The IA-64 architecture can step over a watch point (without triggering
887 it again) if the "dd" (data debug fault disable) bit in the processor
888 status word is set.
889
890 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
891 code there has determined that a hardware watchpoint has indeed
892 been hit. The CPU will then be able to execute one instruction
1777feb0 893 without triggering a watchpoint. */
74174d2e
UW		 894
895 t->to_have_steppable_watchpoint = 1;
896 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
897 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
898 t->to_stopped_data_address = ia64_linux_stopped_data_address;
899 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
900 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
901
10d6c8cd 902 /* Register the target. */
f973ed9c 903 linux_nat_add_target (t);
9f0bdab8 904 linux_nat_set_new_thread (t, ia64_linux_new_thread);
26ab7092 905 linux_nat_set_status_is_event (t, ia64_linux_status_is_event);
287a334e 906}
GDB Binutils - Deliverables
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