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* ldlang.c (lang_size_sections_1): Don't warn on backwards dot
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
CommitLineData
16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
6aba47ca 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
13547ab6 4 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
16461d7d
KB		 22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
7d9b040b 40#include "infcall.h"
b33e8514 41#include "osabi.h"
9fc9f5e2 42#include "ia64-tdep.h"
0d5de010 43#include "cp-abi.h"
16461d7d 44
968d1cb4 45#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 46#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 47#include "libunwind-frame.h"
48#include "libunwind-ia64.h"
c5a27d9c
JJ		 49
50/* Note: KERNEL_START is supposed to be an address which is not going
51 to ever contain any valid unwind info. For ia64 linux, the choice
52 of 0xc000000000000000 is fairly safe since that's uncached space.
53
54 We use KERNEL_START as follows: after obtaining the kernel's
55 unwind table via getunwind(), we project its unwind data into
56 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
57 when ia64_access_mem() sees a memory access to this
58 address-range, we redirect it to ktab instead.
59
60 None of this hackery is needed with a modern kernel/libcs
61 which uses the kernel virtual DSO to provide access to the
62 kernel's unwind info. In that case, ktab_size remains 0 and
63 hence the value of KERNEL_START doesn't matter. */
64
65#define KERNEL_START 0xc000000000000000ULL
66
67static size_t ktab_size = 0;
68struct ia64_table_entry
69 {
70 uint64_t start_offset;
71 uint64_t end_offset;
72 uint64_t info_offset;
73 };
74
75static struct ia64_table_entry *ktab = NULL;
76
968d1cb4
JJ		 77#endif
78
698cb3f0
KB		 79/* An enumeration of the different IA-64 instruction types. */
80
16461d7d
KB		 81typedef enum instruction_type
82{
83 A, /* Integer ALU ; I-unit or M-unit */
84 I, /* Non-ALU integer; I-unit */
85 M, /* Memory ; M-unit */
86 F, /* Floating-point ; F-unit */
87 B, /* Branch ; B-unit */
88 L, /* Extended (L+X) ; I-unit */
89 X, /* Extended (L+X) ; I-unit */
90 undefined /* undefined or reserved */
91} instruction_type;
92
93/* We represent IA-64 PC addresses as the value of the instruction
94 pointer or'd with some bit combination in the low nibble which
95 represents the slot number in the bundle addressed by the
96 instruction pointer. The problem is that the Linux kernel
97 multiplies its slot numbers (for exceptions) by one while the
98 disassembler multiplies its slot numbers by 6. In addition, I've
99 heard it said that the simulator uses 1 as the multiplier.
100
101 I've fixed the disassembler so that the bytes_per_line field will
102 be the slot multiplier. If bytes_per_line comes in as zero, it
103 is set to six (which is how it was set up initially). -- objdump
104 displays pretty disassembly dumps with this value. For our purposes,
105 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
106 never want to also display the raw bytes the way objdump does. */
107
108#define SLOT_MULTIPLIER 1
109
110/* Length in bytes of an instruction bundle */
111
112#define BUNDLE_LEN 16
113
16461d7d
KB		 114static gdbarch_init_ftype ia64_gdbarch_init;
115
116static gdbarch_register_name_ftype ia64_register_name;
004d836a 117static gdbarch_register_type_ftype ia64_register_type;
16461d7d 118static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 119static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 120static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 121static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 122
004d836a
JJ		 123static struct type *builtin_type_ia64_ext;
124
125#define NUM_IA64_RAW_REGS 462
16461d7d 126
16461d7d
KB		 127static int sp_regnum = IA64_GR12_REGNUM;
128static int fp_regnum = IA64_VFP_REGNUM;
129static int lr_regnum = IA64_VRAP_REGNUM;
130
004d836a 131/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 132 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 133enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
134 V127_REGNUM = V32_REGNUM + 95,
135 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 136
137/* Array of register names; There should be ia64_num_regs strings in
138 the initializer. */
139
140static char *ia64_register_names[] =
141{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
144 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
16461d7d
KB		 157
158 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
159 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
160 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
161 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
162 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
163 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
164 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
165 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
166 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
167 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
168 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
169 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
170 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
171 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
172 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
173 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
174
004d836a
JJ		 175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "",
16461d7d
KB		 183
184 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
185
186 "vfp", "vrap",
187
188 "pr", "ip", "psr", "cfm",
189
190 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
191 "", "", "", "", "", "", "", "",
192 "rsc", "bsp", "bspstore", "rnat",
193 "", "fcr", "", "",
194 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
195 "ccv", "", "", "", "unat", "", "", "",
196 "fpsr", "", "", "", "itc",
197 "", "", "", "", "", "", "", "", "", "",
198 "", "", "", "", "", "", "", "", "",
199 "pfs", "lc", "ec",
200 "", "", "", "", "", "", "", "", "", "",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "", "", "", "", "", "", "", "", "", "",
206 "",
207 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
208 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
209 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
210 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
211 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
212 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
213 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
214 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
215 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
216 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
217 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
218 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
219 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
220 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
221 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
222 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 223
224 "bof",
225
226 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
227 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
228 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
229 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
230 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
231 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
232 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
233 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
234 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
235 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
236 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
237 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
238
239 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
240 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
241 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
242 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
243 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
244 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
245 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
246 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 247};
248
004d836a
JJ		 249struct ia64_frame_cache
250{
251 CORE_ADDR base; /* frame pointer base for frame */
252 CORE_ADDR pc; /* function start pc for frame */
253 CORE_ADDR saved_sp; /* stack pointer for frame */
254 CORE_ADDR bsp; /* points at r32 for the current frame */
255 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 256 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 257 int frameless;
258 int sof; /* Size of frame (decoded from cfm value) */
259 int sol; /* Size of locals (decoded from cfm value) */
260 int sor; /* Number of rotating registers. (decoded from cfm value) */
261 CORE_ADDR after_prologue;
262 /* Address of first instruction after the last
263 prologue instruction; Note that there may
264 be instructions from the function's body
265 intermingled with the prologue. */
266 int mem_stack_frame_size;
267 /* Size of the memory stack frame (may be zero),
268 or -1 if it has not been determined yet. */
269 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 270 for this frame. 0 if no register is being used
16461d7d 271 as the frame pointer. */
004d836a
JJ		 272
273 /* Saved registers. */
274 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
275
276};
244bc108 277
698cb3f0
KB		 278#define SIGCONTEXT_REGISTER_ADDRESS \
279 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 280
004d836a
JJ		 281int
282ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
283 struct reggroup *group)
16461d7d 284{
004d836a
JJ		 285 int vector_p;
286 int float_p;
287 int raw_p;
288 if (group == all_reggroup)
289 return 1;
290 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
291 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
292 raw_p = regnum < NUM_IA64_RAW_REGS;
293 if (group == float_reggroup)
294 return float_p;
295 if (group == vector_reggroup)
296 return vector_p;
297 if (group == general_reggroup)
298 return (!vector_p && !float_p);
299 if (group == save_reggroup || group == restore_reggroup)
300 return raw_p;
301 return 0;
16461d7d
KB		 302}
303
004d836a
JJ		 304static const char *
305ia64_register_name (int reg)
16461d7d 306{
004d836a 307 return ia64_register_names[reg];
16461d7d
KB		 308}
309
004d836a
JJ		 310struct type *
311ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 312{
004d836a
JJ		 313 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
314 return builtin_type_ia64_ext;
315 else
316 return builtin_type_long;
16461d7d
KB		 317}
318
a78f21af 319static int
004d836a 320ia64_dwarf_reg_to_regnum (int reg)
16461d7d 321{
004d836a
JJ		 322 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
323 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
324 return reg;
16461d7d
KB		 325}
326
4afcc598 327static int
2fda21a6 328floatformat_valid (const struct floatformat *fmt, const void *from)
4afcc598
JJ		 329{
330 return 1;
331}
332
16461d7d
KB		 333const struct floatformat floatformat_ia64_ext =
334{
335 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 336 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 337};
338
8da61cc4
DJ		 339const struct floatformat *floatformats_ia64_ext[2] =
340{
341 &floatformat_ia64_ext,
342 &floatformat_ia64_ext
343};
344
16461d7d
KB		 345
346/* Extract ``len'' bits from an instruction bundle starting at
347 bit ``from''. */
348
244bc108 349static long long
16461d7d
KB		 350extract_bit_field (char *bundle, int from, int len)
351{
352 long long result = 0LL;
353 int to = from + len;
354 int from_byte = from / 8;
355 int to_byte = to / 8;
356 unsigned char *b = (unsigned char *) bundle;
357 unsigned char c;
358 int lshift;
359 int i;
360
361 c = b[from_byte];
362 if (from_byte == to_byte)
363 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
364 result = c >> (from % 8);
365 lshift = 8 - (from % 8);
366
367 for (i = from_byte+1; i < to_byte; i++)
368 {
369 result |= ((long long) b[i]) << lshift;
370 lshift += 8;
371 }
372
373 if (from_byte < to_byte && (to % 8 != 0))
374 {
375 c = b[to_byte];
376 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
377 result |= ((long long) c) << lshift;
378 }
379
380 return result;
381}
382
383/* Replace the specified bits in an instruction bundle */
384
244bc108 385static void
16461d7d
KB		 386replace_bit_field (char *bundle, long long val, int from, int len)
387{
388 int to = from + len;
389 int from_byte = from / 8;
390 int to_byte = to / 8;
391 unsigned char *b = (unsigned char *) bundle;
392 unsigned char c;
393
394 if (from_byte == to_byte)
395 {
396 unsigned char left, right;
397 c = b[from_byte];
398 left = (c >> (to % 8)) << (to % 8);
399 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
400 c = (unsigned char) (val & 0xff);
401 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
402 c |= right | left;
403 b[from_byte] = c;
404 }
405 else
406 {
407 int i;
408 c = b[from_byte];
409 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
410 c = c | (val << (from % 8));
411 b[from_byte] = c;
412 val >>= 8 - from % 8;
413
414 for (i = from_byte+1; i < to_byte; i++)
415 {
416 c = val & 0xff;
417 val >>= 8;
418 b[i] = c;
419 }
420
421 if (to % 8 != 0)
422 {
423 unsigned char cv = (unsigned char) val;
424 c = b[to_byte];
425 c = c >> (to % 8) << (to % 8);
426 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
427 b[to_byte] = c;
428 }
429 }
430}
431
432/* Return the contents of slot N (for N = 0, 1, or 2) in
433 and instruction bundle */
434
244bc108 435static long long
2fc3ac7e 436slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 437{
438 return extract_bit_field (bundle, 5+41*slotnum, 41);
439}
440
441/* Store an instruction in an instruction bundle */
442
244bc108 443static void
2fc3ac7e 444replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 445{
446 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
447}
448
64a5b29c 449static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 450{
451 { M, I, I }, /* 00 */
452 { M, I, I }, /* 01 */
453 { M, I, I }, /* 02 */
454 { M, I, I }, /* 03 */
455 { M, L, X }, /* 04 */
456 { M, L, X }, /* 05 */
457 { undefined, undefined, undefined }, /* 06 */
458 { undefined, undefined, undefined }, /* 07 */
459 { M, M, I }, /* 08 */
460 { M, M, I }, /* 09 */
461 { M, M, I }, /* 0A */
462 { M, M, I }, /* 0B */
463 { M, F, I }, /* 0C */
464 { M, F, I }, /* 0D */
465 { M, M, F }, /* 0E */
466 { M, M, F }, /* 0F */
467 { M, I, B }, /* 10 */
468 { M, I, B }, /* 11 */
469 { M, B, B }, /* 12 */
470 { M, B, B }, /* 13 */
471 { undefined, undefined, undefined }, /* 14 */
472 { undefined, undefined, undefined }, /* 15 */
473 { B, B, B }, /* 16 */
474 { B, B, B }, /* 17 */
475 { M, M, B }, /* 18 */
476 { M, M, B }, /* 19 */
477 { undefined, undefined, undefined }, /* 1A */
478 { undefined, undefined, undefined }, /* 1B */
479 { M, F, B }, /* 1C */
480 { M, F, B }, /* 1D */
481 { undefined, undefined, undefined }, /* 1E */
482 { undefined, undefined, undefined }, /* 1F */
483};
484
485/* Fetch and (partially) decode an instruction at ADDR and return the
486 address of the next instruction to fetch. */
487
488static CORE_ADDR
489fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
490{
491 char bundle[BUNDLE_LEN];
492 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
493 long long template;
494 int val;
495
c26e1c2b
KB		 496 /* Warn about slot numbers greater than 2. We used to generate
497 an error here on the assumption that the user entered an invalid
498 address. But, sometimes GDB itself requests an invalid address.
499 This can (easily) happen when execution stops in a function for
500 which there are no symbols. The prologue scanner will attempt to
501 find the beginning of the function - if the nearest symbol
502 happens to not be aligned on a bundle boundary (16 bytes), the
503 resulting starting address will cause GDB to think that the slot
504 number is too large.
505
506 So we warn about it and set the slot number to zero. It is
507 not necessarily a fatal condition, particularly if debugging
508 at the assembly language level. */
16461d7d 509 if (slotnum > 2)
c26e1c2b 510 {
8a3fe4f8
AC		 511 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
512 "Using slot 0 instead"));
c26e1c2b
KB		 513 slotnum = 0;
514 }
16461d7d
KB		 515
516 addr &= ~0x0f;
517
518 val = target_read_memory (addr, bundle, BUNDLE_LEN);
519
520 if (val != 0)
521 return 0;
522
523 *instr = slotN_contents (bundle, slotnum);
524 template = extract_bit_field (bundle, 0, 5);
525 *it = template_encoding_table[(int)template][slotnum];
526
64a5b29c 527 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 528 addr += 16;
529 else
530 addr += (slotnum + 1) * SLOT_MULTIPLIER;
531
532 return addr;
533}
534
535/* There are 5 different break instructions (break.i, break.b,
536 break.m, break.f, and break.x), but they all have the same
537 encoding. (The five bit template in the low five bits of the
538 instruction bundle distinguishes one from another.)
539
540 The runtime architecture manual specifies that break instructions
541 used for debugging purposes must have the upper two bits of the 21
542 bit immediate set to a 0 and a 1 respectively. A breakpoint
543 instruction encodes the most significant bit of its 21 bit
544 immediate at bit 36 of the 41 bit instruction. The penultimate msb
545 is at bit 25 which leads to the pattern below.
546
547 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
548 it turns out that 0x80000 was used as the syscall break in the early
549 simulators. So I changed the pattern slightly to do "break.i 0x080001"
550 instead. But that didn't work either (I later found out that this
551 pattern was used by the simulator that I was using.) So I ended up
552 using the pattern seen below. */
553
554#if 0
aaab4dba 555#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 556#endif
aaab4dba 557#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 558
559static int
8181d85f 560ia64_memory_insert_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 561{
8181d85f 562 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 563 char bundle[BUNDLE_LEN];
564 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
565 long long instr;
566 int val;
126fa72d 567 int template;
16461d7d
KB		 568
569 if (slotnum > 2)
8a3fe4f8 570 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 571
572 addr &= ~0x0f;
573
574 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 575
576 /* Check for L type instruction in 2nd slot, if present then
577 bump up the slot number to the 3rd slot */
578 template = extract_bit_field (bundle, 0, 5);
579 if (slotnum == 1 && template_encoding_table[template][1] == L)
580 {
581 slotnum = 2;
582 }
583
16461d7d 584 instr = slotN_contents (bundle, slotnum);
8181d85f
DJ		 585 memcpy (bp_tgt->shadow_contents, &instr, sizeof (instr));
586 bp_tgt->placed_size = bp_tgt->shadow_len = sizeof (instr);
aaab4dba 587 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 588 if (val == 0)
589 target_write_memory (addr, bundle, BUNDLE_LEN);
590
591 return val;
592}
593
594static int
8181d85f 595ia64_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 596{
8181d85f 597 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 598 char bundle[BUNDLE_LEN];
599 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
600 long long instr;
601 int val;
126fa72d 602 int template;
16461d7d
KB		 603
604 addr &= ~0x0f;
605
606 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 607
608 /* Check for L type instruction in 2nd slot, if present then
609 bump up the slot number to the 3rd slot */
610 template = extract_bit_field (bundle, 0, 5);
611 if (slotnum == 1 && template_encoding_table[template][1] == L)
612 {
613 slotnum = 2;
614 }
615
8181d85f 616 memcpy (&instr, bp_tgt->shadow_contents, sizeof instr);
16461d7d
KB		 617 replace_slotN_contents (bundle, instr, slotnum);
618 if (val == 0)
619 target_write_memory (addr, bundle, BUNDLE_LEN);
620
621 return val;
622}
623
624/* We don't really want to use this, but remote.c needs to call it in order
625 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 626const unsigned char *
fba45db2 627ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 628{
629 static unsigned char breakpoint[] =
630 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
631 *lenptr = sizeof (breakpoint);
632#if 0
633 *pcptr &= ~0x0f;
634#endif
635 return breakpoint;
636}
637
a78f21af 638static CORE_ADDR
39f77062 639ia64_read_pc (ptid_t ptid)
16461d7d 640{
39f77062
KB		 641 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
642 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 643 int slot_num = (psr_value >> 41) & 3;
644
645 return pc_value | (slot_num * SLOT_MULTIPLIER);
646}
647
54a5c8d8 648void
39f77062 649ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 650{
651 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 652 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 653 psr_value &= ~(3LL << 41);
654 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
655
656 new_pc &= ~0xfLL;
657
39f77062
KB		 658 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
659 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 660}
661
662#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
663
664/* Returns the address of the slot that's NSLOTS slots away from
665 the address ADDR. NSLOTS may be positive or negative. */
666static CORE_ADDR
667rse_address_add(CORE_ADDR addr, int nslots)
668{
669 CORE_ADDR new_addr;
670 int mandatory_nat_slots = nslots / 63;
671 int direction = nslots < 0 ? -1 : 1;
672
673 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
674
675 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
676 new_addr += 8 * direction;
677
678 if (IS_NaT_COLLECTION_ADDR(new_addr))
679 new_addr += 8 * direction;
680
681 return new_addr;
682}
683
004d836a
JJ		 684static void
685ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 686 int regnum, gdb_byte *buf)
16461d7d 687{
004d836a 688 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 689 {
88d82102 690#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c
JJ		 691 /* First try and use the libunwind special reg accessor, otherwise fallback to
692 standard logic. */
693 if (!libunwind_is_initialized ()
694 || libunwind_get_reg_special (gdbarch, regnum, buf) != 0)
88d82102 695#endif
004d836a 696 {
c5a27d9c
JJ		 697 /* The fallback position is to assume that r32-r127 are found sequentially
698 in memory starting at $bof. This isn't always true, but without libunwind,
699 this is the best we can do. */
700 ULONGEST cfm;
701 ULONGEST bsp;
702 CORE_ADDR reg;
703 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
704 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
705
706 /* The bsp points at the end of the register frame so we
707 subtract the size of frame from it to get start of register frame. */
708 bsp = rse_address_add (bsp, -(cfm & 0x7f));
709
710 if ((cfm & 0x7f) > regnum - V32_REGNUM)
711 {
712 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
713 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
714 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
715 }
716 else
717 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a 718 }
004d836a
JJ		 719 }
720 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
721 {
722 ULONGEST unatN_val;
723 ULONGEST unat;
724 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
725 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 726 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 727 }
728 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
729 {
730 ULONGEST natN_val = 0;
731 ULONGEST bsp;
732 ULONGEST cfm;
733 CORE_ADDR gr_addr = 0;
734 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
735 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
736
737 /* The bsp points at the end of the register frame so we
738 subtract the size of frame from it to get start of register frame. */
739 bsp = rse_address_add (bsp, -(cfm & 0x7f));
740
741 if ((cfm & 0x7f) > regnum - V32_REGNUM)
742 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
743
744 if (gr_addr != 0)
745 {
746 /* Compute address of nat collection bits. */
747 CORE_ADDR nat_addr = gr_addr | 0x1f8;
748 CORE_ADDR nat_collection;
749 int nat_bit;
750 /* If our nat collection address is bigger than bsp, we have to get
751 the nat collection from rnat. Otherwise, we fetch the nat
752 collection from the computed address. */
753 if (nat_addr >= bsp)
754 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
755 else
756 nat_collection = read_memory_integer (nat_addr, 8);
757 nat_bit = (gr_addr >> 3) & 0x3f;
758 natN_val = (nat_collection >> nat_bit) & 1;
759 }
760
aa2a9a3c 761 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 762 }
004d836a
JJ		 763 else if (regnum == VBOF_REGNUM)
764 {
765 /* A virtual register frame start is provided for user convenience.
766 It can be calculated as the bsp - sof (sizeof frame). */
767 ULONGEST bsp, vbsp;
768 ULONGEST cfm;
769 CORE_ADDR reg;
770 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
771 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
772
773 /* The bsp points at the end of the register frame so we
774 subtract the size of frame from it to get beginning of frame. */
775 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 776 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 777 }
778 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
779 {
780 ULONGEST pr;
781 ULONGEST cfm;
782 ULONGEST prN_val;
783 CORE_ADDR reg;
784 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
785 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
786
787 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
788 {
789 /* Fetch predicate register rename base from current frame
790 marker for this frame. */
791 int rrb_pr = (cfm >> 32) & 0x3f;
792
793 /* Adjust the register number to account for register rotation. */
794 regnum = VP16_REGNUM
795 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
796 }
797 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 798 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 799 }
800 else
aa2a9a3c 801 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 802}
803
004d836a
JJ		 804static void
805ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 806 int regnum, const gdb_byte *buf)
16461d7d 807{
004d836a 808 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 809 {
004d836a
JJ		 810 ULONGEST bsp;
811 ULONGEST cfm;
812 CORE_ADDR reg;
813 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
814 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
815
816 bsp = rse_address_add (bsp, -(cfm & 0x7f));
817
818 if ((cfm & 0x7f) > regnum - V32_REGNUM)
819 {
820 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
821 write_memory (reg_addr, (void *)buf, 8);
822 }
823 }
824 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
825 {
826 ULONGEST unatN_val, unat, unatN_mask;
827 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 828 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 829 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
830 if (unatN_val == 0)
831 unat &= ~unatN_mask;
832 else if (unatN_val == 1)
833 unat |= unatN_mask;
834 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
835 }
836 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
837 {
838 ULONGEST natN_val;
839 ULONGEST bsp;
840 ULONGEST cfm;
841 CORE_ADDR gr_addr = 0;
842 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
843 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
844
845 /* The bsp points at the end of the register frame so we
846 subtract the size of frame from it to get start of register frame. */
847 bsp = rse_address_add (bsp, -(cfm & 0x7f));
848
849 if ((cfm & 0x7f) > regnum - V32_REGNUM)
850 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
851
aa2a9a3c 852 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 853
854 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
855 {
856 /* Compute address of nat collection bits. */
857 CORE_ADDR nat_addr = gr_addr | 0x1f8;
858 CORE_ADDR nat_collection;
859 int natN_bit = (gr_addr >> 3) & 0x3f;
860 ULONGEST natN_mask = (1LL << natN_bit);
861 /* If our nat collection address is bigger than bsp, we have to get
862 the nat collection from rnat. Otherwise, we fetch the nat
863 collection from the computed address. */
864 if (nat_addr >= bsp)
865 {
866 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
867 if (natN_val)
868 nat_collection |= natN_mask;
869 else
870 nat_collection &= ~natN_mask;
871 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
872 }
873 else
874 {
875 char nat_buf[8];
876 nat_collection = read_memory_integer (nat_addr, 8);
877 if (natN_val)
878 nat_collection |= natN_mask;
879 else
880 nat_collection &= ~natN_mask;
aa2a9a3c 881 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 882 write_memory (nat_addr, nat_buf, 8);
883 }
884 }
885 }
886 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
887 {
888 ULONGEST pr;
889 ULONGEST cfm;
890 ULONGEST prN_val;
891 ULONGEST prN_mask;
892
893 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
894 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
895
896 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
897 {
898 /* Fetch predicate register rename base from current frame
899 marker for this frame. */
900 int rrb_pr = (cfm >> 32) & 0x3f;
901
902 /* Adjust the register number to account for register rotation. */
903 regnum = VP16_REGNUM
904 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
905 }
aa2a9a3c 906 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 907 prN_mask = (1LL << (regnum - VP0_REGNUM));
908 if (prN_val == 0)
909 pr &= ~prN_mask;
910 else if (prN_val == 1)
911 pr |= prN_mask;
912 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 913 }
16461d7d
KB		 914}
915
004d836a
JJ		 916/* The ia64 needs to convert between various ieee floating-point formats
917 and the special ia64 floating point register format. */
918
919static int
920ia64_convert_register_p (int regno, struct type *type)
921{
922 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
923}
924
925static void
926ia64_register_to_value (struct frame_info *frame, int regnum,
88d82102 927 struct type *valtype, gdb_byte *out)
004d836a
JJ		 928{
929 char in[MAX_REGISTER_SIZE];
930 frame_register_read (frame, regnum, in);
931 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
932}
933
934static void
935ia64_value_to_register (struct frame_info *frame, int regnum,
88d82102 936 struct type *valtype, const gdb_byte *in)
004d836a
JJ		 937{
938 char out[MAX_REGISTER_SIZE];
939 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
940 put_frame_register (frame, regnum, out);
941}
942
943
58ab00f9
KB		 944/* Limit the number of skipped non-prologue instructions since examining
945 of the prologue is expensive. */
5ea2bd7f 946static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 947
948/* Given PC representing the starting address of a function, and
949 LIM_PC which is the (sloppy) limit to which to scan when looking
950 for a prologue, attempt to further refine this limit by using
951 the line data in the symbol table. If successful, a better guess
952 on where the prologue ends is returned, otherwise the previous
953 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
954 which will be set to indicate whether the returned limit may be
955 used with no further scanning in the event that the function is
956 frameless. */
957
634aa483
AC		 958/* FIXME: cagney/2004-02-14: This function and logic have largely been
959 superseded by skip_prologue_using_sal. */
960
58ab00f9
KB		 961static CORE_ADDR
962refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
963{
964 struct symtab_and_line prologue_sal;
965 CORE_ADDR start_pc = pc;
966
967 /* Start off not trusting the limit. */
968 *trust_limit = 0;
969
970 prologue_sal = find_pc_line (pc, 0);
971 if (prologue_sal.line != 0)
972 {
973 int i;
974 CORE_ADDR addr = prologue_sal.end;
975
976 /* Handle the case in which compiler's optimizer/scheduler
977 has moved instructions into the prologue. We scan ahead
978 in the function looking for address ranges whose corresponding
979 line number is less than or equal to the first one that we
980 found for the function. (It can be less than when the
981 scheduler puts a body instruction before the first prologue
982 instruction.) */
983 for (i = 2 * max_skip_non_prologue_insns;
984 i > 0 && (lim_pc == 0 || addr < lim_pc);
985 i--)
986 {
987 struct symtab_and_line sal;
988
989 sal = find_pc_line (addr, 0);
990 if (sal.line == 0)
991 break;
992 if (sal.line <= prologue_sal.line
993 && sal.symtab == prologue_sal.symtab)
994 {
995 prologue_sal = sal;
996 }
997 addr = sal.end;
998 }
999
1000 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1001 {
1002 lim_pc = prologue_sal.end;
1003 if (start_pc == get_pc_function_start (lim_pc))
1004 *trust_limit = 1;
1005 }
1006 }
1007 return lim_pc;
1008}
1009
16461d7d
KB		 1010#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1011 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1012 || (14 <= (_regnum_) && (_regnum_) <= 31))
1013#define imm9(_instr_) \
1014 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1015 | (((_instr_) & 0x00008000000LL) >> 20) \
1016 | (((_instr_) & 0x00000001fc0LL) >> 6))
1017
004d836a
JJ		 1018/* Allocate and initialize a frame cache. */
1019
1020static struct ia64_frame_cache *
1021ia64_alloc_frame_cache (void)
1022{
1023 struct ia64_frame_cache *cache;
1024 int i;
1025
1026 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1027
1028 /* Base address. */
1029 cache->base = 0;
1030 cache->pc = 0;
1031 cache->cfm = 0;
4afcc598 1032 cache->prev_cfm = 0;
004d836a
JJ		 1033 cache->sof = 0;
1034 cache->sol = 0;
1035 cache->sor = 0;
1036 cache->bsp = 0;
1037 cache->fp_reg = 0;
1038 cache->frameless = 1;
1039
1040 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1041 cache->saved_regs[i] = 0;
1042
1043 return cache;
1044}
1045
16461d7d 1046static CORE_ADDR
004d836a 1047examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1048{
1049 CORE_ADDR next_pc;
1050 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1051 instruction_type it;
1052 long long instr;
16461d7d
KB		 1053 int cfm_reg = 0;
1054 int ret_reg = 0;
1055 int fp_reg = 0;
1056 int unat_save_reg = 0;
1057 int pr_save_reg = 0;
1058 int mem_stack_frame_size = 0;
1059 int spill_reg = 0;
1060 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1061 char instores[8];
1062 char infpstores[8];
5ea2bd7f 1063 char reg_contents[256];
58ab00f9 1064 int trust_limit;
004d836a
JJ		 1065 int frameless = 1;
1066 int i;
1067 CORE_ADDR addr;
1068 char buf[8];
1069 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1070
1071 memset (instores, 0, sizeof instores);
1072 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1073 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1074
004d836a
JJ		 1075 if (cache->after_prologue != 0
1076 && cache->after_prologue <= lim_pc)
1077 return cache->after_prologue;
16461d7d 1078
58ab00f9 1079 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1080 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1081
1082 /* We want to check if we have a recognizable function start before we
1083 look ahead for a prologue. */
16461d7d
KB		 1084 if (pc < lim_pc && next_pc
1085 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1086 {
5ea2bd7f 1087 /* alloc - start of a regular function. */
16461d7d
KB		 1088 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1089 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1090 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1091 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1092
1093 /* Verify that the current cfm matches what we think is the
1094 function start. If we have somehow jumped within a function,
1095 we do not want to interpret the prologue and calculate the
1096 addresses of various registers such as the return address.
1097 We will instead treat the frame as frameless. */
1098 if (!next_frame ||
1099 (sof == (cache->cfm & 0x7f) &&
1100 sol == ((cache->cfm >> 7) & 0x7f)))
1101 frameless = 0;
1102
16461d7d
KB		 1103 cfm_reg = rN;
1104 last_prologue_pc = next_pc;
1105 pc = next_pc;
1106 }
1107 else
58ab00f9 1108 {
5ea2bd7f
JJ		 1109 /* Look for a leaf routine. */
1110 if (pc < lim_pc && next_pc
1111 && (it == I || it == M)
1112 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1113 {
1114 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1115 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1116 | ((instr & 0x001f8000000LL) >> 20)
1117 | ((instr & 0x000000fe000LL) >> 13));
1118 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1119 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1120 int qp = (int) (instr & 0x0000000003fLL);
1121 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1122 {
1123 /* mov r2, r12 - beginning of leaf routine */
1124 fp_reg = rN;
5ea2bd7f
JJ		 1125 last_prologue_pc = next_pc;
1126 }
1127 }
1128
1129 /* If we don't recognize a regular function or leaf routine, we are
1130 done. */
1131 if (!fp_reg)
1132 {
1133 pc = lim_pc;
1134 if (trust_limit)
1135 last_prologue_pc = lim_pc;
1136 }
58ab00f9 1137 }
16461d7d
KB		 1138
1139 /* Loop, looking for prologue instructions, keeping track of
1140 where preserved registers were spilled. */
1141 while (pc < lim_pc)
1142 {
1143 next_pc = fetch_instruction (pc, &it, &instr);
1144 if (next_pc == 0)
1145 break;
1146
594706e6 1147 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1148 {
102d615a
JJ		 1149 /* Exit loop upon hitting a non-nop branch instruction. */
1150 if (trust_limit)
1151 lim_pc = pc;
1152 break;
1153 }
1154 else if (((instr & 0x3fLL) != 0LL) &&
1155 (frameless || ret_reg != 0))
1156 {
1157 /* Exit loop upon hitting a predicated instruction if
1158 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1159 if (trust_limit)
1160 lim_pc = pc;
0927a22b
KB		 1161 break;
1162 }
1163 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1164 {
1165 /* Move from BR */
1166 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1167 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1168 int qp = (int) (instr & 0x0000000003f);
1169
1170 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1171 {
1172 ret_reg = rN;
1173 last_prologue_pc = next_pc;
1174 }
1175 }
1176 else if ((it == I || it == M)
1177 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1178 {
1179 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1180 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1181 | ((instr & 0x001f8000000LL) >> 20)
1182 | ((instr & 0x000000fe000LL) >> 13));
1183 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1184 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1185 int qp = (int) (instr & 0x0000000003fLL);
1186
1187 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1188 {
1189 /* mov rN, r12 */
1190 fp_reg = rN;
1191 last_prologue_pc = next_pc;
1192 }
1193 else if (qp == 0 && rN == 12 && rM == 12)
1194 {
1195 /* adds r12, -mem_stack_frame_size, r12 */
1196 mem_stack_frame_size -= imm;
1197 last_prologue_pc = next_pc;
1198 }
1199 else if (qp == 0 && rN == 2
1200 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1201 {
004d836a
JJ		 1202 char buf[MAX_REGISTER_SIZE];
1203 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1204 /* adds r2, spilloffset, rFramePointer
1205 or
1206 adds r2, spilloffset, r12
1207
1208 Get ready for stf.spill or st8.spill instructions.
1209 The address to start spilling at is loaded into r2.
1210 FIXME: Why r2? That's what gcc currently uses; it
1211 could well be different for other compilers. */
1212
1213 /* Hmm... whether or not this will work will depend on
1214 where the pc is. If it's still early in the prologue
1215 this'll be wrong. FIXME */
004d836a
JJ		 1216 if (next_frame)
1217 {
1218 frame_unwind_register (next_frame, sp_regnum, buf);
1219 saved_sp = extract_unsigned_integer (buf, 8);
1220 }
1221 spill_addr = saved_sp
16461d7d
KB		 1222 + (rM == 12 ? 0 : mem_stack_frame_size)
1223 + imm;
1224 spill_reg = rN;
1225 last_prologue_pc = next_pc;
1226 }
5ea2bd7f
JJ		 1227 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1228 rN < 256 && imm == 0)
1229 {
1230 /* mov rN, rM where rM is an input register */
1231 reg_contents[rN] = rM;
1232 last_prologue_pc = next_pc;
1233 }
1234 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1235 rM == 2)
1236 {
1237 /* mov r12, r2 */
1238 last_prologue_pc = next_pc;
1239 break;
1240 }
16461d7d
KB		 1241 }
1242 else if (it == M
1243 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1244 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1245 {
1246 /* stf.spill [rN] = fM, imm9
1247 or
1248 stf.spill [rN] = fM */
1249
1250 int imm = imm9(instr);
1251 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1252 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1253 int qp = (int) (instr & 0x0000000003fLL);
1254 if (qp == 0 && rN == spill_reg && spill_addr != 0
1255 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1256 {
004d836a 1257 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1258
594706e6 1259 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1260 spill_addr += imm;
1261 else
1262 spill_addr = 0; /* last one; must be done */
1263 last_prologue_pc = next_pc;
1264 }
1265 }
1266 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1267 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1268 {
1269 /* mov.m rN = arM
1270 or
1271 mov.i rN = arM */
1272
1273 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1274 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1275 int qp = (int) (instr & 0x0000000003fLL);
1276 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1277 {
1278 /* We have something like "mov.m r3 = ar.unat". Remember the
1279 r3 (or whatever) and watch for a store of this register... */
1280 unat_save_reg = rN;
1281 last_prologue_pc = next_pc;
1282 }
1283 }
1284 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1285 {
1286 /* mov rN = pr */
1287 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1288 int qp = (int) (instr & 0x0000000003fLL);
1289 if (qp == 0 && isScratch (rN))
1290 {
1291 pr_save_reg = rN;
1292 last_prologue_pc = next_pc;
1293 }
1294 }
1295 else if (it == M
1296 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1297 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1298 {
1299 /* st8 [rN] = rM
1300 or
1301 st8 [rN] = rM, imm9 */
1302 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1303 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1304 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1305 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1306 if (qp == 0 && rN == spill_reg && spill_addr != 0
1307 && (rM == unat_save_reg || rM == pr_save_reg))
1308 {
1309 /* We've found a spill of either the UNAT register or the PR
1310 register. (Well, not exactly; what we've actually found is
1311 a spill of the register that UNAT or PR was moved to).
1312 Record that fact and move on... */
1313 if (rM == unat_save_reg)
1314 {
1315 /* Track UNAT register */
004d836a 1316 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1317 unat_save_reg = 0;
1318 }
1319 else
1320 {
1321 /* Track PR register */
004d836a 1322 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1323 pr_save_reg = 0;
1324 }
1325 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1326 /* st8 [rN] = rM, imm9 */
1327 spill_addr += imm9(instr);
1328 else
1329 spill_addr = 0; /* must be done spilling */
1330 last_prologue_pc = next_pc;
1331 }
0927a22b
KB		 1332 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1333 {
1334 /* Allow up to one store of each input register. */
1335 instores[rM-32] = 1;
1336 last_prologue_pc = next_pc;
1337 }
5ea2bd7f
JJ		 1338 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1339 !instores[indirect-32])
1340 {
1341 /* Allow an indirect store of an input register. */
1342 instores[indirect-32] = 1;
1343 last_prologue_pc = next_pc;
1344 }
0927a22b
KB		 1345 }
1346 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1347 {
1348 /* One of
1349 st1 [rN] = rM
1350 st2 [rN] = rM
1351 st4 [rN] = rM
1352 st8 [rN] = rM
1353 Note that the st8 case is handled in the clause above.
1354
1355 Advance over stores of input registers. One store per input
1356 register is permitted. */
1357 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1358 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1359 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1360 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1361 {
1362 instores[rM-32] = 1;
1363 last_prologue_pc = next_pc;
1364 }
5ea2bd7f
JJ		 1365 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1366 !instores[indirect-32])
1367 {
1368 /* Allow an indirect store of an input register. */
1369 instores[indirect-32] = 1;
1370 last_prologue_pc = next_pc;
1371 }
0927a22b
KB		 1372 }
1373 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1374 {
1375 /* Either
1376 stfs [rN] = fM
1377 or
1378 stfd [rN] = fM
1379
1380 Advance over stores of floating point input registers. Again
1381 one store per register is permitted */
1382 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1383 int qp = (int) (instr & 0x0000000003fLL);
1384 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1385 {
1386 infpstores[fM-8] = 1;
1387 last_prologue_pc = next_pc;
1388 }
16461d7d
KB		 1389 }
1390 else if (it == M
1391 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1392 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1393 {
1394 /* st8.spill [rN] = rM
1395 or
1396 st8.spill [rN] = rM, imm9 */
1397 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1398 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1399 int qp = (int) (instr & 0x0000000003fLL);
1400 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1401 {
1402 /* We've found a spill of one of the preserved general purpose
1403 regs. Record the spill address and advance the spill
1404 register if appropriate. */
004d836a 1405 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1406 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1407 /* st8.spill [rN] = rM, imm9 */
1408 spill_addr += imm9(instr);
1409 else
1410 spill_addr = 0; /* Done spilling */
1411 last_prologue_pc = next_pc;
1412 }
1413 }
16461d7d
KB		 1414
1415 pc = next_pc;
1416 }
1417
004d836a
JJ		 1418 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1419 registers for the previous frame which will be needed later. */
16461d7d 1420
004d836a 1421 if (!frameless && next_frame)
da50a4b7 1422 {
004d836a
JJ		 1423 /* Extract the size of the rotating portion of the stack
1424 frame and the register rename base from the current
1425 frame marker. */
1426 cfm = cache->cfm;
1427 sor = cache->sor;
1428 sof = cache->sof;
1429 sol = cache->sol;
1430 rrb_gr = (cfm >> 18) & 0x7f;
1431
1432 /* Find the bof (beginning of frame). */
1433 bof = rse_address_add (cache->bsp, -sof);
1434
1435 for (i = 0, addr = bof;
1436 i < sof;
1437 i++, addr += 8)
1438 {
1439 if (IS_NaT_COLLECTION_ADDR (addr))
1440 {
1441 addr += 8;
1442 }
1443 if (i+32 == cfm_reg)
1444 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1445 if (i+32 == ret_reg)
1446 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1447 if (i+32 == fp_reg)
1448 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1449 }
16461d7d 1450
004d836a
JJ		 1451 /* For the previous argument registers we require the previous bof.
1452 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1453 cfm = 0;
004d836a
JJ		 1454 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1455 {
1456 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1457 }
1458 else if (cfm_reg != 0)
1459 {
1460 frame_unwind_register (next_frame, cfm_reg, buf);
1461 cfm = extract_unsigned_integer (buf, 8);
1462 }
1463 cache->prev_cfm = cfm;
1464
1465 if (cfm != 0)
1466 {
004d836a
JJ		 1467 sor = ((cfm >> 14) & 0xf) * 8;
1468 sof = (cfm & 0x7f);
1469 sol = (cfm >> 7) & 0x7f;
1470 rrb_gr = (cfm >> 18) & 0x7f;
1471
1472 /* The previous bof only requires subtraction of the sol (size of locals)
1473 due to the overlap between output and input of subsequent frames. */
1474 bof = rse_address_add (bof, -sol);
1475
1476 for (i = 0, addr = bof;
1477 i < sof;
1478 i++, addr += 8)
1479 {
1480 if (IS_NaT_COLLECTION_ADDR (addr))
1481 {
1482 addr += 8;
1483 }
1484 if (i < sor)
1485 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1486 = addr;
1487 else
1488 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1489 }
1490
1491 }
1492 }
1493
5ea2bd7f
JJ		 1494 /* Try and trust the lim_pc value whenever possible. */
1495 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1496 last_prologue_pc = lim_pc;
1497
1498 cache->frameless = frameless;
1499 cache->after_prologue = last_prologue_pc;
1500 cache->mem_stack_frame_size = mem_stack_frame_size;
1501 cache->fp_reg = fp_reg;
5ea2bd7f 1502
16461d7d
KB		 1503 return last_prologue_pc;
1504}
1505
1506CORE_ADDR
1507ia64_skip_prologue (CORE_ADDR pc)
1508{
004d836a
JJ		 1509 struct ia64_frame_cache cache;
1510 cache.base = 0;
1511 cache.after_prologue = 0;
1512 cache.cfm = 0;
1513 cache.bsp = 0;
1514
1515 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1516 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1517}
1518
004d836a
JJ		 1519
1520/* Normal frames. */
1521
1522static struct ia64_frame_cache *
1523ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1524{
004d836a
JJ		 1525 struct ia64_frame_cache *cache;
1526 char buf[8];
1527 CORE_ADDR cfm, sof, sol, bsp, psr;
1528 int i;
16461d7d 1529
004d836a
JJ		 1530 if (*this_cache)
1531 return *this_cache;
16461d7d 1532
004d836a
JJ		 1533 cache = ia64_alloc_frame_cache ();
1534 *this_cache = cache;
16461d7d 1535
004d836a
JJ		 1536 frame_unwind_register (next_frame, sp_regnum, buf);
1537 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1538
004d836a
JJ		 1539 /* We always want the bsp to point to the end of frame.
1540 This way, we can always get the beginning of frame (bof)
1541 by subtracting frame size. */
1542 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1543 cache->bsp = extract_unsigned_integer (buf, 8);
1544
1545 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1546 psr = extract_unsigned_integer (buf, 8);
1547
1548 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1549 cfm = extract_unsigned_integer (buf, 8);
1550
1551 cache->sof = (cfm & 0x7f);
1552 cache->sol = (cfm >> 7) & 0x7f;
1553 cache->sor = ((cfm >> 14) & 0xf) * 8;
1554
1555 cache->cfm = cfm;
1556
1557 cache->pc = frame_func_unwind (next_frame);
1558
1559 if (cache->pc != 0)
1560 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1561
1562 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1563
1564 return cache;
16461d7d
KB		 1565}
1566
a78f21af 1567static void
004d836a
JJ		 1568ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1569 struct frame_id *this_id)
16461d7d 1570{
004d836a
JJ		 1571 struct ia64_frame_cache *cache =
1572 ia64_frame_cache (next_frame, this_cache);
16461d7d 1573
c5a27d9c 1574 /* If outermost frame, mark with null frame id. */
004d836a 1575 if (cache->base == 0)
c5a27d9c
JJ		 1576 (*this_id) = null_frame_id;
1577 else
1578 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1579 if (gdbarch_debug >= 1)
1580 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1581 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1582 paddr_nz (this_id->code_addr),
1583 paddr_nz (this_id->stack_addr),
1584 paddr_nz (cache->bsp), next_frame);
004d836a 1585}
244bc108 1586
004d836a
JJ		 1587static void
1588ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1589 int regnum, int *optimizedp,
1590 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1591 int *realnump, gdb_byte *valuep)
004d836a
JJ		 1592{
1593 struct ia64_frame_cache *cache =
1594 ia64_frame_cache (next_frame, this_cache);
1595 char dummy_valp[MAX_REGISTER_SIZE];
1596 char buf[8];
1597
1598 gdb_assert (regnum >= 0);
244bc108 1599
004d836a 1600 if (!target_has_registers)
8a3fe4f8 1601 error (_("No registers."));
244bc108 1602
004d836a
JJ		 1603 *optimizedp = 0;
1604 *addrp = 0;
1605 *lvalp = not_lval;
1606 *realnump = -1;
244bc108 1607
004d836a
JJ		 1608 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1609 when valuep is not supplied. */
1610 if (!valuep)
1611 valuep = dummy_valp;
1612
aa2a9a3c 1613 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1614
1615 if (regnum == SP_REGNUM)
16461d7d
KB		 1616 {
1617 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1618 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1619 cache->base);
16461d7d
KB		 1620 }
1621 else if (regnum == IA64_BSP_REGNUM)
1622 {
004d836a
JJ		 1623 char cfm_valuep[MAX_REGISTER_SIZE];
1624 int cfm_optim;
1625 int cfm_realnum;
1626 enum lval_type cfm_lval;
1627 CORE_ADDR cfm_addr;
1628 CORE_ADDR bsp, prev_cfm, prev_bsp;
1629
1630 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1631 This corresponds to what the hardware bsp register will be if we pop the frame
1632 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1633 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1634 the start of the output registers. We can calculate the end of that frame by adding
1635 the size of output (sof (size of frame) - sol (size of locals)). */
1636 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1637 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1638 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1639
1640 bsp = rse_address_add (cache->bsp, -(cache->sof));
1641 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1642
aa2a9a3c 1643 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1644 prev_bsp);
1645 }
1646 else if (regnum == IA64_CFM_REGNUM)
1647 {
4afcc598
JJ		 1648 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1649
1650 if (addr != 0)
004d836a 1651 {
4afcc598
JJ		 1652 *lvalp = lval_memory;
1653 *addrp = addr;
1654 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1655 }
4afcc598
JJ		 1656 else if (cache->prev_cfm)
1657 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1658 else if (cache->frameless)
004d836a 1659 {
4afcc598
JJ		 1660 CORE_ADDR cfm = 0;
1661 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1662 }
16461d7d
KB		 1663 }
1664 else if (regnum == IA64_VFP_REGNUM)
1665 {
1666 /* If the function in question uses an automatic register (r32-r127)
1667 for the frame pointer, it'll be found by ia64_find_saved_register()
1668 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1669 still provide a value since we know the size of the frame. */
1670 CORE_ADDR vfp = cache->base;
aa2a9a3c 1671 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1672 }
004d836a 1673 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1674 {
004d836a 1675 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1676 int pr_optim;
004d836a 1677 int pr_realnum;
16461d7d
KB		 1678 enum lval_type pr_lval;
1679 CORE_ADDR pr_addr;
004d836a
JJ		 1680 ULONGEST prN_val;
1681 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1682 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1683 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1684 {
1685 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1686 marker for this frame. */
1687 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1688
004d836a
JJ		 1689 /* Adjust the register number to account for register rotation. */
1690 regnum = VP16_REGNUM
1691 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1692 }
004d836a
JJ		 1693 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1694 regnum - VP0_REGNUM, 1);
aa2a9a3c 1695 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1696 }
1697 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1698 {
004d836a 1699 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1700 int unat_optim;
004d836a 1701 int unat_realnum;
16461d7d
KB		 1702 enum lval_type unat_lval;
1703 CORE_ADDR unat_addr;
004d836a
JJ		 1704 ULONGEST unatN_val;
1705 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1706 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1707 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1708 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1709 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1710 unatN_val);
16461d7d
KB		 1711 }
1712 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1713 {
1714 int natval = 0;
1715 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1716 interested in. */
1717 CORE_ADDR gr_addr;
244bc108 1718
004d836a
JJ		 1719 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1720 + IA64_GR0_REGNUM];
1721 if (gr_addr != 0)
244bc108 1722 {
004d836a 1723 /* Compute address of nat collection bits. */
16461d7d 1724 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1725 CORE_ADDR bsp;
16461d7d
KB		 1726 CORE_ADDR nat_collection;
1727 int nat_bit;
1728 /* If our nat collection address is bigger than bsp, we have to get
1729 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1730 collection from the computed address. */
1731 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1732 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1733 if (nat_addr >= bsp)
004d836a
JJ		 1734 {
1735 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1736 nat_collection = extract_unsigned_integer (buf, 8);
1737 }
16461d7d
KB		 1738 else
1739 nat_collection = read_memory_integer (nat_addr, 8);
1740 nat_bit = (gr_addr >> 3) & 0x3f;
1741 natval = (nat_collection >> nat_bit) & 1;
1742 }
004d836a 1743
aa2a9a3c 1744 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1745 }
1746 else if (regnum == IA64_IP_REGNUM)
1747 {
004d836a 1748 CORE_ADDR pc = 0;
4afcc598 1749 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1750
4afcc598 1751 if (addr != 0)
004d836a 1752 {
4afcc598
JJ		 1753 *lvalp = lval_memory;
1754 *addrp = addr;
1755 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1756 pc = extract_unsigned_integer (buf, 8);
1757 }
4afcc598 1758 else if (cache->frameless)
004d836a 1759 {
4afcc598
JJ		 1760 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1761 pc = extract_unsigned_integer (buf, 8);
244bc108 1762 }
004d836a
JJ		 1763 pc &= ~0xf;
1764 store_unsigned_integer (valuep, 8, pc);
244bc108 1765 }
004d836a 1766 else if (regnum == IA64_PSR_REGNUM)
244bc108 1767 {
4afcc598
JJ		 1768 /* We don't know how to get the complete previous PSR, but we need it for
1769 the slot information when we unwind the pc (pc is formed of IP register
1770 plus slot information from PSR). To get the previous slot information,
1771 we mask it off the return address. */
004d836a
JJ		 1772 ULONGEST slot_num = 0;
1773 CORE_ADDR pc= 0;
1774 CORE_ADDR psr = 0;
4afcc598 1775 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1776
1777 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1778 psr = extract_unsigned_integer (buf, 8);
1779
4afcc598 1780 if (addr != 0)
244bc108 1781 {
4afcc598
JJ		 1782 *lvalp = lval_memory;
1783 *addrp = addr;
1784 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1785 pc = extract_unsigned_integer (buf, 8);
244bc108 1786 }
4afcc598 1787 else if (cache->frameless)
004d836a 1788 {
4afcc598
JJ		 1789 CORE_ADDR pc;
1790 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1791 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1792 }
1793 psr &= ~(3LL << 41);
1794 slot_num = pc & 0x3LL;
1795 psr |= (CORE_ADDR)slot_num << 41;
1796 store_unsigned_integer (valuep, 8, psr);
1797 }
4afcc598
JJ		 1798 else if (regnum == IA64_BR0_REGNUM)
1799 {
1800 CORE_ADDR br0 = 0;
1801 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1802 if (addr != 0)
1803 {
1804 *lvalp = lval_memory;
1805 *addrp = addr;
1806 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1807 br0 = extract_unsigned_integer (buf, 8);
1808 }
1809 store_unsigned_integer (valuep, 8, br0);
1810 }
004d836a
JJ		 1811 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1812 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1813 {
1814 CORE_ADDR addr = 0;
1815 if (regnum >= V32_REGNUM)
1816 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1817 addr = cache->saved_regs[regnum];
244bc108
KB		 1818 if (addr != 0)
1819 {
004d836a
JJ		 1820 *lvalp = lval_memory;
1821 *addrp = addr;
aa2a9a3c 1822 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1823 }
004d836a 1824 else if (cache->frameless)
244bc108 1825 {
004d836a
JJ		 1826 char r_valuep[MAX_REGISTER_SIZE];
1827 int r_optim;
1828 int r_realnum;
1829 enum lval_type r_lval;
1830 CORE_ADDR r_addr;
1831 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1832 CORE_ADDR addr = 0;
1833 if (regnum >= V32_REGNUM)
1834 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1835 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1836 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1837 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1838 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1839 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1840 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1841 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1842
1843 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1844 *lvalp = lval_memory;
1845 *addrp = addr;
aa2a9a3c 1846 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1847 }
16461d7d
KB		 1848 }
1849 else
1850 {
004d836a 1851 CORE_ADDR addr = 0;
3a854e23
KB		 1852 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1853 {
1854 /* Fetch floating point register rename base from current
004d836a
JJ		 1855 frame marker for this frame. */
1856 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1857
1858 /* Adjust the floating point register number to account for
004d836a 1859 register rotation. */
3a854e23
KB		 1860 regnum = IA64_FR32_REGNUM
1861 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1862 }
1863
004d836a
JJ		 1864 /* If we have stored a memory address, access the register. */
1865 addr = cache->saved_regs[regnum];
1866 if (addr != 0)
1867 {
1868 *lvalp = lval_memory;
1869 *addrp = addr;
aa2a9a3c 1870 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1871 }
1872 /* Otherwise, punt and get the current value of the register. */
1873 else
1874 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1875 }
4afcc598
JJ		 1876
1877 if (gdbarch_debug >= 1)
1878 fprintf_unfiltered (gdb_stdlog,
78ced177 1879 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1880 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1881 ? ia64_register_names[regnum] : "r??"),
1882 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1883}
004d836a
JJ		 1884
1885static const struct frame_unwind ia64_frame_unwind =
1886{
1887 NORMAL_FRAME,
1888 &ia64_frame_this_id,
1889 &ia64_frame_prev_register
1890};
1891
1892static const struct frame_unwind *
1893ia64_frame_sniffer (struct frame_info *next_frame)
1894{
1895 return &ia64_frame_unwind;
1896}
1897
1898/* Signal trampolines. */
1899
1900static void
1901ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1902{
1903 if (SIGCONTEXT_REGISTER_ADDRESS)
1904 {
1905 int regno;
1906
1907 cache->saved_regs[IA64_VRAP_REGNUM] =
1908 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1909 cache->saved_regs[IA64_CFM_REGNUM] =
1910 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1911 cache->saved_regs[IA64_PSR_REGNUM] =
1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1913 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1915 cache->saved_regs[IA64_RNAT_REGNUM] =
1916 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1917 cache->saved_regs[IA64_CCV_REGNUM] =
1918 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1919 cache->saved_regs[IA64_UNAT_REGNUM] =
1920 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1921 cache->saved_regs[IA64_FPSR_REGNUM] =
1922 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1923 cache->saved_regs[IA64_PFS_REGNUM] =
1924 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1925 cache->saved_regs[IA64_LC_REGNUM] =
1926 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1927 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1928 cache->saved_regs[regno] =
1929 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1930 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1931 cache->saved_regs[regno] =
1932 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1933 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1934 cache->saved_regs[regno] =
1935 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1936 }
1937}
1938
1939static struct ia64_frame_cache *
1940ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1941{
1942 struct ia64_frame_cache *cache;
1943 CORE_ADDR addr;
1944 char buf[8];
1945 int i;
1946
1947 if (*this_cache)
1948 return *this_cache;
1949
1950 cache = ia64_alloc_frame_cache ();
1951
1952 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1953 /* Note that frame size is hard-coded below. We cannot calculate it
1954 via prologue examination. */
1955 cache->base = extract_unsigned_integer (buf, 8) + 16;
1956
1957 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1958 cache->bsp = extract_unsigned_integer (buf, 8);
1959
1960 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1961 cache->cfm = extract_unsigned_integer (buf, 8);
1962 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1963
1964 ia64_sigtramp_frame_init_saved_regs (cache);
1965
1966 *this_cache = cache;
1967 return cache;
1968}
1969
1970static void
1971ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1972 void **this_cache, struct frame_id *this_id)
1973{
1974 struct ia64_frame_cache *cache =
1975 ia64_sigtramp_frame_cache (next_frame, this_cache);
1976
4afcc598
JJ		 1977 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1978 if (gdbarch_debug >= 1)
1979 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1980 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1981 paddr_nz (this_id->code_addr),
1982 paddr_nz (this_id->stack_addr),
1983 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1984}
1985
1986static void
1987ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1988 void **this_cache,
1989 int regnum, int *optimizedp,
1990 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1991 int *realnump, gdb_byte *valuep)
004d836a 1992{
4afcc598
JJ		 1993 char dummy_valp[MAX_REGISTER_SIZE];
1994 char buf[MAX_REGISTER_SIZE];
1995
1996 struct ia64_frame_cache *cache =
1997 ia64_sigtramp_frame_cache (next_frame, this_cache);
1998
1999 gdb_assert (regnum >= 0);
2000
2001 if (!target_has_registers)
8a3fe4f8 2002 error (_("No registers."));
4afcc598
JJ		 2003
2004 *optimizedp = 0;
2005 *addrp = 0;
2006 *lvalp = not_lval;
2007 *realnump = -1;
2008
2009 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2010 when valuep is not supplied. */
2011 if (!valuep)
2012 valuep = dummy_valp;
2013
2014 memset (valuep, 0, register_size (current_gdbarch, regnum));
2015
2016 if (regnum == IA64_IP_REGNUM)
2017 {
2018 CORE_ADDR pc = 0;
2019 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2020
2021 if (addr != 0)
2022 {
2023 *lvalp = lval_memory;
2024 *addrp = addr;
2025 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2026 pc = extract_unsigned_integer (buf, 8);
2027 }
2028 pc &= ~0xf;
2029 store_unsigned_integer (valuep, 8, pc);
2030 }
2031 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2032 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2033 {
2034 CORE_ADDR addr = 0;
2035 if (regnum >= V32_REGNUM)
2036 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2037 addr = cache->saved_regs[regnum];
2038 if (addr != 0)
2039 {
2040 *lvalp = lval_memory;
2041 *addrp = addr;
2042 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2043 }
2044 }
2045 else
2046 {
2047 /* All other registers not listed above. */
2048 CORE_ADDR addr = cache->saved_regs[regnum];
2049 if (addr != 0)
2050 {
2051 *lvalp = lval_memory;
2052 *addrp = addr;
2053 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2054 }
2055 }
004d836a 2056
4afcc598
JJ		 2057 if (gdbarch_debug >= 1)
2058 fprintf_unfiltered (gdb_stdlog,
78ced177 2059 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2060 (regnum < IA64_GR32_REGNUM
2061 || (regnum > IA64_GR127_REGNUM
2062 && regnum < LAST_PSEUDO_REGNUM))
2063 ? ia64_register_names[regnum]
2064 : (regnum < LAST_PSEUDO_REGNUM
2065 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2066 : "OUT_OF_RANGE"),
78ced177 2067 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2068}
2069
2070static const struct frame_unwind ia64_sigtramp_frame_unwind =
2071{
2072 SIGTRAMP_FRAME,
2073 ia64_sigtramp_frame_this_id,
2074 ia64_sigtramp_frame_prev_register
2075};
2076
2077static const struct frame_unwind *
2078ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2079{
2080 char *name;
2081 CORE_ADDR pc = frame_pc_unwind (next_frame);
2082
2083 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2084 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2085 return &ia64_sigtramp_frame_unwind;
2086
2087 return NULL;
2088}
2089\f
2090
2091static CORE_ADDR
2092ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2093{
2094 struct ia64_frame_cache *cache =
2095 ia64_frame_cache (next_frame, this_cache);
2096
2097 return cache->base;
2098}
2099
2100static const struct frame_base ia64_frame_base =
2101{
2102 &ia64_frame_unwind,
2103 ia64_frame_base_address,
2104 ia64_frame_base_address,
2105 ia64_frame_base_address
2106};
16461d7d 2107
968d1cb4
JJ		 2108#ifdef HAVE_LIBUNWIND_IA64_H
2109
2110struct ia64_unwind_table_entry
2111 {
2112 unw_word_t start_offset;
2113 unw_word_t end_offset;
2114 unw_word_t info_offset;
2115 };
2116
2117static __inline__ uint64_t
2118ia64_rse_slot_num (uint64_t addr)
2119{
2120 return (addr >> 3) & 0x3f;
2121}
2122
2123/* Skip over a designated number of registers in the backing
2124 store, remembering every 64th position is for NAT. */
2125static __inline__ uint64_t
2126ia64_rse_skip_regs (uint64_t addr, long num_regs)
2127{
2128 long delta = ia64_rse_slot_num(addr) + num_regs;
2129
2130 if (num_regs < 0)
2131 delta -= 0x3e;
2132 return addr + ((num_regs + delta/0x3f) << 3);
2133}
2134
2135/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2136 number to a libunwind register number. */
2137static int
2138ia64_gdb2uw_regnum (int regnum)
2139{
2140 if (regnum == sp_regnum)
2141 return UNW_IA64_SP;
2142 else if (regnum == IA64_BSP_REGNUM)
2143 return UNW_IA64_BSP;
2144 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2145 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2146 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2147 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2148 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2149 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2150 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2151 return -1;
2152 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2153 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2154 else if (regnum == IA64_PR_REGNUM)
2155 return UNW_IA64_PR;
2156 else if (regnum == IA64_IP_REGNUM)
2157 return UNW_REG_IP;
2158 else if (regnum == IA64_CFM_REGNUM)
2159 return UNW_IA64_CFM;
2160 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2161 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2162 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2163 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2164 else
2165 return -1;
2166}
2167
2168/* Gdb libunwind-frame callback function to convert from a libunwind register
2169 number to a ia64 gdb register number. */
2170static int
2171ia64_uw2gdb_regnum (int uw_regnum)
2172{
2173 if (uw_regnum == UNW_IA64_SP)
2174 return sp_regnum;
2175 else if (uw_regnum == UNW_IA64_BSP)
2176 return IA64_BSP_REGNUM;
2177 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2178 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2179 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2180 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2181 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2182 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2183 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2184 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2185 else if (uw_regnum == UNW_IA64_PR)
2186 return IA64_PR_REGNUM;
2187 else if (uw_regnum == UNW_REG_IP)
2188 return IA64_IP_REGNUM;
2189 else if (uw_regnum == UNW_IA64_CFM)
2190 return IA64_CFM_REGNUM;
2191 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2192 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2193 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2194 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2195 else
2196 return -1;
2197}
2198
2199/* Gdb libunwind-frame callback function to reveal if register is a float
2200 register or not. */
2201static int
2202ia64_is_fpreg (int uw_regnum)
2203{
2204 return unw_is_fpreg (uw_regnum);
2205}
2206
2207/* Libunwind callback accessor function for general registers. */
2208static int
2209ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2210 int write, void *arg)
2211{
2212 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2213 unw_word_t bsp, sof, sol, cfm, psr, ip;
2214 struct frame_info *next_frame = arg;
2215 long new_sof, old_sof;
2216 char buf[MAX_REGISTER_SIZE];
2217
2218 if (write)
2219 {
2220 if (regnum < 0)
2221 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2222 return 0;
2223
2224 switch (uw_regnum)
2225 {
2226 case UNW_REG_IP:
2227 ia64_write_pc (*val, inferior_ptid);
2228 break;
2229
2230 case UNW_IA64_AR_BSPSTORE:
2231 write_register (IA64_BSP_REGNUM, *val);
2232 break;
2233
2234 case UNW_IA64_AR_BSP:
2235 case UNW_IA64_BSP:
2236 /* Account for the fact that ptrace() expects bsp to point
2237 after the current register frame. */
2238 cfm = read_register (IA64_CFM_REGNUM);
2239 sof = (cfm & 0x7f);
2240 bsp = ia64_rse_skip_regs (*val, sof);
2241 write_register (IA64_BSP_REGNUM, bsp);
2242 break;
2243
2244 case UNW_IA64_CFM:
2245 /* If we change CFM, we need to adjust ptrace's notion of
2246 bsp accordingly, so that the real bsp remains
2247 unchanged. */
2248 bsp = read_register (IA64_BSP_REGNUM);
2249 cfm = read_register (IA64_CFM_REGNUM);
2250 old_sof = (cfm & 0x7f);
2251 new_sof = (*val & 0x7f);
2252 if (old_sof != new_sof)
2253 {
2254 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2255 write_register (IA64_BSP_REGNUM, bsp);
2256 }
2257 write_register (IA64_CFM_REGNUM, *val);
2258 break;
2259
2260 default:
2261 write_register (regnum, *val);
2262 break;
2263 }
2264 if (gdbarch_debug >= 1)
2265 fprintf_unfiltered (gdb_stdlog,
78ced177 2266 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2267 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2268 ? ia64_register_names[regnum] : "r??"),
2269 paddr_nz (*val));
968d1cb4
JJ		 2270 }
2271 else
2272 {
2273 switch (uw_regnum)
2274 {
2275 case UNW_REG_IP:
2276 /* Libunwind expects to see the pc value which means the slot number
2277 from the psr must be merged with the ip word address. */
2278 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2279 ip = extract_unsigned_integer (buf, 8);
2280 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2281 psr = extract_unsigned_integer (buf, 8);
2282 *val = ip | ((psr >> 41) & 0x3);
2283 break;
2284
2285 case UNW_IA64_AR_BSP:
2286 /* Libunwind expects to see the beginning of the current register
2287 frame so we must account for the fact that ptrace() will return a value
2288 for bsp that points *after* the current register frame. */
2289 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2290 bsp = extract_unsigned_integer (buf, 8);
2291 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2292 cfm = extract_unsigned_integer (buf, 8);
2293 sof = (cfm & 0x7f);
2294 *val = ia64_rse_skip_regs (bsp, -sof);
2295 break;
2296
2297 case UNW_IA64_AR_BSPSTORE:
2298 /* Libunwind wants bspstore to be after the current register frame.
2299 This is what ptrace() and gdb treats as the regular bsp value. */
2300 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2301 *val = extract_unsigned_integer (buf, 8);
2302 break;
2303
2304 default:
2305 /* For all other registers, just unwind the value directly. */
2306 frame_unwind_register (next_frame, regnum, buf);
2307 *val = extract_unsigned_integer (buf, 8);
2308 break;
2309 }
2310
2311 if (gdbarch_debug >= 1)
2312 fprintf_unfiltered (gdb_stdlog,
78ced177 2313 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2314 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2315 ? ia64_register_names[regnum] : "r??"),
2316 paddr_nz (*val));
968d1cb4
JJ		 2317 }
2318 return 0;
2319}
2320
2321/* Libunwind callback accessor function for floating-point registers. */
2322static int
2323ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2324 int write, void *arg)
2325{
2326 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2327
2328 if (write)
2329 regcache_cooked_write (current_regcache, regnum, (char *) val);
2330 else
2331 regcache_cooked_read (current_regcache, regnum, (char *) val);
2332 return 0;
2333}
2334
c5a27d9c
JJ		 2335/* Libunwind callback accessor function for top-level rse registers. */
2336static int
2337ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2338 int write, void *arg)
2339{
2340 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2341 unw_word_t bsp, sof, sol, cfm, psr, ip;
2342 long new_sof, old_sof;
2343
2344 if (write)
2345 {
2346 if (regnum < 0)
2347 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2348 return 0;
2349
2350 switch (uw_regnum)
2351 {
2352 case UNW_REG_IP:
2353 ia64_write_pc (*val, inferior_ptid);
2354 break;
2355
2356 case UNW_IA64_AR_BSPSTORE:
2357 write_register (IA64_BSP_REGNUM, *val);
2358 break;
2359
2360 case UNW_IA64_AR_BSP:
2361 case UNW_IA64_BSP:
2362 /* Account for the fact that ptrace() expects bsp to point
2363 after the current register frame. */
2364 cfm = read_register (IA64_CFM_REGNUM);
2365 sof = (cfm & 0x7f);
2366 bsp = ia64_rse_skip_regs (*val, sof);
2367 write_register (IA64_BSP_REGNUM, bsp);
2368 break;
2369
2370 case UNW_IA64_CFM:
2371 /* If we change CFM, we need to adjust ptrace's notion of
2372 bsp accordingly, so that the real bsp remains
2373 unchanged. */
2374 bsp = read_register (IA64_BSP_REGNUM);
2375 cfm = read_register (IA64_CFM_REGNUM);
2376 old_sof = (cfm & 0x7f);
2377 new_sof = (*val & 0x7f);
2378 if (old_sof != new_sof)
2379 {
2380 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2381 write_register (IA64_BSP_REGNUM, bsp);
2382 }
2383 write_register (IA64_CFM_REGNUM, *val);
2384 break;
2385
2386 default:
2387 write_register (regnum, *val);
2388 break;
2389 }
2390 if (gdbarch_debug >= 1)
2391 fprintf_unfiltered (gdb_stdlog,
2392 " access_rse_reg: to cache: %4s=0x%s\n",
2393 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2394 ? ia64_register_names[regnum] : "r??"),
2395 paddr_nz (*val));
2396 }
2397 else
2398 {
2399 switch (uw_regnum)
2400 {
2401 case UNW_REG_IP:
2402 /* Libunwind expects to see the pc value which means the slot number
2403 from the psr must be merged with the ip word address. */
2404 ip = read_register (IA64_IP_REGNUM);
2405 psr = read_register (IA64_PSR_REGNUM);
2406 *val = ip | ((psr >> 41) & 0x3);
2407 break;
2408
2409 case UNW_IA64_AR_BSP:
2410 /* Libunwind expects to see the beginning of the current register
2411 frame so we must account for the fact that ptrace() will return a value
2412 for bsp that points *after* the current register frame. */
2413 bsp = read_register (IA64_BSP_REGNUM);
2414 cfm = read_register (IA64_CFM_REGNUM);
2415 sof = (cfm & 0x7f);
2416 *val = ia64_rse_skip_regs (bsp, -sof);
2417 break;
2418
2419 case UNW_IA64_AR_BSPSTORE:
2420 /* Libunwind wants bspstore to be after the current register frame.
2421 This is what ptrace() and gdb treats as the regular bsp value. */
2422 *val = read_register (IA64_BSP_REGNUM);
2423 break;
2424
2425 default:
2426 /* For all other registers, just read the value directly. */
2427 *val = read_register (regnum);
2428 break;
2429 }
2430 }
2431
2432 if (gdbarch_debug >= 1)
2433 fprintf_unfiltered (gdb_stdlog,
2434 " access_rse_reg: from cache: %4s=0x%s\n",
2435 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2436 ? ia64_register_names[regnum] : "r??"),
2437 paddr_nz (*val));
2438
2439 return 0;
2440}
2441
968d1cb4
JJ		 2442/* Libunwind callback accessor function for accessing memory. */
2443static int
2444ia64_access_mem (unw_addr_space_t as,
2445 unw_word_t addr, unw_word_t *val,
2446 int write, void *arg)
2447{
c5a27d9c
JJ		 2448 if (addr - KERNEL_START < ktab_size)
2449 {
2450 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2451 + (addr - KERNEL_START));
2452
2453 if (write)
2454 *laddr = *val;
2455 else
2456 *val = *laddr;
2457 return 0;
2458 }
2459
968d1cb4
JJ		 2460 /* XXX do we need to normalize byte-order here? */
2461 if (write)
2462 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2463 else
2464 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2465}
2466
2467/* Call low-level function to access the kernel unwind table. */
13547ab6
DJ		 2468static LONGEST
2469getunwind_table (gdb_byte **buf_p)
968d1cb4
JJ		 2470{
2471 LONGEST x;
c5a27d9c 2472
10d6c8cd
DJ		 2473 /* FIXME drow/2005-09-10: This code used to call
2474 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2475 for the currently running ia64-linux kernel. That data should
2476 come from the core file and be accessed via the auxv vector; if
2477 we want to preserve fall back to the running kernel's table, then
2478 we should find a way to override the corefile layer's
2479 xfer_partial method. */
968d1cb4 2480
13547ab6
DJ		 2481 x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2482 NULL, buf_p);
2483
2484 return x;
968d1cb4 2485}
10d6c8cd 2486
968d1cb4
JJ		 2487/* Get the kernel unwind table. */
2488static int
2489get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2490{
c5a27d9c 2491 static struct ia64_table_entry *etab;
968d1cb4 2492
c5a27d9c 2493 if (!ktab)
968d1cb4 2494 {
13547ab6 2495 gdb_byte *ktab_buf;
eeec829c 2496 LONGEST size;
13547ab6 2497
eeec829c
DJ		 2498 size = getunwind_table (&ktab_buf);
2499 if (size <= 0)
13547ab6 2500 return -UNW_ENOINFO;
eeec829c
DJ		 2501
2502 ktab = (struct ia64_table_entry *) ktab_buf;
2503 ktab_size = size;
13547ab6 2504
968d1cb4 2505 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2506 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2507 }
2508
2509 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2510 return -UNW_ENOINFO;
2511
2512 di->format = UNW_INFO_FORMAT_TABLE;
2513 di->gp = 0;
2514 di->start_ip = ktab[0].start_offset;
2515 di->end_ip = etab[-1].end_offset;
2516 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2517 di->u.ti.segbase = 0;
2518 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2519 di->u.ti.table_data = (unw_word_t *) ktab;
2520
2521 if (gdbarch_debug >= 1)
2522 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2523 "segbase=0x%s, length=%s, gp=0x%s\n",
2524 (char *) di->u.ti.name_ptr,
2525 paddr_nz (di->u.ti.segbase),
2526 paddr_u (di->u.ti.table_len),
2527 paddr_nz (di->gp));
968d1cb4
JJ		 2528 return 0;
2529}
2530
2531/* Find the unwind table entry for a specified address. */
2532static int
2533ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2534 unw_dyn_info_t *dip, void **buf)
2535{
2536 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2537 Elf_Internal_Ehdr *ehdr;
2538 unw_word_t segbase = 0;
2539 CORE_ADDR load_base;
2540 bfd *bfd;
2541 int i;
2542
2543 bfd = objfile->obfd;
2544
2545 ehdr = elf_tdata (bfd)->elf_header;
2546 phdr = elf_tdata (bfd)->phdr;
2547
2548 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2549
2550 for (i = 0; i < ehdr->e_phnum; ++i)
2551 {
2552 switch (phdr[i].p_type)
2553 {
2554 case PT_LOAD:
2555 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2556 < phdr[i].p_memsz)
2557 p_text = phdr + i;
2558 break;
2559
2560 case PT_IA_64_UNWIND:
2561 p_unwind = phdr + i;
2562 break;
2563
2564 default:
2565 break;
2566 }
2567 }
2568
c5a27d9c 2569 if (!p_text || !p_unwind)
968d1cb4
JJ		 2570 return -UNW_ENOINFO;
2571
c5a27d9c
JJ		 2572 /* Verify that the segment that contains the IP also contains
2573 the static unwind table. If not, we may be in the Linux kernel's
2574 DSO gate page in which case the unwind table is another segment.
2575 Otherwise, we are dealing with runtime-generated code, for which we
2576 have no info here. */
968d1cb4
JJ		 2577 segbase = p_text->p_vaddr + load_base;
2578
c5a27d9c
JJ		 2579 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2580 {
2581 int ok = 0;
2582 for (i = 0; i < ehdr->e_phnum; ++i)
2583 {
2584 if (phdr[i].p_type == PT_LOAD
2585 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2586 {
2587 ok = 1;
2588 /* Get the segbase from the section containing the
2589 libunwind table. */
2590 segbase = phdr[i].p_vaddr + load_base;
2591 }
2592 }
2593 if (!ok)
2594 return -UNW_ENOINFO;
2595 }
2596
2597 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2598 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2599 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2600 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2601 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2602 dip->u.rti.segbase = segbase;
2603 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2604 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2605
2606 return 0;
2607}
2608
2609/* Libunwind callback accessor function to acquire procedure unwind-info. */
2610static int
2611ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2612 int need_unwind_info, void *arg)
2613{
2614 struct obj_section *sec = find_pc_section (ip);
2615 unw_dyn_info_t di;
2616 int ret;
2617 void *buf = NULL;
2618
2619 if (!sec)
2620 {
2621 /* XXX This only works if the host and the target architecture are
2622 both ia64 and if the have (more or less) the same kernel
2623 version. */
2624 if (get_kernel_table (ip, &di) < 0)
2625 return -UNW_ENOINFO;
503ff15d
KB		 2626
2627 if (gdbarch_debug >= 1)
78ced177
JJ		 2628 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2629 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2630 "length=%s,data=0x%s)\n",
2631 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2632 paddr_nz (di.u.ti.segbase),
2633 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2634 paddr_nz (di.gp),
2635 paddr_u (di.u.ti.table_len),
2636 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2637 }
2638 else
2639 {
2640 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2641 if (ret < 0)
2642 return ret;
968d1cb4 2643
503ff15d 2644 if (gdbarch_debug >= 1)
78ced177
JJ		 2645 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2646 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2647 "length=%s,data=0x%s)\n",
2648 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2649 paddr_nz (di.u.rti.segbase),
2650 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2651 paddr_nz (di.gp),
2652 paddr_u (di.u.rti.table_len),
2653 paddr_nz (di.u.rti.table_data));
503ff15d 2654 }
968d1cb4 2655
503ff15d
KB		 2656 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2657 arg);
968d1cb4
JJ		 2658
2659 /* We no longer need the dyn info storage so free it. */
2660 xfree (buf);
2661
2662 return ret;
2663}
2664
2665/* Libunwind callback accessor function for cleanup. */
2666static void
2667ia64_put_unwind_info (unw_addr_space_t as,
2668 unw_proc_info_t *pip, void *arg)
2669{
2670 /* Nothing required for now. */
2671}
2672
2673/* Libunwind callback accessor function to get head of the dynamic
2674 unwind-info registration list. */
2675static int
2676ia64_get_dyn_info_list (unw_addr_space_t as,
2677 unw_word_t *dilap, void *arg)
2678{
2679 struct obj_section *text_sec;
2680 struct objfile *objfile;
2681 unw_word_t ip, addr;
2682 unw_dyn_info_t di;
2683 int ret;
2684
2685 if (!libunwind_is_initialized ())
2686 return -UNW_ENOINFO;
2687
2688 for (objfile = object_files; objfile; objfile = objfile->next)
2689 {
2690 void *buf = NULL;
2691
2692 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2693 ip = text_sec->addr;
2694 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2695 if (ret >= 0)
2696 {
503ff15d 2697 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2698 /* We no longer need the dyn info storage so free it. */
2699 xfree (buf);
2700
2701 if (addr)
2702 {
2703 if (gdbarch_debug >= 1)
2704 fprintf_unfiltered (gdb_stdlog,
2705 "dynamic unwind table in objfile %s "
78ced177 2706 "at 0x%s (gp=0x%s)\n",
968d1cb4 2707 bfd_get_filename (objfile->obfd),
78ced177 2708 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2709 *dilap = addr;
2710 return 0;
2711 }
2712 }
2713 }
2714 return -UNW_ENOINFO;
2715}
2716
2717
2718/* Frame interface functions for libunwind. */
2719
2720static void
2721ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2722 struct frame_id *this_id)
968d1cb4
JJ		 2723{
2724 char buf[8];
2725 CORE_ADDR bsp;
2726 struct frame_id id;
c5a27d9c
JJ		 2727 CORE_ADDR prev_ip, addr;
2728 int realnum, optimized;
2729 enum lval_type lval;
2730
968d1cb4
JJ		 2731
2732 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2733 if (frame_id_eq (id, null_frame_id))
2734 {
2735 (*this_id) = null_frame_id;
2736 return;
2737 }
968d1cb4 2738
c5a27d9c
JJ		 2739 /* We must add the bsp as the special address for frame comparison
2740 purposes. */
968d1cb4
JJ		 2741 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2742 bsp = extract_unsigned_integer (buf, 8);
2743
c5a27d9c
JJ		 2744 /* If the previous frame pc value is 0, then we are at the end of the stack
2745 and don't want to unwind past this frame. We return a null frame_id to
2746 indicate this. */
2747 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2748 &optimized, &lval, &addr, &realnum, buf);
2749 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2750
2751 if (prev_ip != 0)
2752 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2753 else
2754 (*this_id) = null_frame_id;
968d1cb4
JJ		 2755
2756 if (gdbarch_debug >= 1)
2757 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2758 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2759 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2760 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2761}
2762
2763static void
2764ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2765 void **this_cache,
2766 int regnum, int *optimizedp,
2767 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2768 int *realnump, gdb_byte *valuep)
968d1cb4
JJ		 2769{
2770 int reg = regnum;
2771
2772 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2773 reg = IA64_PR_REGNUM;
2774 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2775 reg = IA64_UNAT_REGNUM;
2776
2777 /* Let libunwind do most of the work. */
2778 libunwind_frame_prev_register (next_frame, this_cache, reg,
2779 optimizedp, lvalp, addrp, realnump, valuep);
2780
6672f2ae
AS		 2781 /* No more to do if the value is not supposed to be supplied. */
2782 if (!valuep)
2783 return;
2784
968d1cb4
JJ		 2785 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2786 {
2787 ULONGEST prN_val;
2788
2789 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2790 {
2791 int rrb_pr = 0;
2792 ULONGEST cfm;
2793 unsigned char buf[MAX_REGISTER_SIZE];
2794
2795 /* Fetch predicate register rename base from current frame
2796 marker for this frame. */
2797 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2798 cfm = extract_unsigned_integer (buf, 8);
2799 rrb_pr = (cfm >> 32) & 0x3f;
2800
2801 /* Adjust the register number to account for register rotation. */
2802 regnum = VP16_REGNUM
2803 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2804 }
2805 prN_val = extract_bit_field ((unsigned char *) valuep,
2806 regnum - VP0_REGNUM, 1);
2807 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2808 }
2809 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2810 {
2811 ULONGEST unatN_val;
2812
2813 unatN_val = extract_bit_field ((unsigned char *) valuep,
2814 regnum - IA64_NAT0_REGNUM, 1);
2815 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2816 unatN_val);
2817 }
2818 else if (regnum == IA64_BSP_REGNUM)
2819 {
2820 char cfm_valuep[MAX_REGISTER_SIZE];
2821 int cfm_optim;
2822 int cfm_realnum;
2823 enum lval_type cfm_lval;
2824 CORE_ADDR cfm_addr;
2825 CORE_ADDR bsp, prev_cfm, prev_bsp;
2826
2827 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2828 This corresponds to what the hardware bsp register will be if we pop the frame
2829 back which is why we might have been called. We know that libunwind will pass us back
2830 the beginning of the current frame so we should just add sof to it. */
2831 prev_bsp = extract_unsigned_integer (valuep, 8);
2832 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2833 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2834 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2835 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2836
2837 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2838 prev_bsp);
2839 }
2840
2841 if (gdbarch_debug >= 1)
2842 fprintf_unfiltered (gdb_stdlog,
78ced177 2843 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2844 (regnum < IA64_GR32_REGNUM
2845 || (regnum > IA64_GR127_REGNUM
2846 && regnum < LAST_PSEUDO_REGNUM))
2847 ? ia64_register_names[regnum]
2848 : (regnum < LAST_PSEUDO_REGNUM
2849 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2850 : "OUT_OF_RANGE"),
78ced177 2851 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2852}
2853
2854static const struct frame_unwind ia64_libunwind_frame_unwind =
2855{
2856 NORMAL_FRAME,
2857 ia64_libunwind_frame_this_id,
2858 ia64_libunwind_frame_prev_register
2859};
2860
2861static const struct frame_unwind *
2862ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2863{
2864 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2865 return &ia64_libunwind_frame_unwind;
2866
2867 return NULL;
2868}
2869
c5a27d9c
JJ		 2870static void
2871ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2872 struct frame_id *this_id)
2873{
2874 char buf[8];
2875 CORE_ADDR bsp;
2876 struct frame_id id;
2877 CORE_ADDR prev_ip;
2878
2879 libunwind_frame_this_id (next_frame, this_cache, &id);
2880 if (frame_id_eq (id, null_frame_id))
2881 {
2882 (*this_id) = null_frame_id;
2883 return;
2884 }
2885
2886 /* We must add the bsp as the special address for frame comparison
2887 purposes. */
2888 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2889 bsp = extract_unsigned_integer (buf, 8);
2890
2891 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2892 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2893
2894 if (gdbarch_debug >= 1)
2895 fprintf_unfiltered (gdb_stdlog,
2896 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2897 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2898 paddr_nz (bsp), next_frame);
2899}
2900
2901static void
2902ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2903 void **this_cache,
2904 int regnum, int *optimizedp,
2905 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2906 int *realnump, gdb_byte *valuep)
c5a27d9c
JJ		 2907
2908{
f1b4b38e 2909 gdb_byte buf[8];
c5a27d9c
JJ		 2910 CORE_ADDR prev_ip, addr;
2911 int realnum, optimized;
2912 enum lval_type lval;
2913
2914
2915 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2916 method of getting previous registers. */
2917 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2918 &optimized, &lval, &addr, &realnum, buf);
2919 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2920
2921 if (prev_ip == 0)
2922 {
2923 void *tmp_cache = NULL;
2924 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2925 addrp, realnump, valuep);
2926 }
2927 else
2928 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2929 addrp, realnump, valuep);
2930}
2931
2932static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2933{
2934 SIGTRAMP_FRAME,
2935 ia64_libunwind_sigtramp_frame_this_id,
2936 ia64_libunwind_sigtramp_frame_prev_register
2937};
2938
2939static const struct frame_unwind *
2940ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2941{
2942 if (libunwind_is_initialized ())
2943 {
2944 if (libunwind_sigtramp_frame_sniffer (next_frame))
2945 return &ia64_libunwind_sigtramp_frame_unwind;
2946 return NULL;
2947 }
2948 else
2949 return ia64_sigtramp_frame_sniffer (next_frame);
2950}
2951
968d1cb4
JJ		 2952/* Set of libunwind callback acccessor functions. */
2953static unw_accessors_t ia64_unw_accessors =
2954{
2955 ia64_find_proc_info_x,
2956 ia64_put_unwind_info,
2957 ia64_get_dyn_info_list,
2958 ia64_access_mem,
2959 ia64_access_reg,
2960 ia64_access_fpreg,
2961 /* resume */
2962 /* get_proc_name */
2963};
2964
c5a27d9c
JJ		 2965/* Set of special libunwind callback acccessor functions specific for accessing
2966 the rse registers. At the top of the stack, we want libunwind to figure out
2967 how to read r32 - r127. Though usually they are found sequentially in memory
2968 starting from $bof, this is not always true. */
2969static unw_accessors_t ia64_unw_rse_accessors =
2970{
2971 ia64_find_proc_info_x,
2972 ia64_put_unwind_info,
2973 ia64_get_dyn_info_list,
2974 ia64_access_mem,
2975 ia64_access_rse_reg,
2976 ia64_access_fpreg,
2977 /* resume */
2978 /* get_proc_name */
2979};
2980
968d1cb4
JJ		 2981/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2982static struct libunwind_descr ia64_libunwind_descr =
2983{
2984 ia64_gdb2uw_regnum,
2985 ia64_uw2gdb_regnum,
2986 ia64_is_fpreg,
2987 &ia64_unw_accessors,
c5a27d9c 2988 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2989};
2990
2991#endif /* HAVE_LIBUNWIND_IA64_H */
2992
74055713
AC		 2993/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2994 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2995 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2996int
2997ia64_use_struct_convention (int gcc_p, struct type *type)
2998{
64a5b29c
KB		 2999 struct type *float_elt_type;
3000
3001 /* HFAs are structures (or arrays) consisting entirely of floating
3002 point values of the same length. Up to 8 of these are returned
3003 in registers. Don't use the struct convention when this is the
004d836a 3004 case. */
64a5b29c
KB		 3005 float_elt_type = is_float_or_hfa_type (type);
3006 if (float_elt_type != NULL
3007 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
3008 return 0;
3009
3010 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 3011 Don't use the struct convention for those either. */
16461d7d
KB		 3012 return TYPE_LENGTH (type) > 32;
3013}
3014
3015void
2d522557
AC		 3016ia64_extract_return_value (struct type *type, struct regcache *regcache,
3017 gdb_byte *valbuf)
16461d7d 3018{
64a5b29c
KB		 3019 struct type *float_elt_type;
3020
3021 float_elt_type = is_float_or_hfa_type (type);
3022 if (float_elt_type != NULL)
3023 {
004d836a 3024 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 3025 int offset = 0;
3026 int regnum = IA64_FR8_REGNUM;
3027 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3028
3029 while (n-- > 0)
3030 {
004d836a
JJ		 3031 regcache_cooked_read (regcache, regnum, from);
3032 convert_typed_floating (from, builtin_type_ia64_ext,
3033 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 3034 offset += TYPE_LENGTH (float_elt_type);
3035 regnum++;
3036 }
3037 }
16461d7d 3038 else
004d836a
JJ		 3039 {
3040 ULONGEST val;
3041 int offset = 0;
3042 int regnum = IA64_GR8_REGNUM;
7b9ee6a8
DJ		 3043 int reglen = TYPE_LENGTH (register_type (get_regcache_arch (regcache),
3044 IA64_GR8_REGNUM));
004d836a
JJ		 3045 int n = TYPE_LENGTH (type) / reglen;
3046 int m = TYPE_LENGTH (type) % reglen;
16461d7d 3047
004d836a
JJ		 3048 while (n-- > 0)
3049 {
3050 ULONGEST val;
3051 regcache_cooked_read_unsigned (regcache, regnum, &val);
3052 memcpy ((char *)valbuf + offset, &val, reglen);
3053 offset += reglen;
3054 regnum++;
3055 }
16461d7d 3056
004d836a
JJ		 3057 if (m)
3058 {
3059 regcache_cooked_read_unsigned (regcache, regnum, &val);
3060 memcpy ((char *)valbuf + offset, &val, m);
3061 }
3062 }
16461d7d
KB		 3063}
3064
3065CORE_ADDR
004d836a 3066ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 3067{
8a3fe4f8 3068 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 3069 return 0;
16461d7d
KB		 3070}
3071
16461d7d 3072
64a5b29c
KB		 3073static int
3074is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3075{
3076 switch (TYPE_CODE (t))
3077 {
3078 case TYPE_CODE_FLT:
3079 if (*etp)
3080 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3081 else
3082 {
3083 *etp = t;
3084 return 1;
3085 }
3086 break;
3087 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3088 return
3089 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3090 etp);
64a5b29c
KB		 3091 break;
3092 case TYPE_CODE_STRUCT:
3093 {
3094 int i;
3095
3096 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3097 if (!is_float_or_hfa_type_recurse
3098 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3099 return 0;
3100 return 1;
3101 }
3102 break;
3103 default:
3104 return 0;
3105 break;
3106 }
3107}
3108
3109/* Determine if the given type is one of the floating point types or
3110 and HFA (which is a struct, array, or combination thereof whose
004d836a 3111 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3112
3113static struct type *
3114is_float_or_hfa_type (struct type *t)
3115{
3116 struct type *et = 0;
3117
3118 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3119}
3120
3121
98f96ba1
KB		 3122/* Return 1 if the alignment of T is such that the next even slot
3123 should be used. Return 0, if the next available slot should
3124 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3125 and Runtime manual). */
98f96ba1
KB		 3126
3127static int
3128slot_alignment_is_next_even (struct type *t)
3129{
3130 switch (TYPE_CODE (t))
3131 {
3132 case TYPE_CODE_INT:
3133 case TYPE_CODE_FLT:
3134 if (TYPE_LENGTH (t) > 8)
3135 return 1;
3136 else
3137 return 0;
3138 case TYPE_CODE_ARRAY:
3139 return
3140 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3141 case TYPE_CODE_STRUCT:
3142 {
3143 int i;
3144
3145 for (i = 0; i < TYPE_NFIELDS (t); i++)
3146 if (slot_alignment_is_next_even
3147 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3148 return 1;
3149 return 0;
3150 }
3151 default:
3152 return 0;
3153 }
3154}
3155
64a5b29c
KB		 3156/* Attempt to find (and return) the global pointer for the given
3157 function.
3158
3159 This is a rather nasty bit of code searchs for the .dynamic section
3160 in the objfile corresponding to the pc of the function we're trying
3161 to call. Once it finds the addresses at which the .dynamic section
3162 lives in the child process, it scans the Elf64_Dyn entries for a
3163 DT_PLTGOT tag. If it finds one of these, the corresponding
3164 d_un.d_ptr value is the global pointer. */
3165
3166static CORE_ADDR
b33e8514 3167ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3168{
76d689a6 3169 struct obj_section *faddr_sect;
64a5b29c 3170
76d689a6
KB		 3171 faddr_sect = find_pc_section (faddr);
3172 if (faddr_sect != NULL)
64a5b29c
KB		 3173 {
3174 struct obj_section *osect;
3175
76d689a6 3176 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3177 {
3178 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3179 break;
3180 }
3181
76d689a6 3182 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3183 {
3184 CORE_ADDR addr;
3185
3186 addr = osect->addr;
3187 while (addr < osect->endaddr)
3188 {
3189 int status;
3190 LONGEST tag;
3191 char buf[8];
3192
3193 status = target_read_memory (addr, buf, sizeof (buf));
3194 if (status != 0)
3195 break;
3196 tag = extract_signed_integer (buf, sizeof (buf));
3197
3198 if (tag == DT_PLTGOT)
3199 {
3200 CORE_ADDR global_pointer;
3201
3202 status = target_read_memory (addr + 8, buf, sizeof (buf));
3203 if (status != 0)
3204 break;
7c0b4a20 3205 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3206
3207 /* The payoff... */
3208 return global_pointer;
3209 }
3210
3211 if (tag == DT_NULL)
3212 break;
3213
3214 addr += 16;
3215 }
3216 }
3217 }
3218 return 0;
3219}
3220
3221/* Given a function's address, attempt to find (and return) the
3222 corresponding (canonical) function descriptor. Return 0 if
004d836a 3223 not found. */
64a5b29c
KB		 3224static CORE_ADDR
3225find_extant_func_descr (CORE_ADDR faddr)
3226{
76d689a6 3227 struct obj_section *faddr_sect;
64a5b29c 3228
004d836a 3229 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3230 faddr_sect = find_pc_section (faddr);
3231 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3232 return faddr;
3233
76d689a6 3234 if (faddr_sect != NULL)
64a5b29c 3235 {
76d689a6
KB		 3236 struct obj_section *osect;
3237 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3238 {
3239 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3240 break;
3241 }
3242
76d689a6 3243 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3244 {
3245 CORE_ADDR addr;
3246
3247 addr = osect->addr;
3248 while (addr < osect->endaddr)
3249 {
3250 int status;
3251 LONGEST faddr2;
3252 char buf[8];
3253
3254 status = target_read_memory (addr, buf, sizeof (buf));
3255 if (status != 0)
3256 break;
3257 faddr2 = extract_signed_integer (buf, sizeof (buf));
3258
3259 if (faddr == faddr2)
3260 return addr;
3261
3262 addr += 16;
3263 }
3264 }
3265 }
3266 return 0;
3267}
3268
3269/* Attempt to find a function descriptor corresponding to the
3270 given address. If none is found, construct one on the
004d836a 3271 stack using the address at fdaptr. */
64a5b29c
KB		 3272
3273static CORE_ADDR
3274find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
3275{
3276 CORE_ADDR fdesc;
3277
3278 fdesc = find_extant_func_descr (faddr);
3279
3280 if (fdesc == 0)
3281 {
3282 CORE_ADDR global_pointer;
3283 char buf[16];
3284
3285 fdesc = *fdaptr;
3286 *fdaptr += 16;
3287
b33e8514 3288 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3289
3290 if (global_pointer == 0)
3291 global_pointer = read_register (IA64_GR1_REGNUM);
3292
fbd9dcd3
AC		 3293 store_unsigned_integer (buf, 8, faddr);
3294 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3295
3296 write_memory (fdesc, buf, 16);
3297 }
3298
3299 return fdesc;
3300}
16461d7d 3301
af8b88dd
JJ		 3302/* Use the following routine when printing out function pointers
3303 so the user can see the function address rather than just the
3304 function descriptor. */
3305static CORE_ADDR
e2d0e7eb
AC		 3306ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3307 struct target_ops *targ)
af8b88dd
JJ		 3308{
3309 struct obj_section *s;
3310
3311 s = find_pc_section (addr);
3312
3313 /* check if ADDR points to a function descriptor. */
3314 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3315 return read_memory_unsigned_integer (addr, 8);
3316
0d5de010
DJ		 3317 /* There are also descriptors embedded in vtables. */
3318 if (s)
3319 {
3320 struct minimal_symbol *minsym;
3321
3322 minsym = lookup_minimal_symbol_by_pc (addr);
3323
3324 if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3325 return read_memory_unsigned_integer (addr, 8);
3326 }
3327
af8b88dd
JJ		 3328 return addr;
3329}
3330
a78f21af 3331static CORE_ADDR
004d836a
JJ		 3332ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3333{
3334 return sp & ~0xfLL;
3335}
3336
3337static CORE_ADDR
7d9b040b 3338ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3339 struct regcache *regcache, CORE_ADDR bp_addr,
3340 int nargs, struct value **args, CORE_ADDR sp,
3341 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3342{
3343 int argno;
ea7c478f 3344 struct value *arg;
16461d7d
KB		 3345 struct type *type;
3346 int len, argoffset;
64a5b29c 3347 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3348 int floatreg;
004d836a 3349 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3350 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3351
3352 nslots = 0;
64a5b29c 3353 nfuncargs = 0;
004d836a 3354 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3355 for (argno = 0; argno < nargs; argno++)
3356 {
3357 arg = args[argno];
4991999e 3358 type = check_typedef (value_type (arg));
16461d7d
KB		 3359 len = TYPE_LENGTH (type);
3360
98f96ba1 3361 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3362 nslots++;
3363
64a5b29c
KB		 3364 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3365 nfuncargs++;
3366
16461d7d
KB		 3367 nslots += (len + 7) / 8;
3368 }
3369
004d836a 3370 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3371 rseslots = (nslots > 8) ? 8 : nslots;
3372 memslots = nslots - rseslots;
3373
004d836a
JJ		 3374 /* Allocate a new RSE frame. */
3375 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3376
004d836a 3377 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3378 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3379 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3380
004d836a 3381 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3382 pfs &= 0xc000000000000000LL;
3383 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3384 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3385
3386 cfm &= 0xc000000000000000LL;
3387 cfm |= rseslots;
004d836a 3388 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3389
64a5b29c
KB		 3390 /* We will attempt to find function descriptors in the .opd segment,
3391 but if we can't we'll construct them ourselves. That being the
004d836a 3392 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3393 funcdescaddr = sp - nfuncargs * 16;
3394 funcdescaddr &= ~0xfLL;
3395
3396 /* Adjust the stack pointer to it's new value. The calling conventions
3397 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3398 necessary for the memory slots and our function descriptors. */
64a5b29c 3399 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3400 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3401
64a5b29c
KB		 3402 /* Place the arguments where they belong. The arguments will be
3403 either placed in the RSE backing store or on the memory stack.
3404 In addition, floating point arguments or HFAs are placed in
004d836a 3405 floating point registers. */
16461d7d
KB		 3406 slotnum = 0;
3407 floatreg = IA64_FR8_REGNUM;
3408 for (argno = 0; argno < nargs; argno++)
3409 {
64a5b29c
KB		 3410 struct type *float_elt_type;
3411
16461d7d 3412 arg = args[argno];
4991999e 3413 type = check_typedef (value_type (arg));
16461d7d 3414 len = TYPE_LENGTH (type);
64a5b29c 3415
004d836a 3416 /* Special handling for function parameters. */
64a5b29c
KB		 3417 if (len == 8
3418 && TYPE_CODE (type) == TYPE_CODE_PTR
3419 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3420 {
3421 char val_buf[8];
3422
fbd9dcd3 3423 store_unsigned_integer (val_buf, 8,
0fd88904 3424 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3425 &funcdescaddr));
64a5b29c
KB		 3426 if (slotnum < rseslots)
3427 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3428 else
3429 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3430 slotnum++;
3431 continue;
3432 }
3433
004d836a 3434 /* Normal slots. */
98f96ba1
KB		 3435
3436 /* Skip odd slot if necessary... */
3437 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3438 slotnum++;
98f96ba1 3439
16461d7d
KB		 3440 argoffset = 0;
3441 while (len > 0)
3442 {
3443 char val_buf[8];
3444
3445 memset (val_buf, 0, 8);
0fd88904 3446 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3447
3448 if (slotnum < rseslots)
3449 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3450 else
3451 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3452
3453 argoffset += 8;
3454 len -= 8;
3455 slotnum++;
3456 }
64a5b29c 3457
004d836a 3458 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3459 float_elt_type = is_float_or_hfa_type (type);
3460 if (float_elt_type != NULL)
3461 {
3462 argoffset = 0;
3463 len = TYPE_LENGTH (type);
3464 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3465 {
004d836a 3466 char to[MAX_REGISTER_SIZE];
0fd88904 3467 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3468 to, builtin_type_ia64_ext);
3469 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3470 floatreg++;
3471 argoffset += TYPE_LENGTH (float_elt_type);
3472 len -= TYPE_LENGTH (float_elt_type);
3473 }
16461d7d
KB		 3474 }
3475 }
3476
004d836a 3477 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3478 if (struct_return)
3479 {
004d836a 3480 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3481 }
3482
b33e8514 3483 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3484
004d836a
JJ		 3485 if (global_pointer != 0)
3486 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3487
004d836a 3488 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3489
004d836a 3490 write_register (sp_regnum, sp);
16461d7d
KB		 3491
3492 return sp;
3493}
3494
004d836a
JJ		 3495static struct frame_id
3496ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3497{
004d836a 3498 char buf[8];
4afcc598 3499 CORE_ADDR sp, bsp;
004d836a
JJ		 3500
3501 frame_unwind_register (next_frame, sp_regnum, buf);
3502 sp = extract_unsigned_integer (buf, 8);
3503
4afcc598
JJ		 3504 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3505 bsp = extract_unsigned_integer (buf, 8);
3506
3507 if (gdbarch_debug >= 1)
3508 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3509 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3510 paddr_nz (frame_pc_unwind (next_frame)),
3511 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3512
3513 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3514}
3515
004d836a
JJ		 3516static CORE_ADDR
3517ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3518{
004d836a
JJ		 3519 char buf[8];
3520 CORE_ADDR ip, psr, pc;
3521
3522 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3523 ip = extract_unsigned_integer (buf, 8);
3524 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3525 psr = extract_unsigned_integer (buf, 8);
3526
3527 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3528 return pc;
16461d7d
KB		 3529}
3530
3531static void
88d82102
JJ		 3532ia64_store_return_value (struct type *type, struct regcache *regcache,
3533 const gdb_byte *valbuf)
16461d7d 3534{
004d836a 3535 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3536 {
004d836a
JJ		 3537 char to[MAX_REGISTER_SIZE];
3538 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3539 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3540 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3541 }
3542 else
004d836a 3543 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3544}
3545
3546static void
1750fa04
AC		 3547ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3548 struct regcache *regcache,
3549 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3550 CORE_ADDR *targ_addr, int *targ_len)
3551{
3552 *targ_addr = memaddr;
3553 *targ_len = nr_bytes;
3554}
3555
6926787d
AS		 3556static int
3557ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3558{
3559 info->bytes_per_line = SLOT_MULTIPLIER;
3560 return print_insn_ia64 (memaddr, info);
3561}
3562
16461d7d
KB		 3563static struct gdbarch *
3564ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3565{
3566 struct gdbarch *gdbarch;
244bc108 3567 struct gdbarch_tdep *tdep;
244bc108 3568
85bf2b91
JJ		 3569 /* If there is already a candidate, use it. */
3570 arches = gdbarch_list_lookup_by_info (arches, &info);
3571 if (arches != NULL)
3572 return arches->gdbarch;
16461d7d 3573
244bc108
KB		 3574 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3575 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3576
b33e8514 3577 tdep->sigcontext_register_address = 0;
698cb3f0 3578
004d836a
JJ		 3579 /* Define the ia64 floating-point format to gdb. */
3580 builtin_type_ia64_ext =
3581 init_type (TYPE_CODE_FLT, 128 / 8,
3582 0, "builtin_type_ia64_ext", NULL);
8da61cc4 3583 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = floatformats_ia64_ext;
004d836a 3584
5439edaa
AC		 3585 /* According to the ia64 specs, instructions that store long double
3586 floats in memory use a long-double format different than that
3587 used in the floating registers. The memory format matches the
3588 x86 extended float format which is 80 bits. An OS may choose to
3589 use this format (e.g. GNU/Linux) or choose to use a different
3590 format for storing long doubles (e.g. HPUX). In the latter case,
3591 the setting of the format may be moved/overridden in an
3592 OS-specific tdep file. */
8da61cc4 3593 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
32edc941 3594
16461d7d
KB		 3595 set_gdbarch_short_bit (gdbarch, 16);
3596 set_gdbarch_int_bit (gdbarch, 32);
3597 set_gdbarch_long_bit (gdbarch, 64);
3598 set_gdbarch_long_long_bit (gdbarch, 64);
3599 set_gdbarch_float_bit (gdbarch, 32);
3600 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3601 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3602 set_gdbarch_ptr_bit (gdbarch, 64);
3603
004d836a
JJ		 3604 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3605 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3606 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3607 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3608
3609 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3610 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3611 gets a number of extra failures. */
b1e29e33 3612 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3613 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3614
004d836a
JJ		 3615 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3616 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3617 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3618 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3619 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3620 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3621 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3622
004d836a 3623 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3624
b5622e8d 3625 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3626 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3627
004d836a 3628 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3629 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3630
3631 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3632 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3633 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3634 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3635 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3636
3637 /* Settings for calling functions in the inferior. */
8dd5115e 3638 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3639 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3640 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3641
004d836a 3642 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3643#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3644 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3645 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3646 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3647#else
3648 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3649#endif
004d836a
JJ		 3650 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3651 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3652
3653 /* Settings that should be unnecessary. */
3654 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3655
16461d7d
KB		 3656 set_gdbarch_remote_translate_xfer_address (
3657 gdbarch, ia64_remote_translate_xfer_address);
3658
6926787d 3659 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3660 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3661
0d5de010
DJ		 3662 /* The virtual table contains 16-byte descriptors, not pointers to
3663 descriptors. */
3664 set_gdbarch_vtable_function_descriptors (gdbarch, 1);
3665
b33e8514
AS		 3666 /* Hook in ABI-specific overrides, if they have been registered. */
3667 gdbarch_init_osabi (info, gdbarch);
3668
16461d7d
KB		 3669 return gdbarch;
3670}
3671
a78f21af
AC		 3672extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3673
16461d7d
KB		 3674void
3675_initialize_ia64_tdep (void)
3676{
b33e8514 3677 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3678}
GDB Binutils - Deliverables
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