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[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
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16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
6aba47ca 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
13547ab6 4 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
16461d7d
KB		 22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
e6bb342a 28#include "gdbtypes.h"
4e052eda 29#include "regcache.h"
004d836a
JJ		 30#include "reggroups.h"
31#include "frame.h"
32#include "frame-base.h"
33#include "frame-unwind.h"
d16aafd8 34#include "doublest.h"
fd0407d6 35#include "value.h"
bd1ce8ba 36#include "gdb_assert.h"
16461d7d
KB		 37#include "objfiles.h"
38#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 39#include "elf-bfd.h"
a89aa300 40#include "dis-asm.h"
7d9b040b 41#include "infcall.h"
b33e8514 42#include "osabi.h"
9fc9f5e2 43#include "ia64-tdep.h"
0d5de010 44#include "cp-abi.h"
16461d7d 45
968d1cb4 46#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 47#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 48#include "libunwind-frame.h"
49#include "libunwind-ia64.h"
c5a27d9c
JJ		 50
51/* Note: KERNEL_START is supposed to be an address which is not going
52 to ever contain any valid unwind info. For ia64 linux, the choice
53 of 0xc000000000000000 is fairly safe since that's uncached space.
54
55 We use KERNEL_START as follows: after obtaining the kernel's
56 unwind table via getunwind(), we project its unwind data into
57 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
58 when ia64_access_mem() sees a memory access to this
59 address-range, we redirect it to ktab instead.
60
61 None of this hackery is needed with a modern kernel/libcs
62 which uses the kernel virtual DSO to provide access to the
63 kernel's unwind info. In that case, ktab_size remains 0 and
64 hence the value of KERNEL_START doesn't matter. */
65
66#define KERNEL_START 0xc000000000000000ULL
67
68static size_t ktab_size = 0;
69struct ia64_table_entry
70 {
71 uint64_t start_offset;
72 uint64_t end_offset;
73 uint64_t info_offset;
74 };
75
76static struct ia64_table_entry *ktab = NULL;
77
968d1cb4
JJ		 78#endif
79
698cb3f0
KB		 80/* An enumeration of the different IA-64 instruction types. */
81
16461d7d
KB		 82typedef enum instruction_type
83{
84 A, /* Integer ALU ; I-unit or M-unit */
85 I, /* Non-ALU integer; I-unit */
86 M, /* Memory ; M-unit */
87 F, /* Floating-point ; F-unit */
88 B, /* Branch ; B-unit */
89 L, /* Extended (L+X) ; I-unit */
90 X, /* Extended (L+X) ; I-unit */
91 undefined /* undefined or reserved */
92} instruction_type;
93
94/* We represent IA-64 PC addresses as the value of the instruction
95 pointer or'd with some bit combination in the low nibble which
96 represents the slot number in the bundle addressed by the
97 instruction pointer. The problem is that the Linux kernel
98 multiplies its slot numbers (for exceptions) by one while the
99 disassembler multiplies its slot numbers by 6. In addition, I've
100 heard it said that the simulator uses 1 as the multiplier.
101
102 I've fixed the disassembler so that the bytes_per_line field will
103 be the slot multiplier. If bytes_per_line comes in as zero, it
104 is set to six (which is how it was set up initially). -- objdump
105 displays pretty disassembly dumps with this value. For our purposes,
106 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
107 never want to also display the raw bytes the way objdump does. */
108
109#define SLOT_MULTIPLIER 1
110
111/* Length in bytes of an instruction bundle */
112
113#define BUNDLE_LEN 16
114
16461d7d
KB		 115static gdbarch_init_ftype ia64_gdbarch_init;
116
117static gdbarch_register_name_ftype ia64_register_name;
004d836a 118static gdbarch_register_type_ftype ia64_register_type;
16461d7d 119static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 120static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 121static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 122static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 123
004d836a
JJ		 124static struct type *builtin_type_ia64_ext;
125
126#define NUM_IA64_RAW_REGS 462
16461d7d 127
16461d7d
KB		 128static int sp_regnum = IA64_GR12_REGNUM;
129static int fp_regnum = IA64_VFP_REGNUM;
130static int lr_regnum = IA64_VRAP_REGNUM;
131
004d836a 132/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 133 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 134enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
135 V127_REGNUM = V32_REGNUM + 95,
136 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 137
138/* Array of register names; There should be ia64_num_regs strings in
139 the initializer. */
140
141static char *ia64_register_names[] =
142{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
145 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
16461d7d
KB		 158
159 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
160 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
161 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
162 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
163 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
164 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
165 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
166 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
167 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
168 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
169 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
170 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
171 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
172 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
173 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
174 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
175
004d836a
JJ		 176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "",
16461d7d
KB		 184
185 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
186
187 "vfp", "vrap",
188
189 "pr", "ip", "psr", "cfm",
190
191 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
192 "", "", "", "", "", "", "", "",
193 "rsc", "bsp", "bspstore", "rnat",
194 "", "fcr", "", "",
195 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
196 "ccv", "", "", "", "unat", "", "", "",
197 "fpsr", "", "", "", "itc",
198 "", "", "", "", "", "", "", "", "", "",
199 "", "", "", "", "", "", "", "", "",
200 "pfs", "lc", "ec",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "", "", "", "", "", "", "", "", "", "",
206 "", "", "", "", "", "", "", "", "", "",
207 "",
208 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
209 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
210 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
211 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
212 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
213 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
214 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
215 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
216 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
217 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
218 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
219 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
220 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
221 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
222 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
223 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 224
225 "bof",
226
227 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
228 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
229 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
230 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
231 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
232 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
233 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
234 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
235 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
236 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
237 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
238 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
239
240 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
241 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
242 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
243 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
244 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
245 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
246 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
247 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 248};
249
004d836a
JJ		 250struct ia64_frame_cache
251{
252 CORE_ADDR base; /* frame pointer base for frame */
253 CORE_ADDR pc; /* function start pc for frame */
254 CORE_ADDR saved_sp; /* stack pointer for frame */
255 CORE_ADDR bsp; /* points at r32 for the current frame */
256 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 257 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 258 int frameless;
259 int sof; /* Size of frame (decoded from cfm value) */
260 int sol; /* Size of locals (decoded from cfm value) */
261 int sor; /* Number of rotating registers. (decoded from cfm value) */
262 CORE_ADDR after_prologue;
263 /* Address of first instruction after the last
264 prologue instruction; Note that there may
265 be instructions from the function's body
266 intermingled with the prologue. */
267 int mem_stack_frame_size;
268 /* Size of the memory stack frame (may be zero),
269 or -1 if it has not been determined yet. */
270 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 271 for this frame. 0 if no register is being used
16461d7d 272 as the frame pointer. */
004d836a
JJ		 273
274 /* Saved registers. */
275 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
276
277};
244bc108 278
698cb3f0
KB		 279#define SIGCONTEXT_REGISTER_ADDRESS \
280 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 281
004d836a
JJ		 282int
283ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
284 struct reggroup *group)
16461d7d 285{
004d836a
JJ		 286 int vector_p;
287 int float_p;
288 int raw_p;
289 if (group == all_reggroup)
290 return 1;
291 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
292 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
293 raw_p = regnum < NUM_IA64_RAW_REGS;
294 if (group == float_reggroup)
295 return float_p;
296 if (group == vector_reggroup)
297 return vector_p;
298 if (group == general_reggroup)
299 return (!vector_p && !float_p);
300 if (group == save_reggroup || group == restore_reggroup)
301 return raw_p;
302 return 0;
16461d7d
KB		 303}
304
004d836a
JJ		 305static const char *
306ia64_register_name (int reg)
16461d7d 307{
004d836a 308 return ia64_register_names[reg];
16461d7d
KB		 309}
310
004d836a
JJ		 311struct type *
312ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 313{
004d836a
JJ		 314 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
315 return builtin_type_ia64_ext;
316 else
317 return builtin_type_long;
16461d7d
KB		 318}
319
a78f21af 320static int
004d836a 321ia64_dwarf_reg_to_regnum (int reg)
16461d7d 322{
004d836a
JJ		 323 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
324 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
325 return reg;
16461d7d
KB		 326}
327
4afcc598 328static int
2fda21a6 329floatformat_valid (const struct floatformat *fmt, const void *from)
4afcc598
JJ		 330{
331 return 1;
332}
333
16461d7d
KB		 334const struct floatformat floatformat_ia64_ext =
335{
336 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 337 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 338};
339
8da61cc4
DJ		 340const struct floatformat *floatformats_ia64_ext[2] =
341{
342 &floatformat_ia64_ext,
343 &floatformat_ia64_ext
344};
345
16461d7d
KB		 346
347/* Extract ``len'' bits from an instruction bundle starting at
348 bit ``from''. */
349
244bc108 350static long long
16461d7d
KB		 351extract_bit_field (char *bundle, int from, int len)
352{
353 long long result = 0LL;
354 int to = from + len;
355 int from_byte = from / 8;
356 int to_byte = to / 8;
357 unsigned char *b = (unsigned char *) bundle;
358 unsigned char c;
359 int lshift;
360 int i;
361
362 c = b[from_byte];
363 if (from_byte == to_byte)
364 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
365 result = c >> (from % 8);
366 lshift = 8 - (from % 8);
367
368 for (i = from_byte+1; i < to_byte; i++)
369 {
370 result |= ((long long) b[i]) << lshift;
371 lshift += 8;
372 }
373
374 if (from_byte < to_byte && (to % 8 != 0))
375 {
376 c = b[to_byte];
377 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
378 result |= ((long long) c) << lshift;
379 }
380
381 return result;
382}
383
384/* Replace the specified bits in an instruction bundle */
385
244bc108 386static void
16461d7d
KB		 387replace_bit_field (char *bundle, long long val, int from, int len)
388{
389 int to = from + len;
390 int from_byte = from / 8;
391 int to_byte = to / 8;
392 unsigned char *b = (unsigned char *) bundle;
393 unsigned char c;
394
395 if (from_byte == to_byte)
396 {
397 unsigned char left, right;
398 c = b[from_byte];
399 left = (c >> (to % 8)) << (to % 8);
400 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
401 c = (unsigned char) (val & 0xff);
402 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
403 c |= right | left;
404 b[from_byte] = c;
405 }
406 else
407 {
408 int i;
409 c = b[from_byte];
410 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
411 c = c | (val << (from % 8));
412 b[from_byte] = c;
413 val >>= 8 - from % 8;
414
415 for (i = from_byte+1; i < to_byte; i++)
416 {
417 c = val & 0xff;
418 val >>= 8;
419 b[i] = c;
420 }
421
422 if (to % 8 != 0)
423 {
424 unsigned char cv = (unsigned char) val;
425 c = b[to_byte];
426 c = c >> (to % 8) << (to % 8);
427 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
428 b[to_byte] = c;
429 }
430 }
431}
432
433/* Return the contents of slot N (for N = 0, 1, or 2) in
434 and instruction bundle */
435
244bc108 436static long long
2fc3ac7e 437slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 438{
439 return extract_bit_field (bundle, 5+41*slotnum, 41);
440}
441
442/* Store an instruction in an instruction bundle */
443
244bc108 444static void
2fc3ac7e 445replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 446{
447 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
448}
449
64a5b29c 450static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 451{
452 { M, I, I }, /* 00 */
453 { M, I, I }, /* 01 */
454 { M, I, I }, /* 02 */
455 { M, I, I }, /* 03 */
456 { M, L, X }, /* 04 */
457 { M, L, X }, /* 05 */
458 { undefined, undefined, undefined }, /* 06 */
459 { undefined, undefined, undefined }, /* 07 */
460 { M, M, I }, /* 08 */
461 { M, M, I }, /* 09 */
462 { M, M, I }, /* 0A */
463 { M, M, I }, /* 0B */
464 { M, F, I }, /* 0C */
465 { M, F, I }, /* 0D */
466 { M, M, F }, /* 0E */
467 { M, M, F }, /* 0F */
468 { M, I, B }, /* 10 */
469 { M, I, B }, /* 11 */
470 { M, B, B }, /* 12 */
471 { M, B, B }, /* 13 */
472 { undefined, undefined, undefined }, /* 14 */
473 { undefined, undefined, undefined }, /* 15 */
474 { B, B, B }, /* 16 */
475 { B, B, B }, /* 17 */
476 { M, M, B }, /* 18 */
477 { M, M, B }, /* 19 */
478 { undefined, undefined, undefined }, /* 1A */
479 { undefined, undefined, undefined }, /* 1B */
480 { M, F, B }, /* 1C */
481 { M, F, B }, /* 1D */
482 { undefined, undefined, undefined }, /* 1E */
483 { undefined, undefined, undefined }, /* 1F */
484};
485
486/* Fetch and (partially) decode an instruction at ADDR and return the
487 address of the next instruction to fetch. */
488
489static CORE_ADDR
490fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
491{
492 char bundle[BUNDLE_LEN];
493 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
494 long long template;
495 int val;
496
c26e1c2b
KB		 497 /* Warn about slot numbers greater than 2. We used to generate
498 an error here on the assumption that the user entered an invalid
499 address. But, sometimes GDB itself requests an invalid address.
500 This can (easily) happen when execution stops in a function for
501 which there are no symbols. The prologue scanner will attempt to
502 find the beginning of the function - if the nearest symbol
503 happens to not be aligned on a bundle boundary (16 bytes), the
504 resulting starting address will cause GDB to think that the slot
505 number is too large.
506
507 So we warn about it and set the slot number to zero. It is
508 not necessarily a fatal condition, particularly if debugging
509 at the assembly language level. */
16461d7d 510 if (slotnum > 2)
c26e1c2b 511 {
8a3fe4f8
AC		 512 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
513 "Using slot 0 instead"));
c26e1c2b
KB		 514 slotnum = 0;
515 }
16461d7d
KB		 516
517 addr &= ~0x0f;
518
519 val = target_read_memory (addr, bundle, BUNDLE_LEN);
520
521 if (val != 0)
522 return 0;
523
524 *instr = slotN_contents (bundle, slotnum);
525 template = extract_bit_field (bundle, 0, 5);
526 *it = template_encoding_table[(int)template][slotnum];
527
64a5b29c 528 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 529 addr += 16;
530 else
531 addr += (slotnum + 1) * SLOT_MULTIPLIER;
532
533 return addr;
534}
535
536/* There are 5 different break instructions (break.i, break.b,
537 break.m, break.f, and break.x), but they all have the same
538 encoding. (The five bit template in the low five bits of the
539 instruction bundle distinguishes one from another.)
540
541 The runtime architecture manual specifies that break instructions
542 used for debugging purposes must have the upper two bits of the 21
543 bit immediate set to a 0 and a 1 respectively. A breakpoint
544 instruction encodes the most significant bit of its 21 bit
545 immediate at bit 36 of the 41 bit instruction. The penultimate msb
546 is at bit 25 which leads to the pattern below.
547
548 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
549 it turns out that 0x80000 was used as the syscall break in the early
550 simulators. So I changed the pattern slightly to do "break.i 0x080001"
551 instead. But that didn't work either (I later found out that this
552 pattern was used by the simulator that I was using.) So I ended up
553 using the pattern seen below. */
554
555#if 0
aaab4dba 556#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 557#endif
aaab4dba 558#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 559
560static int
8181d85f 561ia64_memory_insert_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 562{
8181d85f 563 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 564 char bundle[BUNDLE_LEN];
565 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
566 long long instr;
567 int val;
126fa72d 568 int template;
16461d7d
KB		 569
570 if (slotnum > 2)
8a3fe4f8 571 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 572
573 addr &= ~0x0f;
574
575 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 576
577 /* Check for L type instruction in 2nd slot, if present then
578 bump up the slot number to the 3rd slot */
579 template = extract_bit_field (bundle, 0, 5);
580 if (slotnum == 1 && template_encoding_table[template][1] == L)
581 {
582 slotnum = 2;
583 }
584
16461d7d 585 instr = slotN_contents (bundle, slotnum);
8181d85f
DJ		 586 memcpy (bp_tgt->shadow_contents, &instr, sizeof (instr));
587 bp_tgt->placed_size = bp_tgt->shadow_len = sizeof (instr);
aaab4dba 588 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 589 if (val == 0)
590 target_write_memory (addr, bundle, BUNDLE_LEN);
591
592 return val;
593}
594
595static int
8181d85f 596ia64_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 597{
8181d85f 598 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 599 char bundle[BUNDLE_LEN];
600 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
601 long long instr;
602 int val;
126fa72d 603 int template;
16461d7d
KB		 604
605 addr &= ~0x0f;
606
607 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 608
609 /* Check for L type instruction in 2nd slot, if present then
610 bump up the slot number to the 3rd slot */
611 template = extract_bit_field (bundle, 0, 5);
612 if (slotnum == 1 && template_encoding_table[template][1] == L)
613 {
614 slotnum = 2;
615 }
616
8181d85f 617 memcpy (&instr, bp_tgt->shadow_contents, sizeof instr);
16461d7d
KB		 618 replace_slotN_contents (bundle, instr, slotnum);
619 if (val == 0)
620 target_write_memory (addr, bundle, BUNDLE_LEN);
621
622 return val;
623}
624
625/* We don't really want to use this, but remote.c needs to call it in order
626 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 627const unsigned char *
fba45db2 628ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 629{
630 static unsigned char breakpoint[] =
631 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
632 *lenptr = sizeof (breakpoint);
633#if 0
634 *pcptr &= ~0x0f;
635#endif
636 return breakpoint;
637}
638
a78f21af 639static CORE_ADDR
39f77062 640ia64_read_pc (ptid_t ptid)
16461d7d 641{
39f77062
KB		 642 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
643 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 644 int slot_num = (psr_value >> 41) & 3;
645
646 return pc_value | (slot_num * SLOT_MULTIPLIER);
647}
648
54a5c8d8 649void
39f77062 650ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 651{
652 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 653 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 654 psr_value &= ~(3LL << 41);
655 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
656
657 new_pc &= ~0xfLL;
658
39f77062
KB		 659 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
660 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 661}
662
663#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
664
665/* Returns the address of the slot that's NSLOTS slots away from
666 the address ADDR. NSLOTS may be positive or negative. */
667static CORE_ADDR
668rse_address_add(CORE_ADDR addr, int nslots)
669{
670 CORE_ADDR new_addr;
671 int mandatory_nat_slots = nslots / 63;
672 int direction = nslots < 0 ? -1 : 1;
673
674 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
675
676 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
677 new_addr += 8 * direction;
678
679 if (IS_NaT_COLLECTION_ADDR(new_addr))
680 new_addr += 8 * direction;
681
682 return new_addr;
683}
684
004d836a
JJ		 685static void
686ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 687 int regnum, gdb_byte *buf)
16461d7d 688{
004d836a 689 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 690 {
88d82102 691#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c
JJ		 692 /* First try and use the libunwind special reg accessor, otherwise fallback to
693 standard logic. */
694 if (!libunwind_is_initialized ()
695 || libunwind_get_reg_special (gdbarch, regnum, buf) != 0)
88d82102 696#endif
004d836a 697 {
c5a27d9c
JJ		 698 /* The fallback position is to assume that r32-r127 are found sequentially
699 in memory starting at $bof. This isn't always true, but without libunwind,
700 this is the best we can do. */
701 ULONGEST cfm;
702 ULONGEST bsp;
703 CORE_ADDR reg;
704 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
705 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
706
707 /* The bsp points at the end of the register frame so we
708 subtract the size of frame from it to get start of register frame. */
709 bsp = rse_address_add (bsp, -(cfm & 0x7f));
710
711 if ((cfm & 0x7f) > regnum - V32_REGNUM)
712 {
713 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
714 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
715 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
716 }
717 else
718 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a 719 }
004d836a
JJ		 720 }
721 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
722 {
723 ULONGEST unatN_val;
724 ULONGEST unat;
725 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
726 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 727 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 728 }
729 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
730 {
731 ULONGEST natN_val = 0;
732 ULONGEST bsp;
733 ULONGEST cfm;
734 CORE_ADDR gr_addr = 0;
735 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
736 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
737
738 /* The bsp points at the end of the register frame so we
739 subtract the size of frame from it to get start of register frame. */
740 bsp = rse_address_add (bsp, -(cfm & 0x7f));
741
742 if ((cfm & 0x7f) > regnum - V32_REGNUM)
743 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
744
745 if (gr_addr != 0)
746 {
747 /* Compute address of nat collection bits. */
748 CORE_ADDR nat_addr = gr_addr | 0x1f8;
749 CORE_ADDR nat_collection;
750 int nat_bit;
751 /* If our nat collection address is bigger than bsp, we have to get
752 the nat collection from rnat. Otherwise, we fetch the nat
753 collection from the computed address. */
754 if (nat_addr >= bsp)
755 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
756 else
757 nat_collection = read_memory_integer (nat_addr, 8);
758 nat_bit = (gr_addr >> 3) & 0x3f;
759 natN_val = (nat_collection >> nat_bit) & 1;
760 }
761
aa2a9a3c 762 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 763 }
004d836a
JJ		 764 else if (regnum == VBOF_REGNUM)
765 {
766 /* A virtual register frame start is provided for user convenience.
767 It can be calculated as the bsp - sof (sizeof frame). */
768 ULONGEST bsp, vbsp;
769 ULONGEST cfm;
770 CORE_ADDR reg;
771 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
772 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
773
774 /* The bsp points at the end of the register frame so we
775 subtract the size of frame from it to get beginning of frame. */
776 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 777 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 778 }
779 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
780 {
781 ULONGEST pr;
782 ULONGEST cfm;
783 ULONGEST prN_val;
784 CORE_ADDR reg;
785 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
786 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
787
788 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
789 {
790 /* Fetch predicate register rename base from current frame
791 marker for this frame. */
792 int rrb_pr = (cfm >> 32) & 0x3f;
793
794 /* Adjust the register number to account for register rotation. */
795 regnum = VP16_REGNUM
796 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
797 }
798 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 799 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 800 }
801 else
aa2a9a3c 802 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 803}
804
004d836a
JJ		 805static void
806ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 807 int regnum, const gdb_byte *buf)
16461d7d 808{
004d836a 809 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 810 {
004d836a
JJ		 811 ULONGEST bsp;
812 ULONGEST cfm;
813 CORE_ADDR reg;
814 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
815 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
816
817 bsp = rse_address_add (bsp, -(cfm & 0x7f));
818
819 if ((cfm & 0x7f) > regnum - V32_REGNUM)
820 {
821 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
822 write_memory (reg_addr, (void *)buf, 8);
823 }
824 }
825 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
826 {
827 ULONGEST unatN_val, unat, unatN_mask;
828 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 829 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 830 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
831 if (unatN_val == 0)
832 unat &= ~unatN_mask;
833 else if (unatN_val == 1)
834 unat |= unatN_mask;
835 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
836 }
837 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
838 {
839 ULONGEST natN_val;
840 ULONGEST bsp;
841 ULONGEST cfm;
842 CORE_ADDR gr_addr = 0;
843 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
844 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
845
846 /* The bsp points at the end of the register frame so we
847 subtract the size of frame from it to get start of register frame. */
848 bsp = rse_address_add (bsp, -(cfm & 0x7f));
849
850 if ((cfm & 0x7f) > regnum - V32_REGNUM)
851 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
852
aa2a9a3c 853 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 854
855 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
856 {
857 /* Compute address of nat collection bits. */
858 CORE_ADDR nat_addr = gr_addr | 0x1f8;
859 CORE_ADDR nat_collection;
860 int natN_bit = (gr_addr >> 3) & 0x3f;
861 ULONGEST natN_mask = (1LL << natN_bit);
862 /* If our nat collection address is bigger than bsp, we have to get
863 the nat collection from rnat. Otherwise, we fetch the nat
864 collection from the computed address. */
865 if (nat_addr >= bsp)
866 {
867 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
868 if (natN_val)
869 nat_collection |= natN_mask;
870 else
871 nat_collection &= ~natN_mask;
872 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
873 }
874 else
875 {
876 char nat_buf[8];
877 nat_collection = read_memory_integer (nat_addr, 8);
878 if (natN_val)
879 nat_collection |= natN_mask;
880 else
881 nat_collection &= ~natN_mask;
aa2a9a3c 882 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 883 write_memory (nat_addr, nat_buf, 8);
884 }
885 }
886 }
887 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
888 {
889 ULONGEST pr;
890 ULONGEST cfm;
891 ULONGEST prN_val;
892 ULONGEST prN_mask;
893
894 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
895 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
896
897 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
898 {
899 /* Fetch predicate register rename base from current frame
900 marker for this frame. */
901 int rrb_pr = (cfm >> 32) & 0x3f;
902
903 /* Adjust the register number to account for register rotation. */
904 regnum = VP16_REGNUM
905 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
906 }
aa2a9a3c 907 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 908 prN_mask = (1LL << (regnum - VP0_REGNUM));
909 if (prN_val == 0)
910 pr &= ~prN_mask;
911 else if (prN_val == 1)
912 pr |= prN_mask;
913 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 914 }
16461d7d
KB		 915}
916
004d836a
JJ		 917/* The ia64 needs to convert between various ieee floating-point formats
918 and the special ia64 floating point register format. */
919
920static int
921ia64_convert_register_p (int regno, struct type *type)
922{
923 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
924}
925
926static void
927ia64_register_to_value (struct frame_info *frame, int regnum,
88d82102 928 struct type *valtype, gdb_byte *out)
004d836a
JJ		 929{
930 char in[MAX_REGISTER_SIZE];
931 frame_register_read (frame, regnum, in);
932 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
933}
934
935static void
936ia64_value_to_register (struct frame_info *frame, int regnum,
88d82102 937 struct type *valtype, const gdb_byte *in)
004d836a
JJ		 938{
939 char out[MAX_REGISTER_SIZE];
940 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
941 put_frame_register (frame, regnum, out);
942}
943
944
58ab00f9
KB		 945/* Limit the number of skipped non-prologue instructions since examining
946 of the prologue is expensive. */
5ea2bd7f 947static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 948
949/* Given PC representing the starting address of a function, and
950 LIM_PC which is the (sloppy) limit to which to scan when looking
951 for a prologue, attempt to further refine this limit by using
952 the line data in the symbol table. If successful, a better guess
953 on where the prologue ends is returned, otherwise the previous
954 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
955 which will be set to indicate whether the returned limit may be
956 used with no further scanning in the event that the function is
957 frameless. */
958
634aa483
AC		 959/* FIXME: cagney/2004-02-14: This function and logic have largely been
960 superseded by skip_prologue_using_sal. */
961
58ab00f9
KB		 962static CORE_ADDR
963refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
964{
965 struct symtab_and_line prologue_sal;
966 CORE_ADDR start_pc = pc;
967
968 /* Start off not trusting the limit. */
969 *trust_limit = 0;
970
971 prologue_sal = find_pc_line (pc, 0);
972 if (prologue_sal.line != 0)
973 {
974 int i;
975 CORE_ADDR addr = prologue_sal.end;
976
977 /* Handle the case in which compiler's optimizer/scheduler
978 has moved instructions into the prologue. We scan ahead
979 in the function looking for address ranges whose corresponding
980 line number is less than or equal to the first one that we
981 found for the function. (It can be less than when the
982 scheduler puts a body instruction before the first prologue
983 instruction.) */
984 for (i = 2 * max_skip_non_prologue_insns;
985 i > 0 && (lim_pc == 0 || addr < lim_pc);
986 i--)
987 {
988 struct symtab_and_line sal;
989
990 sal = find_pc_line (addr, 0);
991 if (sal.line == 0)
992 break;
993 if (sal.line <= prologue_sal.line
994 && sal.symtab == prologue_sal.symtab)
995 {
996 prologue_sal = sal;
997 }
998 addr = sal.end;
999 }
1000
1001 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1002 {
1003 lim_pc = prologue_sal.end;
1004 if (start_pc == get_pc_function_start (lim_pc))
1005 *trust_limit = 1;
1006 }
1007 }
1008 return lim_pc;
1009}
1010
16461d7d
KB		 1011#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1012 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1013 || (14 <= (_regnum_) && (_regnum_) <= 31))
1014#define imm9(_instr_) \
1015 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1016 | (((_instr_) & 0x00008000000LL) >> 20) \
1017 | (((_instr_) & 0x00000001fc0LL) >> 6))
1018
004d836a
JJ		 1019/* Allocate and initialize a frame cache. */
1020
1021static struct ia64_frame_cache *
1022ia64_alloc_frame_cache (void)
1023{
1024 struct ia64_frame_cache *cache;
1025 int i;
1026
1027 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1028
1029 /* Base address. */
1030 cache->base = 0;
1031 cache->pc = 0;
1032 cache->cfm = 0;
4afcc598 1033 cache->prev_cfm = 0;
004d836a
JJ		 1034 cache->sof = 0;
1035 cache->sol = 0;
1036 cache->sor = 0;
1037 cache->bsp = 0;
1038 cache->fp_reg = 0;
1039 cache->frameless = 1;
1040
1041 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1042 cache->saved_regs[i] = 0;
1043
1044 return cache;
1045}
1046
16461d7d 1047static CORE_ADDR
004d836a 1048examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1049{
1050 CORE_ADDR next_pc;
1051 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1052 instruction_type it;
1053 long long instr;
16461d7d
KB		 1054 int cfm_reg = 0;
1055 int ret_reg = 0;
1056 int fp_reg = 0;
1057 int unat_save_reg = 0;
1058 int pr_save_reg = 0;
1059 int mem_stack_frame_size = 0;
1060 int spill_reg = 0;
1061 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1062 char instores[8];
1063 char infpstores[8];
5ea2bd7f 1064 char reg_contents[256];
58ab00f9 1065 int trust_limit;
004d836a
JJ		 1066 int frameless = 1;
1067 int i;
1068 CORE_ADDR addr;
1069 char buf[8];
1070 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1071
1072 memset (instores, 0, sizeof instores);
1073 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1074 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1075
004d836a
JJ		 1076 if (cache->after_prologue != 0
1077 && cache->after_prologue <= lim_pc)
1078 return cache->after_prologue;
16461d7d 1079
58ab00f9 1080 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1081 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1082
1083 /* We want to check if we have a recognizable function start before we
1084 look ahead for a prologue. */
16461d7d
KB		 1085 if (pc < lim_pc && next_pc
1086 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1087 {
5ea2bd7f 1088 /* alloc - start of a regular function. */
16461d7d
KB		 1089 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1090 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1091 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1092 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1093
1094 /* Verify that the current cfm matches what we think is the
1095 function start. If we have somehow jumped within a function,
1096 we do not want to interpret the prologue and calculate the
1097 addresses of various registers such as the return address.
1098 We will instead treat the frame as frameless. */
1099 if (!next_frame ||
1100 (sof == (cache->cfm & 0x7f) &&
1101 sol == ((cache->cfm >> 7) & 0x7f)))
1102 frameless = 0;
1103
16461d7d
KB		 1104 cfm_reg = rN;
1105 last_prologue_pc = next_pc;
1106 pc = next_pc;
1107 }
1108 else
58ab00f9 1109 {
5ea2bd7f
JJ		 1110 /* Look for a leaf routine. */
1111 if (pc < lim_pc && next_pc
1112 && (it == I || it == M)
1113 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1114 {
1115 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1116 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1117 | ((instr & 0x001f8000000LL) >> 20)
1118 | ((instr & 0x000000fe000LL) >> 13));
1119 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1120 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1121 int qp = (int) (instr & 0x0000000003fLL);
1122 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1123 {
1124 /* mov r2, r12 - beginning of leaf routine */
1125 fp_reg = rN;
5ea2bd7f
JJ		 1126 last_prologue_pc = next_pc;
1127 }
1128 }
1129
1130 /* If we don't recognize a regular function or leaf routine, we are
1131 done. */
1132 if (!fp_reg)
1133 {
1134 pc = lim_pc;
1135 if (trust_limit)
1136 last_prologue_pc = lim_pc;
1137 }
58ab00f9 1138 }
16461d7d
KB		 1139
1140 /* Loop, looking for prologue instructions, keeping track of
1141 where preserved registers were spilled. */
1142 while (pc < lim_pc)
1143 {
1144 next_pc = fetch_instruction (pc, &it, &instr);
1145 if (next_pc == 0)
1146 break;
1147
594706e6 1148 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1149 {
102d615a
JJ		 1150 /* Exit loop upon hitting a non-nop branch instruction. */
1151 if (trust_limit)
1152 lim_pc = pc;
1153 break;
1154 }
1155 else if (((instr & 0x3fLL) != 0LL) &&
1156 (frameless || ret_reg != 0))
1157 {
1158 /* Exit loop upon hitting a predicated instruction if
1159 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1160 if (trust_limit)
1161 lim_pc = pc;
0927a22b
KB		 1162 break;
1163 }
1164 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1165 {
1166 /* Move from BR */
1167 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1168 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1169 int qp = (int) (instr & 0x0000000003f);
1170
1171 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1172 {
1173 ret_reg = rN;
1174 last_prologue_pc = next_pc;
1175 }
1176 }
1177 else if ((it == I || it == M)
1178 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1179 {
1180 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1181 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1182 | ((instr & 0x001f8000000LL) >> 20)
1183 | ((instr & 0x000000fe000LL) >> 13));
1184 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1185 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1186 int qp = (int) (instr & 0x0000000003fLL);
1187
1188 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1189 {
1190 /* mov rN, r12 */
1191 fp_reg = rN;
1192 last_prologue_pc = next_pc;
1193 }
1194 else if (qp == 0 && rN == 12 && rM == 12)
1195 {
1196 /* adds r12, -mem_stack_frame_size, r12 */
1197 mem_stack_frame_size -= imm;
1198 last_prologue_pc = next_pc;
1199 }
1200 else if (qp == 0 && rN == 2
1201 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1202 {
004d836a
JJ		 1203 char buf[MAX_REGISTER_SIZE];
1204 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1205 /* adds r2, spilloffset, rFramePointer
1206 or
1207 adds r2, spilloffset, r12
1208
1209 Get ready for stf.spill or st8.spill instructions.
1210 The address to start spilling at is loaded into r2.
1211 FIXME: Why r2? That's what gcc currently uses; it
1212 could well be different for other compilers. */
1213
1214 /* Hmm... whether or not this will work will depend on
1215 where the pc is. If it's still early in the prologue
1216 this'll be wrong. FIXME */
004d836a
JJ		 1217 if (next_frame)
1218 {
1219 frame_unwind_register (next_frame, sp_regnum, buf);
1220 saved_sp = extract_unsigned_integer (buf, 8);
1221 }
1222 spill_addr = saved_sp
16461d7d
KB		 1223 + (rM == 12 ? 0 : mem_stack_frame_size)
1224 + imm;
1225 spill_reg = rN;
1226 last_prologue_pc = next_pc;
1227 }
5ea2bd7f
JJ		 1228 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1229 rN < 256 && imm == 0)
1230 {
1231 /* mov rN, rM where rM is an input register */
1232 reg_contents[rN] = rM;
1233 last_prologue_pc = next_pc;
1234 }
1235 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1236 rM == 2)
1237 {
1238 /* mov r12, r2 */
1239 last_prologue_pc = next_pc;
1240 break;
1241 }
16461d7d
KB		 1242 }
1243 else if (it == M
1244 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1245 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1246 {
1247 /* stf.spill [rN] = fM, imm9
1248 or
1249 stf.spill [rN] = fM */
1250
1251 int imm = imm9(instr);
1252 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1253 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1254 int qp = (int) (instr & 0x0000000003fLL);
1255 if (qp == 0 && rN == spill_reg && spill_addr != 0
1256 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1257 {
004d836a 1258 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1259
594706e6 1260 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1261 spill_addr += imm;
1262 else
1263 spill_addr = 0; /* last one; must be done */
1264 last_prologue_pc = next_pc;
1265 }
1266 }
1267 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1268 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1269 {
1270 /* mov.m rN = arM
1271 or
1272 mov.i rN = arM */
1273
1274 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1275 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1276 int qp = (int) (instr & 0x0000000003fLL);
1277 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1278 {
1279 /* We have something like "mov.m r3 = ar.unat". Remember the
1280 r3 (or whatever) and watch for a store of this register... */
1281 unat_save_reg = rN;
1282 last_prologue_pc = next_pc;
1283 }
1284 }
1285 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1286 {
1287 /* mov rN = pr */
1288 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1289 int qp = (int) (instr & 0x0000000003fLL);
1290 if (qp == 0 && isScratch (rN))
1291 {
1292 pr_save_reg = rN;
1293 last_prologue_pc = next_pc;
1294 }
1295 }
1296 else if (it == M
1297 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1298 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1299 {
1300 /* st8 [rN] = rM
1301 or
1302 st8 [rN] = rM, imm9 */
1303 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1304 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1305 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1306 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1307 if (qp == 0 && rN == spill_reg && spill_addr != 0
1308 && (rM == unat_save_reg || rM == pr_save_reg))
1309 {
1310 /* We've found a spill of either the UNAT register or the PR
1311 register. (Well, not exactly; what we've actually found is
1312 a spill of the register that UNAT or PR was moved to).
1313 Record that fact and move on... */
1314 if (rM == unat_save_reg)
1315 {
1316 /* Track UNAT register */
004d836a 1317 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1318 unat_save_reg = 0;
1319 }
1320 else
1321 {
1322 /* Track PR register */
004d836a 1323 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1324 pr_save_reg = 0;
1325 }
1326 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1327 /* st8 [rN] = rM, imm9 */
1328 spill_addr += imm9(instr);
1329 else
1330 spill_addr = 0; /* must be done spilling */
1331 last_prologue_pc = next_pc;
1332 }
0927a22b
KB		 1333 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1334 {
1335 /* Allow up to one store of each input register. */
1336 instores[rM-32] = 1;
1337 last_prologue_pc = next_pc;
1338 }
5ea2bd7f
JJ		 1339 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1340 !instores[indirect-32])
1341 {
1342 /* Allow an indirect store of an input register. */
1343 instores[indirect-32] = 1;
1344 last_prologue_pc = next_pc;
1345 }
0927a22b
KB		 1346 }
1347 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1348 {
1349 /* One of
1350 st1 [rN] = rM
1351 st2 [rN] = rM
1352 st4 [rN] = rM
1353 st8 [rN] = rM
1354 Note that the st8 case is handled in the clause above.
1355
1356 Advance over stores of input registers. One store per input
1357 register is permitted. */
1358 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1359 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1360 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1361 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1362 {
1363 instores[rM-32] = 1;
1364 last_prologue_pc = next_pc;
1365 }
5ea2bd7f
JJ		 1366 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1367 !instores[indirect-32])
1368 {
1369 /* Allow an indirect store of an input register. */
1370 instores[indirect-32] = 1;
1371 last_prologue_pc = next_pc;
1372 }
0927a22b
KB		 1373 }
1374 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1375 {
1376 /* Either
1377 stfs [rN] = fM
1378 or
1379 stfd [rN] = fM
1380
1381 Advance over stores of floating point input registers. Again
1382 one store per register is permitted */
1383 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1384 int qp = (int) (instr & 0x0000000003fLL);
1385 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1386 {
1387 infpstores[fM-8] = 1;
1388 last_prologue_pc = next_pc;
1389 }
16461d7d
KB		 1390 }
1391 else if (it == M
1392 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1393 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1394 {
1395 /* st8.spill [rN] = rM
1396 or
1397 st8.spill [rN] = rM, imm9 */
1398 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1399 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1400 int qp = (int) (instr & 0x0000000003fLL);
1401 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1402 {
1403 /* We've found a spill of one of the preserved general purpose
1404 regs. Record the spill address and advance the spill
1405 register if appropriate. */
004d836a 1406 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1407 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1408 /* st8.spill [rN] = rM, imm9 */
1409 spill_addr += imm9(instr);
1410 else
1411 spill_addr = 0; /* Done spilling */
1412 last_prologue_pc = next_pc;
1413 }
1414 }
16461d7d
KB		 1415
1416 pc = next_pc;
1417 }
1418
004d836a
JJ		 1419 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1420 registers for the previous frame which will be needed later. */
16461d7d 1421
004d836a 1422 if (!frameless && next_frame)
da50a4b7 1423 {
004d836a
JJ		 1424 /* Extract the size of the rotating portion of the stack
1425 frame and the register rename base from the current
1426 frame marker. */
1427 cfm = cache->cfm;
1428 sor = cache->sor;
1429 sof = cache->sof;
1430 sol = cache->sol;
1431 rrb_gr = (cfm >> 18) & 0x7f;
1432
1433 /* Find the bof (beginning of frame). */
1434 bof = rse_address_add (cache->bsp, -sof);
1435
1436 for (i = 0, addr = bof;
1437 i < sof;
1438 i++, addr += 8)
1439 {
1440 if (IS_NaT_COLLECTION_ADDR (addr))
1441 {
1442 addr += 8;
1443 }
1444 if (i+32 == cfm_reg)
1445 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1446 if (i+32 == ret_reg)
1447 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1448 if (i+32 == fp_reg)
1449 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1450 }
16461d7d 1451
004d836a
JJ		 1452 /* For the previous argument registers we require the previous bof.
1453 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1454 cfm = 0;
004d836a
JJ		 1455 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1456 {
1457 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1458 }
1459 else if (cfm_reg != 0)
1460 {
1461 frame_unwind_register (next_frame, cfm_reg, buf);
1462 cfm = extract_unsigned_integer (buf, 8);
1463 }
1464 cache->prev_cfm = cfm;
1465
1466 if (cfm != 0)
1467 {
004d836a
JJ		 1468 sor = ((cfm >> 14) & 0xf) * 8;
1469 sof = (cfm & 0x7f);
1470 sol = (cfm >> 7) & 0x7f;
1471 rrb_gr = (cfm >> 18) & 0x7f;
1472
1473 /* The previous bof only requires subtraction of the sol (size of locals)
1474 due to the overlap between output and input of subsequent frames. */
1475 bof = rse_address_add (bof, -sol);
1476
1477 for (i = 0, addr = bof;
1478 i < sof;
1479 i++, addr += 8)
1480 {
1481 if (IS_NaT_COLLECTION_ADDR (addr))
1482 {
1483 addr += 8;
1484 }
1485 if (i < sor)
1486 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1487 = addr;
1488 else
1489 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1490 }
1491
1492 }
1493 }
1494
5ea2bd7f
JJ		 1495 /* Try and trust the lim_pc value whenever possible. */
1496 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1497 last_prologue_pc = lim_pc;
1498
1499 cache->frameless = frameless;
1500 cache->after_prologue = last_prologue_pc;
1501 cache->mem_stack_frame_size = mem_stack_frame_size;
1502 cache->fp_reg = fp_reg;
5ea2bd7f 1503
16461d7d
KB		 1504 return last_prologue_pc;
1505}
1506
1507CORE_ADDR
1508ia64_skip_prologue (CORE_ADDR pc)
1509{
004d836a
JJ		 1510 struct ia64_frame_cache cache;
1511 cache.base = 0;
1512 cache.after_prologue = 0;
1513 cache.cfm = 0;
1514 cache.bsp = 0;
1515
1516 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1517 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1518}
1519
004d836a
JJ		 1520
1521/* Normal frames. */
1522
1523static struct ia64_frame_cache *
1524ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1525{
004d836a
JJ		 1526 struct ia64_frame_cache *cache;
1527 char buf[8];
1528 CORE_ADDR cfm, sof, sol, bsp, psr;
1529 int i;
16461d7d 1530
004d836a
JJ		 1531 if (*this_cache)
1532 return *this_cache;
16461d7d 1533
004d836a
JJ		 1534 cache = ia64_alloc_frame_cache ();
1535 *this_cache = cache;
16461d7d 1536
004d836a
JJ		 1537 frame_unwind_register (next_frame, sp_regnum, buf);
1538 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1539
004d836a
JJ		 1540 /* We always want the bsp to point to the end of frame.
1541 This way, we can always get the beginning of frame (bof)
1542 by subtracting frame size. */
1543 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1544 cache->bsp = extract_unsigned_integer (buf, 8);
1545
1546 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1547 psr = extract_unsigned_integer (buf, 8);
1548
1549 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1550 cfm = extract_unsigned_integer (buf, 8);
1551
1552 cache->sof = (cfm & 0x7f);
1553 cache->sol = (cfm >> 7) & 0x7f;
1554 cache->sor = ((cfm >> 14) & 0xf) * 8;
1555
1556 cache->cfm = cfm;
1557
1558 cache->pc = frame_func_unwind (next_frame);
1559
1560 if (cache->pc != 0)
1561 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1562
1563 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1564
1565 return cache;
16461d7d
KB		 1566}
1567
a78f21af 1568static void
004d836a
JJ		 1569ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1570 struct frame_id *this_id)
16461d7d 1571{
004d836a
JJ		 1572 struct ia64_frame_cache *cache =
1573 ia64_frame_cache (next_frame, this_cache);
16461d7d 1574
c5a27d9c 1575 /* If outermost frame, mark with null frame id. */
004d836a 1576 if (cache->base == 0)
c5a27d9c
JJ		 1577 (*this_id) = null_frame_id;
1578 else
1579 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1580 if (gdbarch_debug >= 1)
1581 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1582 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1583 paddr_nz (this_id->code_addr),
1584 paddr_nz (this_id->stack_addr),
1585 paddr_nz (cache->bsp), next_frame);
004d836a 1586}
244bc108 1587
004d836a
JJ		 1588static void
1589ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1590 int regnum, int *optimizedp,
1591 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1592 int *realnump, gdb_byte *valuep)
004d836a
JJ		 1593{
1594 struct ia64_frame_cache *cache =
1595 ia64_frame_cache (next_frame, this_cache);
1596 char dummy_valp[MAX_REGISTER_SIZE];
1597 char buf[8];
1598
1599 gdb_assert (regnum >= 0);
244bc108 1600
004d836a 1601 if (!target_has_registers)
8a3fe4f8 1602 error (_("No registers."));
244bc108 1603
004d836a
JJ		 1604 *optimizedp = 0;
1605 *addrp = 0;
1606 *lvalp = not_lval;
1607 *realnump = -1;
244bc108 1608
004d836a
JJ		 1609 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1610 when valuep is not supplied. */
1611 if (!valuep)
1612 valuep = dummy_valp;
1613
aa2a9a3c 1614 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1615
1616 if (regnum == SP_REGNUM)
16461d7d
KB		 1617 {
1618 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1619 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1620 cache->base);
16461d7d
KB		 1621 }
1622 else if (regnum == IA64_BSP_REGNUM)
1623 {
004d836a
JJ		 1624 char cfm_valuep[MAX_REGISTER_SIZE];
1625 int cfm_optim;
1626 int cfm_realnum;
1627 enum lval_type cfm_lval;
1628 CORE_ADDR cfm_addr;
1629 CORE_ADDR bsp, prev_cfm, prev_bsp;
1630
1631 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1632 This corresponds to what the hardware bsp register will be if we pop the frame
1633 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1634 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1635 the start of the output registers. We can calculate the end of that frame by adding
1636 the size of output (sof (size of frame) - sol (size of locals)). */
1637 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1638 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1639 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1640
1641 bsp = rse_address_add (cache->bsp, -(cache->sof));
1642 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1643
aa2a9a3c 1644 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1645 prev_bsp);
1646 }
1647 else if (regnum == IA64_CFM_REGNUM)
1648 {
4afcc598
JJ		 1649 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1650
1651 if (addr != 0)
004d836a 1652 {
4afcc598
JJ		 1653 *lvalp = lval_memory;
1654 *addrp = addr;
1655 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1656 }
4afcc598
JJ		 1657 else if (cache->prev_cfm)
1658 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1659 else if (cache->frameless)
004d836a 1660 {
4afcc598
JJ		 1661 CORE_ADDR cfm = 0;
1662 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1663 }
16461d7d
KB		 1664 }
1665 else if (regnum == IA64_VFP_REGNUM)
1666 {
1667 /* If the function in question uses an automatic register (r32-r127)
1668 for the frame pointer, it'll be found by ia64_find_saved_register()
1669 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1670 still provide a value since we know the size of the frame. */
1671 CORE_ADDR vfp = cache->base;
aa2a9a3c 1672 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1673 }
004d836a 1674 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1675 {
004d836a 1676 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1677 int pr_optim;
004d836a 1678 int pr_realnum;
16461d7d
KB		 1679 enum lval_type pr_lval;
1680 CORE_ADDR pr_addr;
004d836a
JJ		 1681 ULONGEST prN_val;
1682 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1683 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1684 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1685 {
1686 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1687 marker for this frame. */
1688 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1689
004d836a
JJ		 1690 /* Adjust the register number to account for register rotation. */
1691 regnum = VP16_REGNUM
1692 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1693 }
004d836a
JJ		 1694 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1695 regnum - VP0_REGNUM, 1);
aa2a9a3c 1696 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1697 }
1698 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1699 {
004d836a 1700 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1701 int unat_optim;
004d836a 1702 int unat_realnum;
16461d7d
KB		 1703 enum lval_type unat_lval;
1704 CORE_ADDR unat_addr;
004d836a
JJ		 1705 ULONGEST unatN_val;
1706 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1707 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1708 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1709 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1710 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1711 unatN_val);
16461d7d
KB		 1712 }
1713 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1714 {
1715 int natval = 0;
1716 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1717 interested in. */
1718 CORE_ADDR gr_addr;
244bc108 1719
004d836a
JJ		 1720 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1721 + IA64_GR0_REGNUM];
1722 if (gr_addr != 0)
244bc108 1723 {
004d836a 1724 /* Compute address of nat collection bits. */
16461d7d 1725 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1726 CORE_ADDR bsp;
16461d7d
KB		 1727 CORE_ADDR nat_collection;
1728 int nat_bit;
1729 /* If our nat collection address is bigger than bsp, we have to get
1730 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1731 collection from the computed address. */
1732 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1733 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1734 if (nat_addr >= bsp)
004d836a
JJ		 1735 {
1736 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1737 nat_collection = extract_unsigned_integer (buf, 8);
1738 }
16461d7d
KB		 1739 else
1740 nat_collection = read_memory_integer (nat_addr, 8);
1741 nat_bit = (gr_addr >> 3) & 0x3f;
1742 natval = (nat_collection >> nat_bit) & 1;
1743 }
004d836a 1744
aa2a9a3c 1745 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1746 }
1747 else if (regnum == IA64_IP_REGNUM)
1748 {
004d836a 1749 CORE_ADDR pc = 0;
4afcc598 1750 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1751
4afcc598 1752 if (addr != 0)
004d836a 1753 {
4afcc598
JJ		 1754 *lvalp = lval_memory;
1755 *addrp = addr;
1756 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1757 pc = extract_unsigned_integer (buf, 8);
1758 }
4afcc598 1759 else if (cache->frameless)
004d836a 1760 {
4afcc598
JJ		 1761 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1762 pc = extract_unsigned_integer (buf, 8);
244bc108 1763 }
004d836a
JJ		 1764 pc &= ~0xf;
1765 store_unsigned_integer (valuep, 8, pc);
244bc108 1766 }
004d836a 1767 else if (regnum == IA64_PSR_REGNUM)
244bc108 1768 {
4afcc598
JJ		 1769 /* We don't know how to get the complete previous PSR, but we need it for
1770 the slot information when we unwind the pc (pc is formed of IP register
1771 plus slot information from PSR). To get the previous slot information,
1772 we mask it off the return address. */
004d836a
JJ		 1773 ULONGEST slot_num = 0;
1774 CORE_ADDR pc= 0;
1775 CORE_ADDR psr = 0;
4afcc598 1776 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1777
1778 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1779 psr = extract_unsigned_integer (buf, 8);
1780
4afcc598 1781 if (addr != 0)
244bc108 1782 {
4afcc598
JJ		 1783 *lvalp = lval_memory;
1784 *addrp = addr;
1785 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1786 pc = extract_unsigned_integer (buf, 8);
244bc108 1787 }
4afcc598 1788 else if (cache->frameless)
004d836a 1789 {
4afcc598
JJ		 1790 CORE_ADDR pc;
1791 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1792 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1793 }
1794 psr &= ~(3LL << 41);
1795 slot_num = pc & 0x3LL;
1796 psr |= (CORE_ADDR)slot_num << 41;
1797 store_unsigned_integer (valuep, 8, psr);
1798 }
4afcc598
JJ		 1799 else if (regnum == IA64_BR0_REGNUM)
1800 {
1801 CORE_ADDR br0 = 0;
1802 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1803 if (addr != 0)
1804 {
1805 *lvalp = lval_memory;
1806 *addrp = addr;
1807 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1808 br0 = extract_unsigned_integer (buf, 8);
1809 }
1810 store_unsigned_integer (valuep, 8, br0);
1811 }
004d836a
JJ		 1812 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1813 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1814 {
1815 CORE_ADDR addr = 0;
1816 if (regnum >= V32_REGNUM)
1817 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1818 addr = cache->saved_regs[regnum];
244bc108
KB		 1819 if (addr != 0)
1820 {
004d836a
JJ		 1821 *lvalp = lval_memory;
1822 *addrp = addr;
aa2a9a3c 1823 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1824 }
004d836a 1825 else if (cache->frameless)
244bc108 1826 {
004d836a
JJ		 1827 char r_valuep[MAX_REGISTER_SIZE];
1828 int r_optim;
1829 int r_realnum;
1830 enum lval_type r_lval;
1831 CORE_ADDR r_addr;
1832 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1833 CORE_ADDR addr = 0;
1834 if (regnum >= V32_REGNUM)
1835 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1836 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1837 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1838 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1839 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1840 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1841 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1842 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1843
1844 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1845 *lvalp = lval_memory;
1846 *addrp = addr;
aa2a9a3c 1847 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1848 }
16461d7d
KB		 1849 }
1850 else
1851 {
004d836a 1852 CORE_ADDR addr = 0;
3a854e23
KB		 1853 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1854 {
1855 /* Fetch floating point register rename base from current
004d836a
JJ		 1856 frame marker for this frame. */
1857 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1858
1859 /* Adjust the floating point register number to account for
004d836a 1860 register rotation. */
3a854e23
KB		 1861 regnum = IA64_FR32_REGNUM
1862 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1863 }
1864
004d836a
JJ		 1865 /* If we have stored a memory address, access the register. */
1866 addr = cache->saved_regs[regnum];
1867 if (addr != 0)
1868 {
1869 *lvalp = lval_memory;
1870 *addrp = addr;
aa2a9a3c 1871 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1872 }
1873 /* Otherwise, punt and get the current value of the register. */
1874 else
1875 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1876 }
4afcc598
JJ		 1877
1878 if (gdbarch_debug >= 1)
1879 fprintf_unfiltered (gdb_stdlog,
78ced177 1880 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1881 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1882 ? ia64_register_names[regnum] : "r??"),
1883 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1884}
004d836a
JJ		 1885
1886static const struct frame_unwind ia64_frame_unwind =
1887{
1888 NORMAL_FRAME,
1889 &ia64_frame_this_id,
1890 &ia64_frame_prev_register
1891};
1892
1893static const struct frame_unwind *
1894ia64_frame_sniffer (struct frame_info *next_frame)
1895{
1896 return &ia64_frame_unwind;
1897}
1898
1899/* Signal trampolines. */
1900
1901static void
1902ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1903{
1904 if (SIGCONTEXT_REGISTER_ADDRESS)
1905 {
1906 int regno;
1907
1908 cache->saved_regs[IA64_VRAP_REGNUM] =
1909 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1910 cache->saved_regs[IA64_CFM_REGNUM] =
1911 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1912 cache->saved_regs[IA64_PSR_REGNUM] =
1913 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1914 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1915 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1916 cache->saved_regs[IA64_RNAT_REGNUM] =
1917 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1918 cache->saved_regs[IA64_CCV_REGNUM] =
1919 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1920 cache->saved_regs[IA64_UNAT_REGNUM] =
1921 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1922 cache->saved_regs[IA64_FPSR_REGNUM] =
1923 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1924 cache->saved_regs[IA64_PFS_REGNUM] =
1925 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1926 cache->saved_regs[IA64_LC_REGNUM] =
1927 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1928 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1929 cache->saved_regs[regno] =
1930 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1931 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1932 cache->saved_regs[regno] =
1933 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1934 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1935 cache->saved_regs[regno] =
1936 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1937 }
1938}
1939
1940static struct ia64_frame_cache *
1941ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1942{
1943 struct ia64_frame_cache *cache;
1944 CORE_ADDR addr;
1945 char buf[8];
1946 int i;
1947
1948 if (*this_cache)
1949 return *this_cache;
1950
1951 cache = ia64_alloc_frame_cache ();
1952
1953 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1954 /* Note that frame size is hard-coded below. We cannot calculate it
1955 via prologue examination. */
1956 cache->base = extract_unsigned_integer (buf, 8) + 16;
1957
1958 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1959 cache->bsp = extract_unsigned_integer (buf, 8);
1960
1961 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1962 cache->cfm = extract_unsigned_integer (buf, 8);
1963 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1964
1965 ia64_sigtramp_frame_init_saved_regs (cache);
1966
1967 *this_cache = cache;
1968 return cache;
1969}
1970
1971static void
1972ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1973 void **this_cache, struct frame_id *this_id)
1974{
1975 struct ia64_frame_cache *cache =
1976 ia64_sigtramp_frame_cache (next_frame, this_cache);
1977
4afcc598
JJ		 1978 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1979 if (gdbarch_debug >= 1)
1980 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1981 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1982 paddr_nz (this_id->code_addr),
1983 paddr_nz (this_id->stack_addr),
1984 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1985}
1986
1987static void
1988ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1989 void **this_cache,
1990 int regnum, int *optimizedp,
1991 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1992 int *realnump, gdb_byte *valuep)
004d836a 1993{
4afcc598
JJ		 1994 char dummy_valp[MAX_REGISTER_SIZE];
1995 char buf[MAX_REGISTER_SIZE];
1996
1997 struct ia64_frame_cache *cache =
1998 ia64_sigtramp_frame_cache (next_frame, this_cache);
1999
2000 gdb_assert (regnum >= 0);
2001
2002 if (!target_has_registers)
8a3fe4f8 2003 error (_("No registers."));
4afcc598
JJ		 2004
2005 *optimizedp = 0;
2006 *addrp = 0;
2007 *lvalp = not_lval;
2008 *realnump = -1;
2009
2010 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2011 when valuep is not supplied. */
2012 if (!valuep)
2013 valuep = dummy_valp;
2014
2015 memset (valuep, 0, register_size (current_gdbarch, regnum));
2016
2017 if (regnum == IA64_IP_REGNUM)
2018 {
2019 CORE_ADDR pc = 0;
2020 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2021
2022 if (addr != 0)
2023 {
2024 *lvalp = lval_memory;
2025 *addrp = addr;
2026 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2027 pc = extract_unsigned_integer (buf, 8);
2028 }
2029 pc &= ~0xf;
2030 store_unsigned_integer (valuep, 8, pc);
2031 }
2032 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2033 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2034 {
2035 CORE_ADDR addr = 0;
2036 if (regnum >= V32_REGNUM)
2037 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2038 addr = cache->saved_regs[regnum];
2039 if (addr != 0)
2040 {
2041 *lvalp = lval_memory;
2042 *addrp = addr;
2043 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2044 }
2045 }
2046 else
2047 {
2048 /* All other registers not listed above. */
2049 CORE_ADDR addr = cache->saved_regs[regnum];
2050 if (addr != 0)
2051 {
2052 *lvalp = lval_memory;
2053 *addrp = addr;
2054 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2055 }
2056 }
004d836a 2057
4afcc598
JJ		 2058 if (gdbarch_debug >= 1)
2059 fprintf_unfiltered (gdb_stdlog,
78ced177 2060 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2061 (regnum < IA64_GR32_REGNUM
2062 || (regnum > IA64_GR127_REGNUM
2063 && regnum < LAST_PSEUDO_REGNUM))
2064 ? ia64_register_names[regnum]
2065 : (regnum < LAST_PSEUDO_REGNUM
2066 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2067 : "OUT_OF_RANGE"),
78ced177 2068 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2069}
2070
2071static const struct frame_unwind ia64_sigtramp_frame_unwind =
2072{
2073 SIGTRAMP_FRAME,
2074 ia64_sigtramp_frame_this_id,
2075 ia64_sigtramp_frame_prev_register
2076};
2077
2078static const struct frame_unwind *
2079ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2080{
2081 char *name;
2082 CORE_ADDR pc = frame_pc_unwind (next_frame);
2083
2084 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2085 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2086 return &ia64_sigtramp_frame_unwind;
2087
2088 return NULL;
2089}
2090\f
2091
2092static CORE_ADDR
2093ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2094{
2095 struct ia64_frame_cache *cache =
2096 ia64_frame_cache (next_frame, this_cache);
2097
2098 return cache->base;
2099}
2100
2101static const struct frame_base ia64_frame_base =
2102{
2103 &ia64_frame_unwind,
2104 ia64_frame_base_address,
2105 ia64_frame_base_address,
2106 ia64_frame_base_address
2107};
16461d7d 2108
968d1cb4
JJ		 2109#ifdef HAVE_LIBUNWIND_IA64_H
2110
2111struct ia64_unwind_table_entry
2112 {
2113 unw_word_t start_offset;
2114 unw_word_t end_offset;
2115 unw_word_t info_offset;
2116 };
2117
2118static __inline__ uint64_t
2119ia64_rse_slot_num (uint64_t addr)
2120{
2121 return (addr >> 3) & 0x3f;
2122}
2123
2124/* Skip over a designated number of registers in the backing
2125 store, remembering every 64th position is for NAT. */
2126static __inline__ uint64_t
2127ia64_rse_skip_regs (uint64_t addr, long num_regs)
2128{
2129 long delta = ia64_rse_slot_num(addr) + num_regs;
2130
2131 if (num_regs < 0)
2132 delta -= 0x3e;
2133 return addr + ((num_regs + delta/0x3f) << 3);
2134}
2135
2136/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2137 number to a libunwind register number. */
2138static int
2139ia64_gdb2uw_regnum (int regnum)
2140{
2141 if (regnum == sp_regnum)
2142 return UNW_IA64_SP;
2143 else if (regnum == IA64_BSP_REGNUM)
2144 return UNW_IA64_BSP;
2145 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2146 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2147 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2148 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2149 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2150 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2151 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2152 return -1;
2153 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2154 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2155 else if (regnum == IA64_PR_REGNUM)
2156 return UNW_IA64_PR;
2157 else if (regnum == IA64_IP_REGNUM)
2158 return UNW_REG_IP;
2159 else if (regnum == IA64_CFM_REGNUM)
2160 return UNW_IA64_CFM;
2161 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2162 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2163 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2164 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2165 else
2166 return -1;
2167}
2168
2169/* Gdb libunwind-frame callback function to convert from a libunwind register
2170 number to a ia64 gdb register number. */
2171static int
2172ia64_uw2gdb_regnum (int uw_regnum)
2173{
2174 if (uw_regnum == UNW_IA64_SP)
2175 return sp_regnum;
2176 else if (uw_regnum == UNW_IA64_BSP)
2177 return IA64_BSP_REGNUM;
2178 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2179 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2180 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2181 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2182 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2183 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2184 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2185 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2186 else if (uw_regnum == UNW_IA64_PR)
2187 return IA64_PR_REGNUM;
2188 else if (uw_regnum == UNW_REG_IP)
2189 return IA64_IP_REGNUM;
2190 else if (uw_regnum == UNW_IA64_CFM)
2191 return IA64_CFM_REGNUM;
2192 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2193 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2194 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2195 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2196 else
2197 return -1;
2198}
2199
2200/* Gdb libunwind-frame callback function to reveal if register is a float
2201 register or not. */
2202static int
2203ia64_is_fpreg (int uw_regnum)
2204{
2205 return unw_is_fpreg (uw_regnum);
2206}
2207
2208/* Libunwind callback accessor function for general registers. */
2209static int
2210ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2211 int write, void *arg)
2212{
2213 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2214 unw_word_t bsp, sof, sol, cfm, psr, ip;
2215 struct frame_info *next_frame = arg;
2216 long new_sof, old_sof;
2217 char buf[MAX_REGISTER_SIZE];
2218
2219 if (write)
2220 {
2221 if (regnum < 0)
2222 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2223 return 0;
2224
2225 switch (uw_regnum)
2226 {
2227 case UNW_REG_IP:
2228 ia64_write_pc (*val, inferior_ptid);
2229 break;
2230
2231 case UNW_IA64_AR_BSPSTORE:
2232 write_register (IA64_BSP_REGNUM, *val);
2233 break;
2234
2235 case UNW_IA64_AR_BSP:
2236 case UNW_IA64_BSP:
2237 /* Account for the fact that ptrace() expects bsp to point
2238 after the current register frame. */
2239 cfm = read_register (IA64_CFM_REGNUM);
2240 sof = (cfm & 0x7f);
2241 bsp = ia64_rse_skip_regs (*val, sof);
2242 write_register (IA64_BSP_REGNUM, bsp);
2243 break;
2244
2245 case UNW_IA64_CFM:
2246 /* If we change CFM, we need to adjust ptrace's notion of
2247 bsp accordingly, so that the real bsp remains
2248 unchanged. */
2249 bsp = read_register (IA64_BSP_REGNUM);
2250 cfm = read_register (IA64_CFM_REGNUM);
2251 old_sof = (cfm & 0x7f);
2252 new_sof = (*val & 0x7f);
2253 if (old_sof != new_sof)
2254 {
2255 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2256 write_register (IA64_BSP_REGNUM, bsp);
2257 }
2258 write_register (IA64_CFM_REGNUM, *val);
2259 break;
2260
2261 default:
2262 write_register (regnum, *val);
2263 break;
2264 }
2265 if (gdbarch_debug >= 1)
2266 fprintf_unfiltered (gdb_stdlog,
78ced177 2267 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2268 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2269 ? ia64_register_names[regnum] : "r??"),
2270 paddr_nz (*val));
968d1cb4
JJ		 2271 }
2272 else
2273 {
2274 switch (uw_regnum)
2275 {
2276 case UNW_REG_IP:
2277 /* Libunwind expects to see the pc value which means the slot number
2278 from the psr must be merged with the ip word address. */
2279 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2280 ip = extract_unsigned_integer (buf, 8);
2281 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2282 psr = extract_unsigned_integer (buf, 8);
2283 *val = ip | ((psr >> 41) & 0x3);
2284 break;
2285
2286 case UNW_IA64_AR_BSP:
2287 /* Libunwind expects to see the beginning of the current register
2288 frame so we must account for the fact that ptrace() will return a value
2289 for bsp that points *after* the current register frame. */
2290 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2291 bsp = extract_unsigned_integer (buf, 8);
2292 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2293 cfm = extract_unsigned_integer (buf, 8);
2294 sof = (cfm & 0x7f);
2295 *val = ia64_rse_skip_regs (bsp, -sof);
2296 break;
2297
2298 case UNW_IA64_AR_BSPSTORE:
2299 /* Libunwind wants bspstore to be after the current register frame.
2300 This is what ptrace() and gdb treats as the regular bsp value. */
2301 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2302 *val = extract_unsigned_integer (buf, 8);
2303 break;
2304
2305 default:
2306 /* For all other registers, just unwind the value directly. */
2307 frame_unwind_register (next_frame, regnum, buf);
2308 *val = extract_unsigned_integer (buf, 8);
2309 break;
2310 }
2311
2312 if (gdbarch_debug >= 1)
2313 fprintf_unfiltered (gdb_stdlog,
78ced177 2314 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2315 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2316 ? ia64_register_names[regnum] : "r??"),
2317 paddr_nz (*val));
968d1cb4
JJ		 2318 }
2319 return 0;
2320}
2321
2322/* Libunwind callback accessor function for floating-point registers. */
2323static int
2324ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2325 int write, void *arg)
2326{
2327 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2328
2329 if (write)
2330 regcache_cooked_write (current_regcache, regnum, (char *) val);
2331 else
2332 regcache_cooked_read (current_regcache, regnum, (char *) val);
2333 return 0;
2334}
2335
c5a27d9c
JJ		 2336/* Libunwind callback accessor function for top-level rse registers. */
2337static int
2338ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2339 int write, void *arg)
2340{
2341 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2342 unw_word_t bsp, sof, sol, cfm, psr, ip;
2343 long new_sof, old_sof;
2344
2345 if (write)
2346 {
2347 if (regnum < 0)
2348 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2349 return 0;
2350
2351 switch (uw_regnum)
2352 {
2353 case UNW_REG_IP:
2354 ia64_write_pc (*val, inferior_ptid);
2355 break;
2356
2357 case UNW_IA64_AR_BSPSTORE:
2358 write_register (IA64_BSP_REGNUM, *val);
2359 break;
2360
2361 case UNW_IA64_AR_BSP:
2362 case UNW_IA64_BSP:
2363 /* Account for the fact that ptrace() expects bsp to point
2364 after the current register frame. */
2365 cfm = read_register (IA64_CFM_REGNUM);
2366 sof = (cfm & 0x7f);
2367 bsp = ia64_rse_skip_regs (*val, sof);
2368 write_register (IA64_BSP_REGNUM, bsp);
2369 break;
2370
2371 case UNW_IA64_CFM:
2372 /* If we change CFM, we need to adjust ptrace's notion of
2373 bsp accordingly, so that the real bsp remains
2374 unchanged. */
2375 bsp = read_register (IA64_BSP_REGNUM);
2376 cfm = read_register (IA64_CFM_REGNUM);
2377 old_sof = (cfm & 0x7f);
2378 new_sof = (*val & 0x7f);
2379 if (old_sof != new_sof)
2380 {
2381 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2382 write_register (IA64_BSP_REGNUM, bsp);
2383 }
2384 write_register (IA64_CFM_REGNUM, *val);
2385 break;
2386
2387 default:
2388 write_register (regnum, *val);
2389 break;
2390 }
2391 if (gdbarch_debug >= 1)
2392 fprintf_unfiltered (gdb_stdlog,
2393 " access_rse_reg: to cache: %4s=0x%s\n",
2394 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2395 ? ia64_register_names[regnum] : "r??"),
2396 paddr_nz (*val));
2397 }
2398 else
2399 {
2400 switch (uw_regnum)
2401 {
2402 case UNW_REG_IP:
2403 /* Libunwind expects to see the pc value which means the slot number
2404 from the psr must be merged with the ip word address. */
2405 ip = read_register (IA64_IP_REGNUM);
2406 psr = read_register (IA64_PSR_REGNUM);
2407 *val = ip | ((psr >> 41) & 0x3);
2408 break;
2409
2410 case UNW_IA64_AR_BSP:
2411 /* Libunwind expects to see the beginning of the current register
2412 frame so we must account for the fact that ptrace() will return a value
2413 for bsp that points *after* the current register frame. */
2414 bsp = read_register (IA64_BSP_REGNUM);
2415 cfm = read_register (IA64_CFM_REGNUM);
2416 sof = (cfm & 0x7f);
2417 *val = ia64_rse_skip_regs (bsp, -sof);
2418 break;
2419
2420 case UNW_IA64_AR_BSPSTORE:
2421 /* Libunwind wants bspstore to be after the current register frame.
2422 This is what ptrace() and gdb treats as the regular bsp value. */
2423 *val = read_register (IA64_BSP_REGNUM);
2424 break;
2425
2426 default:
2427 /* For all other registers, just read the value directly. */
2428 *val = read_register (regnum);
2429 break;
2430 }
2431 }
2432
2433 if (gdbarch_debug >= 1)
2434 fprintf_unfiltered (gdb_stdlog,
2435 " access_rse_reg: from cache: %4s=0x%s\n",
2436 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2437 ? ia64_register_names[regnum] : "r??"),
2438 paddr_nz (*val));
2439
2440 return 0;
2441}
2442
968d1cb4
JJ		 2443/* Libunwind callback accessor function for accessing memory. */
2444static int
2445ia64_access_mem (unw_addr_space_t as,
2446 unw_word_t addr, unw_word_t *val,
2447 int write, void *arg)
2448{
c5a27d9c
JJ		 2449 if (addr - KERNEL_START < ktab_size)
2450 {
2451 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2452 + (addr - KERNEL_START));
2453
2454 if (write)
2455 *laddr = *val;
2456 else
2457 *val = *laddr;
2458 return 0;
2459 }
2460
968d1cb4
JJ		 2461 /* XXX do we need to normalize byte-order here? */
2462 if (write)
2463 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2464 else
2465 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2466}
2467
2468/* Call low-level function to access the kernel unwind table. */
13547ab6
DJ		 2469static LONGEST
2470getunwind_table (gdb_byte **buf_p)
968d1cb4
JJ		 2471{
2472 LONGEST x;
c5a27d9c 2473
10d6c8cd
DJ		 2474 /* FIXME drow/2005-09-10: This code used to call
2475 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2476 for the currently running ia64-linux kernel. That data should
2477 come from the core file and be accessed via the auxv vector; if
2478 we want to preserve fall back to the running kernel's table, then
2479 we should find a way to override the corefile layer's
2480 xfer_partial method. */
968d1cb4 2481
13547ab6
DJ		 2482 x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2483 NULL, buf_p);
2484
2485 return x;
968d1cb4 2486}
10d6c8cd 2487
968d1cb4
JJ		 2488/* Get the kernel unwind table. */
2489static int
2490get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2491{
c5a27d9c 2492 static struct ia64_table_entry *etab;
968d1cb4 2493
c5a27d9c 2494 if (!ktab)
968d1cb4 2495 {
13547ab6 2496 gdb_byte *ktab_buf;
eeec829c 2497 LONGEST size;
13547ab6 2498
eeec829c
DJ		 2499 size = getunwind_table (&ktab_buf);
2500 if (size <= 0)
13547ab6 2501 return -UNW_ENOINFO;
eeec829c
DJ		 2502
2503 ktab = (struct ia64_table_entry *) ktab_buf;
2504 ktab_size = size;
13547ab6 2505
968d1cb4 2506 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2507 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2508 }
2509
2510 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2511 return -UNW_ENOINFO;
2512
2513 di->format = UNW_INFO_FORMAT_TABLE;
2514 di->gp = 0;
2515 di->start_ip = ktab[0].start_offset;
2516 di->end_ip = etab[-1].end_offset;
2517 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2518 di->u.ti.segbase = 0;
2519 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2520 di->u.ti.table_data = (unw_word_t *) ktab;
2521
2522 if (gdbarch_debug >= 1)
2523 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2524 "segbase=0x%s, length=%s, gp=0x%s\n",
2525 (char *) di->u.ti.name_ptr,
2526 paddr_nz (di->u.ti.segbase),
2527 paddr_u (di->u.ti.table_len),
2528 paddr_nz (di->gp));
968d1cb4
JJ		 2529 return 0;
2530}
2531
2532/* Find the unwind table entry for a specified address. */
2533static int
2534ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2535 unw_dyn_info_t *dip, void **buf)
2536{
2537 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2538 Elf_Internal_Ehdr *ehdr;
2539 unw_word_t segbase = 0;
2540 CORE_ADDR load_base;
2541 bfd *bfd;
2542 int i;
2543
2544 bfd = objfile->obfd;
2545
2546 ehdr = elf_tdata (bfd)->elf_header;
2547 phdr = elf_tdata (bfd)->phdr;
2548
2549 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2550
2551 for (i = 0; i < ehdr->e_phnum; ++i)
2552 {
2553 switch (phdr[i].p_type)
2554 {
2555 case PT_LOAD:
2556 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2557 < phdr[i].p_memsz)
2558 p_text = phdr + i;
2559 break;
2560
2561 case PT_IA_64_UNWIND:
2562 p_unwind = phdr + i;
2563 break;
2564
2565 default:
2566 break;
2567 }
2568 }
2569
c5a27d9c 2570 if (!p_text || !p_unwind)
968d1cb4
JJ		 2571 return -UNW_ENOINFO;
2572
c5a27d9c
JJ		 2573 /* Verify that the segment that contains the IP also contains
2574 the static unwind table. If not, we may be in the Linux kernel's
2575 DSO gate page in which case the unwind table is another segment.
2576 Otherwise, we are dealing with runtime-generated code, for which we
2577 have no info here. */
968d1cb4
JJ		 2578 segbase = p_text->p_vaddr + load_base;
2579
c5a27d9c
JJ		 2580 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2581 {
2582 int ok = 0;
2583 for (i = 0; i < ehdr->e_phnum; ++i)
2584 {
2585 if (phdr[i].p_type == PT_LOAD
2586 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2587 {
2588 ok = 1;
2589 /* Get the segbase from the section containing the
2590 libunwind table. */
2591 segbase = phdr[i].p_vaddr + load_base;
2592 }
2593 }
2594 if (!ok)
2595 return -UNW_ENOINFO;
2596 }
2597
2598 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2599 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2600 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2601 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2602 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2603 dip->u.rti.segbase = segbase;
2604 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2605 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2606
2607 return 0;
2608}
2609
2610/* Libunwind callback accessor function to acquire procedure unwind-info. */
2611static int
2612ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2613 int need_unwind_info, void *arg)
2614{
2615 struct obj_section *sec = find_pc_section (ip);
2616 unw_dyn_info_t di;
2617 int ret;
2618 void *buf = NULL;
2619
2620 if (!sec)
2621 {
2622 /* XXX This only works if the host and the target architecture are
2623 both ia64 and if the have (more or less) the same kernel
2624 version. */
2625 if (get_kernel_table (ip, &di) < 0)
2626 return -UNW_ENOINFO;
503ff15d
KB		 2627
2628 if (gdbarch_debug >= 1)
78ced177
JJ		 2629 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2630 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2631 "length=%s,data=0x%s)\n",
2632 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2633 paddr_nz (di.u.ti.segbase),
2634 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2635 paddr_nz (di.gp),
2636 paddr_u (di.u.ti.table_len),
2637 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2638 }
2639 else
2640 {
2641 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2642 if (ret < 0)
2643 return ret;
968d1cb4 2644
503ff15d 2645 if (gdbarch_debug >= 1)
78ced177
JJ		 2646 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2647 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2648 "length=%s,data=0x%s)\n",
2649 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2650 paddr_nz (di.u.rti.segbase),
2651 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2652 paddr_nz (di.gp),
2653 paddr_u (di.u.rti.table_len),
2654 paddr_nz (di.u.rti.table_data));
503ff15d 2655 }
968d1cb4 2656
503ff15d
KB		 2657 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2658 arg);
968d1cb4
JJ		 2659
2660 /* We no longer need the dyn info storage so free it. */
2661 xfree (buf);
2662
2663 return ret;
2664}
2665
2666/* Libunwind callback accessor function for cleanup. */
2667static void
2668ia64_put_unwind_info (unw_addr_space_t as,
2669 unw_proc_info_t *pip, void *arg)
2670{
2671 /* Nothing required for now. */
2672}
2673
2674/* Libunwind callback accessor function to get head of the dynamic
2675 unwind-info registration list. */
2676static int
2677ia64_get_dyn_info_list (unw_addr_space_t as,
2678 unw_word_t *dilap, void *arg)
2679{
2680 struct obj_section *text_sec;
2681 struct objfile *objfile;
2682 unw_word_t ip, addr;
2683 unw_dyn_info_t di;
2684 int ret;
2685
2686 if (!libunwind_is_initialized ())
2687 return -UNW_ENOINFO;
2688
2689 for (objfile = object_files; objfile; objfile = objfile->next)
2690 {
2691 void *buf = NULL;
2692
2693 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2694 ip = text_sec->addr;
2695 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2696 if (ret >= 0)
2697 {
503ff15d 2698 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2699 /* We no longer need the dyn info storage so free it. */
2700 xfree (buf);
2701
2702 if (addr)
2703 {
2704 if (gdbarch_debug >= 1)
2705 fprintf_unfiltered (gdb_stdlog,
2706 "dynamic unwind table in objfile %s "
78ced177 2707 "at 0x%s (gp=0x%s)\n",
968d1cb4 2708 bfd_get_filename (objfile->obfd),
78ced177 2709 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2710 *dilap = addr;
2711 return 0;
2712 }
2713 }
2714 }
2715 return -UNW_ENOINFO;
2716}
2717
2718
2719/* Frame interface functions for libunwind. */
2720
2721static void
2722ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2723 struct frame_id *this_id)
968d1cb4
JJ		 2724{
2725 char buf[8];
2726 CORE_ADDR bsp;
2727 struct frame_id id;
c5a27d9c
JJ		 2728 CORE_ADDR prev_ip, addr;
2729 int realnum, optimized;
2730 enum lval_type lval;
2731
968d1cb4
JJ		 2732
2733 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2734 if (frame_id_eq (id, null_frame_id))
2735 {
2736 (*this_id) = null_frame_id;
2737 return;
2738 }
968d1cb4 2739
c5a27d9c
JJ		 2740 /* We must add the bsp as the special address for frame comparison
2741 purposes. */
968d1cb4
JJ		 2742 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2743 bsp = extract_unsigned_integer (buf, 8);
2744
c5a27d9c
JJ		 2745 /* If the previous frame pc value is 0, then we are at the end of the stack
2746 and don't want to unwind past this frame. We return a null frame_id to
2747 indicate this. */
2748 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2749 &optimized, &lval, &addr, &realnum, buf);
2750 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2751
2752 if (prev_ip != 0)
2753 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2754 else
2755 (*this_id) = null_frame_id;
968d1cb4
JJ		 2756
2757 if (gdbarch_debug >= 1)
2758 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2759 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2760 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2761 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2762}
2763
2764static void
2765ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2766 void **this_cache,
2767 int regnum, int *optimizedp,
2768 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2769 int *realnump, gdb_byte *valuep)
968d1cb4
JJ		 2770{
2771 int reg = regnum;
2772
2773 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2774 reg = IA64_PR_REGNUM;
2775 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2776 reg = IA64_UNAT_REGNUM;
2777
2778 /* Let libunwind do most of the work. */
2779 libunwind_frame_prev_register (next_frame, this_cache, reg,
2780 optimizedp, lvalp, addrp, realnump, valuep);
2781
6672f2ae
AS		 2782 /* No more to do if the value is not supposed to be supplied. */
2783 if (!valuep)
2784 return;
2785
968d1cb4
JJ		 2786 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2787 {
2788 ULONGEST prN_val;
2789
2790 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2791 {
2792 int rrb_pr = 0;
2793 ULONGEST cfm;
2794 unsigned char buf[MAX_REGISTER_SIZE];
2795
2796 /* Fetch predicate register rename base from current frame
2797 marker for this frame. */
2798 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2799 cfm = extract_unsigned_integer (buf, 8);
2800 rrb_pr = (cfm >> 32) & 0x3f;
2801
2802 /* Adjust the register number to account for register rotation. */
2803 regnum = VP16_REGNUM
2804 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2805 }
2806 prN_val = extract_bit_field ((unsigned char *) valuep,
2807 regnum - VP0_REGNUM, 1);
2808 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2809 }
2810 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2811 {
2812 ULONGEST unatN_val;
2813
2814 unatN_val = extract_bit_field ((unsigned char *) valuep,
2815 regnum - IA64_NAT0_REGNUM, 1);
2816 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2817 unatN_val);
2818 }
2819 else if (regnum == IA64_BSP_REGNUM)
2820 {
2821 char cfm_valuep[MAX_REGISTER_SIZE];
2822 int cfm_optim;
2823 int cfm_realnum;
2824 enum lval_type cfm_lval;
2825 CORE_ADDR cfm_addr;
2826 CORE_ADDR bsp, prev_cfm, prev_bsp;
2827
2828 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2829 This corresponds to what the hardware bsp register will be if we pop the frame
2830 back which is why we might have been called. We know that libunwind will pass us back
2831 the beginning of the current frame so we should just add sof to it. */
2832 prev_bsp = extract_unsigned_integer (valuep, 8);
2833 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2834 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2835 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2836 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2837
2838 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2839 prev_bsp);
2840 }
2841
2842 if (gdbarch_debug >= 1)
2843 fprintf_unfiltered (gdb_stdlog,
78ced177 2844 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2845 (regnum < IA64_GR32_REGNUM
2846 || (regnum > IA64_GR127_REGNUM
2847 && regnum < LAST_PSEUDO_REGNUM))
2848 ? ia64_register_names[regnum]
2849 : (regnum < LAST_PSEUDO_REGNUM
2850 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2851 : "OUT_OF_RANGE"),
78ced177 2852 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2853}
2854
2855static const struct frame_unwind ia64_libunwind_frame_unwind =
2856{
2857 NORMAL_FRAME,
2858 ia64_libunwind_frame_this_id,
2859 ia64_libunwind_frame_prev_register
2860};
2861
2862static const struct frame_unwind *
2863ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2864{
2865 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2866 return &ia64_libunwind_frame_unwind;
2867
2868 return NULL;
2869}
2870
c5a27d9c
JJ		 2871static void
2872ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2873 struct frame_id *this_id)
2874{
2875 char buf[8];
2876 CORE_ADDR bsp;
2877 struct frame_id id;
2878 CORE_ADDR prev_ip;
2879
2880 libunwind_frame_this_id (next_frame, this_cache, &id);
2881 if (frame_id_eq (id, null_frame_id))
2882 {
2883 (*this_id) = null_frame_id;
2884 return;
2885 }
2886
2887 /* We must add the bsp as the special address for frame comparison
2888 purposes. */
2889 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2890 bsp = extract_unsigned_integer (buf, 8);
2891
2892 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2893 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2894
2895 if (gdbarch_debug >= 1)
2896 fprintf_unfiltered (gdb_stdlog,
2897 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2898 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2899 paddr_nz (bsp), next_frame);
2900}
2901
2902static void
2903ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2904 void **this_cache,
2905 int regnum, int *optimizedp,
2906 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2907 int *realnump, gdb_byte *valuep)
c5a27d9c
JJ		 2908
2909{
f1b4b38e 2910 gdb_byte buf[8];
c5a27d9c
JJ		 2911 CORE_ADDR prev_ip, addr;
2912 int realnum, optimized;
2913 enum lval_type lval;
2914
2915
2916 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2917 method of getting previous registers. */
2918 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2919 &optimized, &lval, &addr, &realnum, buf);
2920 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2921
2922 if (prev_ip == 0)
2923 {
2924 void *tmp_cache = NULL;
2925 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2926 addrp, realnump, valuep);
2927 }
2928 else
2929 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2930 addrp, realnump, valuep);
2931}
2932
2933static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2934{
2935 SIGTRAMP_FRAME,
2936 ia64_libunwind_sigtramp_frame_this_id,
2937 ia64_libunwind_sigtramp_frame_prev_register
2938};
2939
2940static const struct frame_unwind *
2941ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2942{
2943 if (libunwind_is_initialized ())
2944 {
2945 if (libunwind_sigtramp_frame_sniffer (next_frame))
2946 return &ia64_libunwind_sigtramp_frame_unwind;
2947 return NULL;
2948 }
2949 else
2950 return ia64_sigtramp_frame_sniffer (next_frame);
2951}
2952
968d1cb4
JJ		 2953/* Set of libunwind callback acccessor functions. */
2954static unw_accessors_t ia64_unw_accessors =
2955{
2956 ia64_find_proc_info_x,
2957 ia64_put_unwind_info,
2958 ia64_get_dyn_info_list,
2959 ia64_access_mem,
2960 ia64_access_reg,
2961 ia64_access_fpreg,
2962 /* resume */
2963 /* get_proc_name */
2964};
2965
c5a27d9c
JJ		 2966/* Set of special libunwind callback acccessor functions specific for accessing
2967 the rse registers. At the top of the stack, we want libunwind to figure out
2968 how to read r32 - r127. Though usually they are found sequentially in memory
2969 starting from $bof, this is not always true. */
2970static unw_accessors_t ia64_unw_rse_accessors =
2971{
2972 ia64_find_proc_info_x,
2973 ia64_put_unwind_info,
2974 ia64_get_dyn_info_list,
2975 ia64_access_mem,
2976 ia64_access_rse_reg,
2977 ia64_access_fpreg,
2978 /* resume */
2979 /* get_proc_name */
2980};
2981
968d1cb4
JJ		 2982/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2983static struct libunwind_descr ia64_libunwind_descr =
2984{
2985 ia64_gdb2uw_regnum,
2986 ia64_uw2gdb_regnum,
2987 ia64_is_fpreg,
2988 &ia64_unw_accessors,
c5a27d9c 2989 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2990};
2991
2992#endif /* HAVE_LIBUNWIND_IA64_H */
2993
74055713
AC		 2994/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2995 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2996 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2997int
2998ia64_use_struct_convention (int gcc_p, struct type *type)
2999{
64a5b29c
KB		 3000 struct type *float_elt_type;
3001
3002 /* HFAs are structures (or arrays) consisting entirely of floating
3003 point values of the same length. Up to 8 of these are returned
3004 in registers. Don't use the struct convention when this is the
004d836a 3005 case. */
64a5b29c
KB		 3006 float_elt_type = is_float_or_hfa_type (type);
3007 if (float_elt_type != NULL
3008 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
3009 return 0;
3010
3011 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 3012 Don't use the struct convention for those either. */
16461d7d
KB		 3013 return TYPE_LENGTH (type) > 32;
3014}
3015
3016void
2d522557
AC		 3017ia64_extract_return_value (struct type *type, struct regcache *regcache,
3018 gdb_byte *valbuf)
16461d7d 3019{
64a5b29c
KB		 3020 struct type *float_elt_type;
3021
3022 float_elt_type = is_float_or_hfa_type (type);
3023 if (float_elt_type != NULL)
3024 {
004d836a 3025 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 3026 int offset = 0;
3027 int regnum = IA64_FR8_REGNUM;
3028 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3029
3030 while (n-- > 0)
3031 {
004d836a
JJ		 3032 regcache_cooked_read (regcache, regnum, from);
3033 convert_typed_floating (from, builtin_type_ia64_ext,
3034 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 3035 offset += TYPE_LENGTH (float_elt_type);
3036 regnum++;
3037 }
3038 }
16461d7d 3039 else
004d836a
JJ		 3040 {
3041 ULONGEST val;
3042 int offset = 0;
3043 int regnum = IA64_GR8_REGNUM;
7b9ee6a8
DJ		 3044 int reglen = TYPE_LENGTH (register_type (get_regcache_arch (regcache),
3045 IA64_GR8_REGNUM));
004d836a
JJ		 3046 int n = TYPE_LENGTH (type) / reglen;
3047 int m = TYPE_LENGTH (type) % reglen;
16461d7d 3048
004d836a
JJ		 3049 while (n-- > 0)
3050 {
3051 ULONGEST val;
3052 regcache_cooked_read_unsigned (regcache, regnum, &val);
3053 memcpy ((char *)valbuf + offset, &val, reglen);
3054 offset += reglen;
3055 regnum++;
3056 }
16461d7d 3057
004d836a
JJ		 3058 if (m)
3059 {
3060 regcache_cooked_read_unsigned (regcache, regnum, &val);
3061 memcpy ((char *)valbuf + offset, &val, m);
3062 }
3063 }
16461d7d
KB		 3064}
3065
3066CORE_ADDR
004d836a 3067ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 3068{
8a3fe4f8 3069 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 3070 return 0;
16461d7d
KB		 3071}
3072
16461d7d 3073
64a5b29c
KB		 3074static int
3075is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3076{
3077 switch (TYPE_CODE (t))
3078 {
3079 case TYPE_CODE_FLT:
3080 if (*etp)
3081 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3082 else
3083 {
3084 *etp = t;
3085 return 1;
3086 }
3087 break;
3088 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3089 return
3090 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3091 etp);
64a5b29c
KB		 3092 break;
3093 case TYPE_CODE_STRUCT:
3094 {
3095 int i;
3096
3097 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3098 if (!is_float_or_hfa_type_recurse
3099 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3100 return 0;
3101 return 1;
3102 }
3103 break;
3104 default:
3105 return 0;
3106 break;
3107 }
3108}
3109
3110/* Determine if the given type is one of the floating point types or
3111 and HFA (which is a struct, array, or combination thereof whose
004d836a 3112 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3113
3114static struct type *
3115is_float_or_hfa_type (struct type *t)
3116{
3117 struct type *et = 0;
3118
3119 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3120}
3121
3122
98f96ba1
KB		 3123/* Return 1 if the alignment of T is such that the next even slot
3124 should be used. Return 0, if the next available slot should
3125 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3126 and Runtime manual). */
98f96ba1
KB		 3127
3128static int
3129slot_alignment_is_next_even (struct type *t)
3130{
3131 switch (TYPE_CODE (t))
3132 {
3133 case TYPE_CODE_INT:
3134 case TYPE_CODE_FLT:
3135 if (TYPE_LENGTH (t) > 8)
3136 return 1;
3137 else
3138 return 0;
3139 case TYPE_CODE_ARRAY:
3140 return
3141 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3142 case TYPE_CODE_STRUCT:
3143 {
3144 int i;
3145
3146 for (i = 0; i < TYPE_NFIELDS (t); i++)
3147 if (slot_alignment_is_next_even
3148 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3149 return 1;
3150 return 0;
3151 }
3152 default:
3153 return 0;
3154 }
3155}
3156
64a5b29c
KB		 3157/* Attempt to find (and return) the global pointer for the given
3158 function.
3159
3160 This is a rather nasty bit of code searchs for the .dynamic section
3161 in the objfile corresponding to the pc of the function we're trying
3162 to call. Once it finds the addresses at which the .dynamic section
3163 lives in the child process, it scans the Elf64_Dyn entries for a
3164 DT_PLTGOT tag. If it finds one of these, the corresponding
3165 d_un.d_ptr value is the global pointer. */
3166
3167static CORE_ADDR
b33e8514 3168ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3169{
76d689a6 3170 struct obj_section *faddr_sect;
64a5b29c 3171
76d689a6
KB		 3172 faddr_sect = find_pc_section (faddr);
3173 if (faddr_sect != NULL)
64a5b29c
KB		 3174 {
3175 struct obj_section *osect;
3176
76d689a6 3177 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3178 {
3179 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3180 break;
3181 }
3182
76d689a6 3183 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3184 {
3185 CORE_ADDR addr;
3186
3187 addr = osect->addr;
3188 while (addr < osect->endaddr)
3189 {
3190 int status;
3191 LONGEST tag;
3192 char buf[8];
3193
3194 status = target_read_memory (addr, buf, sizeof (buf));
3195 if (status != 0)
3196 break;
3197 tag = extract_signed_integer (buf, sizeof (buf));
3198
3199 if (tag == DT_PLTGOT)
3200 {
3201 CORE_ADDR global_pointer;
3202
3203 status = target_read_memory (addr + 8, buf, sizeof (buf));
3204 if (status != 0)
3205 break;
7c0b4a20 3206 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3207
3208 /* The payoff... */
3209 return global_pointer;
3210 }
3211
3212 if (tag == DT_NULL)
3213 break;
3214
3215 addr += 16;
3216 }
3217 }
3218 }
3219 return 0;
3220}
3221
3222/* Given a function's address, attempt to find (and return) the
3223 corresponding (canonical) function descriptor. Return 0 if
004d836a 3224 not found. */
64a5b29c
KB		 3225static CORE_ADDR
3226find_extant_func_descr (CORE_ADDR faddr)
3227{
76d689a6 3228 struct obj_section *faddr_sect;
64a5b29c 3229
004d836a 3230 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3231 faddr_sect = find_pc_section (faddr);
3232 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3233 return faddr;
3234
76d689a6 3235 if (faddr_sect != NULL)
64a5b29c 3236 {
76d689a6
KB		 3237 struct obj_section *osect;
3238 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3239 {
3240 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3241 break;
3242 }
3243
76d689a6 3244 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3245 {
3246 CORE_ADDR addr;
3247
3248 addr = osect->addr;
3249 while (addr < osect->endaddr)
3250 {
3251 int status;
3252 LONGEST faddr2;
3253 char buf[8];
3254
3255 status = target_read_memory (addr, buf, sizeof (buf));
3256 if (status != 0)
3257 break;
3258 faddr2 = extract_signed_integer (buf, sizeof (buf));
3259
3260 if (faddr == faddr2)
3261 return addr;
3262
3263 addr += 16;
3264 }
3265 }
3266 }
3267 return 0;
3268}
3269
3270/* Attempt to find a function descriptor corresponding to the
3271 given address. If none is found, construct one on the
004d836a 3272 stack using the address at fdaptr. */
64a5b29c
KB		 3273
3274static CORE_ADDR
3275find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
3276{
3277 CORE_ADDR fdesc;
3278
3279 fdesc = find_extant_func_descr (faddr);
3280
3281 if (fdesc == 0)
3282 {
3283 CORE_ADDR global_pointer;
3284 char buf[16];
3285
3286 fdesc = *fdaptr;
3287 *fdaptr += 16;
3288
b33e8514 3289 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3290
3291 if (global_pointer == 0)
3292 global_pointer = read_register (IA64_GR1_REGNUM);
3293
fbd9dcd3
AC		 3294 store_unsigned_integer (buf, 8, faddr);
3295 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3296
3297 write_memory (fdesc, buf, 16);
3298 }
3299
3300 return fdesc;
3301}
16461d7d 3302
af8b88dd
JJ		 3303/* Use the following routine when printing out function pointers
3304 so the user can see the function address rather than just the
3305 function descriptor. */
3306static CORE_ADDR
e2d0e7eb
AC		 3307ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3308 struct target_ops *targ)
af8b88dd
JJ		 3309{
3310 struct obj_section *s;
3311
3312 s = find_pc_section (addr);
3313
3314 /* check if ADDR points to a function descriptor. */
3315 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3316 return read_memory_unsigned_integer (addr, 8);
3317
0d5de010
DJ		 3318 /* There are also descriptors embedded in vtables. */
3319 if (s)
3320 {
3321 struct minimal_symbol *minsym;
3322
3323 minsym = lookup_minimal_symbol_by_pc (addr);
3324
3325 if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3326 return read_memory_unsigned_integer (addr, 8);
3327 }
3328
af8b88dd
JJ		 3329 return addr;
3330}
3331
a78f21af 3332static CORE_ADDR
004d836a
JJ		 3333ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3334{
3335 return sp & ~0xfLL;
3336}
3337
3338static CORE_ADDR
7d9b040b 3339ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3340 struct regcache *regcache, CORE_ADDR bp_addr,
3341 int nargs, struct value **args, CORE_ADDR sp,
3342 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3343{
3344 int argno;
ea7c478f 3345 struct value *arg;
16461d7d
KB		 3346 struct type *type;
3347 int len, argoffset;
64a5b29c 3348 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3349 int floatreg;
004d836a 3350 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3351 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3352
3353 nslots = 0;
64a5b29c 3354 nfuncargs = 0;
004d836a 3355 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3356 for (argno = 0; argno < nargs; argno++)
3357 {
3358 arg = args[argno];
4991999e 3359 type = check_typedef (value_type (arg));
16461d7d
KB		 3360 len = TYPE_LENGTH (type);
3361
98f96ba1 3362 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3363 nslots++;
3364
64a5b29c
KB		 3365 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3366 nfuncargs++;
3367
16461d7d
KB		 3368 nslots += (len + 7) / 8;
3369 }
3370
004d836a 3371 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3372 rseslots = (nslots > 8) ? 8 : nslots;
3373 memslots = nslots - rseslots;
3374
004d836a
JJ		 3375 /* Allocate a new RSE frame. */
3376 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3377
004d836a 3378 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3379 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3380 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3381
004d836a 3382 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3383 pfs &= 0xc000000000000000LL;
3384 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3385 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3386
3387 cfm &= 0xc000000000000000LL;
3388 cfm |= rseslots;
004d836a 3389 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3390
64a5b29c
KB		 3391 /* We will attempt to find function descriptors in the .opd segment,
3392 but if we can't we'll construct them ourselves. That being the
004d836a 3393 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3394 funcdescaddr = sp - nfuncargs * 16;
3395 funcdescaddr &= ~0xfLL;
3396
3397 /* Adjust the stack pointer to it's new value. The calling conventions
3398 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3399 necessary for the memory slots and our function descriptors. */
64a5b29c 3400 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3401 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3402
64a5b29c
KB		 3403 /* Place the arguments where they belong. The arguments will be
3404 either placed in the RSE backing store or on the memory stack.
3405 In addition, floating point arguments or HFAs are placed in
004d836a 3406 floating point registers. */
16461d7d
KB		 3407 slotnum = 0;
3408 floatreg = IA64_FR8_REGNUM;
3409 for (argno = 0; argno < nargs; argno++)
3410 {
64a5b29c
KB		 3411 struct type *float_elt_type;
3412
16461d7d 3413 arg = args[argno];
4991999e 3414 type = check_typedef (value_type (arg));
16461d7d 3415 len = TYPE_LENGTH (type);
64a5b29c 3416
004d836a 3417 /* Special handling for function parameters. */
64a5b29c
KB		 3418 if (len == 8
3419 && TYPE_CODE (type) == TYPE_CODE_PTR
3420 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3421 {
3422 char val_buf[8];
3423
fbd9dcd3 3424 store_unsigned_integer (val_buf, 8,
0fd88904 3425 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3426 &funcdescaddr));
64a5b29c
KB		 3427 if (slotnum < rseslots)
3428 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3429 else
3430 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3431 slotnum++;
3432 continue;
3433 }
3434
004d836a 3435 /* Normal slots. */
98f96ba1
KB		 3436
3437 /* Skip odd slot if necessary... */
3438 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3439 slotnum++;
98f96ba1 3440
16461d7d
KB		 3441 argoffset = 0;
3442 while (len > 0)
3443 {
3444 char val_buf[8];
3445
3446 memset (val_buf, 0, 8);
0fd88904 3447 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3448
3449 if (slotnum < rseslots)
3450 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3451 else
3452 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3453
3454 argoffset += 8;
3455 len -= 8;
3456 slotnum++;
3457 }
64a5b29c 3458
004d836a 3459 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3460 float_elt_type = is_float_or_hfa_type (type);
3461 if (float_elt_type != NULL)
3462 {
3463 argoffset = 0;
3464 len = TYPE_LENGTH (type);
3465 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3466 {
004d836a 3467 char to[MAX_REGISTER_SIZE];
0fd88904 3468 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3469 to, builtin_type_ia64_ext);
3470 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3471 floatreg++;
3472 argoffset += TYPE_LENGTH (float_elt_type);
3473 len -= TYPE_LENGTH (float_elt_type);
3474 }
16461d7d
KB		 3475 }
3476 }
3477
004d836a 3478 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3479 if (struct_return)
3480 {
004d836a 3481 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3482 }
3483
b33e8514 3484 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3485
004d836a
JJ		 3486 if (global_pointer != 0)
3487 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3488
004d836a 3489 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3490
004d836a 3491 write_register (sp_regnum, sp);
16461d7d
KB		 3492
3493 return sp;
3494}
3495
004d836a
JJ		 3496static struct frame_id
3497ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3498{
004d836a 3499 char buf[8];
4afcc598 3500 CORE_ADDR sp, bsp;
004d836a
JJ		 3501
3502 frame_unwind_register (next_frame, sp_regnum, buf);
3503 sp = extract_unsigned_integer (buf, 8);
3504
4afcc598
JJ		 3505 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3506 bsp = extract_unsigned_integer (buf, 8);
3507
3508 if (gdbarch_debug >= 1)
3509 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3510 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3511 paddr_nz (frame_pc_unwind (next_frame)),
3512 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3513
3514 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3515}
3516
004d836a
JJ		 3517static CORE_ADDR
3518ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3519{
004d836a
JJ		 3520 char buf[8];
3521 CORE_ADDR ip, psr, pc;
3522
3523 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3524 ip = extract_unsigned_integer (buf, 8);
3525 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3526 psr = extract_unsigned_integer (buf, 8);
3527
3528 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3529 return pc;
16461d7d
KB		 3530}
3531
3532static void
88d82102
JJ		 3533ia64_store_return_value (struct type *type, struct regcache *regcache,
3534 const gdb_byte *valbuf)
16461d7d 3535{
004d836a 3536 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3537 {
004d836a
JJ		 3538 char to[MAX_REGISTER_SIZE];
3539 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3540 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3541 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3542 }
3543 else
004d836a 3544 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3545}
3546
3547static void
1750fa04
AC		 3548ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3549 struct regcache *regcache,
3550 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3551 CORE_ADDR *targ_addr, int *targ_len)
3552{
3553 *targ_addr = memaddr;
3554 *targ_len = nr_bytes;
3555}
3556
6926787d
AS		 3557static int
3558ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3559{
3560 info->bytes_per_line = SLOT_MULTIPLIER;
3561 return print_insn_ia64 (memaddr, info);
3562}
3563
16461d7d
KB		 3564static struct gdbarch *
3565ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3566{
3567 struct gdbarch *gdbarch;
244bc108 3568 struct gdbarch_tdep *tdep;
244bc108 3569
85bf2b91
JJ		 3570 /* If there is already a candidate, use it. */
3571 arches = gdbarch_list_lookup_by_info (arches, &info);
3572 if (arches != NULL)
3573 return arches->gdbarch;
16461d7d 3574
244bc108
KB		 3575 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3576 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3577
b33e8514 3578 tdep->sigcontext_register_address = 0;
698cb3f0 3579
004d836a
JJ		 3580 /* Define the ia64 floating-point format to gdb. */
3581 builtin_type_ia64_ext =
3582 init_type (TYPE_CODE_FLT, 128 / 8,
3583 0, "builtin_type_ia64_ext", NULL);
8da61cc4 3584 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = floatformats_ia64_ext;
004d836a 3585
5439edaa
AC		 3586 /* According to the ia64 specs, instructions that store long double
3587 floats in memory use a long-double format different than that
3588 used in the floating registers. The memory format matches the
3589 x86 extended float format which is 80 bits. An OS may choose to
3590 use this format (e.g. GNU/Linux) or choose to use a different
3591 format for storing long doubles (e.g. HPUX). In the latter case,
3592 the setting of the format may be moved/overridden in an
3593 OS-specific tdep file. */
8da61cc4 3594 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
32edc941 3595
16461d7d
KB		 3596 set_gdbarch_short_bit (gdbarch, 16);
3597 set_gdbarch_int_bit (gdbarch, 32);
3598 set_gdbarch_long_bit (gdbarch, 64);
3599 set_gdbarch_long_long_bit (gdbarch, 64);
3600 set_gdbarch_float_bit (gdbarch, 32);
3601 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3602 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3603 set_gdbarch_ptr_bit (gdbarch, 64);
3604
004d836a
JJ		 3605 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3606 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3607 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3608 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3609
3610 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3611 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3612 gets a number of extra failures. */
b1e29e33 3613 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3614 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3615
004d836a
JJ		 3616 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3617 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3618 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3619 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3620 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3621 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3622 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3623
004d836a 3624 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3625
b5622e8d 3626 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3627 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3628
004d836a 3629 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3630 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3631
3632 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3633 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3634 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3635 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3636 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3637
3638 /* Settings for calling functions in the inferior. */
8dd5115e 3639 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3640 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3641 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3642
004d836a 3643 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3644#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3645 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3646 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3647 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3648#else
3649 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3650#endif
004d836a
JJ		 3651 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3652 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3653
3654 /* Settings that should be unnecessary. */
3655 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3656
16461d7d
KB		 3657 set_gdbarch_remote_translate_xfer_address (
3658 gdbarch, ia64_remote_translate_xfer_address);
3659
6926787d 3660 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3661 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3662
0d5de010
DJ		 3663 /* The virtual table contains 16-byte descriptors, not pointers to
3664 descriptors. */
3665 set_gdbarch_vtable_function_descriptors (gdbarch, 1);
3666
b33e8514
AS		 3667 /* Hook in ABI-specific overrides, if they have been registered. */
3668 gdbarch_init_osabi (info, gdbarch);
3669
16461d7d
KB		 3670 return gdbarch;
3671}
3672
a78f21af
AC		 3673extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3674
16461d7d
KB		 3675void
3676_initialize_ia64_tdep (void)
3677{
b33e8514 3678 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3679}
GDB Binutils - Deliverables
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