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[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
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16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
9b254dd1 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
13547ab6 4 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
16461d7d
KB		 11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
16461d7d
KB		 20
21#include "defs.h"
22#include "inferior.h"
16461d7d 23#include "gdbcore.h"
8064c6ae 24#include "arch-utils.h"
16461d7d 25#include "floatformat.h"
e6bb342a 26#include "gdbtypes.h"
4e052eda 27#include "regcache.h"
004d836a
JJ		 28#include "reggroups.h"
29#include "frame.h"
30#include "frame-base.h"
31#include "frame-unwind.h"
d16aafd8 32#include "doublest.h"
fd0407d6 33#include "value.h"
bd1ce8ba 34#include "gdb_assert.h"
16461d7d
KB		 35#include "objfiles.h"
36#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 37#include "elf-bfd.h"
a89aa300 38#include "dis-asm.h"
7d9b040b 39#include "infcall.h"
b33e8514 40#include "osabi.h"
9fc9f5e2 41#include "ia64-tdep.h"
0d5de010 42#include "cp-abi.h"
16461d7d 43
968d1cb4 44#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 45#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
c5a27d9c
JJ		 48
49/* Note: KERNEL_START is supposed to be an address which is not going
50 to ever contain any valid unwind info. For ia64 linux, the choice
51 of 0xc000000000000000 is fairly safe since that's uncached space.
52
53 We use KERNEL_START as follows: after obtaining the kernel's
54 unwind table via getunwind(), we project its unwind data into
55 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
56 when ia64_access_mem() sees a memory access to this
57 address-range, we redirect it to ktab instead.
58
59 None of this hackery is needed with a modern kernel/libcs
60 which uses the kernel virtual DSO to provide access to the
61 kernel's unwind info. In that case, ktab_size remains 0 and
62 hence the value of KERNEL_START doesn't matter. */
63
64#define KERNEL_START 0xc000000000000000ULL
65
66static size_t ktab_size = 0;
67struct ia64_table_entry
68 {
69 uint64_t start_offset;
70 uint64_t end_offset;
71 uint64_t info_offset;
72 };
73
74static struct ia64_table_entry *ktab = NULL;
75
968d1cb4
JJ		 76#endif
77
698cb3f0
KB		 78/* An enumeration of the different IA-64 instruction types. */
79
16461d7d
KB		 80typedef enum instruction_type
81{
82 A, /* Integer ALU ; I-unit or M-unit */
83 I, /* Non-ALU integer; I-unit */
84 M, /* Memory ; M-unit */
85 F, /* Floating-point ; F-unit */
86 B, /* Branch ; B-unit */
87 L, /* Extended (L+X) ; I-unit */
88 X, /* Extended (L+X) ; I-unit */
89 undefined /* undefined or reserved */
90} instruction_type;
91
92/* We represent IA-64 PC addresses as the value of the instruction
93 pointer or'd with some bit combination in the low nibble which
94 represents the slot number in the bundle addressed by the
95 instruction pointer. The problem is that the Linux kernel
96 multiplies its slot numbers (for exceptions) by one while the
97 disassembler multiplies its slot numbers by 6. In addition, I've
98 heard it said that the simulator uses 1 as the multiplier.
99
100 I've fixed the disassembler so that the bytes_per_line field will
101 be the slot multiplier. If bytes_per_line comes in as zero, it
102 is set to six (which is how it was set up initially). -- objdump
103 displays pretty disassembly dumps with this value. For our purposes,
104 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
105 never want to also display the raw bytes the way objdump does. */
106
107#define SLOT_MULTIPLIER 1
108
109/* Length in bytes of an instruction bundle */
110
111#define BUNDLE_LEN 16
112
16461d7d
KB		 113static gdbarch_init_ftype ia64_gdbarch_init;
114
115static gdbarch_register_name_ftype ia64_register_name;
004d836a 116static gdbarch_register_type_ftype ia64_register_type;
16461d7d 117static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 118static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 119static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 120static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 121
004d836a
JJ		 122static struct type *builtin_type_ia64_ext;
123
124#define NUM_IA64_RAW_REGS 462
16461d7d 125
16461d7d
KB		 126static int sp_regnum = IA64_GR12_REGNUM;
127static int fp_regnum = IA64_VFP_REGNUM;
128static int lr_regnum = IA64_VRAP_REGNUM;
129
004d836a 130/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 131 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 132enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
133 V127_REGNUM = V32_REGNUM + 95,
134 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 135
136/* Array of register names; There should be ia64_num_regs strings in
137 the initializer. */
138
139static char *ia64_register_names[] =
140{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
143 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
16461d7d
KB		 156
157 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
158 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
159 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
160 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
161 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
162 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
163 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
164 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
165 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
166 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
167 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
168 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
169 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
170 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
171 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
172 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
173
004d836a
JJ		 174 "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
16461d7d
KB		 182
183 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
184
185 "vfp", "vrap",
186
187 "pr", "ip", "psr", "cfm",
188
189 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
190 "", "", "", "", "", "", "", "",
191 "rsc", "bsp", "bspstore", "rnat",
192 "", "fcr", "", "",
193 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
194 "ccv", "", "", "", "unat", "", "", "",
195 "fpsr", "", "", "", "itc",
196 "", "", "", "", "", "", "", "", "", "",
197 "", "", "", "", "", "", "", "", "",
198 "pfs", "lc", "ec",
199 "", "", "", "", "", "", "", "", "", "",
200 "", "", "", "", "", "", "", "", "", "",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "",
206 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
207 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
208 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
209 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
210 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
211 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
212 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
213 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
214 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
215 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
216 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
217 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
218 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
219 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
220 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
221 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 222
223 "bof",
224
225 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
226 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
227 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
228 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
229 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
230 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
231 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
232 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
233 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
234 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
235 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
236 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
237
238 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
239 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
240 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
241 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
242 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
243 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
244 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
245 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 246};
247
004d836a
JJ		 248struct ia64_frame_cache
249{
250 CORE_ADDR base; /* frame pointer base for frame */
251 CORE_ADDR pc; /* function start pc for frame */
252 CORE_ADDR saved_sp; /* stack pointer for frame */
253 CORE_ADDR bsp; /* points at r32 for the current frame */
254 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 255 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 256 int frameless;
257 int sof; /* Size of frame (decoded from cfm value) */
258 int sol; /* Size of locals (decoded from cfm value) */
259 int sor; /* Number of rotating registers. (decoded from cfm value) */
260 CORE_ADDR after_prologue;
261 /* Address of first instruction after the last
262 prologue instruction; Note that there may
263 be instructions from the function's body
264 intermingled with the prologue. */
265 int mem_stack_frame_size;
266 /* Size of the memory stack frame (may be zero),
267 or -1 if it has not been determined yet. */
268 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 269 for this frame. 0 if no register is being used
16461d7d 270 as the frame pointer. */
004d836a
JJ		 271
272 /* Saved registers. */
273 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
274
275};
244bc108 276
004d836a
JJ		 277int
278ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
279 struct reggroup *group)
16461d7d 280{
004d836a
JJ		 281 int vector_p;
282 int float_p;
283 int raw_p;
284 if (group == all_reggroup)
285 return 1;
286 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
287 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
288 raw_p = regnum < NUM_IA64_RAW_REGS;
289 if (group == float_reggroup)
290 return float_p;
291 if (group == vector_reggroup)
292 return vector_p;
293 if (group == general_reggroup)
294 return (!vector_p && !float_p);
295 if (group == save_reggroup || group == restore_reggroup)
296 return raw_p;
297 return 0;
16461d7d
KB		 298}
299
004d836a 300static const char *
d93859e2 301ia64_register_name (struct gdbarch *gdbarch, int reg)
16461d7d 302{
004d836a 303 return ia64_register_names[reg];
16461d7d
KB		 304}
305
004d836a
JJ		 306struct type *
307ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 308{
004d836a
JJ		 309 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
310 return builtin_type_ia64_ext;
311 else
312 return builtin_type_long;
16461d7d
KB		 313}
314
a78f21af 315static int
d3f73121 316ia64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
16461d7d 317{
004d836a
JJ		 318 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
319 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
320 return reg;
16461d7d
KB		 321}
322
4afcc598 323static int
2fda21a6 324floatformat_valid (const struct floatformat *fmt, const void *from)
4afcc598
JJ		 325{
326 return 1;
327}
328
16461d7d
KB		 329const struct floatformat floatformat_ia64_ext =
330{
331 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
b14d30e1 332 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid, NULL
16461d7d
KB		 333};
334
8da61cc4
DJ		 335const struct floatformat *floatformats_ia64_ext[2] =
336{
337 &floatformat_ia64_ext,
338 &floatformat_ia64_ext
339};
340
16461d7d
KB		 341
342/* Extract ``len'' bits from an instruction bundle starting at
343 bit ``from''. */
344
244bc108 345static long long
16461d7d
KB		 346extract_bit_field (char *bundle, int from, int len)
347{
348 long long result = 0LL;
349 int to = from + len;
350 int from_byte = from / 8;
351 int to_byte = to / 8;
352 unsigned char *b = (unsigned char *) bundle;
353 unsigned char c;
354 int lshift;
355 int i;
356
357 c = b[from_byte];
358 if (from_byte == to_byte)
359 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
360 result = c >> (from % 8);
361 lshift = 8 - (from % 8);
362
363 for (i = from_byte+1; i < to_byte; i++)
364 {
365 result |= ((long long) b[i]) << lshift;
366 lshift += 8;
367 }
368
369 if (from_byte < to_byte && (to % 8 != 0))
370 {
371 c = b[to_byte];
372 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
373 result |= ((long long) c) << lshift;
374 }
375
376 return result;
377}
378
379/* Replace the specified bits in an instruction bundle */
380
244bc108 381static void
16461d7d
KB		 382replace_bit_field (char *bundle, long long val, int from, int len)
383{
384 int to = from + len;
385 int from_byte = from / 8;
386 int to_byte = to / 8;
387 unsigned char *b = (unsigned char *) bundle;
388 unsigned char c;
389
390 if (from_byte == to_byte)
391 {
392 unsigned char left, right;
393 c = b[from_byte];
394 left = (c >> (to % 8)) << (to % 8);
395 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
396 c = (unsigned char) (val & 0xff);
397 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
398 c |= right | left;
399 b[from_byte] = c;
400 }
401 else
402 {
403 int i;
404 c = b[from_byte];
405 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
406 c = c | (val << (from % 8));
407 b[from_byte] = c;
408 val >>= 8 - from % 8;
409
410 for (i = from_byte+1; i < to_byte; i++)
411 {
412 c = val & 0xff;
413 val >>= 8;
414 b[i] = c;
415 }
416
417 if (to % 8 != 0)
418 {
419 unsigned char cv = (unsigned char) val;
420 c = b[to_byte];
421 c = c >> (to % 8) << (to % 8);
422 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
423 b[to_byte] = c;
424 }
425 }
426}
427
428/* Return the contents of slot N (for N = 0, 1, or 2) in
429 and instruction bundle */
430
244bc108 431static long long
2fc3ac7e 432slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 433{
434 return extract_bit_field (bundle, 5+41*slotnum, 41);
435}
436
437/* Store an instruction in an instruction bundle */
438
244bc108 439static void
2fc3ac7e 440replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 441{
442 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
443}
444
64a5b29c 445static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 446{
447 { M, I, I }, /* 00 */
448 { M, I, I }, /* 01 */
449 { M, I, I }, /* 02 */
450 { M, I, I }, /* 03 */
451 { M, L, X }, /* 04 */
452 { M, L, X }, /* 05 */
453 { undefined, undefined, undefined }, /* 06 */
454 { undefined, undefined, undefined }, /* 07 */
455 { M, M, I }, /* 08 */
456 { M, M, I }, /* 09 */
457 { M, M, I }, /* 0A */
458 { M, M, I }, /* 0B */
459 { M, F, I }, /* 0C */
460 { M, F, I }, /* 0D */
461 { M, M, F }, /* 0E */
462 { M, M, F }, /* 0F */
463 { M, I, B }, /* 10 */
464 { M, I, B }, /* 11 */
465 { M, B, B }, /* 12 */
466 { M, B, B }, /* 13 */
467 { undefined, undefined, undefined }, /* 14 */
468 { undefined, undefined, undefined }, /* 15 */
469 { B, B, B }, /* 16 */
470 { B, B, B }, /* 17 */
471 { M, M, B }, /* 18 */
472 { M, M, B }, /* 19 */
473 { undefined, undefined, undefined }, /* 1A */
474 { undefined, undefined, undefined }, /* 1B */
475 { M, F, B }, /* 1C */
476 { M, F, B }, /* 1D */
477 { undefined, undefined, undefined }, /* 1E */
478 { undefined, undefined, undefined }, /* 1F */
479};
480
481/* Fetch and (partially) decode an instruction at ADDR and return the
482 address of the next instruction to fetch. */
483
484static CORE_ADDR
485fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
486{
487 char bundle[BUNDLE_LEN];
488 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
489 long long template;
490 int val;
491
c26e1c2b
KB		 492 /* Warn about slot numbers greater than 2. We used to generate
493 an error here on the assumption that the user entered an invalid
494 address. But, sometimes GDB itself requests an invalid address.
495 This can (easily) happen when execution stops in a function for
496 which there are no symbols. The prologue scanner will attempt to
497 find the beginning of the function - if the nearest symbol
498 happens to not be aligned on a bundle boundary (16 bytes), the
499 resulting starting address will cause GDB to think that the slot
500 number is too large.
501
502 So we warn about it and set the slot number to zero. It is
503 not necessarily a fatal condition, particularly if debugging
504 at the assembly language level. */
16461d7d 505 if (slotnum > 2)
c26e1c2b 506 {
8a3fe4f8
AC		 507 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
508 "Using slot 0 instead"));
c26e1c2b
KB		 509 slotnum = 0;
510 }
16461d7d
KB		 511
512 addr &= ~0x0f;
513
514 val = target_read_memory (addr, bundle, BUNDLE_LEN);
515
516 if (val != 0)
517 return 0;
518
519 *instr = slotN_contents (bundle, slotnum);
520 template = extract_bit_field (bundle, 0, 5);
521 *it = template_encoding_table[(int)template][slotnum];
522
64a5b29c 523 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 524 addr += 16;
525 else
526 addr += (slotnum + 1) * SLOT_MULTIPLIER;
527
528 return addr;
529}
530
531/* There are 5 different break instructions (break.i, break.b,
532 break.m, break.f, and break.x), but they all have the same
533 encoding. (The five bit template in the low five bits of the
534 instruction bundle distinguishes one from another.)
535
536 The runtime architecture manual specifies that break instructions
537 used for debugging purposes must have the upper two bits of the 21
538 bit immediate set to a 0 and a 1 respectively. A breakpoint
539 instruction encodes the most significant bit of its 21 bit
540 immediate at bit 36 of the 41 bit instruction. The penultimate msb
541 is at bit 25 which leads to the pattern below.
542
543 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
544 it turns out that 0x80000 was used as the syscall break in the early
545 simulators. So I changed the pattern slightly to do "break.i 0x080001"
546 instead. But that didn't work either (I later found out that this
547 pattern was used by the simulator that I was using.) So I ended up
548 using the pattern seen below. */
549
550#if 0
aaab4dba 551#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 552#endif
aaab4dba 553#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 554
555static int
ae4b2284
MD		 556ia64_memory_insert_breakpoint (struct gdbarch *gdbarch,
557 struct bp_target_info *bp_tgt)
16461d7d 558{
8181d85f 559 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 560 char bundle[BUNDLE_LEN];
561 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
562 long long instr;
563 int val;
126fa72d 564 int template;
16461d7d
KB		 565
566 if (slotnum > 2)
8a3fe4f8 567 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 568
569 addr &= ~0x0f;
570
571 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 572
573 /* Check for L type instruction in 2nd slot, if present then
574 bump up the slot number to the 3rd slot */
575 template = extract_bit_field (bundle, 0, 5);
576 if (slotnum == 1 && template_encoding_table[template][1] == L)
577 {
578 slotnum = 2;
579 }
580
16461d7d 581 instr = slotN_contents (bundle, slotnum);
8181d85f
DJ		 582 memcpy (bp_tgt->shadow_contents, &instr, sizeof (instr));
583 bp_tgt->placed_size = bp_tgt->shadow_len = sizeof (instr);
aaab4dba 584 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 585 if (val == 0)
586 target_write_memory (addr, bundle, BUNDLE_LEN);
587
588 return val;
589}
590
591static int
ae4b2284
MD		 592ia64_memory_remove_breakpoint (struct gdbarch *gdbarch,
593 struct bp_target_info *bp_tgt)
16461d7d 594{
8181d85f 595 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 596 char bundle[BUNDLE_LEN];
597 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
598 long long instr;
599 int val;
126fa72d 600 int template;
16461d7d
KB		 601
602 addr &= ~0x0f;
603
604 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 605
606 /* Check for L type instruction in 2nd slot, if present then
607 bump up the slot number to the 3rd slot */
608 template = extract_bit_field (bundle, 0, 5);
609 if (slotnum == 1 && template_encoding_table[template][1] == L)
610 {
611 slotnum = 2;
612 }
613
8181d85f 614 memcpy (&instr, bp_tgt->shadow_contents, sizeof instr);
16461d7d
KB		 615 replace_slotN_contents (bundle, instr, slotnum);
616 if (val == 0)
617 target_write_memory (addr, bundle, BUNDLE_LEN);
618
619 return val;
620}
621
622/* We don't really want to use this, but remote.c needs to call it in order
623 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 624const unsigned char *
67d57894 625ia64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 626{
627 static unsigned char breakpoint[] =
628 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
629 *lenptr = sizeof (breakpoint);
630#if 0
631 *pcptr &= ~0x0f;
632#endif
633 return breakpoint;
634}
635
a78f21af 636static CORE_ADDR
61a1198a 637ia64_read_pc (struct regcache *regcache)
16461d7d 638{
61a1198a
UW		 639 ULONGEST psr_value, pc_value;
640 int slot_num;
641
642 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
643 regcache_cooked_read_unsigned (regcache, IA64_IP_REGNUM, &pc_value);
644 slot_num = (psr_value >> 41) & 3;
16461d7d
KB		 645
646 return pc_value | (slot_num * SLOT_MULTIPLIER);
647}
648
54a5c8d8 649void
61a1198a 650ia64_write_pc (struct regcache *regcache, CORE_ADDR new_pc)
16461d7d
KB		 651{
652 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
61a1198a
UW		 653 ULONGEST psr_value;
654
655 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
16461d7d 656 psr_value &= ~(3LL << 41);
61a1198a 657 psr_value |= (ULONGEST)(slot_num & 0x3) << 41;
16461d7d
KB		 658
659 new_pc &= ~0xfLL;
660
61a1198a
UW		 661 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr_value);
662 regcache_cooked_write_unsigned (regcache, IA64_IP_REGNUM, new_pc);
16461d7d
KB		 663}
664
665#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
666
667/* Returns the address of the slot that's NSLOTS slots away from
668 the address ADDR. NSLOTS may be positive or negative. */
669static CORE_ADDR
670rse_address_add(CORE_ADDR addr, int nslots)
671{
672 CORE_ADDR new_addr;
673 int mandatory_nat_slots = nslots / 63;
674 int direction = nslots < 0 ? -1 : 1;
675
676 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
677
678 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
679 new_addr += 8 * direction;
680
681 if (IS_NaT_COLLECTION_ADDR(new_addr))
682 new_addr += 8 * direction;
683
684 return new_addr;
685}
686
004d836a
JJ		 687static void
688ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 689 int regnum, gdb_byte *buf)
16461d7d 690{
004d836a 691 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 692 {
88d82102 693#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c
JJ		 694 /* First try and use the libunwind special reg accessor, otherwise fallback to
695 standard logic. */
696 if (!libunwind_is_initialized ()
45ecac4b 697 || libunwind_get_reg_special (gdbarch, regcache, regnum, buf) != 0)
88d82102 698#endif
004d836a 699 {
c5a27d9c
JJ		 700 /* The fallback position is to assume that r32-r127 are found sequentially
701 in memory starting at $bof. This isn't always true, but without libunwind,
702 this is the best we can do. */
703 ULONGEST cfm;
704 ULONGEST bsp;
705 CORE_ADDR reg;
706 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
707 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
708
709 /* The bsp points at the end of the register frame so we
710 subtract the size of frame from it to get start of register frame. */
711 bsp = rse_address_add (bsp, -(cfm & 0x7f));
712
713 if ((cfm & 0x7f) > regnum - V32_REGNUM)
714 {
715 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
716 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
088568da 717 store_unsigned_integer (buf, register_size (gdbarch, regnum), reg);
c5a27d9c
JJ		 718 }
719 else
088568da 720 store_unsigned_integer (buf, register_size (gdbarch, regnum), 0);
004d836a 721 }
004d836a
JJ		 722 }
723 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
724 {
725 ULONGEST unatN_val;
726 ULONGEST unat;
727 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
728 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
088568da 729 store_unsigned_integer (buf, register_size (gdbarch, regnum), unatN_val);
004d836a
JJ		 730 }
731 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
732 {
733 ULONGEST natN_val = 0;
734 ULONGEST bsp;
735 ULONGEST cfm;
736 CORE_ADDR gr_addr = 0;
737 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
738 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
739
740 /* The bsp points at the end of the register frame so we
741 subtract the size of frame from it to get start of register frame. */
742 bsp = rse_address_add (bsp, -(cfm & 0x7f));
743
744 if ((cfm & 0x7f) > regnum - V32_REGNUM)
745 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
746
747 if (gr_addr != 0)
748 {
749 /* Compute address of nat collection bits. */
750 CORE_ADDR nat_addr = gr_addr | 0x1f8;
751 CORE_ADDR nat_collection;
752 int nat_bit;
753 /* If our nat collection address is bigger than bsp, we have to get
754 the nat collection from rnat. Otherwise, we fetch the nat
755 collection from the computed address. */
756 if (nat_addr >= bsp)
757 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
758 else
759 nat_collection = read_memory_integer (nat_addr, 8);
760 nat_bit = (gr_addr >> 3) & 0x3f;
761 natN_val = (nat_collection >> nat_bit) & 1;
762 }
763
088568da 764 store_unsigned_integer (buf, register_size (gdbarch, regnum), natN_val);
244bc108 765 }
004d836a
JJ		 766 else if (regnum == VBOF_REGNUM)
767 {
768 /* A virtual register frame start is provided for user convenience.
769 It can be calculated as the bsp - sof (sizeof frame). */
770 ULONGEST bsp, vbsp;
771 ULONGEST cfm;
772 CORE_ADDR reg;
773 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
774 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
775
776 /* The bsp points at the end of the register frame so we
777 subtract the size of frame from it to get beginning of frame. */
778 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
088568da 779 store_unsigned_integer (buf, register_size (gdbarch, regnum), vbsp);
004d836a
JJ		 780 }
781 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
782 {
783 ULONGEST pr;
784 ULONGEST cfm;
785 ULONGEST prN_val;
786 CORE_ADDR reg;
787 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
788 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
789
790 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
791 {
792 /* Fetch predicate register rename base from current frame
793 marker for this frame. */
794 int rrb_pr = (cfm >> 32) & 0x3f;
795
796 /* Adjust the register number to account for register rotation. */
797 regnum = VP16_REGNUM
798 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
799 }
800 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
088568da 801 store_unsigned_integer (buf, register_size (gdbarch, regnum), prN_val);
004d836a
JJ		 802 }
803 else
088568da 804 memset (buf, 0, register_size (gdbarch, regnum));
16461d7d
KB		 805}
806
004d836a
JJ		 807static void
808ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 809 int regnum, const gdb_byte *buf)
16461d7d 810{
004d836a 811 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 812 {
004d836a
JJ		 813 ULONGEST bsp;
814 ULONGEST cfm;
815 CORE_ADDR reg;
816 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
817 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
818
819 bsp = rse_address_add (bsp, -(cfm & 0x7f));
820
821 if ((cfm & 0x7f) > regnum - V32_REGNUM)
822 {
823 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
824 write_memory (reg_addr, (void *)buf, 8);
825 }
826 }
827 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
828 {
829 ULONGEST unatN_val, unat, unatN_mask;
830 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
088568da 831 unatN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum));
004d836a
JJ		 832 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
833 if (unatN_val == 0)
834 unat &= ~unatN_mask;
835 else if (unatN_val == 1)
836 unat |= unatN_mask;
837 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
838 }
839 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
840 {
841 ULONGEST natN_val;
842 ULONGEST bsp;
843 ULONGEST cfm;
844 CORE_ADDR gr_addr = 0;
845 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
846 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
847
848 /* The bsp points at the end of the register frame so we
849 subtract the size of frame from it to get start of register frame. */
850 bsp = rse_address_add (bsp, -(cfm & 0x7f));
851
852 if ((cfm & 0x7f) > regnum - V32_REGNUM)
853 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
854
088568da 855 natN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum));
004d836a
JJ		 856
857 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
858 {
859 /* Compute address of nat collection bits. */
860 CORE_ADDR nat_addr = gr_addr | 0x1f8;
861 CORE_ADDR nat_collection;
862 int natN_bit = (gr_addr >> 3) & 0x3f;
863 ULONGEST natN_mask = (1LL << natN_bit);
864 /* If our nat collection address is bigger than bsp, we have to get
865 the nat collection from rnat. Otherwise, we fetch the nat
866 collection from the computed address. */
867 if (nat_addr >= bsp)
868 {
869 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
870 if (natN_val)
871 nat_collection |= natN_mask;
872 else
873 nat_collection &= ~natN_mask;
874 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
875 }
876 else
877 {
878 char nat_buf[8];
879 nat_collection = read_memory_integer (nat_addr, 8);
880 if (natN_val)
881 nat_collection |= natN_mask;
882 else
883 nat_collection &= ~natN_mask;
088568da 884 store_unsigned_integer (nat_buf, register_size (gdbarch, regnum), nat_collection);
004d836a
JJ		 885 write_memory (nat_addr, nat_buf, 8);
886 }
887 }
888 }
889 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
890 {
891 ULONGEST pr;
892 ULONGEST cfm;
893 ULONGEST prN_val;
894 ULONGEST prN_mask;
895
896 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
897 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
898
899 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
900 {
901 /* Fetch predicate register rename base from current frame
902 marker for this frame. */
903 int rrb_pr = (cfm >> 32) & 0x3f;
904
905 /* Adjust the register number to account for register rotation. */
906 regnum = VP16_REGNUM
907 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
908 }
088568da 909 prN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum));
004d836a
JJ		 910 prN_mask = (1LL << (regnum - VP0_REGNUM));
911 if (prN_val == 0)
912 pr &= ~prN_mask;
913 else if (prN_val == 1)
914 pr |= prN_mask;
915 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 916 }
16461d7d
KB		 917}
918
004d836a
JJ		 919/* The ia64 needs to convert between various ieee floating-point formats
920 and the special ia64 floating point register format. */
921
922static int
0abe36f5 923ia64_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type)
004d836a 924{
83acabca
DJ		 925 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM
926 && type != builtin_type_ia64_ext);
004d836a
JJ		 927}
928
929static void
930ia64_register_to_value (struct frame_info *frame, int regnum,
88d82102 931 struct type *valtype, gdb_byte *out)
004d836a
JJ		 932{
933 char in[MAX_REGISTER_SIZE];
934 frame_register_read (frame, regnum, in);
935 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
936}
937
938static void
939ia64_value_to_register (struct frame_info *frame, int regnum,
88d82102 940 struct type *valtype, const gdb_byte *in)
004d836a
JJ		 941{
942 char out[MAX_REGISTER_SIZE];
943 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
944 put_frame_register (frame, regnum, out);
945}
946
947
58ab00f9
KB		 948/* Limit the number of skipped non-prologue instructions since examining
949 of the prologue is expensive. */
5ea2bd7f 950static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 951
952/* Given PC representing the starting address of a function, and
953 LIM_PC which is the (sloppy) limit to which to scan when looking
954 for a prologue, attempt to further refine this limit by using
955 the line data in the symbol table. If successful, a better guess
956 on where the prologue ends is returned, otherwise the previous
957 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
958 which will be set to indicate whether the returned limit may be
959 used with no further scanning in the event that the function is
960 frameless. */
961
634aa483
AC		 962/* FIXME: cagney/2004-02-14: This function and logic have largely been
963 superseded by skip_prologue_using_sal. */
964
58ab00f9
KB		 965static CORE_ADDR
966refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
967{
968 struct symtab_and_line prologue_sal;
969 CORE_ADDR start_pc = pc;
39312971
JB		 970 CORE_ADDR end_pc;
971
972 /* The prologue can not possibly go past the function end itself,
973 so we can already adjust LIM_PC accordingly. */
974 if (find_pc_partial_function (pc, NULL, NULL, &end_pc) && end_pc < lim_pc)
975 lim_pc = end_pc;
58ab00f9
KB		 976
977 /* Start off not trusting the limit. */
978 *trust_limit = 0;
979
980 prologue_sal = find_pc_line (pc, 0);
981 if (prologue_sal.line != 0)
982 {
983 int i;
984 CORE_ADDR addr = prologue_sal.end;
985
986 /* Handle the case in which compiler's optimizer/scheduler
987 has moved instructions into the prologue. We scan ahead
988 in the function looking for address ranges whose corresponding
989 line number is less than or equal to the first one that we
990 found for the function. (It can be less than when the
991 scheduler puts a body instruction before the first prologue
992 instruction.) */
993 for (i = 2 * max_skip_non_prologue_insns;
994 i > 0 && (lim_pc == 0 || addr < lim_pc);
995 i--)
996 {
997 struct symtab_and_line sal;
998
999 sal = find_pc_line (addr, 0);
1000 if (sal.line == 0)
1001 break;
1002 if (sal.line <= prologue_sal.line
1003 && sal.symtab == prologue_sal.symtab)
1004 {
1005 prologue_sal = sal;
1006 }
1007 addr = sal.end;
1008 }
1009
1010 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1011 {
1012 lim_pc = prologue_sal.end;
1013 if (start_pc == get_pc_function_start (lim_pc))
1014 *trust_limit = 1;
1015 }
1016 }
1017 return lim_pc;
1018}
1019
16461d7d
KB		 1020#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1021 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1022 || (14 <= (_regnum_) && (_regnum_) <= 31))
1023#define imm9(_instr_) \
1024 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1025 | (((_instr_) & 0x00008000000LL) >> 20) \
1026 | (((_instr_) & 0x00000001fc0LL) >> 6))
1027
004d836a
JJ		 1028/* Allocate and initialize a frame cache. */
1029
1030static struct ia64_frame_cache *
1031ia64_alloc_frame_cache (void)
1032{
1033 struct ia64_frame_cache *cache;
1034 int i;
1035
1036 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1037
1038 /* Base address. */
1039 cache->base = 0;
1040 cache->pc = 0;
1041 cache->cfm = 0;
4afcc598 1042 cache->prev_cfm = 0;
004d836a
JJ		 1043 cache->sof = 0;
1044 cache->sol = 0;
1045 cache->sor = 0;
1046 cache->bsp = 0;
1047 cache->fp_reg = 0;
1048 cache->frameless = 1;
1049
1050 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1051 cache->saved_regs[i] = 0;
1052
1053 return cache;
1054}
1055
16461d7d 1056static CORE_ADDR
004d836a 1057examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1058{
1059 CORE_ADDR next_pc;
1060 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1061 instruction_type it;
1062 long long instr;
16461d7d
KB		 1063 int cfm_reg = 0;
1064 int ret_reg = 0;
1065 int fp_reg = 0;
1066 int unat_save_reg = 0;
1067 int pr_save_reg = 0;
1068 int mem_stack_frame_size = 0;
1069 int spill_reg = 0;
1070 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1071 char instores[8];
1072 char infpstores[8];
5ea2bd7f 1073 char reg_contents[256];
58ab00f9 1074 int trust_limit;
004d836a
JJ		 1075 int frameless = 1;
1076 int i;
1077 CORE_ADDR addr;
1078 char buf[8];
1079 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1080
1081 memset (instores, 0, sizeof instores);
1082 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1083 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1084
004d836a
JJ		 1085 if (cache->after_prologue != 0
1086 && cache->after_prologue <= lim_pc)
1087 return cache->after_prologue;
16461d7d 1088
58ab00f9 1089 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1090 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1091
1092 /* We want to check if we have a recognizable function start before we
1093 look ahead for a prologue. */
16461d7d
KB		 1094 if (pc < lim_pc && next_pc
1095 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1096 {
5ea2bd7f 1097 /* alloc - start of a regular function. */
16461d7d
KB		 1098 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1099 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1100 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1101 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1102
1103 /* Verify that the current cfm matches what we think is the
1104 function start. If we have somehow jumped within a function,
1105 we do not want to interpret the prologue and calculate the
1106 addresses of various registers such as the return address.
1107 We will instead treat the frame as frameless. */
1108 if (!next_frame ||
1109 (sof == (cache->cfm & 0x7f) &&
1110 sol == ((cache->cfm >> 7) & 0x7f)))
1111 frameless = 0;
1112
16461d7d
KB		 1113 cfm_reg = rN;
1114 last_prologue_pc = next_pc;
1115 pc = next_pc;
1116 }
1117 else
58ab00f9 1118 {
5ea2bd7f
JJ		 1119 /* Look for a leaf routine. */
1120 if (pc < lim_pc && next_pc
1121 && (it == I || it == M)
1122 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1123 {
1124 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1125 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1126 | ((instr & 0x001f8000000LL) >> 20)
1127 | ((instr & 0x000000fe000LL) >> 13));
1128 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1129 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1130 int qp = (int) (instr & 0x0000000003fLL);
1131 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1132 {
1133 /* mov r2, r12 - beginning of leaf routine */
1134 fp_reg = rN;
5ea2bd7f
JJ		 1135 last_prologue_pc = next_pc;
1136 }
1137 }
1138
1139 /* If we don't recognize a regular function or leaf routine, we are
1140 done. */
1141 if (!fp_reg)
1142 {
1143 pc = lim_pc;
1144 if (trust_limit)
1145 last_prologue_pc = lim_pc;
1146 }
58ab00f9 1147 }
16461d7d
KB		 1148
1149 /* Loop, looking for prologue instructions, keeping track of
1150 where preserved registers were spilled. */
1151 while (pc < lim_pc)
1152 {
1153 next_pc = fetch_instruction (pc, &it, &instr);
1154 if (next_pc == 0)
1155 break;
1156
594706e6 1157 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1158 {
102d615a
JJ		 1159 /* Exit loop upon hitting a non-nop branch instruction. */
1160 if (trust_limit)
1161 lim_pc = pc;
1162 break;
1163 }
1164 else if (((instr & 0x3fLL) != 0LL) &&
1165 (frameless || ret_reg != 0))
1166 {
1167 /* Exit loop upon hitting a predicated instruction if
1168 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1169 if (trust_limit)
1170 lim_pc = pc;
0927a22b
KB		 1171 break;
1172 }
1173 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1174 {
1175 /* Move from BR */
1176 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1177 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1178 int qp = (int) (instr & 0x0000000003f);
1179
1180 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1181 {
1182 ret_reg = rN;
1183 last_prologue_pc = next_pc;
1184 }
1185 }
1186 else if ((it == I || it == M)
1187 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1188 {
1189 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1190 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1191 | ((instr & 0x001f8000000LL) >> 20)
1192 | ((instr & 0x000000fe000LL) >> 13));
1193 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1194 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1195 int qp = (int) (instr & 0x0000000003fLL);
1196
1197 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1198 {
1199 /* mov rN, r12 */
1200 fp_reg = rN;
1201 last_prologue_pc = next_pc;
1202 }
1203 else if (qp == 0 && rN == 12 && rM == 12)
1204 {
1205 /* adds r12, -mem_stack_frame_size, r12 */
1206 mem_stack_frame_size -= imm;
1207 last_prologue_pc = next_pc;
1208 }
1209 else if (qp == 0 && rN == 2
1210 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1211 {
004d836a
JJ		 1212 char buf[MAX_REGISTER_SIZE];
1213 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1214 /* adds r2, spilloffset, rFramePointer
1215 or
1216 adds r2, spilloffset, r12
1217
1218 Get ready for stf.spill or st8.spill instructions.
1219 The address to start spilling at is loaded into r2.
1220 FIXME: Why r2? That's what gcc currently uses; it
1221 could well be different for other compilers. */
1222
1223 /* Hmm... whether or not this will work will depend on
1224 where the pc is. If it's still early in the prologue
1225 this'll be wrong. FIXME */
004d836a
JJ		 1226 if (next_frame)
1227 {
1228 frame_unwind_register (next_frame, sp_regnum, buf);
1229 saved_sp = extract_unsigned_integer (buf, 8);
1230 }
1231 spill_addr = saved_sp
16461d7d
KB		 1232 + (rM == 12 ? 0 : mem_stack_frame_size)
1233 + imm;
1234 spill_reg = rN;
1235 last_prologue_pc = next_pc;
1236 }
5ea2bd7f
JJ		 1237 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1238 rN < 256 && imm == 0)
1239 {
1240 /* mov rN, rM where rM is an input register */
1241 reg_contents[rN] = rM;
1242 last_prologue_pc = next_pc;
1243 }
1244 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1245 rM == 2)
1246 {
1247 /* mov r12, r2 */
1248 last_prologue_pc = next_pc;
1249 break;
1250 }
16461d7d
KB		 1251 }
1252 else if (it == M
1253 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1254 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1255 {
1256 /* stf.spill [rN] = fM, imm9
1257 or
1258 stf.spill [rN] = fM */
1259
1260 int imm = imm9(instr);
1261 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1262 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1263 int qp = (int) (instr & 0x0000000003fLL);
1264 if (qp == 0 && rN == spill_reg && spill_addr != 0
1265 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1266 {
004d836a 1267 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1268
594706e6 1269 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1270 spill_addr += imm;
1271 else
1272 spill_addr = 0; /* last one; must be done */
1273 last_prologue_pc = next_pc;
1274 }
1275 }
1276 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1277 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1278 {
1279 /* mov.m rN = arM
1280 or
1281 mov.i rN = arM */
1282
1283 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1284 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1285 int qp = (int) (instr & 0x0000000003fLL);
1286 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1287 {
1288 /* We have something like "mov.m r3 = ar.unat". Remember the
1289 r3 (or whatever) and watch for a store of this register... */
1290 unat_save_reg = rN;
1291 last_prologue_pc = next_pc;
1292 }
1293 }
1294 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1295 {
1296 /* mov rN = pr */
1297 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1298 int qp = (int) (instr & 0x0000000003fLL);
1299 if (qp == 0 && isScratch (rN))
1300 {
1301 pr_save_reg = rN;
1302 last_prologue_pc = next_pc;
1303 }
1304 }
1305 else if (it == M
1306 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1307 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1308 {
1309 /* st8 [rN] = rM
1310 or
1311 st8 [rN] = rM, imm9 */
1312 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1313 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1314 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1315 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1316 if (qp == 0 && rN == spill_reg && spill_addr != 0
1317 && (rM == unat_save_reg || rM == pr_save_reg))
1318 {
1319 /* We've found a spill of either the UNAT register or the PR
1320 register. (Well, not exactly; what we've actually found is
1321 a spill of the register that UNAT or PR was moved to).
1322 Record that fact and move on... */
1323 if (rM == unat_save_reg)
1324 {
1325 /* Track UNAT register */
004d836a 1326 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1327 unat_save_reg = 0;
1328 }
1329 else
1330 {
1331 /* Track PR register */
004d836a 1332 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1333 pr_save_reg = 0;
1334 }
1335 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1336 /* st8 [rN] = rM, imm9 */
1337 spill_addr += imm9(instr);
1338 else
1339 spill_addr = 0; /* must be done spilling */
1340 last_prologue_pc = next_pc;
1341 }
0927a22b
KB		 1342 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1343 {
1344 /* Allow up to one store of each input register. */
1345 instores[rM-32] = 1;
1346 last_prologue_pc = next_pc;
1347 }
5ea2bd7f
JJ		 1348 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1349 !instores[indirect-32])
1350 {
1351 /* Allow an indirect store of an input register. */
1352 instores[indirect-32] = 1;
1353 last_prologue_pc = next_pc;
1354 }
0927a22b
KB		 1355 }
1356 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1357 {
1358 /* One of
1359 st1 [rN] = rM
1360 st2 [rN] = rM
1361 st4 [rN] = rM
1362 st8 [rN] = rM
1363 Note that the st8 case is handled in the clause above.
1364
1365 Advance over stores of input registers. One store per input
1366 register is permitted. */
1367 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1368 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1369 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1370 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1371 {
1372 instores[rM-32] = 1;
1373 last_prologue_pc = next_pc;
1374 }
5ea2bd7f
JJ		 1375 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1376 !instores[indirect-32])
1377 {
1378 /* Allow an indirect store of an input register. */
1379 instores[indirect-32] = 1;
1380 last_prologue_pc = next_pc;
1381 }
0927a22b
KB		 1382 }
1383 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1384 {
1385 /* Either
1386 stfs [rN] = fM
1387 or
1388 stfd [rN] = fM
1389
1390 Advance over stores of floating point input registers. Again
1391 one store per register is permitted */
1392 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1393 int qp = (int) (instr & 0x0000000003fLL);
1394 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1395 {
1396 infpstores[fM-8] = 1;
1397 last_prologue_pc = next_pc;
1398 }
16461d7d
KB		 1399 }
1400 else if (it == M
1401 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1402 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1403 {
1404 /* st8.spill [rN] = rM
1405 or
1406 st8.spill [rN] = rM, imm9 */
1407 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1408 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1409 int qp = (int) (instr & 0x0000000003fLL);
1410 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1411 {
1412 /* We've found a spill of one of the preserved general purpose
1413 regs. Record the spill address and advance the spill
1414 register if appropriate. */
004d836a 1415 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1416 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1417 /* st8.spill [rN] = rM, imm9 */
1418 spill_addr += imm9(instr);
1419 else
1420 spill_addr = 0; /* Done spilling */
1421 last_prologue_pc = next_pc;
1422 }
1423 }
16461d7d
KB		 1424
1425 pc = next_pc;
1426 }
1427
004d836a
JJ		 1428 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1429 registers for the previous frame which will be needed later. */
16461d7d 1430
004d836a 1431 if (!frameless && next_frame)
da50a4b7 1432 {
004d836a
JJ		 1433 /* Extract the size of the rotating portion of the stack
1434 frame and the register rename base from the current
1435 frame marker. */
1436 cfm = cache->cfm;
1437 sor = cache->sor;
1438 sof = cache->sof;
1439 sol = cache->sol;
1440 rrb_gr = (cfm >> 18) & 0x7f;
1441
1442 /* Find the bof (beginning of frame). */
1443 bof = rse_address_add (cache->bsp, -sof);
1444
1445 for (i = 0, addr = bof;
1446 i < sof;
1447 i++, addr += 8)
1448 {
1449 if (IS_NaT_COLLECTION_ADDR (addr))
1450 {
1451 addr += 8;
1452 }
1453 if (i+32 == cfm_reg)
1454 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1455 if (i+32 == ret_reg)
1456 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1457 if (i+32 == fp_reg)
1458 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1459 }
16461d7d 1460
004d836a
JJ		 1461 /* For the previous argument registers we require the previous bof.
1462 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1463 cfm = 0;
004d836a
JJ		 1464 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1465 {
1466 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1467 }
1468 else if (cfm_reg != 0)
1469 {
1470 frame_unwind_register (next_frame, cfm_reg, buf);
1471 cfm = extract_unsigned_integer (buf, 8);
1472 }
1473 cache->prev_cfm = cfm;
1474
1475 if (cfm != 0)
1476 {
004d836a
JJ		 1477 sor = ((cfm >> 14) & 0xf) * 8;
1478 sof = (cfm & 0x7f);
1479 sol = (cfm >> 7) & 0x7f;
1480 rrb_gr = (cfm >> 18) & 0x7f;
1481
1482 /* The previous bof only requires subtraction of the sol (size of locals)
1483 due to the overlap between output and input of subsequent frames. */
1484 bof = rse_address_add (bof, -sol);
1485
1486 for (i = 0, addr = bof;
1487 i < sof;
1488 i++, addr += 8)
1489 {
1490 if (IS_NaT_COLLECTION_ADDR (addr))
1491 {
1492 addr += 8;
1493 }
1494 if (i < sor)
1495 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1496 = addr;
1497 else
1498 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1499 }
1500
1501 }
1502 }
1503
5ea2bd7f
JJ		 1504 /* Try and trust the lim_pc value whenever possible. */
1505 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1506 last_prologue_pc = lim_pc;
1507
1508 cache->frameless = frameless;
1509 cache->after_prologue = last_prologue_pc;
1510 cache->mem_stack_frame_size = mem_stack_frame_size;
1511 cache->fp_reg = fp_reg;
5ea2bd7f 1512
16461d7d
KB		 1513 return last_prologue_pc;
1514}
1515
1516CORE_ADDR
6093d2eb 1517ia64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
16461d7d 1518{
004d836a
JJ		 1519 struct ia64_frame_cache cache;
1520 cache.base = 0;
1521 cache.after_prologue = 0;
1522 cache.cfm = 0;
1523 cache.bsp = 0;
1524
1525 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1526 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1527}
1528
004d836a
JJ		 1529
1530/* Normal frames. */
1531
1532static struct ia64_frame_cache *
1533ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1534{
004d836a
JJ		 1535 struct ia64_frame_cache *cache;
1536 char buf[8];
1537 CORE_ADDR cfm, sof, sol, bsp, psr;
1538 int i;
16461d7d 1539
004d836a
JJ		 1540 if (*this_cache)
1541 return *this_cache;
16461d7d 1542
004d836a
JJ		 1543 cache = ia64_alloc_frame_cache ();
1544 *this_cache = cache;
16461d7d 1545
004d836a
JJ		 1546 frame_unwind_register (next_frame, sp_regnum, buf);
1547 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1548
004d836a
JJ		 1549 /* We always want the bsp to point to the end of frame.
1550 This way, we can always get the beginning of frame (bof)
1551 by subtracting frame size. */
1552 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1553 cache->bsp = extract_unsigned_integer (buf, 8);
1554
1555 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1556 psr = extract_unsigned_integer (buf, 8);
1557
1558 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1559 cfm = extract_unsigned_integer (buf, 8);
1560
1561 cache->sof = (cfm & 0x7f);
1562 cache->sol = (cfm >> 7) & 0x7f;
1563 cache->sor = ((cfm >> 14) & 0xf) * 8;
1564
1565 cache->cfm = cfm;
1566
93d42b30 1567 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
004d836a
JJ		 1568
1569 if (cache->pc != 0)
1570 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1571
1572 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1573
1574 return cache;
16461d7d
KB		 1575}
1576
a78f21af 1577static void
004d836a
JJ		 1578ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1579 struct frame_id *this_id)
16461d7d 1580{
004d836a
JJ		 1581 struct ia64_frame_cache *cache =
1582 ia64_frame_cache (next_frame, this_cache);
16461d7d 1583
c5a27d9c 1584 /* If outermost frame, mark with null frame id. */
004d836a 1585 if (cache->base == 0)
c5a27d9c
JJ		 1586 (*this_id) = null_frame_id;
1587 else
1588 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1589 if (gdbarch_debug >= 1)
1590 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1591 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1592 paddr_nz (this_id->code_addr),
1593 paddr_nz (this_id->stack_addr),
1594 paddr_nz (cache->bsp), next_frame);
004d836a 1595}
244bc108 1596
004d836a
JJ		 1597static void
1598ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1599 int regnum, int *optimizedp,
1600 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1601 int *realnump, gdb_byte *valuep)
004d836a 1602{
088568da 1603 struct gdbarch *gdbarch = get_frame_arch (next_frame);
004d836a
JJ		 1604 struct ia64_frame_cache *cache =
1605 ia64_frame_cache (next_frame, this_cache);
1606 char dummy_valp[MAX_REGISTER_SIZE];
1607 char buf[8];
1608
1609 gdb_assert (regnum >= 0);
244bc108 1610
004d836a 1611 if (!target_has_registers)
8a3fe4f8 1612 error (_("No registers."));
244bc108 1613
004d836a
JJ		 1614 *optimizedp = 0;
1615 *addrp = 0;
1616 *lvalp = not_lval;
1617 *realnump = -1;
244bc108 1618
004d836a
JJ		 1619 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1620 when valuep is not supplied. */
1621 if (!valuep)
1622 valuep = dummy_valp;
1623
088568da 1624 memset (valuep, 0, register_size (gdbarch, regnum));
004d836a 1625
088568da 1626 if (regnum == gdbarch_sp_regnum (gdbarch))
16461d7d
KB		 1627 {
1628 /* Handle SP values for all frames but the topmost. */
088568da 1629 store_unsigned_integer (valuep, register_size (gdbarch, regnum),
004d836a 1630 cache->base);
16461d7d
KB		 1631 }
1632 else if (regnum == IA64_BSP_REGNUM)
1633 {
004d836a
JJ		 1634 char cfm_valuep[MAX_REGISTER_SIZE];
1635 int cfm_optim;
1636 int cfm_realnum;
1637 enum lval_type cfm_lval;
1638 CORE_ADDR cfm_addr;
1639 CORE_ADDR bsp, prev_cfm, prev_bsp;
1640
1641 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1642 This corresponds to what the hardware bsp register will be if we pop the frame
1643 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1644 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1645 the start of the output registers. We can calculate the end of that frame by adding
1646 the size of output (sof (size of frame) - sol (size of locals)). */
1647 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1648 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1649 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1650
1651 bsp = rse_address_add (cache->bsp, -(cache->sof));
1652 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1653
088568da 1654 store_unsigned_integer (valuep, register_size (gdbarch, regnum),
004d836a
JJ		 1655 prev_bsp);
1656 }
1657 else if (regnum == IA64_CFM_REGNUM)
1658 {
4afcc598
JJ		 1659 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1660
1661 if (addr != 0)
004d836a 1662 {
4afcc598
JJ		 1663 *lvalp = lval_memory;
1664 *addrp = addr;
088568da 1665 read_memory (addr, valuep, register_size (gdbarch, regnum));
004d836a 1666 }
4afcc598 1667 else if (cache->prev_cfm)
088568da 1668 store_unsigned_integer (valuep, register_size (gdbarch, regnum), cache->prev_cfm);
4afcc598 1669 else if (cache->frameless)
004d836a 1670 {
4afcc598
JJ		 1671 CORE_ADDR cfm = 0;
1672 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1673 }
16461d7d
KB		 1674 }
1675 else if (regnum == IA64_VFP_REGNUM)
1676 {
1677 /* If the function in question uses an automatic register (r32-r127)
1678 for the frame pointer, it'll be found by ia64_find_saved_register()
1679 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1680 still provide a value since we know the size of the frame. */
1681 CORE_ADDR vfp = cache->base;
088568da 1682 store_unsigned_integer (valuep, register_size (gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1683 }
004d836a 1684 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1685 {
004d836a 1686 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1687 int pr_optim;
004d836a 1688 int pr_realnum;
16461d7d
KB		 1689 enum lval_type pr_lval;
1690 CORE_ADDR pr_addr;
004d836a
JJ		 1691 ULONGEST prN_val;
1692 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1693 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1694 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1695 {
1696 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1697 marker for this frame. */
1698 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1699
004d836a
JJ		 1700 /* Adjust the register number to account for register rotation. */
1701 regnum = VP16_REGNUM
1702 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1703 }
004d836a
JJ		 1704 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1705 regnum - VP0_REGNUM, 1);
088568da 1706 store_unsigned_integer (valuep, register_size (gdbarch, regnum), prN_val);
16461d7d
KB		 1707 }
1708 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1709 {
004d836a 1710 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1711 int unat_optim;
004d836a 1712 int unat_realnum;
16461d7d
KB		 1713 enum lval_type unat_lval;
1714 CORE_ADDR unat_addr;
004d836a
JJ		 1715 ULONGEST unatN_val;
1716 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1717 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1718 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1719 regnum - IA64_NAT0_REGNUM, 1);
088568da 1720 store_unsigned_integer (valuep, register_size (gdbarch, regnum),
16461d7d 1721 unatN_val);
16461d7d
KB		 1722 }
1723 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1724 {
1725 int natval = 0;
1726 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1727 interested in. */
1728 CORE_ADDR gr_addr;
244bc108 1729
004d836a
JJ		 1730 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1731 + IA64_GR0_REGNUM];
1732 if (gr_addr != 0)
244bc108 1733 {
004d836a 1734 /* Compute address of nat collection bits. */
16461d7d 1735 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1736 CORE_ADDR bsp;
16461d7d
KB		 1737 CORE_ADDR nat_collection;
1738 int nat_bit;
1739 /* If our nat collection address is bigger than bsp, we have to get
1740 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1741 collection from the computed address. */
1742 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1743 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1744 if (nat_addr >= bsp)
004d836a
JJ		 1745 {
1746 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1747 nat_collection = extract_unsigned_integer (buf, 8);
1748 }
16461d7d
KB		 1749 else
1750 nat_collection = read_memory_integer (nat_addr, 8);
1751 nat_bit = (gr_addr >> 3) & 0x3f;
1752 natval = (nat_collection >> nat_bit) & 1;
1753 }
004d836a 1754
088568da 1755 store_unsigned_integer (valuep, register_size (gdbarch, regnum), natval);
244bc108
KB		 1756 }
1757 else if (regnum == IA64_IP_REGNUM)
1758 {
004d836a 1759 CORE_ADDR pc = 0;
4afcc598 1760 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1761
4afcc598 1762 if (addr != 0)
004d836a 1763 {
4afcc598
JJ		 1764 *lvalp = lval_memory;
1765 *addrp = addr;
088568da 1766 read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1767 pc = extract_unsigned_integer (buf, 8);
1768 }
4afcc598 1769 else if (cache->frameless)
004d836a 1770 {
4afcc598
JJ		 1771 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1772 pc = extract_unsigned_integer (buf, 8);
244bc108 1773 }
004d836a
JJ		 1774 pc &= ~0xf;
1775 store_unsigned_integer (valuep, 8, pc);
244bc108 1776 }
004d836a 1777 else if (regnum == IA64_PSR_REGNUM)
244bc108 1778 {
4afcc598
JJ		 1779 /* We don't know how to get the complete previous PSR, but we need it for
1780 the slot information when we unwind the pc (pc is formed of IP register
1781 plus slot information from PSR). To get the previous slot information,
1782 we mask it off the return address. */
004d836a
JJ		 1783 ULONGEST slot_num = 0;
1784 CORE_ADDR pc= 0;
1785 CORE_ADDR psr = 0;
4afcc598 1786 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1787
1788 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1789 psr = extract_unsigned_integer (buf, 8);
1790
4afcc598 1791 if (addr != 0)
244bc108 1792 {
4afcc598
JJ		 1793 *lvalp = lval_memory;
1794 *addrp = addr;
088568da 1795 read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
004d836a 1796 pc = extract_unsigned_integer (buf, 8);
244bc108 1797 }
4afcc598 1798 else if (cache->frameless)
004d836a 1799 {
4afcc598
JJ		 1800 CORE_ADDR pc;
1801 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1802 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1803 }
1804 psr &= ~(3LL << 41);
1805 slot_num = pc & 0x3LL;
1806 psr |= (CORE_ADDR)slot_num << 41;
1807 store_unsigned_integer (valuep, 8, psr);
1808 }
4afcc598
JJ		 1809 else if (regnum == IA64_BR0_REGNUM)
1810 {
1811 CORE_ADDR br0 = 0;
1812 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1813 if (addr != 0)
1814 {
1815 *lvalp = lval_memory;
1816 *addrp = addr;
088568da 1817 read_memory (addr, buf, register_size (gdbarch, IA64_BR0_REGNUM));
4afcc598
JJ		 1818 br0 = extract_unsigned_integer (buf, 8);
1819 }
1820 store_unsigned_integer (valuep, 8, br0);
1821 }
004d836a
JJ		 1822 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1823 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1824 {
1825 CORE_ADDR addr = 0;
1826 if (regnum >= V32_REGNUM)
1827 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1828 addr = cache->saved_regs[regnum];
244bc108
KB		 1829 if (addr != 0)
1830 {
004d836a
JJ		 1831 *lvalp = lval_memory;
1832 *addrp = addr;
088568da 1833 read_memory (addr, valuep, register_size (gdbarch, regnum));
244bc108 1834 }
004d836a 1835 else if (cache->frameless)
244bc108 1836 {
004d836a
JJ		 1837 char r_valuep[MAX_REGISTER_SIZE];
1838 int r_optim;
1839 int r_realnum;
1840 enum lval_type r_lval;
1841 CORE_ADDR r_addr;
1842 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1843 CORE_ADDR addr = 0;
1844 if (regnum >= V32_REGNUM)
1845 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1846 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1847 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1848 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1849 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1850 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1851 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1852 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1853
1854 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1855 *lvalp = lval_memory;
1856 *addrp = addr;
088568da 1857 read_memory (addr, valuep, register_size (gdbarch, regnum));
244bc108 1858 }
16461d7d
KB		 1859 }
1860 else
1861 {
004d836a 1862 CORE_ADDR addr = 0;
3a854e23
KB		 1863 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1864 {
1865 /* Fetch floating point register rename base from current
004d836a
JJ		 1866 frame marker for this frame. */
1867 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1868
1869 /* Adjust the floating point register number to account for
004d836a 1870 register rotation. */
3a854e23
KB		 1871 regnum = IA64_FR32_REGNUM
1872 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1873 }
1874
004d836a
JJ		 1875 /* If we have stored a memory address, access the register. */
1876 addr = cache->saved_regs[regnum];
1877 if (addr != 0)
1878 {
1879 *lvalp = lval_memory;
1880 *addrp = addr;
088568da 1881 read_memory (addr, valuep, register_size (gdbarch, regnum));
004d836a
JJ		 1882 }
1883 /* Otherwise, punt and get the current value of the register. */
1884 else
1885 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1886 }
4afcc598
JJ		 1887
1888 if (gdbarch_debug >= 1)
1889 fprintf_unfiltered (gdb_stdlog,
78ced177 1890 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1891 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1892 ? ia64_register_names[regnum] : "r??"),
1893 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1894}
004d836a
JJ		 1895
1896static const struct frame_unwind ia64_frame_unwind =
1897{
1898 NORMAL_FRAME,
1899 &ia64_frame_this_id,
1900 &ia64_frame_prev_register
1901};
1902
1903static const struct frame_unwind *
1904ia64_frame_sniffer (struct frame_info *next_frame)
1905{
1906 return &ia64_frame_unwind;
1907}
1908
1909/* Signal trampolines. */
1910
1911static void
2685572f
UW		 1912ia64_sigtramp_frame_init_saved_regs (struct frame_info *next_frame,
1913 struct ia64_frame_cache *cache)
004d836a 1914{
2685572f
UW		 1915 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
1916
1917 if (tdep->sigcontext_register_address)
004d836a
JJ		 1918 {
1919 int regno;
1920
1921 cache->saved_regs[IA64_VRAP_REGNUM] =
2685572f 1922 tdep->sigcontext_register_address (cache->base, IA64_IP_REGNUM);
004d836a 1923 cache->saved_regs[IA64_CFM_REGNUM] =
2685572f 1924 tdep->sigcontext_register_address (cache->base, IA64_CFM_REGNUM);
004d836a 1925 cache->saved_regs[IA64_PSR_REGNUM] =
2685572f 1926 tdep->sigcontext_register_address (cache->base, IA64_PSR_REGNUM);
004d836a 1927 cache->saved_regs[IA64_BSP_REGNUM] =
2685572f 1928 tdep->sigcontext_register_address (cache->base, IA64_BSP_REGNUM);
004d836a 1929 cache->saved_regs[IA64_RNAT_REGNUM] =
2685572f 1930 tdep->sigcontext_register_address (cache->base, IA64_RNAT_REGNUM);
004d836a 1931 cache->saved_regs[IA64_CCV_REGNUM] =
2685572f 1932 tdep->sigcontext_register_address (cache->base, IA64_CCV_REGNUM);
004d836a 1933 cache->saved_regs[IA64_UNAT_REGNUM] =
2685572f 1934 tdep->sigcontext_register_address (cache->base, IA64_UNAT_REGNUM);
004d836a 1935 cache->saved_regs[IA64_FPSR_REGNUM] =
2685572f 1936 tdep->sigcontext_register_address (cache->base, IA64_FPSR_REGNUM);
004d836a 1937 cache->saved_regs[IA64_PFS_REGNUM] =
2685572f 1938 tdep->sigcontext_register_address (cache->base, IA64_PFS_REGNUM);
004d836a 1939 cache->saved_regs[IA64_LC_REGNUM] =
2685572f 1940 tdep->sigcontext_register_address (cache->base, IA64_LC_REGNUM);
004d836a 1941 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598 1942 cache->saved_regs[regno] =
2685572f 1943 tdep->sigcontext_register_address (cache->base, regno);
004d836a
JJ		 1944 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1945 cache->saved_regs[regno] =
2685572f 1946 tdep->sigcontext_register_address (cache->base, regno);
932644f0 1947 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a 1948 cache->saved_regs[regno] =
2685572f 1949 tdep->sigcontext_register_address (cache->base, regno);
004d836a
JJ		 1950 }
1951}
1952
1953static struct ia64_frame_cache *
1954ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1955{
1956 struct ia64_frame_cache *cache;
1957 CORE_ADDR addr;
1958 char buf[8];
1959 int i;
1960
1961 if (*this_cache)
1962 return *this_cache;
1963
1964 cache = ia64_alloc_frame_cache ();
1965
1966 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1967 /* Note that frame size is hard-coded below. We cannot calculate it
1968 via prologue examination. */
1969 cache->base = extract_unsigned_integer (buf, 8) + 16;
1970
1971 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1972 cache->bsp = extract_unsigned_integer (buf, 8);
1973
1974 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1975 cache->cfm = extract_unsigned_integer (buf, 8);
1976 cache->sof = cache->cfm & 0x7f;
004d836a 1977
2685572f 1978 ia64_sigtramp_frame_init_saved_regs (next_frame, cache);
004d836a
JJ		 1979
1980 *this_cache = cache;
1981 return cache;
1982}
1983
1984static void
1985ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1986 void **this_cache, struct frame_id *this_id)
1987{
1988 struct ia64_frame_cache *cache =
1989 ia64_sigtramp_frame_cache (next_frame, this_cache);
1990
4afcc598
JJ		 1991 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1992 if (gdbarch_debug >= 1)
1993 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1994 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1995 paddr_nz (this_id->code_addr),
1996 paddr_nz (this_id->stack_addr),
1997 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1998}
1999
2000static void
2001ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
2002 void **this_cache,
2003 int regnum, int *optimizedp,
2004 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2005 int *realnump, gdb_byte *valuep)
004d836a 2006{
4afcc598
JJ		 2007 char dummy_valp[MAX_REGISTER_SIZE];
2008 char buf[MAX_REGISTER_SIZE];
2009
088568da 2010 struct gdbarch *gdbarch = get_frame_arch (next_frame);
4afcc598
JJ		 2011 struct ia64_frame_cache *cache =
2012 ia64_sigtramp_frame_cache (next_frame, this_cache);
2013
2014 gdb_assert (regnum >= 0);
2015
2016 if (!target_has_registers)
8a3fe4f8 2017 error (_("No registers."));
4afcc598
JJ		 2018
2019 *optimizedp = 0;
2020 *addrp = 0;
2021 *lvalp = not_lval;
2022 *realnump = -1;
2023
2024 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2025 when valuep is not supplied. */
2026 if (!valuep)
2027 valuep = dummy_valp;
2028
088568da 2029 memset (valuep, 0, register_size (gdbarch, regnum));
4afcc598
JJ		 2030
2031 if (regnum == IA64_IP_REGNUM)
2032 {
2033 CORE_ADDR pc = 0;
2034 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2035
2036 if (addr != 0)
2037 {
2038 *lvalp = lval_memory;
2039 *addrp = addr;
088568da 2040 read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
4afcc598
JJ		 2041 pc = extract_unsigned_integer (buf, 8);
2042 }
2043 pc &= ~0xf;
2044 store_unsigned_integer (valuep, 8, pc);
2045 }
2046 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2047 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2048 {
2049 CORE_ADDR addr = 0;
2050 if (regnum >= V32_REGNUM)
2051 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2052 addr = cache->saved_regs[regnum];
2053 if (addr != 0)
2054 {
2055 *lvalp = lval_memory;
2056 *addrp = addr;
088568da 2057 read_memory (addr, valuep, register_size (gdbarch, regnum));
4afcc598
JJ		 2058 }
2059 }
2060 else
2061 {
2062 /* All other registers not listed above. */
2063 CORE_ADDR addr = cache->saved_regs[regnum];
2064 if (addr != 0)
2065 {
2066 *lvalp = lval_memory;
2067 *addrp = addr;
088568da 2068 read_memory (addr, valuep, register_size (gdbarch, regnum));
4afcc598
JJ		 2069 }
2070 }
004d836a 2071
4afcc598
JJ		 2072 if (gdbarch_debug >= 1)
2073 fprintf_unfiltered (gdb_stdlog,
78ced177 2074 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2075 (regnum < IA64_GR32_REGNUM
2076 || (regnum > IA64_GR127_REGNUM
2077 && regnum < LAST_PSEUDO_REGNUM))
2078 ? ia64_register_names[regnum]
2079 : (regnum < LAST_PSEUDO_REGNUM
2080 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2081 : "OUT_OF_RANGE"),
78ced177 2082 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2083}
2084
2085static const struct frame_unwind ia64_sigtramp_frame_unwind =
2086{
2087 SIGTRAMP_FRAME,
2088 ia64_sigtramp_frame_this_id,
2089 ia64_sigtramp_frame_prev_register
2090};
2091
2092static const struct frame_unwind *
2093ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2094{
74174d2e
UW		 2095 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
2096 if (tdep->pc_in_sigtramp)
2097 {
2098 CORE_ADDR pc = frame_pc_unwind (next_frame);
004d836a 2099
74174d2e
UW		 2100 if (tdep->pc_in_sigtramp (pc))
2101 return &ia64_sigtramp_frame_unwind;
2102 }
004d836a
JJ		 2103
2104 return NULL;
2105}
2106\f
2107
2108static CORE_ADDR
2109ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2110{
2111 struct ia64_frame_cache *cache =
2112 ia64_frame_cache (next_frame, this_cache);
2113
2114 return cache->base;
2115}
2116
2117static const struct frame_base ia64_frame_base =
2118{
2119 &ia64_frame_unwind,
2120 ia64_frame_base_address,
2121 ia64_frame_base_address,
2122 ia64_frame_base_address
2123};
16461d7d 2124
968d1cb4
JJ		 2125#ifdef HAVE_LIBUNWIND_IA64_H
2126
2127struct ia64_unwind_table_entry
2128 {
2129 unw_word_t start_offset;
2130 unw_word_t end_offset;
2131 unw_word_t info_offset;
2132 };
2133
2134static __inline__ uint64_t
2135ia64_rse_slot_num (uint64_t addr)
2136{
2137 return (addr >> 3) & 0x3f;
2138}
2139
2140/* Skip over a designated number of registers in the backing
2141 store, remembering every 64th position is for NAT. */
2142static __inline__ uint64_t
2143ia64_rse_skip_regs (uint64_t addr, long num_regs)
2144{
2145 long delta = ia64_rse_slot_num(addr) + num_regs;
2146
2147 if (num_regs < 0)
2148 delta -= 0x3e;
2149 return addr + ((num_regs + delta/0x3f) << 3);
2150}
2151
2152/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2153 number to a libunwind register number. */
2154static int
2155ia64_gdb2uw_regnum (int regnum)
2156{
2157 if (regnum == sp_regnum)
2158 return UNW_IA64_SP;
2159 else if (regnum == IA64_BSP_REGNUM)
2160 return UNW_IA64_BSP;
2161 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2162 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2163 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2164 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2165 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2166 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2167 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2168 return -1;
2169 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2170 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2171 else if (regnum == IA64_PR_REGNUM)
2172 return UNW_IA64_PR;
2173 else if (regnum == IA64_IP_REGNUM)
2174 return UNW_REG_IP;
2175 else if (regnum == IA64_CFM_REGNUM)
2176 return UNW_IA64_CFM;
2177 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2178 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2179 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2180 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2181 else
2182 return -1;
2183}
2184
2185/* Gdb libunwind-frame callback function to convert from a libunwind register
2186 number to a ia64 gdb register number. */
2187static int
2188ia64_uw2gdb_regnum (int uw_regnum)
2189{
2190 if (uw_regnum == UNW_IA64_SP)
2191 return sp_regnum;
2192 else if (uw_regnum == UNW_IA64_BSP)
2193 return IA64_BSP_REGNUM;
2194 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2195 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2196 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2197 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2198 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2199 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2200 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2201 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2202 else if (uw_regnum == UNW_IA64_PR)
2203 return IA64_PR_REGNUM;
2204 else if (uw_regnum == UNW_REG_IP)
2205 return IA64_IP_REGNUM;
2206 else if (uw_regnum == UNW_IA64_CFM)
2207 return IA64_CFM_REGNUM;
2208 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2209 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2210 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2211 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2212 else
2213 return -1;
2214}
2215
2216/* Gdb libunwind-frame callback function to reveal if register is a float
2217 register or not. */
2218static int
2219ia64_is_fpreg (int uw_regnum)
2220{
2221 return unw_is_fpreg (uw_regnum);
2222}
2223
2224/* Libunwind callback accessor function for general registers. */
2225static int
2226ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2227 int write, void *arg)
2228{
2229 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2230 unw_word_t bsp, sof, sol, cfm, psr, ip;
2231 struct frame_info *next_frame = arg;
2232 long new_sof, old_sof;
2233 char buf[MAX_REGISTER_SIZE];
2234
45ecac4b
UW		 2235 /* We never call any libunwind routines that need to write registers. */
2236 gdb_assert (!write);
968d1cb4 2237
45ecac4b 2238 switch (uw_regnum)
968d1cb4 2239 {
45ecac4b
UW		 2240 case UNW_REG_IP:
2241 /* Libunwind expects to see the pc value which means the slot number
2242 from the psr must be merged with the ip word address. */
2243 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2244 ip = extract_unsigned_integer (buf, 8);
2245 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2246 psr = extract_unsigned_integer (buf, 8);
2247 *val = ip | ((psr >> 41) & 0x3);
2248 break;
2249
2250 case UNW_IA64_AR_BSP:
2251 /* Libunwind expects to see the beginning of the current register
2252 frame so we must account for the fact that ptrace() will return a value
2253 for bsp that points *after* the current register frame. */
2254 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2255 bsp = extract_unsigned_integer (buf, 8);
2256 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2257 cfm = extract_unsigned_integer (buf, 8);
2258 sof = (cfm & 0x7f);
2259 *val = ia64_rse_skip_regs (bsp, -sof);
2260 break;
968d1cb4 2261
45ecac4b
UW		 2262 case UNW_IA64_AR_BSPSTORE:
2263 /* Libunwind wants bspstore to be after the current register frame.
2264 This is what ptrace() and gdb treats as the regular bsp value. */
2265 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2266 *val = extract_unsigned_integer (buf, 8);
2267 break;
2268
2269 default:
2270 /* For all other registers, just unwind the value directly. */
2271 frame_unwind_register (next_frame, regnum, buf);
2272 *val = extract_unsigned_integer (buf, 8);
2273 break;
968d1cb4 2274 }
45ecac4b
UW		 2275
2276 if (gdbarch_debug >= 1)
2277 fprintf_unfiltered (gdb_stdlog,
2278 " access_reg: from cache: %4s=0x%s\n",
2279 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2280 ? ia64_register_names[regnum] : "r??"),
2281 paddr_nz (*val));
968d1cb4
JJ		 2282 return 0;
2283}
2284
2285/* Libunwind callback accessor function for floating-point registers. */
2286static int
2287ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2288 int write, void *arg)
2289{
2290 int regnum = ia64_uw2gdb_regnum (uw_regnum);
45ecac4b 2291 struct frame_info *next_frame = arg;
968d1cb4 2292
45ecac4b
UW		 2293 /* We never call any libunwind routines that need to write registers. */
2294 gdb_assert (!write);
2295
2296 frame_unwind_register (next_frame, regnum, (char *) val);
2297
968d1cb4
JJ		 2298 return 0;
2299}
2300
c5a27d9c
JJ		 2301/* Libunwind callback accessor function for top-level rse registers. */
2302static int
2303ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2304 int write, void *arg)
2305{
2306 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2307 unw_word_t bsp, sof, sol, cfm, psr, ip;
45ecac4b 2308 struct regcache *regcache = arg;
c5a27d9c 2309 long new_sof, old_sof;
45ecac4b 2310 char buf[MAX_REGISTER_SIZE];
c5a27d9c 2311
45ecac4b
UW		 2312 /* We never call any libunwind routines that need to write registers. */
2313 gdb_assert (!write);
c5a27d9c 2314
45ecac4b 2315 switch (uw_regnum)
c5a27d9c 2316 {
45ecac4b
UW		 2317 case UNW_REG_IP:
2318 /* Libunwind expects to see the pc value which means the slot number
2319 from the psr must be merged with the ip word address. */
2320 regcache_cooked_read (regcache, IA64_IP_REGNUM, buf);
2321 ip = extract_unsigned_integer (buf, 8);
2322 regcache_cooked_read (regcache, IA64_PSR_REGNUM, buf);
2323 psr = extract_unsigned_integer (buf, 8);
2324 *val = ip | ((psr >> 41) & 0x3);
2325 break;
c5a27d9c 2326
45ecac4b
UW		 2327 case UNW_IA64_AR_BSP:
2328 /* Libunwind expects to see the beginning of the current register
2329 frame so we must account for the fact that ptrace() will return a value
2330 for bsp that points *after* the current register frame. */
2331 regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2332 bsp = extract_unsigned_integer (buf, 8);
2333 regcache_cooked_read (regcache, IA64_CFM_REGNUM, buf);
2334 cfm = extract_unsigned_integer (buf, 8);
2335 sof = (cfm & 0x7f);
2336 *val = ia64_rse_skip_regs (bsp, -sof);
2337 break;
c5a27d9c 2338
45ecac4b
UW		 2339 case UNW_IA64_AR_BSPSTORE:
2340 /* Libunwind wants bspstore to be after the current register frame.
2341 This is what ptrace() and gdb treats as the regular bsp value. */
2342 regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2343 *val = extract_unsigned_integer (buf, 8);
2344 break;
c5a27d9c 2345
45ecac4b
UW		 2346 default:
2347 /* For all other registers, just unwind the value directly. */
2348 regcache_cooked_read (regcache, regnum, buf);
2349 *val = extract_unsigned_integer (buf, 8);
2350 break;
c5a27d9c
JJ		 2351 }
2352
2353 if (gdbarch_debug >= 1)
2354 fprintf_unfiltered (gdb_stdlog,
2355 " access_rse_reg: from cache: %4s=0x%s\n",
2356 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2357 ? ia64_register_names[regnum] : "r??"),
2358 paddr_nz (*val));
2359
2360 return 0;
2361}
2362
45ecac4b
UW		 2363/* Libunwind callback accessor function for top-level fp registers. */
2364static int
2365ia64_access_rse_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2366 unw_fpreg_t *val, int write, void *arg)
2367{
2368 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2369 struct regcache *regcache = arg;
2370
2371 /* We never call any libunwind routines that need to write registers. */
2372 gdb_assert (!write);
2373
2374 regcache_cooked_read (regcache, regnum, (char *) val);
2375
2376 return 0;
2377}
2378
968d1cb4
JJ		 2379/* Libunwind callback accessor function for accessing memory. */
2380static int
2381ia64_access_mem (unw_addr_space_t as,
2382 unw_word_t addr, unw_word_t *val,
2383 int write, void *arg)
2384{
c5a27d9c
JJ		 2385 if (addr - KERNEL_START < ktab_size)
2386 {
2387 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2388 + (addr - KERNEL_START));
2389
2390 if (write)
2391 *laddr = *val;
2392 else
2393 *val = *laddr;
2394 return 0;
2395 }
2396
968d1cb4
JJ		 2397 /* XXX do we need to normalize byte-order here? */
2398 if (write)
2399 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2400 else
2401 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2402}
2403
2404/* Call low-level function to access the kernel unwind table. */
13547ab6
DJ		 2405static LONGEST
2406getunwind_table (gdb_byte **buf_p)
968d1cb4
JJ		 2407{
2408 LONGEST x;
c5a27d9c 2409
10d6c8cd
DJ		 2410 /* FIXME drow/2005-09-10: This code used to call
2411 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2412 for the currently running ia64-linux kernel. That data should
2413 come from the core file and be accessed via the auxv vector; if
2414 we want to preserve fall back to the running kernel's table, then
2415 we should find a way to override the corefile layer's
2416 xfer_partial method. */
968d1cb4 2417
13547ab6
DJ		 2418 x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2419 NULL, buf_p);
2420
2421 return x;
968d1cb4 2422}
10d6c8cd 2423
968d1cb4
JJ		 2424/* Get the kernel unwind table. */
2425static int
2426get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2427{
c5a27d9c 2428 static struct ia64_table_entry *etab;
968d1cb4 2429
c5a27d9c 2430 if (!ktab)
968d1cb4 2431 {
13547ab6 2432 gdb_byte *ktab_buf;
eeec829c 2433 LONGEST size;
13547ab6 2434
eeec829c
DJ		 2435 size = getunwind_table (&ktab_buf);
2436 if (size <= 0)
13547ab6 2437 return -UNW_ENOINFO;
eeec829c
DJ		 2438
2439 ktab = (struct ia64_table_entry *) ktab_buf;
2440 ktab_size = size;
13547ab6 2441
968d1cb4 2442 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2443 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2444 }
2445
2446 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2447 return -UNW_ENOINFO;
2448
2449 di->format = UNW_INFO_FORMAT_TABLE;
2450 di->gp = 0;
2451 di->start_ip = ktab[0].start_offset;
2452 di->end_ip = etab[-1].end_offset;
2453 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2454 di->u.ti.segbase = 0;
2455 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2456 di->u.ti.table_data = (unw_word_t *) ktab;
2457
2458 if (gdbarch_debug >= 1)
2459 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2460 "segbase=0x%s, length=%s, gp=0x%s\n",
2461 (char *) di->u.ti.name_ptr,
2462 paddr_nz (di->u.ti.segbase),
2463 paddr_u (di->u.ti.table_len),
2464 paddr_nz (di->gp));
968d1cb4
JJ		 2465 return 0;
2466}
2467
2468/* Find the unwind table entry for a specified address. */
2469static int
2470ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2471 unw_dyn_info_t *dip, void **buf)
2472{
2473 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2474 Elf_Internal_Ehdr *ehdr;
2475 unw_word_t segbase = 0;
2476 CORE_ADDR load_base;
2477 bfd *bfd;
2478 int i;
2479
2480 bfd = objfile->obfd;
2481
2482 ehdr = elf_tdata (bfd)->elf_header;
2483 phdr = elf_tdata (bfd)->phdr;
2484
2485 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2486
2487 for (i = 0; i < ehdr->e_phnum; ++i)
2488 {
2489 switch (phdr[i].p_type)
2490 {
2491 case PT_LOAD:
2492 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2493 < phdr[i].p_memsz)
2494 p_text = phdr + i;
2495 break;
2496
2497 case PT_IA_64_UNWIND:
2498 p_unwind = phdr + i;
2499 break;
2500
2501 default:
2502 break;
2503 }
2504 }
2505
c5a27d9c 2506 if (!p_text || !p_unwind)
968d1cb4
JJ		 2507 return -UNW_ENOINFO;
2508
c5a27d9c
JJ		 2509 /* Verify that the segment that contains the IP also contains
2510 the static unwind table. If not, we may be in the Linux kernel's
2511 DSO gate page in which case the unwind table is another segment.
2512 Otherwise, we are dealing with runtime-generated code, for which we
2513 have no info here. */
968d1cb4
JJ		 2514 segbase = p_text->p_vaddr + load_base;
2515
c5a27d9c
JJ		 2516 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2517 {
2518 int ok = 0;
2519 for (i = 0; i < ehdr->e_phnum; ++i)
2520 {
2521 if (phdr[i].p_type == PT_LOAD
2522 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2523 {
2524 ok = 1;
2525 /* Get the segbase from the section containing the
2526 libunwind table. */
2527 segbase = phdr[i].p_vaddr + load_base;
2528 }
2529 }
2530 if (!ok)
2531 return -UNW_ENOINFO;
2532 }
2533
2534 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2535 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2536 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2537 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2538 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2539 dip->u.rti.segbase = segbase;
2540 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2541 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2542
2543 return 0;
2544}
2545
2546/* Libunwind callback accessor function to acquire procedure unwind-info. */
2547static int
2548ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2549 int need_unwind_info, void *arg)
2550{
2551 struct obj_section *sec = find_pc_section (ip);
2552 unw_dyn_info_t di;
2553 int ret;
2554 void *buf = NULL;
2555
2556 if (!sec)
2557 {
2558 /* XXX This only works if the host and the target architecture are
2559 both ia64 and if the have (more or less) the same kernel
2560 version. */
2561 if (get_kernel_table (ip, &di) < 0)
2562 return -UNW_ENOINFO;
503ff15d
KB		 2563
2564 if (gdbarch_debug >= 1)
78ced177
JJ		 2565 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2566 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2567 "length=%s,data=0x%s)\n",
2568 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2569 paddr_nz (di.u.ti.segbase),
2570 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2571 paddr_nz (di.gp),
2572 paddr_u (di.u.ti.table_len),
2573 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2574 }
2575 else
2576 {
2577 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2578 if (ret < 0)
2579 return ret;
968d1cb4 2580
503ff15d 2581 if (gdbarch_debug >= 1)
78ced177
JJ		 2582 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2583 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2584 "length=%s,data=0x%s)\n",
2585 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2586 paddr_nz (di.u.rti.segbase),
2587 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2588 paddr_nz (di.gp),
2589 paddr_u (di.u.rti.table_len),
2590 paddr_nz (di.u.rti.table_data));
503ff15d 2591 }
968d1cb4 2592
503ff15d
KB		 2593 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2594 arg);
968d1cb4
JJ		 2595
2596 /* We no longer need the dyn info storage so free it. */
2597 xfree (buf);
2598
2599 return ret;
2600}
2601
2602/* Libunwind callback accessor function for cleanup. */
2603static void
2604ia64_put_unwind_info (unw_addr_space_t as,
2605 unw_proc_info_t *pip, void *arg)
2606{
2607 /* Nothing required for now. */
2608}
2609
2610/* Libunwind callback accessor function to get head of the dynamic
2611 unwind-info registration list. */
2612static int
2613ia64_get_dyn_info_list (unw_addr_space_t as,
2614 unw_word_t *dilap, void *arg)
2615{
2616 struct obj_section *text_sec;
2617 struct objfile *objfile;
2618 unw_word_t ip, addr;
2619 unw_dyn_info_t di;
2620 int ret;
2621
2622 if (!libunwind_is_initialized ())
2623 return -UNW_ENOINFO;
2624
2625 for (objfile = object_files; objfile; objfile = objfile->next)
2626 {
2627 void *buf = NULL;
2628
2629 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2630 ip = text_sec->addr;
2631 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2632 if (ret >= 0)
2633 {
503ff15d 2634 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2635 /* We no longer need the dyn info storage so free it. */
2636 xfree (buf);
2637
2638 if (addr)
2639 {
2640 if (gdbarch_debug >= 1)
2641 fprintf_unfiltered (gdb_stdlog,
2642 "dynamic unwind table in objfile %s "
78ced177 2643 "at 0x%s (gp=0x%s)\n",
968d1cb4 2644 bfd_get_filename (objfile->obfd),
78ced177 2645 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2646 *dilap = addr;
2647 return 0;
2648 }
2649 }
2650 }
2651 return -UNW_ENOINFO;
2652}
2653
2654
2655/* Frame interface functions for libunwind. */
2656
2657static void
2658ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2659 struct frame_id *this_id)
968d1cb4
JJ		 2660{
2661 char buf[8];
2662 CORE_ADDR bsp;
2663 struct frame_id id;
c5a27d9c
JJ		 2664 CORE_ADDR prev_ip, addr;
2665 int realnum, optimized;
2666 enum lval_type lval;
2667
968d1cb4
JJ		 2668
2669 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2670 if (frame_id_eq (id, null_frame_id))
2671 {
2672 (*this_id) = null_frame_id;
2673 return;
2674 }
968d1cb4 2675
c5a27d9c
JJ		 2676 /* We must add the bsp as the special address for frame comparison
2677 purposes. */
968d1cb4
JJ		 2678 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2679 bsp = extract_unsigned_integer (buf, 8);
2680
c5a27d9c
JJ		 2681 /* If the previous frame pc value is 0, then we are at the end of the stack
2682 and don't want to unwind past this frame. We return a null frame_id to
2683 indicate this. */
2684 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2685 &optimized, &lval, &addr, &realnum, buf);
2686 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2687
2688 if (prev_ip != 0)
2689 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2690 else
2691 (*this_id) = null_frame_id;
968d1cb4
JJ		 2692
2693 if (gdbarch_debug >= 1)
2694 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2695 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2696 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2697 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2698}
2699
2700static void
2701ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2702 void **this_cache,
2703 int regnum, int *optimizedp,
2704 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2705 int *realnump, gdb_byte *valuep)
968d1cb4
JJ		 2706{
2707 int reg = regnum;
2708
088568da 2709 struct gdbarch *gdbarch = get_frame_arch (next_frame);
968d1cb4
JJ		 2710 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2711 reg = IA64_PR_REGNUM;
2712 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2713 reg = IA64_UNAT_REGNUM;
2714
2715 /* Let libunwind do most of the work. */
2716 libunwind_frame_prev_register (next_frame, this_cache, reg,
2717 optimizedp, lvalp, addrp, realnump, valuep);
2718
6672f2ae
AS		 2719 /* No more to do if the value is not supposed to be supplied. */
2720 if (!valuep)
2721 return;
2722
968d1cb4
JJ		 2723 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2724 {
2725 ULONGEST prN_val;
2726
2727 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2728 {
2729 int rrb_pr = 0;
2730 ULONGEST cfm;
2731 unsigned char buf[MAX_REGISTER_SIZE];
2732
2733 /* Fetch predicate register rename base from current frame
2734 marker for this frame. */
2735 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2736 cfm = extract_unsigned_integer (buf, 8);
2737 rrb_pr = (cfm >> 32) & 0x3f;
2738
2739 /* Adjust the register number to account for register rotation. */
2740 regnum = VP16_REGNUM
2741 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2742 }
2743 prN_val = extract_bit_field ((unsigned char *) valuep,
2744 regnum - VP0_REGNUM, 1);
088568da 2745 store_unsigned_integer (valuep, register_size (gdbarch, regnum), prN_val);
968d1cb4
JJ		 2746 }
2747 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2748 {
2749 ULONGEST unatN_val;
2750
2751 unatN_val = extract_bit_field ((unsigned char *) valuep,
2752 regnum - IA64_NAT0_REGNUM, 1);
088568da 2753 store_unsigned_integer (valuep, register_size (gdbarch, regnum),
968d1cb4
JJ		 2754 unatN_val);
2755 }
2756 else if (regnum == IA64_BSP_REGNUM)
2757 {
2758 char cfm_valuep[MAX_REGISTER_SIZE];
2759 int cfm_optim;
2760 int cfm_realnum;
2761 enum lval_type cfm_lval;
2762 CORE_ADDR cfm_addr;
2763 CORE_ADDR bsp, prev_cfm, prev_bsp;
2764
2765 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2766 This corresponds to what the hardware bsp register will be if we pop the frame
2767 back which is why we might have been called. We know that libunwind will pass us back
2768 the beginning of the current frame so we should just add sof to it. */
2769 prev_bsp = extract_unsigned_integer (valuep, 8);
2770 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2771 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2772 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2773 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2774
088568da 2775 store_unsigned_integer (valuep, register_size (gdbarch, regnum),
968d1cb4
JJ		 2776 prev_bsp);
2777 }
2778
2779 if (gdbarch_debug >= 1)
2780 fprintf_unfiltered (gdb_stdlog,
78ced177 2781 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2782 (regnum < IA64_GR32_REGNUM
2783 || (regnum > IA64_GR127_REGNUM
2784 && regnum < LAST_PSEUDO_REGNUM))
2785 ? ia64_register_names[regnum]
2786 : (regnum < LAST_PSEUDO_REGNUM
2787 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2788 : "OUT_OF_RANGE"),
78ced177 2789 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2790}
2791
2792static const struct frame_unwind ia64_libunwind_frame_unwind =
2793{
2794 NORMAL_FRAME,
2795 ia64_libunwind_frame_this_id,
272dfcfd
AS		 2796 ia64_libunwind_frame_prev_register,
2797 NULL,
2798 NULL,
2799 NULL,
2800 libunwind_frame_dealloc_cache
968d1cb4
JJ		 2801};
2802
2803static const struct frame_unwind *
2804ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2805{
2806 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2807 return &ia64_libunwind_frame_unwind;
2808
2809 return NULL;
2810}
2811
c5a27d9c
JJ		 2812static void
2813ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2814 struct frame_id *this_id)
2815{
2816 char buf[8];
2817 CORE_ADDR bsp;
2818 struct frame_id id;
2819 CORE_ADDR prev_ip;
2820
2821 libunwind_frame_this_id (next_frame, this_cache, &id);
2822 if (frame_id_eq (id, null_frame_id))
2823 {
2824 (*this_id) = null_frame_id;
2825 return;
2826 }
2827
2828 /* We must add the bsp as the special address for frame comparison
2829 purposes. */
2830 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2831 bsp = extract_unsigned_integer (buf, 8);
2832
2833 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2834 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2835
2836 if (gdbarch_debug >= 1)
2837 fprintf_unfiltered (gdb_stdlog,
2838 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2839 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2840 paddr_nz (bsp), next_frame);
2841}
2842
2843static void
2844ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2845 void **this_cache,
2846 int regnum, int *optimizedp,
2847 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2848 int *realnump, gdb_byte *valuep)
c5a27d9c
JJ		 2849
2850{
f1b4b38e 2851 gdb_byte buf[8];
c5a27d9c
JJ		 2852 CORE_ADDR prev_ip, addr;
2853 int realnum, optimized;
2854 enum lval_type lval;
2855
2856
2857 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2858 method of getting previous registers. */
2859 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2860 &optimized, &lval, &addr, &realnum, buf);
2861 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2862
2863 if (prev_ip == 0)
2864 {
2865 void *tmp_cache = NULL;
2866 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2867 addrp, realnump, valuep);
2868 }
2869 else
2870 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2871 addrp, realnump, valuep);
2872}
2873
2874static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2875{
2876 SIGTRAMP_FRAME,
2877 ia64_libunwind_sigtramp_frame_this_id,
2878 ia64_libunwind_sigtramp_frame_prev_register
2879};
2880
2881static const struct frame_unwind *
2882ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2883{
2884 if (libunwind_is_initialized ())
2885 {
2886 if (libunwind_sigtramp_frame_sniffer (next_frame))
2887 return &ia64_libunwind_sigtramp_frame_unwind;
2888 return NULL;
2889 }
2890 else
2891 return ia64_sigtramp_frame_sniffer (next_frame);
2892}
2893
968d1cb4
JJ		 2894/* Set of libunwind callback acccessor functions. */
2895static unw_accessors_t ia64_unw_accessors =
2896{
2897 ia64_find_proc_info_x,
2898 ia64_put_unwind_info,
2899 ia64_get_dyn_info_list,
2900 ia64_access_mem,
2901 ia64_access_reg,
2902 ia64_access_fpreg,
2903 /* resume */
2904 /* get_proc_name */
2905};
2906
c5a27d9c
JJ		 2907/* Set of special libunwind callback acccessor functions specific for accessing
2908 the rse registers. At the top of the stack, we want libunwind to figure out
2909 how to read r32 - r127. Though usually they are found sequentially in memory
2910 starting from $bof, this is not always true. */
2911static unw_accessors_t ia64_unw_rse_accessors =
2912{
2913 ia64_find_proc_info_x,
2914 ia64_put_unwind_info,
2915 ia64_get_dyn_info_list,
2916 ia64_access_mem,
2917 ia64_access_rse_reg,
45ecac4b 2918 ia64_access_rse_fpreg,
c5a27d9c
JJ		 2919 /* resume */
2920 /* get_proc_name */
2921};
2922
968d1cb4
JJ		 2923/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2924static struct libunwind_descr ia64_libunwind_descr =
2925{
2926 ia64_gdb2uw_regnum,
2927 ia64_uw2gdb_regnum,
2928 ia64_is_fpreg,
2929 &ia64_unw_accessors,
c5a27d9c 2930 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2931};
2932
2933#endif /* HAVE_LIBUNWIND_IA64_H */
2934
4c8b6ae0
UW		 2935static int
2936ia64_use_struct_convention (struct type *type)
16461d7d 2937{
64a5b29c
KB		 2938 struct type *float_elt_type;
2939
4c8b6ae0
UW		 2940 /* Don't use the struct convention for anything but structure,
2941 union, or array types. */
2942 if (!(TYPE_CODE (type) == TYPE_CODE_STRUCT
2943 || TYPE_CODE (type) == TYPE_CODE_UNION
2944 || TYPE_CODE (type) == TYPE_CODE_ARRAY))
2945 return 0;
2946
64a5b29c
KB		 2947 /* HFAs are structures (or arrays) consisting entirely of floating
2948 point values of the same length. Up to 8 of these are returned
2949 in registers. Don't use the struct convention when this is the
004d836a 2950 case. */
64a5b29c
KB		 2951 float_elt_type = is_float_or_hfa_type (type);
2952 if (float_elt_type != NULL
2953 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2954 return 0;
2955
2956 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 2957 Don't use the struct convention for those either. */
16461d7d
KB		 2958 return TYPE_LENGTH (type) > 32;
2959}
2960
4c8b6ae0 2961static void
2d522557
AC		 2962ia64_extract_return_value (struct type *type, struct regcache *regcache,
2963 gdb_byte *valbuf)
16461d7d 2964{
64a5b29c
KB		 2965 struct type *float_elt_type;
2966
2967 float_elt_type = is_float_or_hfa_type (type);
2968 if (float_elt_type != NULL)
2969 {
004d836a 2970 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 2971 int offset = 0;
2972 int regnum = IA64_FR8_REGNUM;
2973 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2974
2975 while (n-- > 0)
2976 {
004d836a
JJ		 2977 regcache_cooked_read (regcache, regnum, from);
2978 convert_typed_floating (from, builtin_type_ia64_ext,
2979 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 2980 offset += TYPE_LENGTH (float_elt_type);
2981 regnum++;
2982 }
2983 }
16461d7d 2984 else
004d836a
JJ		 2985 {
2986 ULONGEST val;
2987 int offset = 0;
2988 int regnum = IA64_GR8_REGNUM;
7b9ee6a8
DJ		 2989 int reglen = TYPE_LENGTH (register_type (get_regcache_arch (regcache),
2990 IA64_GR8_REGNUM));
004d836a
JJ		 2991 int n = TYPE_LENGTH (type) / reglen;
2992 int m = TYPE_LENGTH (type) % reglen;
16461d7d 2993
004d836a
JJ		 2994 while (n-- > 0)
2995 {
2996 ULONGEST val;
2997 regcache_cooked_read_unsigned (regcache, regnum, &val);
2998 memcpy ((char *)valbuf + offset, &val, reglen);
2999 offset += reglen;
3000 regnum++;
3001 }
16461d7d 3002
004d836a
JJ		 3003 if (m)
3004 {
3005 regcache_cooked_read_unsigned (regcache, regnum, &val);
3006 memcpy ((char *)valbuf + offset, &val, m);
3007 }
3008 }
16461d7d
KB		 3009}
3010
4c8b6ae0
UW		 3011static void
3012ia64_store_return_value (struct type *type, struct regcache *regcache,
3013 const gdb_byte *valbuf)
3014{
3015 struct type *float_elt_type;
3016
3017 float_elt_type = is_float_or_hfa_type (type);
3018 if (float_elt_type != NULL)
3019 {
3020 char to[MAX_REGISTER_SIZE];
3021 int offset = 0;
3022 int regnum = IA64_FR8_REGNUM;
3023 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3024
3025 while (n-- > 0)
3026 {
3027 convert_typed_floating ((char *)valbuf + offset, float_elt_type,
3028 to, builtin_type_ia64_ext);
3029 regcache_cooked_write (regcache, regnum, to);
3030 offset += TYPE_LENGTH (float_elt_type);
3031 regnum++;
3032 }
3033 }
3034 else
3035 {
3036 ULONGEST val;
3037 int offset = 0;
3038 int regnum = IA64_GR8_REGNUM;
3039 int reglen = TYPE_LENGTH (register_type (get_regcache_arch (regcache),
3040 IA64_GR8_REGNUM));
3041 int n = TYPE_LENGTH (type) / reglen;
3042 int m = TYPE_LENGTH (type) % reglen;
3043
3044 while (n-- > 0)
3045 {
3046 ULONGEST val;
3047 memcpy (&val, (char *)valbuf + offset, reglen);
3048 regcache_cooked_write_unsigned (regcache, regnum, val);
3049 offset += reglen;
3050 regnum++;
3051 }
3052
3053 if (m)
3054 {
3055 memcpy (&val, (char *)valbuf + offset, m);
3056 regcache_cooked_write_unsigned (regcache, regnum, val);
3057 }
3058 }
3059}
3060
3061static enum return_value_convention
3062ia64_return_value (struct gdbarch *gdbarch, struct type *valtype,
3063 struct regcache *regcache, gdb_byte *readbuf,
3064 const gdb_byte *writebuf)
3065{
3066 int struct_return = ia64_use_struct_convention (valtype);
3067
3068 if (writebuf != NULL)
3069 {
3070 gdb_assert (!struct_return);
3071 ia64_store_return_value (valtype, regcache, writebuf);
3072 }
3073
3074 if (readbuf != NULL)
3075 {
3076 gdb_assert (!struct_return);
3077 ia64_extract_return_value (valtype, regcache, readbuf);
3078 }
3079
3080 if (struct_return)
3081 return RETURN_VALUE_STRUCT_CONVENTION;
3082 else
3083 return RETURN_VALUE_REGISTER_CONVENTION;
3084}
16461d7d 3085
64a5b29c
KB		 3086static int
3087is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3088{
3089 switch (TYPE_CODE (t))
3090 {
3091 case TYPE_CODE_FLT:
3092 if (*etp)
3093 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3094 else
3095 {
3096 *etp = t;
3097 return 1;
3098 }
3099 break;
3100 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3101 return
3102 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3103 etp);
64a5b29c
KB		 3104 break;
3105 case TYPE_CODE_STRUCT:
3106 {
3107 int i;
3108
3109 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3110 if (!is_float_or_hfa_type_recurse
3111 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3112 return 0;
3113 return 1;
3114 }
3115 break;
3116 default:
3117 return 0;
3118 break;
3119 }
3120}
3121
3122/* Determine if the given type is one of the floating point types or
3123 and HFA (which is a struct, array, or combination thereof whose
004d836a 3124 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3125
3126static struct type *
3127is_float_or_hfa_type (struct type *t)
3128{
3129 struct type *et = 0;
3130
3131 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3132}
3133
3134
98f96ba1
KB		 3135/* Return 1 if the alignment of T is such that the next even slot
3136 should be used. Return 0, if the next available slot should
3137 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3138 and Runtime manual). */
98f96ba1
KB		 3139
3140static int
3141slot_alignment_is_next_even (struct type *t)
3142{
3143 switch (TYPE_CODE (t))
3144 {
3145 case TYPE_CODE_INT:
3146 case TYPE_CODE_FLT:
3147 if (TYPE_LENGTH (t) > 8)
3148 return 1;
3149 else
3150 return 0;
3151 case TYPE_CODE_ARRAY:
3152 return
3153 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3154 case TYPE_CODE_STRUCT:
3155 {
3156 int i;
3157
3158 for (i = 0; i < TYPE_NFIELDS (t); i++)
3159 if (slot_alignment_is_next_even
3160 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3161 return 1;
3162 return 0;
3163 }
3164 default:
3165 return 0;
3166 }
3167}
3168
64a5b29c
KB		 3169/* Attempt to find (and return) the global pointer for the given
3170 function.
3171
3172 This is a rather nasty bit of code searchs for the .dynamic section
3173 in the objfile corresponding to the pc of the function we're trying
3174 to call. Once it finds the addresses at which the .dynamic section
3175 lives in the child process, it scans the Elf64_Dyn entries for a
3176 DT_PLTGOT tag. If it finds one of these, the corresponding
3177 d_un.d_ptr value is the global pointer. */
3178
3179static CORE_ADDR
b33e8514 3180ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3181{
76d689a6 3182 struct obj_section *faddr_sect;
64a5b29c 3183
76d689a6
KB		 3184 faddr_sect = find_pc_section (faddr);
3185 if (faddr_sect != NULL)
64a5b29c
KB		 3186 {
3187 struct obj_section *osect;
3188
76d689a6 3189 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3190 {
3191 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3192 break;
3193 }
3194
76d689a6 3195 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3196 {
3197 CORE_ADDR addr;
3198
3199 addr = osect->addr;
3200 while (addr < osect->endaddr)
3201 {
3202 int status;
3203 LONGEST tag;
3204 char buf[8];
3205
3206 status = target_read_memory (addr, buf, sizeof (buf));
3207 if (status != 0)
3208 break;
3209 tag = extract_signed_integer (buf, sizeof (buf));
3210
3211 if (tag == DT_PLTGOT)
3212 {
3213 CORE_ADDR global_pointer;
3214
3215 status = target_read_memory (addr + 8, buf, sizeof (buf));
3216 if (status != 0)
3217 break;
7c0b4a20 3218 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3219
3220 /* The payoff... */
3221 return global_pointer;
3222 }
3223
3224 if (tag == DT_NULL)
3225 break;
3226
3227 addr += 16;
3228 }
3229 }
3230 }
3231 return 0;
3232}
3233
3234/* Given a function's address, attempt to find (and return) the
3235 corresponding (canonical) function descriptor. Return 0 if
004d836a 3236 not found. */
64a5b29c
KB		 3237static CORE_ADDR
3238find_extant_func_descr (CORE_ADDR faddr)
3239{
76d689a6 3240 struct obj_section *faddr_sect;
64a5b29c 3241
004d836a 3242 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3243 faddr_sect = find_pc_section (faddr);
3244 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3245 return faddr;
3246
76d689a6 3247 if (faddr_sect != NULL)
64a5b29c 3248 {
76d689a6
KB		 3249 struct obj_section *osect;
3250 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3251 {
3252 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3253 break;
3254 }
3255
76d689a6 3256 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3257 {
3258 CORE_ADDR addr;
3259
3260 addr = osect->addr;
3261 while (addr < osect->endaddr)
3262 {
3263 int status;
3264 LONGEST faddr2;
3265 char buf[8];
3266
3267 status = target_read_memory (addr, buf, sizeof (buf));
3268 if (status != 0)
3269 break;
3270 faddr2 = extract_signed_integer (buf, sizeof (buf));
3271
3272 if (faddr == faddr2)
3273 return addr;
3274
3275 addr += 16;
3276 }
3277 }
3278 }
3279 return 0;
3280}
3281
3282/* Attempt to find a function descriptor corresponding to the
3283 given address. If none is found, construct one on the
004d836a 3284 stack using the address at fdaptr. */
64a5b29c
KB		 3285
3286static CORE_ADDR
9c9acae0 3287find_func_descr (struct regcache *regcache, CORE_ADDR faddr, CORE_ADDR *fdaptr)
64a5b29c
KB		 3288{
3289 CORE_ADDR fdesc;
3290
3291 fdesc = find_extant_func_descr (faddr);
3292
3293 if (fdesc == 0)
3294 {
9c9acae0 3295 ULONGEST global_pointer;
64a5b29c
KB		 3296 char buf[16];
3297
3298 fdesc = *fdaptr;
3299 *fdaptr += 16;
3300
b33e8514 3301 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3302
3303 if (global_pointer == 0)
9c9acae0
UW		 3304 regcache_cooked_read_unsigned (regcache,
3305 IA64_GR1_REGNUM, &global_pointer);
64a5b29c 3306
fbd9dcd3
AC		 3307 store_unsigned_integer (buf, 8, faddr);
3308 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3309
3310 write_memory (fdesc, buf, 16);
3311 }
3312
3313 return fdesc;
3314}
16461d7d 3315
af8b88dd
JJ		 3316/* Use the following routine when printing out function pointers
3317 so the user can see the function address rather than just the
3318 function descriptor. */
3319static CORE_ADDR
e2d0e7eb
AC		 3320ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3321 struct target_ops *targ)
af8b88dd
JJ		 3322{
3323 struct obj_section *s;
3324
3325 s = find_pc_section (addr);
3326
3327 /* check if ADDR points to a function descriptor. */
3328 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3329 return read_memory_unsigned_integer (addr, 8);
3330
0d5de010
DJ		 3331 /* There are also descriptors embedded in vtables. */
3332 if (s)
3333 {
3334 struct minimal_symbol *minsym;
3335
3336 minsym = lookup_minimal_symbol_by_pc (addr);
3337
3338 if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3339 return read_memory_unsigned_integer (addr, 8);
3340 }
3341
af8b88dd
JJ		 3342 return addr;
3343}
3344
a78f21af 3345static CORE_ADDR
004d836a
JJ		 3346ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3347{
3348 return sp & ~0xfLL;
3349}
3350
3351static CORE_ADDR
7d9b040b 3352ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3353 struct regcache *regcache, CORE_ADDR bp_addr,
3354 int nargs, struct value **args, CORE_ADDR sp,
3355 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3356{
3357 int argno;
ea7c478f 3358 struct value *arg;
16461d7d
KB		 3359 struct type *type;
3360 int len, argoffset;
64a5b29c 3361 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3362 int floatreg;
9c9acae0
UW		 3363 ULONGEST bsp, cfm, pfs, new_bsp;
3364 CORE_ADDR funcdescaddr, pc, global_pointer;
7d9b040b 3365 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3366
3367 nslots = 0;
64a5b29c 3368 nfuncargs = 0;
004d836a 3369 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3370 for (argno = 0; argno < nargs; argno++)
3371 {
3372 arg = args[argno];
4991999e 3373 type = check_typedef (value_type (arg));
16461d7d
KB		 3374 len = TYPE_LENGTH (type);
3375
98f96ba1 3376 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3377 nslots++;
3378
64a5b29c
KB		 3379 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3380 nfuncargs++;
3381
16461d7d
KB		 3382 nslots += (len + 7) / 8;
3383 }
3384
004d836a 3385 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3386 rseslots = (nslots > 8) ? 8 : nslots;
3387 memslots = nslots - rseslots;
3388
004d836a 3389 /* Allocate a new RSE frame. */
9c9acae0 3390 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
16461d7d 3391
9c9acae0 3392 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
16461d7d 3393 new_bsp = rse_address_add (bsp, rseslots);
9c9acae0 3394 regcache_cooked_write_unsigned (regcache, IA64_BSP_REGNUM, new_bsp);
16461d7d 3395
9c9acae0 3396 regcache_cooked_read_unsigned (regcache, IA64_PFS_REGNUM, &pfs);
16461d7d
KB		 3397 pfs &= 0xc000000000000000LL;
3398 pfs |= (cfm & 0xffffffffffffLL);
9c9acae0 3399 regcache_cooked_write_unsigned (regcache, IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3400
3401 cfm &= 0xc000000000000000LL;
3402 cfm |= rseslots;
9c9acae0 3403 regcache_cooked_write_unsigned (regcache, IA64_CFM_REGNUM, cfm);
16461d7d 3404
64a5b29c
KB		 3405 /* We will attempt to find function descriptors in the .opd segment,
3406 but if we can't we'll construct them ourselves. That being the
004d836a 3407 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3408 funcdescaddr = sp - nfuncargs * 16;
3409 funcdescaddr &= ~0xfLL;
3410
3411 /* Adjust the stack pointer to it's new value. The calling conventions
3412 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3413 necessary for the memory slots and our function descriptors. */
64a5b29c 3414 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3415 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3416
64a5b29c
KB		 3417 /* Place the arguments where they belong. The arguments will be
3418 either placed in the RSE backing store or on the memory stack.
3419 In addition, floating point arguments or HFAs are placed in
004d836a 3420 floating point registers. */
16461d7d
KB		 3421 slotnum = 0;
3422 floatreg = IA64_FR8_REGNUM;
3423 for (argno = 0; argno < nargs; argno++)
3424 {
64a5b29c
KB		 3425 struct type *float_elt_type;
3426
16461d7d 3427 arg = args[argno];
4991999e 3428 type = check_typedef (value_type (arg));
16461d7d 3429 len = TYPE_LENGTH (type);
64a5b29c 3430
004d836a 3431 /* Special handling for function parameters. */
64a5b29c
KB		 3432 if (len == 8
3433 && TYPE_CODE (type) == TYPE_CODE_PTR
3434 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3435 {
3436 char val_buf[8];
9c9acae0 3437 ULONGEST faddr = extract_unsigned_integer (value_contents (arg), 8);
fbd9dcd3 3438 store_unsigned_integer (val_buf, 8,
9c9acae0 3439 find_func_descr (regcache, faddr,
fbd9dcd3 3440 &funcdescaddr));
64a5b29c
KB		 3441 if (slotnum < rseslots)
3442 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3443 else
3444 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3445 slotnum++;
3446 continue;
3447 }
3448
004d836a 3449 /* Normal slots. */
98f96ba1
KB		 3450
3451 /* Skip odd slot if necessary... */
3452 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3453 slotnum++;
98f96ba1 3454
16461d7d
KB		 3455 argoffset = 0;
3456 while (len > 0)
3457 {
3458 char val_buf[8];
3459
3460 memset (val_buf, 0, 8);
0fd88904 3461 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3462
3463 if (slotnum < rseslots)
3464 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3465 else
3466 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3467
3468 argoffset += 8;
3469 len -= 8;
3470 slotnum++;
3471 }
64a5b29c 3472
004d836a 3473 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3474 float_elt_type = is_float_or_hfa_type (type);
3475 if (float_elt_type != NULL)
3476 {
3477 argoffset = 0;
3478 len = TYPE_LENGTH (type);
3479 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3480 {
004d836a 3481 char to[MAX_REGISTER_SIZE];
0fd88904 3482 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3483 to, builtin_type_ia64_ext);
3484 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3485 floatreg++;
3486 argoffset += TYPE_LENGTH (float_elt_type);
3487 len -= TYPE_LENGTH (float_elt_type);
3488 }
16461d7d
KB		 3489 }
3490 }
3491
004d836a 3492 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3493 if (struct_return)
3494 {
004d836a 3495 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3496 }
3497
b33e8514 3498 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3499
004d836a 3500 if (global_pointer != 0)
9c9acae0 3501 regcache_cooked_write_unsigned (regcache, IA64_GR1_REGNUM, global_pointer);
a59fe496 3502
9c9acae0 3503 regcache_cooked_write_unsigned (regcache, IA64_BR0_REGNUM, bp_addr);
16461d7d 3504
9c9acae0 3505 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
16461d7d
KB		 3506
3507 return sp;
3508}
3509
004d836a
JJ		 3510static struct frame_id
3511ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3512{
004d836a 3513 char buf[8];
4afcc598 3514 CORE_ADDR sp, bsp;
004d836a
JJ		 3515
3516 frame_unwind_register (next_frame, sp_regnum, buf);
3517 sp = extract_unsigned_integer (buf, 8);
3518
4afcc598
JJ		 3519 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3520 bsp = extract_unsigned_integer (buf, 8);
3521
3522 if (gdbarch_debug >= 1)
3523 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3524 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3525 paddr_nz (frame_pc_unwind (next_frame)),
3526 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3527
3528 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3529}
3530
004d836a
JJ		 3531static CORE_ADDR
3532ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3533{
004d836a
JJ		 3534 char buf[8];
3535 CORE_ADDR ip, psr, pc;
3536
3537 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3538 ip = extract_unsigned_integer (buf, 8);
3539 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3540 psr = extract_unsigned_integer (buf, 8);
3541
3542 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3543 return pc;
16461d7d
KB		 3544}
3545
6926787d
AS		 3546static int
3547ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3548{
3549 info->bytes_per_line = SLOT_MULTIPLIER;
3550 return print_insn_ia64 (memaddr, info);
3551}
3552
16461d7d
KB		 3553static struct gdbarch *
3554ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3555{
3556 struct gdbarch *gdbarch;
244bc108 3557 struct gdbarch_tdep *tdep;
244bc108 3558
85bf2b91
JJ		 3559 /* If there is already a candidate, use it. */
3560 arches = gdbarch_list_lookup_by_info (arches, &info);
3561 if (arches != NULL)
3562 return arches->gdbarch;
16461d7d 3563
244bc108
KB		 3564 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3565 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3566
b33e8514 3567 tdep->sigcontext_register_address = 0;
74174d2e 3568 tdep->pc_in_sigtramp = 0;
698cb3f0 3569
5439edaa
AC		 3570 /* According to the ia64 specs, instructions that store long double
3571 floats in memory use a long-double format different than that
3572 used in the floating registers. The memory format matches the
3573 x86 extended float format which is 80 bits. An OS may choose to
3574 use this format (e.g. GNU/Linux) or choose to use a different
3575 format for storing long doubles (e.g. HPUX). In the latter case,
3576 the setting of the format may be moved/overridden in an
3577 OS-specific tdep file. */
8da61cc4 3578 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
32edc941 3579
16461d7d
KB		 3580 set_gdbarch_short_bit (gdbarch, 16);
3581 set_gdbarch_int_bit (gdbarch, 32);
3582 set_gdbarch_long_bit (gdbarch, 64);
3583 set_gdbarch_long_long_bit (gdbarch, 64);
3584 set_gdbarch_float_bit (gdbarch, 32);
3585 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3586 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3587 set_gdbarch_ptr_bit (gdbarch, 64);
3588
004d836a
JJ		 3589 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3590 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3591 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3592 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3593
3594 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a 3595 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3596
004d836a
JJ		 3597 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3598 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3599 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3600 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3601 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3602 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3603 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3604
004d836a 3605 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3606
4c8b6ae0 3607 set_gdbarch_return_value (gdbarch, ia64_return_value);
16461d7d
KB		 3608
3609 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3610 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3611 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3612 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3613 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3614
3615 /* Settings for calling functions in the inferior. */
8dd5115e 3616 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3617 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3618 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3619
004d836a 3620 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3621#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3622 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3623 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3624 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3625#else
3626 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3627#endif
004d836a
JJ		 3628 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3629 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3630
3631 /* Settings that should be unnecessary. */
3632 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3633
6926787d 3634 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3635 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3636
0d5de010
DJ		 3637 /* The virtual table contains 16-byte descriptors, not pointers to
3638 descriptors. */
3639 set_gdbarch_vtable_function_descriptors (gdbarch, 1);
3640
b33e8514
AS		 3641 /* Hook in ABI-specific overrides, if they have been registered. */
3642 gdbarch_init_osabi (info, gdbarch);
3643
16461d7d
KB		 3644 return gdbarch;
3645}
3646
a78f21af
AC		 3647extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3648
16461d7d
KB		 3649void
3650_initialize_ia64_tdep (void)
3651{
83acabca
DJ		 3652 /* Define the ia64 floating-point format to gdb. */
3653 builtin_type_ia64_ext =
3654 init_type (TYPE_CODE_FLT, 128 / 8,
3655 0, "builtin_type_ia64_ext", NULL);
3656 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = floatformats_ia64_ext;
3657
b33e8514 3658 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3659}
GDB Binutils - Deliverables
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