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2003-11-05 Michael Chastain <mec@shout.net>
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
CommitLineData
16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
51603483 3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
16461d7d
KB		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22#include "defs.h"
23#include "inferior.h"
24#include "symfile.h" /* for entry_point_address */
25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
16461d7d 40
698cb3f0
KB		 41/* Hook for determining the global pointer when calling functions in
42 the inferior under AIX. The initialization code in ia64-aix-nat.c
43 sets this hook to the address of a function which will find the
44 global pointer for a given address.
45
46 The generic code which uses the dynamic section in the inferior for
47 finding the global pointer is not of much use on AIX since the
48 values obtained from the inferior have not been relocated. */
49
50CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
51
52/* An enumeration of the different IA-64 instruction types. */
53
16461d7d
KB		 54typedef enum instruction_type
55{
56 A, /* Integer ALU ; I-unit or M-unit */
57 I, /* Non-ALU integer; I-unit */
58 M, /* Memory ; M-unit */
59 F, /* Floating-point ; F-unit */
60 B, /* Branch ; B-unit */
61 L, /* Extended (L+X) ; I-unit */
62 X, /* Extended (L+X) ; I-unit */
63 undefined /* undefined or reserved */
64} instruction_type;
65
66/* We represent IA-64 PC addresses as the value of the instruction
67 pointer or'd with some bit combination in the low nibble which
68 represents the slot number in the bundle addressed by the
69 instruction pointer. The problem is that the Linux kernel
70 multiplies its slot numbers (for exceptions) by one while the
71 disassembler multiplies its slot numbers by 6. In addition, I've
72 heard it said that the simulator uses 1 as the multiplier.
73
74 I've fixed the disassembler so that the bytes_per_line field will
75 be the slot multiplier. If bytes_per_line comes in as zero, it
76 is set to six (which is how it was set up initially). -- objdump
77 displays pretty disassembly dumps with this value. For our purposes,
78 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
79 never want to also display the raw bytes the way objdump does. */
80
81#define SLOT_MULTIPLIER 1
82
83/* Length in bytes of an instruction bundle */
84
85#define BUNDLE_LEN 16
86
d7fa2ae2 87/* FIXME: These extern declarations should go in ia64-tdep.h. */
244bc108 88extern CORE_ADDR ia64_linux_sigcontext_register_address (CORE_ADDR, int);
d7fa2ae2 89extern CORE_ADDR ia64_aix_sigcontext_register_address (CORE_ADDR, int);
244bc108 90
16461d7d
KB		 91static gdbarch_init_ftype ia64_gdbarch_init;
92
93static gdbarch_register_name_ftype ia64_register_name;
004d836a 94static gdbarch_register_type_ftype ia64_register_type;
16461d7d 95static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 96static gdbarch_skip_prologue_ftype ia64_skip_prologue;
004d836a
JJ		 97static gdbarch_extract_return_value_ftype ia64_extract_return_value;
98static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address;
16461d7d 99static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
64a5b29c 100static struct type *is_float_or_hfa_type (struct type *t);
16461d7d 101
004d836a
JJ		 102static struct type *builtin_type_ia64_ext;
103
104#define NUM_IA64_RAW_REGS 462
16461d7d 105
16461d7d
KB		 106static int sp_regnum = IA64_GR12_REGNUM;
107static int fp_regnum = IA64_VFP_REGNUM;
108static int lr_regnum = IA64_VRAP_REGNUM;
109
004d836a 110/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 111 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 112enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
113 V127_REGNUM = V32_REGNUM + 95,
114 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 115
116/* Array of register names; There should be ia64_num_regs strings in
117 the initializer. */
118
119static char *ia64_register_names[] =
120{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
16461d7d
KB		 136
137 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
138 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
139 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
140 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
141 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
142 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
143 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
144 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
145 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
146 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
147 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
148 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
149 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
150 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
151 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
152 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
153
004d836a
JJ		 154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
16461d7d
KB		 162
163 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
164
165 "vfp", "vrap",
166
167 "pr", "ip", "psr", "cfm",
168
169 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
170 "", "", "", "", "", "", "", "",
171 "rsc", "bsp", "bspstore", "rnat",
172 "", "fcr", "", "",
173 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
174 "ccv", "", "", "", "unat", "", "", "",
175 "fpsr", "", "", "", "itc",
176 "", "", "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "", "",
178 "pfs", "lc", "ec",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
185 "",
186 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
187 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
188 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
189 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
190 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
191 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
192 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
193 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
194 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
195 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
196 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
197 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
198 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
199 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
200 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
201 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 202
203 "bof",
204
205 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
206 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
207 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
208 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
209 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
210 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
211 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
212 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
213 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
214 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
215 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
216 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
217
218 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
219 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
220 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
221 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
222 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
223 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
224 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
225 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 226};
227
004d836a
JJ		 228struct ia64_frame_cache
229{
230 CORE_ADDR base; /* frame pointer base for frame */
231 CORE_ADDR pc; /* function start pc for frame */
232 CORE_ADDR saved_sp; /* stack pointer for frame */
233 CORE_ADDR bsp; /* points at r32 for the current frame */
234 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 235 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 236 int frameless;
237 int sof; /* Size of frame (decoded from cfm value) */
238 int sol; /* Size of locals (decoded from cfm value) */
239 int sor; /* Number of rotating registers. (decoded from cfm value) */
240 CORE_ADDR after_prologue;
241 /* Address of first instruction after the last
242 prologue instruction; Note that there may
243 be instructions from the function's body
244 intermingled with the prologue. */
245 int mem_stack_frame_size;
246 /* Size of the memory stack frame (may be zero),
247 or -1 if it has not been determined yet. */
248 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 249 for this frame. 0 if no register is being used
16461d7d 250 as the frame pointer. */
004d836a
JJ		 251
252 /* Saved registers. */
253 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
254
255};
244bc108
KB		 256
257struct gdbarch_tdep
258 {
244bc108
KB		 259 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
260 /* OS specific function which, given a frame address
261 and register number, returns the offset to the
262 given register from the start of the frame. */
698cb3f0 263 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
244bc108
KB		 264 };
265
698cb3f0
KB		 266#define SIGCONTEXT_REGISTER_ADDRESS \
267 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
268#define FIND_GLOBAL_POINTER \
269 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
16461d7d 270
004d836a
JJ		 271int
272ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
273 struct reggroup *group)
16461d7d 274{
004d836a
JJ		 275 int vector_p;
276 int float_p;
277 int raw_p;
278 if (group == all_reggroup)
279 return 1;
280 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
281 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
282 raw_p = regnum < NUM_IA64_RAW_REGS;
283 if (group == float_reggroup)
284 return float_p;
285 if (group == vector_reggroup)
286 return vector_p;
287 if (group == general_reggroup)
288 return (!vector_p && !float_p);
289 if (group == save_reggroup || group == restore_reggroup)
290 return raw_p;
291 return 0;
16461d7d
KB		 292}
293
004d836a
JJ		 294static const char *
295ia64_register_name (int reg)
16461d7d 296{
004d836a 297 return ia64_register_names[reg];
16461d7d
KB		 298}
299
004d836a
JJ		 300struct type *
301ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 302{
004d836a
JJ		 303 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
304 return builtin_type_ia64_ext;
305 else
306 return builtin_type_long;
16461d7d
KB		 307}
308
a78f21af 309static int
004d836a 310ia64_dwarf_reg_to_regnum (int reg)
16461d7d 311{
004d836a
JJ		 312 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
313 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
314 return reg;
16461d7d
KB		 315}
316
4afcc598
JJ		 317static int
318floatformat_valid (fmt, from)
319 const struct floatformat *fmt;
320 const char *from;
321{
322 return 1;
323}
324
16461d7d
KB		 325const struct floatformat floatformat_ia64_ext =
326{
327 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 328 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 329};
330
16461d7d 331
244bc108
KB		 332/* Read the given register from a sigcontext structure in the
333 specified frame. */
334
335static CORE_ADDR
336read_sigcontext_register (struct frame_info *frame, int regnum)
337{
338 CORE_ADDR regaddr;
339
340 if (frame == NULL)
8e65ff28
AC		 341 internal_error (__FILE__, __LINE__,
342 "read_sigcontext_register: NULL frame");
5a203e44 343 if (!(get_frame_type (frame) == SIGTRAMP_FRAME))
8e65ff28 344 internal_error (__FILE__, __LINE__,
5a203e44 345 "read_sigcontext_register: frame not a signal trampoline");
244bc108 346 if (SIGCONTEXT_REGISTER_ADDRESS == 0)
8e65ff28
AC		 347 internal_error (__FILE__, __LINE__,
348 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
244bc108 349
1e2330ba 350 regaddr = SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame), regnum);
244bc108 351 if (regaddr)
aa2a9a3c 352 return read_memory_integer (regaddr, register_size (current_gdbarch, regnum));
244bc108 353 else
8e65ff28
AC		 354 internal_error (__FILE__, __LINE__,
355 "read_sigcontext_register: Register %d not in struct sigcontext", regnum);
244bc108
KB		 356}
357
16461d7d
KB		 358/* Extract ``len'' bits from an instruction bundle starting at
359 bit ``from''. */
360
244bc108 361static long long
16461d7d
KB		 362extract_bit_field (char *bundle, int from, int len)
363{
364 long long result = 0LL;
365 int to = from + len;
366 int from_byte = from / 8;
367 int to_byte = to / 8;
368 unsigned char *b = (unsigned char *) bundle;
369 unsigned char c;
370 int lshift;
371 int i;
372
373 c = b[from_byte];
374 if (from_byte == to_byte)
375 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
376 result = c >> (from % 8);
377 lshift = 8 - (from % 8);
378
379 for (i = from_byte+1; i < to_byte; i++)
380 {
381 result |= ((long long) b[i]) << lshift;
382 lshift += 8;
383 }
384
385 if (from_byte < to_byte && (to % 8 != 0))
386 {
387 c = b[to_byte];
388 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
389 result |= ((long long) c) << lshift;
390 }
391
392 return result;
393}
394
395/* Replace the specified bits in an instruction bundle */
396
244bc108 397static void
16461d7d
KB		 398replace_bit_field (char *bundle, long long val, int from, int len)
399{
400 int to = from + len;
401 int from_byte = from / 8;
402 int to_byte = to / 8;
403 unsigned char *b = (unsigned char *) bundle;
404 unsigned char c;
405
406 if (from_byte == to_byte)
407 {
408 unsigned char left, right;
409 c = b[from_byte];
410 left = (c >> (to % 8)) << (to % 8);
411 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
412 c = (unsigned char) (val & 0xff);
413 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
414 c |= right | left;
415 b[from_byte] = c;
416 }
417 else
418 {
419 int i;
420 c = b[from_byte];
421 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
422 c = c | (val << (from % 8));
423 b[from_byte] = c;
424 val >>= 8 - from % 8;
425
426 for (i = from_byte+1; i < to_byte; i++)
427 {
428 c = val & 0xff;
429 val >>= 8;
430 b[i] = c;
431 }
432
433 if (to % 8 != 0)
434 {
435 unsigned char cv = (unsigned char) val;
436 c = b[to_byte];
437 c = c >> (to % 8) << (to % 8);
438 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
439 b[to_byte] = c;
440 }
441 }
442}
443
444/* Return the contents of slot N (for N = 0, 1, or 2) in
445 and instruction bundle */
446
244bc108 447static long long
2fc3ac7e 448slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 449{
450 return extract_bit_field (bundle, 5+41*slotnum, 41);
451}
452
453/* Store an instruction in an instruction bundle */
454
244bc108 455static void
2fc3ac7e 456replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 457{
458 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
459}
460
64a5b29c 461static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 462{
463 { M, I, I }, /* 00 */
464 { M, I, I }, /* 01 */
465 { M, I, I }, /* 02 */
466 { M, I, I }, /* 03 */
467 { M, L, X }, /* 04 */
468 { M, L, X }, /* 05 */
469 { undefined, undefined, undefined }, /* 06 */
470 { undefined, undefined, undefined }, /* 07 */
471 { M, M, I }, /* 08 */
472 { M, M, I }, /* 09 */
473 { M, M, I }, /* 0A */
474 { M, M, I }, /* 0B */
475 { M, F, I }, /* 0C */
476 { M, F, I }, /* 0D */
477 { M, M, F }, /* 0E */
478 { M, M, F }, /* 0F */
479 { M, I, B }, /* 10 */
480 { M, I, B }, /* 11 */
481 { M, B, B }, /* 12 */
482 { M, B, B }, /* 13 */
483 { undefined, undefined, undefined }, /* 14 */
484 { undefined, undefined, undefined }, /* 15 */
485 { B, B, B }, /* 16 */
486 { B, B, B }, /* 17 */
487 { M, M, B }, /* 18 */
488 { M, M, B }, /* 19 */
489 { undefined, undefined, undefined }, /* 1A */
490 { undefined, undefined, undefined }, /* 1B */
491 { M, F, B }, /* 1C */
492 { M, F, B }, /* 1D */
493 { undefined, undefined, undefined }, /* 1E */
494 { undefined, undefined, undefined }, /* 1F */
495};
496
497/* Fetch and (partially) decode an instruction at ADDR and return the
498 address of the next instruction to fetch. */
499
500static CORE_ADDR
501fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
502{
503 char bundle[BUNDLE_LEN];
504 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
505 long long template;
506 int val;
507
c26e1c2b
KB		 508 /* Warn about slot numbers greater than 2. We used to generate
509 an error here on the assumption that the user entered an invalid
510 address. But, sometimes GDB itself requests an invalid address.
511 This can (easily) happen when execution stops in a function for
512 which there are no symbols. The prologue scanner will attempt to
513 find the beginning of the function - if the nearest symbol
514 happens to not be aligned on a bundle boundary (16 bytes), the
515 resulting starting address will cause GDB to think that the slot
516 number is too large.
517
518 So we warn about it and set the slot number to zero. It is
519 not necessarily a fatal condition, particularly if debugging
520 at the assembly language level. */
16461d7d 521 if (slotnum > 2)
c26e1c2b
KB		 522 {
523 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
524 "Using slot 0 instead");
525 slotnum = 0;
526 }
16461d7d
KB		 527
528 addr &= ~0x0f;
529
530 val = target_read_memory (addr, bundle, BUNDLE_LEN);
531
532 if (val != 0)
533 return 0;
534
535 *instr = slotN_contents (bundle, slotnum);
536 template = extract_bit_field (bundle, 0, 5);
537 *it = template_encoding_table[(int)template][slotnum];
538
64a5b29c 539 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 540 addr += 16;
541 else
542 addr += (slotnum + 1) * SLOT_MULTIPLIER;
543
544 return addr;
545}
546
547/* There are 5 different break instructions (break.i, break.b,
548 break.m, break.f, and break.x), but they all have the same
549 encoding. (The five bit template in the low five bits of the
550 instruction bundle distinguishes one from another.)
551
552 The runtime architecture manual specifies that break instructions
553 used for debugging purposes must have the upper two bits of the 21
554 bit immediate set to a 0 and a 1 respectively. A breakpoint
555 instruction encodes the most significant bit of its 21 bit
556 immediate at bit 36 of the 41 bit instruction. The penultimate msb
557 is at bit 25 which leads to the pattern below.
558
559 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
560 it turns out that 0x80000 was used as the syscall break in the early
561 simulators. So I changed the pattern slightly to do "break.i 0x080001"
562 instead. But that didn't work either (I later found out that this
563 pattern was used by the simulator that I was using.) So I ended up
564 using the pattern seen below. */
565
566#if 0
aaab4dba 567#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 568#endif
aaab4dba 569#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 570
571static int
572ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
573{
574 char bundle[BUNDLE_LEN];
575 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
576 long long instr;
577 int val;
126fa72d 578 int template;
16461d7d
KB		 579
580 if (slotnum > 2)
581 error("Can't insert breakpoint for slot numbers greater than 2.");
582
583 addr &= ~0x0f;
584
585 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 586
587 /* Check for L type instruction in 2nd slot, if present then
588 bump up the slot number to the 3rd slot */
589 template = extract_bit_field (bundle, 0, 5);
590 if (slotnum == 1 && template_encoding_table[template][1] == L)
591 {
592 slotnum = 2;
593 }
594
16461d7d
KB		 595 instr = slotN_contents (bundle, slotnum);
596 memcpy(contents_cache, &instr, sizeof(instr));
aaab4dba 597 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 598 if (val == 0)
599 target_write_memory (addr, bundle, BUNDLE_LEN);
600
601 return val;
602}
603
604static int
605ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
606{
607 char bundle[BUNDLE_LEN];
608 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
609 long long instr;
610 int val;
126fa72d 611 int template;
16461d7d
KB		 612
613 addr &= ~0x0f;
614
615 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 616
617 /* Check for L type instruction in 2nd slot, if present then
618 bump up the slot number to the 3rd slot */
619 template = extract_bit_field (bundle, 0, 5);
620 if (slotnum == 1 && template_encoding_table[template][1] == L)
621 {
622 slotnum = 2;
623 }
624
16461d7d
KB		 625 memcpy (&instr, contents_cache, sizeof instr);
626 replace_slotN_contents (bundle, instr, slotnum);
627 if (val == 0)
628 target_write_memory (addr, bundle, BUNDLE_LEN);
629
630 return val;
631}
632
633/* We don't really want to use this, but remote.c needs to call it in order
634 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 635const unsigned char *
fba45db2 636ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 637{
638 static unsigned char breakpoint[] =
639 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
640 *lenptr = sizeof (breakpoint);
641#if 0
642 *pcptr &= ~0x0f;
643#endif
644 return breakpoint;
645}
646
bd1ce8ba
AC		 647static CORE_ADDR
648ia64_read_fp (void)
649{
650 /* We won't necessarily have a frame pointer and even if we do, it
651 winds up being extraordinarly messy when attempting to find the
652 frame chain. So for the purposes of creating frames (which is
653 all deprecated_read_fp() is used for), simply use the stack
654 pointer value instead. */
655 gdb_assert (SP_REGNUM >= 0);
656 return read_register (SP_REGNUM);
657}
658
a78f21af 659static CORE_ADDR
39f77062 660ia64_read_pc (ptid_t ptid)
16461d7d 661{
39f77062
KB		 662 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
663 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 664 int slot_num = (psr_value >> 41) & 3;
665
666 return pc_value | (slot_num * SLOT_MULTIPLIER);
667}
668
a78f21af 669static void
39f77062 670ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 671{
672 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 673 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 674 psr_value &= ~(3LL << 41);
675 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
676
677 new_pc &= ~0xfLL;
678
39f77062
KB		 679 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
680 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 681}
682
683#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
684
685/* Returns the address of the slot that's NSLOTS slots away from
686 the address ADDR. NSLOTS may be positive or negative. */
687static CORE_ADDR
688rse_address_add(CORE_ADDR addr, int nslots)
689{
690 CORE_ADDR new_addr;
691 int mandatory_nat_slots = nslots / 63;
692 int direction = nslots < 0 ? -1 : 1;
693
694 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
695
696 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
697 new_addr += 8 * direction;
698
699 if (IS_NaT_COLLECTION_ADDR(new_addr))
700 new_addr += 8 * direction;
701
702 return new_addr;
703}
704
004d836a
JJ		 705static void
706ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
707 int regnum, void *buf)
16461d7d 708{
004d836a 709 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 710 {
004d836a
JJ		 711 ULONGEST bsp;
712 ULONGEST cfm;
713 CORE_ADDR reg;
714 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
715 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
716
717 /* The bsp points at the end of the register frame so we
718 subtract the size of frame from it to get start of register frame. */
719 bsp = rse_address_add (bsp, -(cfm & 0x7f));
720
721 if ((cfm & 0x7f) > regnum - V32_REGNUM)
722 {
723 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
724 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
aa2a9a3c 725 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
004d836a 726 }
244bc108 727 else
aa2a9a3c 728 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a
JJ		 729 }
730 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
731 {
732 ULONGEST unatN_val;
733 ULONGEST unat;
734 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
735 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 736 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 737 }
738 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
739 {
740 ULONGEST natN_val = 0;
741 ULONGEST bsp;
742 ULONGEST cfm;
743 CORE_ADDR gr_addr = 0;
744 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
745 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
746
747 /* The bsp points at the end of the register frame so we
748 subtract the size of frame from it to get start of register frame. */
749 bsp = rse_address_add (bsp, -(cfm & 0x7f));
750
751 if ((cfm & 0x7f) > regnum - V32_REGNUM)
752 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
753
754 if (gr_addr != 0)
755 {
756 /* Compute address of nat collection bits. */
757 CORE_ADDR nat_addr = gr_addr | 0x1f8;
758 CORE_ADDR nat_collection;
759 int nat_bit;
760 /* If our nat collection address is bigger than bsp, we have to get
761 the nat collection from rnat. Otherwise, we fetch the nat
762 collection from the computed address. */
763 if (nat_addr >= bsp)
764 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
765 else
766 nat_collection = read_memory_integer (nat_addr, 8);
767 nat_bit = (gr_addr >> 3) & 0x3f;
768 natN_val = (nat_collection >> nat_bit) & 1;
769 }
770
aa2a9a3c 771 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 772 }
004d836a
JJ		 773 else if (regnum == VBOF_REGNUM)
774 {
775 /* A virtual register frame start is provided for user convenience.
776 It can be calculated as the bsp - sof (sizeof frame). */
777 ULONGEST bsp, vbsp;
778 ULONGEST cfm;
779 CORE_ADDR reg;
780 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
781 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
782
783 /* The bsp points at the end of the register frame so we
784 subtract the size of frame from it to get beginning of frame. */
785 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 786 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 787 }
788 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
789 {
790 ULONGEST pr;
791 ULONGEST cfm;
792 ULONGEST prN_val;
793 CORE_ADDR reg;
794 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
795 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
796
797 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
798 {
799 /* Fetch predicate register rename base from current frame
800 marker for this frame. */
801 int rrb_pr = (cfm >> 32) & 0x3f;
802
803 /* Adjust the register number to account for register rotation. */
804 regnum = VP16_REGNUM
805 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
806 }
807 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 808 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 809 }
810 else
aa2a9a3c 811 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 812}
813
004d836a
JJ		 814static void
815ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
816 int regnum, const void *buf)
16461d7d 817{
004d836a 818 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 819 {
004d836a
JJ		 820 ULONGEST bsp;
821 ULONGEST cfm;
822 CORE_ADDR reg;
823 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
824 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
825
826 bsp = rse_address_add (bsp, -(cfm & 0x7f));
827
828 if ((cfm & 0x7f) > regnum - V32_REGNUM)
829 {
830 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
831 write_memory (reg_addr, (void *)buf, 8);
832 }
833 }
834 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
835 {
836 ULONGEST unatN_val, unat, unatN_mask;
837 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 838 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 839 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
840 if (unatN_val == 0)
841 unat &= ~unatN_mask;
842 else if (unatN_val == 1)
843 unat |= unatN_mask;
844 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
845 }
846 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
847 {
848 ULONGEST natN_val;
849 ULONGEST bsp;
850 ULONGEST cfm;
851 CORE_ADDR gr_addr = 0;
852 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
853 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
854
855 /* The bsp points at the end of the register frame so we
856 subtract the size of frame from it to get start of register frame. */
857 bsp = rse_address_add (bsp, -(cfm & 0x7f));
858
859 if ((cfm & 0x7f) > regnum - V32_REGNUM)
860 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
861
aa2a9a3c 862 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 863
864 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
865 {
866 /* Compute address of nat collection bits. */
867 CORE_ADDR nat_addr = gr_addr | 0x1f8;
868 CORE_ADDR nat_collection;
869 int natN_bit = (gr_addr >> 3) & 0x3f;
870 ULONGEST natN_mask = (1LL << natN_bit);
871 /* If our nat collection address is bigger than bsp, we have to get
872 the nat collection from rnat. Otherwise, we fetch the nat
873 collection from the computed address. */
874 if (nat_addr >= bsp)
875 {
876 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
877 if (natN_val)
878 nat_collection |= natN_mask;
879 else
880 nat_collection &= ~natN_mask;
881 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
882 }
883 else
884 {
885 char nat_buf[8];
886 nat_collection = read_memory_integer (nat_addr, 8);
887 if (natN_val)
888 nat_collection |= natN_mask;
889 else
890 nat_collection &= ~natN_mask;
aa2a9a3c 891 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 892 write_memory (nat_addr, nat_buf, 8);
893 }
894 }
895 }
896 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
897 {
898 ULONGEST pr;
899 ULONGEST cfm;
900 ULONGEST prN_val;
901 ULONGEST prN_mask;
902
903 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
904 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
905
906 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
907 {
908 /* Fetch predicate register rename base from current frame
909 marker for this frame. */
910 int rrb_pr = (cfm >> 32) & 0x3f;
911
912 /* Adjust the register number to account for register rotation. */
913 regnum = VP16_REGNUM
914 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
915 }
aa2a9a3c 916 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 917 prN_mask = (1LL << (regnum - VP0_REGNUM));
918 if (prN_val == 0)
919 pr &= ~prN_mask;
920 else if (prN_val == 1)
921 pr |= prN_mask;
922 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 923 }
16461d7d
KB		 924}
925
004d836a
JJ		 926/* The ia64 needs to convert between various ieee floating-point formats
927 and the special ia64 floating point register format. */
928
929static int
930ia64_convert_register_p (int regno, struct type *type)
931{
932 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
933}
934
935static void
936ia64_register_to_value (struct frame_info *frame, int regnum,
937 struct type *valtype, void *out)
938{
939 char in[MAX_REGISTER_SIZE];
940 frame_register_read (frame, regnum, in);
941 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
942}
943
944static void
945ia64_value_to_register (struct frame_info *frame, int regnum,
946 struct type *valtype, const void *in)
947{
948 char out[MAX_REGISTER_SIZE];
949 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
950 put_frame_register (frame, regnum, out);
951}
952
953
58ab00f9
KB		 954/* Limit the number of skipped non-prologue instructions since examining
955 of the prologue is expensive. */
5ea2bd7f 956static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 957
958/* Given PC representing the starting address of a function, and
959 LIM_PC which is the (sloppy) limit to which to scan when looking
960 for a prologue, attempt to further refine this limit by using
961 the line data in the symbol table. If successful, a better guess
962 on where the prologue ends is returned, otherwise the previous
963 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
964 which will be set to indicate whether the returned limit may be
965 used with no further scanning in the event that the function is
966 frameless. */
967
968static CORE_ADDR
969refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
970{
971 struct symtab_and_line prologue_sal;
972 CORE_ADDR start_pc = pc;
973
974 /* Start off not trusting the limit. */
975 *trust_limit = 0;
976
977 prologue_sal = find_pc_line (pc, 0);
978 if (prologue_sal.line != 0)
979 {
980 int i;
981 CORE_ADDR addr = prologue_sal.end;
982
983 /* Handle the case in which compiler's optimizer/scheduler
984 has moved instructions into the prologue. We scan ahead
985 in the function looking for address ranges whose corresponding
986 line number is less than or equal to the first one that we
987 found for the function. (It can be less than when the
988 scheduler puts a body instruction before the first prologue
989 instruction.) */
990 for (i = 2 * max_skip_non_prologue_insns;
991 i > 0 && (lim_pc == 0 || addr < lim_pc);
992 i--)
993 {
994 struct symtab_and_line sal;
995
996 sal = find_pc_line (addr, 0);
997 if (sal.line == 0)
998 break;
999 if (sal.line <= prologue_sal.line
1000 && sal.symtab == prologue_sal.symtab)
1001 {
1002 prologue_sal = sal;
1003 }
1004 addr = sal.end;
1005 }
1006
1007 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1008 {
1009 lim_pc = prologue_sal.end;
1010 if (start_pc == get_pc_function_start (lim_pc))
1011 *trust_limit = 1;
1012 }
1013 }
1014 return lim_pc;
1015}
1016
16461d7d
KB		 1017#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1018 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1019 || (14 <= (_regnum_) && (_regnum_) <= 31))
1020#define imm9(_instr_) \
1021 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1022 | (((_instr_) & 0x00008000000LL) >> 20) \
1023 | (((_instr_) & 0x00000001fc0LL) >> 6))
1024
004d836a
JJ		 1025/* Allocate and initialize a frame cache. */
1026
1027static struct ia64_frame_cache *
1028ia64_alloc_frame_cache (void)
1029{
1030 struct ia64_frame_cache *cache;
1031 int i;
1032
1033 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1034
1035 /* Base address. */
1036 cache->base = 0;
1037 cache->pc = 0;
1038 cache->cfm = 0;
4afcc598 1039 cache->prev_cfm = 0;
004d836a
JJ		 1040 cache->sof = 0;
1041 cache->sol = 0;
1042 cache->sor = 0;
1043 cache->bsp = 0;
1044 cache->fp_reg = 0;
1045 cache->frameless = 1;
1046
1047 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1048 cache->saved_regs[i] = 0;
1049
1050 return cache;
1051}
1052
16461d7d 1053static CORE_ADDR
004d836a 1054examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1055{
1056 CORE_ADDR next_pc;
1057 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1058 instruction_type it;
1059 long long instr;
16461d7d
KB		 1060 int cfm_reg = 0;
1061 int ret_reg = 0;
1062 int fp_reg = 0;
1063 int unat_save_reg = 0;
1064 int pr_save_reg = 0;
1065 int mem_stack_frame_size = 0;
1066 int spill_reg = 0;
1067 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1068 char instores[8];
1069 char infpstores[8];
5ea2bd7f 1070 char reg_contents[256];
58ab00f9 1071 int trust_limit;
004d836a
JJ		 1072 int frameless = 1;
1073 int i;
1074 CORE_ADDR addr;
1075 char buf[8];
1076 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1077
1078 memset (instores, 0, sizeof instores);
1079 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1080 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1081
004d836a
JJ		 1082 if (cache->after_prologue != 0
1083 && cache->after_prologue <= lim_pc)
1084 return cache->after_prologue;
16461d7d 1085
58ab00f9 1086 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1087 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1088
1089 /* We want to check if we have a recognizable function start before we
1090 look ahead for a prologue. */
16461d7d
KB		 1091 if (pc < lim_pc && next_pc
1092 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1093 {
5ea2bd7f 1094 /* alloc - start of a regular function. */
16461d7d
KB		 1095 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1096 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1097 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1098 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1099
1100 /* Verify that the current cfm matches what we think is the
1101 function start. If we have somehow jumped within a function,
1102 we do not want to interpret the prologue and calculate the
1103 addresses of various registers such as the return address.
1104 We will instead treat the frame as frameless. */
1105 if (!next_frame ||
1106 (sof == (cache->cfm & 0x7f) &&
1107 sol == ((cache->cfm >> 7) & 0x7f)))
1108 frameless = 0;
1109
16461d7d
KB		 1110 cfm_reg = rN;
1111 last_prologue_pc = next_pc;
1112 pc = next_pc;
1113 }
1114 else
58ab00f9 1115 {
5ea2bd7f
JJ		 1116 /* Look for a leaf routine. */
1117 if (pc < lim_pc && next_pc
1118 && (it == I || it == M)
1119 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1120 {
1121 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1122 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1123 | ((instr & 0x001f8000000LL) >> 20)
1124 | ((instr & 0x000000fe000LL) >> 13));
1125 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1126 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1127 int qp = (int) (instr & 0x0000000003fLL);
1128 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1129 {
1130 /* mov r2, r12 - beginning of leaf routine */
1131 fp_reg = rN;
5ea2bd7f
JJ		 1132 last_prologue_pc = next_pc;
1133 }
1134 }
1135
1136 /* If we don't recognize a regular function or leaf routine, we are
1137 done. */
1138 if (!fp_reg)
1139 {
1140 pc = lim_pc;
1141 if (trust_limit)
1142 last_prologue_pc = lim_pc;
1143 }
58ab00f9 1144 }
16461d7d
KB		 1145
1146 /* Loop, looking for prologue instructions, keeping track of
1147 where preserved registers were spilled. */
1148 while (pc < lim_pc)
1149 {
1150 next_pc = fetch_instruction (pc, &it, &instr);
1151 if (next_pc == 0)
1152 break;
1153
102d615a 1154 if (it == B && ((instr & 0x1e1f800003f) != 0x04000000000))
0927a22b 1155 {
102d615a
JJ		 1156 /* Exit loop upon hitting a non-nop branch instruction. */
1157 if (trust_limit)
1158 lim_pc = pc;
1159 break;
1160 }
1161 else if (((instr & 0x3fLL) != 0LL) &&
1162 (frameless || ret_reg != 0))
1163 {
1164 /* Exit loop upon hitting a predicated instruction if
1165 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1166 if (trust_limit)
1167 lim_pc = pc;
0927a22b
KB		 1168 break;
1169 }
1170 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1171 {
1172 /* Move from BR */
1173 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1174 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1175 int qp = (int) (instr & 0x0000000003f);
1176
1177 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1178 {
1179 ret_reg = rN;
1180 last_prologue_pc = next_pc;
1181 }
1182 }
1183 else if ((it == I || it == M)
1184 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1185 {
1186 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1187 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1188 | ((instr & 0x001f8000000LL) >> 20)
1189 | ((instr & 0x000000fe000LL) >> 13));
1190 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1191 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1192 int qp = (int) (instr & 0x0000000003fLL);
1193
1194 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1195 {
1196 /* mov rN, r12 */
1197 fp_reg = rN;
1198 last_prologue_pc = next_pc;
1199 }
1200 else if (qp == 0 && rN == 12 && rM == 12)
1201 {
1202 /* adds r12, -mem_stack_frame_size, r12 */
1203 mem_stack_frame_size -= imm;
1204 last_prologue_pc = next_pc;
1205 }
1206 else if (qp == 0 && rN == 2
1207 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1208 {
004d836a
JJ		 1209 char buf[MAX_REGISTER_SIZE];
1210 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1211 /* adds r2, spilloffset, rFramePointer
1212 or
1213 adds r2, spilloffset, r12
1214
1215 Get ready for stf.spill or st8.spill instructions.
1216 The address to start spilling at is loaded into r2.
1217 FIXME: Why r2? That's what gcc currently uses; it
1218 could well be different for other compilers. */
1219
1220 /* Hmm... whether or not this will work will depend on
1221 where the pc is. If it's still early in the prologue
1222 this'll be wrong. FIXME */
004d836a
JJ		 1223 if (next_frame)
1224 {
1225 frame_unwind_register (next_frame, sp_regnum, buf);
1226 saved_sp = extract_unsigned_integer (buf, 8);
1227 }
1228 spill_addr = saved_sp
16461d7d
KB		 1229 + (rM == 12 ? 0 : mem_stack_frame_size)
1230 + imm;
1231 spill_reg = rN;
1232 last_prologue_pc = next_pc;
1233 }
5ea2bd7f
JJ		 1234 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1235 rN < 256 && imm == 0)
1236 {
1237 /* mov rN, rM where rM is an input register */
1238 reg_contents[rN] = rM;
1239 last_prologue_pc = next_pc;
1240 }
1241 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1242 rM == 2)
1243 {
1244 /* mov r12, r2 */
1245 last_prologue_pc = next_pc;
1246 break;
1247 }
16461d7d
KB		 1248 }
1249 else if (it == M
1250 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1251 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1252 {
1253 /* stf.spill [rN] = fM, imm9
1254 or
1255 stf.spill [rN] = fM */
1256
1257 int imm = imm9(instr);
1258 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1259 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1260 int qp = (int) (instr & 0x0000000003fLL);
1261 if (qp == 0 && rN == spill_reg && spill_addr != 0
1262 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1263 {
004d836a 1264 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d
KB		 1265
1266 if ((instr & 0x1efc0000000) == 0x0eec0000000)
1267 spill_addr += imm;
1268 else
1269 spill_addr = 0; /* last one; must be done */
1270 last_prologue_pc = next_pc;
1271 }
1272 }
1273 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1274 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1275 {
1276 /* mov.m rN = arM
1277 or
1278 mov.i rN = arM */
1279
1280 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1281 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1282 int qp = (int) (instr & 0x0000000003fLL);
1283 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1284 {
1285 /* We have something like "mov.m r3 = ar.unat". Remember the
1286 r3 (or whatever) and watch for a store of this register... */
1287 unat_save_reg = rN;
1288 last_prologue_pc = next_pc;
1289 }
1290 }
1291 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1292 {
1293 /* mov rN = pr */
1294 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1295 int qp = (int) (instr & 0x0000000003fLL);
1296 if (qp == 0 && isScratch (rN))
1297 {
1298 pr_save_reg = rN;
1299 last_prologue_pc = next_pc;
1300 }
1301 }
1302 else if (it == M
1303 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1304 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1305 {
1306 /* st8 [rN] = rM
1307 or
1308 st8 [rN] = rM, imm9 */
1309 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1310 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1311 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1312 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1313 if (qp == 0 && rN == spill_reg && spill_addr != 0
1314 && (rM == unat_save_reg || rM == pr_save_reg))
1315 {
1316 /* We've found a spill of either the UNAT register or the PR
1317 register. (Well, not exactly; what we've actually found is
1318 a spill of the register that UNAT or PR was moved to).
1319 Record that fact and move on... */
1320 if (rM == unat_save_reg)
1321 {
1322 /* Track UNAT register */
004d836a 1323 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1324 unat_save_reg = 0;
1325 }
1326 else
1327 {
1328 /* Track PR register */
004d836a 1329 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1330 pr_save_reg = 0;
1331 }
1332 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1333 /* st8 [rN] = rM, imm9 */
1334 spill_addr += imm9(instr);
1335 else
1336 spill_addr = 0; /* must be done spilling */
1337 last_prologue_pc = next_pc;
1338 }
0927a22b
KB		 1339 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1340 {
1341 /* Allow up to one store of each input register. */
1342 instores[rM-32] = 1;
1343 last_prologue_pc = next_pc;
1344 }
5ea2bd7f
JJ		 1345 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1346 !instores[indirect-32])
1347 {
1348 /* Allow an indirect store of an input register. */
1349 instores[indirect-32] = 1;
1350 last_prologue_pc = next_pc;
1351 }
0927a22b
KB		 1352 }
1353 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1354 {
1355 /* One of
1356 st1 [rN] = rM
1357 st2 [rN] = rM
1358 st4 [rN] = rM
1359 st8 [rN] = rM
1360 Note that the st8 case is handled in the clause above.
1361
1362 Advance over stores of input registers. One store per input
1363 register is permitted. */
1364 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1365 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1366 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1367 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1368 {
1369 instores[rM-32] = 1;
1370 last_prologue_pc = next_pc;
1371 }
5ea2bd7f
JJ		 1372 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1373 !instores[indirect-32])
1374 {
1375 /* Allow an indirect store of an input register. */
1376 instores[indirect-32] = 1;
1377 last_prologue_pc = next_pc;
1378 }
0927a22b
KB		 1379 }
1380 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1381 {
1382 /* Either
1383 stfs [rN] = fM
1384 or
1385 stfd [rN] = fM
1386
1387 Advance over stores of floating point input registers. Again
1388 one store per register is permitted */
1389 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1390 int qp = (int) (instr & 0x0000000003fLL);
1391 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1392 {
1393 infpstores[fM-8] = 1;
1394 last_prologue_pc = next_pc;
1395 }
16461d7d
KB		 1396 }
1397 else if (it == M
1398 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1399 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1400 {
1401 /* st8.spill [rN] = rM
1402 or
1403 st8.spill [rN] = rM, imm9 */
1404 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1405 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1406 int qp = (int) (instr & 0x0000000003fLL);
1407 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1408 {
1409 /* We've found a spill of one of the preserved general purpose
1410 regs. Record the spill address and advance the spill
1411 register if appropriate. */
004d836a 1412 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1413 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1414 /* st8.spill [rN] = rM, imm9 */
1415 spill_addr += imm9(instr);
1416 else
1417 spill_addr = 0; /* Done spilling */
1418 last_prologue_pc = next_pc;
1419 }
1420 }
16461d7d
KB		 1421
1422 pc = next_pc;
1423 }
1424
004d836a
JJ		 1425 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1426 registers for the previous frame which will be needed later. */
16461d7d 1427
004d836a 1428 if (!frameless && next_frame)
da50a4b7 1429 {
004d836a
JJ		 1430 /* Extract the size of the rotating portion of the stack
1431 frame and the register rename base from the current
1432 frame marker. */
1433 cfm = cache->cfm;
1434 sor = cache->sor;
1435 sof = cache->sof;
1436 sol = cache->sol;
1437 rrb_gr = (cfm >> 18) & 0x7f;
1438
1439 /* Find the bof (beginning of frame). */
1440 bof = rse_address_add (cache->bsp, -sof);
1441
1442 for (i = 0, addr = bof;
1443 i < sof;
1444 i++, addr += 8)
1445 {
1446 if (IS_NaT_COLLECTION_ADDR (addr))
1447 {
1448 addr += 8;
1449 }
1450 if (i+32 == cfm_reg)
1451 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1452 if (i+32 == ret_reg)
1453 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1454 if (i+32 == fp_reg)
1455 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1456 }
16461d7d 1457
004d836a
JJ		 1458 /* For the previous argument registers we require the previous bof.
1459 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1460 cfm = 0;
004d836a
JJ		 1461 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1462 {
1463 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1464 }
1465 else if (cfm_reg != 0)
1466 {
1467 frame_unwind_register (next_frame, cfm_reg, buf);
1468 cfm = extract_unsigned_integer (buf, 8);
1469 }
1470 cache->prev_cfm = cfm;
1471
1472 if (cfm != 0)
1473 {
004d836a
JJ		 1474 sor = ((cfm >> 14) & 0xf) * 8;
1475 sof = (cfm & 0x7f);
1476 sol = (cfm >> 7) & 0x7f;
1477 rrb_gr = (cfm >> 18) & 0x7f;
1478
1479 /* The previous bof only requires subtraction of the sol (size of locals)
1480 due to the overlap between output and input of subsequent frames. */
1481 bof = rse_address_add (bof, -sol);
1482
1483 for (i = 0, addr = bof;
1484 i < sof;
1485 i++, addr += 8)
1486 {
1487 if (IS_NaT_COLLECTION_ADDR (addr))
1488 {
1489 addr += 8;
1490 }
1491 if (i < sor)
1492 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1493 = addr;
1494 else
1495 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1496 }
1497
1498 }
1499 }
1500
5ea2bd7f
JJ		 1501 /* Try and trust the lim_pc value whenever possible. */
1502 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1503 last_prologue_pc = lim_pc;
1504
1505 cache->frameless = frameless;
1506 cache->after_prologue = last_prologue_pc;
1507 cache->mem_stack_frame_size = mem_stack_frame_size;
1508 cache->fp_reg = fp_reg;
5ea2bd7f 1509
16461d7d
KB		 1510 return last_prologue_pc;
1511}
1512
1513CORE_ADDR
1514ia64_skip_prologue (CORE_ADDR pc)
1515{
004d836a
JJ		 1516 struct ia64_frame_cache cache;
1517 cache.base = 0;
1518 cache.after_prologue = 0;
1519 cache.cfm = 0;
1520 cache.bsp = 0;
1521
1522 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1523 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1524}
1525
004d836a
JJ		 1526
1527/* Normal frames. */
1528
1529static struct ia64_frame_cache *
1530ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1531{
004d836a
JJ		 1532 struct ia64_frame_cache *cache;
1533 char buf[8];
1534 CORE_ADDR cfm, sof, sol, bsp, psr;
1535 int i;
16461d7d 1536
004d836a
JJ		 1537 if (*this_cache)
1538 return *this_cache;
16461d7d 1539
004d836a
JJ		 1540 cache = ia64_alloc_frame_cache ();
1541 *this_cache = cache;
16461d7d 1542
004d836a
JJ		 1543 frame_unwind_register (next_frame, sp_regnum, buf);
1544 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1545
004d836a
JJ		 1546 /* We always want the bsp to point to the end of frame.
1547 This way, we can always get the beginning of frame (bof)
1548 by subtracting frame size. */
1549 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1550 cache->bsp = extract_unsigned_integer (buf, 8);
1551
1552 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1553 psr = extract_unsigned_integer (buf, 8);
1554
1555 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1556 cfm = extract_unsigned_integer (buf, 8);
1557
1558 cache->sof = (cfm & 0x7f);
1559 cache->sol = (cfm >> 7) & 0x7f;
1560 cache->sor = ((cfm >> 14) & 0xf) * 8;
1561
1562 cache->cfm = cfm;
1563
1564 cache->pc = frame_func_unwind (next_frame);
1565
1566 if (cache->pc != 0)
1567 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1568
1569 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1570
1571 return cache;
16461d7d
KB		 1572}
1573
a78f21af 1574static void
004d836a
JJ		 1575ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1576 struct frame_id *this_id)
16461d7d 1577{
004d836a
JJ		 1578 struct ia64_frame_cache *cache =
1579 ia64_frame_cache (next_frame, this_cache);
16461d7d 1580
004d836a
JJ		 1581 /* This marks the outermost frame. */
1582 if (cache->base == 0)
1583 return;
16461d7d 1584
4afcc598
JJ		 1585 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1586 if (gdbarch_debug >= 1)
1587 fprintf_unfiltered (gdb_stdlog,
1588 "regular frame id: code %lx, stack %lx, special %lx, next_frame %p\n",
1589 this_id->code_addr, this_id->stack_addr, cache->bsp, next_frame);
004d836a 1590}
244bc108 1591
004d836a
JJ		 1592static void
1593ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1594 int regnum, int *optimizedp,
1595 enum lval_type *lvalp, CORE_ADDR *addrp,
1596 int *realnump, void *valuep)
1597{
1598 struct ia64_frame_cache *cache =
1599 ia64_frame_cache (next_frame, this_cache);
1600 char dummy_valp[MAX_REGISTER_SIZE];
1601 char buf[8];
1602
1603 gdb_assert (regnum >= 0);
244bc108 1604
004d836a
JJ		 1605 if (!target_has_registers)
1606 error ("No registers.");
244bc108 1607
004d836a
JJ		 1608 *optimizedp = 0;
1609 *addrp = 0;
1610 *lvalp = not_lval;
1611 *realnump = -1;
244bc108 1612
004d836a
JJ		 1613 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1614 when valuep is not supplied. */
1615 if (!valuep)
1616 valuep = dummy_valp;
1617
aa2a9a3c 1618 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1619
1620 if (regnum == SP_REGNUM)
16461d7d
KB		 1621 {
1622 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1623 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1624 cache->base);
16461d7d
KB		 1625 }
1626 else if (regnum == IA64_BSP_REGNUM)
1627 {
004d836a
JJ		 1628 char cfm_valuep[MAX_REGISTER_SIZE];
1629 int cfm_optim;
1630 int cfm_realnum;
1631 enum lval_type cfm_lval;
1632 CORE_ADDR cfm_addr;
1633 CORE_ADDR bsp, prev_cfm, prev_bsp;
1634
1635 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1636 This corresponds to what the hardware bsp register will be if we pop the frame
1637 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1638 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1639 the start of the output registers. We can calculate the end of that frame by adding
1640 the size of output (sof (size of frame) - sol (size of locals)). */
1641 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1642 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1643 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1644
1645 bsp = rse_address_add (cache->bsp, -(cache->sof));
1646 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1647
aa2a9a3c 1648 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1649 prev_bsp);
1650 }
1651 else if (regnum == IA64_CFM_REGNUM)
1652 {
4afcc598
JJ		 1653 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1654
1655 if (addr != 0)
004d836a 1656 {
4afcc598
JJ		 1657 *lvalp = lval_memory;
1658 *addrp = addr;
1659 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1660 }
4afcc598
JJ		 1661 else if (cache->prev_cfm)
1662 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1663 else if (cache->frameless)
004d836a 1664 {
4afcc598
JJ		 1665 CORE_ADDR cfm = 0;
1666 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1667 }
16461d7d
KB		 1668 }
1669 else if (regnum == IA64_VFP_REGNUM)
1670 {
1671 /* If the function in question uses an automatic register (r32-r127)
1672 for the frame pointer, it'll be found by ia64_find_saved_register()
1673 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1674 still provide a value since we know the size of the frame. */
1675 CORE_ADDR vfp = cache->base;
aa2a9a3c 1676 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1677 }
004d836a 1678 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1679 {
004d836a 1680 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1681 int pr_optim;
004d836a 1682 int pr_realnum;
16461d7d
KB		 1683 enum lval_type pr_lval;
1684 CORE_ADDR pr_addr;
004d836a
JJ		 1685 ULONGEST prN_val;
1686 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1687 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1688 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1689 {
1690 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1691 marker for this frame. */
1692 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1693
004d836a
JJ		 1694 /* Adjust the register number to account for register rotation. */
1695 regnum = VP16_REGNUM
1696 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1697 }
004d836a
JJ		 1698 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1699 regnum - VP0_REGNUM, 1);
aa2a9a3c 1700 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1701 }
1702 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1703 {
004d836a 1704 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1705 int unat_optim;
004d836a 1706 int unat_realnum;
16461d7d
KB		 1707 enum lval_type unat_lval;
1708 CORE_ADDR unat_addr;
004d836a
JJ		 1709 ULONGEST unatN_val;
1710 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1711 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1712 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1713 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1714 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1715 unatN_val);
16461d7d
KB		 1716 }
1717 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1718 {
1719 int natval = 0;
1720 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1721 interested in. */
1722 CORE_ADDR gr_addr;
244bc108 1723
004d836a
JJ		 1724 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1725 + IA64_GR0_REGNUM];
1726 if (gr_addr != 0)
244bc108 1727 {
004d836a 1728 /* Compute address of nat collection bits. */
16461d7d 1729 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1730 CORE_ADDR bsp;
16461d7d
KB		 1731 CORE_ADDR nat_collection;
1732 int nat_bit;
1733 /* If our nat collection address is bigger than bsp, we have to get
1734 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1735 collection from the computed address. */
1736 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1737 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1738 if (nat_addr >= bsp)
004d836a
JJ		 1739 {
1740 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1741 nat_collection = extract_unsigned_integer (buf, 8);
1742 }
16461d7d
KB		 1743 else
1744 nat_collection = read_memory_integer (nat_addr, 8);
1745 nat_bit = (gr_addr >> 3) & 0x3f;
1746 natval = (nat_collection >> nat_bit) & 1;
1747 }
004d836a 1748
aa2a9a3c 1749 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1750 }
1751 else if (regnum == IA64_IP_REGNUM)
1752 {
004d836a 1753 CORE_ADDR pc = 0;
4afcc598 1754 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1755
4afcc598 1756 if (addr != 0)
004d836a 1757 {
4afcc598
JJ		 1758 *lvalp = lval_memory;
1759 *addrp = addr;
1760 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1761 pc = extract_unsigned_integer (buf, 8);
1762 }
4afcc598 1763 else if (cache->frameless)
004d836a 1764 {
4afcc598
JJ		 1765 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1766 pc = extract_unsigned_integer (buf, 8);
244bc108 1767 }
004d836a
JJ		 1768 pc &= ~0xf;
1769 store_unsigned_integer (valuep, 8, pc);
244bc108 1770 }
004d836a 1771 else if (regnum == IA64_PSR_REGNUM)
244bc108 1772 {
4afcc598
JJ		 1773 /* We don't know how to get the complete previous PSR, but we need it for
1774 the slot information when we unwind the pc (pc is formed of IP register
1775 plus slot information from PSR). To get the previous slot information,
1776 we mask it off the return address. */
004d836a
JJ		 1777 ULONGEST slot_num = 0;
1778 CORE_ADDR pc= 0;
1779 CORE_ADDR psr = 0;
4afcc598 1780 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1781
1782 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1783 psr = extract_unsigned_integer (buf, 8);
1784
4afcc598 1785 if (addr != 0)
244bc108 1786 {
4afcc598
JJ		 1787 *lvalp = lval_memory;
1788 *addrp = addr;
1789 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1790 pc = extract_unsigned_integer (buf, 8);
244bc108 1791 }
4afcc598 1792 else if (cache->frameless)
004d836a 1793 {
4afcc598
JJ		 1794 CORE_ADDR pc;
1795 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1796 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1797 }
1798 psr &= ~(3LL << 41);
1799 slot_num = pc & 0x3LL;
1800 psr |= (CORE_ADDR)slot_num << 41;
1801 store_unsigned_integer (valuep, 8, psr);
1802 }
4afcc598
JJ		 1803 else if (regnum == IA64_BR0_REGNUM)
1804 {
1805 CORE_ADDR br0 = 0;
1806 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1807 if (addr != 0)
1808 {
1809 *lvalp = lval_memory;
1810 *addrp = addr;
1811 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1812 br0 = extract_unsigned_integer (buf, 8);
1813 }
1814 store_unsigned_integer (valuep, 8, br0);
1815 }
004d836a
JJ		 1816 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1817 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1818 {
1819 CORE_ADDR addr = 0;
1820 if (regnum >= V32_REGNUM)
1821 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1822 addr = cache->saved_regs[regnum];
244bc108
KB		 1823 if (addr != 0)
1824 {
004d836a
JJ		 1825 *lvalp = lval_memory;
1826 *addrp = addr;
aa2a9a3c 1827 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1828 }
004d836a 1829 else if (cache->frameless)
244bc108 1830 {
004d836a
JJ		 1831 char r_valuep[MAX_REGISTER_SIZE];
1832 int r_optim;
1833 int r_realnum;
1834 enum lval_type r_lval;
1835 CORE_ADDR r_addr;
1836 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1837 CORE_ADDR addr = 0;
1838 if (regnum >= V32_REGNUM)
1839 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1840 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1841 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1842 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1843 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1844 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1845 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1846 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1847
1848 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1849 *lvalp = lval_memory;
1850 *addrp = addr;
aa2a9a3c 1851 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1852 }
16461d7d
KB		 1853 }
1854 else
1855 {
004d836a 1856 CORE_ADDR addr = 0;
3a854e23
KB		 1857 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1858 {
1859 /* Fetch floating point register rename base from current
004d836a
JJ		 1860 frame marker for this frame. */
1861 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1862
1863 /* Adjust the floating point register number to account for
004d836a 1864 register rotation. */
3a854e23
KB		 1865 regnum = IA64_FR32_REGNUM
1866 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1867 }
1868
004d836a
JJ		 1869 /* If we have stored a memory address, access the register. */
1870 addr = cache->saved_regs[regnum];
1871 if (addr != 0)
1872 {
1873 *lvalp = lval_memory;
1874 *addrp = addr;
aa2a9a3c 1875 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1876 }
1877 /* Otherwise, punt and get the current value of the register. */
1878 else
1879 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1880 }
4afcc598
JJ		 1881
1882 if (gdbarch_debug >= 1)
1883 fprintf_unfiltered (gdb_stdlog,
1884 "regular prev register <%d> <%s> is %lx\n", regnum,
1885 (((unsigned) regnum <= IA64_NAT127_REGNUM)
1886 ? ia64_register_names[regnum] : "r??"), extract_unsigned_integer (valuep, 8));
16461d7d 1887}
004d836a
JJ		 1888
1889static const struct frame_unwind ia64_frame_unwind =
1890{
1891 NORMAL_FRAME,
1892 &ia64_frame_this_id,
1893 &ia64_frame_prev_register
1894};
1895
1896static const struct frame_unwind *
1897ia64_frame_sniffer (struct frame_info *next_frame)
1898{
1899 return &ia64_frame_unwind;
1900}
1901
1902/* Signal trampolines. */
1903
1904static void
1905ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1906{
1907 if (SIGCONTEXT_REGISTER_ADDRESS)
1908 {
1909 int regno;
1910
1911 cache->saved_regs[IA64_VRAP_REGNUM] =
1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1913 cache->saved_regs[IA64_CFM_REGNUM] =
1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1915 cache->saved_regs[IA64_PSR_REGNUM] =
1916 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1917 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1918 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1919 cache->saved_regs[IA64_RNAT_REGNUM] =
1920 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1921 cache->saved_regs[IA64_CCV_REGNUM] =
1922 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1923 cache->saved_regs[IA64_UNAT_REGNUM] =
1924 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1925 cache->saved_regs[IA64_FPSR_REGNUM] =
1926 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1927 cache->saved_regs[IA64_PFS_REGNUM] =
1928 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1929 cache->saved_regs[IA64_LC_REGNUM] =
1930 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1931 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1932 cache->saved_regs[regno] =
1933 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1934 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1935 cache->saved_regs[regno] =
1936 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1937 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1938 cache->saved_regs[regno] =
1939 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1940 }
1941}
1942
1943static struct ia64_frame_cache *
1944ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1945{
1946 struct ia64_frame_cache *cache;
1947 CORE_ADDR addr;
1948 char buf[8];
1949 int i;
1950
1951 if (*this_cache)
1952 return *this_cache;
1953
1954 cache = ia64_alloc_frame_cache ();
1955
1956 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1957 /* Note that frame size is hard-coded below. We cannot calculate it
1958 via prologue examination. */
1959 cache->base = extract_unsigned_integer (buf, 8) + 16;
1960
1961 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1962 cache->bsp = extract_unsigned_integer (buf, 8);
1963
1964 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1965 cache->cfm = extract_unsigned_integer (buf, 8);
1966 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1967
1968 ia64_sigtramp_frame_init_saved_regs (cache);
1969
1970 *this_cache = cache;
1971 return cache;
1972}
1973
1974static void
1975ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1976 void **this_cache, struct frame_id *this_id)
1977{
1978 struct ia64_frame_cache *cache =
1979 ia64_sigtramp_frame_cache (next_frame, this_cache);
1980
4afcc598
JJ		 1981 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1982 if (gdbarch_debug >= 1)
1983 fprintf_unfiltered (gdb_stdlog,
1984 "sigtramp frame id: code %lx, stack %lx, special %lx, next_frame %p\n",
1985 this_id->code_addr, this_id->stack_addr, cache->bsp, next_frame);
004d836a
JJ		 1986}
1987
1988static void
1989ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1990 void **this_cache,
1991 int regnum, int *optimizedp,
1992 enum lval_type *lvalp, CORE_ADDR *addrp,
1993 int *realnump, void *valuep)
1994{
4afcc598
JJ		 1995 char dummy_valp[MAX_REGISTER_SIZE];
1996 char buf[MAX_REGISTER_SIZE];
1997
1998 struct ia64_frame_cache *cache =
1999 ia64_sigtramp_frame_cache (next_frame, this_cache);
2000
2001 gdb_assert (regnum >= 0);
2002
2003 if (!target_has_registers)
2004 error ("No registers.");
2005
2006 *optimizedp = 0;
2007 *addrp = 0;
2008 *lvalp = not_lval;
2009 *realnump = -1;
2010
2011 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2012 when valuep is not supplied. */
2013 if (!valuep)
2014 valuep = dummy_valp;
2015
2016 memset (valuep, 0, register_size (current_gdbarch, regnum));
2017
2018 if (regnum == IA64_IP_REGNUM)
2019 {
2020 CORE_ADDR pc = 0;
2021 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2022
2023 if (addr != 0)
2024 {
2025 *lvalp = lval_memory;
2026 *addrp = addr;
2027 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2028 pc = extract_unsigned_integer (buf, 8);
2029 }
2030 pc &= ~0xf;
2031 store_unsigned_integer (valuep, 8, pc);
2032 }
2033 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2034 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2035 {
2036 CORE_ADDR addr = 0;
2037 if (regnum >= V32_REGNUM)
2038 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2039 addr = cache->saved_regs[regnum];
2040 if (addr != 0)
2041 {
2042 *lvalp = lval_memory;
2043 *addrp = addr;
2044 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2045 }
2046 }
2047 else
2048 {
2049 /* All other registers not listed above. */
2050 CORE_ADDR addr = cache->saved_regs[regnum];
2051 if (addr != 0)
2052 {
2053 *lvalp = lval_memory;
2054 *addrp = addr;
2055 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2056 }
2057 }
004d836a 2058
4afcc598
JJ		 2059 if (gdbarch_debug >= 1)
2060 fprintf_unfiltered (gdb_stdlog,
2061 "sigtramp prev register <%s> is %lx\n",
2062 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2063 ? ia64_register_names[regnum] : "r??"), extract_unsigned_integer (valuep, 8));
004d836a
JJ		 2064}
2065
2066static const struct frame_unwind ia64_sigtramp_frame_unwind =
2067{
2068 SIGTRAMP_FRAME,
2069 ia64_sigtramp_frame_this_id,
2070 ia64_sigtramp_frame_prev_register
2071};
2072
2073static const struct frame_unwind *
2074ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2075{
2076 char *name;
2077 CORE_ADDR pc = frame_pc_unwind (next_frame);
2078
2079 find_pc_partial_function (pc, &name, NULL, NULL);
2080 if (PC_IN_SIGTRAMP (pc, name))
2081 return &ia64_sigtramp_frame_unwind;
2082
2083 return NULL;
2084}
2085\f
2086
2087static CORE_ADDR
2088ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2089{
2090 struct ia64_frame_cache *cache =
2091 ia64_frame_cache (next_frame, this_cache);
2092
2093 return cache->base;
2094}
2095
2096static const struct frame_base ia64_frame_base =
2097{
2098 &ia64_frame_unwind,
2099 ia64_frame_base_address,
2100 ia64_frame_base_address,
2101 ia64_frame_base_address
2102};
16461d7d
KB		 2103
2104/* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
2105 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
2106 and TYPE is the type (which is known to be struct, union or array). */
2107int
2108ia64_use_struct_convention (int gcc_p, struct type *type)
2109{
64a5b29c
KB		 2110 struct type *float_elt_type;
2111
2112 /* HFAs are structures (or arrays) consisting entirely of floating
2113 point values of the same length. Up to 8 of these are returned
2114 in registers. Don't use the struct convention when this is the
004d836a 2115 case. */
64a5b29c
KB		 2116 float_elt_type = is_float_or_hfa_type (type);
2117 if (float_elt_type != NULL
2118 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2119 return 0;
2120
2121 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 2122 Don't use the struct convention for those either. */
16461d7d
KB		 2123 return TYPE_LENGTH (type) > 32;
2124}
2125
2126void
004d836a 2127ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
16461d7d 2128{
64a5b29c
KB		 2129 struct type *float_elt_type;
2130
2131 float_elt_type = is_float_or_hfa_type (type);
2132 if (float_elt_type != NULL)
2133 {
004d836a 2134 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 2135 int offset = 0;
2136 int regnum = IA64_FR8_REGNUM;
2137 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2138
2139 while (n-- > 0)
2140 {
004d836a
JJ		 2141 regcache_cooked_read (regcache, regnum, from);
2142 convert_typed_floating (from, builtin_type_ia64_ext,
2143 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 2144 offset += TYPE_LENGTH (float_elt_type);
2145 regnum++;
2146 }
2147 }
16461d7d 2148 else
004d836a
JJ		 2149 {
2150 ULONGEST val;
2151 int offset = 0;
2152 int regnum = IA64_GR8_REGNUM;
2153 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2154 int n = TYPE_LENGTH (type) / reglen;
2155 int m = TYPE_LENGTH (type) % reglen;
16461d7d 2156
004d836a
JJ		 2157 while (n-- > 0)
2158 {
2159 ULONGEST val;
2160 regcache_cooked_read_unsigned (regcache, regnum, &val);
2161 memcpy ((char *)valbuf + offset, &val, reglen);
2162 offset += reglen;
2163 regnum++;
2164 }
16461d7d 2165
004d836a
JJ		 2166 if (m)
2167 {
2168 regcache_cooked_read_unsigned (regcache, regnum, &val);
2169 memcpy ((char *)valbuf + offset, &val, m);
2170 }
2171 }
16461d7d
KB		 2172}
2173
2174CORE_ADDR
004d836a 2175ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 2176{
004d836a
JJ		 2177 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2178 return 0;
16461d7d
KB		 2179}
2180
16461d7d 2181
64a5b29c
KB		 2182static int
2183is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2184{
2185 switch (TYPE_CODE (t))
2186 {
2187 case TYPE_CODE_FLT:
2188 if (*etp)
2189 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2190 else
2191 {
2192 *etp = t;
2193 return 1;
2194 }
2195 break;
2196 case TYPE_CODE_ARRAY:
98f96ba1
KB		 2197 return
2198 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2199 etp);
64a5b29c
KB		 2200 break;
2201 case TYPE_CODE_STRUCT:
2202 {
2203 int i;
2204
2205 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 2206 if (!is_float_or_hfa_type_recurse
2207 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 2208 return 0;
2209 return 1;
2210 }
2211 break;
2212 default:
2213 return 0;
2214 break;
2215 }
2216}
2217
2218/* Determine if the given type is one of the floating point types or
2219 and HFA (which is a struct, array, or combination thereof whose
004d836a 2220 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 2221
2222static struct type *
2223is_float_or_hfa_type (struct type *t)
2224{
2225 struct type *et = 0;
2226
2227 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2228}
2229
2230
98f96ba1
KB		 2231/* Return 1 if the alignment of T is such that the next even slot
2232 should be used. Return 0, if the next available slot should
2233 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 2234 and Runtime manual). */
98f96ba1
KB		 2235
2236static int
2237slot_alignment_is_next_even (struct type *t)
2238{
2239 switch (TYPE_CODE (t))
2240 {
2241 case TYPE_CODE_INT:
2242 case TYPE_CODE_FLT:
2243 if (TYPE_LENGTH (t) > 8)
2244 return 1;
2245 else
2246 return 0;
2247 case TYPE_CODE_ARRAY:
2248 return
2249 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2250 case TYPE_CODE_STRUCT:
2251 {
2252 int i;
2253
2254 for (i = 0; i < TYPE_NFIELDS (t); i++)
2255 if (slot_alignment_is_next_even
2256 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2257 return 1;
2258 return 0;
2259 }
2260 default:
2261 return 0;
2262 }
2263}
2264
64a5b29c
KB		 2265/* Attempt to find (and return) the global pointer for the given
2266 function.
2267
2268 This is a rather nasty bit of code searchs for the .dynamic section
2269 in the objfile corresponding to the pc of the function we're trying
2270 to call. Once it finds the addresses at which the .dynamic section
2271 lives in the child process, it scans the Elf64_Dyn entries for a
2272 DT_PLTGOT tag. If it finds one of these, the corresponding
2273 d_un.d_ptr value is the global pointer. */
2274
2275static CORE_ADDR
698cb3f0 2276generic_elf_find_global_pointer (CORE_ADDR faddr)
64a5b29c 2277{
76d689a6 2278 struct obj_section *faddr_sect;
64a5b29c 2279
76d689a6
KB		 2280 faddr_sect = find_pc_section (faddr);
2281 if (faddr_sect != NULL)
64a5b29c
KB		 2282 {
2283 struct obj_section *osect;
2284
76d689a6 2285 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 2286 {
2287 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2288 break;
2289 }
2290
76d689a6 2291 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 2292 {
2293 CORE_ADDR addr;
2294
2295 addr = osect->addr;
2296 while (addr < osect->endaddr)
2297 {
2298 int status;
2299 LONGEST tag;
2300 char buf[8];
2301
2302 status = target_read_memory (addr, buf, sizeof (buf));
2303 if (status != 0)
2304 break;
2305 tag = extract_signed_integer (buf, sizeof (buf));
2306
2307 if (tag == DT_PLTGOT)
2308 {
2309 CORE_ADDR global_pointer;
2310
2311 status = target_read_memory (addr + 8, buf, sizeof (buf));
2312 if (status != 0)
2313 break;
7c0b4a20 2314 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 2315
2316 /* The payoff... */
2317 return global_pointer;
2318 }
2319
2320 if (tag == DT_NULL)
2321 break;
2322
2323 addr += 16;
2324 }
2325 }
2326 }
2327 return 0;
2328}
2329
2330/* Given a function's address, attempt to find (and return) the
2331 corresponding (canonical) function descriptor. Return 0 if
004d836a 2332 not found. */
64a5b29c
KB		 2333static CORE_ADDR
2334find_extant_func_descr (CORE_ADDR faddr)
2335{
76d689a6 2336 struct obj_section *faddr_sect;
64a5b29c 2337
004d836a 2338 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 2339 faddr_sect = find_pc_section (faddr);
2340 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 2341 return faddr;
2342
76d689a6 2343 if (faddr_sect != NULL)
64a5b29c 2344 {
76d689a6
KB		 2345 struct obj_section *osect;
2346 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 2347 {
2348 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2349 break;
2350 }
2351
76d689a6 2352 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 2353 {
2354 CORE_ADDR addr;
2355
2356 addr = osect->addr;
2357 while (addr < osect->endaddr)
2358 {
2359 int status;
2360 LONGEST faddr2;
2361 char buf[8];
2362
2363 status = target_read_memory (addr, buf, sizeof (buf));
2364 if (status != 0)
2365 break;
2366 faddr2 = extract_signed_integer (buf, sizeof (buf));
2367
2368 if (faddr == faddr2)
2369 return addr;
2370
2371 addr += 16;
2372 }
2373 }
2374 }
2375 return 0;
2376}
2377
2378/* Attempt to find a function descriptor corresponding to the
2379 given address. If none is found, construct one on the
004d836a 2380 stack using the address at fdaptr. */
64a5b29c
KB		 2381
2382static CORE_ADDR
2383find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2384{
2385 CORE_ADDR fdesc;
2386
2387 fdesc = find_extant_func_descr (faddr);
2388
2389 if (fdesc == 0)
2390 {
2391 CORE_ADDR global_pointer;
2392 char buf[16];
2393
2394 fdesc = *fdaptr;
2395 *fdaptr += 16;
2396
698cb3f0 2397 global_pointer = FIND_GLOBAL_POINTER (faddr);
64a5b29c
KB		 2398
2399 if (global_pointer == 0)
2400 global_pointer = read_register (IA64_GR1_REGNUM);
2401
fbd9dcd3
AC		 2402 store_unsigned_integer (buf, 8, faddr);
2403 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 2404
2405 write_memory (fdesc, buf, 16);
2406 }
2407
2408 return fdesc;
2409}
16461d7d 2410
af8b88dd
JJ		 2411/* Use the following routine when printing out function pointers
2412 so the user can see the function address rather than just the
2413 function descriptor. */
2414static CORE_ADDR
e2d0e7eb
AC		 2415ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
2416 struct target_ops *targ)
af8b88dd
JJ		 2417{
2418 struct obj_section *s;
2419
2420 s = find_pc_section (addr);
2421
2422 /* check if ADDR points to a function descriptor. */
2423 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
2424 return read_memory_unsigned_integer (addr, 8);
2425
2426 return addr;
2427}
2428
a78f21af 2429static CORE_ADDR
004d836a
JJ		 2430ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2431{
2432 return sp & ~0xfLL;
2433}
2434
2435static CORE_ADDR
2436ia64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
8dd5115e
AS		 2437 struct regcache *regcache, CORE_ADDR bp_addr,
2438 int nargs, struct value **args, CORE_ADDR sp,
2439 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 2440{
2441 int argno;
ea7c478f 2442 struct value *arg;
16461d7d
KB		 2443 struct type *type;
2444 int len, argoffset;
64a5b29c 2445 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 2446 int floatreg;
004d836a 2447 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
16461d7d
KB		 2448
2449 nslots = 0;
64a5b29c 2450 nfuncargs = 0;
004d836a 2451 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 2452 for (argno = 0; argno < nargs; argno++)
2453 {
2454 arg = args[argno];
2455 type = check_typedef (VALUE_TYPE (arg));
2456 len = TYPE_LENGTH (type);
2457
98f96ba1 2458 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 2459 nslots++;
2460
64a5b29c
KB		 2461 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
2462 nfuncargs++;
2463
16461d7d
KB		 2464 nslots += (len + 7) / 8;
2465 }
2466
004d836a 2467 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 2468 rseslots = (nslots > 8) ? 8 : nslots;
2469 memslots = nslots - rseslots;
2470
004d836a
JJ		 2471 /* Allocate a new RSE frame. */
2472 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 2473
004d836a 2474 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 2475 new_bsp = rse_address_add (bsp, rseslots);
004d836a 2476 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 2477
004d836a 2478 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 2479 pfs &= 0xc000000000000000LL;
2480 pfs |= (cfm & 0xffffffffffffLL);
004d836a 2481 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 2482
2483 cfm &= 0xc000000000000000LL;
2484 cfm |= rseslots;
004d836a 2485 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 2486
64a5b29c
KB		 2487 /* We will attempt to find function descriptors in the .opd segment,
2488 but if we can't we'll construct them ourselves. That being the
004d836a 2489 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 2490 funcdescaddr = sp - nfuncargs * 16;
2491 funcdescaddr &= ~0xfLL;
2492
2493 /* Adjust the stack pointer to it's new value. The calling conventions
2494 require us to have 16 bytes of scratch, plus whatever space is
004d836a 2495 necessary for the memory slots and our function descriptors. */
64a5b29c 2496 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 2497 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 2498
64a5b29c
KB		 2499 /* Place the arguments where they belong. The arguments will be
2500 either placed in the RSE backing store or on the memory stack.
2501 In addition, floating point arguments or HFAs are placed in
004d836a 2502 floating point registers. */
16461d7d
KB		 2503 slotnum = 0;
2504 floatreg = IA64_FR8_REGNUM;
2505 for (argno = 0; argno < nargs; argno++)
2506 {
64a5b29c
KB		 2507 struct type *float_elt_type;
2508
16461d7d
KB		 2509 arg = args[argno];
2510 type = check_typedef (VALUE_TYPE (arg));
2511 len = TYPE_LENGTH (type);
64a5b29c 2512
004d836a 2513 /* Special handling for function parameters. */
64a5b29c
KB		 2514 if (len == 8
2515 && TYPE_CODE (type) == TYPE_CODE_PTR
2516 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
2517 {
2518 char val_buf[8];
2519
fbd9dcd3 2520 store_unsigned_integer (val_buf, 8,
7c0b4a20 2521 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
fbd9dcd3 2522 &funcdescaddr));
64a5b29c
KB		 2523 if (slotnum < rseslots)
2524 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2525 else
2526 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2527 slotnum++;
2528 continue;
2529 }
2530
004d836a 2531 /* Normal slots. */
98f96ba1
KB		 2532
2533 /* Skip odd slot if necessary... */
2534 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 2535 slotnum++;
98f96ba1 2536
16461d7d
KB		 2537 argoffset = 0;
2538 while (len > 0)
2539 {
2540 char val_buf[8];
2541
2542 memset (val_buf, 0, 8);
2543 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
2544
2545 if (slotnum < rseslots)
2546 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2547 else
2548 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2549
2550 argoffset += 8;
2551 len -= 8;
2552 slotnum++;
2553 }
64a5b29c 2554
004d836a 2555 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 2556 float_elt_type = is_float_or_hfa_type (type);
2557 if (float_elt_type != NULL)
2558 {
2559 argoffset = 0;
2560 len = TYPE_LENGTH (type);
2561 while (len > 0 && floatreg < IA64_FR16_REGNUM)
2562 {
004d836a
JJ		 2563 char to[MAX_REGISTER_SIZE];
2564 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
2565 to, builtin_type_ia64_ext);
2566 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 2567 floatreg++;
2568 argoffset += TYPE_LENGTH (float_elt_type);
2569 len -= TYPE_LENGTH (float_elt_type);
2570 }
16461d7d
KB		 2571 }
2572 }
2573
004d836a 2574 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 2575 if (struct_return)
2576 {
004d836a 2577 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 2578 }
2579
004d836a 2580 global_pointer = FIND_GLOBAL_POINTER (func_addr);
8dd5115e 2581
004d836a
JJ		 2582 if (global_pointer != 0)
2583 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 2584
004d836a 2585 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 2586
004d836a 2587 write_register (sp_regnum, sp);
16461d7d
KB		 2588
2589 return sp;
2590}
2591
004d836a
JJ		 2592static struct frame_id
2593ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 2594{
004d836a 2595 char buf[8];
4afcc598 2596 CORE_ADDR sp, bsp;
004d836a
JJ		 2597
2598 frame_unwind_register (next_frame, sp_regnum, buf);
2599 sp = extract_unsigned_integer (buf, 8);
2600
4afcc598
JJ		 2601 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2602 bsp = extract_unsigned_integer (buf, 8);
2603
2604 if (gdbarch_debug >= 1)
2605 fprintf_unfiltered (gdb_stdlog,
2606 "dummy frame id: code %lx, stack %lx, special %lx\n",
2607 frame_pc_unwind (next_frame), sp, bsp);
2608
2609 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 2610}
2611
004d836a
JJ		 2612static CORE_ADDR
2613ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 2614{
004d836a
JJ		 2615 char buf[8];
2616 CORE_ADDR ip, psr, pc;
2617
2618 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2619 ip = extract_unsigned_integer (buf, 8);
2620 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2621 psr = extract_unsigned_integer (buf, 8);
2622
2623 pc = (ip & ~0xf) | ((psr >> 41) & 3);
2624 return pc;
16461d7d
KB		 2625}
2626
2627static void
004d836a 2628ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
16461d7d 2629{
004d836a 2630 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 2631 {
004d836a
JJ		 2632 char to[MAX_REGISTER_SIZE];
2633 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
2634 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
2635 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 2636 }
2637 else
004d836a 2638 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 2639}
2640
2641static void
1750fa04
AC		 2642ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
2643 struct regcache *regcache,
2644 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 2645 CORE_ADDR *targ_addr, int *targ_len)
2646{
2647 *targ_addr = memaddr;
2648 *targ_len = nr_bytes;
2649}
2650
244bc108
KB		 2651static void
2652process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
2653{
2654 int *os_ident_ptr = obj;
2655 const char *name;
2656 unsigned int sectsize;
2657
2658 name = bfd_get_section_name (abfd, sect);
2659 sectsize = bfd_section_size (abfd, sect);
2660 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
2661 {
2662 unsigned int name_length, data_length, note_type;
2663 char *note = alloca (sectsize);
2664
2665 bfd_get_section_contents (abfd, sect, note,
2666 (file_ptr) 0, (bfd_size_type) sectsize);
2667
2668 name_length = bfd_h_get_32 (abfd, note);
2669 data_length = bfd_h_get_32 (abfd, note + 4);
2670 note_type = bfd_h_get_32 (abfd, note + 8);
2671
2672 if (name_length == 4 && data_length == 16 && note_type == 1
2673 && strcmp (note + 12, "GNU") == 0)
2674 {
2675 int os_number = bfd_h_get_32 (abfd, note + 16);
2676
004d836a 2677 /* The case numbers are from abi-tags in glibc. */
244bc108
KB		 2678 switch (os_number)
2679 {
2680 case 0 :
2681 *os_ident_ptr = ELFOSABI_LINUX;
2682 break;
244bc108
KB		 2683 case 1 :
2684 *os_ident_ptr = ELFOSABI_HURD;
2685 break;
2686 case 2 :
2687 *os_ident_ptr = ELFOSABI_SOLARIS;
2688 break;
244bc108 2689 default :
8e65ff28
AC		 2690 internal_error (__FILE__, __LINE__,
2691 "process_note_abi_sections: unknown OS number %d", os_number);
244bc108
KB		 2692 break;
2693 }
2694 }
2695 }
2696}
2697
6926787d
AS		 2698static int
2699ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
2700{
2701 info->bytes_per_line = SLOT_MULTIPLIER;
2702 return print_insn_ia64 (memaddr, info);
2703}
2704
16461d7d
KB		 2705static struct gdbarch *
2706ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2707{
2708 struct gdbarch *gdbarch;
244bc108 2709 struct gdbarch_tdep *tdep;
244bc108 2710
85bf2b91
JJ		 2711 /* If there is already a candidate, use it. */
2712 arches = gdbarch_list_lookup_by_info (arches, &info);
2713 if (arches != NULL)
2714 return arches->gdbarch;
16461d7d 2715
244bc108
KB		 2716 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2717 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 2718
d7fa2ae2
KB		 2719 /* Set the method of obtaining the sigcontext addresses at which
2720 registers are saved. The method of checking to see if
2721 native_find_global_pointer is nonzero to indicate that we're
2722 on AIX is kind of hokey, but I can't think of a better way
2723 to do it. */
85bf2b91 2724 if (info.osabi == GDB_OSABI_LINUX)
244bc108 2725 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
d7fa2ae2
KB		 2726 else if (native_find_global_pointer != 0)
2727 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
244bc108
KB		 2728 else
2729 tdep->sigcontext_register_address = 0;
16461d7d 2730
ca557f44
AC		 2731 /* We know that GNU/Linux won't have to resort to the
2732 native_find_global_pointer hackery. But that's the only one we
2733 know about so far, so if native_find_global_pointer is set to
2734 something non-zero, then use it. Otherwise fall back to using
2735 generic_elf_find_global_pointer. This arrangement should (in
2736 theory) allow us to cross debug GNU/Linux binaries from an AIX
2737 machine. */
85bf2b91 2738 if (info.osabi == GDB_OSABI_LINUX)
698cb3f0
KB		 2739 tdep->find_global_pointer = generic_elf_find_global_pointer;
2740 else if (native_find_global_pointer != 0)
2741 tdep->find_global_pointer = native_find_global_pointer;
2742 else
2743 tdep->find_global_pointer = generic_elf_find_global_pointer;
2744
004d836a
JJ		 2745 /* Define the ia64 floating-point format to gdb. */
2746 builtin_type_ia64_ext =
2747 init_type (TYPE_CODE_FLT, 128 / 8,
2748 0, "builtin_type_ia64_ext", NULL);
2749 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
2750
16461d7d
KB		 2751 set_gdbarch_short_bit (gdbarch, 16);
2752 set_gdbarch_int_bit (gdbarch, 32);
2753 set_gdbarch_long_bit (gdbarch, 64);
2754 set_gdbarch_long_long_bit (gdbarch, 64);
2755 set_gdbarch_float_bit (gdbarch, 32);
2756 set_gdbarch_double_bit (gdbarch, 64);
33c08150 2757 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 2758 set_gdbarch_ptr_bit (gdbarch, 64);
2759
004d836a
JJ		 2760 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
2761 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 2762 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 2763 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 2764
2765 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 2766 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2767 gets a number of extra failures. */
b1e29e33 2768 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 2769 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 2770
004d836a
JJ		 2771 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
2772 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
2773 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
2774 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
2775 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
2776 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
2777 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 2778
004d836a 2779 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d
KB		 2780
2781 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 2782 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 2783
004d836a
JJ		 2784 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
2785 set_gdbarch_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 2786
2787 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
2788 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
2789 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
2790 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
2791 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
2792
2793 /* Settings for calling functions in the inferior. */
8dd5115e 2794 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 2795 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
2796 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 2797
004d836a
JJ		 2798 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
2799 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
2800 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
2801 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 2802
2803 /* Settings that should be unnecessary. */
2804 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2805
16461d7d
KB		 2806 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2807 set_gdbarch_function_start_offset (gdbarch, 0);
4156bb53 2808 set_gdbarch_frame_args_skip (gdbarch, 0);
16461d7d
KB		 2809
2810 set_gdbarch_remote_translate_xfer_address (
2811 gdbarch, ia64_remote_translate_xfer_address);
2812
6926787d 2813 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 2814 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 2815
16461d7d
KB		 2816 return gdbarch;
2817}
2818
a78f21af
AC		 2819extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
2820
16461d7d
KB		 2821void
2822_initialize_ia64_tdep (void)
2823{
2824 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
16461d7d 2825}
GDB Binutils - Deliverables
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