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2005-06-08 Jeff Johnston <jjohnstn@redhat.com>
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
CommitLineData
16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
0fd88904 3 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
9fc9f5e2 4 Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
7d9b040b 40#include "infcall.h"
b33e8514 41#include "osabi.h"
9fc9f5e2 42#include "ia64-tdep.h"
16461d7d 43
968d1cb4 44#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 45#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
c5a27d9c
JJ		 48
49/* Note: KERNEL_START is supposed to be an address which is not going
50 to ever contain any valid unwind info. For ia64 linux, the choice
51 of 0xc000000000000000 is fairly safe since that's uncached space.
52
53 We use KERNEL_START as follows: after obtaining the kernel's
54 unwind table via getunwind(), we project its unwind data into
55 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
56 when ia64_access_mem() sees a memory access to this
57 address-range, we redirect it to ktab instead.
58
59 None of this hackery is needed with a modern kernel/libcs
60 which uses the kernel virtual DSO to provide access to the
61 kernel's unwind info. In that case, ktab_size remains 0 and
62 hence the value of KERNEL_START doesn't matter. */
63
64#define KERNEL_START 0xc000000000000000ULL
65
66static size_t ktab_size = 0;
67struct ia64_table_entry
68 {
69 uint64_t start_offset;
70 uint64_t end_offset;
71 uint64_t info_offset;
72 };
73
74static struct ia64_table_entry *ktab = NULL;
75
968d1cb4
JJ		 76#endif
77
698cb3f0
KB		 78/* An enumeration of the different IA-64 instruction types. */
79
16461d7d
KB		 80typedef enum instruction_type
81{
82 A, /* Integer ALU ; I-unit or M-unit */
83 I, /* Non-ALU integer; I-unit */
84 M, /* Memory ; M-unit */
85 F, /* Floating-point ; F-unit */
86 B, /* Branch ; B-unit */
87 L, /* Extended (L+X) ; I-unit */
88 X, /* Extended (L+X) ; I-unit */
89 undefined /* undefined or reserved */
90} instruction_type;
91
92/* We represent IA-64 PC addresses as the value of the instruction
93 pointer or'd with some bit combination in the low nibble which
94 represents the slot number in the bundle addressed by the
95 instruction pointer. The problem is that the Linux kernel
96 multiplies its slot numbers (for exceptions) by one while the
97 disassembler multiplies its slot numbers by 6. In addition, I've
98 heard it said that the simulator uses 1 as the multiplier.
99
100 I've fixed the disassembler so that the bytes_per_line field will
101 be the slot multiplier. If bytes_per_line comes in as zero, it
102 is set to six (which is how it was set up initially). -- objdump
103 displays pretty disassembly dumps with this value. For our purposes,
104 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
105 never want to also display the raw bytes the way objdump does. */
106
107#define SLOT_MULTIPLIER 1
108
109/* Length in bytes of an instruction bundle */
110
111#define BUNDLE_LEN 16
112
16461d7d
KB		 113static gdbarch_init_ftype ia64_gdbarch_init;
114
115static gdbarch_register_name_ftype ia64_register_name;
004d836a 116static gdbarch_register_type_ftype ia64_register_type;
16461d7d 117static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 118static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 119static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 120static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 121
004d836a
JJ		 122static struct type *builtin_type_ia64_ext;
123
124#define NUM_IA64_RAW_REGS 462
16461d7d 125
16461d7d
KB		 126static int sp_regnum = IA64_GR12_REGNUM;
127static int fp_regnum = IA64_VFP_REGNUM;
128static int lr_regnum = IA64_VRAP_REGNUM;
129
004d836a 130/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 131 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 132enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
133 V127_REGNUM = V32_REGNUM + 95,
134 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 135
136/* Array of register names; There should be ia64_num_regs strings in
137 the initializer. */
138
139static char *ia64_register_names[] =
140{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
143 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
16461d7d
KB		 156
157 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
158 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
159 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
160 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
161 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
162 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
163 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
164 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
165 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
166 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
167 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
168 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
169 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
170 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
171 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
172 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
173
004d836a
JJ		 174 "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
16461d7d
KB		 182
183 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
184
185 "vfp", "vrap",
186
187 "pr", "ip", "psr", "cfm",
188
189 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
190 "", "", "", "", "", "", "", "",
191 "rsc", "bsp", "bspstore", "rnat",
192 "", "fcr", "", "",
193 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
194 "ccv", "", "", "", "unat", "", "", "",
195 "fpsr", "", "", "", "itc",
196 "", "", "", "", "", "", "", "", "", "",
197 "", "", "", "", "", "", "", "", "",
198 "pfs", "lc", "ec",
199 "", "", "", "", "", "", "", "", "", "",
200 "", "", "", "", "", "", "", "", "", "",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "",
206 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
207 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
208 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
209 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
210 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
211 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
212 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
213 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
214 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
215 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
216 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
217 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
218 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
219 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
220 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
221 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 222
223 "bof",
224
225 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
226 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
227 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
228 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
229 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
230 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
231 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
232 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
233 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
234 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
235 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
236 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
237
238 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
239 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
240 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
241 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
242 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
243 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
244 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
245 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 246};
247
004d836a
JJ		 248struct ia64_frame_cache
249{
250 CORE_ADDR base; /* frame pointer base for frame */
251 CORE_ADDR pc; /* function start pc for frame */
252 CORE_ADDR saved_sp; /* stack pointer for frame */
253 CORE_ADDR bsp; /* points at r32 for the current frame */
254 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 255 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 256 int frameless;
257 int sof; /* Size of frame (decoded from cfm value) */
258 int sol; /* Size of locals (decoded from cfm value) */
259 int sor; /* Number of rotating registers. (decoded from cfm value) */
260 CORE_ADDR after_prologue;
261 /* Address of first instruction after the last
262 prologue instruction; Note that there may
263 be instructions from the function's body
264 intermingled with the prologue. */
265 int mem_stack_frame_size;
266 /* Size of the memory stack frame (may be zero),
267 or -1 if it has not been determined yet. */
268 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 269 for this frame. 0 if no register is being used
16461d7d 270 as the frame pointer. */
004d836a
JJ		 271
272 /* Saved registers. */
273 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
274
275};
244bc108 276
698cb3f0
KB		 277#define SIGCONTEXT_REGISTER_ADDRESS \
278 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 279
004d836a
JJ		 280int
281ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
282 struct reggroup *group)
16461d7d 283{
004d836a
JJ		 284 int vector_p;
285 int float_p;
286 int raw_p;
287 if (group == all_reggroup)
288 return 1;
289 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
290 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
291 raw_p = regnum < NUM_IA64_RAW_REGS;
292 if (group == float_reggroup)
293 return float_p;
294 if (group == vector_reggroup)
295 return vector_p;
296 if (group == general_reggroup)
297 return (!vector_p && !float_p);
298 if (group == save_reggroup || group == restore_reggroup)
299 return raw_p;
300 return 0;
16461d7d
KB		 301}
302
004d836a
JJ		 303static const char *
304ia64_register_name (int reg)
16461d7d 305{
004d836a 306 return ia64_register_names[reg];
16461d7d
KB		 307}
308
004d836a
JJ		 309struct type *
310ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 311{
004d836a
JJ		 312 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
313 return builtin_type_ia64_ext;
314 else
315 return builtin_type_long;
16461d7d
KB		 316}
317
a78f21af 318static int
004d836a 319ia64_dwarf_reg_to_regnum (int reg)
16461d7d 320{
004d836a
JJ		 321 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
322 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
323 return reg;
16461d7d
KB		 324}
325
4afcc598 326static int
7be0c536 327floatformat_valid (const struct floatformat *fmt, const char *from)
4afcc598
JJ		 328{
329 return 1;
330}
331
16461d7d
KB		 332const struct floatformat floatformat_ia64_ext =
333{
334 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 335 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 336};
337
16461d7d
KB		 338
339/* Extract ``len'' bits from an instruction bundle starting at
340 bit ``from''. */
341
244bc108 342static long long
16461d7d
KB		 343extract_bit_field (char *bundle, int from, int len)
344{
345 long long result = 0LL;
346 int to = from + len;
347 int from_byte = from / 8;
348 int to_byte = to / 8;
349 unsigned char *b = (unsigned char *) bundle;
350 unsigned char c;
351 int lshift;
352 int i;
353
354 c = b[from_byte];
355 if (from_byte == to_byte)
356 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
357 result = c >> (from % 8);
358 lshift = 8 - (from % 8);
359
360 for (i = from_byte+1; i < to_byte; i++)
361 {
362 result |= ((long long) b[i]) << lshift;
363 lshift += 8;
364 }
365
366 if (from_byte < to_byte && (to % 8 != 0))
367 {
368 c = b[to_byte];
369 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
370 result |= ((long long) c) << lshift;
371 }
372
373 return result;
374}
375
376/* Replace the specified bits in an instruction bundle */
377
244bc108 378static void
16461d7d
KB		 379replace_bit_field (char *bundle, long long val, int from, int len)
380{
381 int to = from + len;
382 int from_byte = from / 8;
383 int to_byte = to / 8;
384 unsigned char *b = (unsigned char *) bundle;
385 unsigned char c;
386
387 if (from_byte == to_byte)
388 {
389 unsigned char left, right;
390 c = b[from_byte];
391 left = (c >> (to % 8)) << (to % 8);
392 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
393 c = (unsigned char) (val & 0xff);
394 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
395 c |= right | left;
396 b[from_byte] = c;
397 }
398 else
399 {
400 int i;
401 c = b[from_byte];
402 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
403 c = c | (val << (from % 8));
404 b[from_byte] = c;
405 val >>= 8 - from % 8;
406
407 for (i = from_byte+1; i < to_byte; i++)
408 {
409 c = val & 0xff;
410 val >>= 8;
411 b[i] = c;
412 }
413
414 if (to % 8 != 0)
415 {
416 unsigned char cv = (unsigned char) val;
417 c = b[to_byte];
418 c = c >> (to % 8) << (to % 8);
419 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
420 b[to_byte] = c;
421 }
422 }
423}
424
425/* Return the contents of slot N (for N = 0, 1, or 2) in
426 and instruction bundle */
427
244bc108 428static long long
2fc3ac7e 429slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 430{
431 return extract_bit_field (bundle, 5+41*slotnum, 41);
432}
433
434/* Store an instruction in an instruction bundle */
435
244bc108 436static void
2fc3ac7e 437replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 438{
439 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
440}
441
64a5b29c 442static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 443{
444 { M, I, I }, /* 00 */
445 { M, I, I }, /* 01 */
446 { M, I, I }, /* 02 */
447 { M, I, I }, /* 03 */
448 { M, L, X }, /* 04 */
449 { M, L, X }, /* 05 */
450 { undefined, undefined, undefined }, /* 06 */
451 { undefined, undefined, undefined }, /* 07 */
452 { M, M, I }, /* 08 */
453 { M, M, I }, /* 09 */
454 { M, M, I }, /* 0A */
455 { M, M, I }, /* 0B */
456 { M, F, I }, /* 0C */
457 { M, F, I }, /* 0D */
458 { M, M, F }, /* 0E */
459 { M, M, F }, /* 0F */
460 { M, I, B }, /* 10 */
461 { M, I, B }, /* 11 */
462 { M, B, B }, /* 12 */
463 { M, B, B }, /* 13 */
464 { undefined, undefined, undefined }, /* 14 */
465 { undefined, undefined, undefined }, /* 15 */
466 { B, B, B }, /* 16 */
467 { B, B, B }, /* 17 */
468 { M, M, B }, /* 18 */
469 { M, M, B }, /* 19 */
470 { undefined, undefined, undefined }, /* 1A */
471 { undefined, undefined, undefined }, /* 1B */
472 { M, F, B }, /* 1C */
473 { M, F, B }, /* 1D */
474 { undefined, undefined, undefined }, /* 1E */
475 { undefined, undefined, undefined }, /* 1F */
476};
477
478/* Fetch and (partially) decode an instruction at ADDR and return the
479 address of the next instruction to fetch. */
480
481static CORE_ADDR
482fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
483{
484 char bundle[BUNDLE_LEN];
485 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
486 long long template;
487 int val;
488
c26e1c2b
KB		 489 /* Warn about slot numbers greater than 2. We used to generate
490 an error here on the assumption that the user entered an invalid
491 address. But, sometimes GDB itself requests an invalid address.
492 This can (easily) happen when execution stops in a function for
493 which there are no symbols. The prologue scanner will attempt to
494 find the beginning of the function - if the nearest symbol
495 happens to not be aligned on a bundle boundary (16 bytes), the
496 resulting starting address will cause GDB to think that the slot
497 number is too large.
498
499 So we warn about it and set the slot number to zero. It is
500 not necessarily a fatal condition, particularly if debugging
501 at the assembly language level. */
16461d7d 502 if (slotnum > 2)
c26e1c2b 503 {
8a3fe4f8
AC		 504 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
505 "Using slot 0 instead"));
c26e1c2b
KB		 506 slotnum = 0;
507 }
16461d7d
KB		 508
509 addr &= ~0x0f;
510
511 val = target_read_memory (addr, bundle, BUNDLE_LEN);
512
513 if (val != 0)
514 return 0;
515
516 *instr = slotN_contents (bundle, slotnum);
517 template = extract_bit_field (bundle, 0, 5);
518 *it = template_encoding_table[(int)template][slotnum];
519
64a5b29c 520 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 521 addr += 16;
522 else
523 addr += (slotnum + 1) * SLOT_MULTIPLIER;
524
525 return addr;
526}
527
528/* There are 5 different break instructions (break.i, break.b,
529 break.m, break.f, and break.x), but they all have the same
530 encoding. (The five bit template in the low five bits of the
531 instruction bundle distinguishes one from another.)
532
533 The runtime architecture manual specifies that break instructions
534 used for debugging purposes must have the upper two bits of the 21
535 bit immediate set to a 0 and a 1 respectively. A breakpoint
536 instruction encodes the most significant bit of its 21 bit
537 immediate at bit 36 of the 41 bit instruction. The penultimate msb
538 is at bit 25 which leads to the pattern below.
539
540 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
541 it turns out that 0x80000 was used as the syscall break in the early
542 simulators. So I changed the pattern slightly to do "break.i 0x080001"
543 instead. But that didn't work either (I later found out that this
544 pattern was used by the simulator that I was using.) So I ended up
545 using the pattern seen below. */
546
547#if 0
aaab4dba 548#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 549#endif
aaab4dba 550#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 551
552static int
5a168c78 553ia64_memory_insert_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache)
16461d7d
KB		 554{
555 char bundle[BUNDLE_LEN];
556 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
557 long long instr;
558 int val;
126fa72d 559 int template;
16461d7d
KB		 560
561 if (slotnum > 2)
8a3fe4f8 562 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 563
564 addr &= ~0x0f;
565
566 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 567
568 /* Check for L type instruction in 2nd slot, if present then
569 bump up the slot number to the 3rd slot */
570 template = extract_bit_field (bundle, 0, 5);
571 if (slotnum == 1 && template_encoding_table[template][1] == L)
572 {
573 slotnum = 2;
574 }
575
16461d7d
KB		 576 instr = slotN_contents (bundle, slotnum);
577 memcpy(contents_cache, &instr, sizeof(instr));
aaab4dba 578 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 579 if (val == 0)
580 target_write_memory (addr, bundle, BUNDLE_LEN);
581
582 return val;
583}
584
585static int
5a168c78 586ia64_memory_remove_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache)
16461d7d
KB		 587{
588 char bundle[BUNDLE_LEN];
589 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
590 long long instr;
591 int val;
126fa72d 592 int template;
16461d7d
KB		 593
594 addr &= ~0x0f;
595
596 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 597
598 /* Check for L type instruction in 2nd slot, if present then
599 bump up the slot number to the 3rd slot */
600 template = extract_bit_field (bundle, 0, 5);
601 if (slotnum == 1 && template_encoding_table[template][1] == L)
602 {
603 slotnum = 2;
604 }
605
16461d7d
KB		 606 memcpy (&instr, contents_cache, sizeof instr);
607 replace_slotN_contents (bundle, instr, slotnum);
608 if (val == 0)
609 target_write_memory (addr, bundle, BUNDLE_LEN);
610
611 return val;
612}
613
614/* We don't really want to use this, but remote.c needs to call it in order
615 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 616const unsigned char *
fba45db2 617ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 618{
619 static unsigned char breakpoint[] =
620 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
621 *lenptr = sizeof (breakpoint);
622#if 0
623 *pcptr &= ~0x0f;
624#endif
625 return breakpoint;
626}
627
a78f21af 628static CORE_ADDR
39f77062 629ia64_read_pc (ptid_t ptid)
16461d7d 630{
39f77062
KB		 631 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
632 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 633 int slot_num = (psr_value >> 41) & 3;
634
635 return pc_value | (slot_num * SLOT_MULTIPLIER);
636}
637
54a5c8d8 638void
39f77062 639ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 640{
641 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 642 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 643 psr_value &= ~(3LL << 41);
644 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
645
646 new_pc &= ~0xfLL;
647
39f77062
KB		 648 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
649 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 650}
651
652#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
653
654/* Returns the address of the slot that's NSLOTS slots away from
655 the address ADDR. NSLOTS may be positive or negative. */
656static CORE_ADDR
657rse_address_add(CORE_ADDR addr, int nslots)
658{
659 CORE_ADDR new_addr;
660 int mandatory_nat_slots = nslots / 63;
661 int direction = nslots < 0 ? -1 : 1;
662
663 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
664
665 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
666 new_addr += 8 * direction;
667
668 if (IS_NaT_COLLECTION_ADDR(new_addr))
669 new_addr += 8 * direction;
670
671 return new_addr;
672}
673
004d836a
JJ		 674static void
675ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
676 int regnum, void *buf)
16461d7d 677{
004d836a 678 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 679 {
c5a27d9c
JJ		 680 /* First try and use the libunwind special reg accessor, otherwise fallback to
681 standard logic. */
682 if (!libunwind_is_initialized ()
683 || libunwind_get_reg_special (gdbarch, regnum, buf) != 0)
004d836a 684 {
c5a27d9c
JJ		 685 /* The fallback position is to assume that r32-r127 are found sequentially
686 in memory starting at $bof. This isn't always true, but without libunwind,
687 this is the best we can do. */
688 ULONGEST cfm;
689 ULONGEST bsp;
690 CORE_ADDR reg;
691 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
692 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
693
694 /* The bsp points at the end of the register frame so we
695 subtract the size of frame from it to get start of register frame. */
696 bsp = rse_address_add (bsp, -(cfm & 0x7f));
697
698 if ((cfm & 0x7f) > regnum - V32_REGNUM)
699 {
700 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
701 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
702 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
703 }
704 else
705 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a 706 }
004d836a
JJ		 707 }
708 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
709 {
710 ULONGEST unatN_val;
711 ULONGEST unat;
712 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
713 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 714 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 715 }
716 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
717 {
718 ULONGEST natN_val = 0;
719 ULONGEST bsp;
720 ULONGEST cfm;
721 CORE_ADDR gr_addr = 0;
722 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
723 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
724
725 /* The bsp points at the end of the register frame so we
726 subtract the size of frame from it to get start of register frame. */
727 bsp = rse_address_add (bsp, -(cfm & 0x7f));
728
729 if ((cfm & 0x7f) > regnum - V32_REGNUM)
730 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
731
732 if (gr_addr != 0)
733 {
734 /* Compute address of nat collection bits. */
735 CORE_ADDR nat_addr = gr_addr | 0x1f8;
736 CORE_ADDR nat_collection;
737 int nat_bit;
738 /* If our nat collection address is bigger than bsp, we have to get
739 the nat collection from rnat. Otherwise, we fetch the nat
740 collection from the computed address. */
741 if (nat_addr >= bsp)
742 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
743 else
744 nat_collection = read_memory_integer (nat_addr, 8);
745 nat_bit = (gr_addr >> 3) & 0x3f;
746 natN_val = (nat_collection >> nat_bit) & 1;
747 }
748
aa2a9a3c 749 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 750 }
004d836a
JJ		 751 else if (regnum == VBOF_REGNUM)
752 {
753 /* A virtual register frame start is provided for user convenience.
754 It can be calculated as the bsp - sof (sizeof frame). */
755 ULONGEST bsp, vbsp;
756 ULONGEST cfm;
757 CORE_ADDR reg;
758 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
759 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
760
761 /* The bsp points at the end of the register frame so we
762 subtract the size of frame from it to get beginning of frame. */
763 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 764 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 765 }
766 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
767 {
768 ULONGEST pr;
769 ULONGEST cfm;
770 ULONGEST prN_val;
771 CORE_ADDR reg;
772 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
773 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
774
775 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
776 {
777 /* Fetch predicate register rename base from current frame
778 marker for this frame. */
779 int rrb_pr = (cfm >> 32) & 0x3f;
780
781 /* Adjust the register number to account for register rotation. */
782 regnum = VP16_REGNUM
783 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
784 }
785 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 786 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 787 }
788 else
aa2a9a3c 789 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 790}
791
004d836a
JJ		 792static void
793ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
794 int regnum, const void *buf)
16461d7d 795{
004d836a 796 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 797 {
004d836a
JJ		 798 ULONGEST bsp;
799 ULONGEST cfm;
800 CORE_ADDR reg;
801 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
802 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
803
804 bsp = rse_address_add (bsp, -(cfm & 0x7f));
805
806 if ((cfm & 0x7f) > regnum - V32_REGNUM)
807 {
808 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
809 write_memory (reg_addr, (void *)buf, 8);
810 }
811 }
812 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
813 {
814 ULONGEST unatN_val, unat, unatN_mask;
815 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 816 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 817 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
818 if (unatN_val == 0)
819 unat &= ~unatN_mask;
820 else if (unatN_val == 1)
821 unat |= unatN_mask;
822 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
823 }
824 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
825 {
826 ULONGEST natN_val;
827 ULONGEST bsp;
828 ULONGEST cfm;
829 CORE_ADDR gr_addr = 0;
830 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
831 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
832
833 /* The bsp points at the end of the register frame so we
834 subtract the size of frame from it to get start of register frame. */
835 bsp = rse_address_add (bsp, -(cfm & 0x7f));
836
837 if ((cfm & 0x7f) > regnum - V32_REGNUM)
838 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
839
aa2a9a3c 840 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 841
842 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
843 {
844 /* Compute address of nat collection bits. */
845 CORE_ADDR nat_addr = gr_addr | 0x1f8;
846 CORE_ADDR nat_collection;
847 int natN_bit = (gr_addr >> 3) & 0x3f;
848 ULONGEST natN_mask = (1LL << natN_bit);
849 /* If our nat collection address is bigger than bsp, we have to get
850 the nat collection from rnat. Otherwise, we fetch the nat
851 collection from the computed address. */
852 if (nat_addr >= bsp)
853 {
854 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
855 if (natN_val)
856 nat_collection |= natN_mask;
857 else
858 nat_collection &= ~natN_mask;
859 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
860 }
861 else
862 {
863 char nat_buf[8];
864 nat_collection = read_memory_integer (nat_addr, 8);
865 if (natN_val)
866 nat_collection |= natN_mask;
867 else
868 nat_collection &= ~natN_mask;
aa2a9a3c 869 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 870 write_memory (nat_addr, nat_buf, 8);
871 }
872 }
873 }
874 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
875 {
876 ULONGEST pr;
877 ULONGEST cfm;
878 ULONGEST prN_val;
879 ULONGEST prN_mask;
880
881 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
882 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
883
884 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
885 {
886 /* Fetch predicate register rename base from current frame
887 marker for this frame. */
888 int rrb_pr = (cfm >> 32) & 0x3f;
889
890 /* Adjust the register number to account for register rotation. */
891 regnum = VP16_REGNUM
892 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
893 }
aa2a9a3c 894 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 895 prN_mask = (1LL << (regnum - VP0_REGNUM));
896 if (prN_val == 0)
897 pr &= ~prN_mask;
898 else if (prN_val == 1)
899 pr |= prN_mask;
900 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 901 }
16461d7d
KB		 902}
903
004d836a
JJ		 904/* The ia64 needs to convert between various ieee floating-point formats
905 and the special ia64 floating point register format. */
906
907static int
908ia64_convert_register_p (int regno, struct type *type)
909{
910 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
911}
912
913static void
914ia64_register_to_value (struct frame_info *frame, int regnum,
915 struct type *valtype, void *out)
916{
917 char in[MAX_REGISTER_SIZE];
918 frame_register_read (frame, regnum, in);
919 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
920}
921
922static void
923ia64_value_to_register (struct frame_info *frame, int regnum,
924 struct type *valtype, const void *in)
925{
926 char out[MAX_REGISTER_SIZE];
927 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
928 put_frame_register (frame, regnum, out);
929}
930
931
58ab00f9
KB		 932/* Limit the number of skipped non-prologue instructions since examining
933 of the prologue is expensive. */
5ea2bd7f 934static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 935
936/* Given PC representing the starting address of a function, and
937 LIM_PC which is the (sloppy) limit to which to scan when looking
938 for a prologue, attempt to further refine this limit by using
939 the line data in the symbol table. If successful, a better guess
940 on where the prologue ends is returned, otherwise the previous
941 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
942 which will be set to indicate whether the returned limit may be
943 used with no further scanning in the event that the function is
944 frameless. */
945
634aa483
AC		 946/* FIXME: cagney/2004-02-14: This function and logic have largely been
947 superseded by skip_prologue_using_sal. */
948
58ab00f9
KB		 949static CORE_ADDR
950refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
951{
952 struct symtab_and_line prologue_sal;
953 CORE_ADDR start_pc = pc;
954
955 /* Start off not trusting the limit. */
956 *trust_limit = 0;
957
958 prologue_sal = find_pc_line (pc, 0);
959 if (prologue_sal.line != 0)
960 {
961 int i;
962 CORE_ADDR addr = prologue_sal.end;
963
964 /* Handle the case in which compiler's optimizer/scheduler
965 has moved instructions into the prologue. We scan ahead
966 in the function looking for address ranges whose corresponding
967 line number is less than or equal to the first one that we
968 found for the function. (It can be less than when the
969 scheduler puts a body instruction before the first prologue
970 instruction.) */
971 for (i = 2 * max_skip_non_prologue_insns;
972 i > 0 && (lim_pc == 0 || addr < lim_pc);
973 i--)
974 {
975 struct symtab_and_line sal;
976
977 sal = find_pc_line (addr, 0);
978 if (sal.line == 0)
979 break;
980 if (sal.line <= prologue_sal.line
981 && sal.symtab == prologue_sal.symtab)
982 {
983 prologue_sal = sal;
984 }
985 addr = sal.end;
986 }
987
988 if (lim_pc == 0 || prologue_sal.end < lim_pc)
989 {
990 lim_pc = prologue_sal.end;
991 if (start_pc == get_pc_function_start (lim_pc))
992 *trust_limit = 1;
993 }
994 }
995 return lim_pc;
996}
997
16461d7d
KB		 998#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
999 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1000 || (14 <= (_regnum_) && (_regnum_) <= 31))
1001#define imm9(_instr_) \
1002 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1003 | (((_instr_) & 0x00008000000LL) >> 20) \
1004 | (((_instr_) & 0x00000001fc0LL) >> 6))
1005
004d836a
JJ		 1006/* Allocate and initialize a frame cache. */
1007
1008static struct ia64_frame_cache *
1009ia64_alloc_frame_cache (void)
1010{
1011 struct ia64_frame_cache *cache;
1012 int i;
1013
1014 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1015
1016 /* Base address. */
1017 cache->base = 0;
1018 cache->pc = 0;
1019 cache->cfm = 0;
4afcc598 1020 cache->prev_cfm = 0;
004d836a
JJ		 1021 cache->sof = 0;
1022 cache->sol = 0;
1023 cache->sor = 0;
1024 cache->bsp = 0;
1025 cache->fp_reg = 0;
1026 cache->frameless = 1;
1027
1028 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1029 cache->saved_regs[i] = 0;
1030
1031 return cache;
1032}
1033
16461d7d 1034static CORE_ADDR
004d836a 1035examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1036{
1037 CORE_ADDR next_pc;
1038 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1039 instruction_type it;
1040 long long instr;
16461d7d
KB		 1041 int cfm_reg = 0;
1042 int ret_reg = 0;
1043 int fp_reg = 0;
1044 int unat_save_reg = 0;
1045 int pr_save_reg = 0;
1046 int mem_stack_frame_size = 0;
1047 int spill_reg = 0;
1048 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1049 char instores[8];
1050 char infpstores[8];
5ea2bd7f 1051 char reg_contents[256];
58ab00f9 1052 int trust_limit;
004d836a
JJ		 1053 int frameless = 1;
1054 int i;
1055 CORE_ADDR addr;
1056 char buf[8];
1057 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1058
1059 memset (instores, 0, sizeof instores);
1060 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1061 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1062
004d836a
JJ		 1063 if (cache->after_prologue != 0
1064 && cache->after_prologue <= lim_pc)
1065 return cache->after_prologue;
16461d7d 1066
58ab00f9 1067 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1068 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1069
1070 /* We want to check if we have a recognizable function start before we
1071 look ahead for a prologue. */
16461d7d
KB		 1072 if (pc < lim_pc && next_pc
1073 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1074 {
5ea2bd7f 1075 /* alloc - start of a regular function. */
16461d7d
KB		 1076 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1077 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1078 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1079 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1080
1081 /* Verify that the current cfm matches what we think is the
1082 function start. If we have somehow jumped within a function,
1083 we do not want to interpret the prologue and calculate the
1084 addresses of various registers such as the return address.
1085 We will instead treat the frame as frameless. */
1086 if (!next_frame ||
1087 (sof == (cache->cfm & 0x7f) &&
1088 sol == ((cache->cfm >> 7) & 0x7f)))
1089 frameless = 0;
1090
16461d7d
KB		 1091 cfm_reg = rN;
1092 last_prologue_pc = next_pc;
1093 pc = next_pc;
1094 }
1095 else
58ab00f9 1096 {
5ea2bd7f
JJ		 1097 /* Look for a leaf routine. */
1098 if (pc < lim_pc && next_pc
1099 && (it == I || it == M)
1100 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1101 {
1102 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1103 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1104 | ((instr & 0x001f8000000LL) >> 20)
1105 | ((instr & 0x000000fe000LL) >> 13));
1106 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1107 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1108 int qp = (int) (instr & 0x0000000003fLL);
1109 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1110 {
1111 /* mov r2, r12 - beginning of leaf routine */
1112 fp_reg = rN;
5ea2bd7f
JJ		 1113 last_prologue_pc = next_pc;
1114 }
1115 }
1116
1117 /* If we don't recognize a regular function or leaf routine, we are
1118 done. */
1119 if (!fp_reg)
1120 {
1121 pc = lim_pc;
1122 if (trust_limit)
1123 last_prologue_pc = lim_pc;
1124 }
58ab00f9 1125 }
16461d7d
KB		 1126
1127 /* Loop, looking for prologue instructions, keeping track of
1128 where preserved registers were spilled. */
1129 while (pc < lim_pc)
1130 {
1131 next_pc = fetch_instruction (pc, &it, &instr);
1132 if (next_pc == 0)
1133 break;
1134
594706e6 1135 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1136 {
102d615a
JJ		 1137 /* Exit loop upon hitting a non-nop branch instruction. */
1138 if (trust_limit)
1139 lim_pc = pc;
1140 break;
1141 }
1142 else if (((instr & 0x3fLL) != 0LL) &&
1143 (frameless || ret_reg != 0))
1144 {
1145 /* Exit loop upon hitting a predicated instruction if
1146 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1147 if (trust_limit)
1148 lim_pc = pc;
0927a22b
KB		 1149 break;
1150 }
1151 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1152 {
1153 /* Move from BR */
1154 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1155 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1156 int qp = (int) (instr & 0x0000000003f);
1157
1158 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1159 {
1160 ret_reg = rN;
1161 last_prologue_pc = next_pc;
1162 }
1163 }
1164 else if ((it == I || it == M)
1165 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1166 {
1167 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1168 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1169 | ((instr & 0x001f8000000LL) >> 20)
1170 | ((instr & 0x000000fe000LL) >> 13));
1171 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1172 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1173 int qp = (int) (instr & 0x0000000003fLL);
1174
1175 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1176 {
1177 /* mov rN, r12 */
1178 fp_reg = rN;
1179 last_prologue_pc = next_pc;
1180 }
1181 else if (qp == 0 && rN == 12 && rM == 12)
1182 {
1183 /* adds r12, -mem_stack_frame_size, r12 */
1184 mem_stack_frame_size -= imm;
1185 last_prologue_pc = next_pc;
1186 }
1187 else if (qp == 0 && rN == 2
1188 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1189 {
004d836a
JJ		 1190 char buf[MAX_REGISTER_SIZE];
1191 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1192 /* adds r2, spilloffset, rFramePointer
1193 or
1194 adds r2, spilloffset, r12
1195
1196 Get ready for stf.spill or st8.spill instructions.
1197 The address to start spilling at is loaded into r2.
1198 FIXME: Why r2? That's what gcc currently uses; it
1199 could well be different for other compilers. */
1200
1201 /* Hmm... whether or not this will work will depend on
1202 where the pc is. If it's still early in the prologue
1203 this'll be wrong. FIXME */
004d836a
JJ		 1204 if (next_frame)
1205 {
1206 frame_unwind_register (next_frame, sp_regnum, buf);
1207 saved_sp = extract_unsigned_integer (buf, 8);
1208 }
1209 spill_addr = saved_sp
16461d7d
KB		 1210 + (rM == 12 ? 0 : mem_stack_frame_size)
1211 + imm;
1212 spill_reg = rN;
1213 last_prologue_pc = next_pc;
1214 }
5ea2bd7f
JJ		 1215 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1216 rN < 256 && imm == 0)
1217 {
1218 /* mov rN, rM where rM is an input register */
1219 reg_contents[rN] = rM;
1220 last_prologue_pc = next_pc;
1221 }
1222 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1223 rM == 2)
1224 {
1225 /* mov r12, r2 */
1226 last_prologue_pc = next_pc;
1227 break;
1228 }
16461d7d
KB		 1229 }
1230 else if (it == M
1231 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1232 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1233 {
1234 /* stf.spill [rN] = fM, imm9
1235 or
1236 stf.spill [rN] = fM */
1237
1238 int imm = imm9(instr);
1239 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1240 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1241 int qp = (int) (instr & 0x0000000003fLL);
1242 if (qp == 0 && rN == spill_reg && spill_addr != 0
1243 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1244 {
004d836a 1245 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1246
594706e6 1247 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1248 spill_addr += imm;
1249 else
1250 spill_addr = 0; /* last one; must be done */
1251 last_prologue_pc = next_pc;
1252 }
1253 }
1254 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1255 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1256 {
1257 /* mov.m rN = arM
1258 or
1259 mov.i rN = arM */
1260
1261 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1262 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1263 int qp = (int) (instr & 0x0000000003fLL);
1264 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1265 {
1266 /* We have something like "mov.m r3 = ar.unat". Remember the
1267 r3 (or whatever) and watch for a store of this register... */
1268 unat_save_reg = rN;
1269 last_prologue_pc = next_pc;
1270 }
1271 }
1272 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1273 {
1274 /* mov rN = pr */
1275 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1276 int qp = (int) (instr & 0x0000000003fLL);
1277 if (qp == 0 && isScratch (rN))
1278 {
1279 pr_save_reg = rN;
1280 last_prologue_pc = next_pc;
1281 }
1282 }
1283 else if (it == M
1284 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1285 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1286 {
1287 /* st8 [rN] = rM
1288 or
1289 st8 [rN] = rM, imm9 */
1290 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1291 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1292 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1293 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1294 if (qp == 0 && rN == spill_reg && spill_addr != 0
1295 && (rM == unat_save_reg || rM == pr_save_reg))
1296 {
1297 /* We've found a spill of either the UNAT register or the PR
1298 register. (Well, not exactly; what we've actually found is
1299 a spill of the register that UNAT or PR was moved to).
1300 Record that fact and move on... */
1301 if (rM == unat_save_reg)
1302 {
1303 /* Track UNAT register */
004d836a 1304 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1305 unat_save_reg = 0;
1306 }
1307 else
1308 {
1309 /* Track PR register */
004d836a 1310 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1311 pr_save_reg = 0;
1312 }
1313 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1314 /* st8 [rN] = rM, imm9 */
1315 spill_addr += imm9(instr);
1316 else
1317 spill_addr = 0; /* must be done spilling */
1318 last_prologue_pc = next_pc;
1319 }
0927a22b
KB		 1320 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1321 {
1322 /* Allow up to one store of each input register. */
1323 instores[rM-32] = 1;
1324 last_prologue_pc = next_pc;
1325 }
5ea2bd7f
JJ		 1326 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1327 !instores[indirect-32])
1328 {
1329 /* Allow an indirect store of an input register. */
1330 instores[indirect-32] = 1;
1331 last_prologue_pc = next_pc;
1332 }
0927a22b
KB		 1333 }
1334 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1335 {
1336 /* One of
1337 st1 [rN] = rM
1338 st2 [rN] = rM
1339 st4 [rN] = rM
1340 st8 [rN] = rM
1341 Note that the st8 case is handled in the clause above.
1342
1343 Advance over stores of input registers. One store per input
1344 register is permitted. */
1345 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1346 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1347 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1348 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1349 {
1350 instores[rM-32] = 1;
1351 last_prologue_pc = next_pc;
1352 }
5ea2bd7f
JJ		 1353 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1354 !instores[indirect-32])
1355 {
1356 /* Allow an indirect store of an input register. */
1357 instores[indirect-32] = 1;
1358 last_prologue_pc = next_pc;
1359 }
0927a22b
KB		 1360 }
1361 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1362 {
1363 /* Either
1364 stfs [rN] = fM
1365 or
1366 stfd [rN] = fM
1367
1368 Advance over stores of floating point input registers. Again
1369 one store per register is permitted */
1370 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1371 int qp = (int) (instr & 0x0000000003fLL);
1372 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1373 {
1374 infpstores[fM-8] = 1;
1375 last_prologue_pc = next_pc;
1376 }
16461d7d
KB		 1377 }
1378 else if (it == M
1379 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1380 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1381 {
1382 /* st8.spill [rN] = rM
1383 or
1384 st8.spill [rN] = rM, imm9 */
1385 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1386 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1387 int qp = (int) (instr & 0x0000000003fLL);
1388 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1389 {
1390 /* We've found a spill of one of the preserved general purpose
1391 regs. Record the spill address and advance the spill
1392 register if appropriate. */
004d836a 1393 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1394 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1395 /* st8.spill [rN] = rM, imm9 */
1396 spill_addr += imm9(instr);
1397 else
1398 spill_addr = 0; /* Done spilling */
1399 last_prologue_pc = next_pc;
1400 }
1401 }
16461d7d
KB		 1402
1403 pc = next_pc;
1404 }
1405
004d836a
JJ		 1406 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1407 registers for the previous frame which will be needed later. */
16461d7d 1408
004d836a 1409 if (!frameless && next_frame)
da50a4b7 1410 {
004d836a
JJ		 1411 /* Extract the size of the rotating portion of the stack
1412 frame and the register rename base from the current
1413 frame marker. */
1414 cfm = cache->cfm;
1415 sor = cache->sor;
1416 sof = cache->sof;
1417 sol = cache->sol;
1418 rrb_gr = (cfm >> 18) & 0x7f;
1419
1420 /* Find the bof (beginning of frame). */
1421 bof = rse_address_add (cache->bsp, -sof);
1422
1423 for (i = 0, addr = bof;
1424 i < sof;
1425 i++, addr += 8)
1426 {
1427 if (IS_NaT_COLLECTION_ADDR (addr))
1428 {
1429 addr += 8;
1430 }
1431 if (i+32 == cfm_reg)
1432 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1433 if (i+32 == ret_reg)
1434 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1435 if (i+32 == fp_reg)
1436 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1437 }
16461d7d 1438
004d836a
JJ		 1439 /* For the previous argument registers we require the previous bof.
1440 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1441 cfm = 0;
004d836a
JJ		 1442 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1443 {
1444 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1445 }
1446 else if (cfm_reg != 0)
1447 {
1448 frame_unwind_register (next_frame, cfm_reg, buf);
1449 cfm = extract_unsigned_integer (buf, 8);
1450 }
1451 cache->prev_cfm = cfm;
1452
1453 if (cfm != 0)
1454 {
004d836a
JJ		 1455 sor = ((cfm >> 14) & 0xf) * 8;
1456 sof = (cfm & 0x7f);
1457 sol = (cfm >> 7) & 0x7f;
1458 rrb_gr = (cfm >> 18) & 0x7f;
1459
1460 /* The previous bof only requires subtraction of the sol (size of locals)
1461 due to the overlap between output and input of subsequent frames. */
1462 bof = rse_address_add (bof, -sol);
1463
1464 for (i = 0, addr = bof;
1465 i < sof;
1466 i++, addr += 8)
1467 {
1468 if (IS_NaT_COLLECTION_ADDR (addr))
1469 {
1470 addr += 8;
1471 }
1472 if (i < sor)
1473 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1474 = addr;
1475 else
1476 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1477 }
1478
1479 }
1480 }
1481
5ea2bd7f
JJ		 1482 /* Try and trust the lim_pc value whenever possible. */
1483 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1484 last_prologue_pc = lim_pc;
1485
1486 cache->frameless = frameless;
1487 cache->after_prologue = last_prologue_pc;
1488 cache->mem_stack_frame_size = mem_stack_frame_size;
1489 cache->fp_reg = fp_reg;
5ea2bd7f 1490
16461d7d
KB		 1491 return last_prologue_pc;
1492}
1493
1494CORE_ADDR
1495ia64_skip_prologue (CORE_ADDR pc)
1496{
004d836a
JJ		 1497 struct ia64_frame_cache cache;
1498 cache.base = 0;
1499 cache.after_prologue = 0;
1500 cache.cfm = 0;
1501 cache.bsp = 0;
1502
1503 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1504 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1505}
1506
004d836a
JJ		 1507
1508/* Normal frames. */
1509
1510static struct ia64_frame_cache *
1511ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1512{
004d836a
JJ		 1513 struct ia64_frame_cache *cache;
1514 char buf[8];
1515 CORE_ADDR cfm, sof, sol, bsp, psr;
1516 int i;
16461d7d 1517
004d836a
JJ		 1518 if (*this_cache)
1519 return *this_cache;
16461d7d 1520
004d836a
JJ		 1521 cache = ia64_alloc_frame_cache ();
1522 *this_cache = cache;
16461d7d 1523
004d836a
JJ		 1524 frame_unwind_register (next_frame, sp_regnum, buf);
1525 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1526
004d836a
JJ		 1527 /* We always want the bsp to point to the end of frame.
1528 This way, we can always get the beginning of frame (bof)
1529 by subtracting frame size. */
1530 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1531 cache->bsp = extract_unsigned_integer (buf, 8);
1532
1533 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1534 psr = extract_unsigned_integer (buf, 8);
1535
1536 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1537 cfm = extract_unsigned_integer (buf, 8);
1538
1539 cache->sof = (cfm & 0x7f);
1540 cache->sol = (cfm >> 7) & 0x7f;
1541 cache->sor = ((cfm >> 14) & 0xf) * 8;
1542
1543 cache->cfm = cfm;
1544
1545 cache->pc = frame_func_unwind (next_frame);
1546
1547 if (cache->pc != 0)
1548 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1549
1550 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1551
1552 return cache;
16461d7d
KB		 1553}
1554
a78f21af 1555static void
004d836a
JJ		 1556ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1557 struct frame_id *this_id)
16461d7d 1558{
004d836a
JJ		 1559 struct ia64_frame_cache *cache =
1560 ia64_frame_cache (next_frame, this_cache);
16461d7d 1561
c5a27d9c 1562 /* If outermost frame, mark with null frame id. */
004d836a 1563 if (cache->base == 0)
c5a27d9c
JJ		 1564 (*this_id) = null_frame_id;
1565 else
1566 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1567 if (gdbarch_debug >= 1)
1568 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1569 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1570 paddr_nz (this_id->code_addr),
1571 paddr_nz (this_id->stack_addr),
1572 paddr_nz (cache->bsp), next_frame);
004d836a 1573}
244bc108 1574
004d836a
JJ		 1575static void
1576ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1577 int regnum, int *optimizedp,
1578 enum lval_type *lvalp, CORE_ADDR *addrp,
1579 int *realnump, void *valuep)
1580{
1581 struct ia64_frame_cache *cache =
1582 ia64_frame_cache (next_frame, this_cache);
1583 char dummy_valp[MAX_REGISTER_SIZE];
1584 char buf[8];
1585
1586 gdb_assert (regnum >= 0);
244bc108 1587
004d836a 1588 if (!target_has_registers)
8a3fe4f8 1589 error (_("No registers."));
244bc108 1590
004d836a
JJ		 1591 *optimizedp = 0;
1592 *addrp = 0;
1593 *lvalp = not_lval;
1594 *realnump = -1;
244bc108 1595
004d836a
JJ		 1596 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1597 when valuep is not supplied. */
1598 if (!valuep)
1599 valuep = dummy_valp;
1600
aa2a9a3c 1601 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1602
1603 if (regnum == SP_REGNUM)
16461d7d
KB		 1604 {
1605 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1606 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1607 cache->base);
16461d7d
KB		 1608 }
1609 else if (regnum == IA64_BSP_REGNUM)
1610 {
004d836a
JJ		 1611 char cfm_valuep[MAX_REGISTER_SIZE];
1612 int cfm_optim;
1613 int cfm_realnum;
1614 enum lval_type cfm_lval;
1615 CORE_ADDR cfm_addr;
1616 CORE_ADDR bsp, prev_cfm, prev_bsp;
1617
1618 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1619 This corresponds to what the hardware bsp register will be if we pop the frame
1620 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1621 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1622 the start of the output registers. We can calculate the end of that frame by adding
1623 the size of output (sof (size of frame) - sol (size of locals)). */
1624 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1625 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1626 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1627
1628 bsp = rse_address_add (cache->bsp, -(cache->sof));
1629 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1630
aa2a9a3c 1631 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1632 prev_bsp);
1633 }
1634 else if (regnum == IA64_CFM_REGNUM)
1635 {
4afcc598
JJ		 1636 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1637
1638 if (addr != 0)
004d836a 1639 {
4afcc598
JJ		 1640 *lvalp = lval_memory;
1641 *addrp = addr;
1642 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1643 }
4afcc598
JJ		 1644 else if (cache->prev_cfm)
1645 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1646 else if (cache->frameless)
004d836a 1647 {
4afcc598
JJ		 1648 CORE_ADDR cfm = 0;
1649 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1650 }
16461d7d
KB		 1651 }
1652 else if (regnum == IA64_VFP_REGNUM)
1653 {
1654 /* If the function in question uses an automatic register (r32-r127)
1655 for the frame pointer, it'll be found by ia64_find_saved_register()
1656 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1657 still provide a value since we know the size of the frame. */
1658 CORE_ADDR vfp = cache->base;
aa2a9a3c 1659 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1660 }
004d836a 1661 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1662 {
004d836a 1663 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1664 int pr_optim;
004d836a 1665 int pr_realnum;
16461d7d
KB		 1666 enum lval_type pr_lval;
1667 CORE_ADDR pr_addr;
004d836a
JJ		 1668 ULONGEST prN_val;
1669 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1670 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1671 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1672 {
1673 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1674 marker for this frame. */
1675 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1676
004d836a
JJ		 1677 /* Adjust the register number to account for register rotation. */
1678 regnum = VP16_REGNUM
1679 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1680 }
004d836a
JJ		 1681 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1682 regnum - VP0_REGNUM, 1);
aa2a9a3c 1683 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1684 }
1685 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1686 {
004d836a 1687 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1688 int unat_optim;
004d836a 1689 int unat_realnum;
16461d7d
KB		 1690 enum lval_type unat_lval;
1691 CORE_ADDR unat_addr;
004d836a
JJ		 1692 ULONGEST unatN_val;
1693 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1694 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1695 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1696 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1697 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1698 unatN_val);
16461d7d
KB		 1699 }
1700 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1701 {
1702 int natval = 0;
1703 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1704 interested in. */
1705 CORE_ADDR gr_addr;
244bc108 1706
004d836a
JJ		 1707 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1708 + IA64_GR0_REGNUM];
1709 if (gr_addr != 0)
244bc108 1710 {
004d836a 1711 /* Compute address of nat collection bits. */
16461d7d 1712 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1713 CORE_ADDR bsp;
16461d7d
KB		 1714 CORE_ADDR nat_collection;
1715 int nat_bit;
1716 /* If our nat collection address is bigger than bsp, we have to get
1717 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1718 collection from the computed address. */
1719 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1720 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1721 if (nat_addr >= bsp)
004d836a
JJ		 1722 {
1723 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1724 nat_collection = extract_unsigned_integer (buf, 8);
1725 }
16461d7d
KB		 1726 else
1727 nat_collection = read_memory_integer (nat_addr, 8);
1728 nat_bit = (gr_addr >> 3) & 0x3f;
1729 natval = (nat_collection >> nat_bit) & 1;
1730 }
004d836a 1731
aa2a9a3c 1732 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1733 }
1734 else if (regnum == IA64_IP_REGNUM)
1735 {
004d836a 1736 CORE_ADDR pc = 0;
4afcc598 1737 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1738
4afcc598 1739 if (addr != 0)
004d836a 1740 {
4afcc598
JJ		 1741 *lvalp = lval_memory;
1742 *addrp = addr;
1743 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1744 pc = extract_unsigned_integer (buf, 8);
1745 }
4afcc598 1746 else if (cache->frameless)
004d836a 1747 {
4afcc598
JJ		 1748 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1749 pc = extract_unsigned_integer (buf, 8);
244bc108 1750 }
004d836a
JJ		 1751 pc &= ~0xf;
1752 store_unsigned_integer (valuep, 8, pc);
244bc108 1753 }
004d836a 1754 else if (regnum == IA64_PSR_REGNUM)
244bc108 1755 {
4afcc598
JJ		 1756 /* We don't know how to get the complete previous PSR, but we need it for
1757 the slot information when we unwind the pc (pc is formed of IP register
1758 plus slot information from PSR). To get the previous slot information,
1759 we mask it off the return address. */
004d836a
JJ		 1760 ULONGEST slot_num = 0;
1761 CORE_ADDR pc= 0;
1762 CORE_ADDR psr = 0;
4afcc598 1763 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1764
1765 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1766 psr = extract_unsigned_integer (buf, 8);
1767
4afcc598 1768 if (addr != 0)
244bc108 1769 {
4afcc598
JJ		 1770 *lvalp = lval_memory;
1771 *addrp = addr;
1772 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1773 pc = extract_unsigned_integer (buf, 8);
244bc108 1774 }
4afcc598 1775 else if (cache->frameless)
004d836a 1776 {
4afcc598
JJ		 1777 CORE_ADDR pc;
1778 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1779 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1780 }
1781 psr &= ~(3LL << 41);
1782 slot_num = pc & 0x3LL;
1783 psr |= (CORE_ADDR)slot_num << 41;
1784 store_unsigned_integer (valuep, 8, psr);
1785 }
4afcc598
JJ		 1786 else if (regnum == IA64_BR0_REGNUM)
1787 {
1788 CORE_ADDR br0 = 0;
1789 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1790 if (addr != 0)
1791 {
1792 *lvalp = lval_memory;
1793 *addrp = addr;
1794 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1795 br0 = extract_unsigned_integer (buf, 8);
1796 }
1797 store_unsigned_integer (valuep, 8, br0);
1798 }
004d836a
JJ		 1799 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1800 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1801 {
1802 CORE_ADDR addr = 0;
1803 if (regnum >= V32_REGNUM)
1804 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1805 addr = cache->saved_regs[regnum];
244bc108
KB		 1806 if (addr != 0)
1807 {
004d836a
JJ		 1808 *lvalp = lval_memory;
1809 *addrp = addr;
aa2a9a3c 1810 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1811 }
004d836a 1812 else if (cache->frameless)
244bc108 1813 {
004d836a
JJ		 1814 char r_valuep[MAX_REGISTER_SIZE];
1815 int r_optim;
1816 int r_realnum;
1817 enum lval_type r_lval;
1818 CORE_ADDR r_addr;
1819 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1820 CORE_ADDR addr = 0;
1821 if (regnum >= V32_REGNUM)
1822 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1823 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1824 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1825 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1826 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1827 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1828 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1829 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1830
1831 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1832 *lvalp = lval_memory;
1833 *addrp = addr;
aa2a9a3c 1834 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1835 }
16461d7d
KB		 1836 }
1837 else
1838 {
004d836a 1839 CORE_ADDR addr = 0;
3a854e23
KB		 1840 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1841 {
1842 /* Fetch floating point register rename base from current
004d836a
JJ		 1843 frame marker for this frame. */
1844 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1845
1846 /* Adjust the floating point register number to account for
004d836a 1847 register rotation. */
3a854e23
KB		 1848 regnum = IA64_FR32_REGNUM
1849 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1850 }
1851
004d836a
JJ		 1852 /* If we have stored a memory address, access the register. */
1853 addr = cache->saved_regs[regnum];
1854 if (addr != 0)
1855 {
1856 *lvalp = lval_memory;
1857 *addrp = addr;
aa2a9a3c 1858 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1859 }
1860 /* Otherwise, punt and get the current value of the register. */
1861 else
1862 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1863 }
4afcc598
JJ		 1864
1865 if (gdbarch_debug >= 1)
1866 fprintf_unfiltered (gdb_stdlog,
78ced177 1867 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1868 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1869 ? ia64_register_names[regnum] : "r??"),
1870 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1871}
004d836a
JJ		 1872
1873static const struct frame_unwind ia64_frame_unwind =
1874{
1875 NORMAL_FRAME,
1876 &ia64_frame_this_id,
1877 &ia64_frame_prev_register
1878};
1879
1880static const struct frame_unwind *
1881ia64_frame_sniffer (struct frame_info *next_frame)
1882{
1883 return &ia64_frame_unwind;
1884}
1885
1886/* Signal trampolines. */
1887
1888static void
1889ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1890{
1891 if (SIGCONTEXT_REGISTER_ADDRESS)
1892 {
1893 int regno;
1894
1895 cache->saved_regs[IA64_VRAP_REGNUM] =
1896 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1897 cache->saved_regs[IA64_CFM_REGNUM] =
1898 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1899 cache->saved_regs[IA64_PSR_REGNUM] =
1900 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1901 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1902 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1903 cache->saved_regs[IA64_RNAT_REGNUM] =
1904 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1905 cache->saved_regs[IA64_CCV_REGNUM] =
1906 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1907 cache->saved_regs[IA64_UNAT_REGNUM] =
1908 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1909 cache->saved_regs[IA64_FPSR_REGNUM] =
1910 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1911 cache->saved_regs[IA64_PFS_REGNUM] =
1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1913 cache->saved_regs[IA64_LC_REGNUM] =
1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1915 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1916 cache->saved_regs[regno] =
1917 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1918 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1919 cache->saved_regs[regno] =
1920 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1921 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1922 cache->saved_regs[regno] =
1923 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1924 }
1925}
1926
1927static struct ia64_frame_cache *
1928ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1929{
1930 struct ia64_frame_cache *cache;
1931 CORE_ADDR addr;
1932 char buf[8];
1933 int i;
1934
1935 if (*this_cache)
1936 return *this_cache;
1937
1938 cache = ia64_alloc_frame_cache ();
1939
1940 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1941 /* Note that frame size is hard-coded below. We cannot calculate it
1942 via prologue examination. */
1943 cache->base = extract_unsigned_integer (buf, 8) + 16;
1944
1945 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1946 cache->bsp = extract_unsigned_integer (buf, 8);
1947
1948 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1949 cache->cfm = extract_unsigned_integer (buf, 8);
1950 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1951
1952 ia64_sigtramp_frame_init_saved_regs (cache);
1953
1954 *this_cache = cache;
1955 return cache;
1956}
1957
1958static void
1959ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1960 void **this_cache, struct frame_id *this_id)
1961{
1962 struct ia64_frame_cache *cache =
1963 ia64_sigtramp_frame_cache (next_frame, this_cache);
1964
4afcc598
JJ		 1965 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1966 if (gdbarch_debug >= 1)
1967 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1968 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1969 paddr_nz (this_id->code_addr),
1970 paddr_nz (this_id->stack_addr),
1971 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1972}
1973
1974static void
1975ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1976 void **this_cache,
1977 int regnum, int *optimizedp,
1978 enum lval_type *lvalp, CORE_ADDR *addrp,
1979 int *realnump, void *valuep)
1980{
4afcc598
JJ		 1981 char dummy_valp[MAX_REGISTER_SIZE];
1982 char buf[MAX_REGISTER_SIZE];
1983
1984 struct ia64_frame_cache *cache =
1985 ia64_sigtramp_frame_cache (next_frame, this_cache);
1986
1987 gdb_assert (regnum >= 0);
1988
1989 if (!target_has_registers)
8a3fe4f8 1990 error (_("No registers."));
4afcc598
JJ		 1991
1992 *optimizedp = 0;
1993 *addrp = 0;
1994 *lvalp = not_lval;
1995 *realnump = -1;
1996
1997 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1998 when valuep is not supplied. */
1999 if (!valuep)
2000 valuep = dummy_valp;
2001
2002 memset (valuep, 0, register_size (current_gdbarch, regnum));
2003
2004 if (regnum == IA64_IP_REGNUM)
2005 {
2006 CORE_ADDR pc = 0;
2007 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2008
2009 if (addr != 0)
2010 {
2011 *lvalp = lval_memory;
2012 *addrp = addr;
2013 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2014 pc = extract_unsigned_integer (buf, 8);
2015 }
2016 pc &= ~0xf;
2017 store_unsigned_integer (valuep, 8, pc);
2018 }
2019 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2020 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2021 {
2022 CORE_ADDR addr = 0;
2023 if (regnum >= V32_REGNUM)
2024 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2025 addr = cache->saved_regs[regnum];
2026 if (addr != 0)
2027 {
2028 *lvalp = lval_memory;
2029 *addrp = addr;
2030 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2031 }
2032 }
2033 else
2034 {
2035 /* All other registers not listed above. */
2036 CORE_ADDR addr = cache->saved_regs[regnum];
2037 if (addr != 0)
2038 {
2039 *lvalp = lval_memory;
2040 *addrp = addr;
2041 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2042 }
2043 }
004d836a 2044
4afcc598
JJ		 2045 if (gdbarch_debug >= 1)
2046 fprintf_unfiltered (gdb_stdlog,
78ced177 2047 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2048 (regnum < IA64_GR32_REGNUM
2049 || (regnum > IA64_GR127_REGNUM
2050 && regnum < LAST_PSEUDO_REGNUM))
2051 ? ia64_register_names[regnum]
2052 : (regnum < LAST_PSEUDO_REGNUM
2053 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2054 : "OUT_OF_RANGE"),
78ced177 2055 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2056}
2057
2058static const struct frame_unwind ia64_sigtramp_frame_unwind =
2059{
2060 SIGTRAMP_FRAME,
2061 ia64_sigtramp_frame_this_id,
2062 ia64_sigtramp_frame_prev_register
2063};
2064
2065static const struct frame_unwind *
2066ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2067{
2068 char *name;
2069 CORE_ADDR pc = frame_pc_unwind (next_frame);
2070
2071 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2072 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2073 return &ia64_sigtramp_frame_unwind;
2074
2075 return NULL;
2076}
2077\f
2078
2079static CORE_ADDR
2080ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2081{
2082 struct ia64_frame_cache *cache =
2083 ia64_frame_cache (next_frame, this_cache);
2084
2085 return cache->base;
2086}
2087
2088static const struct frame_base ia64_frame_base =
2089{
2090 &ia64_frame_unwind,
2091 ia64_frame_base_address,
2092 ia64_frame_base_address,
2093 ia64_frame_base_address
2094};
16461d7d 2095
968d1cb4
JJ		 2096#ifdef HAVE_LIBUNWIND_IA64_H
2097
2098struct ia64_unwind_table_entry
2099 {
2100 unw_word_t start_offset;
2101 unw_word_t end_offset;
2102 unw_word_t info_offset;
2103 };
2104
2105static __inline__ uint64_t
2106ia64_rse_slot_num (uint64_t addr)
2107{
2108 return (addr >> 3) & 0x3f;
2109}
2110
2111/* Skip over a designated number of registers in the backing
2112 store, remembering every 64th position is for NAT. */
2113static __inline__ uint64_t
2114ia64_rse_skip_regs (uint64_t addr, long num_regs)
2115{
2116 long delta = ia64_rse_slot_num(addr) + num_regs;
2117
2118 if (num_regs < 0)
2119 delta -= 0x3e;
2120 return addr + ((num_regs + delta/0x3f) << 3);
2121}
2122
2123/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2124 number to a libunwind register number. */
2125static int
2126ia64_gdb2uw_regnum (int regnum)
2127{
2128 if (regnum == sp_regnum)
2129 return UNW_IA64_SP;
2130 else if (regnum == IA64_BSP_REGNUM)
2131 return UNW_IA64_BSP;
2132 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2133 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2134 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2135 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2136 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2137 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2138 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2139 return -1;
2140 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2141 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2142 else if (regnum == IA64_PR_REGNUM)
2143 return UNW_IA64_PR;
2144 else if (regnum == IA64_IP_REGNUM)
2145 return UNW_REG_IP;
2146 else if (regnum == IA64_CFM_REGNUM)
2147 return UNW_IA64_CFM;
2148 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2149 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2150 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2151 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2152 else
2153 return -1;
2154}
2155
2156/* Gdb libunwind-frame callback function to convert from a libunwind register
2157 number to a ia64 gdb register number. */
2158static int
2159ia64_uw2gdb_regnum (int uw_regnum)
2160{
2161 if (uw_regnum == UNW_IA64_SP)
2162 return sp_regnum;
2163 else if (uw_regnum == UNW_IA64_BSP)
2164 return IA64_BSP_REGNUM;
2165 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2166 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2167 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2168 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2169 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2170 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2171 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2172 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2173 else if (uw_regnum == UNW_IA64_PR)
2174 return IA64_PR_REGNUM;
2175 else if (uw_regnum == UNW_REG_IP)
2176 return IA64_IP_REGNUM;
2177 else if (uw_regnum == UNW_IA64_CFM)
2178 return IA64_CFM_REGNUM;
2179 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2180 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2181 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2182 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2183 else
2184 return -1;
2185}
2186
2187/* Gdb libunwind-frame callback function to reveal if register is a float
2188 register or not. */
2189static int
2190ia64_is_fpreg (int uw_regnum)
2191{
2192 return unw_is_fpreg (uw_regnum);
2193}
2194
2195/* Libunwind callback accessor function for general registers. */
2196static int
2197ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2198 int write, void *arg)
2199{
2200 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2201 unw_word_t bsp, sof, sol, cfm, psr, ip;
2202 struct frame_info *next_frame = arg;
2203 long new_sof, old_sof;
2204 char buf[MAX_REGISTER_SIZE];
2205
2206 if (write)
2207 {
2208 if (regnum < 0)
2209 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2210 return 0;
2211
2212 switch (uw_regnum)
2213 {
2214 case UNW_REG_IP:
2215 ia64_write_pc (*val, inferior_ptid);
2216 break;
2217
2218 case UNW_IA64_AR_BSPSTORE:
2219 write_register (IA64_BSP_REGNUM, *val);
2220 break;
2221
2222 case UNW_IA64_AR_BSP:
2223 case UNW_IA64_BSP:
2224 /* Account for the fact that ptrace() expects bsp to point
2225 after the current register frame. */
2226 cfm = read_register (IA64_CFM_REGNUM);
2227 sof = (cfm & 0x7f);
2228 bsp = ia64_rse_skip_regs (*val, sof);
2229 write_register (IA64_BSP_REGNUM, bsp);
2230 break;
2231
2232 case UNW_IA64_CFM:
2233 /* If we change CFM, we need to adjust ptrace's notion of
2234 bsp accordingly, so that the real bsp remains
2235 unchanged. */
2236 bsp = read_register (IA64_BSP_REGNUM);
2237 cfm = read_register (IA64_CFM_REGNUM);
2238 old_sof = (cfm & 0x7f);
2239 new_sof = (*val & 0x7f);
2240 if (old_sof != new_sof)
2241 {
2242 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2243 write_register (IA64_BSP_REGNUM, bsp);
2244 }
2245 write_register (IA64_CFM_REGNUM, *val);
2246 break;
2247
2248 default:
2249 write_register (regnum, *val);
2250 break;
2251 }
2252 if (gdbarch_debug >= 1)
2253 fprintf_unfiltered (gdb_stdlog,
78ced177 2254 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2255 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2256 ? ia64_register_names[regnum] : "r??"),
2257 paddr_nz (*val));
968d1cb4
JJ		 2258 }
2259 else
2260 {
2261 switch (uw_regnum)
2262 {
2263 case UNW_REG_IP:
2264 /* Libunwind expects to see the pc value which means the slot number
2265 from the psr must be merged with the ip word address. */
2266 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2267 ip = extract_unsigned_integer (buf, 8);
2268 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2269 psr = extract_unsigned_integer (buf, 8);
2270 *val = ip | ((psr >> 41) & 0x3);
2271 break;
2272
2273 case UNW_IA64_AR_BSP:
2274 /* Libunwind expects to see the beginning of the current register
2275 frame so we must account for the fact that ptrace() will return a value
2276 for bsp that points *after* the current register frame. */
2277 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2278 bsp = extract_unsigned_integer (buf, 8);
2279 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2280 cfm = extract_unsigned_integer (buf, 8);
2281 sof = (cfm & 0x7f);
2282 *val = ia64_rse_skip_regs (bsp, -sof);
2283 break;
2284
2285 case UNW_IA64_AR_BSPSTORE:
2286 /* Libunwind wants bspstore to be after the current register frame.
2287 This is what ptrace() and gdb treats as the regular bsp value. */
2288 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2289 *val = extract_unsigned_integer (buf, 8);
2290 break;
2291
2292 default:
2293 /* For all other registers, just unwind the value directly. */
2294 frame_unwind_register (next_frame, regnum, buf);
2295 *val = extract_unsigned_integer (buf, 8);
2296 break;
2297 }
2298
2299 if (gdbarch_debug >= 1)
2300 fprintf_unfiltered (gdb_stdlog,
78ced177 2301 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2302 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2303 ? ia64_register_names[regnum] : "r??"),
2304 paddr_nz (*val));
968d1cb4
JJ		 2305 }
2306 return 0;
2307}
2308
2309/* Libunwind callback accessor function for floating-point registers. */
2310static int
2311ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2312 int write, void *arg)
2313{
2314 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2315
2316 if (write)
2317 regcache_cooked_write (current_regcache, regnum, (char *) val);
2318 else
2319 regcache_cooked_read (current_regcache, regnum, (char *) val);
2320 return 0;
2321}
2322
c5a27d9c
JJ		 2323/* Libunwind callback accessor function for top-level rse registers. */
2324static int
2325ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2326 int write, void *arg)
2327{
2328 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2329 unw_word_t bsp, sof, sol, cfm, psr, ip;
2330 long new_sof, old_sof;
2331
2332 if (write)
2333 {
2334 if (regnum < 0)
2335 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2336 return 0;
2337
2338 switch (uw_regnum)
2339 {
2340 case UNW_REG_IP:
2341 ia64_write_pc (*val, inferior_ptid);
2342 break;
2343
2344 case UNW_IA64_AR_BSPSTORE:
2345 write_register (IA64_BSP_REGNUM, *val);
2346 break;
2347
2348 case UNW_IA64_AR_BSP:
2349 case UNW_IA64_BSP:
2350 /* Account for the fact that ptrace() expects bsp to point
2351 after the current register frame. */
2352 cfm = read_register (IA64_CFM_REGNUM);
2353 sof = (cfm & 0x7f);
2354 bsp = ia64_rse_skip_regs (*val, sof);
2355 write_register (IA64_BSP_REGNUM, bsp);
2356 break;
2357
2358 case UNW_IA64_CFM:
2359 /* If we change CFM, we need to adjust ptrace's notion of
2360 bsp accordingly, so that the real bsp remains
2361 unchanged. */
2362 bsp = read_register (IA64_BSP_REGNUM);
2363 cfm = read_register (IA64_CFM_REGNUM);
2364 old_sof = (cfm & 0x7f);
2365 new_sof = (*val & 0x7f);
2366 if (old_sof != new_sof)
2367 {
2368 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2369 write_register (IA64_BSP_REGNUM, bsp);
2370 }
2371 write_register (IA64_CFM_REGNUM, *val);
2372 break;
2373
2374 default:
2375 write_register (regnum, *val);
2376 break;
2377 }
2378 if (gdbarch_debug >= 1)
2379 fprintf_unfiltered (gdb_stdlog,
2380 " access_rse_reg: to cache: %4s=0x%s\n",
2381 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2382 ? ia64_register_names[regnum] : "r??"),
2383 paddr_nz (*val));
2384 }
2385 else
2386 {
2387 switch (uw_regnum)
2388 {
2389 case UNW_REG_IP:
2390 /* Libunwind expects to see the pc value which means the slot number
2391 from the psr must be merged with the ip word address. */
2392 ip = read_register (IA64_IP_REGNUM);
2393 psr = read_register (IA64_PSR_REGNUM);
2394 *val = ip | ((psr >> 41) & 0x3);
2395 break;
2396
2397 case UNW_IA64_AR_BSP:
2398 /* Libunwind expects to see the beginning of the current register
2399 frame so we must account for the fact that ptrace() will return a value
2400 for bsp that points *after* the current register frame. */
2401 bsp = read_register (IA64_BSP_REGNUM);
2402 cfm = read_register (IA64_CFM_REGNUM);
2403 sof = (cfm & 0x7f);
2404 *val = ia64_rse_skip_regs (bsp, -sof);
2405 break;
2406
2407 case UNW_IA64_AR_BSPSTORE:
2408 /* Libunwind wants bspstore to be after the current register frame.
2409 This is what ptrace() and gdb treats as the regular bsp value. */
2410 *val = read_register (IA64_BSP_REGNUM);
2411 break;
2412
2413 default:
2414 /* For all other registers, just read the value directly. */
2415 *val = read_register (regnum);
2416 break;
2417 }
2418 }
2419
2420 if (gdbarch_debug >= 1)
2421 fprintf_unfiltered (gdb_stdlog,
2422 " access_rse_reg: from cache: %4s=0x%s\n",
2423 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2424 ? ia64_register_names[regnum] : "r??"),
2425 paddr_nz (*val));
2426
2427 return 0;
2428}
2429
968d1cb4
JJ		 2430/* Libunwind callback accessor function for accessing memory. */
2431static int
2432ia64_access_mem (unw_addr_space_t as,
2433 unw_word_t addr, unw_word_t *val,
2434 int write, void *arg)
2435{
c5a27d9c
JJ		 2436 if (addr - KERNEL_START < ktab_size)
2437 {
2438 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2439 + (addr - KERNEL_START));
2440
2441 if (write)
2442 *laddr = *val;
2443 else
2444 *val = *laddr;
2445 return 0;
2446 }
2447
968d1cb4
JJ		 2448 /* XXX do we need to normalize byte-order here? */
2449 if (write)
2450 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2451 else
2452 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2453}
2454
2455/* Call low-level function to access the kernel unwind table. */
2456static int
2457getunwind_table (void *buf, size_t len)
2458{
2459 LONGEST x;
c5a27d9c
JJ		 2460
2461 /* FIXME: This is a temporary solution to backtracing syscalls in corefiles.
2462 To do this properly, the AUXV section should be used. This
2463 fix will work as long as the kernel used to generate the corefile
2464 is equivalent to the kernel used to debug the corefile. */
2465 x = ia64_linux_xfer_unwind_table (&current_target,
2466 TARGET_OBJECT_UNWIND_TABLE, NULL,
2467 buf, NULL, 0, len);
968d1cb4
JJ		 2468
2469 return (int)x;
2470}
2471
2472/* Get the kernel unwind table. */
2473static int
2474get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2475{
c5a27d9c 2476 static struct ia64_table_entry *etab;
968d1cb4 2477
c5a27d9c 2478 if (!ktab)
968d1cb4 2479 {
c5a27d9c 2480 size_t size;
968d1cb4
JJ		 2481 size = getunwind_table (NULL, 0);
2482 if ((int)size < 0)
c5a27d9c
JJ		 2483 return -UNW_ENOINFO;
2484 ktab_size = size;
2485 ktab = xmalloc (ktab_size);
2486 getunwind_table (ktab, ktab_size);
2487
968d1cb4 2488 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2489 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2490 }
2491
2492 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2493 return -UNW_ENOINFO;
2494
2495 di->format = UNW_INFO_FORMAT_TABLE;
2496 di->gp = 0;
2497 di->start_ip = ktab[0].start_offset;
2498 di->end_ip = etab[-1].end_offset;
2499 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2500 di->u.ti.segbase = 0;
2501 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2502 di->u.ti.table_data = (unw_word_t *) ktab;
2503
2504 if (gdbarch_debug >= 1)
2505 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2506 "segbase=0x%s, length=%s, gp=0x%s\n",
2507 (char *) di->u.ti.name_ptr,
2508 paddr_nz (di->u.ti.segbase),
2509 paddr_u (di->u.ti.table_len),
2510 paddr_nz (di->gp));
968d1cb4
JJ		 2511 return 0;
2512}
2513
2514/* Find the unwind table entry for a specified address. */
2515static int
2516ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2517 unw_dyn_info_t *dip, void **buf)
2518{
2519 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2520 Elf_Internal_Ehdr *ehdr;
2521 unw_word_t segbase = 0;
2522 CORE_ADDR load_base;
2523 bfd *bfd;
2524 int i;
2525
2526 bfd = objfile->obfd;
2527
2528 ehdr = elf_tdata (bfd)->elf_header;
2529 phdr = elf_tdata (bfd)->phdr;
2530
2531 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2532
2533 for (i = 0; i < ehdr->e_phnum; ++i)
2534 {
2535 switch (phdr[i].p_type)
2536 {
2537 case PT_LOAD:
2538 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2539 < phdr[i].p_memsz)
2540 p_text = phdr + i;
2541 break;
2542
2543 case PT_IA_64_UNWIND:
2544 p_unwind = phdr + i;
2545 break;
2546
2547 default:
2548 break;
2549 }
2550 }
2551
c5a27d9c 2552 if (!p_text || !p_unwind)
968d1cb4
JJ		 2553 return -UNW_ENOINFO;
2554
c5a27d9c
JJ		 2555 /* Verify that the segment that contains the IP also contains
2556 the static unwind table. If not, we may be in the Linux kernel's
2557 DSO gate page in which case the unwind table is another segment.
2558 Otherwise, we are dealing with runtime-generated code, for which we
2559 have no info here. */
968d1cb4
JJ		 2560 segbase = p_text->p_vaddr + load_base;
2561
c5a27d9c
JJ		 2562 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2563 {
2564 int ok = 0;
2565 for (i = 0; i < ehdr->e_phnum; ++i)
2566 {
2567 if (phdr[i].p_type == PT_LOAD
2568 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2569 {
2570 ok = 1;
2571 /* Get the segbase from the section containing the
2572 libunwind table. */
2573 segbase = phdr[i].p_vaddr + load_base;
2574 }
2575 }
2576 if (!ok)
2577 return -UNW_ENOINFO;
2578 }
2579
2580 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2581 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2582 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2583 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2584 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2585 dip->u.rti.segbase = segbase;
2586 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2587 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2588
2589 return 0;
2590}
2591
2592/* Libunwind callback accessor function to acquire procedure unwind-info. */
2593static int
2594ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2595 int need_unwind_info, void *arg)
2596{
2597 struct obj_section *sec = find_pc_section (ip);
2598 unw_dyn_info_t di;
2599 int ret;
2600 void *buf = NULL;
2601
2602 if (!sec)
2603 {
2604 /* XXX This only works if the host and the target architecture are
2605 both ia64 and if the have (more or less) the same kernel
2606 version. */
2607 if (get_kernel_table (ip, &di) < 0)
2608 return -UNW_ENOINFO;
503ff15d
KB		 2609
2610 if (gdbarch_debug >= 1)
78ced177
JJ		 2611 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2612 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2613 "length=%s,data=0x%s)\n",
2614 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2615 paddr_nz (di.u.ti.segbase),
2616 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2617 paddr_nz (di.gp),
2618 paddr_u (di.u.ti.table_len),
2619 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2620 }
2621 else
2622 {
2623 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2624 if (ret < 0)
2625 return ret;
968d1cb4 2626
503ff15d 2627 if (gdbarch_debug >= 1)
78ced177
JJ		 2628 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2629 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2630 "length=%s,data=0x%s)\n",
2631 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2632 paddr_nz (di.u.rti.segbase),
2633 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2634 paddr_nz (di.gp),
2635 paddr_u (di.u.rti.table_len),
2636 paddr_nz (di.u.rti.table_data));
503ff15d 2637 }
968d1cb4 2638
503ff15d
KB		 2639 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2640 arg);
968d1cb4
JJ		 2641
2642 /* We no longer need the dyn info storage so free it. */
2643 xfree (buf);
2644
2645 return ret;
2646}
2647
2648/* Libunwind callback accessor function for cleanup. */
2649static void
2650ia64_put_unwind_info (unw_addr_space_t as,
2651 unw_proc_info_t *pip, void *arg)
2652{
2653 /* Nothing required for now. */
2654}
2655
2656/* Libunwind callback accessor function to get head of the dynamic
2657 unwind-info registration list. */
2658static int
2659ia64_get_dyn_info_list (unw_addr_space_t as,
2660 unw_word_t *dilap, void *arg)
2661{
2662 struct obj_section *text_sec;
2663 struct objfile *objfile;
2664 unw_word_t ip, addr;
2665 unw_dyn_info_t di;
2666 int ret;
2667
2668 if (!libunwind_is_initialized ())
2669 return -UNW_ENOINFO;
2670
2671 for (objfile = object_files; objfile; objfile = objfile->next)
2672 {
2673 void *buf = NULL;
2674
2675 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2676 ip = text_sec->addr;
2677 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2678 if (ret >= 0)
2679 {
503ff15d 2680 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2681 /* We no longer need the dyn info storage so free it. */
2682 xfree (buf);
2683
2684 if (addr)
2685 {
2686 if (gdbarch_debug >= 1)
2687 fprintf_unfiltered (gdb_stdlog,
2688 "dynamic unwind table in objfile %s "
78ced177 2689 "at 0x%s (gp=0x%s)\n",
968d1cb4 2690 bfd_get_filename (objfile->obfd),
78ced177 2691 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2692 *dilap = addr;
2693 return 0;
2694 }
2695 }
2696 }
2697 return -UNW_ENOINFO;
2698}
2699
2700
2701/* Frame interface functions for libunwind. */
2702
2703static void
2704ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2705 struct frame_id *this_id)
968d1cb4
JJ		 2706{
2707 char buf[8];
2708 CORE_ADDR bsp;
2709 struct frame_id id;
c5a27d9c
JJ		 2710 CORE_ADDR prev_ip, addr;
2711 int realnum, optimized;
2712 enum lval_type lval;
2713
968d1cb4
JJ		 2714
2715 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2716 if (frame_id_eq (id, null_frame_id))
2717 {
2718 (*this_id) = null_frame_id;
2719 return;
2720 }
968d1cb4 2721
c5a27d9c
JJ		 2722 /* We must add the bsp as the special address for frame comparison
2723 purposes. */
968d1cb4
JJ		 2724 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2725 bsp = extract_unsigned_integer (buf, 8);
2726
c5a27d9c
JJ		 2727 /* If the previous frame pc value is 0, then we are at the end of the stack
2728 and don't want to unwind past this frame. We return a null frame_id to
2729 indicate this. */
2730 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
2731 &optimized, &lval, &addr, &realnum, &prev_ip);
2732
2733 if (prev_ip != 0)
2734 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2735 else
2736 (*this_id) = null_frame_id;
968d1cb4
JJ		 2737
2738 if (gdbarch_debug >= 1)
2739 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2740 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2741 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2742 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2743}
2744
2745static void
2746ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2747 void **this_cache,
2748 int regnum, int *optimizedp,
2749 enum lval_type *lvalp, CORE_ADDR *addrp,
2750 int *realnump, void *valuep)
2751{
2752 int reg = regnum;
2753
2754 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2755 reg = IA64_PR_REGNUM;
2756 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2757 reg = IA64_UNAT_REGNUM;
2758
2759 /* Let libunwind do most of the work. */
2760 libunwind_frame_prev_register (next_frame, this_cache, reg,
2761 optimizedp, lvalp, addrp, realnump, valuep);
2762
6672f2ae
AS		 2763 /* No more to do if the value is not supposed to be supplied. */
2764 if (!valuep)
2765 return;
2766
968d1cb4
JJ		 2767 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2768 {
2769 ULONGEST prN_val;
2770
2771 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2772 {
2773 int rrb_pr = 0;
2774 ULONGEST cfm;
2775 unsigned char buf[MAX_REGISTER_SIZE];
2776
2777 /* Fetch predicate register rename base from current frame
2778 marker for this frame. */
2779 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2780 cfm = extract_unsigned_integer (buf, 8);
2781 rrb_pr = (cfm >> 32) & 0x3f;
2782
2783 /* Adjust the register number to account for register rotation. */
2784 regnum = VP16_REGNUM
2785 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2786 }
2787 prN_val = extract_bit_field ((unsigned char *) valuep,
2788 regnum - VP0_REGNUM, 1);
2789 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2790 }
2791 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2792 {
2793 ULONGEST unatN_val;
2794
2795 unatN_val = extract_bit_field ((unsigned char *) valuep,
2796 regnum - IA64_NAT0_REGNUM, 1);
2797 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2798 unatN_val);
2799 }
2800 else if (regnum == IA64_BSP_REGNUM)
2801 {
2802 char cfm_valuep[MAX_REGISTER_SIZE];
2803 int cfm_optim;
2804 int cfm_realnum;
2805 enum lval_type cfm_lval;
2806 CORE_ADDR cfm_addr;
2807 CORE_ADDR bsp, prev_cfm, prev_bsp;
2808
2809 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2810 This corresponds to what the hardware bsp register will be if we pop the frame
2811 back which is why we might have been called. We know that libunwind will pass us back
2812 the beginning of the current frame so we should just add sof to it. */
2813 prev_bsp = extract_unsigned_integer (valuep, 8);
2814 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2815 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2816 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2817 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2818
2819 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2820 prev_bsp);
2821 }
2822
2823 if (gdbarch_debug >= 1)
2824 fprintf_unfiltered (gdb_stdlog,
78ced177 2825 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2826 (regnum < IA64_GR32_REGNUM
2827 || (regnum > IA64_GR127_REGNUM
2828 && regnum < LAST_PSEUDO_REGNUM))
2829 ? ia64_register_names[regnum]
2830 : (regnum < LAST_PSEUDO_REGNUM
2831 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2832 : "OUT_OF_RANGE"),
78ced177 2833 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2834}
2835
2836static const struct frame_unwind ia64_libunwind_frame_unwind =
2837{
2838 NORMAL_FRAME,
2839 ia64_libunwind_frame_this_id,
2840 ia64_libunwind_frame_prev_register
2841};
2842
2843static const struct frame_unwind *
2844ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2845{
2846 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2847 return &ia64_libunwind_frame_unwind;
2848
2849 return NULL;
2850}
2851
c5a27d9c
JJ		 2852static void
2853ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2854 struct frame_id *this_id)
2855{
2856 char buf[8];
2857 CORE_ADDR bsp;
2858 struct frame_id id;
2859 CORE_ADDR prev_ip;
2860
2861 libunwind_frame_this_id (next_frame, this_cache, &id);
2862 if (frame_id_eq (id, null_frame_id))
2863 {
2864 (*this_id) = null_frame_id;
2865 return;
2866 }
2867
2868 /* We must add the bsp as the special address for frame comparison
2869 purposes. */
2870 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2871 bsp = extract_unsigned_integer (buf, 8);
2872
2873 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2874 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2875
2876 if (gdbarch_debug >= 1)
2877 fprintf_unfiltered (gdb_stdlog,
2878 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2879 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2880 paddr_nz (bsp), next_frame);
2881}
2882
2883static void
2884ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2885 void **this_cache,
2886 int regnum, int *optimizedp,
2887 enum lval_type *lvalp, CORE_ADDR *addrp,
2888 int *realnump, void *valuep)
2889
2890{
2891 CORE_ADDR prev_ip, addr;
2892 int realnum, optimized;
2893 enum lval_type lval;
2894
2895
2896 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2897 method of getting previous registers. */
2898 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
2899 &optimized, &lval, &addr, &realnum, &prev_ip);
2900
2901 if (prev_ip == 0)
2902 {
2903 void *tmp_cache = NULL;
2904 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2905 addrp, realnump, valuep);
2906 }
2907 else
2908 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2909 addrp, realnump, valuep);
2910}
2911
2912static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2913{
2914 SIGTRAMP_FRAME,
2915 ia64_libunwind_sigtramp_frame_this_id,
2916 ia64_libunwind_sigtramp_frame_prev_register
2917};
2918
2919static const struct frame_unwind *
2920ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2921{
2922 if (libunwind_is_initialized ())
2923 {
2924 if (libunwind_sigtramp_frame_sniffer (next_frame))
2925 return &ia64_libunwind_sigtramp_frame_unwind;
2926 return NULL;
2927 }
2928 else
2929 return ia64_sigtramp_frame_sniffer (next_frame);
2930}
2931
968d1cb4
JJ		 2932/* Set of libunwind callback acccessor functions. */
2933static unw_accessors_t ia64_unw_accessors =
2934{
2935 ia64_find_proc_info_x,
2936 ia64_put_unwind_info,
2937 ia64_get_dyn_info_list,
2938 ia64_access_mem,
2939 ia64_access_reg,
2940 ia64_access_fpreg,
2941 /* resume */
2942 /* get_proc_name */
2943};
2944
c5a27d9c
JJ		 2945/* Set of special libunwind callback acccessor functions specific for accessing
2946 the rse registers. At the top of the stack, we want libunwind to figure out
2947 how to read r32 - r127. Though usually they are found sequentially in memory
2948 starting from $bof, this is not always true. */
2949static unw_accessors_t ia64_unw_rse_accessors =
2950{
2951 ia64_find_proc_info_x,
2952 ia64_put_unwind_info,
2953 ia64_get_dyn_info_list,
2954 ia64_access_mem,
2955 ia64_access_rse_reg,
2956 ia64_access_fpreg,
2957 /* resume */
2958 /* get_proc_name */
2959};
2960
968d1cb4
JJ		 2961/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2962static struct libunwind_descr ia64_libunwind_descr =
2963{
2964 ia64_gdb2uw_regnum,
2965 ia64_uw2gdb_regnum,
2966 ia64_is_fpreg,
2967 &ia64_unw_accessors,
c5a27d9c 2968 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2969};
2970
2971#endif /* HAVE_LIBUNWIND_IA64_H */
2972
74055713
AC		 2973/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2974 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2975 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2976int
2977ia64_use_struct_convention (int gcc_p, struct type *type)
2978{
64a5b29c
KB		 2979 struct type *float_elt_type;
2980
2981 /* HFAs are structures (or arrays) consisting entirely of floating
2982 point values of the same length. Up to 8 of these are returned
2983 in registers. Don't use the struct convention when this is the
004d836a 2984 case. */
64a5b29c
KB		 2985 float_elt_type = is_float_or_hfa_type (type);
2986 if (float_elt_type != NULL
2987 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2988 return 0;
2989
2990 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 2991 Don't use the struct convention for those either. */
16461d7d
KB		 2992 return TYPE_LENGTH (type) > 32;
2993}
2994
2995void
2d522557
AC		 2996ia64_extract_return_value (struct type *type, struct regcache *regcache,
2997 gdb_byte *valbuf)
16461d7d 2998{
64a5b29c
KB		 2999 struct type *float_elt_type;
3000
3001 float_elt_type = is_float_or_hfa_type (type);
3002 if (float_elt_type != NULL)
3003 {
004d836a 3004 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 3005 int offset = 0;
3006 int regnum = IA64_FR8_REGNUM;
3007 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3008
3009 while (n-- > 0)
3010 {
004d836a
JJ		 3011 regcache_cooked_read (regcache, regnum, from);
3012 convert_typed_floating (from, builtin_type_ia64_ext,
3013 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 3014 offset += TYPE_LENGTH (float_elt_type);
3015 regnum++;
3016 }
3017 }
16461d7d 3018 else
004d836a
JJ		 3019 {
3020 ULONGEST val;
3021 int offset = 0;
3022 int regnum = IA64_GR8_REGNUM;
3023 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
3024 int n = TYPE_LENGTH (type) / reglen;
3025 int m = TYPE_LENGTH (type) % reglen;
16461d7d 3026
004d836a
JJ		 3027 while (n-- > 0)
3028 {
3029 ULONGEST val;
3030 regcache_cooked_read_unsigned (regcache, regnum, &val);
3031 memcpy ((char *)valbuf + offset, &val, reglen);
3032 offset += reglen;
3033 regnum++;
3034 }
16461d7d 3035
004d836a
JJ		 3036 if (m)
3037 {
3038 regcache_cooked_read_unsigned (regcache, regnum, &val);
3039 memcpy ((char *)valbuf + offset, &val, m);
3040 }
3041 }
16461d7d
KB		 3042}
3043
3044CORE_ADDR
004d836a 3045ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 3046{
8a3fe4f8 3047 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 3048 return 0;
16461d7d
KB		 3049}
3050
16461d7d 3051
64a5b29c
KB		 3052static int
3053is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3054{
3055 switch (TYPE_CODE (t))
3056 {
3057 case TYPE_CODE_FLT:
3058 if (*etp)
3059 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3060 else
3061 {
3062 *etp = t;
3063 return 1;
3064 }
3065 break;
3066 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3067 return
3068 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3069 etp);
64a5b29c
KB		 3070 break;
3071 case TYPE_CODE_STRUCT:
3072 {
3073 int i;
3074
3075 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3076 if (!is_float_or_hfa_type_recurse
3077 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3078 return 0;
3079 return 1;
3080 }
3081 break;
3082 default:
3083 return 0;
3084 break;
3085 }
3086}
3087
3088/* Determine if the given type is one of the floating point types or
3089 and HFA (which is a struct, array, or combination thereof whose
004d836a 3090 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3091
3092static struct type *
3093is_float_or_hfa_type (struct type *t)
3094{
3095 struct type *et = 0;
3096
3097 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3098}
3099
3100
98f96ba1
KB		 3101/* Return 1 if the alignment of T is such that the next even slot
3102 should be used. Return 0, if the next available slot should
3103 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3104 and Runtime manual). */
98f96ba1
KB		 3105
3106static int
3107slot_alignment_is_next_even (struct type *t)
3108{
3109 switch (TYPE_CODE (t))
3110 {
3111 case TYPE_CODE_INT:
3112 case TYPE_CODE_FLT:
3113 if (TYPE_LENGTH (t) > 8)
3114 return 1;
3115 else
3116 return 0;
3117 case TYPE_CODE_ARRAY:
3118 return
3119 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3120 case TYPE_CODE_STRUCT:
3121 {
3122 int i;
3123
3124 for (i = 0; i < TYPE_NFIELDS (t); i++)
3125 if (slot_alignment_is_next_even
3126 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3127 return 1;
3128 return 0;
3129 }
3130 default:
3131 return 0;
3132 }
3133}
3134
64a5b29c
KB		 3135/* Attempt to find (and return) the global pointer for the given
3136 function.
3137
3138 This is a rather nasty bit of code searchs for the .dynamic section
3139 in the objfile corresponding to the pc of the function we're trying
3140 to call. Once it finds the addresses at which the .dynamic section
3141 lives in the child process, it scans the Elf64_Dyn entries for a
3142 DT_PLTGOT tag. If it finds one of these, the corresponding
3143 d_un.d_ptr value is the global pointer. */
3144
3145static CORE_ADDR
b33e8514 3146ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3147{
76d689a6 3148 struct obj_section *faddr_sect;
64a5b29c 3149
76d689a6
KB		 3150 faddr_sect = find_pc_section (faddr);
3151 if (faddr_sect != NULL)
64a5b29c
KB		 3152 {
3153 struct obj_section *osect;
3154
76d689a6 3155 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3156 {
3157 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3158 break;
3159 }
3160
76d689a6 3161 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3162 {
3163 CORE_ADDR addr;
3164
3165 addr = osect->addr;
3166 while (addr < osect->endaddr)
3167 {
3168 int status;
3169 LONGEST tag;
3170 char buf[8];
3171
3172 status = target_read_memory (addr, buf, sizeof (buf));
3173 if (status != 0)
3174 break;
3175 tag = extract_signed_integer (buf, sizeof (buf));
3176
3177 if (tag == DT_PLTGOT)
3178 {
3179 CORE_ADDR global_pointer;
3180
3181 status = target_read_memory (addr + 8, buf, sizeof (buf));
3182 if (status != 0)
3183 break;
7c0b4a20 3184 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3185
3186 /* The payoff... */
3187 return global_pointer;
3188 }
3189
3190 if (tag == DT_NULL)
3191 break;
3192
3193 addr += 16;
3194 }
3195 }
3196 }
3197 return 0;
3198}
3199
3200/* Given a function's address, attempt to find (and return) the
3201 corresponding (canonical) function descriptor. Return 0 if
004d836a 3202 not found. */
64a5b29c
KB		 3203static CORE_ADDR
3204find_extant_func_descr (CORE_ADDR faddr)
3205{
76d689a6 3206 struct obj_section *faddr_sect;
64a5b29c 3207
004d836a 3208 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3209 faddr_sect = find_pc_section (faddr);
3210 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3211 return faddr;
3212
76d689a6 3213 if (faddr_sect != NULL)
64a5b29c 3214 {
76d689a6
KB		 3215 struct obj_section *osect;
3216 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3217 {
3218 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3219 break;
3220 }
3221
76d689a6 3222 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3223 {
3224 CORE_ADDR addr;
3225
3226 addr = osect->addr;
3227 while (addr < osect->endaddr)
3228 {
3229 int status;
3230 LONGEST faddr2;
3231 char buf[8];
3232
3233 status = target_read_memory (addr, buf, sizeof (buf));
3234 if (status != 0)
3235 break;
3236 faddr2 = extract_signed_integer (buf, sizeof (buf));
3237
3238 if (faddr == faddr2)
3239 return addr;
3240
3241 addr += 16;
3242 }
3243 }
3244 }
3245 return 0;
3246}
3247
3248/* Attempt to find a function descriptor corresponding to the
3249 given address. If none is found, construct one on the
004d836a 3250 stack using the address at fdaptr. */
64a5b29c
KB		 3251
3252static CORE_ADDR
3253find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
3254{
3255 CORE_ADDR fdesc;
3256
3257 fdesc = find_extant_func_descr (faddr);
3258
3259 if (fdesc == 0)
3260 {
3261 CORE_ADDR global_pointer;
3262 char buf[16];
3263
3264 fdesc = *fdaptr;
3265 *fdaptr += 16;
3266
b33e8514 3267 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3268
3269 if (global_pointer == 0)
3270 global_pointer = read_register (IA64_GR1_REGNUM);
3271
fbd9dcd3
AC		 3272 store_unsigned_integer (buf, 8, faddr);
3273 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3274
3275 write_memory (fdesc, buf, 16);
3276 }
3277
3278 return fdesc;
3279}
16461d7d 3280
af8b88dd
JJ		 3281/* Use the following routine when printing out function pointers
3282 so the user can see the function address rather than just the
3283 function descriptor. */
3284static CORE_ADDR
e2d0e7eb
AC		 3285ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3286 struct target_ops *targ)
af8b88dd
JJ		 3287{
3288 struct obj_section *s;
3289
3290 s = find_pc_section (addr);
3291
3292 /* check if ADDR points to a function descriptor. */
3293 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3294 return read_memory_unsigned_integer (addr, 8);
3295
3296 return addr;
3297}
3298
a78f21af 3299static CORE_ADDR
004d836a
JJ		 3300ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3301{
3302 return sp & ~0xfLL;
3303}
3304
3305static CORE_ADDR
7d9b040b 3306ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3307 struct regcache *regcache, CORE_ADDR bp_addr,
3308 int nargs, struct value **args, CORE_ADDR sp,
3309 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3310{
3311 int argno;
ea7c478f 3312 struct value *arg;
16461d7d
KB		 3313 struct type *type;
3314 int len, argoffset;
64a5b29c 3315 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3316 int floatreg;
004d836a 3317 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3318 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3319
3320 nslots = 0;
64a5b29c 3321 nfuncargs = 0;
004d836a 3322 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3323 for (argno = 0; argno < nargs; argno++)
3324 {
3325 arg = args[argno];
4991999e 3326 type = check_typedef (value_type (arg));
16461d7d
KB		 3327 len = TYPE_LENGTH (type);
3328
98f96ba1 3329 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3330 nslots++;
3331
64a5b29c
KB		 3332 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3333 nfuncargs++;
3334
16461d7d
KB		 3335 nslots += (len + 7) / 8;
3336 }
3337
004d836a 3338 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3339 rseslots = (nslots > 8) ? 8 : nslots;
3340 memslots = nslots - rseslots;
3341
004d836a
JJ		 3342 /* Allocate a new RSE frame. */
3343 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3344
004d836a 3345 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3346 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3347 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3348
004d836a 3349 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3350 pfs &= 0xc000000000000000LL;
3351 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3352 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3353
3354 cfm &= 0xc000000000000000LL;
3355 cfm |= rseslots;
004d836a 3356 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3357
64a5b29c
KB		 3358 /* We will attempt to find function descriptors in the .opd segment,
3359 but if we can't we'll construct them ourselves. That being the
004d836a 3360 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3361 funcdescaddr = sp - nfuncargs * 16;
3362 funcdescaddr &= ~0xfLL;
3363
3364 /* Adjust the stack pointer to it's new value. The calling conventions
3365 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3366 necessary for the memory slots and our function descriptors. */
64a5b29c 3367 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3368 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3369
64a5b29c
KB		 3370 /* Place the arguments where they belong. The arguments will be
3371 either placed in the RSE backing store or on the memory stack.
3372 In addition, floating point arguments or HFAs are placed in
004d836a 3373 floating point registers. */
16461d7d
KB		 3374 slotnum = 0;
3375 floatreg = IA64_FR8_REGNUM;
3376 for (argno = 0; argno < nargs; argno++)
3377 {
64a5b29c
KB		 3378 struct type *float_elt_type;
3379
16461d7d 3380 arg = args[argno];
4991999e 3381 type = check_typedef (value_type (arg));
16461d7d 3382 len = TYPE_LENGTH (type);
64a5b29c 3383
004d836a 3384 /* Special handling for function parameters. */
64a5b29c
KB		 3385 if (len == 8
3386 && TYPE_CODE (type) == TYPE_CODE_PTR
3387 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3388 {
3389 char val_buf[8];
3390
fbd9dcd3 3391 store_unsigned_integer (val_buf, 8,
0fd88904 3392 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3393 &funcdescaddr));
64a5b29c
KB		 3394 if (slotnum < rseslots)
3395 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3396 else
3397 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3398 slotnum++;
3399 continue;
3400 }
3401
004d836a 3402 /* Normal slots. */
98f96ba1
KB		 3403
3404 /* Skip odd slot if necessary... */
3405 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3406 slotnum++;
98f96ba1 3407
16461d7d
KB		 3408 argoffset = 0;
3409 while (len > 0)
3410 {
3411 char val_buf[8];
3412
3413 memset (val_buf, 0, 8);
0fd88904 3414 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3415
3416 if (slotnum < rseslots)
3417 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3418 else
3419 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3420
3421 argoffset += 8;
3422 len -= 8;
3423 slotnum++;
3424 }
64a5b29c 3425
004d836a 3426 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3427 float_elt_type = is_float_or_hfa_type (type);
3428 if (float_elt_type != NULL)
3429 {
3430 argoffset = 0;
3431 len = TYPE_LENGTH (type);
3432 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3433 {
004d836a 3434 char to[MAX_REGISTER_SIZE];
0fd88904 3435 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3436 to, builtin_type_ia64_ext);
3437 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3438 floatreg++;
3439 argoffset += TYPE_LENGTH (float_elt_type);
3440 len -= TYPE_LENGTH (float_elt_type);
3441 }
16461d7d
KB		 3442 }
3443 }
3444
004d836a 3445 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3446 if (struct_return)
3447 {
004d836a 3448 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3449 }
3450
b33e8514 3451 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3452
004d836a
JJ		 3453 if (global_pointer != 0)
3454 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3455
004d836a 3456 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3457
004d836a 3458 write_register (sp_regnum, sp);
16461d7d
KB		 3459
3460 return sp;
3461}
3462
004d836a
JJ		 3463static struct frame_id
3464ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3465{
004d836a 3466 char buf[8];
4afcc598 3467 CORE_ADDR sp, bsp;
004d836a
JJ		 3468
3469 frame_unwind_register (next_frame, sp_regnum, buf);
3470 sp = extract_unsigned_integer (buf, 8);
3471
4afcc598
JJ		 3472 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3473 bsp = extract_unsigned_integer (buf, 8);
3474
3475 if (gdbarch_debug >= 1)
3476 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3477 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3478 paddr_nz (frame_pc_unwind (next_frame)),
3479 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3480
3481 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3482}
3483
004d836a
JJ		 3484static CORE_ADDR
3485ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3486{
004d836a
JJ		 3487 char buf[8];
3488 CORE_ADDR ip, psr, pc;
3489
3490 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3491 ip = extract_unsigned_integer (buf, 8);
3492 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3493 psr = extract_unsigned_integer (buf, 8);
3494
3495 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3496 return pc;
16461d7d
KB		 3497}
3498
3499static void
004d836a 3500ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
16461d7d 3501{
004d836a 3502 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3503 {
004d836a
JJ		 3504 char to[MAX_REGISTER_SIZE];
3505 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3506 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3507 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3508 }
3509 else
004d836a 3510 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3511}
3512
3513static void
1750fa04
AC		 3514ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3515 struct regcache *regcache,
3516 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3517 CORE_ADDR *targ_addr, int *targ_len)
3518{
3519 *targ_addr = memaddr;
3520 *targ_len = nr_bytes;
3521}
3522
6926787d
AS		 3523static int
3524ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3525{
3526 info->bytes_per_line = SLOT_MULTIPLIER;
3527 return print_insn_ia64 (memaddr, info);
3528}
3529
16461d7d
KB		 3530static struct gdbarch *
3531ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3532{
3533 struct gdbarch *gdbarch;
244bc108 3534 struct gdbarch_tdep *tdep;
244bc108 3535
85bf2b91
JJ		 3536 /* If there is already a candidate, use it. */
3537 arches = gdbarch_list_lookup_by_info (arches, &info);
3538 if (arches != NULL)
3539 return arches->gdbarch;
16461d7d 3540
244bc108
KB		 3541 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3542 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3543
b33e8514 3544 tdep->sigcontext_register_address = 0;
698cb3f0 3545
004d836a
JJ		 3546 /* Define the ia64 floating-point format to gdb. */
3547 builtin_type_ia64_ext =
3548 init_type (TYPE_CODE_FLT, 128 / 8,
3549 0, "builtin_type_ia64_ext", NULL);
3550 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3551
5439edaa
AC		 3552 /* According to the ia64 specs, instructions that store long double
3553 floats in memory use a long-double format different than that
3554 used in the floating registers. The memory format matches the
3555 x86 extended float format which is 80 bits. An OS may choose to
3556 use this format (e.g. GNU/Linux) or choose to use a different
3557 format for storing long doubles (e.g. HPUX). In the latter case,
3558 the setting of the format may be moved/overridden in an
3559 OS-specific tdep file. */
32edc941
JJ		 3560 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3561
16461d7d
KB		 3562 set_gdbarch_short_bit (gdbarch, 16);
3563 set_gdbarch_int_bit (gdbarch, 32);
3564 set_gdbarch_long_bit (gdbarch, 64);
3565 set_gdbarch_long_long_bit (gdbarch, 64);
3566 set_gdbarch_float_bit (gdbarch, 32);
3567 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3568 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3569 set_gdbarch_ptr_bit (gdbarch, 64);
3570
004d836a
JJ		 3571 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3572 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3573 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3574 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3575
3576 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3577 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3578 gets a number of extra failures. */
b1e29e33 3579 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3580 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3581
004d836a
JJ		 3582 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3583 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3584 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3585 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3586 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3587 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3588 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3589
004d836a 3590 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3591
b5622e8d 3592 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3593 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3594
004d836a 3595 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3596 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3597
3598 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3599 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3600 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3601 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3602 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3603
3604 /* Settings for calling functions in the inferior. */
8dd5115e 3605 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3606 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3607 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3608
004d836a 3609 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3610#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3611 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3612 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3613 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3614#else
3615 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3616#endif
004d836a
JJ		 3617 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3618 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3619
3620 /* Settings that should be unnecessary. */
3621 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3622
16461d7d
KB		 3623 set_gdbarch_remote_translate_xfer_address (
3624 gdbarch, ia64_remote_translate_xfer_address);
3625
6926787d 3626 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3627 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3628
b33e8514
AS		 3629 /* Hook in ABI-specific overrides, if they have been registered. */
3630 gdbarch_init_osabi (info, gdbarch);
3631
16461d7d
KB		 3632 return gdbarch;
3633}
3634
a78f21af
AC		 3635extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3636
16461d7d
KB		 3637void
3638_initialize_ia64_tdep (void)
3639{
b33e8514 3640 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3641}
GDB Binutils - Deliverables
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