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[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
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16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
13547ab6
DJ		 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
16461d7d
KB		 22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
7d9b040b 40#include "infcall.h"
b33e8514 41#include "osabi.h"
9fc9f5e2 42#include "ia64-tdep.h"
16461d7d 43
968d1cb4 44#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 45#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
c5a27d9c
JJ		 48
49/* Note: KERNEL_START is supposed to be an address which is not going
50 to ever contain any valid unwind info. For ia64 linux, the choice
51 of 0xc000000000000000 is fairly safe since that's uncached space.
52
53 We use KERNEL_START as follows: after obtaining the kernel's
54 unwind table via getunwind(), we project its unwind data into
55 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
56 when ia64_access_mem() sees a memory access to this
57 address-range, we redirect it to ktab instead.
58
59 None of this hackery is needed with a modern kernel/libcs
60 which uses the kernel virtual DSO to provide access to the
61 kernel's unwind info. In that case, ktab_size remains 0 and
62 hence the value of KERNEL_START doesn't matter. */
63
64#define KERNEL_START 0xc000000000000000ULL
65
66static size_t ktab_size = 0;
67struct ia64_table_entry
68 {
69 uint64_t start_offset;
70 uint64_t end_offset;
71 uint64_t info_offset;
72 };
73
74static struct ia64_table_entry *ktab = NULL;
75
968d1cb4
JJ		 76#endif
77
698cb3f0
KB		 78/* An enumeration of the different IA-64 instruction types. */
79
16461d7d
KB		 80typedef enum instruction_type
81{
82 A, /* Integer ALU ; I-unit or M-unit */
83 I, /* Non-ALU integer; I-unit */
84 M, /* Memory ; M-unit */
85 F, /* Floating-point ; F-unit */
86 B, /* Branch ; B-unit */
87 L, /* Extended (L+X) ; I-unit */
88 X, /* Extended (L+X) ; I-unit */
89 undefined /* undefined or reserved */
90} instruction_type;
91
92/* We represent IA-64 PC addresses as the value of the instruction
93 pointer or'd with some bit combination in the low nibble which
94 represents the slot number in the bundle addressed by the
95 instruction pointer. The problem is that the Linux kernel
96 multiplies its slot numbers (for exceptions) by one while the
97 disassembler multiplies its slot numbers by 6. In addition, I've
98 heard it said that the simulator uses 1 as the multiplier.
99
100 I've fixed the disassembler so that the bytes_per_line field will
101 be the slot multiplier. If bytes_per_line comes in as zero, it
102 is set to six (which is how it was set up initially). -- objdump
103 displays pretty disassembly dumps with this value. For our purposes,
104 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
105 never want to also display the raw bytes the way objdump does. */
106
107#define SLOT_MULTIPLIER 1
108
109/* Length in bytes of an instruction bundle */
110
111#define BUNDLE_LEN 16
112
16461d7d
KB		 113static gdbarch_init_ftype ia64_gdbarch_init;
114
115static gdbarch_register_name_ftype ia64_register_name;
004d836a 116static gdbarch_register_type_ftype ia64_register_type;
16461d7d 117static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 118static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 119static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 120static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 121
004d836a
JJ		 122static struct type *builtin_type_ia64_ext;
123
124#define NUM_IA64_RAW_REGS 462
16461d7d 125
16461d7d
KB		 126static int sp_regnum = IA64_GR12_REGNUM;
127static int fp_regnum = IA64_VFP_REGNUM;
128static int lr_regnum = IA64_VRAP_REGNUM;
129
004d836a 130/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 131 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 132enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
133 V127_REGNUM = V32_REGNUM + 95,
134 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 135
136/* Array of register names; There should be ia64_num_regs strings in
137 the initializer. */
138
139static char *ia64_register_names[] =
140{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
143 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
16461d7d
KB		 156
157 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
158 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
159 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
160 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
161 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
162 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
163 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
164 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
165 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
166 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
167 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
168 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
169 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
170 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
171 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
172 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
173
004d836a
JJ		 174 "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
16461d7d
KB		 182
183 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
184
185 "vfp", "vrap",
186
187 "pr", "ip", "psr", "cfm",
188
189 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
190 "", "", "", "", "", "", "", "",
191 "rsc", "bsp", "bspstore", "rnat",
192 "", "fcr", "", "",
193 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
194 "ccv", "", "", "", "unat", "", "", "",
195 "fpsr", "", "", "", "itc",
196 "", "", "", "", "", "", "", "", "", "",
197 "", "", "", "", "", "", "", "", "",
198 "pfs", "lc", "ec",
199 "", "", "", "", "", "", "", "", "", "",
200 "", "", "", "", "", "", "", "", "", "",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "",
206 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
207 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
208 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
209 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
210 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
211 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
212 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
213 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
214 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
215 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
216 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
217 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
218 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
219 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
220 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
221 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 222
223 "bof",
224
225 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
226 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
227 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
228 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
229 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
230 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
231 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
232 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
233 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
234 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
235 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
236 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
237
238 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
239 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
240 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
241 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
242 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
243 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
244 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
245 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 246};
247
004d836a
JJ		 248struct ia64_frame_cache
249{
250 CORE_ADDR base; /* frame pointer base for frame */
251 CORE_ADDR pc; /* function start pc for frame */
252 CORE_ADDR saved_sp; /* stack pointer for frame */
253 CORE_ADDR bsp; /* points at r32 for the current frame */
254 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 255 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 256 int frameless;
257 int sof; /* Size of frame (decoded from cfm value) */
258 int sol; /* Size of locals (decoded from cfm value) */
259 int sor; /* Number of rotating registers. (decoded from cfm value) */
260 CORE_ADDR after_prologue;
261 /* Address of first instruction after the last
262 prologue instruction; Note that there may
263 be instructions from the function's body
264 intermingled with the prologue. */
265 int mem_stack_frame_size;
266 /* Size of the memory stack frame (may be zero),
267 or -1 if it has not been determined yet. */
268 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 269 for this frame. 0 if no register is being used
16461d7d 270 as the frame pointer. */
004d836a
JJ		 271
272 /* Saved registers. */
273 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
274
275};
244bc108 276
698cb3f0
KB		 277#define SIGCONTEXT_REGISTER_ADDRESS \
278 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 279
004d836a
JJ		 280int
281ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
282 struct reggroup *group)
16461d7d 283{
004d836a
JJ		 284 int vector_p;
285 int float_p;
286 int raw_p;
287 if (group == all_reggroup)
288 return 1;
289 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
290 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
291 raw_p = regnum < NUM_IA64_RAW_REGS;
292 if (group == float_reggroup)
293 return float_p;
294 if (group == vector_reggroup)
295 return vector_p;
296 if (group == general_reggroup)
297 return (!vector_p && !float_p);
298 if (group == save_reggroup || group == restore_reggroup)
299 return raw_p;
300 return 0;
16461d7d
KB		 301}
302
004d836a
JJ		 303static const char *
304ia64_register_name (int reg)
16461d7d 305{
004d836a 306 return ia64_register_names[reg];
16461d7d
KB		 307}
308
004d836a
JJ		 309struct type *
310ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 311{
004d836a
JJ		 312 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
313 return builtin_type_ia64_ext;
314 else
315 return builtin_type_long;
16461d7d
KB		 316}
317
a78f21af 318static int
004d836a 319ia64_dwarf_reg_to_regnum (int reg)
16461d7d 320{
004d836a
JJ		 321 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
322 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
323 return reg;
16461d7d
KB		 324}
325
4afcc598 326static int
2fda21a6 327floatformat_valid (const struct floatformat *fmt, const void *from)
4afcc598
JJ		 328{
329 return 1;
330}
331
16461d7d
KB		 332const struct floatformat floatformat_ia64_ext =
333{
334 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 335 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 336};
337
16461d7d
KB		 338
339/* Extract ``len'' bits from an instruction bundle starting at
340 bit ``from''. */
341
244bc108 342static long long
16461d7d
KB		 343extract_bit_field (char *bundle, int from, int len)
344{
345 long long result = 0LL;
346 int to = from + len;
347 int from_byte = from / 8;
348 int to_byte = to / 8;
349 unsigned char *b = (unsigned char *) bundle;
350 unsigned char c;
351 int lshift;
352 int i;
353
354 c = b[from_byte];
355 if (from_byte == to_byte)
356 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
357 result = c >> (from % 8);
358 lshift = 8 - (from % 8);
359
360 for (i = from_byte+1; i < to_byte; i++)
361 {
362 result |= ((long long) b[i]) << lshift;
363 lshift += 8;
364 }
365
366 if (from_byte < to_byte && (to % 8 != 0))
367 {
368 c = b[to_byte];
369 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
370 result |= ((long long) c) << lshift;
371 }
372
373 return result;
374}
375
376/* Replace the specified bits in an instruction bundle */
377
244bc108 378static void
16461d7d
KB		 379replace_bit_field (char *bundle, long long val, int from, int len)
380{
381 int to = from + len;
382 int from_byte = from / 8;
383 int to_byte = to / 8;
384 unsigned char *b = (unsigned char *) bundle;
385 unsigned char c;
386
387 if (from_byte == to_byte)
388 {
389 unsigned char left, right;
390 c = b[from_byte];
391 left = (c >> (to % 8)) << (to % 8);
392 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
393 c = (unsigned char) (val & 0xff);
394 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
395 c |= right | left;
396 b[from_byte] = c;
397 }
398 else
399 {
400 int i;
401 c = b[from_byte];
402 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
403 c = c | (val << (from % 8));
404 b[from_byte] = c;
405 val >>= 8 - from % 8;
406
407 for (i = from_byte+1; i < to_byte; i++)
408 {
409 c = val & 0xff;
410 val >>= 8;
411 b[i] = c;
412 }
413
414 if (to % 8 != 0)
415 {
416 unsigned char cv = (unsigned char) val;
417 c = b[to_byte];
418 c = c >> (to % 8) << (to % 8);
419 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
420 b[to_byte] = c;
421 }
422 }
423}
424
425/* Return the contents of slot N (for N = 0, 1, or 2) in
426 and instruction bundle */
427
244bc108 428static long long
2fc3ac7e 429slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 430{
431 return extract_bit_field (bundle, 5+41*slotnum, 41);
432}
433
434/* Store an instruction in an instruction bundle */
435
244bc108 436static void
2fc3ac7e 437replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 438{
439 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
440}
441
64a5b29c 442static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 443{
444 { M, I, I }, /* 00 */
445 { M, I, I }, /* 01 */
446 { M, I, I }, /* 02 */
447 { M, I, I }, /* 03 */
448 { M, L, X }, /* 04 */
449 { M, L, X }, /* 05 */
450 { undefined, undefined, undefined }, /* 06 */
451 { undefined, undefined, undefined }, /* 07 */
452 { M, M, I }, /* 08 */
453 { M, M, I }, /* 09 */
454 { M, M, I }, /* 0A */
455 { M, M, I }, /* 0B */
456 { M, F, I }, /* 0C */
457 { M, F, I }, /* 0D */
458 { M, M, F }, /* 0E */
459 { M, M, F }, /* 0F */
460 { M, I, B }, /* 10 */
461 { M, I, B }, /* 11 */
462 { M, B, B }, /* 12 */
463 { M, B, B }, /* 13 */
464 { undefined, undefined, undefined }, /* 14 */
465 { undefined, undefined, undefined }, /* 15 */
466 { B, B, B }, /* 16 */
467 { B, B, B }, /* 17 */
468 { M, M, B }, /* 18 */
469 { M, M, B }, /* 19 */
470 { undefined, undefined, undefined }, /* 1A */
471 { undefined, undefined, undefined }, /* 1B */
472 { M, F, B }, /* 1C */
473 { M, F, B }, /* 1D */
474 { undefined, undefined, undefined }, /* 1E */
475 { undefined, undefined, undefined }, /* 1F */
476};
477
478/* Fetch and (partially) decode an instruction at ADDR and return the
479 address of the next instruction to fetch. */
480
481static CORE_ADDR
482fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
483{
484 char bundle[BUNDLE_LEN];
485 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
486 long long template;
487 int val;
488
c26e1c2b
KB		 489 /* Warn about slot numbers greater than 2. We used to generate
490 an error here on the assumption that the user entered an invalid
491 address. But, sometimes GDB itself requests an invalid address.
492 This can (easily) happen when execution stops in a function for
493 which there are no symbols. The prologue scanner will attempt to
494 find the beginning of the function - if the nearest symbol
495 happens to not be aligned on a bundle boundary (16 bytes), the
496 resulting starting address will cause GDB to think that the slot
497 number is too large.
498
499 So we warn about it and set the slot number to zero. It is
500 not necessarily a fatal condition, particularly if debugging
501 at the assembly language level. */
16461d7d 502 if (slotnum > 2)
c26e1c2b 503 {
8a3fe4f8
AC		 504 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
505 "Using slot 0 instead"));
c26e1c2b
KB		 506 slotnum = 0;
507 }
16461d7d
KB		 508
509 addr &= ~0x0f;
510
511 val = target_read_memory (addr, bundle, BUNDLE_LEN);
512
513 if (val != 0)
514 return 0;
515
516 *instr = slotN_contents (bundle, slotnum);
517 template = extract_bit_field (bundle, 0, 5);
518 *it = template_encoding_table[(int)template][slotnum];
519
64a5b29c 520 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 521 addr += 16;
522 else
523 addr += (slotnum + 1) * SLOT_MULTIPLIER;
524
525 return addr;
526}
527
528/* There are 5 different break instructions (break.i, break.b,
529 break.m, break.f, and break.x), but they all have the same
530 encoding. (The five bit template in the low five bits of the
531 instruction bundle distinguishes one from another.)
532
533 The runtime architecture manual specifies that break instructions
534 used for debugging purposes must have the upper two bits of the 21
535 bit immediate set to a 0 and a 1 respectively. A breakpoint
536 instruction encodes the most significant bit of its 21 bit
537 immediate at bit 36 of the 41 bit instruction. The penultimate msb
538 is at bit 25 which leads to the pattern below.
539
540 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
541 it turns out that 0x80000 was used as the syscall break in the early
542 simulators. So I changed the pattern slightly to do "break.i 0x080001"
543 instead. But that didn't work either (I later found out that this
544 pattern was used by the simulator that I was using.) So I ended up
545 using the pattern seen below. */
546
547#if 0
aaab4dba 548#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 549#endif
aaab4dba 550#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 551
552static int
8181d85f 553ia64_memory_insert_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 554{
8181d85f 555 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 556 char bundle[BUNDLE_LEN];
557 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
558 long long instr;
559 int val;
126fa72d 560 int template;
16461d7d
KB		 561
562 if (slotnum > 2)
8a3fe4f8 563 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 564
565 addr &= ~0x0f;
566
567 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 568
569 /* Check for L type instruction in 2nd slot, if present then
570 bump up the slot number to the 3rd slot */
571 template = extract_bit_field (bundle, 0, 5);
572 if (slotnum == 1 && template_encoding_table[template][1] == L)
573 {
574 slotnum = 2;
575 }
576
16461d7d 577 instr = slotN_contents (bundle, slotnum);
8181d85f
DJ		 578 memcpy (bp_tgt->shadow_contents, &instr, sizeof (instr));
579 bp_tgt->placed_size = bp_tgt->shadow_len = sizeof (instr);
aaab4dba 580 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 581 if (val == 0)
582 target_write_memory (addr, bundle, BUNDLE_LEN);
583
584 return val;
585}
586
587static int
8181d85f 588ia64_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 589{
8181d85f 590 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 591 char bundle[BUNDLE_LEN];
592 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
593 long long instr;
594 int val;
126fa72d 595 int template;
16461d7d
KB		 596
597 addr &= ~0x0f;
598
599 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 600
601 /* Check for L type instruction in 2nd slot, if present then
602 bump up the slot number to the 3rd slot */
603 template = extract_bit_field (bundle, 0, 5);
604 if (slotnum == 1 && template_encoding_table[template][1] == L)
605 {
606 slotnum = 2;
607 }
608
8181d85f 609 memcpy (&instr, bp_tgt->shadow_contents, sizeof instr);
16461d7d
KB		 610 replace_slotN_contents (bundle, instr, slotnum);
611 if (val == 0)
612 target_write_memory (addr, bundle, BUNDLE_LEN);
613
614 return val;
615}
616
617/* We don't really want to use this, but remote.c needs to call it in order
618 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 619const unsigned char *
fba45db2 620ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 621{
622 static unsigned char breakpoint[] =
623 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
624 *lenptr = sizeof (breakpoint);
625#if 0
626 *pcptr &= ~0x0f;
627#endif
628 return breakpoint;
629}
630
a78f21af 631static CORE_ADDR
39f77062 632ia64_read_pc (ptid_t ptid)
16461d7d 633{
39f77062
KB		 634 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
635 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 636 int slot_num = (psr_value >> 41) & 3;
637
638 return pc_value | (slot_num * SLOT_MULTIPLIER);
639}
640
54a5c8d8 641void
39f77062 642ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 643{
644 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 645 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 646 psr_value &= ~(3LL << 41);
647 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
648
649 new_pc &= ~0xfLL;
650
39f77062
KB		 651 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
652 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 653}
654
655#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
656
657/* Returns the address of the slot that's NSLOTS slots away from
658 the address ADDR. NSLOTS may be positive or negative. */
659static CORE_ADDR
660rse_address_add(CORE_ADDR addr, int nslots)
661{
662 CORE_ADDR new_addr;
663 int mandatory_nat_slots = nslots / 63;
664 int direction = nslots < 0 ? -1 : 1;
665
666 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
667
668 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
669 new_addr += 8 * direction;
670
671 if (IS_NaT_COLLECTION_ADDR(new_addr))
672 new_addr += 8 * direction;
673
674 return new_addr;
675}
676
004d836a
JJ		 677static void
678ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 679 int regnum, gdb_byte *buf)
16461d7d 680{
004d836a 681 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 682 {
88d82102 683#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c
JJ		 684 /* First try and use the libunwind special reg accessor, otherwise fallback to
685 standard logic. */
686 if (!libunwind_is_initialized ()
687 || libunwind_get_reg_special (gdbarch, regnum, buf) != 0)
88d82102 688#endif
004d836a 689 {
c5a27d9c
JJ		 690 /* The fallback position is to assume that r32-r127 are found sequentially
691 in memory starting at $bof. This isn't always true, but without libunwind,
692 this is the best we can do. */
693 ULONGEST cfm;
694 ULONGEST bsp;
695 CORE_ADDR reg;
696 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
697 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
698
699 /* The bsp points at the end of the register frame so we
700 subtract the size of frame from it to get start of register frame. */
701 bsp = rse_address_add (bsp, -(cfm & 0x7f));
702
703 if ((cfm & 0x7f) > regnum - V32_REGNUM)
704 {
705 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
706 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
707 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
708 }
709 else
710 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a 711 }
004d836a
JJ		 712 }
713 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
714 {
715 ULONGEST unatN_val;
716 ULONGEST unat;
717 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
718 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 719 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 720 }
721 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
722 {
723 ULONGEST natN_val = 0;
724 ULONGEST bsp;
725 ULONGEST cfm;
726 CORE_ADDR gr_addr = 0;
727 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
728 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
729
730 /* The bsp points at the end of the register frame so we
731 subtract the size of frame from it to get start of register frame. */
732 bsp = rse_address_add (bsp, -(cfm & 0x7f));
733
734 if ((cfm & 0x7f) > regnum - V32_REGNUM)
735 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
736
737 if (gr_addr != 0)
738 {
739 /* Compute address of nat collection bits. */
740 CORE_ADDR nat_addr = gr_addr | 0x1f8;
741 CORE_ADDR nat_collection;
742 int nat_bit;
743 /* If our nat collection address is bigger than bsp, we have to get
744 the nat collection from rnat. Otherwise, we fetch the nat
745 collection from the computed address. */
746 if (nat_addr >= bsp)
747 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
748 else
749 nat_collection = read_memory_integer (nat_addr, 8);
750 nat_bit = (gr_addr >> 3) & 0x3f;
751 natN_val = (nat_collection >> nat_bit) & 1;
752 }
753
aa2a9a3c 754 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 755 }
004d836a
JJ		 756 else if (regnum == VBOF_REGNUM)
757 {
758 /* A virtual register frame start is provided for user convenience.
759 It can be calculated as the bsp - sof (sizeof frame). */
760 ULONGEST bsp, vbsp;
761 ULONGEST cfm;
762 CORE_ADDR reg;
763 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
764 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
765
766 /* The bsp points at the end of the register frame so we
767 subtract the size of frame from it to get beginning of frame. */
768 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 769 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 770 }
771 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
772 {
773 ULONGEST pr;
774 ULONGEST cfm;
775 ULONGEST prN_val;
776 CORE_ADDR reg;
777 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
778 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
779
780 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
781 {
782 /* Fetch predicate register rename base from current frame
783 marker for this frame. */
784 int rrb_pr = (cfm >> 32) & 0x3f;
785
786 /* Adjust the register number to account for register rotation. */
787 regnum = VP16_REGNUM
788 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
789 }
790 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 791 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 792 }
793 else
aa2a9a3c 794 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 795}
796
004d836a
JJ		 797static void
798ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 799 int regnum, const gdb_byte *buf)
16461d7d 800{
004d836a 801 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 802 {
004d836a
JJ		 803 ULONGEST bsp;
804 ULONGEST cfm;
805 CORE_ADDR reg;
806 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
807 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
808
809 bsp = rse_address_add (bsp, -(cfm & 0x7f));
810
811 if ((cfm & 0x7f) > regnum - V32_REGNUM)
812 {
813 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
814 write_memory (reg_addr, (void *)buf, 8);
815 }
816 }
817 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
818 {
819 ULONGEST unatN_val, unat, unatN_mask;
820 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 821 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 822 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
823 if (unatN_val == 0)
824 unat &= ~unatN_mask;
825 else if (unatN_val == 1)
826 unat |= unatN_mask;
827 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
828 }
829 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
830 {
831 ULONGEST natN_val;
832 ULONGEST bsp;
833 ULONGEST cfm;
834 CORE_ADDR gr_addr = 0;
835 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
836 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
837
838 /* The bsp points at the end of the register frame so we
839 subtract the size of frame from it to get start of register frame. */
840 bsp = rse_address_add (bsp, -(cfm & 0x7f));
841
842 if ((cfm & 0x7f) > regnum - V32_REGNUM)
843 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
844
aa2a9a3c 845 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 846
847 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
848 {
849 /* Compute address of nat collection bits. */
850 CORE_ADDR nat_addr = gr_addr | 0x1f8;
851 CORE_ADDR nat_collection;
852 int natN_bit = (gr_addr >> 3) & 0x3f;
853 ULONGEST natN_mask = (1LL << natN_bit);
854 /* If our nat collection address is bigger than bsp, we have to get
855 the nat collection from rnat. Otherwise, we fetch the nat
856 collection from the computed address. */
857 if (nat_addr >= bsp)
858 {
859 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
860 if (natN_val)
861 nat_collection |= natN_mask;
862 else
863 nat_collection &= ~natN_mask;
864 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
865 }
866 else
867 {
868 char nat_buf[8];
869 nat_collection = read_memory_integer (nat_addr, 8);
870 if (natN_val)
871 nat_collection |= natN_mask;
872 else
873 nat_collection &= ~natN_mask;
aa2a9a3c 874 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 875 write_memory (nat_addr, nat_buf, 8);
876 }
877 }
878 }
879 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
880 {
881 ULONGEST pr;
882 ULONGEST cfm;
883 ULONGEST prN_val;
884 ULONGEST prN_mask;
885
886 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
887 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
888
889 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
890 {
891 /* Fetch predicate register rename base from current frame
892 marker for this frame. */
893 int rrb_pr = (cfm >> 32) & 0x3f;
894
895 /* Adjust the register number to account for register rotation. */
896 regnum = VP16_REGNUM
897 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
898 }
aa2a9a3c 899 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 900 prN_mask = (1LL << (regnum - VP0_REGNUM));
901 if (prN_val == 0)
902 pr &= ~prN_mask;
903 else if (prN_val == 1)
904 pr |= prN_mask;
905 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 906 }
16461d7d
KB		 907}
908
004d836a
JJ		 909/* The ia64 needs to convert between various ieee floating-point formats
910 and the special ia64 floating point register format. */
911
912static int
913ia64_convert_register_p (int regno, struct type *type)
914{
915 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
916}
917
918static void
919ia64_register_to_value (struct frame_info *frame, int regnum,
88d82102 920 struct type *valtype, gdb_byte *out)
004d836a
JJ		 921{
922 char in[MAX_REGISTER_SIZE];
923 frame_register_read (frame, regnum, in);
924 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
925}
926
927static void
928ia64_value_to_register (struct frame_info *frame, int regnum,
88d82102 929 struct type *valtype, const gdb_byte *in)
004d836a
JJ		 930{
931 char out[MAX_REGISTER_SIZE];
932 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
933 put_frame_register (frame, regnum, out);
934}
935
936
58ab00f9
KB		 937/* Limit the number of skipped non-prologue instructions since examining
938 of the prologue is expensive. */
5ea2bd7f 939static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 940
941/* Given PC representing the starting address of a function, and
942 LIM_PC which is the (sloppy) limit to which to scan when looking
943 for a prologue, attempt to further refine this limit by using
944 the line data in the symbol table. If successful, a better guess
945 on where the prologue ends is returned, otherwise the previous
946 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
947 which will be set to indicate whether the returned limit may be
948 used with no further scanning in the event that the function is
949 frameless. */
950
634aa483
AC		 951/* FIXME: cagney/2004-02-14: This function and logic have largely been
952 superseded by skip_prologue_using_sal. */
953
58ab00f9
KB		 954static CORE_ADDR
955refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
956{
957 struct symtab_and_line prologue_sal;
958 CORE_ADDR start_pc = pc;
959
960 /* Start off not trusting the limit. */
961 *trust_limit = 0;
962
963 prologue_sal = find_pc_line (pc, 0);
964 if (prologue_sal.line != 0)
965 {
966 int i;
967 CORE_ADDR addr = prologue_sal.end;
968
969 /* Handle the case in which compiler's optimizer/scheduler
970 has moved instructions into the prologue. We scan ahead
971 in the function looking for address ranges whose corresponding
972 line number is less than or equal to the first one that we
973 found for the function. (It can be less than when the
974 scheduler puts a body instruction before the first prologue
975 instruction.) */
976 for (i = 2 * max_skip_non_prologue_insns;
977 i > 0 && (lim_pc == 0 || addr < lim_pc);
978 i--)
979 {
980 struct symtab_and_line sal;
981
982 sal = find_pc_line (addr, 0);
983 if (sal.line == 0)
984 break;
985 if (sal.line <= prologue_sal.line
986 && sal.symtab == prologue_sal.symtab)
987 {
988 prologue_sal = sal;
989 }
990 addr = sal.end;
991 }
992
993 if (lim_pc == 0 || prologue_sal.end < lim_pc)
994 {
995 lim_pc = prologue_sal.end;
996 if (start_pc == get_pc_function_start (lim_pc))
997 *trust_limit = 1;
998 }
999 }
1000 return lim_pc;
1001}
1002
16461d7d
KB		 1003#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1004 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1005 || (14 <= (_regnum_) && (_regnum_) <= 31))
1006#define imm9(_instr_) \
1007 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1008 | (((_instr_) & 0x00008000000LL) >> 20) \
1009 | (((_instr_) & 0x00000001fc0LL) >> 6))
1010
004d836a
JJ		 1011/* Allocate and initialize a frame cache. */
1012
1013static struct ia64_frame_cache *
1014ia64_alloc_frame_cache (void)
1015{
1016 struct ia64_frame_cache *cache;
1017 int i;
1018
1019 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1020
1021 /* Base address. */
1022 cache->base = 0;
1023 cache->pc = 0;
1024 cache->cfm = 0;
4afcc598 1025 cache->prev_cfm = 0;
004d836a
JJ		 1026 cache->sof = 0;
1027 cache->sol = 0;
1028 cache->sor = 0;
1029 cache->bsp = 0;
1030 cache->fp_reg = 0;
1031 cache->frameless = 1;
1032
1033 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1034 cache->saved_regs[i] = 0;
1035
1036 return cache;
1037}
1038
16461d7d 1039static CORE_ADDR
004d836a 1040examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1041{
1042 CORE_ADDR next_pc;
1043 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1044 instruction_type it;
1045 long long instr;
16461d7d
KB		 1046 int cfm_reg = 0;
1047 int ret_reg = 0;
1048 int fp_reg = 0;
1049 int unat_save_reg = 0;
1050 int pr_save_reg = 0;
1051 int mem_stack_frame_size = 0;
1052 int spill_reg = 0;
1053 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1054 char instores[8];
1055 char infpstores[8];
5ea2bd7f 1056 char reg_contents[256];
58ab00f9 1057 int trust_limit;
004d836a
JJ		 1058 int frameless = 1;
1059 int i;
1060 CORE_ADDR addr;
1061 char buf[8];
1062 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1063
1064 memset (instores, 0, sizeof instores);
1065 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1066 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1067
004d836a
JJ		 1068 if (cache->after_prologue != 0
1069 && cache->after_prologue <= lim_pc)
1070 return cache->after_prologue;
16461d7d 1071
58ab00f9 1072 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1073 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1074
1075 /* We want to check if we have a recognizable function start before we
1076 look ahead for a prologue. */
16461d7d
KB		 1077 if (pc < lim_pc && next_pc
1078 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1079 {
5ea2bd7f 1080 /* alloc - start of a regular function. */
16461d7d
KB		 1081 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1082 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1083 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1084 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1085
1086 /* Verify that the current cfm matches what we think is the
1087 function start. If we have somehow jumped within a function,
1088 we do not want to interpret the prologue and calculate the
1089 addresses of various registers such as the return address.
1090 We will instead treat the frame as frameless. */
1091 if (!next_frame ||
1092 (sof == (cache->cfm & 0x7f) &&
1093 sol == ((cache->cfm >> 7) & 0x7f)))
1094 frameless = 0;
1095
16461d7d
KB		 1096 cfm_reg = rN;
1097 last_prologue_pc = next_pc;
1098 pc = next_pc;
1099 }
1100 else
58ab00f9 1101 {
5ea2bd7f
JJ		 1102 /* Look for a leaf routine. */
1103 if (pc < lim_pc && next_pc
1104 && (it == I || it == M)
1105 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1106 {
1107 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1108 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1109 | ((instr & 0x001f8000000LL) >> 20)
1110 | ((instr & 0x000000fe000LL) >> 13));
1111 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1112 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1113 int qp = (int) (instr & 0x0000000003fLL);
1114 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1115 {
1116 /* mov r2, r12 - beginning of leaf routine */
1117 fp_reg = rN;
5ea2bd7f
JJ		 1118 last_prologue_pc = next_pc;
1119 }
1120 }
1121
1122 /* If we don't recognize a regular function or leaf routine, we are
1123 done. */
1124 if (!fp_reg)
1125 {
1126 pc = lim_pc;
1127 if (trust_limit)
1128 last_prologue_pc = lim_pc;
1129 }
58ab00f9 1130 }
16461d7d
KB		 1131
1132 /* Loop, looking for prologue instructions, keeping track of
1133 where preserved registers were spilled. */
1134 while (pc < lim_pc)
1135 {
1136 next_pc = fetch_instruction (pc, &it, &instr);
1137 if (next_pc == 0)
1138 break;
1139
594706e6 1140 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1141 {
102d615a
JJ		 1142 /* Exit loop upon hitting a non-nop branch instruction. */
1143 if (trust_limit)
1144 lim_pc = pc;
1145 break;
1146 }
1147 else if (((instr & 0x3fLL) != 0LL) &&
1148 (frameless || ret_reg != 0))
1149 {
1150 /* Exit loop upon hitting a predicated instruction if
1151 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1152 if (trust_limit)
1153 lim_pc = pc;
0927a22b
KB		 1154 break;
1155 }
1156 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1157 {
1158 /* Move from BR */
1159 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1160 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1161 int qp = (int) (instr & 0x0000000003f);
1162
1163 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1164 {
1165 ret_reg = rN;
1166 last_prologue_pc = next_pc;
1167 }
1168 }
1169 else if ((it == I || it == M)
1170 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1171 {
1172 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1173 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1174 | ((instr & 0x001f8000000LL) >> 20)
1175 | ((instr & 0x000000fe000LL) >> 13));
1176 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1177 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1178 int qp = (int) (instr & 0x0000000003fLL);
1179
1180 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1181 {
1182 /* mov rN, r12 */
1183 fp_reg = rN;
1184 last_prologue_pc = next_pc;
1185 }
1186 else if (qp == 0 && rN == 12 && rM == 12)
1187 {
1188 /* adds r12, -mem_stack_frame_size, r12 */
1189 mem_stack_frame_size -= imm;
1190 last_prologue_pc = next_pc;
1191 }
1192 else if (qp == 0 && rN == 2
1193 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1194 {
004d836a
JJ		 1195 char buf[MAX_REGISTER_SIZE];
1196 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1197 /* adds r2, spilloffset, rFramePointer
1198 or
1199 adds r2, spilloffset, r12
1200
1201 Get ready for stf.spill or st8.spill instructions.
1202 The address to start spilling at is loaded into r2.
1203 FIXME: Why r2? That's what gcc currently uses; it
1204 could well be different for other compilers. */
1205
1206 /* Hmm... whether or not this will work will depend on
1207 where the pc is. If it's still early in the prologue
1208 this'll be wrong. FIXME */
004d836a
JJ		 1209 if (next_frame)
1210 {
1211 frame_unwind_register (next_frame, sp_regnum, buf);
1212 saved_sp = extract_unsigned_integer (buf, 8);
1213 }
1214 spill_addr = saved_sp
16461d7d
KB		 1215 + (rM == 12 ? 0 : mem_stack_frame_size)
1216 + imm;
1217 spill_reg = rN;
1218 last_prologue_pc = next_pc;
1219 }
5ea2bd7f
JJ		 1220 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1221 rN < 256 && imm == 0)
1222 {
1223 /* mov rN, rM where rM is an input register */
1224 reg_contents[rN] = rM;
1225 last_prologue_pc = next_pc;
1226 }
1227 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1228 rM == 2)
1229 {
1230 /* mov r12, r2 */
1231 last_prologue_pc = next_pc;
1232 break;
1233 }
16461d7d
KB		 1234 }
1235 else if (it == M
1236 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1237 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1238 {
1239 /* stf.spill [rN] = fM, imm9
1240 or
1241 stf.spill [rN] = fM */
1242
1243 int imm = imm9(instr);
1244 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1245 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1246 int qp = (int) (instr & 0x0000000003fLL);
1247 if (qp == 0 && rN == spill_reg && spill_addr != 0
1248 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1249 {
004d836a 1250 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1251
594706e6 1252 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1253 spill_addr += imm;
1254 else
1255 spill_addr = 0; /* last one; must be done */
1256 last_prologue_pc = next_pc;
1257 }
1258 }
1259 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1260 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1261 {
1262 /* mov.m rN = arM
1263 or
1264 mov.i rN = arM */
1265
1266 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1267 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1268 int qp = (int) (instr & 0x0000000003fLL);
1269 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1270 {
1271 /* We have something like "mov.m r3 = ar.unat". Remember the
1272 r3 (or whatever) and watch for a store of this register... */
1273 unat_save_reg = rN;
1274 last_prologue_pc = next_pc;
1275 }
1276 }
1277 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1278 {
1279 /* mov rN = pr */
1280 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1281 int qp = (int) (instr & 0x0000000003fLL);
1282 if (qp == 0 && isScratch (rN))
1283 {
1284 pr_save_reg = rN;
1285 last_prologue_pc = next_pc;
1286 }
1287 }
1288 else if (it == M
1289 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1290 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1291 {
1292 /* st8 [rN] = rM
1293 or
1294 st8 [rN] = rM, imm9 */
1295 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1296 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1297 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1298 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1299 if (qp == 0 && rN == spill_reg && spill_addr != 0
1300 && (rM == unat_save_reg || rM == pr_save_reg))
1301 {
1302 /* We've found a spill of either the UNAT register or the PR
1303 register. (Well, not exactly; what we've actually found is
1304 a spill of the register that UNAT or PR was moved to).
1305 Record that fact and move on... */
1306 if (rM == unat_save_reg)
1307 {
1308 /* Track UNAT register */
004d836a 1309 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1310 unat_save_reg = 0;
1311 }
1312 else
1313 {
1314 /* Track PR register */
004d836a 1315 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1316 pr_save_reg = 0;
1317 }
1318 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1319 /* st8 [rN] = rM, imm9 */
1320 spill_addr += imm9(instr);
1321 else
1322 spill_addr = 0; /* must be done spilling */
1323 last_prologue_pc = next_pc;
1324 }
0927a22b
KB		 1325 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1326 {
1327 /* Allow up to one store of each input register. */
1328 instores[rM-32] = 1;
1329 last_prologue_pc = next_pc;
1330 }
5ea2bd7f
JJ		 1331 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1332 !instores[indirect-32])
1333 {
1334 /* Allow an indirect store of an input register. */
1335 instores[indirect-32] = 1;
1336 last_prologue_pc = next_pc;
1337 }
0927a22b
KB		 1338 }
1339 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1340 {
1341 /* One of
1342 st1 [rN] = rM
1343 st2 [rN] = rM
1344 st4 [rN] = rM
1345 st8 [rN] = rM
1346 Note that the st8 case is handled in the clause above.
1347
1348 Advance over stores of input registers. One store per input
1349 register is permitted. */
1350 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1351 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1352 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1353 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1354 {
1355 instores[rM-32] = 1;
1356 last_prologue_pc = next_pc;
1357 }
5ea2bd7f
JJ		 1358 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1359 !instores[indirect-32])
1360 {
1361 /* Allow an indirect store of an input register. */
1362 instores[indirect-32] = 1;
1363 last_prologue_pc = next_pc;
1364 }
0927a22b
KB		 1365 }
1366 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1367 {
1368 /* Either
1369 stfs [rN] = fM
1370 or
1371 stfd [rN] = fM
1372
1373 Advance over stores of floating point input registers. Again
1374 one store per register is permitted */
1375 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1376 int qp = (int) (instr & 0x0000000003fLL);
1377 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1378 {
1379 infpstores[fM-8] = 1;
1380 last_prologue_pc = next_pc;
1381 }
16461d7d
KB		 1382 }
1383 else if (it == M
1384 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1385 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1386 {
1387 /* st8.spill [rN] = rM
1388 or
1389 st8.spill [rN] = rM, imm9 */
1390 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1391 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1392 int qp = (int) (instr & 0x0000000003fLL);
1393 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1394 {
1395 /* We've found a spill of one of the preserved general purpose
1396 regs. Record the spill address and advance the spill
1397 register if appropriate. */
004d836a 1398 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1399 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1400 /* st8.spill [rN] = rM, imm9 */
1401 spill_addr += imm9(instr);
1402 else
1403 spill_addr = 0; /* Done spilling */
1404 last_prologue_pc = next_pc;
1405 }
1406 }
16461d7d
KB		 1407
1408 pc = next_pc;
1409 }
1410
004d836a
JJ		 1411 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1412 registers for the previous frame which will be needed later. */
16461d7d 1413
004d836a 1414 if (!frameless && next_frame)
da50a4b7 1415 {
004d836a
JJ		 1416 /* Extract the size of the rotating portion of the stack
1417 frame and the register rename base from the current
1418 frame marker. */
1419 cfm = cache->cfm;
1420 sor = cache->sor;
1421 sof = cache->sof;
1422 sol = cache->sol;
1423 rrb_gr = (cfm >> 18) & 0x7f;
1424
1425 /* Find the bof (beginning of frame). */
1426 bof = rse_address_add (cache->bsp, -sof);
1427
1428 for (i = 0, addr = bof;
1429 i < sof;
1430 i++, addr += 8)
1431 {
1432 if (IS_NaT_COLLECTION_ADDR (addr))
1433 {
1434 addr += 8;
1435 }
1436 if (i+32 == cfm_reg)
1437 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1438 if (i+32 == ret_reg)
1439 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1440 if (i+32 == fp_reg)
1441 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1442 }
16461d7d 1443
004d836a
JJ		 1444 /* For the previous argument registers we require the previous bof.
1445 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1446 cfm = 0;
004d836a
JJ		 1447 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1448 {
1449 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1450 }
1451 else if (cfm_reg != 0)
1452 {
1453 frame_unwind_register (next_frame, cfm_reg, buf);
1454 cfm = extract_unsigned_integer (buf, 8);
1455 }
1456 cache->prev_cfm = cfm;
1457
1458 if (cfm != 0)
1459 {
004d836a
JJ		 1460 sor = ((cfm >> 14) & 0xf) * 8;
1461 sof = (cfm & 0x7f);
1462 sol = (cfm >> 7) & 0x7f;
1463 rrb_gr = (cfm >> 18) & 0x7f;
1464
1465 /* The previous bof only requires subtraction of the sol (size of locals)
1466 due to the overlap between output and input of subsequent frames. */
1467 bof = rse_address_add (bof, -sol);
1468
1469 for (i = 0, addr = bof;
1470 i < sof;
1471 i++, addr += 8)
1472 {
1473 if (IS_NaT_COLLECTION_ADDR (addr))
1474 {
1475 addr += 8;
1476 }
1477 if (i < sor)
1478 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1479 = addr;
1480 else
1481 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1482 }
1483
1484 }
1485 }
1486
5ea2bd7f
JJ		 1487 /* Try and trust the lim_pc value whenever possible. */
1488 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1489 last_prologue_pc = lim_pc;
1490
1491 cache->frameless = frameless;
1492 cache->after_prologue = last_prologue_pc;
1493 cache->mem_stack_frame_size = mem_stack_frame_size;
1494 cache->fp_reg = fp_reg;
5ea2bd7f 1495
16461d7d
KB		 1496 return last_prologue_pc;
1497}
1498
1499CORE_ADDR
1500ia64_skip_prologue (CORE_ADDR pc)
1501{
004d836a
JJ		 1502 struct ia64_frame_cache cache;
1503 cache.base = 0;
1504 cache.after_prologue = 0;
1505 cache.cfm = 0;
1506 cache.bsp = 0;
1507
1508 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1509 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1510}
1511
004d836a
JJ		 1512
1513/* Normal frames. */
1514
1515static struct ia64_frame_cache *
1516ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1517{
004d836a
JJ		 1518 struct ia64_frame_cache *cache;
1519 char buf[8];
1520 CORE_ADDR cfm, sof, sol, bsp, psr;
1521 int i;
16461d7d 1522
004d836a
JJ		 1523 if (*this_cache)
1524 return *this_cache;
16461d7d 1525
004d836a
JJ		 1526 cache = ia64_alloc_frame_cache ();
1527 *this_cache = cache;
16461d7d 1528
004d836a
JJ		 1529 frame_unwind_register (next_frame, sp_regnum, buf);
1530 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1531
004d836a
JJ		 1532 /* We always want the bsp to point to the end of frame.
1533 This way, we can always get the beginning of frame (bof)
1534 by subtracting frame size. */
1535 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1536 cache->bsp = extract_unsigned_integer (buf, 8);
1537
1538 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1539 psr = extract_unsigned_integer (buf, 8);
1540
1541 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1542 cfm = extract_unsigned_integer (buf, 8);
1543
1544 cache->sof = (cfm & 0x7f);
1545 cache->sol = (cfm >> 7) & 0x7f;
1546 cache->sor = ((cfm >> 14) & 0xf) * 8;
1547
1548 cache->cfm = cfm;
1549
1550 cache->pc = frame_func_unwind (next_frame);
1551
1552 if (cache->pc != 0)
1553 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1554
1555 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1556
1557 return cache;
16461d7d
KB		 1558}
1559
a78f21af 1560static void
004d836a
JJ		 1561ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1562 struct frame_id *this_id)
16461d7d 1563{
004d836a
JJ		 1564 struct ia64_frame_cache *cache =
1565 ia64_frame_cache (next_frame, this_cache);
16461d7d 1566
c5a27d9c 1567 /* If outermost frame, mark with null frame id. */
004d836a 1568 if (cache->base == 0)
c5a27d9c
JJ		 1569 (*this_id) = null_frame_id;
1570 else
1571 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1572 if (gdbarch_debug >= 1)
1573 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1574 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1575 paddr_nz (this_id->code_addr),
1576 paddr_nz (this_id->stack_addr),
1577 paddr_nz (cache->bsp), next_frame);
004d836a 1578}
244bc108 1579
004d836a
JJ		 1580static void
1581ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1582 int regnum, int *optimizedp,
1583 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1584 int *realnump, gdb_byte *valuep)
004d836a
JJ		 1585{
1586 struct ia64_frame_cache *cache =
1587 ia64_frame_cache (next_frame, this_cache);
1588 char dummy_valp[MAX_REGISTER_SIZE];
1589 char buf[8];
1590
1591 gdb_assert (regnum >= 0);
244bc108 1592
004d836a 1593 if (!target_has_registers)
8a3fe4f8 1594 error (_("No registers."));
244bc108 1595
004d836a
JJ		 1596 *optimizedp = 0;
1597 *addrp = 0;
1598 *lvalp = not_lval;
1599 *realnump = -1;
244bc108 1600
004d836a
JJ		 1601 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1602 when valuep is not supplied. */
1603 if (!valuep)
1604 valuep = dummy_valp;
1605
aa2a9a3c 1606 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1607
1608 if (regnum == SP_REGNUM)
16461d7d
KB		 1609 {
1610 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1611 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1612 cache->base);
16461d7d
KB		 1613 }
1614 else if (regnum == IA64_BSP_REGNUM)
1615 {
004d836a
JJ		 1616 char cfm_valuep[MAX_REGISTER_SIZE];
1617 int cfm_optim;
1618 int cfm_realnum;
1619 enum lval_type cfm_lval;
1620 CORE_ADDR cfm_addr;
1621 CORE_ADDR bsp, prev_cfm, prev_bsp;
1622
1623 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1624 This corresponds to what the hardware bsp register will be if we pop the frame
1625 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1626 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1627 the start of the output registers. We can calculate the end of that frame by adding
1628 the size of output (sof (size of frame) - sol (size of locals)). */
1629 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1630 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1631 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1632
1633 bsp = rse_address_add (cache->bsp, -(cache->sof));
1634 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1635
aa2a9a3c 1636 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1637 prev_bsp);
1638 }
1639 else if (regnum == IA64_CFM_REGNUM)
1640 {
4afcc598
JJ		 1641 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1642
1643 if (addr != 0)
004d836a 1644 {
4afcc598
JJ		 1645 *lvalp = lval_memory;
1646 *addrp = addr;
1647 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1648 }
4afcc598
JJ		 1649 else if (cache->prev_cfm)
1650 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1651 else if (cache->frameless)
004d836a 1652 {
4afcc598
JJ		 1653 CORE_ADDR cfm = 0;
1654 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1655 }
16461d7d
KB		 1656 }
1657 else if (regnum == IA64_VFP_REGNUM)
1658 {
1659 /* If the function in question uses an automatic register (r32-r127)
1660 for the frame pointer, it'll be found by ia64_find_saved_register()
1661 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1662 still provide a value since we know the size of the frame. */
1663 CORE_ADDR vfp = cache->base;
aa2a9a3c 1664 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1665 }
004d836a 1666 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1667 {
004d836a 1668 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1669 int pr_optim;
004d836a 1670 int pr_realnum;
16461d7d
KB		 1671 enum lval_type pr_lval;
1672 CORE_ADDR pr_addr;
004d836a
JJ		 1673 ULONGEST prN_val;
1674 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1675 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1676 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1677 {
1678 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1679 marker for this frame. */
1680 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1681
004d836a
JJ		 1682 /* Adjust the register number to account for register rotation. */
1683 regnum = VP16_REGNUM
1684 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1685 }
004d836a
JJ		 1686 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1687 regnum - VP0_REGNUM, 1);
aa2a9a3c 1688 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1689 }
1690 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1691 {
004d836a 1692 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1693 int unat_optim;
004d836a 1694 int unat_realnum;
16461d7d
KB		 1695 enum lval_type unat_lval;
1696 CORE_ADDR unat_addr;
004d836a
JJ		 1697 ULONGEST unatN_val;
1698 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1699 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1700 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1701 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1702 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1703 unatN_val);
16461d7d
KB		 1704 }
1705 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1706 {
1707 int natval = 0;
1708 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1709 interested in. */
1710 CORE_ADDR gr_addr;
244bc108 1711
004d836a
JJ		 1712 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1713 + IA64_GR0_REGNUM];
1714 if (gr_addr != 0)
244bc108 1715 {
004d836a 1716 /* Compute address of nat collection bits. */
16461d7d 1717 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1718 CORE_ADDR bsp;
16461d7d
KB		 1719 CORE_ADDR nat_collection;
1720 int nat_bit;
1721 /* If our nat collection address is bigger than bsp, we have to get
1722 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1723 collection from the computed address. */
1724 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1725 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1726 if (nat_addr >= bsp)
004d836a
JJ		 1727 {
1728 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1729 nat_collection = extract_unsigned_integer (buf, 8);
1730 }
16461d7d
KB		 1731 else
1732 nat_collection = read_memory_integer (nat_addr, 8);
1733 nat_bit = (gr_addr >> 3) & 0x3f;
1734 natval = (nat_collection >> nat_bit) & 1;
1735 }
004d836a 1736
aa2a9a3c 1737 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1738 }
1739 else if (regnum == IA64_IP_REGNUM)
1740 {
004d836a 1741 CORE_ADDR pc = 0;
4afcc598 1742 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1743
4afcc598 1744 if (addr != 0)
004d836a 1745 {
4afcc598
JJ		 1746 *lvalp = lval_memory;
1747 *addrp = addr;
1748 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1749 pc = extract_unsigned_integer (buf, 8);
1750 }
4afcc598 1751 else if (cache->frameless)
004d836a 1752 {
4afcc598
JJ		 1753 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1754 pc = extract_unsigned_integer (buf, 8);
244bc108 1755 }
004d836a
JJ		 1756 pc &= ~0xf;
1757 store_unsigned_integer (valuep, 8, pc);
244bc108 1758 }
004d836a 1759 else if (regnum == IA64_PSR_REGNUM)
244bc108 1760 {
4afcc598
JJ		 1761 /* We don't know how to get the complete previous PSR, but we need it for
1762 the slot information when we unwind the pc (pc is formed of IP register
1763 plus slot information from PSR). To get the previous slot information,
1764 we mask it off the return address. */
004d836a
JJ		 1765 ULONGEST slot_num = 0;
1766 CORE_ADDR pc= 0;
1767 CORE_ADDR psr = 0;
4afcc598 1768 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1769
1770 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1771 psr = extract_unsigned_integer (buf, 8);
1772
4afcc598 1773 if (addr != 0)
244bc108 1774 {
4afcc598
JJ		 1775 *lvalp = lval_memory;
1776 *addrp = addr;
1777 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1778 pc = extract_unsigned_integer (buf, 8);
244bc108 1779 }
4afcc598 1780 else if (cache->frameless)
004d836a 1781 {
4afcc598
JJ		 1782 CORE_ADDR pc;
1783 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1784 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1785 }
1786 psr &= ~(3LL << 41);
1787 slot_num = pc & 0x3LL;
1788 psr |= (CORE_ADDR)slot_num << 41;
1789 store_unsigned_integer (valuep, 8, psr);
1790 }
4afcc598
JJ		 1791 else if (regnum == IA64_BR0_REGNUM)
1792 {
1793 CORE_ADDR br0 = 0;
1794 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1795 if (addr != 0)
1796 {
1797 *lvalp = lval_memory;
1798 *addrp = addr;
1799 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1800 br0 = extract_unsigned_integer (buf, 8);
1801 }
1802 store_unsigned_integer (valuep, 8, br0);
1803 }
004d836a
JJ		 1804 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1805 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1806 {
1807 CORE_ADDR addr = 0;
1808 if (regnum >= V32_REGNUM)
1809 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1810 addr = cache->saved_regs[regnum];
244bc108
KB		 1811 if (addr != 0)
1812 {
004d836a
JJ		 1813 *lvalp = lval_memory;
1814 *addrp = addr;
aa2a9a3c 1815 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1816 }
004d836a 1817 else if (cache->frameless)
244bc108 1818 {
004d836a
JJ		 1819 char r_valuep[MAX_REGISTER_SIZE];
1820 int r_optim;
1821 int r_realnum;
1822 enum lval_type r_lval;
1823 CORE_ADDR r_addr;
1824 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1825 CORE_ADDR addr = 0;
1826 if (regnum >= V32_REGNUM)
1827 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1828 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1829 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1830 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1831 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1832 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1833 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1834 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1835
1836 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1837 *lvalp = lval_memory;
1838 *addrp = addr;
aa2a9a3c 1839 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1840 }
16461d7d
KB		 1841 }
1842 else
1843 {
004d836a 1844 CORE_ADDR addr = 0;
3a854e23
KB		 1845 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1846 {
1847 /* Fetch floating point register rename base from current
004d836a
JJ		 1848 frame marker for this frame. */
1849 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1850
1851 /* Adjust the floating point register number to account for
004d836a 1852 register rotation. */
3a854e23
KB		 1853 regnum = IA64_FR32_REGNUM
1854 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1855 }
1856
004d836a
JJ		 1857 /* If we have stored a memory address, access the register. */
1858 addr = cache->saved_regs[regnum];
1859 if (addr != 0)
1860 {
1861 *lvalp = lval_memory;
1862 *addrp = addr;
aa2a9a3c 1863 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1864 }
1865 /* Otherwise, punt and get the current value of the register. */
1866 else
1867 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1868 }
4afcc598
JJ		 1869
1870 if (gdbarch_debug >= 1)
1871 fprintf_unfiltered (gdb_stdlog,
78ced177 1872 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1873 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1874 ? ia64_register_names[regnum] : "r??"),
1875 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1876}
004d836a
JJ		 1877
1878static const struct frame_unwind ia64_frame_unwind =
1879{
1880 NORMAL_FRAME,
1881 &ia64_frame_this_id,
1882 &ia64_frame_prev_register
1883};
1884
1885static const struct frame_unwind *
1886ia64_frame_sniffer (struct frame_info *next_frame)
1887{
1888 return &ia64_frame_unwind;
1889}
1890
1891/* Signal trampolines. */
1892
1893static void
1894ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1895{
1896 if (SIGCONTEXT_REGISTER_ADDRESS)
1897 {
1898 int regno;
1899
1900 cache->saved_regs[IA64_VRAP_REGNUM] =
1901 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1902 cache->saved_regs[IA64_CFM_REGNUM] =
1903 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1904 cache->saved_regs[IA64_PSR_REGNUM] =
1905 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1906 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1907 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1908 cache->saved_regs[IA64_RNAT_REGNUM] =
1909 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1910 cache->saved_regs[IA64_CCV_REGNUM] =
1911 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1912 cache->saved_regs[IA64_UNAT_REGNUM] =
1913 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1914 cache->saved_regs[IA64_FPSR_REGNUM] =
1915 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1916 cache->saved_regs[IA64_PFS_REGNUM] =
1917 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1918 cache->saved_regs[IA64_LC_REGNUM] =
1919 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1920 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1921 cache->saved_regs[regno] =
1922 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1923 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1924 cache->saved_regs[regno] =
1925 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1926 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1927 cache->saved_regs[regno] =
1928 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1929 }
1930}
1931
1932static struct ia64_frame_cache *
1933ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1934{
1935 struct ia64_frame_cache *cache;
1936 CORE_ADDR addr;
1937 char buf[8];
1938 int i;
1939
1940 if (*this_cache)
1941 return *this_cache;
1942
1943 cache = ia64_alloc_frame_cache ();
1944
1945 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1946 /* Note that frame size is hard-coded below. We cannot calculate it
1947 via prologue examination. */
1948 cache->base = extract_unsigned_integer (buf, 8) + 16;
1949
1950 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1951 cache->bsp = extract_unsigned_integer (buf, 8);
1952
1953 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1954 cache->cfm = extract_unsigned_integer (buf, 8);
1955 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1956
1957 ia64_sigtramp_frame_init_saved_regs (cache);
1958
1959 *this_cache = cache;
1960 return cache;
1961}
1962
1963static void
1964ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1965 void **this_cache, struct frame_id *this_id)
1966{
1967 struct ia64_frame_cache *cache =
1968 ia64_sigtramp_frame_cache (next_frame, this_cache);
1969
4afcc598
JJ		 1970 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1971 if (gdbarch_debug >= 1)
1972 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1973 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1974 paddr_nz (this_id->code_addr),
1975 paddr_nz (this_id->stack_addr),
1976 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1977}
1978
1979static void
1980ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1981 void **this_cache,
1982 int regnum, int *optimizedp,
1983 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1984 int *realnump, gdb_byte *valuep)
004d836a 1985{
4afcc598
JJ		 1986 char dummy_valp[MAX_REGISTER_SIZE];
1987 char buf[MAX_REGISTER_SIZE];
1988
1989 struct ia64_frame_cache *cache =
1990 ia64_sigtramp_frame_cache (next_frame, this_cache);
1991
1992 gdb_assert (regnum >= 0);
1993
1994 if (!target_has_registers)
8a3fe4f8 1995 error (_("No registers."));
4afcc598
JJ		 1996
1997 *optimizedp = 0;
1998 *addrp = 0;
1999 *lvalp = not_lval;
2000 *realnump = -1;
2001
2002 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2003 when valuep is not supplied. */
2004 if (!valuep)
2005 valuep = dummy_valp;
2006
2007 memset (valuep, 0, register_size (current_gdbarch, regnum));
2008
2009 if (regnum == IA64_IP_REGNUM)
2010 {
2011 CORE_ADDR pc = 0;
2012 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2013
2014 if (addr != 0)
2015 {
2016 *lvalp = lval_memory;
2017 *addrp = addr;
2018 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2019 pc = extract_unsigned_integer (buf, 8);
2020 }
2021 pc &= ~0xf;
2022 store_unsigned_integer (valuep, 8, pc);
2023 }
2024 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2025 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2026 {
2027 CORE_ADDR addr = 0;
2028 if (regnum >= V32_REGNUM)
2029 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2030 addr = cache->saved_regs[regnum];
2031 if (addr != 0)
2032 {
2033 *lvalp = lval_memory;
2034 *addrp = addr;
2035 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2036 }
2037 }
2038 else
2039 {
2040 /* All other registers not listed above. */
2041 CORE_ADDR addr = cache->saved_regs[regnum];
2042 if (addr != 0)
2043 {
2044 *lvalp = lval_memory;
2045 *addrp = addr;
2046 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2047 }
2048 }
004d836a 2049
4afcc598
JJ		 2050 if (gdbarch_debug >= 1)
2051 fprintf_unfiltered (gdb_stdlog,
78ced177 2052 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2053 (regnum < IA64_GR32_REGNUM
2054 || (regnum > IA64_GR127_REGNUM
2055 && regnum < LAST_PSEUDO_REGNUM))
2056 ? ia64_register_names[regnum]
2057 : (regnum < LAST_PSEUDO_REGNUM
2058 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2059 : "OUT_OF_RANGE"),
78ced177 2060 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2061}
2062
2063static const struct frame_unwind ia64_sigtramp_frame_unwind =
2064{
2065 SIGTRAMP_FRAME,
2066 ia64_sigtramp_frame_this_id,
2067 ia64_sigtramp_frame_prev_register
2068};
2069
2070static const struct frame_unwind *
2071ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2072{
2073 char *name;
2074 CORE_ADDR pc = frame_pc_unwind (next_frame);
2075
2076 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2077 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2078 return &ia64_sigtramp_frame_unwind;
2079
2080 return NULL;
2081}
2082\f
2083
2084static CORE_ADDR
2085ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2086{
2087 struct ia64_frame_cache *cache =
2088 ia64_frame_cache (next_frame, this_cache);
2089
2090 return cache->base;
2091}
2092
2093static const struct frame_base ia64_frame_base =
2094{
2095 &ia64_frame_unwind,
2096 ia64_frame_base_address,
2097 ia64_frame_base_address,
2098 ia64_frame_base_address
2099};
16461d7d 2100
968d1cb4
JJ		 2101#ifdef HAVE_LIBUNWIND_IA64_H
2102
2103struct ia64_unwind_table_entry
2104 {
2105 unw_word_t start_offset;
2106 unw_word_t end_offset;
2107 unw_word_t info_offset;
2108 };
2109
2110static __inline__ uint64_t
2111ia64_rse_slot_num (uint64_t addr)
2112{
2113 return (addr >> 3) & 0x3f;
2114}
2115
2116/* Skip over a designated number of registers in the backing
2117 store, remembering every 64th position is for NAT. */
2118static __inline__ uint64_t
2119ia64_rse_skip_regs (uint64_t addr, long num_regs)
2120{
2121 long delta = ia64_rse_slot_num(addr) + num_regs;
2122
2123 if (num_regs < 0)
2124 delta -= 0x3e;
2125 return addr + ((num_regs + delta/0x3f) << 3);
2126}
2127
2128/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2129 number to a libunwind register number. */
2130static int
2131ia64_gdb2uw_regnum (int regnum)
2132{
2133 if (regnum == sp_regnum)
2134 return UNW_IA64_SP;
2135 else if (regnum == IA64_BSP_REGNUM)
2136 return UNW_IA64_BSP;
2137 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2138 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2139 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2140 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2141 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2142 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2143 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2144 return -1;
2145 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2146 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2147 else if (regnum == IA64_PR_REGNUM)
2148 return UNW_IA64_PR;
2149 else if (regnum == IA64_IP_REGNUM)
2150 return UNW_REG_IP;
2151 else if (regnum == IA64_CFM_REGNUM)
2152 return UNW_IA64_CFM;
2153 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2154 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2155 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2156 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2157 else
2158 return -1;
2159}
2160
2161/* Gdb libunwind-frame callback function to convert from a libunwind register
2162 number to a ia64 gdb register number. */
2163static int
2164ia64_uw2gdb_regnum (int uw_regnum)
2165{
2166 if (uw_regnum == UNW_IA64_SP)
2167 return sp_regnum;
2168 else if (uw_regnum == UNW_IA64_BSP)
2169 return IA64_BSP_REGNUM;
2170 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2171 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2172 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2173 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2174 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2175 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2176 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2177 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2178 else if (uw_regnum == UNW_IA64_PR)
2179 return IA64_PR_REGNUM;
2180 else if (uw_regnum == UNW_REG_IP)
2181 return IA64_IP_REGNUM;
2182 else if (uw_regnum == UNW_IA64_CFM)
2183 return IA64_CFM_REGNUM;
2184 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2185 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2186 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2187 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2188 else
2189 return -1;
2190}
2191
2192/* Gdb libunwind-frame callback function to reveal if register is a float
2193 register or not. */
2194static int
2195ia64_is_fpreg (int uw_regnum)
2196{
2197 return unw_is_fpreg (uw_regnum);
2198}
2199
2200/* Libunwind callback accessor function for general registers. */
2201static int
2202ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2203 int write, void *arg)
2204{
2205 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2206 unw_word_t bsp, sof, sol, cfm, psr, ip;
2207 struct frame_info *next_frame = arg;
2208 long new_sof, old_sof;
2209 char buf[MAX_REGISTER_SIZE];
2210
2211 if (write)
2212 {
2213 if (regnum < 0)
2214 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2215 return 0;
2216
2217 switch (uw_regnum)
2218 {
2219 case UNW_REG_IP:
2220 ia64_write_pc (*val, inferior_ptid);
2221 break;
2222
2223 case UNW_IA64_AR_BSPSTORE:
2224 write_register (IA64_BSP_REGNUM, *val);
2225 break;
2226
2227 case UNW_IA64_AR_BSP:
2228 case UNW_IA64_BSP:
2229 /* Account for the fact that ptrace() expects bsp to point
2230 after the current register frame. */
2231 cfm = read_register (IA64_CFM_REGNUM);
2232 sof = (cfm & 0x7f);
2233 bsp = ia64_rse_skip_regs (*val, sof);
2234 write_register (IA64_BSP_REGNUM, bsp);
2235 break;
2236
2237 case UNW_IA64_CFM:
2238 /* If we change CFM, we need to adjust ptrace's notion of
2239 bsp accordingly, so that the real bsp remains
2240 unchanged. */
2241 bsp = read_register (IA64_BSP_REGNUM);
2242 cfm = read_register (IA64_CFM_REGNUM);
2243 old_sof = (cfm & 0x7f);
2244 new_sof = (*val & 0x7f);
2245 if (old_sof != new_sof)
2246 {
2247 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2248 write_register (IA64_BSP_REGNUM, bsp);
2249 }
2250 write_register (IA64_CFM_REGNUM, *val);
2251 break;
2252
2253 default:
2254 write_register (regnum, *val);
2255 break;
2256 }
2257 if (gdbarch_debug >= 1)
2258 fprintf_unfiltered (gdb_stdlog,
78ced177 2259 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2260 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2261 ? ia64_register_names[regnum] : "r??"),
2262 paddr_nz (*val));
968d1cb4
JJ		 2263 }
2264 else
2265 {
2266 switch (uw_regnum)
2267 {
2268 case UNW_REG_IP:
2269 /* Libunwind expects to see the pc value which means the slot number
2270 from the psr must be merged with the ip word address. */
2271 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2272 ip = extract_unsigned_integer (buf, 8);
2273 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2274 psr = extract_unsigned_integer (buf, 8);
2275 *val = ip | ((psr >> 41) & 0x3);
2276 break;
2277
2278 case UNW_IA64_AR_BSP:
2279 /* Libunwind expects to see the beginning of the current register
2280 frame so we must account for the fact that ptrace() will return a value
2281 for bsp that points *after* the current register frame. */
2282 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2283 bsp = extract_unsigned_integer (buf, 8);
2284 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2285 cfm = extract_unsigned_integer (buf, 8);
2286 sof = (cfm & 0x7f);
2287 *val = ia64_rse_skip_regs (bsp, -sof);
2288 break;
2289
2290 case UNW_IA64_AR_BSPSTORE:
2291 /* Libunwind wants bspstore to be after the current register frame.
2292 This is what ptrace() and gdb treats as the regular bsp value. */
2293 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2294 *val = extract_unsigned_integer (buf, 8);
2295 break;
2296
2297 default:
2298 /* For all other registers, just unwind the value directly. */
2299 frame_unwind_register (next_frame, regnum, buf);
2300 *val = extract_unsigned_integer (buf, 8);
2301 break;
2302 }
2303
2304 if (gdbarch_debug >= 1)
2305 fprintf_unfiltered (gdb_stdlog,
78ced177 2306 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2307 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2308 ? ia64_register_names[regnum] : "r??"),
2309 paddr_nz (*val));
968d1cb4
JJ		 2310 }
2311 return 0;
2312}
2313
2314/* Libunwind callback accessor function for floating-point registers. */
2315static int
2316ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2317 int write, void *arg)
2318{
2319 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2320
2321 if (write)
2322 regcache_cooked_write (current_regcache, regnum, (char *) val);
2323 else
2324 regcache_cooked_read (current_regcache, regnum, (char *) val);
2325 return 0;
2326}
2327
c5a27d9c
JJ		 2328/* Libunwind callback accessor function for top-level rse registers. */
2329static int
2330ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2331 int write, void *arg)
2332{
2333 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2334 unw_word_t bsp, sof, sol, cfm, psr, ip;
2335 long new_sof, old_sof;
2336
2337 if (write)
2338 {
2339 if (regnum < 0)
2340 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2341 return 0;
2342
2343 switch (uw_regnum)
2344 {
2345 case UNW_REG_IP:
2346 ia64_write_pc (*val, inferior_ptid);
2347 break;
2348
2349 case UNW_IA64_AR_BSPSTORE:
2350 write_register (IA64_BSP_REGNUM, *val);
2351 break;
2352
2353 case UNW_IA64_AR_BSP:
2354 case UNW_IA64_BSP:
2355 /* Account for the fact that ptrace() expects bsp to point
2356 after the current register frame. */
2357 cfm = read_register (IA64_CFM_REGNUM);
2358 sof = (cfm & 0x7f);
2359 bsp = ia64_rse_skip_regs (*val, sof);
2360 write_register (IA64_BSP_REGNUM, bsp);
2361 break;
2362
2363 case UNW_IA64_CFM:
2364 /* If we change CFM, we need to adjust ptrace's notion of
2365 bsp accordingly, so that the real bsp remains
2366 unchanged. */
2367 bsp = read_register (IA64_BSP_REGNUM);
2368 cfm = read_register (IA64_CFM_REGNUM);
2369 old_sof = (cfm & 0x7f);
2370 new_sof = (*val & 0x7f);
2371 if (old_sof != new_sof)
2372 {
2373 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2374 write_register (IA64_BSP_REGNUM, bsp);
2375 }
2376 write_register (IA64_CFM_REGNUM, *val);
2377 break;
2378
2379 default:
2380 write_register (regnum, *val);
2381 break;
2382 }
2383 if (gdbarch_debug >= 1)
2384 fprintf_unfiltered (gdb_stdlog,
2385 " access_rse_reg: to cache: %4s=0x%s\n",
2386 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2387 ? ia64_register_names[regnum] : "r??"),
2388 paddr_nz (*val));
2389 }
2390 else
2391 {
2392 switch (uw_regnum)
2393 {
2394 case UNW_REG_IP:
2395 /* Libunwind expects to see the pc value which means the slot number
2396 from the psr must be merged with the ip word address. */
2397 ip = read_register (IA64_IP_REGNUM);
2398 psr = read_register (IA64_PSR_REGNUM);
2399 *val = ip | ((psr >> 41) & 0x3);
2400 break;
2401
2402 case UNW_IA64_AR_BSP:
2403 /* Libunwind expects to see the beginning of the current register
2404 frame so we must account for the fact that ptrace() will return a value
2405 for bsp that points *after* the current register frame. */
2406 bsp = read_register (IA64_BSP_REGNUM);
2407 cfm = read_register (IA64_CFM_REGNUM);
2408 sof = (cfm & 0x7f);
2409 *val = ia64_rse_skip_regs (bsp, -sof);
2410 break;
2411
2412 case UNW_IA64_AR_BSPSTORE:
2413 /* Libunwind wants bspstore to be after the current register frame.
2414 This is what ptrace() and gdb treats as the regular bsp value. */
2415 *val = read_register (IA64_BSP_REGNUM);
2416 break;
2417
2418 default:
2419 /* For all other registers, just read the value directly. */
2420 *val = read_register (regnum);
2421 break;
2422 }
2423 }
2424
2425 if (gdbarch_debug >= 1)
2426 fprintf_unfiltered (gdb_stdlog,
2427 " access_rse_reg: from cache: %4s=0x%s\n",
2428 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2429 ? ia64_register_names[regnum] : "r??"),
2430 paddr_nz (*val));
2431
2432 return 0;
2433}
2434
968d1cb4
JJ		 2435/* Libunwind callback accessor function for accessing memory. */
2436static int
2437ia64_access_mem (unw_addr_space_t as,
2438 unw_word_t addr, unw_word_t *val,
2439 int write, void *arg)
2440{
c5a27d9c
JJ		 2441 if (addr - KERNEL_START < ktab_size)
2442 {
2443 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2444 + (addr - KERNEL_START));
2445
2446 if (write)
2447 *laddr = *val;
2448 else
2449 *val = *laddr;
2450 return 0;
2451 }
2452
968d1cb4
JJ		 2453 /* XXX do we need to normalize byte-order here? */
2454 if (write)
2455 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2456 else
2457 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2458}
2459
2460/* Call low-level function to access the kernel unwind table. */
13547ab6
DJ		 2461static LONGEST
2462getunwind_table (gdb_byte **buf_p)
968d1cb4
JJ		 2463{
2464 LONGEST x;
c5a27d9c 2465
10d6c8cd
DJ		 2466 /* FIXME drow/2005-09-10: This code used to call
2467 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2468 for the currently running ia64-linux kernel. That data should
2469 come from the core file and be accessed via the auxv vector; if
2470 we want to preserve fall back to the running kernel's table, then
2471 we should find a way to override the corefile layer's
2472 xfer_partial method. */
968d1cb4 2473
13547ab6
DJ		 2474 x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2475 NULL, buf_p);
2476
2477 return x;
968d1cb4 2478}
10d6c8cd 2479
968d1cb4
JJ		 2480/* Get the kernel unwind table. */
2481static int
2482get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2483{
c5a27d9c 2484 static struct ia64_table_entry *etab;
968d1cb4 2485
c5a27d9c 2486 if (!ktab)
968d1cb4 2487 {
13547ab6 2488 gdb_byte *ktab_buf;
c5a27d9c 2489 size_t size;
13547ab6
DJ		 2490
2491 ktab_size = getunwind_table (&ktab_buf);
2492 if (ktab_size <= 0)
2493 return -UNW_ENOINFO;
2494 else
2495 ktab = (struct ia64_table_entry *) ktab_buf;
2496
968d1cb4 2497 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2498 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2499 }
2500
2501 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2502 return -UNW_ENOINFO;
2503
2504 di->format = UNW_INFO_FORMAT_TABLE;
2505 di->gp = 0;
2506 di->start_ip = ktab[0].start_offset;
2507 di->end_ip = etab[-1].end_offset;
2508 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2509 di->u.ti.segbase = 0;
2510 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2511 di->u.ti.table_data = (unw_word_t *) ktab;
2512
2513 if (gdbarch_debug >= 1)
2514 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2515 "segbase=0x%s, length=%s, gp=0x%s\n",
2516 (char *) di->u.ti.name_ptr,
2517 paddr_nz (di->u.ti.segbase),
2518 paddr_u (di->u.ti.table_len),
2519 paddr_nz (di->gp));
968d1cb4
JJ		 2520 return 0;
2521}
2522
2523/* Find the unwind table entry for a specified address. */
2524static int
2525ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2526 unw_dyn_info_t *dip, void **buf)
2527{
2528 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2529 Elf_Internal_Ehdr *ehdr;
2530 unw_word_t segbase = 0;
2531 CORE_ADDR load_base;
2532 bfd *bfd;
2533 int i;
2534
2535 bfd = objfile->obfd;
2536
2537 ehdr = elf_tdata (bfd)->elf_header;
2538 phdr = elf_tdata (bfd)->phdr;
2539
2540 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2541
2542 for (i = 0; i < ehdr->e_phnum; ++i)
2543 {
2544 switch (phdr[i].p_type)
2545 {
2546 case PT_LOAD:
2547 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2548 < phdr[i].p_memsz)
2549 p_text = phdr + i;
2550 break;
2551
2552 case PT_IA_64_UNWIND:
2553 p_unwind = phdr + i;
2554 break;
2555
2556 default:
2557 break;
2558 }
2559 }
2560
c5a27d9c 2561 if (!p_text || !p_unwind)
968d1cb4
JJ		 2562 return -UNW_ENOINFO;
2563
c5a27d9c
JJ		 2564 /* Verify that the segment that contains the IP also contains
2565 the static unwind table. If not, we may be in the Linux kernel's
2566 DSO gate page in which case the unwind table is another segment.
2567 Otherwise, we are dealing with runtime-generated code, for which we
2568 have no info here. */
968d1cb4
JJ		 2569 segbase = p_text->p_vaddr + load_base;
2570
c5a27d9c
JJ		 2571 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2572 {
2573 int ok = 0;
2574 for (i = 0; i < ehdr->e_phnum; ++i)
2575 {
2576 if (phdr[i].p_type == PT_LOAD
2577 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2578 {
2579 ok = 1;
2580 /* Get the segbase from the section containing the
2581 libunwind table. */
2582 segbase = phdr[i].p_vaddr + load_base;
2583 }
2584 }
2585 if (!ok)
2586 return -UNW_ENOINFO;
2587 }
2588
2589 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2590 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2591 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2592 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2593 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2594 dip->u.rti.segbase = segbase;
2595 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2596 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2597
2598 return 0;
2599}
2600
2601/* Libunwind callback accessor function to acquire procedure unwind-info. */
2602static int
2603ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2604 int need_unwind_info, void *arg)
2605{
2606 struct obj_section *sec = find_pc_section (ip);
2607 unw_dyn_info_t di;
2608 int ret;
2609 void *buf = NULL;
2610
2611 if (!sec)
2612 {
2613 /* XXX This only works if the host and the target architecture are
2614 both ia64 and if the have (more or less) the same kernel
2615 version. */
2616 if (get_kernel_table (ip, &di) < 0)
2617 return -UNW_ENOINFO;
503ff15d
KB		 2618
2619 if (gdbarch_debug >= 1)
78ced177
JJ		 2620 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2621 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2622 "length=%s,data=0x%s)\n",
2623 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2624 paddr_nz (di.u.ti.segbase),
2625 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2626 paddr_nz (di.gp),
2627 paddr_u (di.u.ti.table_len),
2628 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2629 }
2630 else
2631 {
2632 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2633 if (ret < 0)
2634 return ret;
968d1cb4 2635
503ff15d 2636 if (gdbarch_debug >= 1)
78ced177
JJ		 2637 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2638 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2639 "length=%s,data=0x%s)\n",
2640 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2641 paddr_nz (di.u.rti.segbase),
2642 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2643 paddr_nz (di.gp),
2644 paddr_u (di.u.rti.table_len),
2645 paddr_nz (di.u.rti.table_data));
503ff15d 2646 }
968d1cb4 2647
503ff15d
KB		 2648 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2649 arg);
968d1cb4
JJ		 2650
2651 /* We no longer need the dyn info storage so free it. */
2652 xfree (buf);
2653
2654 return ret;
2655}
2656
2657/* Libunwind callback accessor function for cleanup. */
2658static void
2659ia64_put_unwind_info (unw_addr_space_t as,
2660 unw_proc_info_t *pip, void *arg)
2661{
2662 /* Nothing required for now. */
2663}
2664
2665/* Libunwind callback accessor function to get head of the dynamic
2666 unwind-info registration list. */
2667static int
2668ia64_get_dyn_info_list (unw_addr_space_t as,
2669 unw_word_t *dilap, void *arg)
2670{
2671 struct obj_section *text_sec;
2672 struct objfile *objfile;
2673 unw_word_t ip, addr;
2674 unw_dyn_info_t di;
2675 int ret;
2676
2677 if (!libunwind_is_initialized ())
2678 return -UNW_ENOINFO;
2679
2680 for (objfile = object_files; objfile; objfile = objfile->next)
2681 {
2682 void *buf = NULL;
2683
2684 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2685 ip = text_sec->addr;
2686 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2687 if (ret >= 0)
2688 {
503ff15d 2689 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2690 /* We no longer need the dyn info storage so free it. */
2691 xfree (buf);
2692
2693 if (addr)
2694 {
2695 if (gdbarch_debug >= 1)
2696 fprintf_unfiltered (gdb_stdlog,
2697 "dynamic unwind table in objfile %s "
78ced177 2698 "at 0x%s (gp=0x%s)\n",
968d1cb4 2699 bfd_get_filename (objfile->obfd),
78ced177 2700 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2701 *dilap = addr;
2702 return 0;
2703 }
2704 }
2705 }
2706 return -UNW_ENOINFO;
2707}
2708
2709
2710/* Frame interface functions for libunwind. */
2711
2712static void
2713ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2714 struct frame_id *this_id)
968d1cb4
JJ		 2715{
2716 char buf[8];
2717 CORE_ADDR bsp;
2718 struct frame_id id;
c5a27d9c
JJ		 2719 CORE_ADDR prev_ip, addr;
2720 int realnum, optimized;
2721 enum lval_type lval;
2722
968d1cb4
JJ		 2723
2724 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2725 if (frame_id_eq (id, null_frame_id))
2726 {
2727 (*this_id) = null_frame_id;
2728 return;
2729 }
968d1cb4 2730
c5a27d9c
JJ		 2731 /* We must add the bsp as the special address for frame comparison
2732 purposes. */
968d1cb4
JJ		 2733 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2734 bsp = extract_unsigned_integer (buf, 8);
2735
c5a27d9c
JJ		 2736 /* If the previous frame pc value is 0, then we are at the end of the stack
2737 and don't want to unwind past this frame. We return a null frame_id to
2738 indicate this. */
2739 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2740 &optimized, &lval, &addr, &realnum, buf);
2741 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2742
2743 if (prev_ip != 0)
2744 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2745 else
2746 (*this_id) = null_frame_id;
968d1cb4
JJ		 2747
2748 if (gdbarch_debug >= 1)
2749 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2750 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2751 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2752 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2753}
2754
2755static void
2756ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2757 void **this_cache,
2758 int regnum, int *optimizedp,
2759 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2760 int *realnump, gdb_byte *valuep)
968d1cb4
JJ		 2761{
2762 int reg = regnum;
2763
2764 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2765 reg = IA64_PR_REGNUM;
2766 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2767 reg = IA64_UNAT_REGNUM;
2768
2769 /* Let libunwind do most of the work. */
2770 libunwind_frame_prev_register (next_frame, this_cache, reg,
2771 optimizedp, lvalp, addrp, realnump, valuep);
2772
6672f2ae
AS		 2773 /* No more to do if the value is not supposed to be supplied. */
2774 if (!valuep)
2775 return;
2776
968d1cb4
JJ		 2777 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2778 {
2779 ULONGEST prN_val;
2780
2781 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2782 {
2783 int rrb_pr = 0;
2784 ULONGEST cfm;
2785 unsigned char buf[MAX_REGISTER_SIZE];
2786
2787 /* Fetch predicate register rename base from current frame
2788 marker for this frame. */
2789 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2790 cfm = extract_unsigned_integer (buf, 8);
2791 rrb_pr = (cfm >> 32) & 0x3f;
2792
2793 /* Adjust the register number to account for register rotation. */
2794 regnum = VP16_REGNUM
2795 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2796 }
2797 prN_val = extract_bit_field ((unsigned char *) valuep,
2798 regnum - VP0_REGNUM, 1);
2799 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2800 }
2801 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2802 {
2803 ULONGEST unatN_val;
2804
2805 unatN_val = extract_bit_field ((unsigned char *) valuep,
2806 regnum - IA64_NAT0_REGNUM, 1);
2807 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2808 unatN_val);
2809 }
2810 else if (regnum == IA64_BSP_REGNUM)
2811 {
2812 char cfm_valuep[MAX_REGISTER_SIZE];
2813 int cfm_optim;
2814 int cfm_realnum;
2815 enum lval_type cfm_lval;
2816 CORE_ADDR cfm_addr;
2817 CORE_ADDR bsp, prev_cfm, prev_bsp;
2818
2819 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2820 This corresponds to what the hardware bsp register will be if we pop the frame
2821 back which is why we might have been called. We know that libunwind will pass us back
2822 the beginning of the current frame so we should just add sof to it. */
2823 prev_bsp = extract_unsigned_integer (valuep, 8);
2824 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2825 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2826 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2827 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2828
2829 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2830 prev_bsp);
2831 }
2832
2833 if (gdbarch_debug >= 1)
2834 fprintf_unfiltered (gdb_stdlog,
78ced177 2835 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2836 (regnum < IA64_GR32_REGNUM
2837 || (regnum > IA64_GR127_REGNUM
2838 && regnum < LAST_PSEUDO_REGNUM))
2839 ? ia64_register_names[regnum]
2840 : (regnum < LAST_PSEUDO_REGNUM
2841 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2842 : "OUT_OF_RANGE"),
78ced177 2843 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2844}
2845
2846static const struct frame_unwind ia64_libunwind_frame_unwind =
2847{
2848 NORMAL_FRAME,
2849 ia64_libunwind_frame_this_id,
2850 ia64_libunwind_frame_prev_register
2851};
2852
2853static const struct frame_unwind *
2854ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2855{
2856 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2857 return &ia64_libunwind_frame_unwind;
2858
2859 return NULL;
2860}
2861
c5a27d9c
JJ		 2862static void
2863ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2864 struct frame_id *this_id)
2865{
2866 char buf[8];
2867 CORE_ADDR bsp;
2868 struct frame_id id;
2869 CORE_ADDR prev_ip;
2870
2871 libunwind_frame_this_id (next_frame, this_cache, &id);
2872 if (frame_id_eq (id, null_frame_id))
2873 {
2874 (*this_id) = null_frame_id;
2875 return;
2876 }
2877
2878 /* We must add the bsp as the special address for frame comparison
2879 purposes. */
2880 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2881 bsp = extract_unsigned_integer (buf, 8);
2882
2883 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2884 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2885
2886 if (gdbarch_debug >= 1)
2887 fprintf_unfiltered (gdb_stdlog,
2888 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2889 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2890 paddr_nz (bsp), next_frame);
2891}
2892
2893static void
2894ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2895 void **this_cache,
2896 int regnum, int *optimizedp,
2897 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2898 int *realnump, gdb_byte *valuep)
c5a27d9c
JJ		 2899
2900{
f1b4b38e 2901 gdb_byte buf[8];
c5a27d9c
JJ		 2902 CORE_ADDR prev_ip, addr;
2903 int realnum, optimized;
2904 enum lval_type lval;
2905
2906
2907 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2908 method of getting previous registers. */
2909 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2910 &optimized, &lval, &addr, &realnum, buf);
2911 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2912
2913 if (prev_ip == 0)
2914 {
2915 void *tmp_cache = NULL;
2916 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2917 addrp, realnump, valuep);
2918 }
2919 else
2920 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2921 addrp, realnump, valuep);
2922}
2923
2924static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2925{
2926 SIGTRAMP_FRAME,
2927 ia64_libunwind_sigtramp_frame_this_id,
2928 ia64_libunwind_sigtramp_frame_prev_register
2929};
2930
2931static const struct frame_unwind *
2932ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2933{
2934 if (libunwind_is_initialized ())
2935 {
2936 if (libunwind_sigtramp_frame_sniffer (next_frame))
2937 return &ia64_libunwind_sigtramp_frame_unwind;
2938 return NULL;
2939 }
2940 else
2941 return ia64_sigtramp_frame_sniffer (next_frame);
2942}
2943
968d1cb4
JJ		 2944/* Set of libunwind callback acccessor functions. */
2945static unw_accessors_t ia64_unw_accessors =
2946{
2947 ia64_find_proc_info_x,
2948 ia64_put_unwind_info,
2949 ia64_get_dyn_info_list,
2950 ia64_access_mem,
2951 ia64_access_reg,
2952 ia64_access_fpreg,
2953 /* resume */
2954 /* get_proc_name */
2955};
2956
c5a27d9c
JJ		 2957/* Set of special libunwind callback acccessor functions specific for accessing
2958 the rse registers. At the top of the stack, we want libunwind to figure out
2959 how to read r32 - r127. Though usually they are found sequentially in memory
2960 starting from $bof, this is not always true. */
2961static unw_accessors_t ia64_unw_rse_accessors =
2962{
2963 ia64_find_proc_info_x,
2964 ia64_put_unwind_info,
2965 ia64_get_dyn_info_list,
2966 ia64_access_mem,
2967 ia64_access_rse_reg,
2968 ia64_access_fpreg,
2969 /* resume */
2970 /* get_proc_name */
2971};
2972
968d1cb4
JJ		 2973/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2974static struct libunwind_descr ia64_libunwind_descr =
2975{
2976 ia64_gdb2uw_regnum,
2977 ia64_uw2gdb_regnum,
2978 ia64_is_fpreg,
2979 &ia64_unw_accessors,
c5a27d9c 2980 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2981};
2982
2983#endif /* HAVE_LIBUNWIND_IA64_H */
2984
74055713
AC		 2985/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2986 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2987 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2988int
2989ia64_use_struct_convention (int gcc_p, struct type *type)
2990{
64a5b29c
KB		 2991 struct type *float_elt_type;
2992
2993 /* HFAs are structures (or arrays) consisting entirely of floating
2994 point values of the same length. Up to 8 of these are returned
2995 in registers. Don't use the struct convention when this is the
004d836a 2996 case. */
64a5b29c
KB		 2997 float_elt_type = is_float_or_hfa_type (type);
2998 if (float_elt_type != NULL
2999 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
3000 return 0;
3001
3002 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 3003 Don't use the struct convention for those either. */
16461d7d
KB		 3004 return TYPE_LENGTH (type) > 32;
3005}
3006
3007void
2d522557
AC		 3008ia64_extract_return_value (struct type *type, struct regcache *regcache,
3009 gdb_byte *valbuf)
16461d7d 3010{
64a5b29c
KB		 3011 struct type *float_elt_type;
3012
3013 float_elt_type = is_float_or_hfa_type (type);
3014 if (float_elt_type != NULL)
3015 {
004d836a 3016 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 3017 int offset = 0;
3018 int regnum = IA64_FR8_REGNUM;
3019 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3020
3021 while (n-- > 0)
3022 {
004d836a
JJ		 3023 regcache_cooked_read (regcache, regnum, from);
3024 convert_typed_floating (from, builtin_type_ia64_ext,
3025 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 3026 offset += TYPE_LENGTH (float_elt_type);
3027 regnum++;
3028 }
3029 }
16461d7d 3030 else
004d836a
JJ		 3031 {
3032 ULONGEST val;
3033 int offset = 0;
3034 int regnum = IA64_GR8_REGNUM;
3035 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
3036 int n = TYPE_LENGTH (type) / reglen;
3037 int m = TYPE_LENGTH (type) % reglen;
16461d7d 3038
004d836a
JJ		 3039 while (n-- > 0)
3040 {
3041 ULONGEST val;
3042 regcache_cooked_read_unsigned (regcache, regnum, &val);
3043 memcpy ((char *)valbuf + offset, &val, reglen);
3044 offset += reglen;
3045 regnum++;
3046 }
16461d7d 3047
004d836a
JJ		 3048 if (m)
3049 {
3050 regcache_cooked_read_unsigned (regcache, regnum, &val);
3051 memcpy ((char *)valbuf + offset, &val, m);
3052 }
3053 }
16461d7d
KB		 3054}
3055
3056CORE_ADDR
004d836a 3057ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 3058{
8a3fe4f8 3059 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 3060 return 0;
16461d7d
KB		 3061}
3062
16461d7d 3063
64a5b29c
KB		 3064static int
3065is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3066{
3067 switch (TYPE_CODE (t))
3068 {
3069 case TYPE_CODE_FLT:
3070 if (*etp)
3071 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3072 else
3073 {
3074 *etp = t;
3075 return 1;
3076 }
3077 break;
3078 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3079 return
3080 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3081 etp);
64a5b29c
KB		 3082 break;
3083 case TYPE_CODE_STRUCT:
3084 {
3085 int i;
3086
3087 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3088 if (!is_float_or_hfa_type_recurse
3089 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3090 return 0;
3091 return 1;
3092 }
3093 break;
3094 default:
3095 return 0;
3096 break;
3097 }
3098}
3099
3100/* Determine if the given type is one of the floating point types or
3101 and HFA (which is a struct, array, or combination thereof whose
004d836a 3102 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3103
3104static struct type *
3105is_float_or_hfa_type (struct type *t)
3106{
3107 struct type *et = 0;
3108
3109 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3110}
3111
3112
98f96ba1
KB		 3113/* Return 1 if the alignment of T is such that the next even slot
3114 should be used. Return 0, if the next available slot should
3115 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3116 and Runtime manual). */
98f96ba1
KB		 3117
3118static int
3119slot_alignment_is_next_even (struct type *t)
3120{
3121 switch (TYPE_CODE (t))
3122 {
3123 case TYPE_CODE_INT:
3124 case TYPE_CODE_FLT:
3125 if (TYPE_LENGTH (t) > 8)
3126 return 1;
3127 else
3128 return 0;
3129 case TYPE_CODE_ARRAY:
3130 return
3131 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3132 case TYPE_CODE_STRUCT:
3133 {
3134 int i;
3135
3136 for (i = 0; i < TYPE_NFIELDS (t); i++)
3137 if (slot_alignment_is_next_even
3138 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3139 return 1;
3140 return 0;
3141 }
3142 default:
3143 return 0;
3144 }
3145}
3146
64a5b29c
KB		 3147/* Attempt to find (and return) the global pointer for the given
3148 function.
3149
3150 This is a rather nasty bit of code searchs for the .dynamic section
3151 in the objfile corresponding to the pc of the function we're trying
3152 to call. Once it finds the addresses at which the .dynamic section
3153 lives in the child process, it scans the Elf64_Dyn entries for a
3154 DT_PLTGOT tag. If it finds one of these, the corresponding
3155 d_un.d_ptr value is the global pointer. */
3156
3157static CORE_ADDR
b33e8514 3158ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3159{
76d689a6 3160 struct obj_section *faddr_sect;
64a5b29c 3161
76d689a6
KB		 3162 faddr_sect = find_pc_section (faddr);
3163 if (faddr_sect != NULL)
64a5b29c
KB		 3164 {
3165 struct obj_section *osect;
3166
76d689a6 3167 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3168 {
3169 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3170 break;
3171 }
3172
76d689a6 3173 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3174 {
3175 CORE_ADDR addr;
3176
3177 addr = osect->addr;
3178 while (addr < osect->endaddr)
3179 {
3180 int status;
3181 LONGEST tag;
3182 char buf[8];
3183
3184 status = target_read_memory (addr, buf, sizeof (buf));
3185 if (status != 0)
3186 break;
3187 tag = extract_signed_integer (buf, sizeof (buf));
3188
3189 if (tag == DT_PLTGOT)
3190 {
3191 CORE_ADDR global_pointer;
3192
3193 status = target_read_memory (addr + 8, buf, sizeof (buf));
3194 if (status != 0)
3195 break;
7c0b4a20 3196 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3197
3198 /* The payoff... */
3199 return global_pointer;
3200 }
3201
3202 if (tag == DT_NULL)
3203 break;
3204
3205 addr += 16;
3206 }
3207 }
3208 }
3209 return 0;
3210}
3211
3212/* Given a function's address, attempt to find (and return) the
3213 corresponding (canonical) function descriptor. Return 0 if
004d836a 3214 not found. */
64a5b29c
KB		 3215static CORE_ADDR
3216find_extant_func_descr (CORE_ADDR faddr)
3217{
76d689a6 3218 struct obj_section *faddr_sect;
64a5b29c 3219
004d836a 3220 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3221 faddr_sect = find_pc_section (faddr);
3222 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3223 return faddr;
3224
76d689a6 3225 if (faddr_sect != NULL)
64a5b29c 3226 {
76d689a6
KB		 3227 struct obj_section *osect;
3228 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3229 {
3230 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3231 break;
3232 }
3233
76d689a6 3234 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3235 {
3236 CORE_ADDR addr;
3237
3238 addr = osect->addr;
3239 while (addr < osect->endaddr)
3240 {
3241 int status;
3242 LONGEST faddr2;
3243 char buf[8];
3244
3245 status = target_read_memory (addr, buf, sizeof (buf));
3246 if (status != 0)
3247 break;
3248 faddr2 = extract_signed_integer (buf, sizeof (buf));
3249
3250 if (faddr == faddr2)
3251 return addr;
3252
3253 addr += 16;
3254 }
3255 }
3256 }
3257 return 0;
3258}
3259
3260/* Attempt to find a function descriptor corresponding to the
3261 given address. If none is found, construct one on the
004d836a 3262 stack using the address at fdaptr. */
64a5b29c
KB		 3263
3264static CORE_ADDR
3265find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
3266{
3267 CORE_ADDR fdesc;
3268
3269 fdesc = find_extant_func_descr (faddr);
3270
3271 if (fdesc == 0)
3272 {
3273 CORE_ADDR global_pointer;
3274 char buf[16];
3275
3276 fdesc = *fdaptr;
3277 *fdaptr += 16;
3278
b33e8514 3279 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3280
3281 if (global_pointer == 0)
3282 global_pointer = read_register (IA64_GR1_REGNUM);
3283
fbd9dcd3
AC		 3284 store_unsigned_integer (buf, 8, faddr);
3285 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3286
3287 write_memory (fdesc, buf, 16);
3288 }
3289
3290 return fdesc;
3291}
16461d7d 3292
af8b88dd
JJ		 3293/* Use the following routine when printing out function pointers
3294 so the user can see the function address rather than just the
3295 function descriptor. */
3296static CORE_ADDR
e2d0e7eb
AC		 3297ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3298 struct target_ops *targ)
af8b88dd
JJ		 3299{
3300 struct obj_section *s;
3301
3302 s = find_pc_section (addr);
3303
3304 /* check if ADDR points to a function descriptor. */
3305 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3306 return read_memory_unsigned_integer (addr, 8);
3307
3308 return addr;
3309}
3310
a78f21af 3311static CORE_ADDR
004d836a
JJ		 3312ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3313{
3314 return sp & ~0xfLL;
3315}
3316
3317static CORE_ADDR
7d9b040b 3318ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3319 struct regcache *regcache, CORE_ADDR bp_addr,
3320 int nargs, struct value **args, CORE_ADDR sp,
3321 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3322{
3323 int argno;
ea7c478f 3324 struct value *arg;
16461d7d
KB		 3325 struct type *type;
3326 int len, argoffset;
64a5b29c 3327 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3328 int floatreg;
004d836a 3329 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3330 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3331
3332 nslots = 0;
64a5b29c 3333 nfuncargs = 0;
004d836a 3334 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3335 for (argno = 0; argno < nargs; argno++)
3336 {
3337 arg = args[argno];
4991999e 3338 type = check_typedef (value_type (arg));
16461d7d
KB		 3339 len = TYPE_LENGTH (type);
3340
98f96ba1 3341 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3342 nslots++;
3343
64a5b29c
KB		 3344 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3345 nfuncargs++;
3346
16461d7d
KB		 3347 nslots += (len + 7) / 8;
3348 }
3349
004d836a 3350 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3351 rseslots = (nslots > 8) ? 8 : nslots;
3352 memslots = nslots - rseslots;
3353
004d836a
JJ		 3354 /* Allocate a new RSE frame. */
3355 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3356
004d836a 3357 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3358 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3359 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3360
004d836a 3361 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3362 pfs &= 0xc000000000000000LL;
3363 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3364 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3365
3366 cfm &= 0xc000000000000000LL;
3367 cfm |= rseslots;
004d836a 3368 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3369
64a5b29c
KB		 3370 /* We will attempt to find function descriptors in the .opd segment,
3371 but if we can't we'll construct them ourselves. That being the
004d836a 3372 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3373 funcdescaddr = sp - nfuncargs * 16;
3374 funcdescaddr &= ~0xfLL;
3375
3376 /* Adjust the stack pointer to it's new value. The calling conventions
3377 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3378 necessary for the memory slots and our function descriptors. */
64a5b29c 3379 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3380 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3381
64a5b29c
KB		 3382 /* Place the arguments where they belong. The arguments will be
3383 either placed in the RSE backing store or on the memory stack.
3384 In addition, floating point arguments or HFAs are placed in
004d836a 3385 floating point registers. */
16461d7d
KB		 3386 slotnum = 0;
3387 floatreg = IA64_FR8_REGNUM;
3388 for (argno = 0; argno < nargs; argno++)
3389 {
64a5b29c
KB		 3390 struct type *float_elt_type;
3391
16461d7d 3392 arg = args[argno];
4991999e 3393 type = check_typedef (value_type (arg));
16461d7d 3394 len = TYPE_LENGTH (type);
64a5b29c 3395
004d836a 3396 /* Special handling for function parameters. */
64a5b29c
KB		 3397 if (len == 8
3398 && TYPE_CODE (type) == TYPE_CODE_PTR
3399 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3400 {
3401 char val_buf[8];
3402
fbd9dcd3 3403 store_unsigned_integer (val_buf, 8,
0fd88904 3404 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3405 &funcdescaddr));
64a5b29c
KB		 3406 if (slotnum < rseslots)
3407 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3408 else
3409 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3410 slotnum++;
3411 continue;
3412 }
3413
004d836a 3414 /* Normal slots. */
98f96ba1
KB		 3415
3416 /* Skip odd slot if necessary... */
3417 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3418 slotnum++;
98f96ba1 3419
16461d7d
KB		 3420 argoffset = 0;
3421 while (len > 0)
3422 {
3423 char val_buf[8];
3424
3425 memset (val_buf, 0, 8);
0fd88904 3426 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3427
3428 if (slotnum < rseslots)
3429 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3430 else
3431 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3432
3433 argoffset += 8;
3434 len -= 8;
3435 slotnum++;
3436 }
64a5b29c 3437
004d836a 3438 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3439 float_elt_type = is_float_or_hfa_type (type);
3440 if (float_elt_type != NULL)
3441 {
3442 argoffset = 0;
3443 len = TYPE_LENGTH (type);
3444 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3445 {
004d836a 3446 char to[MAX_REGISTER_SIZE];
0fd88904 3447 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3448 to, builtin_type_ia64_ext);
3449 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3450 floatreg++;
3451 argoffset += TYPE_LENGTH (float_elt_type);
3452 len -= TYPE_LENGTH (float_elt_type);
3453 }
16461d7d
KB		 3454 }
3455 }
3456
004d836a 3457 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3458 if (struct_return)
3459 {
004d836a 3460 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3461 }
3462
b33e8514 3463 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3464
004d836a
JJ		 3465 if (global_pointer != 0)
3466 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3467
004d836a 3468 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3469
004d836a 3470 write_register (sp_regnum, sp);
16461d7d
KB		 3471
3472 return sp;
3473}
3474
004d836a
JJ		 3475static struct frame_id
3476ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3477{
004d836a 3478 char buf[8];
4afcc598 3479 CORE_ADDR sp, bsp;
004d836a
JJ		 3480
3481 frame_unwind_register (next_frame, sp_regnum, buf);
3482 sp = extract_unsigned_integer (buf, 8);
3483
4afcc598
JJ		 3484 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3485 bsp = extract_unsigned_integer (buf, 8);
3486
3487 if (gdbarch_debug >= 1)
3488 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3489 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3490 paddr_nz (frame_pc_unwind (next_frame)),
3491 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3492
3493 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3494}
3495
004d836a
JJ		 3496static CORE_ADDR
3497ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3498{
004d836a
JJ		 3499 char buf[8];
3500 CORE_ADDR ip, psr, pc;
3501
3502 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3503 ip = extract_unsigned_integer (buf, 8);
3504 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3505 psr = extract_unsigned_integer (buf, 8);
3506
3507 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3508 return pc;
16461d7d
KB		 3509}
3510
3511static void
88d82102
JJ		 3512ia64_store_return_value (struct type *type, struct regcache *regcache,
3513 const gdb_byte *valbuf)
16461d7d 3514{
004d836a 3515 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3516 {
004d836a
JJ		 3517 char to[MAX_REGISTER_SIZE];
3518 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3519 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3520 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3521 }
3522 else
004d836a 3523 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3524}
3525
3526static void
1750fa04
AC		 3527ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3528 struct regcache *regcache,
3529 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3530 CORE_ADDR *targ_addr, int *targ_len)
3531{
3532 *targ_addr = memaddr;
3533 *targ_len = nr_bytes;
3534}
3535
6926787d
AS		 3536static int
3537ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3538{
3539 info->bytes_per_line = SLOT_MULTIPLIER;
3540 return print_insn_ia64 (memaddr, info);
3541}
3542
16461d7d
KB		 3543static struct gdbarch *
3544ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3545{
3546 struct gdbarch *gdbarch;
244bc108 3547 struct gdbarch_tdep *tdep;
244bc108 3548
85bf2b91
JJ		 3549 /* If there is already a candidate, use it. */
3550 arches = gdbarch_list_lookup_by_info (arches, &info);
3551 if (arches != NULL)
3552 return arches->gdbarch;
16461d7d 3553
244bc108
KB		 3554 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3555 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3556
b33e8514 3557 tdep->sigcontext_register_address = 0;
698cb3f0 3558
004d836a
JJ		 3559 /* Define the ia64 floating-point format to gdb. */
3560 builtin_type_ia64_ext =
3561 init_type (TYPE_CODE_FLT, 128 / 8,
3562 0, "builtin_type_ia64_ext", NULL);
3563 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3564
5439edaa
AC		 3565 /* According to the ia64 specs, instructions that store long double
3566 floats in memory use a long-double format different than that
3567 used in the floating registers. The memory format matches the
3568 x86 extended float format which is 80 bits. An OS may choose to
3569 use this format (e.g. GNU/Linux) or choose to use a different
3570 format for storing long doubles (e.g. HPUX). In the latter case,
3571 the setting of the format may be moved/overridden in an
3572 OS-specific tdep file. */
32edc941
JJ		 3573 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3574
16461d7d
KB		 3575 set_gdbarch_short_bit (gdbarch, 16);
3576 set_gdbarch_int_bit (gdbarch, 32);
3577 set_gdbarch_long_bit (gdbarch, 64);
3578 set_gdbarch_long_long_bit (gdbarch, 64);
3579 set_gdbarch_float_bit (gdbarch, 32);
3580 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3581 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3582 set_gdbarch_ptr_bit (gdbarch, 64);
3583
004d836a
JJ		 3584 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3585 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3586 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3587 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3588
3589 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3590 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3591 gets a number of extra failures. */
b1e29e33 3592 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3593 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3594
004d836a
JJ		 3595 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3596 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3597 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3598 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3599 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3600 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3601 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3602
004d836a 3603 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3604
b5622e8d 3605 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3606 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3607
004d836a 3608 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3609 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3610
3611 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3612 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3613 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3614 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3615 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3616
3617 /* Settings for calling functions in the inferior. */
8dd5115e 3618 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3619 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3620 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3621
004d836a 3622 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3623#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3624 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3625 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3626 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3627#else
3628 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3629#endif
004d836a
JJ		 3630 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3631 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3632
3633 /* Settings that should be unnecessary. */
3634 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3635
16461d7d
KB		 3636 set_gdbarch_remote_translate_xfer_address (
3637 gdbarch, ia64_remote_translate_xfer_address);
3638
6926787d 3639 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3640 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3641
b33e8514
AS		 3642 /* Hook in ABI-specific overrides, if they have been registered. */
3643 gdbarch_init_osabi (info, gdbarch);
3644
16461d7d
KB		 3645 return gdbarch;
3646}
3647
a78f21af
AC		 3648extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3649
16461d7d
KB		 3650void
3651_initialize_ia64_tdep (void)
3652{
b33e8514 3653 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3654}
GDB Binutils - Deliverables
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