Commit | Line | Data |
---|---|---|
d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
3 | Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003 Free Software | |
4 | Foundation, Inc. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "frame-unwind.h" | |
26 | #include "frame-base.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
34 | #include "symfile.h" | |
35 | #include "objfiles.h" | |
36 | #include "language.h" | |
37 | #include "arch-utils.h" | |
38 | #include "regcache.h" | |
39 | #include "trad-frame.h" | |
73e8eb51 | 40 | #include "dis-asm.h" |
d95a8903 AC |
41 | |
42 | #include "gdb_assert.h" | |
43 | ||
9b32d526 | 44 | #include "m32r-tdep.h" |
d95a8903 AC |
45 | |
46 | /* Local functions */ | |
47 | ||
48 | extern void _initialize_m32r_tdep (void); | |
49 | ||
50 | static CORE_ADDR | |
51 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
52 | { | |
53 | /* Align to the size of an instruction (so that they can safely be | |
54 | pushed onto the stack. */ | |
55 | return sp & ~3; | |
56 | } | |
57 | ||
74055713 AC |
58 | /* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of |
59 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE | |
60 | is the type (which is known to be struct, union or array). | |
d95a8903 AC |
61 | |
62 | The m32r returns anything less than 8 bytes in size in | |
63 | registers. */ | |
64 | ||
65 | static int | |
66 | m32r_use_struct_convention (int gcc_p, struct type *type) | |
67 | { | |
68 | return (TYPE_LENGTH (type) > 8); | |
69 | } | |
70 | ||
71 | ||
72 | /* BREAKPOINT */ | |
73 | #define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00} | |
74 | #define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70} | |
75 | #define M32R_BE_BREAKPOINT16 {0x10, 0xf1} | |
76 | #define M32R_LE_BREAKPOINT16 {0xf1, 0x10} | |
77 | ||
78 | static int | |
79 | m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache) | |
80 | { | |
81 | int val; | |
82 | unsigned char *bp; | |
83 | int bplen; | |
84 | ||
85 | bplen = (addr & 3) ? 2 : 4; | |
86 | ||
87 | /* Save the memory contents. */ | |
88 | val = target_read_memory (addr, contents_cache, bplen); | |
89 | if (val != 0) | |
90 | return val; /* return error */ | |
91 | ||
92 | /* Determine appropriate breakpoint contents and size for this address. */ | |
93 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
94 | { | |
7e3dd49e AC |
95 | if (((addr & 3) == 0) |
96 | && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80))) | |
d95a8903 AC |
97 | { |
98 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
99 | bp = insn; | |
100 | bplen = sizeof (insn); | |
101 | } | |
102 | else | |
103 | { | |
104 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
105 | bp = insn; | |
106 | bplen = sizeof (insn); | |
107 | } | |
108 | } | |
109 | else | |
110 | { /* little-endian */ | |
7e3dd49e AC |
111 | if (((addr & 3) == 0) |
112 | && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80))) | |
d95a8903 AC |
113 | { |
114 | static unsigned char insn[] = M32R_LE_BREAKPOINT32; | |
115 | bp = insn; | |
116 | bplen = sizeof (insn); | |
117 | } | |
118 | else | |
119 | { | |
120 | static unsigned char insn[] = M32R_LE_BREAKPOINT16; | |
121 | bp = insn; | |
122 | bplen = sizeof (insn); | |
123 | } | |
124 | } | |
125 | ||
126 | /* Write the breakpoint. */ | |
127 | val = target_write_memory (addr, (char *) bp, bplen); | |
128 | return val; | |
129 | } | |
130 | ||
131 | static int | |
132 | m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache) | |
133 | { | |
134 | int val; | |
135 | int bplen; | |
136 | ||
137 | /* Determine appropriate breakpoint contents and size for this address. */ | |
138 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
139 | { | |
7e3dd49e AC |
140 | if (((addr & 3) == 0) |
141 | && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80))) | |
d95a8903 AC |
142 | { |
143 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
144 | bplen = sizeof (insn); | |
145 | } | |
146 | else | |
147 | { | |
148 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
149 | bplen = sizeof (insn); | |
150 | } | |
151 | } | |
152 | else | |
153 | { | |
154 | /* little-endian */ | |
7e3dd49e AC |
155 | if (((addr & 3) == 0) |
156 | && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80))) | |
d95a8903 AC |
157 | { |
158 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
159 | bplen = sizeof (insn); | |
160 | } | |
161 | else | |
162 | { | |
163 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
164 | bplen = sizeof (insn); | |
165 | } | |
166 | } | |
167 | ||
168 | /* Write contents. */ | |
169 | val = target_write_memory (addr, contents_cache, bplen); | |
170 | return val; | |
171 | } | |
172 | ||
173 | static const unsigned char * | |
174 | m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
175 | { | |
176 | unsigned char *bp; | |
177 | ||
178 | /* Determine appropriate breakpoint. */ | |
179 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
180 | { | |
181 | if ((*pcptr & 3) == 0) | |
182 | { | |
183 | static unsigned char insn[] = M32R_BE_BREAKPOINT32; | |
184 | bp = insn; | |
185 | *lenptr = sizeof (insn); | |
186 | } | |
187 | else | |
188 | { | |
189 | static unsigned char insn[] = M32R_BE_BREAKPOINT16; | |
190 | bp = insn; | |
191 | *lenptr = sizeof (insn); | |
192 | } | |
193 | } | |
194 | else | |
195 | { | |
196 | if ((*pcptr & 3) == 0) | |
197 | { | |
198 | static unsigned char insn[] = M32R_LE_BREAKPOINT32; | |
199 | bp = insn; | |
200 | *lenptr = sizeof (insn); | |
201 | } | |
202 | else | |
203 | { | |
204 | static unsigned char insn[] = M32R_LE_BREAKPOINT16; | |
205 | bp = insn; | |
206 | *lenptr = sizeof (insn); | |
207 | } | |
208 | } | |
209 | ||
210 | return bp; | |
211 | } | |
212 | ||
213 | ||
214 | char *m32r_register_names[] = { | |
215 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
216 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
217 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
218 | "evb" | |
219 | }; | |
220 | ||
d95a8903 AC |
221 | static const char * |
222 | m32r_register_name (int reg_nr) | |
223 | { | |
224 | if (reg_nr < 0) | |
225 | return NULL; | |
9b32d526 | 226 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
227 | return NULL; |
228 | return m32r_register_names[reg_nr]; | |
229 | } | |
230 | ||
231 | ||
232 | /* Return the GDB type object for the "standard" data type | |
233 | of data in register N. */ | |
234 | ||
235 | static struct type * | |
236 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
237 | { | |
238 | if (reg_nr == M32R_PC_REGNUM) | |
239 | return builtin_type_void_func_ptr; | |
240 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) | |
241 | return builtin_type_void_data_ptr; | |
242 | else | |
243 | return builtin_type_int32; | |
244 | } | |
245 | ||
246 | ||
247 | /* Write into appropriate registers a function return value | |
248 | of type TYPE, given in virtual format. | |
249 | ||
250 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
251 | ||
252 | static void | |
253 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
254 | const void *valbuf) | |
255 | { | |
256 | CORE_ADDR regval; | |
257 | int len = TYPE_LENGTH (type); | |
258 | ||
259 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len); | |
260 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); | |
261 | ||
262 | if (len > 4) | |
263 | { | |
880bc914 | 264 | regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4); |
d95a8903 AC |
265 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
266 | } | |
267 | } | |
268 | ||
269 | /* Extract from an array REGBUF containing the (raw) register state | |
270 | the address in which a function should return its structure value, | |
271 | as a CORE_ADDR (or an expression that can be used as one). */ | |
272 | ||
273 | static CORE_ADDR | |
274 | m32r_extract_struct_value_address (struct regcache *regcache) | |
275 | { | |
276 | ULONGEST addr; | |
277 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); | |
278 | return addr; | |
279 | } | |
280 | ||
281 | ||
282 | /* This is required by skip_prologue. The results of decoding a prologue | |
283 | should be cached because this thrashing is getting nuts. */ | |
284 | ||
285 | static void | |
286 | decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
287 | CORE_ADDR *pl_endptr) | |
288 | { | |
289 | unsigned long framesize; | |
290 | int insn; | |
291 | int op1; | |
292 | int maybe_one_more = 0; | |
293 | CORE_ADDR after_prologue = 0; | |
294 | CORE_ADDR after_stack_adjust = 0; | |
295 | CORE_ADDR current_pc; | |
296 | ||
297 | framesize = 0; | |
298 | after_prologue = 0; | |
299 | ||
300 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
301 | { | |
302 | insn = read_memory_unsigned_integer (current_pc, 2); | |
303 | ||
304 | /* If this is a 32 bit instruction, we dont want to examine its | |
305 | immediate data as though it were an instruction */ | |
306 | if (current_pc & 0x02) | |
307 | { | |
308 | /* Clear the parallel execution bit from 16 bit instruction */ | |
309 | if (maybe_one_more) | |
310 | { | |
311 | /* The last instruction was a branch, usually terminates | |
312 | the series, but if this is a parallel instruction, | |
313 | it may be a stack framing instruction */ | |
314 | if (!(insn & 0x8000)) | |
315 | { | |
316 | /* nope, we are really done */ | |
317 | break; | |
318 | } | |
319 | } | |
320 | /* decode this instruction further */ | |
321 | insn &= 0x7fff; | |
322 | } | |
323 | else | |
324 | { | |
325 | if (maybe_one_more) | |
326 | break; /* This isnt the one more */ | |
327 | if (insn & 0x8000) | |
328 | { | |
329 | if (current_pc == scan_limit) | |
330 | scan_limit += 2; /* extend the search */ | |
331 | current_pc += 2; /* skip the immediate data */ | |
332 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ | |
333 | /* add 16 bit sign-extended offset */ | |
334 | { | |
335 | framesize += | |
336 | -((short) read_memory_unsigned_integer (current_pc, 2)); | |
337 | } | |
338 | else | |
339 | { | |
7e3dd49e AC |
340 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
341 | && read_memory_unsigned_integer (current_pc + 2, | |
342 | 2) == 0x0f24) | |
d95a8903 AC |
343 | /* subtract 24 bit sign-extended negative-offset */ |
344 | { | |
345 | insn = read_memory_unsigned_integer (current_pc - 2, 4); | |
346 | if (insn & 0x00800000) /* sign extend */ | |
347 | insn |= 0xff000000; /* negative */ | |
348 | else | |
349 | insn &= 0x00ffffff; /* positive */ | |
350 | framesize += insn; | |
351 | } | |
352 | } | |
353 | after_prologue = current_pc; | |
354 | continue; | |
355 | } | |
356 | } | |
357 | op1 = insn & 0xf000; /* isolate just the first nibble */ | |
358 | ||
359 | if ((insn & 0xf0ff) == 0x207f) | |
360 | { /* st reg, @-sp */ | |
361 | int regno; | |
362 | framesize += 4; | |
363 | regno = ((insn >> 8) & 0xf); | |
364 | after_prologue = 0; | |
365 | continue; | |
366 | } | |
367 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
368 | /* add 8 bit sign-extended offset */ | |
369 | { | |
370 | int stack_adjust = (char) (insn & 0xff); | |
371 | ||
372 | /* there are probably two of these stack adjustments: | |
373 | 1) A negative one in the prologue, and | |
374 | 2) A positive one in the epilogue. | |
375 | We are only interested in the first one. */ | |
376 | ||
377 | if (stack_adjust < 0) | |
378 | { | |
379 | framesize -= stack_adjust; | |
380 | after_prologue = 0; | |
381 | /* A frameless function may have no "mv fp, sp". | |
382 | In that case, this is the end of the prologue. */ | |
383 | after_stack_adjust = current_pc + 2; | |
384 | } | |
385 | continue; | |
386 | } | |
387 | if (insn == 0x1d8f) | |
388 | { /* mv fp, sp */ | |
389 | after_prologue = current_pc + 2; | |
390 | break; /* end of stack adjustments */ | |
391 | } | |
392 | /* Nop looks like a branch, continue explicitly */ | |
393 | if (insn == 0x7000) | |
394 | { | |
395 | after_prologue = current_pc + 2; | |
396 | continue; /* nop occurs between pushes */ | |
397 | } | |
398 | /* End of prolog if any of these are branch instructions */ | |
399 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) | |
400 | { | |
401 | after_prologue = current_pc; | |
402 | maybe_one_more = 1; | |
403 | continue; | |
404 | } | |
405 | /* Some of the branch instructions are mixed with other types */ | |
406 | if (op1 == 0x1000) | |
407 | { | |
408 | int subop = insn & 0x0ff0; | |
409 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
410 | { | |
411 | after_prologue = current_pc; | |
412 | maybe_one_more = 1; | |
413 | continue; /* jmp , jl */ | |
414 | } | |
415 | } | |
416 | } | |
417 | ||
418 | if (current_pc >= scan_limit) | |
419 | { | |
420 | if (pl_endptr) | |
421 | { | |
422 | if (after_stack_adjust != 0) | |
423 | /* We did not find a "mv fp,sp", but we DID find | |
424 | a stack_adjust. Is it safe to use that as the | |
425 | end of the prologue? I just don't know. */ | |
426 | { | |
427 | *pl_endptr = after_stack_adjust; | |
428 | } | |
429 | else | |
430 | /* We reached the end of the loop without finding the end | |
431 | of the prologue. No way to win -- we should report failure. | |
432 | The way we do that is to return the original start_pc. | |
433 | GDB will set a breakpoint at the start of the function (etc.) */ | |
434 | *pl_endptr = start_pc; | |
435 | } | |
436 | return; | |
437 | } | |
438 | if (after_prologue == 0) | |
439 | after_prologue = current_pc; | |
440 | ||
441 | if (pl_endptr) | |
442 | *pl_endptr = after_prologue; | |
443 | } /* decode_prologue */ | |
444 | ||
445 | /* Function: skip_prologue | |
446 | Find end of function prologue */ | |
447 | ||
448 | #define DEFAULT_SEARCH_LIMIT 44 | |
449 | ||
450 | CORE_ADDR | |
451 | m32r_skip_prologue (CORE_ADDR pc) | |
452 | { | |
453 | CORE_ADDR func_addr, func_end; | |
454 | struct symtab_and_line sal; | |
455 | ||
456 | /* See what the symbol table says */ | |
457 | ||
458 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
459 | { | |
460 | sal = find_pc_line (func_addr, 0); | |
461 | ||
462 | if (sal.line != 0 && sal.end <= func_end) | |
463 | { | |
464 | func_end = sal.end; | |
465 | } | |
466 | else | |
467 | /* Either there's no line info, or the line after the prologue is after | |
468 | the end of the function. In this case, there probably isn't a | |
469 | prologue. */ | |
470 | { | |
471 | func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); | |
472 | } | |
473 | } | |
474 | else | |
475 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
476 | decode_prologue (pc, func_end, &sal.end); | |
477 | return sal.end; | |
478 | } | |
479 | ||
480 | ||
481 | struct m32r_unwind_cache | |
482 | { | |
483 | /* The previous frame's inner most stack address. Used as this | |
484 | frame ID's stack_addr. */ | |
485 | CORE_ADDR prev_sp; | |
486 | /* The frame's base, optionally used by the high-level debug info. */ | |
487 | CORE_ADDR base; | |
488 | int size; | |
489 | /* How far the SP and r13 (FP) have been offset from the start of | |
490 | the stack frame (as defined by the previous frame's stack | |
491 | pointer). */ | |
492 | LONGEST sp_offset; | |
493 | LONGEST r13_offset; | |
494 | int uses_frame; | |
495 | /* Table indicating the location of each and every register. */ | |
496 | struct trad_frame_saved_reg *saved_regs; | |
497 | }; | |
498 | ||
499 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
500 | the saved registers of frame described by FRAME_INFO. This | |
501 | includes special registers such as pc and fp saved in special ways | |
502 | in the stack frame. sp is even more special: the address we return | |
503 | for it IS the sp for the next frame. */ | |
504 | ||
505 | static struct m32r_unwind_cache * | |
506 | m32r_frame_unwind_cache (struct frame_info *next_frame, | |
507 | void **this_prologue_cache) | |
508 | { | |
509 | CORE_ADDR pc; | |
510 | ULONGEST prev_sp; | |
511 | ULONGEST this_base; | |
512 | unsigned long op; | |
513 | int i; | |
514 | struct m32r_unwind_cache *info; | |
515 | ||
516 | if ((*this_prologue_cache)) | |
517 | return (*this_prologue_cache); | |
518 | ||
519 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
520 | (*this_prologue_cache) = info; | |
521 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
522 | ||
523 | info->size = 0; | |
524 | info->sp_offset = 0; | |
525 | ||
526 | info->uses_frame = 0; | |
527 | for (pc = frame_func_unwind (next_frame); | |
528 | pc > 0 && pc < frame_pc_unwind (next_frame); pc += 2) | |
529 | { | |
530 | if ((pc & 2) == 0) | |
531 | { | |
532 | op = get_frame_memory_unsigned (next_frame, pc, 4); | |
533 | if ((op & 0x80000000) == 0x80000000) | |
534 | { | |
535 | /* 32-bit instruction */ | |
536 | if ((op & 0xffff0000) == 0x8faf0000) | |
537 | { | |
538 | /* add3 sp,sp,xxxx */ | |
539 | short n = op & 0xffff; | |
540 | info->sp_offset += n; | |
541 | } | |
7e3dd49e AC |
542 | else if (((op >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
543 | && get_frame_memory_unsigned (next_frame, pc + 4, | |
544 | 2) == 0x0f24) | |
d95a8903 AC |
545 | { |
546 | unsigned long n = op & 0xffffff; | |
547 | info->sp_offset += n; | |
548 | pc += 2; | |
549 | } | |
550 | else | |
551 | break; | |
552 | ||
553 | pc += 2; | |
554 | continue; | |
555 | } | |
556 | } | |
557 | ||
558 | /* 16-bit instructions */ | |
559 | op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff; | |
560 | if ((op & 0xf0ff) == 0x207f) | |
561 | { | |
562 | /* st rn, @-sp */ | |
563 | int regno = ((op >> 8) & 0xf); | |
564 | info->sp_offset -= 4; | |
565 | info->saved_regs[regno].addr = info->sp_offset; | |
566 | } | |
567 | else if ((op & 0xff00) == 0x4f00) | |
568 | { | |
569 | /* addi sp, xx */ | |
570 | int n = (char) (op & 0xff); | |
571 | info->sp_offset += n; | |
572 | } | |
573 | else if (op == 0x1d8f) | |
574 | { | |
575 | /* mv fp, sp */ | |
576 | info->uses_frame = 1; | |
577 | info->r13_offset = info->sp_offset; | |
578 | } | |
579 | else if (op == 0x7000) | |
580 | /* nop */ | |
581 | continue; | |
582 | else | |
583 | break; | |
584 | } | |
585 | ||
586 | info->size = -info->sp_offset; | |
587 | ||
588 | /* Compute the previous frame's stack pointer (which is also the | |
589 | frame's ID's stack address), and this frame's base pointer. */ | |
590 | if (info->uses_frame) | |
591 | { | |
592 | /* The SP was moved to the FP. This indicates that a new frame | |
593 | was created. Get THIS frame's FP value by unwinding it from | |
594 | the next frame. */ | |
7e3dd49e | 595 | this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM); |
d95a8903 AC |
596 | /* The FP points at the last saved register. Adjust the FP back |
597 | to before the first saved register giving the SP. */ | |
598 | prev_sp = this_base + info->size; | |
599 | } | |
600 | else | |
601 | { | |
602 | /* Assume that the FP is this frame's SP but with that pushed | |
603 | stack space added back. */ | |
7e3dd49e | 604 | this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
605 | prev_sp = this_base + info->size; |
606 | } | |
607 | ||
608 | /* Convert that SP/BASE into real addresses. */ | |
609 | info->prev_sp = prev_sp; | |
610 | info->base = this_base; | |
611 | ||
612 | /* Adjust all the saved registers so that they contain addresses and | |
613 | not offsets. */ | |
614 | for (i = 0; i < NUM_REGS - 1; i++) | |
615 | if (trad_frame_addr_p (info->saved_regs, i)) | |
616 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
617 | ||
618 | /* The call instruction moves the caller's PC in the callee's LR. | |
619 | Since this is an unwind, do the reverse. Copy the location of LR | |
620 | into PC (the address / regnum) so that a request for PC will be | |
621 | converted into a request for the LR. */ | |
622 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
623 | ||
624 | /* The previous frame's SP needed to be computed. Save the computed | |
625 | value. */ | |
626 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
627 | ||
628 | return info; | |
629 | } | |
630 | ||
631 | static CORE_ADDR | |
632 | m32r_read_pc (ptid_t ptid) | |
633 | { | |
634 | ptid_t save_ptid; | |
7e3dd49e | 635 | ULONGEST pc; |
d95a8903 AC |
636 | |
637 | save_ptid = inferior_ptid; | |
638 | inferior_ptid = ptid; | |
7e3dd49e | 639 | regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
640 | inferior_ptid = save_ptid; |
641 | return pc; | |
642 | } | |
643 | ||
644 | static void | |
645 | m32r_write_pc (CORE_ADDR val, ptid_t ptid) | |
646 | { | |
647 | ptid_t save_ptid; | |
648 | ||
649 | save_ptid = inferior_ptid; | |
650 | inferior_ptid = ptid; | |
651 | write_register (M32R_PC_REGNUM, val); | |
652 | inferior_ptid = save_ptid; | |
653 | } | |
654 | ||
655 | static CORE_ADDR | |
656 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
657 | { | |
7e3dd49e | 658 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
659 | } |
660 | ||
661 | ||
662 | static CORE_ADDR | |
7d9b040b | 663 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
664 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
665 | struct value **args, CORE_ADDR sp, int struct_return, | |
666 | CORE_ADDR struct_addr) | |
667 | { | |
668 | int stack_offset, stack_alloc; | |
669 | int argreg = ARG1_REGNUM; | |
670 | int argnum; | |
671 | struct type *type; | |
672 | enum type_code typecode; | |
673 | CORE_ADDR regval; | |
674 | char *val; | |
675 | char valbuf[MAX_REGISTER_SIZE]; | |
676 | int len; | |
677 | int odd_sized_struct; | |
678 | ||
679 | /* first force sp to a 4-byte alignment */ | |
680 | sp = sp & ~3; | |
681 | ||
682 | /* Set the return address. For the m32r, the return breakpoint is | |
683 | always at BP_ADDR. */ | |
684 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
685 | ||
686 | /* If STRUCT_RETURN is true, then the struct return address (in | |
687 | STRUCT_ADDR) will consume the first argument-passing register. | |
688 | Both adjust the register count and store that value. */ | |
689 | if (struct_return) | |
690 | { | |
691 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
692 | argreg++; | |
693 | } | |
694 | ||
695 | /* Now make sure there's space on the stack */ | |
696 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
697 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); | |
698 | sp -= stack_alloc; /* make room on stack for args */ | |
699 | ||
700 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
701 | { | |
702 | type = VALUE_TYPE (args[argnum]); | |
703 | typecode = TYPE_CODE (type); | |
704 | len = TYPE_LENGTH (type); | |
705 | ||
706 | memset (valbuf, 0, sizeof (valbuf)); | |
707 | ||
708 | /* Passes structures that do not fit in 2 registers by reference. */ | |
709 | if (len > 8 | |
710 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
711 | { | |
712 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum])); | |
713 | typecode = TYPE_CODE_PTR; | |
714 | len = 4; | |
715 | val = valbuf; | |
716 | } | |
717 | else if (len < 4) | |
718 | { | |
719 | /* value gets right-justified in the register or stack word */ | |
7e3dd49e | 720 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
d95a8903 AC |
721 | (char *) VALUE_CONTENTS (args[argnum]), len); |
722 | val = valbuf; | |
723 | } | |
724 | else | |
725 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
726 | ||
727 | while (len > 0) | |
728 | { | |
729 | if (argreg > ARGN_REGNUM) | |
730 | { | |
731 | /* must go on the stack */ | |
732 | write_memory (sp + stack_offset, val, 4); | |
733 | stack_offset += 4; | |
734 | } | |
735 | else if (argreg <= ARGN_REGNUM) | |
736 | { | |
737 | /* there's room in a register */ | |
738 | regval = | |
7e3dd49e AC |
739 | extract_unsigned_integer (val, |
740 | register_size (gdbarch, argreg)); | |
d95a8903 AC |
741 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
742 | } | |
743 | ||
744 | /* Store the value 4 bytes at a time. This means that things | |
745 | larger than 4 bytes may go partly in registers and partly | |
746 | on the stack. */ | |
7e3dd49e AC |
747 | len -= register_size (gdbarch, argreg); |
748 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
749 | } |
750 | } | |
751 | ||
752 | /* Finally, update the SP register. */ | |
753 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
754 | ||
755 | return sp; | |
756 | } | |
757 | ||
758 | ||
759 | /* Given a return value in `regbuf' with a type `valtype', | |
760 | extract and copy its value into `valbuf'. */ | |
761 | ||
762 | static void | |
763 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
764 | void *dst) | |
765 | { | |
766 | bfd_byte *valbuf = dst; | |
767 | int len = TYPE_LENGTH (type); | |
768 | ULONGEST tmp; | |
769 | ||
770 | /* By using store_unsigned_integer we avoid having to do | |
771 | anything special for small big-endian values. */ | |
772 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
773 | store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp); | |
774 | ||
775 | /* Ignore return values more than 8 bytes in size because the m32r | |
776 | returns anything more than 8 bytes in the stack. */ | |
777 | if (len > 4) | |
778 | { | |
779 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
780 | store_unsigned_integer (valbuf + len - 4, 4, tmp); | |
781 | } | |
782 | } | |
783 | ||
784 | ||
785 | static CORE_ADDR | |
786 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
787 | { | |
7e3dd49e | 788 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
789 | } |
790 | ||
791 | /* Given a GDB frame, determine the address of the calling function's | |
792 | frame. This will be used to create a new GDB frame struct. */ | |
793 | ||
794 | static void | |
795 | m32r_frame_this_id (struct frame_info *next_frame, | |
796 | void **this_prologue_cache, struct frame_id *this_id) | |
797 | { | |
798 | struct m32r_unwind_cache *info | |
799 | = m32r_frame_unwind_cache (next_frame, this_prologue_cache); | |
800 | CORE_ADDR base; | |
801 | CORE_ADDR func; | |
802 | struct minimal_symbol *msym_stack; | |
803 | struct frame_id id; | |
804 | ||
805 | /* The FUNC is easy. */ | |
806 | func = frame_func_unwind (next_frame); | |
807 | ||
d95a8903 AC |
808 | /* Check if the stack is empty. */ |
809 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
810 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
811 | return; | |
812 | ||
813 | /* Hopefully the prologue analysis either correctly determined the | |
814 | frame's base (which is the SP from the previous frame), or set | |
815 | that base to "NULL". */ | |
816 | base = info->prev_sp; | |
817 | if (base == 0) | |
818 | return; | |
819 | ||
820 | id = frame_id_build (base, func); | |
d95a8903 AC |
821 | (*this_id) = id; |
822 | } | |
823 | ||
824 | static void | |
825 | m32r_frame_prev_register (struct frame_info *next_frame, | |
826 | void **this_prologue_cache, | |
827 | int regnum, int *optimizedp, | |
828 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
829 | int *realnump, void *bufferp) | |
830 | { | |
831 | struct m32r_unwind_cache *info | |
832 | = m32r_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
833 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
834 | optimizedp, lvalp, addrp, realnump, bufferp); | |
d95a8903 AC |
835 | } |
836 | ||
837 | static const struct frame_unwind m32r_frame_unwind = { | |
838 | NORMAL_FRAME, | |
839 | m32r_frame_this_id, | |
840 | m32r_frame_prev_register | |
841 | }; | |
842 | ||
843 | static const struct frame_unwind * | |
7e3dd49e | 844 | m32r_frame_sniffer (struct frame_info *next_frame) |
d95a8903 AC |
845 | { |
846 | return &m32r_frame_unwind; | |
847 | } | |
848 | ||
849 | static CORE_ADDR | |
850 | m32r_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
851 | { | |
852 | struct m32r_unwind_cache *info | |
853 | = m32r_frame_unwind_cache (next_frame, this_cache); | |
854 | return info->base; | |
855 | } | |
856 | ||
857 | static const struct frame_base m32r_frame_base = { | |
858 | &m32r_frame_unwind, | |
859 | m32r_frame_base_address, | |
860 | m32r_frame_base_address, | |
861 | m32r_frame_base_address | |
862 | }; | |
863 | ||
864 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
865 | dummy frame. The frame ID's base needs to match the TOS value | |
866 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
867 | breakpoint. */ | |
868 | ||
869 | static struct frame_id | |
870 | m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
871 | { | |
872 | return frame_id_build (m32r_unwind_sp (gdbarch, next_frame), | |
873 | frame_pc_unwind (next_frame)); | |
874 | } | |
875 | ||
876 | ||
877 | static gdbarch_init_ftype m32r_gdbarch_init; | |
878 | ||
879 | static struct gdbarch * | |
880 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
881 | { | |
882 | struct gdbarch *gdbarch; | |
883 | struct gdbarch_tdep *tdep; | |
884 | ||
885 | /* If there is already a candidate, use it. */ | |
886 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
887 | if (arches != NULL) | |
888 | return arches->gdbarch; | |
889 | ||
890 | /* Allocate space for the new architecture. */ | |
891 | tdep = XMALLOC (struct gdbarch_tdep); | |
892 | gdbarch = gdbarch_alloc (&info, tdep); | |
893 | ||
894 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
895 | set_gdbarch_write_pc (gdbarch, m32r_write_pc); | |
896 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); | |
897 | ||
9b32d526 | 898 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d95a8903 AC |
899 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
900 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
901 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
902 | ||
903 | set_gdbarch_extract_return_value (gdbarch, m32r_extract_return_value); | |
904 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); | |
905 | set_gdbarch_store_return_value (gdbarch, m32r_store_return_value); | |
9b32d526 KI |
906 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, |
907 | m32r_extract_struct_value_address); | |
908 | set_gdbarch_deprecated_use_struct_convention (gdbarch, | |
909 | m32r_use_struct_convention); | |
d95a8903 AC |
910 | |
911 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
912 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d95a8903 AC |
913 | set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); |
914 | set_gdbarch_memory_insert_breakpoint (gdbarch, | |
915 | m32r_memory_insert_breakpoint); | |
916 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
917 | m32r_memory_remove_breakpoint); | |
918 | ||
d95a8903 AC |
919 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
920 | ||
7e3dd49e | 921 | frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer); |
d95a8903 AC |
922 | frame_base_set_default (gdbarch, &m32r_frame_base); |
923 | ||
924 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
925 | stack address must match the SP value returned by | |
926 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
927 | set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id); | |
928 | ||
929 | /* Return the unwound PC value. */ | |
930 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
931 | ||
932 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
933 | ||
934 | return gdbarch; | |
935 | } | |
936 | ||
937 | void | |
938 | _initialize_m32r_tdep (void) | |
939 | { | |
940 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
941 | } |