Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
cea15572 | 3 | Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
d95a8903 AC |
4 | Foundation, Inc. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "frame-unwind.h" | |
26 | #include "frame-base.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
34 | #include "symfile.h" | |
35 | #include "objfiles.h" | |
36 | #include "language.h" | |
37 | #include "arch-utils.h" | |
38 | #include "regcache.h" | |
39 | #include "trad-frame.h" | |
73e8eb51 | 40 | #include "dis-asm.h" |
d95a8903 AC |
41 | |
42 | #include "gdb_assert.h" | |
43 | ||
9b32d526 | 44 | #include "m32r-tdep.h" |
d95a8903 AC |
45 | |
46 | /* Local functions */ | |
47 | ||
48 | extern void _initialize_m32r_tdep (void); | |
49 | ||
50 | static CORE_ADDR | |
51 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
52 | { | |
53 | /* Align to the size of an instruction (so that they can safely be | |
54 | pushed onto the stack. */ | |
55 | return sp & ~3; | |
56 | } | |
57 | ||
d95a8903 | 58 | |
9f0b0322 KI |
59 | /* Breakpoints |
60 | ||
61 | The little endian mode of M32R is unique. In most of architectures, | |
62 | two 16-bit instructions, A and B, are placed as the following: | |
63 | ||
64 | Big endian: | |
65 | A0 A1 B0 B1 | |
66 | ||
67 | Little endian: | |
68 | A1 A0 B1 B0 | |
69 | ||
70 | In M32R, they are placed like this: | |
71 | ||
72 | Big endian: | |
73 | A0 A1 B0 B1 | |
74 | ||
75 | Little endian: | |
76 | B1 B0 A1 A0 | |
77 | ||
78 | This is because M32R always fetches instructions in 32-bit. | |
79 | ||
80 | The following functions take care of this behavior. */ | |
d95a8903 AC |
81 | |
82 | static int | |
83 | m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache) | |
84 | { | |
85 | int val; | |
9f0b0322 KI |
86 | char buf[4]; |
87 | char bp_entry[] = { 0x10, 0xf1 }; /* dpt */ | |
d95a8903 AC |
88 | |
89 | /* Save the memory contents. */ | |
9f0b0322 | 90 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
91 | if (val != 0) |
92 | return val; /* return error */ | |
93 | ||
94 | /* Determine appropriate breakpoint contents and size for this address. */ | |
95 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
96 | { | |
9f0b0322 | 97 | if ((addr & 3) == 0) |
d95a8903 | 98 | { |
9f0b0322 KI |
99 | buf[0] = bp_entry[0]; |
100 | buf[1] = bp_entry[1]; | |
101 | buf[2] = contents_cache[2] & 0x7f; | |
102 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
103 | } |
104 | else | |
105 | { | |
9f0b0322 KI |
106 | buf[0] = contents_cache[0]; |
107 | buf[1] = contents_cache[1]; | |
108 | buf[2] = bp_entry[0]; | |
109 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
110 | } |
111 | } | |
9f0b0322 KI |
112 | else /* little-endian */ |
113 | { | |
114 | if ((addr & 3) == 0) | |
d95a8903 | 115 | { |
9f0b0322 KI |
116 | buf[0] = contents_cache[0]; |
117 | buf[1] = contents_cache[1] & 0x7f; | |
118 | buf[2] = bp_entry[1]; | |
119 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
120 | } |
121 | else | |
122 | { | |
9f0b0322 KI |
123 | buf[0] = bp_entry[1]; |
124 | buf[1] = bp_entry[0]; | |
125 | buf[2] = contents_cache[2]; | |
126 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
127 | } |
128 | } | |
129 | ||
130 | /* Write the breakpoint. */ | |
9f0b0322 | 131 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
132 | return val; |
133 | } | |
134 | ||
135 | static int | |
136 | m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache) | |
137 | { | |
138 | int val; | |
9f0b0322 | 139 | char buf[4]; |
d95a8903 | 140 | |
9f0b0322 KI |
141 | buf[0] = contents_cache[0]; |
142 | buf[1] = contents_cache[1]; | |
143 | buf[2] = contents_cache[2]; | |
144 | buf[3] = contents_cache[3]; | |
145 | ||
146 | /* Remove parallel bit. */ | |
d95a8903 AC |
147 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
148 | { | |
9f0b0322 KI |
149 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
150 | buf[2] &= 0x7f; | |
d95a8903 | 151 | } |
9f0b0322 | 152 | else /* little-endian */ |
d95a8903 | 153 | { |
9f0b0322 KI |
154 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
155 | buf[1] &= 0x7f; | |
d95a8903 AC |
156 | } |
157 | ||
158 | /* Write contents. */ | |
9f0b0322 | 159 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
160 | return val; |
161 | } | |
162 | ||
163 | static const unsigned char * | |
164 | m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
165 | { | |
9f0b0322 KI |
166 | static char be_bp_entry[] = { 0x10, 0xf1, 0x70, 0x00 }; /* dpt -> nop */ |
167 | static char le_bp_entry[] = { 0x00, 0x70, 0xf1, 0x10 }; /* dpt -> nop */ | |
d95a8903 AC |
168 | unsigned char *bp; |
169 | ||
170 | /* Determine appropriate breakpoint. */ | |
171 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
172 | { | |
173 | if ((*pcptr & 3) == 0) | |
174 | { | |
9f0b0322 KI |
175 | bp = be_bp_entry; |
176 | *lenptr = 4; | |
d95a8903 AC |
177 | } |
178 | else | |
179 | { | |
9f0b0322 KI |
180 | bp = be_bp_entry; |
181 | *lenptr = 2; | |
d95a8903 AC |
182 | } |
183 | } | |
184 | else | |
185 | { | |
186 | if ((*pcptr & 3) == 0) | |
187 | { | |
9f0b0322 KI |
188 | bp = le_bp_entry; |
189 | *lenptr = 4; | |
d95a8903 AC |
190 | } |
191 | else | |
192 | { | |
9f0b0322 KI |
193 | bp = le_bp_entry + 2; |
194 | *lenptr = 2; | |
d95a8903 AC |
195 | } |
196 | } | |
197 | ||
198 | return bp; | |
199 | } | |
200 | ||
201 | ||
202 | char *m32r_register_names[] = { | |
203 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
204 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
205 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
206 | "evb" | |
207 | }; | |
208 | ||
d95a8903 AC |
209 | static const char * |
210 | m32r_register_name (int reg_nr) | |
211 | { | |
212 | if (reg_nr < 0) | |
213 | return NULL; | |
9b32d526 | 214 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
215 | return NULL; |
216 | return m32r_register_names[reg_nr]; | |
217 | } | |
218 | ||
219 | ||
220 | /* Return the GDB type object for the "standard" data type | |
221 | of data in register N. */ | |
222 | ||
223 | static struct type * | |
224 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
225 | { | |
226 | if (reg_nr == M32R_PC_REGNUM) | |
227 | return builtin_type_void_func_ptr; | |
228 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) | |
229 | return builtin_type_void_data_ptr; | |
230 | else | |
231 | return builtin_type_int32; | |
232 | } | |
233 | ||
234 | ||
235 | /* Write into appropriate registers a function return value | |
236 | of type TYPE, given in virtual format. | |
237 | ||
238 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ | |
239 | ||
240 | static void | |
241 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
242 | const void *valbuf) | |
243 | { | |
244 | CORE_ADDR regval; | |
245 | int len = TYPE_LENGTH (type); | |
246 | ||
247 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len); | |
248 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); | |
249 | ||
250 | if (len > 4) | |
251 | { | |
880bc914 | 252 | regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4); |
d95a8903 AC |
253 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
254 | } | |
255 | } | |
256 | ||
d95a8903 AC |
257 | /* This is required by skip_prologue. The results of decoding a prologue |
258 | should be cached because this thrashing is getting nuts. */ | |
259 | ||
cea15572 | 260 | static int |
d95a8903 | 261 | decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, |
cea15572 | 262 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 AC |
263 | { |
264 | unsigned long framesize; | |
265 | int insn; | |
266 | int op1; | |
d95a8903 | 267 | CORE_ADDR after_prologue = 0; |
cea15572 | 268 | CORE_ADDR after_push = 0; |
d95a8903 AC |
269 | CORE_ADDR after_stack_adjust = 0; |
270 | CORE_ADDR current_pc; | |
cea15572 | 271 | LONGEST return_value; |
d95a8903 AC |
272 | |
273 | framesize = 0; | |
274 | after_prologue = 0; | |
275 | ||
276 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
277 | { | |
cea15572 KI |
278 | /* Check if current pc's location is readable. */ |
279 | if (!safe_read_memory_integer (current_pc, 2, &return_value)) | |
280 | return -1; | |
281 | ||
d95a8903 AC |
282 | insn = read_memory_unsigned_integer (current_pc, 2); |
283 | ||
cea15572 KI |
284 | if (insn == 0x0000) |
285 | break; | |
286 | ||
d95a8903 AC |
287 | /* If this is a 32 bit instruction, we dont want to examine its |
288 | immediate data as though it were an instruction */ | |
289 | if (current_pc & 0x02) | |
290 | { | |
d95a8903 AC |
291 | /* decode this instruction further */ |
292 | insn &= 0x7fff; | |
293 | } | |
294 | else | |
295 | { | |
d95a8903 AC |
296 | if (insn & 0x8000) |
297 | { | |
298 | if (current_pc == scan_limit) | |
299 | scan_limit += 2; /* extend the search */ | |
cea15572 | 300 | |
d95a8903 | 301 | current_pc += 2; /* skip the immediate data */ |
cea15572 KI |
302 | |
303 | /* Check if current pc's location is readable. */ | |
304 | if (!safe_read_memory_integer (current_pc, 2, &return_value)) | |
305 | return -1; | |
306 | ||
d95a8903 AC |
307 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
308 | /* add 16 bit sign-extended offset */ | |
309 | { | |
310 | framesize += | |
311 | -((short) read_memory_unsigned_integer (current_pc, 2)); | |
312 | } | |
313 | else | |
314 | { | |
7e3dd49e | 315 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
cea15572 KI |
316 | && safe_read_memory_integer (current_pc + 2, 2, |
317 | &return_value) | |
7e3dd49e AC |
318 | && read_memory_unsigned_integer (current_pc + 2, |
319 | 2) == 0x0f24) | |
d95a8903 AC |
320 | /* subtract 24 bit sign-extended negative-offset */ |
321 | { | |
322 | insn = read_memory_unsigned_integer (current_pc - 2, 4); | |
323 | if (insn & 0x00800000) /* sign extend */ | |
324 | insn |= 0xff000000; /* negative */ | |
325 | else | |
326 | insn &= 0x00ffffff; /* positive */ | |
327 | framesize += insn; | |
328 | } | |
329 | } | |
cea15572 | 330 | after_push = current_pc + 2; |
d95a8903 AC |
331 | continue; |
332 | } | |
333 | } | |
334 | op1 = insn & 0xf000; /* isolate just the first nibble */ | |
335 | ||
336 | if ((insn & 0xf0ff) == 0x207f) | |
337 | { /* st reg, @-sp */ | |
338 | int regno; | |
339 | framesize += 4; | |
340 | regno = ((insn >> 8) & 0xf); | |
341 | after_prologue = 0; | |
342 | continue; | |
343 | } | |
344 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
345 | /* add 8 bit sign-extended offset */ | |
346 | { | |
347 | int stack_adjust = (char) (insn & 0xff); | |
348 | ||
349 | /* there are probably two of these stack adjustments: | |
350 | 1) A negative one in the prologue, and | |
351 | 2) A positive one in the epilogue. | |
352 | We are only interested in the first one. */ | |
353 | ||
354 | if (stack_adjust < 0) | |
355 | { | |
356 | framesize -= stack_adjust; | |
357 | after_prologue = 0; | |
358 | /* A frameless function may have no "mv fp, sp". | |
359 | In that case, this is the end of the prologue. */ | |
360 | after_stack_adjust = current_pc + 2; | |
361 | } | |
362 | continue; | |
363 | } | |
364 | if (insn == 0x1d8f) | |
365 | { /* mv fp, sp */ | |
366 | after_prologue = current_pc + 2; | |
367 | break; /* end of stack adjustments */ | |
368 | } | |
cea15572 | 369 | |
d95a8903 AC |
370 | /* Nop looks like a branch, continue explicitly */ |
371 | if (insn == 0x7000) | |
372 | { | |
373 | after_prologue = current_pc + 2; | |
374 | continue; /* nop occurs between pushes */ | |
375 | } | |
cea15572 KI |
376 | /* End of prolog if any of these are trap instructions */ |
377 | if ((insn & 0xfff0) == 0x10f0) | |
378 | { | |
379 | after_prologue = current_pc; | |
380 | break; | |
381 | } | |
d95a8903 AC |
382 | /* End of prolog if any of these are branch instructions */ |
383 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) | |
384 | { | |
385 | after_prologue = current_pc; | |
d95a8903 AC |
386 | continue; |
387 | } | |
388 | /* Some of the branch instructions are mixed with other types */ | |
389 | if (op1 == 0x1000) | |
390 | { | |
391 | int subop = insn & 0x0ff0; | |
392 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
393 | { | |
394 | after_prologue = current_pc; | |
d95a8903 AC |
395 | continue; /* jmp , jl */ |
396 | } | |
397 | } | |
398 | } | |
399 | ||
cea15572 KI |
400 | if (framelength) |
401 | *framelength = framesize; | |
402 | ||
d95a8903 AC |
403 | if (current_pc >= scan_limit) |
404 | { | |
405 | if (pl_endptr) | |
406 | { | |
407 | if (after_stack_adjust != 0) | |
408 | /* We did not find a "mv fp,sp", but we DID find | |
409 | a stack_adjust. Is it safe to use that as the | |
410 | end of the prologue? I just don't know. */ | |
411 | { | |
412 | *pl_endptr = after_stack_adjust; | |
413 | } | |
cea15572 KI |
414 | else if (after_push != 0) |
415 | /* We did not find a "mv fp,sp", but we DID find | |
416 | a push. Is it safe to use that as the | |
417 | end of the prologue? I just don't know. */ | |
418 | { | |
419 | *pl_endptr = after_push; | |
420 | } | |
d95a8903 AC |
421 | else |
422 | /* We reached the end of the loop without finding the end | |
423 | of the prologue. No way to win -- we should report failure. | |
424 | The way we do that is to return the original start_pc. | |
425 | GDB will set a breakpoint at the start of the function (etc.) */ | |
426 | *pl_endptr = start_pc; | |
427 | } | |
cea15572 | 428 | return 0; |
d95a8903 | 429 | } |
cea15572 | 430 | |
d95a8903 AC |
431 | if (after_prologue == 0) |
432 | after_prologue = current_pc; | |
433 | ||
434 | if (pl_endptr) | |
435 | *pl_endptr = after_prologue; | |
cea15572 KI |
436 | |
437 | return 0; | |
d95a8903 AC |
438 | } /* decode_prologue */ |
439 | ||
440 | /* Function: skip_prologue | |
441 | Find end of function prologue */ | |
442 | ||
cea15572 | 443 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 AC |
444 | |
445 | CORE_ADDR | |
446 | m32r_skip_prologue (CORE_ADDR pc) | |
447 | { | |
448 | CORE_ADDR func_addr, func_end; | |
449 | struct symtab_and_line sal; | |
cea15572 | 450 | LONGEST return_value; |
d95a8903 AC |
451 | |
452 | /* See what the symbol table says */ | |
453 | ||
454 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
455 | { | |
456 | sal = find_pc_line (func_addr, 0); | |
457 | ||
458 | if (sal.line != 0 && sal.end <= func_end) | |
459 | { | |
460 | func_end = sal.end; | |
461 | } | |
462 | else | |
463 | /* Either there's no line info, or the line after the prologue is after | |
464 | the end of the function. In this case, there probably isn't a | |
465 | prologue. */ | |
466 | { | |
467 | func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); | |
468 | } | |
469 | } | |
470 | else | |
471 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 KI |
472 | |
473 | /* If pc's location is not readable, just quit. */ | |
474 | if (!safe_read_memory_integer (pc, 4, &return_value)) | |
475 | return pc; | |
476 | ||
477 | /* Find the end of prologue. */ | |
478 | if (decode_prologue (pc, func_end, &sal.end, NULL) < 0) | |
479 | return pc; | |
480 | ||
d95a8903 AC |
481 | return sal.end; |
482 | } | |
483 | ||
d95a8903 AC |
484 | struct m32r_unwind_cache |
485 | { | |
486 | /* The previous frame's inner most stack address. Used as this | |
487 | frame ID's stack_addr. */ | |
488 | CORE_ADDR prev_sp; | |
489 | /* The frame's base, optionally used by the high-level debug info. */ | |
490 | CORE_ADDR base; | |
491 | int size; | |
492 | /* How far the SP and r13 (FP) have been offset from the start of | |
493 | the stack frame (as defined by the previous frame's stack | |
494 | pointer). */ | |
495 | LONGEST sp_offset; | |
496 | LONGEST r13_offset; | |
497 | int uses_frame; | |
498 | /* Table indicating the location of each and every register. */ | |
499 | struct trad_frame_saved_reg *saved_regs; | |
500 | }; | |
501 | ||
502 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
503 | the saved registers of frame described by FRAME_INFO. This | |
504 | includes special registers such as pc and fp saved in special ways | |
505 | in the stack frame. sp is even more special: the address we return | |
506 | for it IS the sp for the next frame. */ | |
507 | ||
508 | static struct m32r_unwind_cache * | |
509 | m32r_frame_unwind_cache (struct frame_info *next_frame, | |
510 | void **this_prologue_cache) | |
511 | { | |
cea15572 | 512 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
513 | ULONGEST prev_sp; |
514 | ULONGEST this_base; | |
cea15572 | 515 | unsigned long op, op2; |
d95a8903 AC |
516 | int i; |
517 | struct m32r_unwind_cache *info; | |
518 | ||
cea15572 | 519 | |
d95a8903 AC |
520 | if ((*this_prologue_cache)) |
521 | return (*this_prologue_cache); | |
522 | ||
523 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
524 | (*this_prologue_cache) = info; | |
525 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
526 | ||
527 | info->size = 0; | |
528 | info->sp_offset = 0; | |
d95a8903 | 529 | info->uses_frame = 0; |
cea15572 KI |
530 | |
531 | scan_limit = frame_pc_unwind (next_frame); | |
d95a8903 | 532 | for (pc = frame_func_unwind (next_frame); |
cea15572 | 533 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
534 | { |
535 | if ((pc & 2) == 0) | |
536 | { | |
537 | op = get_frame_memory_unsigned (next_frame, pc, 4); | |
538 | if ((op & 0x80000000) == 0x80000000) | |
539 | { | |
540 | /* 32-bit instruction */ | |
541 | if ((op & 0xffff0000) == 0x8faf0000) | |
542 | { | |
543 | /* add3 sp,sp,xxxx */ | |
544 | short n = op & 0xffff; | |
545 | info->sp_offset += n; | |
546 | } | |
cea15572 KI |
547 | else if (((op >> 8) == 0xe4) |
548 | && get_frame_memory_unsigned (next_frame, pc + 2, | |
7e3dd49e | 549 | 2) == 0x0f24) |
d95a8903 | 550 | { |
cea15572 | 551 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
552 | unsigned long n = op & 0xffffff; |
553 | info->sp_offset += n; | |
cea15572 | 554 | pc += 2; /* skip sub instruction */ |
d95a8903 | 555 | } |
d95a8903 | 556 | |
cea15572 KI |
557 | if (pc == scan_limit) |
558 | scan_limit += 2; /* extend the search */ | |
559 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
560 | continue; |
561 | } | |
562 | } | |
563 | ||
564 | /* 16-bit instructions */ | |
565 | op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff; | |
566 | if ((op & 0xf0ff) == 0x207f) | |
567 | { | |
568 | /* st rn, @-sp */ | |
569 | int regno = ((op >> 8) & 0xf); | |
570 | info->sp_offset -= 4; | |
571 | info->saved_regs[regno].addr = info->sp_offset; | |
572 | } | |
573 | else if ((op & 0xff00) == 0x4f00) | |
574 | { | |
575 | /* addi sp, xx */ | |
576 | int n = (char) (op & 0xff); | |
577 | info->sp_offset += n; | |
578 | } | |
579 | else if (op == 0x1d8f) | |
580 | { | |
581 | /* mv fp, sp */ | |
582 | info->uses_frame = 1; | |
583 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
584 | break; /* end of stack adjustments */ |
585 | } | |
586 | else if ((op & 0xfff0) == 0x10f0) | |
587 | { | |
588 | /* end of prologue if this is a trap instruction */ | |
589 | break; /* end of stack adjustments */ | |
d95a8903 | 590 | } |
d95a8903 AC |
591 | } |
592 | ||
593 | info->size = -info->sp_offset; | |
594 | ||
595 | /* Compute the previous frame's stack pointer (which is also the | |
596 | frame's ID's stack address), and this frame's base pointer. */ | |
597 | if (info->uses_frame) | |
598 | { | |
599 | /* The SP was moved to the FP. This indicates that a new frame | |
600 | was created. Get THIS frame's FP value by unwinding it from | |
601 | the next frame. */ | |
7e3dd49e | 602 | this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM); |
d95a8903 AC |
603 | /* The FP points at the last saved register. Adjust the FP back |
604 | to before the first saved register giving the SP. */ | |
605 | prev_sp = this_base + info->size; | |
606 | } | |
607 | else | |
608 | { | |
609 | /* Assume that the FP is this frame's SP but with that pushed | |
610 | stack space added back. */ | |
7e3dd49e | 611 | this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
612 | prev_sp = this_base + info->size; |
613 | } | |
614 | ||
615 | /* Convert that SP/BASE into real addresses. */ | |
616 | info->prev_sp = prev_sp; | |
617 | info->base = this_base; | |
618 | ||
619 | /* Adjust all the saved registers so that they contain addresses and | |
620 | not offsets. */ | |
621 | for (i = 0; i < NUM_REGS - 1; i++) | |
622 | if (trad_frame_addr_p (info->saved_regs, i)) | |
623 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
624 | ||
625 | /* The call instruction moves the caller's PC in the callee's LR. | |
626 | Since this is an unwind, do the reverse. Copy the location of LR | |
627 | into PC (the address / regnum) so that a request for PC will be | |
628 | converted into a request for the LR. */ | |
629 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
630 | ||
631 | /* The previous frame's SP needed to be computed. Save the computed | |
632 | value. */ | |
633 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
634 | ||
635 | return info; | |
636 | } | |
637 | ||
638 | static CORE_ADDR | |
639 | m32r_read_pc (ptid_t ptid) | |
640 | { | |
641 | ptid_t save_ptid; | |
7e3dd49e | 642 | ULONGEST pc; |
d95a8903 AC |
643 | |
644 | save_ptid = inferior_ptid; | |
645 | inferior_ptid = ptid; | |
7e3dd49e | 646 | regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
647 | inferior_ptid = save_ptid; |
648 | return pc; | |
649 | } | |
650 | ||
651 | static void | |
652 | m32r_write_pc (CORE_ADDR val, ptid_t ptid) | |
653 | { | |
654 | ptid_t save_ptid; | |
655 | ||
656 | save_ptid = inferior_ptid; | |
657 | inferior_ptid = ptid; | |
658 | write_register (M32R_PC_REGNUM, val); | |
659 | inferior_ptid = save_ptid; | |
660 | } | |
661 | ||
662 | static CORE_ADDR | |
663 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
664 | { | |
7e3dd49e | 665 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
666 | } |
667 | ||
668 | ||
669 | static CORE_ADDR | |
7d9b040b | 670 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
671 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
672 | struct value **args, CORE_ADDR sp, int struct_return, | |
673 | CORE_ADDR struct_addr) | |
674 | { | |
675 | int stack_offset, stack_alloc; | |
676 | int argreg = ARG1_REGNUM; | |
677 | int argnum; | |
678 | struct type *type; | |
679 | enum type_code typecode; | |
680 | CORE_ADDR regval; | |
681 | char *val; | |
682 | char valbuf[MAX_REGISTER_SIZE]; | |
683 | int len; | |
684 | int odd_sized_struct; | |
685 | ||
686 | /* first force sp to a 4-byte alignment */ | |
687 | sp = sp & ~3; | |
688 | ||
689 | /* Set the return address. For the m32r, the return breakpoint is | |
690 | always at BP_ADDR. */ | |
691 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
692 | ||
693 | /* If STRUCT_RETURN is true, then the struct return address (in | |
694 | STRUCT_ADDR) will consume the first argument-passing register. | |
695 | Both adjust the register count and store that value. */ | |
696 | if (struct_return) | |
697 | { | |
698 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
699 | argreg++; | |
700 | } | |
701 | ||
702 | /* Now make sure there's space on the stack */ | |
703 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
704 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); | |
705 | sp -= stack_alloc; /* make room on stack for args */ | |
706 | ||
707 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
708 | { | |
709 | type = VALUE_TYPE (args[argnum]); | |
710 | typecode = TYPE_CODE (type); | |
711 | len = TYPE_LENGTH (type); | |
712 | ||
713 | memset (valbuf, 0, sizeof (valbuf)); | |
714 | ||
715 | /* Passes structures that do not fit in 2 registers by reference. */ | |
716 | if (len > 8 | |
717 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
718 | { | |
719 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum])); | |
720 | typecode = TYPE_CODE_PTR; | |
721 | len = 4; | |
722 | val = valbuf; | |
723 | } | |
724 | else if (len < 4) | |
725 | { | |
726 | /* value gets right-justified in the register or stack word */ | |
7e3dd49e | 727 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
d95a8903 AC |
728 | (char *) VALUE_CONTENTS (args[argnum]), len); |
729 | val = valbuf; | |
730 | } | |
731 | else | |
732 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
733 | ||
734 | while (len > 0) | |
735 | { | |
736 | if (argreg > ARGN_REGNUM) | |
737 | { | |
738 | /* must go on the stack */ | |
739 | write_memory (sp + stack_offset, val, 4); | |
740 | stack_offset += 4; | |
741 | } | |
742 | else if (argreg <= ARGN_REGNUM) | |
743 | { | |
744 | /* there's room in a register */ | |
745 | regval = | |
7e3dd49e AC |
746 | extract_unsigned_integer (val, |
747 | register_size (gdbarch, argreg)); | |
d95a8903 AC |
748 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
749 | } | |
750 | ||
751 | /* Store the value 4 bytes at a time. This means that things | |
752 | larger than 4 bytes may go partly in registers and partly | |
753 | on the stack. */ | |
7e3dd49e AC |
754 | len -= register_size (gdbarch, argreg); |
755 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
756 | } |
757 | } | |
758 | ||
759 | /* Finally, update the SP register. */ | |
760 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
761 | ||
762 | return sp; | |
763 | } | |
764 | ||
765 | ||
766 | /* Given a return value in `regbuf' with a type `valtype', | |
767 | extract and copy its value into `valbuf'. */ | |
768 | ||
769 | static void | |
770 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
771 | void *dst) | |
772 | { | |
773 | bfd_byte *valbuf = dst; | |
774 | int len = TYPE_LENGTH (type); | |
775 | ULONGEST tmp; | |
776 | ||
777 | /* By using store_unsigned_integer we avoid having to do | |
778 | anything special for small big-endian values. */ | |
779 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
780 | store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp); | |
781 | ||
782 | /* Ignore return values more than 8 bytes in size because the m32r | |
783 | returns anything more than 8 bytes in the stack. */ | |
784 | if (len > 4) | |
785 | { | |
786 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
787 | store_unsigned_integer (valbuf + len - 4, 4, tmp); | |
788 | } | |
789 | } | |
790 | ||
14588880 KI |
791 | enum return_value_convention |
792 | m32r_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
793 | struct regcache *regcache, void *readbuf, | |
794 | const void *writebuf) | |
795 | { | |
796 | if (TYPE_LENGTH (valtype) > 8) | |
797 | return RETURN_VALUE_STRUCT_CONVENTION; | |
798 | else | |
799 | { | |
800 | if (readbuf != NULL) | |
801 | m32r_extract_return_value (valtype, regcache, readbuf); | |
802 | if (writebuf != NULL) | |
803 | m32r_store_return_value (valtype, regcache, writebuf); | |
804 | return RETURN_VALUE_REGISTER_CONVENTION; | |
805 | } | |
806 | } | |
807 | ||
808 | ||
d95a8903 AC |
809 | |
810 | static CORE_ADDR | |
811 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
812 | { | |
7e3dd49e | 813 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
814 | } |
815 | ||
816 | /* Given a GDB frame, determine the address of the calling function's | |
817 | frame. This will be used to create a new GDB frame struct. */ | |
818 | ||
819 | static void | |
820 | m32r_frame_this_id (struct frame_info *next_frame, | |
821 | void **this_prologue_cache, struct frame_id *this_id) | |
822 | { | |
823 | struct m32r_unwind_cache *info | |
824 | = m32r_frame_unwind_cache (next_frame, this_prologue_cache); | |
825 | CORE_ADDR base; | |
826 | CORE_ADDR func; | |
827 | struct minimal_symbol *msym_stack; | |
828 | struct frame_id id; | |
829 | ||
830 | /* The FUNC is easy. */ | |
831 | func = frame_func_unwind (next_frame); | |
832 | ||
d95a8903 AC |
833 | /* Check if the stack is empty. */ |
834 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
835 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
836 | return; | |
837 | ||
838 | /* Hopefully the prologue analysis either correctly determined the | |
839 | frame's base (which is the SP from the previous frame), or set | |
840 | that base to "NULL". */ | |
841 | base = info->prev_sp; | |
842 | if (base == 0) | |
843 | return; | |
844 | ||
845 | id = frame_id_build (base, func); | |
d95a8903 AC |
846 | (*this_id) = id; |
847 | } | |
848 | ||
849 | static void | |
850 | m32r_frame_prev_register (struct frame_info *next_frame, | |
851 | void **this_prologue_cache, | |
852 | int regnum, int *optimizedp, | |
853 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
854 | int *realnump, void *bufferp) | |
855 | { | |
856 | struct m32r_unwind_cache *info | |
857 | = m32r_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
858 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
859 | optimizedp, lvalp, addrp, realnump, bufferp); | |
d95a8903 AC |
860 | } |
861 | ||
862 | static const struct frame_unwind m32r_frame_unwind = { | |
863 | NORMAL_FRAME, | |
864 | m32r_frame_this_id, | |
865 | m32r_frame_prev_register | |
866 | }; | |
867 | ||
868 | static const struct frame_unwind * | |
7e3dd49e | 869 | m32r_frame_sniffer (struct frame_info *next_frame) |
d95a8903 AC |
870 | { |
871 | return &m32r_frame_unwind; | |
872 | } | |
873 | ||
874 | static CORE_ADDR | |
875 | m32r_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
876 | { | |
877 | struct m32r_unwind_cache *info | |
878 | = m32r_frame_unwind_cache (next_frame, this_cache); | |
879 | return info->base; | |
880 | } | |
881 | ||
882 | static const struct frame_base m32r_frame_base = { | |
883 | &m32r_frame_unwind, | |
884 | m32r_frame_base_address, | |
885 | m32r_frame_base_address, | |
886 | m32r_frame_base_address | |
887 | }; | |
888 | ||
889 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
890 | dummy frame. The frame ID's base needs to match the TOS value | |
891 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
892 | breakpoint. */ | |
893 | ||
894 | static struct frame_id | |
895 | m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
896 | { | |
897 | return frame_id_build (m32r_unwind_sp (gdbarch, next_frame), | |
898 | frame_pc_unwind (next_frame)); | |
899 | } | |
900 | ||
901 | ||
902 | static gdbarch_init_ftype m32r_gdbarch_init; | |
903 | ||
904 | static struct gdbarch * | |
905 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
906 | { | |
907 | struct gdbarch *gdbarch; | |
908 | struct gdbarch_tdep *tdep; | |
909 | ||
910 | /* If there is already a candidate, use it. */ | |
911 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
912 | if (arches != NULL) | |
913 | return arches->gdbarch; | |
914 | ||
915 | /* Allocate space for the new architecture. */ | |
916 | tdep = XMALLOC (struct gdbarch_tdep); | |
917 | gdbarch = gdbarch_alloc (&info, tdep); | |
918 | ||
919 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
920 | set_gdbarch_write_pc (gdbarch, m32r_write_pc); | |
921 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); | |
922 | ||
9b32d526 | 923 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d95a8903 AC |
924 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
925 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
926 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
927 | ||
d95a8903 | 928 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 929 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
930 | |
931 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
932 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d95a8903 AC |
933 | set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); |
934 | set_gdbarch_memory_insert_breakpoint (gdbarch, | |
935 | m32r_memory_insert_breakpoint); | |
936 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
937 | m32r_memory_remove_breakpoint); | |
938 | ||
d95a8903 AC |
939 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
940 | ||
7e3dd49e | 941 | frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer); |
d95a8903 AC |
942 | frame_base_set_default (gdbarch, &m32r_frame_base); |
943 | ||
944 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
945 | stack address must match the SP value returned by | |
946 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
947 | set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id); | |
948 | ||
949 | /* Return the unwound PC value. */ | |
950 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
951 | ||
952 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
953 | ||
954 | return gdbarch; | |
955 | } | |
956 | ||
957 | void | |
958 | _initialize_m32r_tdep (void) | |
959 | { | |
960 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
961 | } |