Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
618f726f | 3 | Copyright (C) 1996-2016 Free Software Foundation, Inc. |
d95a8903 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 AC |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcmd.h" | |
27 | #include "gdbcore.h" | |
d95a8903 AC |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
c46b0409 | 32 | #include "osabi.h" |
d95a8903 AC |
33 | #include "language.h" |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
73e8eb51 | 37 | #include "dis-asm.h" |
77e371c0 | 38 | #include "objfiles.h" |
9b32d526 | 39 | #include "m32r-tdep.h" |
325fac50 | 40 | #include <algorithm> |
d95a8903 AC |
41 | |
42 | /* Local functions */ | |
43 | ||
44 | extern void _initialize_m32r_tdep (void); | |
45 | ||
46 | static CORE_ADDR | |
47 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
48 | { | |
49 | /* Align to the size of an instruction (so that they can safely be | |
50 | pushed onto the stack. */ | |
51 | return sp & ~3; | |
52 | } | |
53 | ||
d95a8903 | 54 | |
9f0b0322 KI |
55 | /* Breakpoints |
56 | ||
025bb325 | 57 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
58 | two 16-bit instructions, A and B, are placed as the following: |
59 | ||
60 | Big endian: | |
61 | A0 A1 B0 B1 | |
62 | ||
63 | Little endian: | |
64 | A1 A0 B1 B0 | |
65 | ||
66 | In M32R, they are placed like this: | |
67 | ||
68 | Big endian: | |
69 | A0 A1 B0 B1 | |
70 | ||
71 | Little endian: | |
72 | B1 B0 A1 A0 | |
73 | ||
74 | This is because M32R always fetches instructions in 32-bit. | |
75 | ||
025bb325 | 76 | The following functions take care of this behavior. */ |
d95a8903 AC |
77 | |
78 | static int | |
ae4b2284 MD |
79 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
80 | struct bp_target_info *bp_tgt) | |
d95a8903 | 81 | { |
0d5ed153 | 82 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
d95a8903 | 83 | int val; |
16ac4ab5 | 84 | gdb_byte buf[4]; |
35c63cd8 | 85 | gdb_byte contents_cache[4]; |
16ac4ab5 | 86 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
87 | |
88 | /* Save the memory contents. */ | |
9f0b0322 | 89 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
90 | if (val != 0) |
91 | return val; /* return error */ | |
92 | ||
35c63cd8 | 93 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
8181d85f DJ |
94 | bp_tgt->placed_size = bp_tgt->shadow_len = 4; |
95 | ||
d95a8903 | 96 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 97 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 98 | { |
9f0b0322 | 99 | if ((addr & 3) == 0) |
d95a8903 | 100 | { |
9f0b0322 KI |
101 | buf[0] = bp_entry[0]; |
102 | buf[1] = bp_entry[1]; | |
103 | buf[2] = contents_cache[2] & 0x7f; | |
104 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
105 | } |
106 | else | |
107 | { | |
9f0b0322 KI |
108 | buf[0] = contents_cache[0]; |
109 | buf[1] = contents_cache[1]; | |
110 | buf[2] = bp_entry[0]; | |
111 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
112 | } |
113 | } | |
9f0b0322 KI |
114 | else /* little-endian */ |
115 | { | |
116 | if ((addr & 3) == 0) | |
d95a8903 | 117 | { |
9f0b0322 KI |
118 | buf[0] = contents_cache[0]; |
119 | buf[1] = contents_cache[1] & 0x7f; | |
120 | buf[2] = bp_entry[1]; | |
121 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
122 | } |
123 | else | |
124 | { | |
9f0b0322 KI |
125 | buf[0] = bp_entry[1]; |
126 | buf[1] = bp_entry[0]; | |
127 | buf[2] = contents_cache[2]; | |
128 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
129 | } |
130 | } | |
131 | ||
132 | /* Write the breakpoint. */ | |
9f0b0322 | 133 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
134 | return val; |
135 | } | |
136 | ||
137 | static int | |
ae4b2284 MD |
138 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
139 | struct bp_target_info *bp_tgt) | |
d95a8903 | 140 | { |
8181d85f | 141 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 142 | int val; |
16ac4ab5 | 143 | gdb_byte buf[4]; |
8181d85f | 144 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 145 | |
9f0b0322 KI |
146 | buf[0] = contents_cache[0]; |
147 | buf[1] = contents_cache[1]; | |
148 | buf[2] = contents_cache[2]; | |
149 | buf[3] = contents_cache[3]; | |
150 | ||
151 | /* Remove parallel bit. */ | |
ae4b2284 | 152 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 153 | { |
9f0b0322 KI |
154 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
155 | buf[2] &= 0x7f; | |
d95a8903 | 156 | } |
9f0b0322 | 157 | else /* little-endian */ |
d95a8903 | 158 | { |
9f0b0322 KI |
159 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
160 | buf[1] &= 0x7f; | |
d95a8903 AC |
161 | } |
162 | ||
163 | /* Write contents. */ | |
dd110abf | 164 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
165 | return val; |
166 | } | |
167 | ||
d19280ad YQ |
168 | static int |
169 | m32r_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
170 | { | |
171 | if ((*pcptr & 3) == 0) | |
172 | return 4; | |
173 | else | |
174 | return 2; | |
175 | } | |
176 | ||
16ac4ab5 | 177 | static const gdb_byte * |
d19280ad | 178 | m32r_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
d95a8903 | 179 | { |
025bb325 MS |
180 | static gdb_byte be_bp_entry[] = { |
181 | 0x10, 0xf1, 0x70, 0x00 | |
182 | }; /* dpt -> nop */ | |
183 | static gdb_byte le_bp_entry[] = { | |
184 | 0x00, 0x70, 0xf1, 0x10 | |
185 | }; /* dpt -> nop */ | |
d19280ad YQ |
186 | |
187 | *size = kind; | |
d95a8903 AC |
188 | |
189 | /* Determine appropriate breakpoint. */ | |
67d57894 | 190 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 191 | return be_bp_entry; |
d95a8903 AC |
192 | else |
193 | { | |
d19280ad YQ |
194 | if (kind == 4) |
195 | return le_bp_entry; | |
d95a8903 | 196 | else |
d19280ad | 197 | return le_bp_entry + 2; |
d95a8903 | 198 | } |
d95a8903 AC |
199 | } |
200 | ||
d19280ad | 201 | GDBARCH_BREAKPOINT_FROM_PC (m32r) |
d95a8903 AC |
202 | |
203 | char *m32r_register_names[] = { | |
204 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
205 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
206 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
207 | "evb" | |
208 | }; | |
209 | ||
d95a8903 | 210 | static const char * |
d93859e2 | 211 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 AC |
212 | { |
213 | if (reg_nr < 0) | |
214 | return NULL; | |
9b32d526 | 215 | if (reg_nr >= M32R_NUM_REGS) |
d95a8903 AC |
216 | return NULL; |
217 | return m32r_register_names[reg_nr]; | |
218 | } | |
219 | ||
220 | ||
221 | /* Return the GDB type object for the "standard" data type | |
222 | of data in register N. */ | |
223 | ||
224 | static struct type * | |
225 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
226 | { | |
227 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 228 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 229 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 230 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 231 | else |
df4df182 | 232 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
233 | } |
234 | ||
235 | ||
236 | /* Write into appropriate registers a function return value | |
025bb325 | 237 | of type TYPE, given in virtual format. |
d95a8903 | 238 | |
025bb325 | 239 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
240 | |
241 | static void | |
242 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 243 | const gdb_byte *valbuf) |
d95a8903 | 244 | { |
e17a4113 UW |
245 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
246 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
247 | CORE_ADDR regval; |
248 | int len = TYPE_LENGTH (type); | |
249 | ||
e17a4113 | 250 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
251 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
252 | ||
253 | if (len > 4) | |
254 | { | |
7c543f7b | 255 | regval = extract_unsigned_integer (valbuf + 4, |
e17a4113 | 256 | len - 4, byte_order); |
d95a8903 AC |
257 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
258 | } | |
259 | } | |
260 | ||
025bb325 | 261 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
262 | should be cached because this thrashing is getting nuts. */ |
263 | ||
cea15572 | 264 | static int |
e17a4113 UW |
265 | decode_prologue (struct gdbarch *gdbarch, |
266 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 267 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 268 | { |
e17a4113 | 269 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
270 | unsigned long framesize; |
271 | int insn; | |
272 | int op1; | |
d95a8903 | 273 | CORE_ADDR after_prologue = 0; |
cea15572 | 274 | CORE_ADDR after_push = 0; |
d95a8903 AC |
275 | CORE_ADDR after_stack_adjust = 0; |
276 | CORE_ADDR current_pc; | |
cea15572 | 277 | LONGEST return_value; |
d95a8903 AC |
278 | |
279 | framesize = 0; | |
280 | after_prologue = 0; | |
281 | ||
282 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
283 | { | |
025bb325 | 284 | /* Check if current pc's location is readable. */ |
e17a4113 | 285 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
286 | return -1; |
287 | ||
e17a4113 | 288 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 289 | |
cea15572 KI |
290 | if (insn == 0x0000) |
291 | break; | |
292 | ||
d95a8903 | 293 | /* If this is a 32 bit instruction, we dont want to examine its |
025bb325 | 294 | immediate data as though it were an instruction. */ |
d95a8903 AC |
295 | if (current_pc & 0x02) |
296 | { | |
025bb325 | 297 | /* Decode this instruction further. */ |
d95a8903 AC |
298 | insn &= 0x7fff; |
299 | } | |
300 | else | |
301 | { | |
d95a8903 AC |
302 | if (insn & 0x8000) |
303 | { | |
304 | if (current_pc == scan_limit) | |
305 | scan_limit += 2; /* extend the search */ | |
cea15572 | 306 | |
d95a8903 | 307 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 308 | |
025bb325 | 309 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
310 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
311 | &return_value)) | |
cea15572 KI |
312 | return -1; |
313 | ||
d95a8903 AC |
314 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
315 | /* add 16 bit sign-extended offset */ | |
316 | { | |
317 | framesize += | |
e17a4113 UW |
318 | -((short) read_memory_unsigned_integer (current_pc, |
319 | 2, byte_order)); | |
d95a8903 AC |
320 | } |
321 | else | |
322 | { | |
025bb325 | 323 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
324 | && safe_read_memory_integer (current_pc + 2, |
325 | 2, byte_order, | |
cea15572 | 326 | &return_value) |
7e3dd49e | 327 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
328 | 2, byte_order) |
329 | == 0x0f24) | |
d95a8903 | 330 | { |
025bb325 | 331 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
332 | insn = read_memory_unsigned_integer (current_pc - 2, |
333 | 4, byte_order); | |
d95a8903 AC |
334 | if (insn & 0x00800000) /* sign extend */ |
335 | insn |= 0xff000000; /* negative */ | |
336 | else | |
337 | insn &= 0x00ffffff; /* positive */ | |
338 | framesize += insn; | |
339 | } | |
340 | } | |
cea15572 | 341 | after_push = current_pc + 2; |
d95a8903 AC |
342 | continue; |
343 | } | |
344 | } | |
025bb325 | 345 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
346 | |
347 | if ((insn & 0xf0ff) == 0x207f) | |
348 | { /* st reg, @-sp */ | |
d95a8903 | 349 | framesize += 4; |
d95a8903 AC |
350 | after_prologue = 0; |
351 | continue; | |
352 | } | |
353 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 354 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 355 | { |
9ffbf372 | 356 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
357 | |
358 | /* there are probably two of these stack adjustments: | |
359 | 1) A negative one in the prologue, and | |
360 | 2) A positive one in the epilogue. | |
361 | We are only interested in the first one. */ | |
362 | ||
363 | if (stack_adjust < 0) | |
364 | { | |
365 | framesize -= stack_adjust; | |
366 | after_prologue = 0; | |
367 | /* A frameless function may have no "mv fp, sp". | |
368 | In that case, this is the end of the prologue. */ | |
369 | after_stack_adjust = current_pc + 2; | |
370 | } | |
371 | continue; | |
372 | } | |
373 | if (insn == 0x1d8f) | |
374 | { /* mv fp, sp */ | |
375 | after_prologue = current_pc + 2; | |
376 | break; /* end of stack adjustments */ | |
377 | } | |
cea15572 | 378 | |
025bb325 | 379 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
380 | if (insn == 0x7000) |
381 | { | |
382 | after_prologue = current_pc + 2; | |
025bb325 | 383 | continue; /* nop occurs between pushes. */ |
d95a8903 | 384 | } |
025bb325 | 385 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
386 | if ((insn & 0xfff0) == 0x10f0) |
387 | { | |
388 | after_prologue = current_pc; | |
389 | break; | |
390 | } | |
025bb325 | 391 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
392 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
393 | { | |
394 | after_prologue = current_pc; | |
d95a8903 AC |
395 | continue; |
396 | } | |
025bb325 | 397 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
398 | if (op1 == 0x1000) |
399 | { | |
400 | int subop = insn & 0x0ff0; | |
401 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
402 | { | |
403 | after_prologue = current_pc; | |
d95a8903 AC |
404 | continue; /* jmp , jl */ |
405 | } | |
406 | } | |
407 | } | |
408 | ||
cea15572 KI |
409 | if (framelength) |
410 | *framelength = framesize; | |
411 | ||
d95a8903 AC |
412 | if (current_pc >= scan_limit) |
413 | { | |
414 | if (pl_endptr) | |
415 | { | |
416 | if (after_stack_adjust != 0) | |
417 | /* We did not find a "mv fp,sp", but we DID find | |
418 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 419 | end of the prologue? I just don't know. */ |
d95a8903 AC |
420 | { |
421 | *pl_endptr = after_stack_adjust; | |
422 | } | |
cea15572 KI |
423 | else if (after_push != 0) |
424 | /* We did not find a "mv fp,sp", but we DID find | |
425 | a push. Is it safe to use that as the | |
025bb325 | 426 | end of the prologue? I just don't know. */ |
cea15572 KI |
427 | { |
428 | *pl_endptr = after_push; | |
429 | } | |
d95a8903 AC |
430 | else |
431 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
432 | of the prologue. No way to win -- we should report |
433 | failure. The way we do that is to return the original | |
434 | start_pc. GDB will set a breakpoint at the start of | |
435 | the function (etc.) */ | |
d95a8903 AC |
436 | *pl_endptr = start_pc; |
437 | } | |
cea15572 | 438 | return 0; |
d95a8903 | 439 | } |
cea15572 | 440 | |
d95a8903 AC |
441 | if (after_prologue == 0) |
442 | after_prologue = current_pc; | |
443 | ||
444 | if (pl_endptr) | |
445 | *pl_endptr = after_prologue; | |
cea15572 KI |
446 | |
447 | return 0; | |
d95a8903 AC |
448 | } /* decode_prologue */ |
449 | ||
450 | /* Function: skip_prologue | |
025bb325 | 451 | Find end of function prologue. */ |
d95a8903 | 452 | |
cea15572 | 453 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 454 | |
63807e1d | 455 | static CORE_ADDR |
6093d2eb | 456 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 457 | { |
e17a4113 | 458 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
459 | CORE_ADDR func_addr, func_end; |
460 | struct symtab_and_line sal; | |
cea15572 | 461 | LONGEST return_value; |
d95a8903 | 462 | |
025bb325 | 463 | /* See what the symbol table says. */ |
d95a8903 AC |
464 | |
465 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
466 | { | |
467 | sal = find_pc_line (func_addr, 0); | |
468 | ||
469 | if (sal.line != 0 && sal.end <= func_end) | |
470 | { | |
471 | func_end = sal.end; | |
472 | } | |
473 | else | |
474 | /* Either there's no line info, or the line after the prologue is after | |
475 | the end of the function. In this case, there probably isn't a | |
476 | prologue. */ | |
477 | { | |
325fac50 | 478 | func_end = std::min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); |
d95a8903 AC |
479 | } |
480 | } | |
481 | else | |
482 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 483 | |
025bb325 | 484 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 485 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
486 | return pc; |
487 | ||
488 | /* Find the end of prologue. */ | |
e17a4113 | 489 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
490 | return pc; |
491 | ||
d95a8903 AC |
492 | return sal.end; |
493 | } | |
494 | ||
d95a8903 AC |
495 | struct m32r_unwind_cache |
496 | { | |
497 | /* The previous frame's inner most stack address. Used as this | |
498 | frame ID's stack_addr. */ | |
499 | CORE_ADDR prev_sp; | |
500 | /* The frame's base, optionally used by the high-level debug info. */ | |
501 | CORE_ADDR base; | |
502 | int size; | |
503 | /* How far the SP and r13 (FP) have been offset from the start of | |
504 | the stack frame (as defined by the previous frame's stack | |
505 | pointer). */ | |
506 | LONGEST sp_offset; | |
507 | LONGEST r13_offset; | |
508 | int uses_frame; | |
509 | /* Table indicating the location of each and every register. */ | |
510 | struct trad_frame_saved_reg *saved_regs; | |
511 | }; | |
512 | ||
513 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
514 | the saved registers of frame described by FRAME_INFO. This | |
515 | includes special registers such as pc and fp saved in special ways | |
516 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 517 | for it IS the sp for the next frame. */ |
d95a8903 AC |
518 | |
519 | static struct m32r_unwind_cache * | |
94afd7a6 | 520 | m32r_frame_unwind_cache (struct frame_info *this_frame, |
d95a8903 AC |
521 | void **this_prologue_cache) |
522 | { | |
cea15572 | 523 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
524 | ULONGEST prev_sp; |
525 | ULONGEST this_base; | |
22e048c9 | 526 | unsigned long op; |
d95a8903 AC |
527 | int i; |
528 | struct m32r_unwind_cache *info; | |
529 | ||
cea15572 | 530 | |
d95a8903 | 531 | if ((*this_prologue_cache)) |
9a3c8263 | 532 | return (struct m32r_unwind_cache *) (*this_prologue_cache); |
d95a8903 AC |
533 | |
534 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
535 | (*this_prologue_cache) = info; | |
94afd7a6 | 536 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
537 | |
538 | info->size = 0; | |
539 | info->sp_offset = 0; | |
d95a8903 | 540 | info->uses_frame = 0; |
cea15572 | 541 | |
94afd7a6 UW |
542 | scan_limit = get_frame_pc (this_frame); |
543 | for (pc = get_frame_func (this_frame); | |
cea15572 | 544 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
545 | { |
546 | if ((pc & 2) == 0) | |
547 | { | |
94afd7a6 | 548 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
549 | if ((op & 0x80000000) == 0x80000000) |
550 | { | |
551 | /* 32-bit instruction */ | |
552 | if ((op & 0xffff0000) == 0x8faf0000) | |
553 | { | |
554 | /* add3 sp,sp,xxxx */ | |
555 | short n = op & 0xffff; | |
556 | info->sp_offset += n; | |
557 | } | |
cea15572 | 558 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 559 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 560 | 2) == 0x0f24) |
d95a8903 | 561 | { |
cea15572 | 562 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
563 | unsigned long n = op & 0xffffff; |
564 | info->sp_offset += n; | |
cea15572 | 565 | pc += 2; /* skip sub instruction */ |
d95a8903 | 566 | } |
d95a8903 | 567 | |
cea15572 KI |
568 | if (pc == scan_limit) |
569 | scan_limit += 2; /* extend the search */ | |
570 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
571 | continue; |
572 | } | |
573 | } | |
574 | ||
575 | /* 16-bit instructions */ | |
94afd7a6 | 576 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
577 | if ((op & 0xf0ff) == 0x207f) |
578 | { | |
579 | /* st rn, @-sp */ | |
580 | int regno = ((op >> 8) & 0xf); | |
581 | info->sp_offset -= 4; | |
582 | info->saved_regs[regno].addr = info->sp_offset; | |
583 | } | |
584 | else if ((op & 0xff00) == 0x4f00) | |
585 | { | |
586 | /* addi sp, xx */ | |
9ffbf372 | 587 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
588 | info->sp_offset += n; |
589 | } | |
590 | else if (op == 0x1d8f) | |
591 | { | |
592 | /* mv fp, sp */ | |
593 | info->uses_frame = 1; | |
594 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
595 | break; /* end of stack adjustments */ |
596 | } | |
597 | else if ((op & 0xfff0) == 0x10f0) | |
598 | { | |
025bb325 MS |
599 | /* End of prologue if this is a trap instruction. */ |
600 | break; /* End of stack adjustments. */ | |
d95a8903 | 601 | } |
d95a8903 AC |
602 | } |
603 | ||
604 | info->size = -info->sp_offset; | |
605 | ||
606 | /* Compute the previous frame's stack pointer (which is also the | |
607 | frame's ID's stack address), and this frame's base pointer. */ | |
608 | if (info->uses_frame) | |
609 | { | |
610 | /* The SP was moved to the FP. This indicates that a new frame | |
611 | was created. Get THIS frame's FP value by unwinding it from | |
612 | the next frame. */ | |
94afd7a6 | 613 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 AC |
614 | /* The FP points at the last saved register. Adjust the FP back |
615 | to before the first saved register giving the SP. */ | |
616 | prev_sp = this_base + info->size; | |
617 | } | |
618 | else | |
619 | { | |
620 | /* Assume that the FP is this frame's SP but with that pushed | |
621 | stack space added back. */ | |
94afd7a6 | 622 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
623 | prev_sp = this_base + info->size; |
624 | } | |
625 | ||
626 | /* Convert that SP/BASE into real addresses. */ | |
627 | info->prev_sp = prev_sp; | |
628 | info->base = this_base; | |
629 | ||
630 | /* Adjust all the saved registers so that they contain addresses and | |
631 | not offsets. */ | |
94afd7a6 | 632 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
d95a8903 AC |
633 | if (trad_frame_addr_p (info->saved_regs, i)) |
634 | info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); | |
635 | ||
636 | /* The call instruction moves the caller's PC in the callee's LR. | |
637 | Since this is an unwind, do the reverse. Copy the location of LR | |
638 | into PC (the address / regnum) so that a request for PC will be | |
639 | converted into a request for the LR. */ | |
640 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
641 | ||
642 | /* The previous frame's SP needed to be computed. Save the computed | |
643 | value. */ | |
644 | trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); | |
645 | ||
646 | return info; | |
647 | } | |
648 | ||
649 | static CORE_ADDR | |
61a1198a | 650 | m32r_read_pc (struct regcache *regcache) |
d95a8903 | 651 | { |
7e3dd49e | 652 | ULONGEST pc; |
61a1198a | 653 | regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); |
d95a8903 AC |
654 | return pc; |
655 | } | |
656 | ||
d95a8903 AC |
657 | static CORE_ADDR |
658 | m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
659 | { | |
7e3dd49e | 660 | return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); |
d95a8903 AC |
661 | } |
662 | ||
663 | ||
664 | static CORE_ADDR | |
7d9b040b | 665 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 AC |
666 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
667 | struct value **args, CORE_ADDR sp, int struct_return, | |
668 | CORE_ADDR struct_addr) | |
669 | { | |
e17a4113 | 670 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
671 | int stack_offset, stack_alloc; |
672 | int argreg = ARG1_REGNUM; | |
673 | int argnum; | |
674 | struct type *type; | |
675 | enum type_code typecode; | |
676 | CORE_ADDR regval; | |
16ac4ab5 KI |
677 | gdb_byte *val; |
678 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
d95a8903 | 679 | int len; |
d95a8903 | 680 | |
025bb325 | 681 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
682 | sp = sp & ~3; |
683 | ||
684 | /* Set the return address. For the m32r, the return breakpoint is | |
685 | always at BP_ADDR. */ | |
686 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
687 | ||
688 | /* If STRUCT_RETURN is true, then the struct return address (in | |
689 | STRUCT_ADDR) will consume the first argument-passing register. | |
690 | Both adjust the register count and store that value. */ | |
691 | if (struct_return) | |
692 | { | |
693 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
694 | argreg++; | |
695 | } | |
696 | ||
025bb325 | 697 | /* Now make sure there's space on the stack. */ |
d95a8903 | 698 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 699 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); |
025bb325 | 700 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
701 | |
702 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
703 | { | |
4991999e | 704 | type = value_type (args[argnum]); |
d95a8903 AC |
705 | typecode = TYPE_CODE (type); |
706 | len = TYPE_LENGTH (type); | |
707 | ||
708 | memset (valbuf, 0, sizeof (valbuf)); | |
709 | ||
710 | /* Passes structures that do not fit in 2 registers by reference. */ | |
711 | if (len > 8 | |
712 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
713 | { | |
e17a4113 UW |
714 | store_unsigned_integer (valbuf, 4, byte_order, |
715 | value_address (args[argnum])); | |
d95a8903 AC |
716 | typecode = TYPE_CODE_PTR; |
717 | len = 4; | |
718 | val = valbuf; | |
719 | } | |
720 | else if (len < 4) | |
721 | { | |
025bb325 | 722 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 723 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
16ac4ab5 | 724 | (gdb_byte *) value_contents (args[argnum]), len); |
d95a8903 AC |
725 | val = valbuf; |
726 | } | |
727 | else | |
16ac4ab5 | 728 | val = (gdb_byte *) value_contents (args[argnum]); |
d95a8903 AC |
729 | |
730 | while (len > 0) | |
731 | { | |
732 | if (argreg > ARGN_REGNUM) | |
733 | { | |
025bb325 | 734 | /* Must go on the stack. */ |
d95a8903 AC |
735 | write_memory (sp + stack_offset, val, 4); |
736 | stack_offset += 4; | |
737 | } | |
738 | else if (argreg <= ARGN_REGNUM) | |
739 | { | |
025bb325 | 740 | /* There's room in a register. */ |
d95a8903 | 741 | regval = |
7e3dd49e | 742 | extract_unsigned_integer (val, |
e17a4113 UW |
743 | register_size (gdbarch, argreg), |
744 | byte_order); | |
d95a8903 AC |
745 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
746 | } | |
747 | ||
748 | /* Store the value 4 bytes at a time. This means that things | |
749 | larger than 4 bytes may go partly in registers and partly | |
750 | on the stack. */ | |
7e3dd49e AC |
751 | len -= register_size (gdbarch, argreg); |
752 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
753 | } |
754 | } | |
755 | ||
756 | /* Finally, update the SP register. */ | |
757 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
758 | ||
759 | return sp; | |
760 | } | |
761 | ||
762 | ||
763 | /* Given a return value in `regbuf' with a type `valtype', | |
764 | extract and copy its value into `valbuf'. */ | |
765 | ||
766 | static void | |
767 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 768 | gdb_byte *dst) |
d95a8903 | 769 | { |
e17a4113 UW |
770 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
771 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d95a8903 AC |
772 | int len = TYPE_LENGTH (type); |
773 | ULONGEST tmp; | |
774 | ||
775 | /* By using store_unsigned_integer we avoid having to do | |
776 | anything special for small big-endian values. */ | |
777 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 778 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
779 | |
780 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 781 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
782 | if (len > 4) |
783 | { | |
784 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 785 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
786 | } |
787 | } | |
788 | ||
63807e1d | 789 | static enum return_value_convention |
6a3a010b | 790 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
791 | struct type *valtype, struct regcache *regcache, |
792 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 KI |
793 | { |
794 | if (TYPE_LENGTH (valtype) > 8) | |
795 | return RETURN_VALUE_STRUCT_CONVENTION; | |
796 | else | |
797 | { | |
798 | if (readbuf != NULL) | |
799 | m32r_extract_return_value (valtype, regcache, readbuf); | |
800 | if (writebuf != NULL) | |
801 | m32r_store_return_value (valtype, regcache, writebuf); | |
802 | return RETURN_VALUE_REGISTER_CONVENTION; | |
803 | } | |
804 | } | |
805 | ||
806 | ||
d95a8903 AC |
807 | |
808 | static CORE_ADDR | |
809 | m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
810 | { | |
7e3dd49e | 811 | return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); |
d95a8903 AC |
812 | } |
813 | ||
814 | /* Given a GDB frame, determine the address of the calling function's | |
815 | frame. This will be used to create a new GDB frame struct. */ | |
816 | ||
817 | static void | |
94afd7a6 | 818 | m32r_frame_this_id (struct frame_info *this_frame, |
d95a8903 AC |
819 | void **this_prologue_cache, struct frame_id *this_id) |
820 | { | |
821 | struct m32r_unwind_cache *info | |
94afd7a6 | 822 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
823 | CORE_ADDR base; |
824 | CORE_ADDR func; | |
3b7344d5 | 825 | struct bound_minimal_symbol msym_stack; |
d95a8903 AC |
826 | struct frame_id id; |
827 | ||
828 | /* The FUNC is easy. */ | |
94afd7a6 | 829 | func = get_frame_func (this_frame); |
d95a8903 | 830 | |
d95a8903 AC |
831 | /* Check if the stack is empty. */ |
832 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
77e371c0 | 833 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) |
d95a8903 AC |
834 | return; |
835 | ||
836 | /* Hopefully the prologue analysis either correctly determined the | |
837 | frame's base (which is the SP from the previous frame), or set | |
838 | that base to "NULL". */ | |
839 | base = info->prev_sp; | |
840 | if (base == 0) | |
841 | return; | |
842 | ||
843 | id = frame_id_build (base, func); | |
d95a8903 AC |
844 | (*this_id) = id; |
845 | } | |
846 | ||
94afd7a6 UW |
847 | static struct value * |
848 | m32r_frame_prev_register (struct frame_info *this_frame, | |
849 | void **this_prologue_cache, int regnum) | |
d95a8903 AC |
850 | { |
851 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
852 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
853 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
854 | } |
855 | ||
856 | static const struct frame_unwind m32r_frame_unwind = { | |
857 | NORMAL_FRAME, | |
8fbca658 | 858 | default_frame_unwind_stop_reason, |
d95a8903 | 859 | m32r_frame_this_id, |
94afd7a6 UW |
860 | m32r_frame_prev_register, |
861 | NULL, | |
862 | default_frame_sniffer | |
d95a8903 AC |
863 | }; |
864 | ||
d95a8903 | 865 | static CORE_ADDR |
94afd7a6 | 866 | m32r_frame_base_address (struct frame_info *this_frame, void **this_cache) |
d95a8903 AC |
867 | { |
868 | struct m32r_unwind_cache *info | |
94afd7a6 | 869 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
870 | return info->base; |
871 | } | |
872 | ||
873 | static const struct frame_base m32r_frame_base = { | |
874 | &m32r_frame_unwind, | |
875 | m32r_frame_base_address, | |
876 | m32r_frame_base_address, | |
877 | m32r_frame_base_address | |
878 | }; | |
879 | ||
94afd7a6 UW |
880 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
881 | frame. The frame ID's base needs to match the TOS value saved by | |
882 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
d95a8903 AC |
883 | |
884 | static struct frame_id | |
94afd7a6 | 885 | m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
d95a8903 | 886 | { |
94afd7a6 UW |
887 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
888 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
d95a8903 AC |
889 | } |
890 | ||
891 | ||
892 | static gdbarch_init_ftype m32r_gdbarch_init; | |
893 | ||
894 | static struct gdbarch * | |
895 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
896 | { | |
897 | struct gdbarch *gdbarch; | |
898 | struct gdbarch_tdep *tdep; | |
899 | ||
900 | /* If there is already a candidate, use it. */ | |
901 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
902 | if (arches != NULL) | |
903 | return arches->gdbarch; | |
904 | ||
905 | /* Allocate space for the new architecture. */ | |
70ba0933 | 906 | tdep = XNEW (struct gdbarch_tdep); |
d95a8903 AC |
907 | gdbarch = gdbarch_alloc (&info, tdep); |
908 | ||
909 | set_gdbarch_read_pc (gdbarch, m32r_read_pc); | |
d95a8903 AC |
910 | set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); |
911 | ||
e839132d | 912 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d27b54ad | 913 | set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM); |
d95a8903 AC |
914 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
915 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
916 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
917 | ||
d95a8903 | 918 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 919 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
920 | |
921 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
922 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
d19280ad | 923 | SET_GDBARCH_BREAKPOINT_MANIPULATION (m32r); |
d95a8903 AC |
924 | set_gdbarch_memory_insert_breakpoint (gdbarch, |
925 | m32r_memory_insert_breakpoint); | |
926 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
927 | m32r_memory_remove_breakpoint); | |
928 | ||
d95a8903 AC |
929 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
930 | ||
d95a8903 AC |
931 | frame_base_set_default (gdbarch, &m32r_frame_base); |
932 | ||
933 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
934 | stack address must match the SP value returned by | |
935 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 936 | set_gdbarch_dummy_id (gdbarch, m32r_dummy_id); |
d95a8903 AC |
937 | |
938 | /* Return the unwound PC value. */ | |
939 | set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); | |
940 | ||
941 | set_gdbarch_print_insn (gdbarch, print_insn_m32r); | |
942 | ||
c46b0409 KI |
943 | /* Hook in ABI-specific overrides, if they have been registered. */ |
944 | gdbarch_init_osabi (info, gdbarch); | |
945 | ||
946 | /* Hook in the default unwinders. */ | |
94afd7a6 | 947 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 948 | |
1c772458 UW |
949 | /* Support simple overlay manager. */ |
950 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
951 | ||
d95a8903 AC |
952 | return gdbarch; |
953 | } | |
954 | ||
955 | void | |
956 | _initialize_m32r_tdep (void) | |
957 | { | |
958 | register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); | |
959 | } |