Commit | Line | Data |
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908f682f | 1 | /* Target-dependent code for Motorola 68HC11 & 68HC12 |
51603483 | 2 | Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
ffe1f3ee | 3 | Contributed by Stephane Carrez, stcarrez@nerim.fr |
78073dd8 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
78073dd8 | 21 | |
82c230c2 SC |
22 | #include "defs.h" |
23 | #include "frame.h" | |
1ea653ae SC |
24 | #include "frame-unwind.h" |
25 | #include "frame-base.h" | |
26 | #include "dwarf2-frame.h" | |
27 | #include "trad-frame.h" | |
82c230c2 SC |
28 | #include "symtab.h" |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdb_string.h" | |
33 | #include "value.h" | |
34 | #include "inferior.h" | |
35 | #include "dis-asm.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "arch-utils.h" | |
4e052eda | 39 | #include "regcache.h" |
b631436b | 40 | #include "reggroups.h" |
78073dd8 | 41 | |
82c230c2 SC |
42 | #include "target.h" |
43 | #include "opcode/m68hc11.h" | |
81967506 SC |
44 | #include "elf/m68hc11.h" |
45 | #include "elf-bfd.h" | |
78073dd8 | 46 | |
7df11f59 SC |
47 | /* Macros for setting and testing a bit in a minimal symbol. |
48 | For 68HC11/68HC12 we have two flags that tell which return | |
49 | type the function is using. This is used for prologue and frame | |
50 | analysis to compute correct stack frame layout. | |
51 | ||
52 | The MSB of the minimal symbol's "info" field is used for this purpose. | |
7df11f59 SC |
53 | |
54 | MSYMBOL_SET_RTC Actually sets the "RTC" bit. | |
55 | MSYMBOL_SET_RTI Actually sets the "RTI" bit. | |
56 | MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. | |
f594e5e9 | 57 | MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */ |
7df11f59 SC |
58 | |
59 | #define MSYMBOL_SET_RTC(msym) \ | |
60 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
61 | | 0x80000000) | |
62 | ||
63 | #define MSYMBOL_SET_RTI(msym) \ | |
64 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
65 | | 0x40000000) | |
66 | ||
67 | #define MSYMBOL_IS_RTC(msym) \ | |
68 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
69 | ||
70 | #define MSYMBOL_IS_RTI(msym) \ | |
71 | (((long) MSYMBOL_INFO (msym) & 0x40000000) != 0) | |
72 | ||
7df11f59 SC |
73 | enum insn_return_kind { |
74 | RETURN_RTS, | |
75 | RETURN_RTC, | |
76 | RETURN_RTI | |
77 | }; | |
78 | ||
79 | ||
78073dd8 AC |
80 | /* Register numbers of various important registers. |
81 | Note that some of these values are "real" register numbers, | |
82 | and correspond to the general registers of the machine, | |
83 | and some are "phony" register numbers which are too large | |
84 | to be actual register numbers as far as the user is concerned | |
85 | but do serve to get the desired values when passed to read_register. */ | |
86 | ||
82c230c2 SC |
87 | #define HARD_X_REGNUM 0 |
88 | #define HARD_D_REGNUM 1 | |
89 | #define HARD_Y_REGNUM 2 | |
90 | #define HARD_SP_REGNUM 3 | |
91 | #define HARD_PC_REGNUM 4 | |
92 | ||
93 | #define HARD_A_REGNUM 5 | |
94 | #define HARD_B_REGNUM 6 | |
95 | #define HARD_CCR_REGNUM 7 | |
5706502a SC |
96 | |
97 | /* 68HC12 page number register. | |
98 | Note: to keep a compatibility with gcc register naming, we must | |
99 | not have to rename FP and other soft registers. The page register | |
100 | is a real hard register and must therefore be counted by NUM_REGS. | |
101 | For this it has the same number as Z register (which is not used). */ | |
102 | #define HARD_PAGE_REGNUM 8 | |
103 | #define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) | |
82c230c2 SC |
104 | |
105 | /* Z is replaced by X or Y by gcc during machine reorg. | |
106 | ??? There is no way to get it and even know whether | |
107 | it's in X or Y or in ZS. */ | |
108 | #define SOFT_Z_REGNUM 8 | |
109 | ||
110 | /* Soft registers. These registers are special. There are treated | |
111 | like normal hard registers by gcc and gdb (ie, within dwarf2 info). | |
112 | They are physically located in memory. */ | |
113 | #define SOFT_FP_REGNUM 9 | |
114 | #define SOFT_TMP_REGNUM 10 | |
115 | #define SOFT_ZS_REGNUM 11 | |
116 | #define SOFT_XY_REGNUM 12 | |
f91a8b6b SC |
117 | #define SOFT_UNUSED_REGNUM 13 |
118 | #define SOFT_D1_REGNUM 14 | |
82c230c2 SC |
119 | #define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) |
120 | #define M68HC11_MAX_SOFT_REGS 32 | |
121 | ||
122 | #define M68HC11_NUM_REGS (8) | |
123 | #define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) | |
124 | #define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) | |
125 | ||
126 | #define M68HC11_REG_SIZE (2) | |
127 | ||
548bcbec SC |
128 | #define M68HC12_NUM_REGS (9) |
129 | #define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) | |
130 | #define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) | |
131 | ||
908f682f | 132 | struct insn_sequence; |
82c230c2 SC |
133 | struct gdbarch_tdep |
134 | { | |
5d1a66bd SC |
135 | /* Stack pointer correction value. For 68hc11, the stack pointer points |
136 | to the next push location. An offset of 1 must be applied to obtain | |
137 | the address where the last value is saved. For 68hc12, the stack | |
138 | pointer points to the last value pushed. No offset is necessary. */ | |
139 | int stack_correction; | |
908f682f SC |
140 | |
141 | /* Description of instructions in the prologue. */ | |
142 | struct insn_sequence *prologue; | |
81967506 | 143 | |
7df11f59 SC |
144 | /* True if the page memory bank register is available |
145 | and must be used. */ | |
146 | int use_page_register; | |
147 | ||
81967506 SC |
148 | /* ELF flags for ABI. */ |
149 | int elf_flags; | |
82c230c2 SC |
150 | }; |
151 | ||
5d1a66bd SC |
152 | #define M6811_TDEP gdbarch_tdep (current_gdbarch) |
153 | #define STACK_CORRECTION (M6811_TDEP->stack_correction) | |
7df11f59 | 154 | #define USE_PAGE_REGISTER (M6811_TDEP->use_page_register) |
5d1a66bd | 155 | |
1ea653ae SC |
156 | struct m68hc11_unwind_cache |
157 | { | |
158 | /* The previous frame's inner most stack address. Used as this | |
159 | frame ID's stack_addr. */ | |
160 | CORE_ADDR prev_sp; | |
161 | /* The frame's base, optionally used by the high-level debug info. */ | |
162 | CORE_ADDR base; | |
163 | CORE_ADDR pc; | |
164 | int size; | |
165 | int prologue_type; | |
166 | CORE_ADDR return_pc; | |
167 | CORE_ADDR sp_offset; | |
168 | int frameless; | |
169 | enum insn_return_kind return_kind; | |
170 | ||
171 | /* Table indicating the location of each and every register. */ | |
172 | struct trad_frame_saved_reg *saved_regs; | |
173 | }; | |
174 | ||
82c230c2 SC |
175 | /* Table of registers for 68HC11. This includes the hard registers |
176 | and the soft registers used by GCC. */ | |
177 | static char * | |
178 | m68hc11_register_names[] = | |
179 | { | |
180 | "x", "d", "y", "sp", "pc", "a", "b", | |
5706502a | 181 | "ccr", "page", "frame","tmp", "zs", "xy", 0, |
82c230c2 SC |
182 | "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
183 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", | |
184 | "d15", "d16", "d17", "d18", "d19", "d20", "d21", | |
185 | "d22", "d23", "d24", "d25", "d26", "d27", "d28", | |
186 | "d29", "d30", "d31", "d32" | |
187 | }; | |
78073dd8 | 188 | |
82c230c2 SC |
189 | struct m68hc11_soft_reg |
190 | { | |
191 | const char *name; | |
192 | CORE_ADDR addr; | |
193 | }; | |
78073dd8 | 194 | |
82c230c2 | 195 | static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; |
78073dd8 | 196 | |
82c230c2 | 197 | #define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr |
78073dd8 | 198 | |
82c230c2 SC |
199 | static int soft_min_addr; |
200 | static int soft_max_addr; | |
201 | static int soft_reg_initialized = 0; | |
78073dd8 | 202 | |
82c230c2 SC |
203 | /* Look in the symbol table for the address of a pseudo register |
204 | in memory. If we don't find it, pretend the register is not used | |
205 | and not available. */ | |
206 | static void | |
207 | m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) | |
208 | { | |
209 | struct minimal_symbol *msymbol; | |
78073dd8 | 210 | |
82c230c2 SC |
211 | msymbol = lookup_minimal_symbol (name, NULL, NULL); |
212 | if (msymbol) | |
213 | { | |
214 | reg->addr = SYMBOL_VALUE_ADDRESS (msymbol); | |
215 | reg->name = xstrdup (name); | |
216 | ||
217 | /* Keep track of the address range for soft registers. */ | |
218 | if (reg->addr < (CORE_ADDR) soft_min_addr) | |
219 | soft_min_addr = reg->addr; | |
220 | if (reg->addr > (CORE_ADDR) soft_max_addr) | |
221 | soft_max_addr = reg->addr; | |
222 | } | |
223 | else | |
224 | { | |
225 | reg->name = 0; | |
226 | reg->addr = 0; | |
227 | } | |
228 | } | |
78073dd8 | 229 | |
82c230c2 SC |
230 | /* Initialize the table of soft register addresses according |
231 | to the symbol table. */ | |
232 | static void | |
233 | m68hc11_initialize_register_info (void) | |
234 | { | |
235 | int i; | |
78073dd8 | 236 | |
82c230c2 SC |
237 | if (soft_reg_initialized) |
238 | return; | |
239 | ||
240 | soft_min_addr = INT_MAX; | |
241 | soft_max_addr = 0; | |
242 | for (i = 0; i < M68HC11_ALL_REGS; i++) | |
243 | { | |
244 | soft_regs[i].name = 0; | |
245 | } | |
246 | ||
247 | m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); | |
248 | m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); | |
249 | m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); | |
250 | soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; | |
251 | m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); | |
78073dd8 | 252 | |
82c230c2 SC |
253 | for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) |
254 | { | |
255 | char buf[10]; | |
78073dd8 | 256 | |
82c230c2 SC |
257 | sprintf (buf, "_.d%d", i - SOFT_D1_REGNUM + 1); |
258 | m68hc11_get_register_info (&soft_regs[i], buf); | |
259 | } | |
78073dd8 | 260 | |
82c230c2 SC |
261 | if (soft_regs[SOFT_FP_REGNUM].name == 0) |
262 | { | |
263 | warning ("No frame soft register found in the symbol table.\n"); | |
264 | warning ("Stack backtrace will not work.\n"); | |
265 | } | |
266 | soft_reg_initialized = 1; | |
267 | } | |
78073dd8 | 268 | |
82c230c2 SC |
269 | /* Given an address in memory, return the soft register number if |
270 | that address corresponds to a soft register. Returns -1 if not. */ | |
271 | static int | |
272 | m68hc11_which_soft_register (CORE_ADDR addr) | |
273 | { | |
274 | int i; | |
275 | ||
276 | if (addr < soft_min_addr || addr > soft_max_addr) | |
277 | return -1; | |
278 | ||
279 | for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) | |
280 | { | |
281 | if (soft_regs[i].name && soft_regs[i].addr == addr) | |
282 | return i; | |
283 | } | |
284 | return -1; | |
285 | } | |
78073dd8 | 286 | |
82c230c2 SC |
287 | /* Fetch a pseudo register. The 68hc11 soft registers are treated like |
288 | pseudo registers. They are located in memory. Translate the register | |
289 | fetch into a memory read. */ | |
46ce284d AC |
290 | static void |
291 | m68hc11_pseudo_register_read (struct gdbarch *gdbarch, | |
292 | struct regcache *regcache, | |
293 | int regno, void *buf) | |
82c230c2 | 294 | { |
548bcbec SC |
295 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
296 | addressing mode. */ | |
297 | if (regno == M68HC12_HARD_PC_REGNUM) | |
298 | { | |
4db73d49 | 299 | ULONGEST pc; |
548bcbec | 300 | const int regsize = TYPE_LENGTH (builtin_type_uint32); |
548bcbec | 301 | |
4db73d49 | 302 | regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc); |
548bcbec SC |
303 | if (pc >= 0x8000 && pc < 0xc000) |
304 | { | |
4db73d49 SC |
305 | ULONGEST page; |
306 | ||
307 | regcache_cooked_read_unsigned (regcache, HARD_PAGE_REGNUM, &page); | |
548bcbec SC |
308 | pc -= 0x8000; |
309 | pc += (page << 14); | |
310 | pc += 0x1000000; | |
311 | } | |
312 | store_unsigned_integer (buf, regsize, pc); | |
313 | return; | |
314 | } | |
315 | ||
82c230c2 SC |
316 | m68hc11_initialize_register_info (); |
317 | ||
318 | /* Fetch a soft register: translate into a memory read. */ | |
319 | if (soft_regs[regno].name) | |
320 | { | |
321 | target_read_memory (soft_regs[regno].addr, buf, 2); | |
322 | } | |
323 | else | |
324 | { | |
325 | memset (buf, 0, 2); | |
326 | } | |
82c230c2 | 327 | } |
78073dd8 | 328 | |
82c230c2 SC |
329 | /* Store a pseudo register. Translate the register store |
330 | into a memory write. */ | |
331 | static void | |
46ce284d AC |
332 | m68hc11_pseudo_register_write (struct gdbarch *gdbarch, |
333 | struct regcache *regcache, | |
334 | int regno, const void *buf) | |
82c230c2 | 335 | { |
548bcbec SC |
336 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
337 | addressing mode. */ | |
338 | if (regno == M68HC12_HARD_PC_REGNUM) | |
339 | { | |
340 | const int regsize = TYPE_LENGTH (builtin_type_uint32); | |
341 | char *tmp = alloca (regsize); | |
342 | CORE_ADDR pc; | |
343 | ||
344 | memcpy (tmp, buf, regsize); | |
345 | pc = extract_unsigned_integer (tmp, regsize); | |
346 | if (pc >= 0x1000000) | |
347 | { | |
348 | pc -= 0x1000000; | |
4db73d49 SC |
349 | regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, |
350 | (pc >> 14) & 0x0ff); | |
548bcbec | 351 | pc &= 0x03fff; |
4db73d49 SC |
352 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, |
353 | pc + 0x8000); | |
548bcbec SC |
354 | } |
355 | else | |
4db73d49 | 356 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); |
548bcbec SC |
357 | return; |
358 | } | |
359 | ||
82c230c2 | 360 | m68hc11_initialize_register_info (); |
78073dd8 | 361 | |
82c230c2 SC |
362 | /* Store a soft register: translate into a memory write. */ |
363 | if (soft_regs[regno].name) | |
364 | { | |
46ce284d AC |
365 | const int regsize = 2; |
366 | char *tmp = alloca (regsize); | |
367 | memcpy (tmp, buf, regsize); | |
368 | target_write_memory (soft_regs[regno].addr, tmp, regsize); | |
82c230c2 SC |
369 | } |
370 | } | |
78073dd8 | 371 | |
fa88f677 | 372 | static const char * |
82c230c2 | 373 | m68hc11_register_name (int reg_nr) |
78073dd8 | 374 | { |
548bcbec SC |
375 | if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER) |
376 | return "pc"; | |
377 | if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER) | |
378 | return "ppc"; | |
379 | ||
82c230c2 SC |
380 | if (reg_nr < 0) |
381 | return NULL; | |
382 | if (reg_nr >= M68HC11_ALL_REGS) | |
383 | return NULL; | |
384 | ||
385 | /* If we don't know the address of a soft register, pretend it | |
386 | does not exist. */ | |
387 | if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) | |
388 | return NULL; | |
389 | return m68hc11_register_names[reg_nr]; | |
390 | } | |
78073dd8 | 391 | |
f4f9705a | 392 | static const unsigned char * |
82c230c2 | 393 | m68hc11_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
78073dd8 | 394 | { |
82c230c2 SC |
395 | static unsigned char breakpoint[] = {0x0}; |
396 | ||
397 | *lenptr = sizeof (breakpoint); | |
398 | return breakpoint; | |
78073dd8 AC |
399 | } |
400 | ||
908f682f SC |
401 | \f |
402 | /* 68HC11 & 68HC12 prologue analysis. | |
403 | ||
404 | */ | |
405 | #define MAX_CODES 12 | |
406 | ||
407 | /* 68HC11 opcodes. */ | |
408 | #undef M6811_OP_PAGE2 | |
b94a41a1 SC |
409 | #define M6811_OP_PAGE2 (0x18) |
410 | #define M6811_OP_LDX (0xde) | |
411 | #define M6811_OP_LDX_EXT (0xfe) | |
412 | #define M6811_OP_PSHX (0x3c) | |
413 | #define M6811_OP_STS (0x9f) | |
414 | #define M6811_OP_STS_EXT (0xbf) | |
415 | #define M6811_OP_TSX (0x30) | |
416 | #define M6811_OP_XGDX (0x8f) | |
417 | #define M6811_OP_ADDD (0xc3) | |
418 | #define M6811_OP_TXS (0x35) | |
419 | #define M6811_OP_DES (0x34) | |
908f682f SC |
420 | |
421 | /* 68HC12 opcodes. */ | |
b94a41a1 SC |
422 | #define M6812_OP_PAGE2 (0x18) |
423 | #define M6812_OP_MOVW (0x01) | |
424 | #define M6812_PB_PSHW (0xae) | |
425 | #define M6812_OP_STS (0x5f) | |
426 | #define M6812_OP_STS_EXT (0x7f) | |
427 | #define M6812_OP_LEAS (0x1b) | |
428 | #define M6812_OP_PSHX (0x34) | |
429 | #define M6812_OP_PSHY (0x35) | |
908f682f SC |
430 | |
431 | /* Operand extraction. */ | |
432 | #define OP_DIRECT (0x100) /* 8-byte direct addressing. */ | |
433 | #define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ | |
434 | #define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ | |
435 | #define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ | |
436 | ||
437 | /* Identification of the sequence. */ | |
438 | enum m6811_seq_type | |
439 | { | |
440 | P_LAST = 0, | |
441 | P_SAVE_REG, /* Save a register on the stack. */ | |
442 | P_SET_FRAME, /* Setup the frame pointer. */ | |
443 | P_LOCAL_1, /* Allocate 1 byte for locals. */ | |
444 | P_LOCAL_2, /* Allocate 2 bytes for locals. */ | |
445 | P_LOCAL_N /* Allocate N bytes for locals. */ | |
446 | }; | |
447 | ||
448 | struct insn_sequence { | |
449 | enum m6811_seq_type type; | |
450 | unsigned length; | |
451 | unsigned short code[MAX_CODES]; | |
452 | }; | |
453 | ||
454 | /* Sequence of instructions in the 68HC11 function prologue. */ | |
455 | static struct insn_sequence m6811_prologue[] = { | |
456 | /* Sequences to save a soft-register. */ | |
457 | { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, | |
458 | M6811_OP_PSHX } }, | |
459 | { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, | |
460 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
b94a41a1 SC |
461 | { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
462 | M6811_OP_PSHX } }, | |
463 | { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, | |
464 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
908f682f SC |
465 | |
466 | /* Sequences to allocate local variables. */ | |
467 | { P_LOCAL_N, 7, { M6811_OP_TSX, | |
468 | M6811_OP_XGDX, | |
469 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
470 | M6811_OP_XGDX, | |
471 | M6811_OP_TXS } }, | |
472 | { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, | |
473 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
474 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
475 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
476 | M6811_OP_PAGE2, M6811_OP_TXS } }, | |
477 | { P_LOCAL_1, 1, { M6811_OP_DES } }, | |
478 | { P_LOCAL_2, 1, { M6811_OP_PSHX } }, | |
479 | { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
480 | ||
481 | /* Initialize the frame pointer. */ | |
482 | { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, | |
b94a41a1 | 483 | { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, |
908f682f SC |
484 | { P_LAST, 0, { 0 } } |
485 | }; | |
486 | ||
487 | ||
488 | /* Sequence of instructions in the 68HC12 function prologue. */ | |
489 | static struct insn_sequence m6812_prologue[] = { | |
490 | { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, | |
491 | OP_IMM_HIGH, OP_IMM_LOW } }, | |
b94a41a1 SC |
492 | { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, |
493 | { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, | |
908f682f | 494 | { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, |
ffe1f3ee SC |
495 | { P_LOCAL_2, 1, { M6812_OP_PSHX } }, |
496 | { P_LOCAL_2, 1, { M6812_OP_PSHY } }, | |
908f682f SC |
497 | { P_LAST, 0 } |
498 | }; | |
499 | ||
500 | ||
501 | /* Analyze the sequence of instructions starting at the given address. | |
502 | Returns a pointer to the sequence when it is recognized and | |
c8a7f6ac | 503 | the optional value (constant/address) associated with it. */ |
908f682f | 504 | static struct insn_sequence * |
c8a7f6ac | 505 | m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc, |
908f682f SC |
506 | CORE_ADDR *val) |
507 | { | |
508 | unsigned char buffer[MAX_CODES]; | |
509 | unsigned bufsize; | |
510 | unsigned j; | |
511 | CORE_ADDR cur_val; | |
512 | short v = 0; | |
513 | ||
514 | bufsize = 0; | |
515 | for (; seq->type != P_LAST; seq++) | |
516 | { | |
517 | cur_val = 0; | |
518 | for (j = 0; j < seq->length; j++) | |
519 | { | |
520 | if (bufsize < j + 1) | |
521 | { | |
c8a7f6ac | 522 | buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, |
908f682f SC |
523 | 1); |
524 | bufsize++; | |
525 | } | |
526 | /* Continue while we match the opcode. */ | |
527 | if (seq->code[j] == buffer[j]) | |
528 | continue; | |
529 | ||
530 | if ((seq->code[j] & 0xf00) == 0) | |
531 | break; | |
532 | ||
533 | /* Extract a sequence parameter (address or constant). */ | |
534 | switch (seq->code[j]) | |
535 | { | |
536 | case OP_DIRECT: | |
537 | cur_val = (CORE_ADDR) buffer[j]; | |
538 | break; | |
539 | ||
540 | case OP_IMM_HIGH: | |
541 | cur_val = cur_val & 0x0ff; | |
542 | cur_val |= (buffer[j] << 8); | |
543 | break; | |
544 | ||
545 | case OP_IMM_LOW: | |
546 | cur_val &= 0x0ff00; | |
547 | cur_val |= buffer[j]; | |
548 | break; | |
549 | ||
550 | case OP_PBYTE: | |
551 | if ((buffer[j] & 0xE0) == 0x80) | |
552 | { | |
553 | v = buffer[j] & 0x1f; | |
554 | if (v & 0x10) | |
555 | v |= 0xfff0; | |
556 | } | |
557 | else if ((buffer[j] & 0xfe) == 0xf0) | |
558 | { | |
c8a7f6ac | 559 | v = read_memory_unsigned_integer (pc + j + 1, 1); |
908f682f SC |
560 | if (buffer[j] & 1) |
561 | v |= 0xff00; | |
562 | } | |
563 | else if (buffer[j] == 0xf2) | |
564 | { | |
c8a7f6ac | 565 | v = read_memory_unsigned_integer (pc + j + 1, 2); |
908f682f SC |
566 | } |
567 | cur_val = v; | |
568 | break; | |
569 | } | |
570 | } | |
571 | ||
572 | /* We have a full match. */ | |
573 | if (j == seq->length) | |
574 | { | |
575 | *val = cur_val; | |
908f682f SC |
576 | return seq; |
577 | } | |
578 | } | |
579 | return 0; | |
580 | } | |
581 | ||
7df11f59 SC |
582 | /* Return the instruction that the function at the PC is using. */ |
583 | static enum insn_return_kind | |
584 | m68hc11_get_return_insn (CORE_ADDR pc) | |
585 | { | |
586 | struct minimal_symbol *sym; | |
587 | ||
588 | /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT | |
589 | function is stored by elfread.c in the high bit of the info field. | |
590 | Use this to decide which instruction the function uses to return. */ | |
591 | sym = lookup_minimal_symbol_by_pc (pc); | |
592 | if (sym == 0) | |
593 | return RETURN_RTS; | |
594 | ||
595 | if (MSYMBOL_IS_RTC (sym)) | |
596 | return RETURN_RTC; | |
597 | else if (MSYMBOL_IS_RTI (sym)) | |
598 | return RETURN_RTI; | |
599 | else | |
600 | return RETURN_RTS; | |
601 | } | |
602 | ||
78073dd8 AC |
603 | /* Analyze the function prologue to find some information |
604 | about the function: | |
605 | - the PC of the first line (for m68hc11_skip_prologue) | |
606 | - the offset of the previous frame saved address (from current frame) | |
607 | - the soft registers which are pushed. */ | |
1ea653ae SC |
608 | static CORE_ADDR |
609 | m68hc11_scan_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
610 | struct m68hc11_unwind_cache *info) | |
78073dd8 | 611 | { |
1ea653ae | 612 | LONGEST save_addr; |
78073dd8 | 613 | CORE_ADDR func_end; |
78073dd8 AC |
614 | int size; |
615 | int found_frame_point; | |
82c230c2 | 616 | int saved_reg; |
908f682f SC |
617 | int done = 0; |
618 | struct insn_sequence *seq_table; | |
1ea653ae SC |
619 | |
620 | info->size = 0; | |
621 | info->sp_offset = 0; | |
622 | if (pc >= current_pc) | |
623 | return current_pc; | |
624 | ||
78073dd8 AC |
625 | size = 0; |
626 | ||
82c230c2 | 627 | m68hc11_initialize_register_info (); |
1ea653ae | 628 | if (pc == 0) |
78073dd8 | 629 | { |
1ea653ae SC |
630 | info->size = 0; |
631 | return pc; | |
78073dd8 AC |
632 | } |
633 | ||
908f682f SC |
634 | seq_table = gdbarch_tdep (current_gdbarch)->prologue; |
635 | ||
78073dd8 AC |
636 | /* The 68hc11 stack is as follows: |
637 | ||
638 | ||
639 | | | | |
640 | +-----------+ | |
641 | | | | |
642 | | args | | |
643 | | | | |
644 | +-----------+ | |
645 | | PC-return | | |
646 | +-----------+ | |
647 | | Old frame | | |
648 | +-----------+ | |
649 | | | | |
650 | | Locals | | |
651 | | | | |
652 | +-----------+ <--- current frame | |
653 | | | | |
654 | ||
655 | With most processors (like 68K) the previous frame can be computed | |
656 | easily because it is always at a fixed offset (see link/unlink). | |
657 | That is, locals are accessed with negative offsets, arguments are | |
658 | accessed with positive ones. Since 68hc11 only supports offsets | |
659 | in the range [0..255], the frame is defined at the bottom of | |
660 | locals (see picture). | |
661 | ||
662 | The purpose of the analysis made here is to find out the size | |
663 | of locals in this function. An alternative to this is to use | |
664 | DWARF2 info. This would be better but I don't know how to | |
665 | access dwarf2 debug from this function. | |
666 | ||
667 | Walk from the function entry point to the point where we save | |
668 | the frame. While walking instructions, compute the size of bytes | |
669 | which are pushed. This gives us the index to access the previous | |
670 | frame. | |
671 | ||
672 | We limit the search to 128 bytes so that the algorithm is bounded | |
673 | in case of random and wrong code. We also stop and abort if | |
674 | we find an instruction which is not supposed to appear in the | |
675 | prologue (as generated by gcc 2.95, 2.96). | |
676 | */ | |
78073dd8 | 677 | func_end = pc + 128; |
78073dd8 | 678 | found_frame_point = 0; |
1ea653ae SC |
679 | info->size = 0; |
680 | save_addr = 0; | |
908f682f | 681 | while (!done && pc + 2 < func_end) |
78073dd8 | 682 | { |
908f682f SC |
683 | struct insn_sequence *seq; |
684 | CORE_ADDR val; | |
1ea653ae | 685 | |
c8a7f6ac | 686 | seq = m68hc11_analyze_instruction (seq_table, pc, &val); |
908f682f SC |
687 | if (seq == 0) |
688 | break; | |
78073dd8 | 689 | |
c8a7f6ac SC |
690 | /* If we are within the instruction group, we can't advance the |
691 | pc nor the stack offset. Otherwise the caller's stack computed | |
692 | from the current stack can be wrong. */ | |
693 | if (pc + seq->length > current_pc) | |
694 | break; | |
695 | ||
696 | pc = pc + seq->length; | |
908f682f | 697 | if (seq->type == P_SAVE_REG) |
78073dd8 | 698 | { |
908f682f SC |
699 | if (found_frame_point) |
700 | { | |
701 | saved_reg = m68hc11_which_soft_register (val); | |
702 | if (saved_reg < 0) | |
703 | break; | |
78073dd8 | 704 | |
908f682f | 705 | save_addr -= 2; |
1ea653ae | 706 | info->saved_regs[saved_reg].addr = save_addr; |
908f682f SC |
707 | } |
708 | else | |
709 | { | |
710 | size += 2; | |
711 | } | |
78073dd8 | 712 | } |
908f682f | 713 | else if (seq->type == P_SET_FRAME) |
78073dd8 AC |
714 | { |
715 | found_frame_point = 1; | |
1ea653ae | 716 | info->size = size; |
78073dd8 | 717 | } |
908f682f | 718 | else if (seq->type == P_LOCAL_1) |
78073dd8 | 719 | { |
6148eca7 SC |
720 | size += 1; |
721 | } | |
908f682f | 722 | else if (seq->type == P_LOCAL_2) |
78073dd8 | 723 | { |
908f682f | 724 | size += 2; |
78073dd8 | 725 | } |
908f682f | 726 | else if (seq->type == P_LOCAL_N) |
78073dd8 | 727 | { |
908f682f SC |
728 | /* Stack pointer is decremented for the allocation. */ |
729 | if (val & 0x8000) | |
730 | size -= (int) (val) | 0xffff0000; | |
731 | else | |
732 | size -= val; | |
78073dd8 AC |
733 | } |
734 | } | |
1ea653ae SC |
735 | if (found_frame_point == 0) |
736 | info->sp_offset = size; | |
737 | else | |
738 | info->sp_offset = -1; | |
739 | return pc; | |
78073dd8 AC |
740 | } |
741 | ||
82c230c2 | 742 | static CORE_ADDR |
78073dd8 AC |
743 | m68hc11_skip_prologue (CORE_ADDR pc) |
744 | { | |
745 | CORE_ADDR func_addr, func_end; | |
746 | struct symtab_and_line sal; | |
1ea653ae | 747 | struct m68hc11_unwind_cache tmp_cache = { 0 }; |
78073dd8 | 748 | |
82c230c2 SC |
749 | /* If we have line debugging information, then the end of the |
750 | prologue should be the first assembly instruction of the | |
78073dd8 AC |
751 | first source line. */ |
752 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
753 | { | |
754 | sal = find_pc_line (func_addr, 0); | |
755 | if (sal.end && sal.end < func_end) | |
756 | return sal.end; | |
757 | } | |
758 | ||
1ea653ae | 759 | pc = m68hc11_scan_prologue (pc, (CORE_ADDR) -1, &tmp_cache); |
78073dd8 AC |
760 | return pc; |
761 | } | |
762 | ||
1ea653ae SC |
763 | static CORE_ADDR |
764 | m68hc11_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
765 | { | |
766 | ULONGEST pc; | |
767 | ||
768 | frame_unwind_unsigned_register (next_frame, gdbarch_pc_regnum (gdbarch), | |
769 | &pc); | |
770 | return pc; | |
771 | } | |
772 | ||
773 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
774 | the saved registers of frame described by FRAME_INFO. This | |
775 | includes special registers such as pc and fp saved in special ways | |
776 | in the stack frame. sp is even more special: the address we return | |
777 | for it IS the sp for the next frame. */ | |
778 | ||
779 | struct m68hc11_unwind_cache * | |
780 | m68hc11_frame_unwind_cache (struct frame_info *next_frame, | |
781 | void **this_prologue_cache) | |
782 | { | |
783 | ULONGEST prev_sp; | |
784 | ULONGEST this_base; | |
785 | struct m68hc11_unwind_cache *info; | |
786 | CORE_ADDR current_pc; | |
787 | int i; | |
788 | ||
789 | if ((*this_prologue_cache)) | |
790 | return (*this_prologue_cache); | |
791 | ||
792 | info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); | |
793 | (*this_prologue_cache) = info; | |
794 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
795 | ||
796 | info->pc = frame_func_unwind (next_frame); | |
797 | ||
798 | info->size = 0; | |
799 | info->return_kind = m68hc11_get_return_insn (info->pc); | |
800 | ||
801 | /* The SP was moved to the FP. This indicates that a new frame | |
802 | was created. Get THIS frame's FP value by unwinding it from | |
803 | the next frame. */ | |
804 | frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &this_base); | |
805 | if (this_base == 0) | |
806 | { | |
807 | info->base = 0; | |
808 | return info; | |
809 | } | |
810 | ||
811 | current_pc = frame_pc_unwind (next_frame); | |
812 | if (info->pc != 0) | |
813 | m68hc11_scan_prologue (info->pc, current_pc, info); | |
814 | ||
815 | info->saved_regs[HARD_PC_REGNUM].addr = info->size; | |
816 | ||
817 | if (info->sp_offset != (CORE_ADDR) -1) | |
818 | { | |
819 | info->saved_regs[HARD_PC_REGNUM].addr = info->sp_offset; | |
820 | frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &this_base); | |
821 | prev_sp = this_base + info->sp_offset + 2; | |
822 | this_base += STACK_CORRECTION; | |
823 | } | |
824 | else | |
825 | { | |
826 | /* The FP points at the last saved register. Adjust the FP back | |
827 | to before the first saved register giving the SP. */ | |
828 | prev_sp = this_base + info->size + 2; | |
829 | ||
830 | this_base += STACK_CORRECTION; | |
831 | if (soft_regs[SOFT_FP_REGNUM].name) | |
832 | info->saved_regs[SOFT_FP_REGNUM].addr = info->size - 2; | |
833 | } | |
834 | ||
835 | if (info->return_kind == RETURN_RTC) | |
836 | { | |
837 | prev_sp += 1; | |
838 | info->saved_regs[HARD_PAGE_REGNUM].addr = info->size; | |
839 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 1; | |
840 | } | |
841 | else if (info->return_kind == RETURN_RTI) | |
842 | { | |
843 | prev_sp += 7; | |
844 | info->saved_regs[HARD_CCR_REGNUM].addr = info->size; | |
845 | info->saved_regs[HARD_D_REGNUM].addr = info->size + 1; | |
846 | info->saved_regs[HARD_X_REGNUM].addr = info->size + 3; | |
847 | info->saved_regs[HARD_Y_REGNUM].addr = info->size + 5; | |
848 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 7; | |
849 | } | |
850 | ||
851 | /* Add 1 here to adjust for the post-decrement nature of the push | |
852 | instruction.*/ | |
853 | info->prev_sp = prev_sp; | |
854 | ||
855 | info->base = this_base; | |
856 | ||
857 | /* Adjust all the saved registers so that they contain addresses and not | |
858 | offsets. */ | |
859 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS - 1; i++) | |
860 | if (trad_frame_addr_p (info->saved_regs, i)) | |
861 | { | |
862 | info->saved_regs[i].addr += this_base; | |
863 | } | |
864 | ||
865 | /* The previous frame's SP needed to be computed. Save the computed | |
866 | value. */ | |
867 | trad_frame_set_value (info->saved_regs, HARD_SP_REGNUM, info->prev_sp); | |
868 | ||
869 | return info; | |
870 | } | |
871 | ||
872 | /* Given a GDB frame, determine the address of the calling function's | |
873 | frame. This will be used to create a new GDB frame struct. */ | |
874 | ||
875 | static void | |
876 | m68hc11_frame_this_id (struct frame_info *next_frame, | |
877 | void **this_prologue_cache, | |
878 | struct frame_id *this_id) | |
879 | { | |
880 | struct m68hc11_unwind_cache *info | |
881 | = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); | |
882 | CORE_ADDR base; | |
883 | CORE_ADDR func; | |
884 | struct frame_id id; | |
885 | ||
886 | /* The FUNC is easy. */ | |
887 | func = frame_func_unwind (next_frame); | |
888 | ||
1ea653ae SC |
889 | /* Hopefully the prologue analysis either correctly determined the |
890 | frame's base (which is the SP from the previous frame), or set | |
891 | that base to "NULL". */ | |
892 | base = info->prev_sp; | |
893 | if (base == 0) | |
894 | return; | |
895 | ||
896 | id = frame_id_build (base, func); | |
897 | #if 0 | |
898 | /* Check that we're not going round in circles with the same frame | |
899 | ID (but avoid applying the test to sentinel frames which do go | |
900 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
901 | compare the frame's PC value. */ | |
902 | if (frame_relative_level (next_frame) >= 0 | |
903 | && get_frame_type (next_frame) != DUMMY_FRAME | |
904 | && frame_id_eq (get_frame_id (next_frame), id)) | |
905 | return; | |
906 | #endif | |
907 | (*this_id) = id; | |
908 | } | |
909 | ||
910 | static void | |
911 | m68hc11_frame_prev_register (struct frame_info *next_frame, | |
912 | void **this_prologue_cache, | |
913 | int regnum, int *optimizedp, | |
914 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
915 | int *realnump, void *bufferp) | |
916 | { | |
917 | struct m68hc11_unwind_cache *info | |
918 | = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); | |
919 | ||
920 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
921 | optimizedp, lvalp, addrp, realnump, bufferp); | |
922 | ||
923 | if (regnum == HARD_PC_REGNUM) | |
924 | { | |
925 | /* Take into account the 68HC12 specific call (PC + page). */ | |
926 | if (info->return_kind == RETURN_RTC | |
927 | && *addrp >= 0x08000 && *addrp < 0x0c000 | |
928 | && USE_PAGE_REGISTER) | |
929 | { | |
930 | int page_optimized; | |
931 | ||
932 | CORE_ADDR page; | |
933 | ||
934 | trad_frame_prev_register (next_frame, info->saved_regs, | |
935 | HARD_PAGE_REGNUM, &page_optimized, | |
936 | 0, &page, 0, 0); | |
937 | *addrp -= 0x08000; | |
938 | *addrp += ((page & 0x0ff) << 14); | |
939 | *addrp += 0x1000000; | |
940 | } | |
941 | } | |
942 | } | |
943 | ||
944 | static const struct frame_unwind m68hc11_frame_unwind = { | |
945 | NORMAL_FRAME, | |
946 | m68hc11_frame_this_id, | |
947 | m68hc11_frame_prev_register | |
948 | }; | |
949 | ||
950 | const struct frame_unwind * | |
1a241548 | 951 | m68hc11_frame_sniffer (struct frame_info *next_frame) |
1ea653ae SC |
952 | { |
953 | return &m68hc11_frame_unwind; | |
954 | } | |
955 | ||
956 | static CORE_ADDR | |
957 | m68hc11_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
958 | { | |
959 | struct m68hc11_unwind_cache *info | |
960 | = m68hc11_frame_unwind_cache (next_frame, this_cache); | |
961 | ||
962 | return info->base; | |
963 | } | |
964 | ||
965 | static CORE_ADDR | |
966 | m68hc11_frame_args_address (struct frame_info *next_frame, void **this_cache) | |
967 | { | |
968 | CORE_ADDR addr; | |
969 | struct m68hc11_unwind_cache *info | |
970 | = m68hc11_frame_unwind_cache (next_frame, this_cache); | |
971 | ||
972 | addr = info->base + info->size; | |
973 | if (info->return_kind == RETURN_RTC) | |
974 | addr += 1; | |
975 | else if (info->return_kind == RETURN_RTI) | |
976 | addr += 7; | |
977 | ||
978 | return addr; | |
979 | } | |
980 | ||
981 | static const struct frame_base m68hc11_frame_base = { | |
982 | &m68hc11_frame_unwind, | |
983 | m68hc11_frame_base_address, | |
984 | m68hc11_frame_base_address, | |
985 | m68hc11_frame_args_address | |
986 | }; | |
987 | ||
988 | static CORE_ADDR | |
989 | m68hc11_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
990 | { | |
991 | ULONGEST sp; | |
992 | frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &sp); | |
993 | return sp; | |
994 | } | |
995 | ||
996 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
997 | dummy frame. The frame ID's base needs to match the TOS value | |
998 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
999 | breakpoint. */ | |
1000 | ||
1001 | static struct frame_id | |
1002 | m68hc11_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1003 | { | |
1004 | ULONGEST tos; | |
1005 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1006 | ||
1007 | frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &tos); | |
1008 | tos += 2; | |
1009 | return frame_id_build (tos, pc); | |
1010 | } | |
78073dd8 | 1011 | |
e286caf2 SC |
1012 | \f |
1013 | /* Get and print the register from the given frame. */ | |
78073dd8 | 1014 | static void |
e286caf2 SC |
1015 | m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
1016 | struct frame_info *frame, int regno) | |
78073dd8 | 1017 | { |
e286caf2 SC |
1018 | LONGEST rval; |
1019 | ||
1020 | if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM | |
1021 | || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) | |
7f5f525d | 1022 | rval = get_frame_register_unsigned (frame, regno); |
e286caf2 | 1023 | else |
7f5f525d | 1024 | rval = get_frame_register_signed (frame, regno); |
e286caf2 SC |
1025 | |
1026 | if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM | |
1027 | || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) | |
7df11f59 | 1028 | { |
e286caf2 SC |
1029 | fprintf_filtered (file, "0x%02x ", (unsigned char) rval); |
1030 | if (regno != HARD_CCR_REGNUM) | |
1031 | print_longest (file, 'd', 1, rval); | |
7df11f59 | 1032 | } |
e286caf2 SC |
1033 | else |
1034 | { | |
1035 | if (regno == HARD_PC_REGNUM && gdbarch_tdep (gdbarch)->use_page_register) | |
1036 | { | |
1037 | ULONGEST page; | |
7df11f59 | 1038 | |
7f5f525d | 1039 | page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); |
e286caf2 SC |
1040 | fprintf_filtered (file, "0x%02x:%04x ", (unsigned) page, |
1041 | (unsigned) rval); | |
1042 | } | |
1043 | else | |
1044 | { | |
1045 | fprintf_filtered (file, "0x%04x ", (unsigned) rval); | |
1046 | if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM | |
1047 | && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) | |
1048 | print_longest (file, 'd', 1, rval); | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | if (regno == HARD_CCR_REGNUM) | |
78073dd8 | 1053 | { |
e286caf2 SC |
1054 | /* CCR register */ |
1055 | int C, Z, N, V; | |
1056 | unsigned char l = rval & 0xff; | |
1057 | ||
1058 | fprintf_filtered (file, "%c%c%c%c%c%c%c%c ", | |
1059 | l & M6811_S_BIT ? 'S' : '-', | |
1060 | l & M6811_X_BIT ? 'X' : '-', | |
1061 | l & M6811_H_BIT ? 'H' : '-', | |
1062 | l & M6811_I_BIT ? 'I' : '-', | |
1063 | l & M6811_N_BIT ? 'N' : '-', | |
1064 | l & M6811_Z_BIT ? 'Z' : '-', | |
1065 | l & M6811_V_BIT ? 'V' : '-', | |
1066 | l & M6811_C_BIT ? 'C' : '-'); | |
1067 | N = (l & M6811_N_BIT) != 0; | |
1068 | Z = (l & M6811_Z_BIT) != 0; | |
1069 | V = (l & M6811_V_BIT) != 0; | |
1070 | C = (l & M6811_C_BIT) != 0; | |
1071 | ||
1072 | /* Print flags following the h8300 */ | |
1073 | if ((C | Z) == 0) | |
1074 | fprintf_filtered (file, "u> "); | |
1075 | else if ((C | Z) == 1) | |
1076 | fprintf_filtered (file, "u<= "); | |
1077 | else if (C == 0) | |
1078 | fprintf_filtered (file, "u< "); | |
1079 | ||
1080 | if (Z == 0) | |
1081 | fprintf_filtered (file, "!= "); | |
1082 | else | |
1083 | fprintf_filtered (file, "== "); | |
1084 | ||
1085 | if ((N ^ V) == 0) | |
1086 | fprintf_filtered (file, ">= "); | |
1087 | else | |
1088 | fprintf_filtered (file, "< "); | |
1089 | ||
1090 | if ((Z | (N ^ V)) == 0) | |
1091 | fprintf_filtered (file, "> "); | |
78073dd8 | 1092 | else |
e286caf2 | 1093 | fprintf_filtered (file, "<= "); |
78073dd8 | 1094 | } |
e286caf2 SC |
1095 | } |
1096 | ||
1097 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1098 | static void | |
1099 | m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
1100 | struct frame_info *frame, int regno, int cpregs) | |
1101 | { | |
1102 | if (regno >= 0) | |
1103 | { | |
1104 | const char *name = gdbarch_register_name (gdbarch, regno); | |
1105 | ||
1106 | if (!name || !*name) | |
1107 | return; | |
1108 | ||
1109 | fprintf_filtered (file, "%-10s ", name); | |
1110 | m68hc11_print_register (gdbarch, file, frame, regno); | |
1111 | fprintf_filtered (file, "\n"); | |
1112 | } | |
1113 | else | |
1114 | { | |
1115 | int i, nr; | |
1116 | ||
1117 | fprintf_filtered (file, "PC="); | |
1118 | m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); | |
1119 | ||
1120 | fprintf_filtered (file, " SP="); | |
1121 | m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); | |
1122 | ||
1123 | fprintf_filtered (file, " FP="); | |
1124 | m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); | |
1125 | ||
1126 | fprintf_filtered (file, "\nCCR="); | |
1127 | m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); | |
1128 | ||
1129 | fprintf_filtered (file, "\nD="); | |
1130 | m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); | |
1131 | ||
1132 | fprintf_filtered (file, " X="); | |
1133 | m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); | |
1134 | ||
1135 | fprintf_filtered (file, " Y="); | |
1136 | m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); | |
1137 | ||
1138 | if (gdbarch_tdep (gdbarch)->use_page_register) | |
1139 | { | |
1140 | fprintf_filtered (file, "\nPage="); | |
1141 | m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); | |
1142 | } | |
1143 | fprintf_filtered (file, "\n"); | |
1144 | ||
1145 | nr = 0; | |
1146 | for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) | |
1147 | { | |
1148 | /* Skip registers which are not defined in the symbol table. */ | |
1149 | if (soft_regs[i].name == 0) | |
1150 | continue; | |
1151 | ||
1152 | fprintf_filtered (file, "D%d=", i - SOFT_D1_REGNUM + 1); | |
1153 | m68hc11_print_register (gdbarch, file, frame, i); | |
1154 | nr++; | |
1155 | if ((nr % 8) == 7) | |
1156 | fprintf_filtered (file, "\n"); | |
1157 | else | |
1158 | fprintf_filtered (file, " "); | |
1159 | } | |
1160 | if (nr && (nr % 8) != 7) | |
1161 | fprintf_filtered (file, "\n"); | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1166 | static void | |
1167 | show_regs (char *args, int from_tty) | |
1168 | { | |
1169 | m68hc11_print_registers_info (current_gdbarch, gdb_stdout, | |
1170 | get_current_frame (), -1, 1); | |
78073dd8 AC |
1171 | } |
1172 | ||
22df305e SC |
1173 | static CORE_ADDR |
1174 | m68hc11_stack_align (CORE_ADDR addr) | |
1175 | { | |
1176 | return ((addr + 1) & -2); | |
1177 | } | |
1178 | ||
82c230c2 | 1179 | static CORE_ADDR |
3dc990bf SC |
1180 | m68hc11_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1181 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1182 | int nargs, struct value **args, CORE_ADDR sp, | |
1183 | int struct_return, CORE_ADDR struct_addr) | |
78073dd8 | 1184 | { |
82c230c2 SC |
1185 | int argnum; |
1186 | int first_stack_argnum; | |
82c230c2 SC |
1187 | struct type *type; |
1188 | char *val; | |
1189 | int len; | |
3dc990bf | 1190 | char buf[2]; |
82c230c2 | 1191 | |
82c230c2 SC |
1192 | first_stack_argnum = 0; |
1193 | if (struct_return) | |
1194 | { | |
184651e3 SC |
1195 | /* The struct is allocated on the stack and gdb used the stack |
1196 | pointer for the address of that struct. We must apply the | |
1197 | stack offset on the address. */ | |
3dc990bf SC |
1198 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, |
1199 | struct_addr + STACK_CORRECTION); | |
82c230c2 SC |
1200 | } |
1201 | else if (nargs > 0) | |
1202 | { | |
1203 | type = VALUE_TYPE (args[0]); | |
1204 | len = TYPE_LENGTH (type); | |
3dc990bf | 1205 | |
82c230c2 SC |
1206 | /* First argument is passed in D and X registers. */ |
1207 | if (len <= 4) | |
1208 | { | |
3dc990bf SC |
1209 | ULONGEST v; |
1210 | ||
1211 | v = extract_unsigned_integer (VALUE_CONTENTS (args[0]), len); | |
82c230c2 | 1212 | first_stack_argnum = 1; |
3dc990bf SC |
1213 | |
1214 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); | |
82c230c2 SC |
1215 | if (len > 2) |
1216 | { | |
1217 | v >>= 16; | |
3dc990bf | 1218 | regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); |
82c230c2 SC |
1219 | } |
1220 | } | |
1221 | } | |
82c230c2 | 1222 | |
3dc990bf | 1223 | for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) |
82c230c2 SC |
1224 | { |
1225 | type = VALUE_TYPE (args[argnum]); | |
1226 | len = TYPE_LENGTH (type); | |
1227 | ||
22df305e SC |
1228 | if (len & 1) |
1229 | { | |
1230 | static char zero = 0; | |
1231 | ||
3dc990bf SC |
1232 | sp--; |
1233 | write_memory (sp, &zero, 1); | |
22df305e | 1234 | } |
3dc990bf SC |
1235 | val = (char*) VALUE_CONTENTS (args[argnum]); |
1236 | sp -= len; | |
1237 | write_memory (sp, val, len); | |
82c230c2 | 1238 | } |
3dc990bf SC |
1239 | |
1240 | /* Store return address. */ | |
1241 | sp -= 2; | |
1242 | store_unsigned_integer (buf, 2, bp_addr); | |
1243 | write_memory (sp, buf, 2); | |
1244 | ||
1245 | /* Finally, update the stack pointer... */ | |
1246 | sp -= STACK_CORRECTION; | |
1247 | regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); | |
1248 | ||
1249 | /* ...and fake a frame pointer. */ | |
1250 | regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); | |
1251 | ||
1252 | /* DWARF2/GCC uses the stack address *before* the function call as a | |
1253 | frame's CFA. */ | |
1254 | return sp + 2; | |
78073dd8 AC |
1255 | } |
1256 | ||
1257 | ||
4db73d49 SC |
1258 | /* Return the GDB type object for the "standard" data type |
1259 | of data in register N. */ | |
1260 | ||
82c230c2 | 1261 | static struct type * |
4db73d49 | 1262 | m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) |
82c230c2 | 1263 | { |
5706502a SC |
1264 | switch (reg_nr) |
1265 | { | |
1266 | case HARD_PAGE_REGNUM: | |
1267 | case HARD_A_REGNUM: | |
1268 | case HARD_B_REGNUM: | |
1269 | case HARD_CCR_REGNUM: | |
1270 | return builtin_type_uint8; | |
1271 | ||
548bcbec SC |
1272 | case M68HC12_HARD_PC_REGNUM: |
1273 | return builtin_type_uint32; | |
1274 | ||
5706502a SC |
1275 | default: |
1276 | return builtin_type_uint16; | |
1277 | } | |
82c230c2 SC |
1278 | } |
1279 | ||
82c230c2 | 1280 | static void |
4db73d49 SC |
1281 | m68hc11_store_return_value (struct type *type, struct regcache *regcache, |
1282 | const void *valbuf) | |
82c230c2 | 1283 | { |
22df305e SC |
1284 | int len; |
1285 | ||
1286 | len = TYPE_LENGTH (type); | |
1287 | ||
1288 | /* First argument is passed in D and X registers. */ | |
4db73d49 SC |
1289 | if (len <= 2) |
1290 | regcache_raw_write_part (regcache, HARD_D_REGNUM, 2 - len, len, valbuf); | |
1291 | else if (len <= 4) | |
22df305e | 1292 | { |
4db73d49 SC |
1293 | regcache_raw_write_part (regcache, HARD_X_REGNUM, 4 - len, |
1294 | len - 2, valbuf); | |
1295 | regcache_raw_write (regcache, HARD_D_REGNUM, (char*) valbuf + (len - 2)); | |
22df305e SC |
1296 | } |
1297 | else | |
1298 | error ("return of value > 4 is not supported."); | |
82c230c2 SC |
1299 | } |
1300 | ||
1301 | ||
ef2b8fcd | 1302 | /* Given a return value in `regcache' with a type `type', |
78073dd8 AC |
1303 | extract and copy its value into `valbuf'. */ |
1304 | ||
82c230c2 | 1305 | static void |
ef2b8fcd SC |
1306 | m68hc11_extract_return_value (struct type *type, struct regcache *regcache, |
1307 | void *valbuf) | |
78073dd8 | 1308 | { |
82c230c2 | 1309 | int len = TYPE_LENGTH (type); |
ef2b8fcd SC |
1310 | char buf[M68HC11_REG_SIZE]; |
1311 | ||
1312 | regcache_raw_read (regcache, HARD_D_REGNUM, buf); | |
22df305e | 1313 | switch (len) |
82c230c2 | 1314 | { |
22df305e | 1315 | case 1: |
ef2b8fcd | 1316 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1317 | break; |
ef2b8fcd | 1318 | |
22df305e | 1319 | case 2: |
ef2b8fcd | 1320 | memcpy (valbuf, buf, 2); |
22df305e | 1321 | break; |
ef2b8fcd | 1322 | |
22df305e | 1323 | case 3: |
ef2b8fcd SC |
1324 | memcpy ((char*) valbuf + 1, buf, 2); |
1325 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1326 | memcpy (valbuf, buf + 1, 1); | |
22df305e | 1327 | break; |
ef2b8fcd | 1328 | |
22df305e | 1329 | case 4: |
ef2b8fcd SC |
1330 | memcpy ((char*) valbuf + 2, buf, 2); |
1331 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1332 | memcpy (valbuf, buf, 2); | |
22df305e SC |
1333 | break; |
1334 | ||
1335 | default: | |
82c230c2 SC |
1336 | error ("bad size for return value"); |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /* Should call_function allocate stack space for a struct return? */ | |
1341 | static int | |
1342 | m68hc11_use_struct_convention (int gcc_p, struct type *type) | |
1343 | { | |
22df305e SC |
1344 | return (TYPE_CODE (type) == TYPE_CODE_STRUCT |
1345 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1346 | || TYPE_LENGTH (type) > 4); | |
82c230c2 SC |
1347 | } |
1348 | ||
1349 | static int | |
1350 | m68hc11_return_value_on_stack (struct type *type) | |
1351 | { | |
22df305e | 1352 | return TYPE_LENGTH (type) > 4; |
82c230c2 SC |
1353 | } |
1354 | ||
1355 | /* Extract from an array REGBUF containing the (raw) register state | |
1356 | the address in which a function should return its structure value, | |
1357 | as a CORE_ADDR (or an expression that can be used as one). */ | |
1358 | static CORE_ADDR | |
4db73d49 | 1359 | m68hc11_extract_struct_value_address (struct regcache *regcache) |
82c230c2 | 1360 | { |
4db73d49 SC |
1361 | char buf[M68HC11_REG_SIZE]; |
1362 | ||
1363 | regcache_cooked_read (regcache, HARD_D_REGNUM, buf); | |
1364 | return extract_unsigned_integer (buf, M68HC11_REG_SIZE); | |
82c230c2 SC |
1365 | } |
1366 | ||
7df11f59 SC |
1367 | /* Test whether the ELF symbol corresponds to a function using rtc or |
1368 | rti to return. */ | |
1369 | ||
1370 | static void | |
1371 | m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
1372 | { | |
1373 | unsigned char flags; | |
1374 | ||
1375 | flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; | |
1376 | if (flags & STO_M68HC12_FAR) | |
1377 | MSYMBOL_SET_RTC (msym); | |
1378 | if (flags & STO_M68HC12_INTERRUPT) | |
1379 | MSYMBOL_SET_RTI (msym); | |
1380 | } | |
1381 | ||
ea3881d9 SC |
1382 | static int |
1383 | gdb_print_insn_m68hc11 (bfd_vma memaddr, disassemble_info *info) | |
1384 | { | |
1385 | if (TARGET_ARCHITECTURE->arch == bfd_arch_m68hc11) | |
1386 | return print_insn_m68hc11 (memaddr, info); | |
1387 | else | |
1388 | return print_insn_m68hc12 (memaddr, info); | |
1389 | } | |
1390 | ||
b631436b SC |
1391 | \f |
1392 | ||
1393 | /* 68HC11/68HC12 register groups. | |
1394 | Identify real hard registers and soft registers used by gcc. */ | |
1395 | ||
1396 | static struct reggroup *m68hc11_soft_reggroup; | |
1397 | static struct reggroup *m68hc11_hard_reggroup; | |
1398 | ||
1399 | static void | |
1400 | m68hc11_init_reggroups (void) | |
1401 | { | |
1402 | m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); | |
1403 | m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); | |
1404 | } | |
1405 | ||
1406 | static void | |
1407 | m68hc11_add_reggroups (struct gdbarch *gdbarch) | |
1408 | { | |
1409 | reggroup_add (gdbarch, m68hc11_hard_reggroup); | |
1410 | reggroup_add (gdbarch, m68hc11_soft_reggroup); | |
1411 | reggroup_add (gdbarch, general_reggroup); | |
1412 | reggroup_add (gdbarch, float_reggroup); | |
1413 | reggroup_add (gdbarch, all_reggroup); | |
1414 | reggroup_add (gdbarch, save_reggroup); | |
1415 | reggroup_add (gdbarch, restore_reggroup); | |
1416 | reggroup_add (gdbarch, vector_reggroup); | |
1417 | reggroup_add (gdbarch, system_reggroup); | |
1418 | } | |
1419 | ||
1420 | static int | |
1421 | m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1422 | struct reggroup *group) | |
1423 | { | |
1424 | /* We must save the real hard register as well as gcc | |
1425 | soft registers including the frame pointer. */ | |
1426 | if (group == save_reggroup || group == restore_reggroup) | |
1427 | { | |
1428 | return (regnum <= gdbarch_num_regs (gdbarch) | |
1429 | || ((regnum == SOFT_FP_REGNUM | |
1430 | || regnum == SOFT_TMP_REGNUM | |
1431 | || regnum == SOFT_ZS_REGNUM | |
1432 | || regnum == SOFT_XY_REGNUM) | |
1433 | && m68hc11_register_name (regnum))); | |
1434 | } | |
1435 | ||
1436 | /* Group to identify gcc soft registers (d1..dN). */ | |
1437 | if (group == m68hc11_soft_reggroup) | |
1438 | { | |
1439 | return regnum >= SOFT_D1_REGNUM && m68hc11_register_name (regnum); | |
1440 | } | |
1441 | ||
1442 | if (group == m68hc11_hard_reggroup) | |
1443 | { | |
1444 | return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM | |
1445 | || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM | |
1446 | || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; | |
1447 | } | |
1448 | return default_register_reggroup_p (gdbarch, regnum, group); | |
1449 | } | |
1450 | ||
82c230c2 SC |
1451 | static struct gdbarch * |
1452 | m68hc11_gdbarch_init (struct gdbarch_info info, | |
1453 | struct gdbarch_list *arches) | |
1454 | { | |
82c230c2 SC |
1455 | struct gdbarch *gdbarch; |
1456 | struct gdbarch_tdep *tdep; | |
81967506 | 1457 | int elf_flags; |
82c230c2 SC |
1458 | |
1459 | soft_reg_initialized = 0; | |
81967506 SC |
1460 | |
1461 | /* Extract the elf_flags if available. */ | |
1462 | if (info.abfd != NULL | |
1463 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1464 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1465 | else | |
1466 | elf_flags = 0; | |
1467 | ||
82c230c2 SC |
1468 | /* try to find a pre-existing architecture */ |
1469 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1470 | arches != NULL; | |
1471 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1472 | { | |
81967506 SC |
1473 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
1474 | continue; | |
1475 | ||
82c230c2 SC |
1476 | return arches->gdbarch; |
1477 | } | |
1478 | ||
1479 | /* Need a new architecture. Fill in a target specific vector. */ | |
1480 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
1481 | gdbarch = gdbarch_alloc (&info, tdep); | |
81967506 | 1482 | tdep->elf_flags = elf_flags; |
ed99b3d0 | 1483 | |
5d1a66bd SC |
1484 | switch (info.bfd_arch_info->arch) |
1485 | { | |
1486 | case bfd_arch_m68hc11: | |
1487 | tdep->stack_correction = 1; | |
7df11f59 | 1488 | tdep->use_page_register = 0; |
908f682f | 1489 | tdep->prologue = m6811_prologue; |
548bcbec SC |
1490 | set_gdbarch_addr_bit (gdbarch, 16); |
1491 | set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); | |
1492 | set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); | |
1493 | set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); | |
5d1a66bd | 1494 | break; |
82c230c2 | 1495 | |
5d1a66bd SC |
1496 | case bfd_arch_m68hc12: |
1497 | tdep->stack_correction = 0; | |
7df11f59 | 1498 | tdep->use_page_register = elf_flags & E_M68HC12_BANKS; |
908f682f | 1499 | tdep->prologue = m6812_prologue; |
548bcbec SC |
1500 | set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); |
1501 | set_gdbarch_num_pseudo_regs (gdbarch, | |
1502 | elf_flags & E_M68HC12_BANKS | |
1503 | ? M68HC12_NUM_PSEUDO_REGS | |
1504 | : M68HC11_NUM_PSEUDO_REGS); | |
1505 | set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS | |
1506 | ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); | |
1507 | set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS | |
1508 | ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); | |
5d1a66bd SC |
1509 | break; |
1510 | ||
1511 | default: | |
1512 | break; | |
1513 | } | |
7d32ba20 SC |
1514 | |
1515 | /* Initially set everything according to the ABI. | |
1516 | Use 16-bit integers since it will be the case for most | |
1517 | programs. The size of these types should normally be set | |
1518 | according to the dwarf2 debug information. */ | |
82c230c2 | 1519 | set_gdbarch_short_bit (gdbarch, 16); |
81967506 | 1520 | set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); |
82c230c2 | 1521 | set_gdbarch_float_bit (gdbarch, 32); |
81967506 | 1522 | set_gdbarch_double_bit (gdbarch, elf_flags & E_M68HC11_F64 ? 64 : 32); |
2417dd25 | 1523 | set_gdbarch_long_double_bit (gdbarch, 64); |
82c230c2 SC |
1524 | set_gdbarch_long_bit (gdbarch, 32); |
1525 | set_gdbarch_ptr_bit (gdbarch, 16); | |
1526 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1527 | ||
b2a02dda SC |
1528 | /* Characters are unsigned. */ |
1529 | set_gdbarch_char_signed (gdbarch, 0); | |
1530 | ||
1ea653ae SC |
1531 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); |
1532 | set_gdbarch_unwind_sp (gdbarch, m68hc11_unwind_sp); | |
1533 | ||
82c230c2 SC |
1534 | /* Set register info. */ |
1535 | set_gdbarch_fp0_regnum (gdbarch, -1); | |
82c230c2 SC |
1536 | set_gdbarch_frame_args_skip (gdbarch, 0); |
1537 | ||
82c230c2 | 1538 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
82c230c2 | 1539 | |
82c230c2 | 1540 | set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); |
82c230c2 | 1541 | set_gdbarch_register_name (gdbarch, m68hc11_register_name); |
4db73d49 | 1542 | set_gdbarch_register_type (gdbarch, m68hc11_register_type); |
46ce284d AC |
1543 | set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); |
1544 | set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); | |
82c230c2 | 1545 | |
3dc990bf SC |
1546 | set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); |
1547 | ||
ef2b8fcd | 1548 | set_gdbarch_extract_return_value (gdbarch, m68hc11_extract_return_value); |
82c230c2 SC |
1549 | set_gdbarch_return_value_on_stack (gdbarch, m68hc11_return_value_on_stack); |
1550 | ||
4db73d49 SC |
1551 | set_gdbarch_store_return_value (gdbarch, m68hc11_store_return_value); |
1552 | set_gdbarch_extract_struct_value_address (gdbarch, m68hc11_extract_struct_value_address); | |
82c230c2 | 1553 | |
0880807f AC |
1554 | set_gdbarch_store_return_value (gdbarch, m68hc11_store_return_value); |
1555 | set_gdbarch_extract_struct_value_address (gdbarch, m68hc11_extract_struct_value_address); | |
82c230c2 | 1556 | set_gdbarch_use_struct_convention (gdbarch, m68hc11_use_struct_convention); |
82c230c2 SC |
1557 | set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); |
1558 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1559 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
1560 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1561 | set_gdbarch_breakpoint_from_pc (gdbarch, m68hc11_breakpoint_from_pc); | |
f27dd7fd | 1562 | set_gdbarch_deprecated_stack_align (gdbarch, m68hc11_stack_align); |
70ed8774 | 1563 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_m68hc11); |
82c230c2 | 1564 | |
b631436b SC |
1565 | m68hc11_add_reggroups (gdbarch); |
1566 | set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); | |
e286caf2 | 1567 | set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); |
b631436b | 1568 | |
1ea653ae SC |
1569 | /* Hook in the DWARF CFI frame unwinder. */ |
1570 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
1ea653ae | 1571 | |
1a241548 | 1572 | frame_unwind_append_sniffer (gdbarch, m68hc11_frame_sniffer); |
1ea653ae SC |
1573 | frame_base_set_default (gdbarch, &m68hc11_frame_base); |
1574 | ||
1575 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1576 | stack address must match the SP value returned by | |
1577 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1578 | set_gdbarch_unwind_dummy_id (gdbarch, m68hc11_unwind_dummy_id); | |
1579 | ||
1580 | /* Return the unwound PC value. */ | |
1581 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); | |
1582 | ||
7df11f59 SC |
1583 | /* Minsymbol frobbing. */ |
1584 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
1585 | m68hc11_elf_make_msymbol_special); | |
1586 | ||
82c230c2 | 1587 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
82c230c2 SC |
1588 | |
1589 | return gdbarch; | |
78073dd8 AC |
1590 | } |
1591 | ||
a78f21af AC |
1592 | extern initialize_file_ftype _initialize_m68hc11_tdep; /* -Wmissing-prototypes */ |
1593 | ||
78073dd8 | 1594 | void |
fba45db2 | 1595 | _initialize_m68hc11_tdep (void) |
78073dd8 | 1596 | { |
82c230c2 | 1597 | register_gdbarch_init (bfd_arch_m68hc11, m68hc11_gdbarch_init); |
ea3881d9 | 1598 | register_gdbarch_init (bfd_arch_m68hc12, m68hc11_gdbarch_init); |
b631436b | 1599 | m68hc11_init_reggroups (); |
78073dd8 | 1600 | |
e286caf2 SC |
1601 | deprecate_cmd (add_com ("regs", class_vars, show_regs, |
1602 | "Print all registers"), | |
1603 | "info registers"); | |
78073dd8 AC |
1604 | } |
1605 |