Commit | Line | Data |
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908f682f | 1 | /* Target-dependent code for Motorola 68HC11 & 68HC12 |
51603483 | 2 | Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
ffe1f3ee | 3 | Contributed by Stephane Carrez, stcarrez@nerim.fr |
78073dd8 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
78073dd8 | 21 | |
82c230c2 SC |
22 | #include "defs.h" |
23 | #include "frame.h" | |
1ea653ae SC |
24 | #include "frame-unwind.h" |
25 | #include "frame-base.h" | |
26 | #include "dwarf2-frame.h" | |
27 | #include "trad-frame.h" | |
82c230c2 SC |
28 | #include "symtab.h" |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdb_string.h" | |
33 | #include "value.h" | |
34 | #include "inferior.h" | |
35 | #include "dis-asm.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "arch-utils.h" | |
4e052eda | 39 | #include "regcache.h" |
b631436b | 40 | #include "reggroups.h" |
78073dd8 | 41 | |
82c230c2 SC |
42 | #include "target.h" |
43 | #include "opcode/m68hc11.h" | |
81967506 SC |
44 | #include "elf/m68hc11.h" |
45 | #include "elf-bfd.h" | |
78073dd8 | 46 | |
7df11f59 SC |
47 | /* Macros for setting and testing a bit in a minimal symbol. |
48 | For 68HC11/68HC12 we have two flags that tell which return | |
49 | type the function is using. This is used for prologue and frame | |
50 | analysis to compute correct stack frame layout. | |
51 | ||
52 | The MSB of the minimal symbol's "info" field is used for this purpose. | |
53 | This field is already being used to store the symbol size, so the | |
54 | assumption is that the symbol size cannot exceed 2^30. | |
55 | ||
56 | MSYMBOL_SET_RTC Actually sets the "RTC" bit. | |
57 | MSYMBOL_SET_RTI Actually sets the "RTI" bit. | |
58 | MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. | |
59 | MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. | |
60 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
61 | i.e. the "info" field with the "special" bit | |
62 | masked out. */ | |
63 | ||
64 | #define MSYMBOL_SET_RTC(msym) \ | |
65 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
66 | | 0x80000000) | |
67 | ||
68 | #define MSYMBOL_SET_RTI(msym) \ | |
69 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
70 | | 0x40000000) | |
71 | ||
72 | #define MSYMBOL_IS_RTC(msym) \ | |
73 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
74 | ||
75 | #define MSYMBOL_IS_RTI(msym) \ | |
76 | (((long) MSYMBOL_INFO (msym) & 0x40000000) != 0) | |
77 | ||
78 | #define MSYMBOL_SIZE(msym) \ | |
79 | ((long) MSYMBOL_INFO (msym) & 0x3fffffff) | |
80 | ||
81 | enum insn_return_kind { | |
82 | RETURN_RTS, | |
83 | RETURN_RTC, | |
84 | RETURN_RTI | |
85 | }; | |
86 | ||
87 | ||
78073dd8 AC |
88 | /* Register numbers of various important registers. |
89 | Note that some of these values are "real" register numbers, | |
90 | and correspond to the general registers of the machine, | |
91 | and some are "phony" register numbers which are too large | |
92 | to be actual register numbers as far as the user is concerned | |
93 | but do serve to get the desired values when passed to read_register. */ | |
94 | ||
82c230c2 SC |
95 | #define HARD_X_REGNUM 0 |
96 | #define HARD_D_REGNUM 1 | |
97 | #define HARD_Y_REGNUM 2 | |
98 | #define HARD_SP_REGNUM 3 | |
99 | #define HARD_PC_REGNUM 4 | |
100 | ||
101 | #define HARD_A_REGNUM 5 | |
102 | #define HARD_B_REGNUM 6 | |
103 | #define HARD_CCR_REGNUM 7 | |
5706502a SC |
104 | |
105 | /* 68HC12 page number register. | |
106 | Note: to keep a compatibility with gcc register naming, we must | |
107 | not have to rename FP and other soft registers. The page register | |
108 | is a real hard register and must therefore be counted by NUM_REGS. | |
109 | For this it has the same number as Z register (which is not used). */ | |
110 | #define HARD_PAGE_REGNUM 8 | |
111 | #define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) | |
82c230c2 SC |
112 | |
113 | /* Z is replaced by X or Y by gcc during machine reorg. | |
114 | ??? There is no way to get it and even know whether | |
115 | it's in X or Y or in ZS. */ | |
116 | #define SOFT_Z_REGNUM 8 | |
117 | ||
118 | /* Soft registers. These registers are special. There are treated | |
119 | like normal hard registers by gcc and gdb (ie, within dwarf2 info). | |
120 | They are physically located in memory. */ | |
121 | #define SOFT_FP_REGNUM 9 | |
122 | #define SOFT_TMP_REGNUM 10 | |
123 | #define SOFT_ZS_REGNUM 11 | |
124 | #define SOFT_XY_REGNUM 12 | |
f91a8b6b SC |
125 | #define SOFT_UNUSED_REGNUM 13 |
126 | #define SOFT_D1_REGNUM 14 | |
82c230c2 SC |
127 | #define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) |
128 | #define M68HC11_MAX_SOFT_REGS 32 | |
129 | ||
130 | #define M68HC11_NUM_REGS (8) | |
131 | #define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) | |
132 | #define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) | |
133 | ||
134 | #define M68HC11_REG_SIZE (2) | |
135 | ||
548bcbec SC |
136 | #define M68HC12_NUM_REGS (9) |
137 | #define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) | |
138 | #define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) | |
139 | ||
908f682f | 140 | struct insn_sequence; |
82c230c2 SC |
141 | struct gdbarch_tdep |
142 | { | |
5d1a66bd SC |
143 | /* Stack pointer correction value. For 68hc11, the stack pointer points |
144 | to the next push location. An offset of 1 must be applied to obtain | |
145 | the address where the last value is saved. For 68hc12, the stack | |
146 | pointer points to the last value pushed. No offset is necessary. */ | |
147 | int stack_correction; | |
908f682f SC |
148 | |
149 | /* Description of instructions in the prologue. */ | |
150 | struct insn_sequence *prologue; | |
81967506 | 151 | |
7df11f59 SC |
152 | /* True if the page memory bank register is available |
153 | and must be used. */ | |
154 | int use_page_register; | |
155 | ||
81967506 SC |
156 | /* ELF flags for ABI. */ |
157 | int elf_flags; | |
82c230c2 SC |
158 | }; |
159 | ||
5d1a66bd SC |
160 | #define M6811_TDEP gdbarch_tdep (current_gdbarch) |
161 | #define STACK_CORRECTION (M6811_TDEP->stack_correction) | |
7df11f59 | 162 | #define USE_PAGE_REGISTER (M6811_TDEP->use_page_register) |
5d1a66bd | 163 | |
1ea653ae SC |
164 | struct m68hc11_unwind_cache |
165 | { | |
166 | /* The previous frame's inner most stack address. Used as this | |
167 | frame ID's stack_addr. */ | |
168 | CORE_ADDR prev_sp; | |
169 | /* The frame's base, optionally used by the high-level debug info. */ | |
170 | CORE_ADDR base; | |
171 | CORE_ADDR pc; | |
172 | int size; | |
173 | int prologue_type; | |
174 | CORE_ADDR return_pc; | |
175 | CORE_ADDR sp_offset; | |
176 | int frameless; | |
177 | enum insn_return_kind return_kind; | |
178 | ||
179 | /* Table indicating the location of each and every register. */ | |
180 | struct trad_frame_saved_reg *saved_regs; | |
181 | }; | |
182 | ||
82c230c2 SC |
183 | /* Table of registers for 68HC11. This includes the hard registers |
184 | and the soft registers used by GCC. */ | |
185 | static char * | |
186 | m68hc11_register_names[] = | |
187 | { | |
188 | "x", "d", "y", "sp", "pc", "a", "b", | |
5706502a | 189 | "ccr", "page", "frame","tmp", "zs", "xy", 0, |
82c230c2 SC |
190 | "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
191 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", | |
192 | "d15", "d16", "d17", "d18", "d19", "d20", "d21", | |
193 | "d22", "d23", "d24", "d25", "d26", "d27", "d28", | |
194 | "d29", "d30", "d31", "d32" | |
195 | }; | |
78073dd8 | 196 | |
82c230c2 SC |
197 | struct m68hc11_soft_reg |
198 | { | |
199 | const char *name; | |
200 | CORE_ADDR addr; | |
201 | }; | |
78073dd8 | 202 | |
82c230c2 | 203 | static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; |
78073dd8 | 204 | |
82c230c2 | 205 | #define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr |
78073dd8 | 206 | |
82c230c2 SC |
207 | static int soft_min_addr; |
208 | static int soft_max_addr; | |
209 | static int soft_reg_initialized = 0; | |
78073dd8 | 210 | |
82c230c2 SC |
211 | /* Look in the symbol table for the address of a pseudo register |
212 | in memory. If we don't find it, pretend the register is not used | |
213 | and not available. */ | |
214 | static void | |
215 | m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) | |
216 | { | |
217 | struct minimal_symbol *msymbol; | |
78073dd8 | 218 | |
82c230c2 SC |
219 | msymbol = lookup_minimal_symbol (name, NULL, NULL); |
220 | if (msymbol) | |
221 | { | |
222 | reg->addr = SYMBOL_VALUE_ADDRESS (msymbol); | |
223 | reg->name = xstrdup (name); | |
224 | ||
225 | /* Keep track of the address range for soft registers. */ | |
226 | if (reg->addr < (CORE_ADDR) soft_min_addr) | |
227 | soft_min_addr = reg->addr; | |
228 | if (reg->addr > (CORE_ADDR) soft_max_addr) | |
229 | soft_max_addr = reg->addr; | |
230 | } | |
231 | else | |
232 | { | |
233 | reg->name = 0; | |
234 | reg->addr = 0; | |
235 | } | |
236 | } | |
78073dd8 | 237 | |
82c230c2 SC |
238 | /* Initialize the table of soft register addresses according |
239 | to the symbol table. */ | |
240 | static void | |
241 | m68hc11_initialize_register_info (void) | |
242 | { | |
243 | int i; | |
78073dd8 | 244 | |
82c230c2 SC |
245 | if (soft_reg_initialized) |
246 | return; | |
247 | ||
248 | soft_min_addr = INT_MAX; | |
249 | soft_max_addr = 0; | |
250 | for (i = 0; i < M68HC11_ALL_REGS; i++) | |
251 | { | |
252 | soft_regs[i].name = 0; | |
253 | } | |
254 | ||
255 | m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); | |
256 | m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); | |
257 | m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); | |
258 | soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; | |
259 | m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); | |
78073dd8 | 260 | |
82c230c2 SC |
261 | for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) |
262 | { | |
263 | char buf[10]; | |
78073dd8 | 264 | |
82c230c2 SC |
265 | sprintf (buf, "_.d%d", i - SOFT_D1_REGNUM + 1); |
266 | m68hc11_get_register_info (&soft_regs[i], buf); | |
267 | } | |
78073dd8 | 268 | |
82c230c2 SC |
269 | if (soft_regs[SOFT_FP_REGNUM].name == 0) |
270 | { | |
271 | warning ("No frame soft register found in the symbol table.\n"); | |
272 | warning ("Stack backtrace will not work.\n"); | |
273 | } | |
274 | soft_reg_initialized = 1; | |
275 | } | |
78073dd8 | 276 | |
82c230c2 SC |
277 | /* Given an address in memory, return the soft register number if |
278 | that address corresponds to a soft register. Returns -1 if not. */ | |
279 | static int | |
280 | m68hc11_which_soft_register (CORE_ADDR addr) | |
281 | { | |
282 | int i; | |
283 | ||
284 | if (addr < soft_min_addr || addr > soft_max_addr) | |
285 | return -1; | |
286 | ||
287 | for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) | |
288 | { | |
289 | if (soft_regs[i].name && soft_regs[i].addr == addr) | |
290 | return i; | |
291 | } | |
292 | return -1; | |
293 | } | |
78073dd8 | 294 | |
82c230c2 SC |
295 | /* Fetch a pseudo register. The 68hc11 soft registers are treated like |
296 | pseudo registers. They are located in memory. Translate the register | |
297 | fetch into a memory read. */ | |
46ce284d AC |
298 | static void |
299 | m68hc11_pseudo_register_read (struct gdbarch *gdbarch, | |
300 | struct regcache *regcache, | |
301 | int regno, void *buf) | |
82c230c2 | 302 | { |
548bcbec SC |
303 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
304 | addressing mode. */ | |
305 | if (regno == M68HC12_HARD_PC_REGNUM) | |
306 | { | |
4db73d49 | 307 | ULONGEST pc; |
548bcbec | 308 | const int regsize = TYPE_LENGTH (builtin_type_uint32); |
548bcbec | 309 | |
4db73d49 | 310 | regcache_cooked_read_unsigned (regcache, HARD_PC_REGNUM, &pc); |
548bcbec SC |
311 | if (pc >= 0x8000 && pc < 0xc000) |
312 | { | |
4db73d49 SC |
313 | ULONGEST page; |
314 | ||
315 | regcache_cooked_read_unsigned (regcache, HARD_PAGE_REGNUM, &page); | |
548bcbec SC |
316 | pc -= 0x8000; |
317 | pc += (page << 14); | |
318 | pc += 0x1000000; | |
319 | } | |
320 | store_unsigned_integer (buf, regsize, pc); | |
321 | return; | |
322 | } | |
323 | ||
82c230c2 SC |
324 | m68hc11_initialize_register_info (); |
325 | ||
326 | /* Fetch a soft register: translate into a memory read. */ | |
327 | if (soft_regs[regno].name) | |
328 | { | |
329 | target_read_memory (soft_regs[regno].addr, buf, 2); | |
330 | } | |
331 | else | |
332 | { | |
333 | memset (buf, 0, 2); | |
334 | } | |
82c230c2 | 335 | } |
78073dd8 | 336 | |
82c230c2 SC |
337 | /* Store a pseudo register. Translate the register store |
338 | into a memory write. */ | |
339 | static void | |
46ce284d AC |
340 | m68hc11_pseudo_register_write (struct gdbarch *gdbarch, |
341 | struct regcache *regcache, | |
342 | int regno, const void *buf) | |
82c230c2 | 343 | { |
548bcbec SC |
344 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
345 | addressing mode. */ | |
346 | if (regno == M68HC12_HARD_PC_REGNUM) | |
347 | { | |
348 | const int regsize = TYPE_LENGTH (builtin_type_uint32); | |
349 | char *tmp = alloca (regsize); | |
350 | CORE_ADDR pc; | |
351 | ||
352 | memcpy (tmp, buf, regsize); | |
353 | pc = extract_unsigned_integer (tmp, regsize); | |
354 | if (pc >= 0x1000000) | |
355 | { | |
356 | pc -= 0x1000000; | |
4db73d49 SC |
357 | regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, |
358 | (pc >> 14) & 0x0ff); | |
548bcbec | 359 | pc &= 0x03fff; |
4db73d49 SC |
360 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, |
361 | pc + 0x8000); | |
548bcbec SC |
362 | } |
363 | else | |
4db73d49 | 364 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); |
548bcbec SC |
365 | return; |
366 | } | |
367 | ||
82c230c2 | 368 | m68hc11_initialize_register_info (); |
78073dd8 | 369 | |
82c230c2 SC |
370 | /* Store a soft register: translate into a memory write. */ |
371 | if (soft_regs[regno].name) | |
372 | { | |
46ce284d AC |
373 | const int regsize = 2; |
374 | char *tmp = alloca (regsize); | |
375 | memcpy (tmp, buf, regsize); | |
376 | target_write_memory (soft_regs[regno].addr, tmp, regsize); | |
82c230c2 SC |
377 | } |
378 | } | |
78073dd8 | 379 | |
fa88f677 | 380 | static const char * |
82c230c2 | 381 | m68hc11_register_name (int reg_nr) |
78073dd8 | 382 | { |
548bcbec SC |
383 | if (reg_nr == M68HC12_HARD_PC_REGNUM && USE_PAGE_REGISTER) |
384 | return "pc"; | |
385 | if (reg_nr == HARD_PC_REGNUM && USE_PAGE_REGISTER) | |
386 | return "ppc"; | |
387 | ||
82c230c2 SC |
388 | if (reg_nr < 0) |
389 | return NULL; | |
390 | if (reg_nr >= M68HC11_ALL_REGS) | |
391 | return NULL; | |
392 | ||
393 | /* If we don't know the address of a soft register, pretend it | |
394 | does not exist. */ | |
395 | if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) | |
396 | return NULL; | |
397 | return m68hc11_register_names[reg_nr]; | |
398 | } | |
78073dd8 | 399 | |
f4f9705a | 400 | static const unsigned char * |
82c230c2 | 401 | m68hc11_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
78073dd8 | 402 | { |
82c230c2 SC |
403 | static unsigned char breakpoint[] = {0x0}; |
404 | ||
405 | *lenptr = sizeof (breakpoint); | |
406 | return breakpoint; | |
78073dd8 AC |
407 | } |
408 | ||
908f682f SC |
409 | \f |
410 | /* 68HC11 & 68HC12 prologue analysis. | |
411 | ||
412 | */ | |
413 | #define MAX_CODES 12 | |
414 | ||
415 | /* 68HC11 opcodes. */ | |
416 | #undef M6811_OP_PAGE2 | |
b94a41a1 SC |
417 | #define M6811_OP_PAGE2 (0x18) |
418 | #define M6811_OP_LDX (0xde) | |
419 | #define M6811_OP_LDX_EXT (0xfe) | |
420 | #define M6811_OP_PSHX (0x3c) | |
421 | #define M6811_OP_STS (0x9f) | |
422 | #define M6811_OP_STS_EXT (0xbf) | |
423 | #define M6811_OP_TSX (0x30) | |
424 | #define M6811_OP_XGDX (0x8f) | |
425 | #define M6811_OP_ADDD (0xc3) | |
426 | #define M6811_OP_TXS (0x35) | |
427 | #define M6811_OP_DES (0x34) | |
908f682f SC |
428 | |
429 | /* 68HC12 opcodes. */ | |
b94a41a1 SC |
430 | #define M6812_OP_PAGE2 (0x18) |
431 | #define M6812_OP_MOVW (0x01) | |
432 | #define M6812_PB_PSHW (0xae) | |
433 | #define M6812_OP_STS (0x5f) | |
434 | #define M6812_OP_STS_EXT (0x7f) | |
435 | #define M6812_OP_LEAS (0x1b) | |
436 | #define M6812_OP_PSHX (0x34) | |
437 | #define M6812_OP_PSHY (0x35) | |
908f682f SC |
438 | |
439 | /* Operand extraction. */ | |
440 | #define OP_DIRECT (0x100) /* 8-byte direct addressing. */ | |
441 | #define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ | |
442 | #define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ | |
443 | #define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ | |
444 | ||
445 | /* Identification of the sequence. */ | |
446 | enum m6811_seq_type | |
447 | { | |
448 | P_LAST = 0, | |
449 | P_SAVE_REG, /* Save a register on the stack. */ | |
450 | P_SET_FRAME, /* Setup the frame pointer. */ | |
451 | P_LOCAL_1, /* Allocate 1 byte for locals. */ | |
452 | P_LOCAL_2, /* Allocate 2 bytes for locals. */ | |
453 | P_LOCAL_N /* Allocate N bytes for locals. */ | |
454 | }; | |
455 | ||
456 | struct insn_sequence { | |
457 | enum m6811_seq_type type; | |
458 | unsigned length; | |
459 | unsigned short code[MAX_CODES]; | |
460 | }; | |
461 | ||
462 | /* Sequence of instructions in the 68HC11 function prologue. */ | |
463 | static struct insn_sequence m6811_prologue[] = { | |
464 | /* Sequences to save a soft-register. */ | |
465 | { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, | |
466 | M6811_OP_PSHX } }, | |
467 | { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, | |
468 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
b94a41a1 SC |
469 | { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
470 | M6811_OP_PSHX } }, | |
471 | { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, | |
472 | M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
908f682f SC |
473 | |
474 | /* Sequences to allocate local variables. */ | |
475 | { P_LOCAL_N, 7, { M6811_OP_TSX, | |
476 | M6811_OP_XGDX, | |
477 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
478 | M6811_OP_XGDX, | |
479 | M6811_OP_TXS } }, | |
480 | { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, | |
481 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
482 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
483 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
484 | M6811_OP_PAGE2, M6811_OP_TXS } }, | |
485 | { P_LOCAL_1, 1, { M6811_OP_DES } }, | |
486 | { P_LOCAL_2, 1, { M6811_OP_PSHX } }, | |
487 | { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
488 | ||
489 | /* Initialize the frame pointer. */ | |
490 | { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, | |
b94a41a1 | 491 | { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, |
908f682f SC |
492 | { P_LAST, 0, { 0 } } |
493 | }; | |
494 | ||
495 | ||
496 | /* Sequence of instructions in the 68HC12 function prologue. */ | |
497 | static struct insn_sequence m6812_prologue[] = { | |
498 | { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, | |
499 | OP_IMM_HIGH, OP_IMM_LOW } }, | |
b94a41a1 SC |
500 | { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, |
501 | { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, | |
908f682f | 502 | { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, |
ffe1f3ee SC |
503 | { P_LOCAL_2, 1, { M6812_OP_PSHX } }, |
504 | { P_LOCAL_2, 1, { M6812_OP_PSHY } }, | |
908f682f SC |
505 | { P_LAST, 0 } |
506 | }; | |
507 | ||
508 | ||
509 | /* Analyze the sequence of instructions starting at the given address. | |
510 | Returns a pointer to the sequence when it is recognized and | |
c8a7f6ac | 511 | the optional value (constant/address) associated with it. */ |
908f682f | 512 | static struct insn_sequence * |
c8a7f6ac | 513 | m68hc11_analyze_instruction (struct insn_sequence *seq, CORE_ADDR pc, |
908f682f SC |
514 | CORE_ADDR *val) |
515 | { | |
516 | unsigned char buffer[MAX_CODES]; | |
517 | unsigned bufsize; | |
518 | unsigned j; | |
519 | CORE_ADDR cur_val; | |
520 | short v = 0; | |
521 | ||
522 | bufsize = 0; | |
523 | for (; seq->type != P_LAST; seq++) | |
524 | { | |
525 | cur_val = 0; | |
526 | for (j = 0; j < seq->length; j++) | |
527 | { | |
528 | if (bufsize < j + 1) | |
529 | { | |
c8a7f6ac | 530 | buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, |
908f682f SC |
531 | 1); |
532 | bufsize++; | |
533 | } | |
534 | /* Continue while we match the opcode. */ | |
535 | if (seq->code[j] == buffer[j]) | |
536 | continue; | |
537 | ||
538 | if ((seq->code[j] & 0xf00) == 0) | |
539 | break; | |
540 | ||
541 | /* Extract a sequence parameter (address or constant). */ | |
542 | switch (seq->code[j]) | |
543 | { | |
544 | case OP_DIRECT: | |
545 | cur_val = (CORE_ADDR) buffer[j]; | |
546 | break; | |
547 | ||
548 | case OP_IMM_HIGH: | |
549 | cur_val = cur_val & 0x0ff; | |
550 | cur_val |= (buffer[j] << 8); | |
551 | break; | |
552 | ||
553 | case OP_IMM_LOW: | |
554 | cur_val &= 0x0ff00; | |
555 | cur_val |= buffer[j]; | |
556 | break; | |
557 | ||
558 | case OP_PBYTE: | |
559 | if ((buffer[j] & 0xE0) == 0x80) | |
560 | { | |
561 | v = buffer[j] & 0x1f; | |
562 | if (v & 0x10) | |
563 | v |= 0xfff0; | |
564 | } | |
565 | else if ((buffer[j] & 0xfe) == 0xf0) | |
566 | { | |
c8a7f6ac | 567 | v = read_memory_unsigned_integer (pc + j + 1, 1); |
908f682f SC |
568 | if (buffer[j] & 1) |
569 | v |= 0xff00; | |
570 | } | |
571 | else if (buffer[j] == 0xf2) | |
572 | { | |
c8a7f6ac | 573 | v = read_memory_unsigned_integer (pc + j + 1, 2); |
908f682f SC |
574 | } |
575 | cur_val = v; | |
576 | break; | |
577 | } | |
578 | } | |
579 | ||
580 | /* We have a full match. */ | |
581 | if (j == seq->length) | |
582 | { | |
583 | *val = cur_val; | |
908f682f SC |
584 | return seq; |
585 | } | |
586 | } | |
587 | return 0; | |
588 | } | |
589 | ||
7df11f59 SC |
590 | /* Return the instruction that the function at the PC is using. */ |
591 | static enum insn_return_kind | |
592 | m68hc11_get_return_insn (CORE_ADDR pc) | |
593 | { | |
594 | struct minimal_symbol *sym; | |
595 | ||
596 | /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT | |
597 | function is stored by elfread.c in the high bit of the info field. | |
598 | Use this to decide which instruction the function uses to return. */ | |
599 | sym = lookup_minimal_symbol_by_pc (pc); | |
600 | if (sym == 0) | |
601 | return RETURN_RTS; | |
602 | ||
603 | if (MSYMBOL_IS_RTC (sym)) | |
604 | return RETURN_RTC; | |
605 | else if (MSYMBOL_IS_RTI (sym)) | |
606 | return RETURN_RTI; | |
607 | else | |
608 | return RETURN_RTS; | |
609 | } | |
610 | ||
78073dd8 AC |
611 | /* Analyze the function prologue to find some information |
612 | about the function: | |
613 | - the PC of the first line (for m68hc11_skip_prologue) | |
614 | - the offset of the previous frame saved address (from current frame) | |
615 | - the soft registers which are pushed. */ | |
1ea653ae SC |
616 | static CORE_ADDR |
617 | m68hc11_scan_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
618 | struct m68hc11_unwind_cache *info) | |
78073dd8 | 619 | { |
1ea653ae | 620 | LONGEST save_addr; |
78073dd8 | 621 | CORE_ADDR func_end; |
78073dd8 AC |
622 | int size; |
623 | int found_frame_point; | |
82c230c2 | 624 | int saved_reg; |
908f682f SC |
625 | int done = 0; |
626 | struct insn_sequence *seq_table; | |
1ea653ae SC |
627 | |
628 | info->size = 0; | |
629 | info->sp_offset = 0; | |
630 | if (pc >= current_pc) | |
631 | return current_pc; | |
632 | ||
78073dd8 AC |
633 | size = 0; |
634 | ||
82c230c2 | 635 | m68hc11_initialize_register_info (); |
1ea653ae | 636 | if (pc == 0) |
78073dd8 | 637 | { |
1ea653ae SC |
638 | info->size = 0; |
639 | return pc; | |
78073dd8 AC |
640 | } |
641 | ||
908f682f SC |
642 | seq_table = gdbarch_tdep (current_gdbarch)->prologue; |
643 | ||
78073dd8 AC |
644 | /* The 68hc11 stack is as follows: |
645 | ||
646 | ||
647 | | | | |
648 | +-----------+ | |
649 | | | | |
650 | | args | | |
651 | | | | |
652 | +-----------+ | |
653 | | PC-return | | |
654 | +-----------+ | |
655 | | Old frame | | |
656 | +-----------+ | |
657 | | | | |
658 | | Locals | | |
659 | | | | |
660 | +-----------+ <--- current frame | |
661 | | | | |
662 | ||
663 | With most processors (like 68K) the previous frame can be computed | |
664 | easily because it is always at a fixed offset (see link/unlink). | |
665 | That is, locals are accessed with negative offsets, arguments are | |
666 | accessed with positive ones. Since 68hc11 only supports offsets | |
667 | in the range [0..255], the frame is defined at the bottom of | |
668 | locals (see picture). | |
669 | ||
670 | The purpose of the analysis made here is to find out the size | |
671 | of locals in this function. An alternative to this is to use | |
672 | DWARF2 info. This would be better but I don't know how to | |
673 | access dwarf2 debug from this function. | |
674 | ||
675 | Walk from the function entry point to the point where we save | |
676 | the frame. While walking instructions, compute the size of bytes | |
677 | which are pushed. This gives us the index to access the previous | |
678 | frame. | |
679 | ||
680 | We limit the search to 128 bytes so that the algorithm is bounded | |
681 | in case of random and wrong code. We also stop and abort if | |
682 | we find an instruction which is not supposed to appear in the | |
683 | prologue (as generated by gcc 2.95, 2.96). | |
684 | */ | |
78073dd8 | 685 | func_end = pc + 128; |
78073dd8 | 686 | found_frame_point = 0; |
1ea653ae SC |
687 | info->size = 0; |
688 | save_addr = 0; | |
908f682f | 689 | while (!done && pc + 2 < func_end) |
78073dd8 | 690 | { |
908f682f SC |
691 | struct insn_sequence *seq; |
692 | CORE_ADDR val; | |
1ea653ae | 693 | |
c8a7f6ac | 694 | seq = m68hc11_analyze_instruction (seq_table, pc, &val); |
908f682f SC |
695 | if (seq == 0) |
696 | break; | |
78073dd8 | 697 | |
c8a7f6ac SC |
698 | /* If we are within the instruction group, we can't advance the |
699 | pc nor the stack offset. Otherwise the caller's stack computed | |
700 | from the current stack can be wrong. */ | |
701 | if (pc + seq->length > current_pc) | |
702 | break; | |
703 | ||
704 | pc = pc + seq->length; | |
908f682f | 705 | if (seq->type == P_SAVE_REG) |
78073dd8 | 706 | { |
908f682f SC |
707 | if (found_frame_point) |
708 | { | |
709 | saved_reg = m68hc11_which_soft_register (val); | |
710 | if (saved_reg < 0) | |
711 | break; | |
78073dd8 | 712 | |
908f682f | 713 | save_addr -= 2; |
1ea653ae | 714 | info->saved_regs[saved_reg].addr = save_addr; |
908f682f SC |
715 | } |
716 | else | |
717 | { | |
718 | size += 2; | |
719 | } | |
78073dd8 | 720 | } |
908f682f | 721 | else if (seq->type == P_SET_FRAME) |
78073dd8 AC |
722 | { |
723 | found_frame_point = 1; | |
1ea653ae | 724 | info->size = size; |
78073dd8 | 725 | } |
908f682f | 726 | else if (seq->type == P_LOCAL_1) |
78073dd8 | 727 | { |
6148eca7 SC |
728 | size += 1; |
729 | } | |
908f682f | 730 | else if (seq->type == P_LOCAL_2) |
78073dd8 | 731 | { |
908f682f | 732 | size += 2; |
78073dd8 | 733 | } |
908f682f | 734 | else if (seq->type == P_LOCAL_N) |
78073dd8 | 735 | { |
908f682f SC |
736 | /* Stack pointer is decremented for the allocation. */ |
737 | if (val & 0x8000) | |
738 | size -= (int) (val) | 0xffff0000; | |
739 | else | |
740 | size -= val; | |
78073dd8 AC |
741 | } |
742 | } | |
1ea653ae SC |
743 | if (found_frame_point == 0) |
744 | info->sp_offset = size; | |
745 | else | |
746 | info->sp_offset = -1; | |
747 | return pc; | |
78073dd8 AC |
748 | } |
749 | ||
82c230c2 | 750 | static CORE_ADDR |
78073dd8 AC |
751 | m68hc11_skip_prologue (CORE_ADDR pc) |
752 | { | |
753 | CORE_ADDR func_addr, func_end; | |
754 | struct symtab_and_line sal; | |
1ea653ae | 755 | struct m68hc11_unwind_cache tmp_cache = { 0 }; |
78073dd8 | 756 | |
82c230c2 SC |
757 | /* If we have line debugging information, then the end of the |
758 | prologue should be the first assembly instruction of the | |
78073dd8 AC |
759 | first source line. */ |
760 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
761 | { | |
762 | sal = find_pc_line (func_addr, 0); | |
763 | if (sal.end && sal.end < func_end) | |
764 | return sal.end; | |
765 | } | |
766 | ||
1ea653ae | 767 | pc = m68hc11_scan_prologue (pc, (CORE_ADDR) -1, &tmp_cache); |
78073dd8 AC |
768 | return pc; |
769 | } | |
770 | ||
1ea653ae SC |
771 | static CORE_ADDR |
772 | m68hc11_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
773 | { | |
774 | ULONGEST pc; | |
775 | ||
776 | frame_unwind_unsigned_register (next_frame, gdbarch_pc_regnum (gdbarch), | |
777 | &pc); | |
778 | return pc; | |
779 | } | |
780 | ||
781 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
782 | the saved registers of frame described by FRAME_INFO. This | |
783 | includes special registers such as pc and fp saved in special ways | |
784 | in the stack frame. sp is even more special: the address we return | |
785 | for it IS the sp for the next frame. */ | |
786 | ||
787 | struct m68hc11_unwind_cache * | |
788 | m68hc11_frame_unwind_cache (struct frame_info *next_frame, | |
789 | void **this_prologue_cache) | |
790 | { | |
791 | ULONGEST prev_sp; | |
792 | ULONGEST this_base; | |
793 | struct m68hc11_unwind_cache *info; | |
794 | CORE_ADDR current_pc; | |
795 | int i; | |
796 | ||
797 | if ((*this_prologue_cache)) | |
798 | return (*this_prologue_cache); | |
799 | ||
800 | info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); | |
801 | (*this_prologue_cache) = info; | |
802 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
803 | ||
804 | info->pc = frame_func_unwind (next_frame); | |
805 | ||
806 | info->size = 0; | |
807 | info->return_kind = m68hc11_get_return_insn (info->pc); | |
808 | ||
809 | /* The SP was moved to the FP. This indicates that a new frame | |
810 | was created. Get THIS frame's FP value by unwinding it from | |
811 | the next frame. */ | |
812 | frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &this_base); | |
813 | if (this_base == 0) | |
814 | { | |
815 | info->base = 0; | |
816 | return info; | |
817 | } | |
818 | ||
819 | current_pc = frame_pc_unwind (next_frame); | |
820 | if (info->pc != 0) | |
821 | m68hc11_scan_prologue (info->pc, current_pc, info); | |
822 | ||
823 | info->saved_regs[HARD_PC_REGNUM].addr = info->size; | |
824 | ||
825 | if (info->sp_offset != (CORE_ADDR) -1) | |
826 | { | |
827 | info->saved_regs[HARD_PC_REGNUM].addr = info->sp_offset; | |
828 | frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &this_base); | |
829 | prev_sp = this_base + info->sp_offset + 2; | |
830 | this_base += STACK_CORRECTION; | |
831 | } | |
832 | else | |
833 | { | |
834 | /* The FP points at the last saved register. Adjust the FP back | |
835 | to before the first saved register giving the SP. */ | |
836 | prev_sp = this_base + info->size + 2; | |
837 | ||
838 | this_base += STACK_CORRECTION; | |
839 | if (soft_regs[SOFT_FP_REGNUM].name) | |
840 | info->saved_regs[SOFT_FP_REGNUM].addr = info->size - 2; | |
841 | } | |
842 | ||
843 | if (info->return_kind == RETURN_RTC) | |
844 | { | |
845 | prev_sp += 1; | |
846 | info->saved_regs[HARD_PAGE_REGNUM].addr = info->size; | |
847 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 1; | |
848 | } | |
849 | else if (info->return_kind == RETURN_RTI) | |
850 | { | |
851 | prev_sp += 7; | |
852 | info->saved_regs[HARD_CCR_REGNUM].addr = info->size; | |
853 | info->saved_regs[HARD_D_REGNUM].addr = info->size + 1; | |
854 | info->saved_regs[HARD_X_REGNUM].addr = info->size + 3; | |
855 | info->saved_regs[HARD_Y_REGNUM].addr = info->size + 5; | |
856 | info->saved_regs[HARD_PC_REGNUM].addr = info->size + 7; | |
857 | } | |
858 | ||
859 | /* Add 1 here to adjust for the post-decrement nature of the push | |
860 | instruction.*/ | |
861 | info->prev_sp = prev_sp; | |
862 | ||
863 | info->base = this_base; | |
864 | ||
865 | /* Adjust all the saved registers so that they contain addresses and not | |
866 | offsets. */ | |
867 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS - 1; i++) | |
868 | if (trad_frame_addr_p (info->saved_regs, i)) | |
869 | { | |
870 | info->saved_regs[i].addr += this_base; | |
871 | } | |
872 | ||
873 | /* The previous frame's SP needed to be computed. Save the computed | |
874 | value. */ | |
875 | trad_frame_set_value (info->saved_regs, HARD_SP_REGNUM, info->prev_sp); | |
876 | ||
877 | return info; | |
878 | } | |
879 | ||
880 | /* Given a GDB frame, determine the address of the calling function's | |
881 | frame. This will be used to create a new GDB frame struct. */ | |
882 | ||
883 | static void | |
884 | m68hc11_frame_this_id (struct frame_info *next_frame, | |
885 | void **this_prologue_cache, | |
886 | struct frame_id *this_id) | |
887 | { | |
888 | struct m68hc11_unwind_cache *info | |
889 | = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); | |
890 | CORE_ADDR base; | |
891 | CORE_ADDR func; | |
892 | struct frame_id id; | |
893 | ||
894 | /* The FUNC is easy. */ | |
895 | func = frame_func_unwind (next_frame); | |
896 | ||
1ea653ae SC |
897 | /* Hopefully the prologue analysis either correctly determined the |
898 | frame's base (which is the SP from the previous frame), or set | |
899 | that base to "NULL". */ | |
900 | base = info->prev_sp; | |
901 | if (base == 0) | |
902 | return; | |
903 | ||
904 | id = frame_id_build (base, func); | |
905 | #if 0 | |
906 | /* Check that we're not going round in circles with the same frame | |
907 | ID (but avoid applying the test to sentinel frames which do go | |
908 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
909 | compare the frame's PC value. */ | |
910 | if (frame_relative_level (next_frame) >= 0 | |
911 | && get_frame_type (next_frame) != DUMMY_FRAME | |
912 | && frame_id_eq (get_frame_id (next_frame), id)) | |
913 | return; | |
914 | #endif | |
915 | (*this_id) = id; | |
916 | } | |
917 | ||
918 | static void | |
919 | m68hc11_frame_prev_register (struct frame_info *next_frame, | |
920 | void **this_prologue_cache, | |
921 | int regnum, int *optimizedp, | |
922 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
923 | int *realnump, void *bufferp) | |
924 | { | |
925 | struct m68hc11_unwind_cache *info | |
926 | = m68hc11_frame_unwind_cache (next_frame, this_prologue_cache); | |
927 | ||
928 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
929 | optimizedp, lvalp, addrp, realnump, bufferp); | |
930 | ||
931 | if (regnum == HARD_PC_REGNUM) | |
932 | { | |
933 | /* Take into account the 68HC12 specific call (PC + page). */ | |
934 | if (info->return_kind == RETURN_RTC | |
935 | && *addrp >= 0x08000 && *addrp < 0x0c000 | |
936 | && USE_PAGE_REGISTER) | |
937 | { | |
938 | int page_optimized; | |
939 | ||
940 | CORE_ADDR page; | |
941 | ||
942 | trad_frame_prev_register (next_frame, info->saved_regs, | |
943 | HARD_PAGE_REGNUM, &page_optimized, | |
944 | 0, &page, 0, 0); | |
945 | *addrp -= 0x08000; | |
946 | *addrp += ((page & 0x0ff) << 14); | |
947 | *addrp += 0x1000000; | |
948 | } | |
949 | } | |
950 | } | |
951 | ||
952 | static const struct frame_unwind m68hc11_frame_unwind = { | |
953 | NORMAL_FRAME, | |
954 | m68hc11_frame_this_id, | |
955 | m68hc11_frame_prev_register | |
956 | }; | |
957 | ||
958 | const struct frame_unwind * | |
1a241548 | 959 | m68hc11_frame_sniffer (struct frame_info *next_frame) |
1ea653ae SC |
960 | { |
961 | return &m68hc11_frame_unwind; | |
962 | } | |
963 | ||
964 | static CORE_ADDR | |
965 | m68hc11_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
966 | { | |
967 | struct m68hc11_unwind_cache *info | |
968 | = m68hc11_frame_unwind_cache (next_frame, this_cache); | |
969 | ||
970 | return info->base; | |
971 | } | |
972 | ||
973 | static CORE_ADDR | |
974 | m68hc11_frame_args_address (struct frame_info *next_frame, void **this_cache) | |
975 | { | |
976 | CORE_ADDR addr; | |
977 | struct m68hc11_unwind_cache *info | |
978 | = m68hc11_frame_unwind_cache (next_frame, this_cache); | |
979 | ||
980 | addr = info->base + info->size; | |
981 | if (info->return_kind == RETURN_RTC) | |
982 | addr += 1; | |
983 | else if (info->return_kind == RETURN_RTI) | |
984 | addr += 7; | |
985 | ||
986 | return addr; | |
987 | } | |
988 | ||
989 | static const struct frame_base m68hc11_frame_base = { | |
990 | &m68hc11_frame_unwind, | |
991 | m68hc11_frame_base_address, | |
992 | m68hc11_frame_base_address, | |
993 | m68hc11_frame_args_address | |
994 | }; | |
995 | ||
996 | static CORE_ADDR | |
997 | m68hc11_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
998 | { | |
999 | ULONGEST sp; | |
1000 | frame_unwind_unsigned_register (next_frame, HARD_SP_REGNUM, &sp); | |
1001 | return sp; | |
1002 | } | |
1003 | ||
1004 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1005 | dummy frame. The frame ID's base needs to match the TOS value | |
1006 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1007 | breakpoint. */ | |
1008 | ||
1009 | static struct frame_id | |
1010 | m68hc11_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1011 | { | |
1012 | ULONGEST tos; | |
1013 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1014 | ||
1015 | frame_unwind_unsigned_register (next_frame, SOFT_FP_REGNUM, &tos); | |
1016 | tos += 2; | |
1017 | return frame_id_build (tos, pc); | |
1018 | } | |
78073dd8 | 1019 | |
e286caf2 SC |
1020 | \f |
1021 | /* Get and print the register from the given frame. */ | |
78073dd8 | 1022 | static void |
e286caf2 SC |
1023 | m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
1024 | struct frame_info *frame, int regno) | |
78073dd8 | 1025 | { |
e286caf2 SC |
1026 | LONGEST rval; |
1027 | ||
1028 | if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM | |
1029 | || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) | |
7f5f525d | 1030 | rval = get_frame_register_unsigned (frame, regno); |
e286caf2 | 1031 | else |
7f5f525d | 1032 | rval = get_frame_register_signed (frame, regno); |
e286caf2 SC |
1033 | |
1034 | if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM | |
1035 | || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) | |
7df11f59 | 1036 | { |
e286caf2 SC |
1037 | fprintf_filtered (file, "0x%02x ", (unsigned char) rval); |
1038 | if (regno != HARD_CCR_REGNUM) | |
1039 | print_longest (file, 'd', 1, rval); | |
7df11f59 | 1040 | } |
e286caf2 SC |
1041 | else |
1042 | { | |
1043 | if (regno == HARD_PC_REGNUM && gdbarch_tdep (gdbarch)->use_page_register) | |
1044 | { | |
1045 | ULONGEST page; | |
7df11f59 | 1046 | |
7f5f525d | 1047 | page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); |
e286caf2 SC |
1048 | fprintf_filtered (file, "0x%02x:%04x ", (unsigned) page, |
1049 | (unsigned) rval); | |
1050 | } | |
1051 | else | |
1052 | { | |
1053 | fprintf_filtered (file, "0x%04x ", (unsigned) rval); | |
1054 | if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM | |
1055 | && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) | |
1056 | print_longest (file, 'd', 1, rval); | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | if (regno == HARD_CCR_REGNUM) | |
78073dd8 | 1061 | { |
e286caf2 SC |
1062 | /* CCR register */ |
1063 | int C, Z, N, V; | |
1064 | unsigned char l = rval & 0xff; | |
1065 | ||
1066 | fprintf_filtered (file, "%c%c%c%c%c%c%c%c ", | |
1067 | l & M6811_S_BIT ? 'S' : '-', | |
1068 | l & M6811_X_BIT ? 'X' : '-', | |
1069 | l & M6811_H_BIT ? 'H' : '-', | |
1070 | l & M6811_I_BIT ? 'I' : '-', | |
1071 | l & M6811_N_BIT ? 'N' : '-', | |
1072 | l & M6811_Z_BIT ? 'Z' : '-', | |
1073 | l & M6811_V_BIT ? 'V' : '-', | |
1074 | l & M6811_C_BIT ? 'C' : '-'); | |
1075 | N = (l & M6811_N_BIT) != 0; | |
1076 | Z = (l & M6811_Z_BIT) != 0; | |
1077 | V = (l & M6811_V_BIT) != 0; | |
1078 | C = (l & M6811_C_BIT) != 0; | |
1079 | ||
1080 | /* Print flags following the h8300 */ | |
1081 | if ((C | Z) == 0) | |
1082 | fprintf_filtered (file, "u> "); | |
1083 | else if ((C | Z) == 1) | |
1084 | fprintf_filtered (file, "u<= "); | |
1085 | else if (C == 0) | |
1086 | fprintf_filtered (file, "u< "); | |
1087 | ||
1088 | if (Z == 0) | |
1089 | fprintf_filtered (file, "!= "); | |
1090 | else | |
1091 | fprintf_filtered (file, "== "); | |
1092 | ||
1093 | if ((N ^ V) == 0) | |
1094 | fprintf_filtered (file, ">= "); | |
1095 | else | |
1096 | fprintf_filtered (file, "< "); | |
1097 | ||
1098 | if ((Z | (N ^ V)) == 0) | |
1099 | fprintf_filtered (file, "> "); | |
78073dd8 | 1100 | else |
e286caf2 | 1101 | fprintf_filtered (file, "<= "); |
78073dd8 | 1102 | } |
e286caf2 SC |
1103 | } |
1104 | ||
1105 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1106 | static void | |
1107 | m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
1108 | struct frame_info *frame, int regno, int cpregs) | |
1109 | { | |
1110 | if (regno >= 0) | |
1111 | { | |
1112 | const char *name = gdbarch_register_name (gdbarch, regno); | |
1113 | ||
1114 | if (!name || !*name) | |
1115 | return; | |
1116 | ||
1117 | fprintf_filtered (file, "%-10s ", name); | |
1118 | m68hc11_print_register (gdbarch, file, frame, regno); | |
1119 | fprintf_filtered (file, "\n"); | |
1120 | } | |
1121 | else | |
1122 | { | |
1123 | int i, nr; | |
1124 | ||
1125 | fprintf_filtered (file, "PC="); | |
1126 | m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); | |
1127 | ||
1128 | fprintf_filtered (file, " SP="); | |
1129 | m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); | |
1130 | ||
1131 | fprintf_filtered (file, " FP="); | |
1132 | m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); | |
1133 | ||
1134 | fprintf_filtered (file, "\nCCR="); | |
1135 | m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); | |
1136 | ||
1137 | fprintf_filtered (file, "\nD="); | |
1138 | m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); | |
1139 | ||
1140 | fprintf_filtered (file, " X="); | |
1141 | m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); | |
1142 | ||
1143 | fprintf_filtered (file, " Y="); | |
1144 | m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); | |
1145 | ||
1146 | if (gdbarch_tdep (gdbarch)->use_page_register) | |
1147 | { | |
1148 | fprintf_filtered (file, "\nPage="); | |
1149 | m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); | |
1150 | } | |
1151 | fprintf_filtered (file, "\n"); | |
1152 | ||
1153 | nr = 0; | |
1154 | for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) | |
1155 | { | |
1156 | /* Skip registers which are not defined in the symbol table. */ | |
1157 | if (soft_regs[i].name == 0) | |
1158 | continue; | |
1159 | ||
1160 | fprintf_filtered (file, "D%d=", i - SOFT_D1_REGNUM + 1); | |
1161 | m68hc11_print_register (gdbarch, file, frame, i); | |
1162 | nr++; | |
1163 | if ((nr % 8) == 7) | |
1164 | fprintf_filtered (file, "\n"); | |
1165 | else | |
1166 | fprintf_filtered (file, " "); | |
1167 | } | |
1168 | if (nr && (nr % 8) != 7) | |
1169 | fprintf_filtered (file, "\n"); | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1174 | static void | |
1175 | show_regs (char *args, int from_tty) | |
1176 | { | |
1177 | m68hc11_print_registers_info (current_gdbarch, gdb_stdout, | |
1178 | get_current_frame (), -1, 1); | |
78073dd8 AC |
1179 | } |
1180 | ||
22df305e SC |
1181 | static CORE_ADDR |
1182 | m68hc11_stack_align (CORE_ADDR addr) | |
1183 | { | |
1184 | return ((addr + 1) & -2); | |
1185 | } | |
1186 | ||
82c230c2 | 1187 | static CORE_ADDR |
3dc990bf SC |
1188 | m68hc11_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1189 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1190 | int nargs, struct value **args, CORE_ADDR sp, | |
1191 | int struct_return, CORE_ADDR struct_addr) | |
78073dd8 | 1192 | { |
82c230c2 SC |
1193 | int argnum; |
1194 | int first_stack_argnum; | |
82c230c2 SC |
1195 | struct type *type; |
1196 | char *val; | |
1197 | int len; | |
3dc990bf | 1198 | char buf[2]; |
82c230c2 | 1199 | |
82c230c2 SC |
1200 | first_stack_argnum = 0; |
1201 | if (struct_return) | |
1202 | { | |
184651e3 SC |
1203 | /* The struct is allocated on the stack and gdb used the stack |
1204 | pointer for the address of that struct. We must apply the | |
1205 | stack offset on the address. */ | |
3dc990bf SC |
1206 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, |
1207 | struct_addr + STACK_CORRECTION); | |
82c230c2 SC |
1208 | } |
1209 | else if (nargs > 0) | |
1210 | { | |
1211 | type = VALUE_TYPE (args[0]); | |
1212 | len = TYPE_LENGTH (type); | |
3dc990bf | 1213 | |
82c230c2 SC |
1214 | /* First argument is passed in D and X registers. */ |
1215 | if (len <= 4) | |
1216 | { | |
3dc990bf SC |
1217 | ULONGEST v; |
1218 | ||
1219 | v = extract_unsigned_integer (VALUE_CONTENTS (args[0]), len); | |
82c230c2 | 1220 | first_stack_argnum = 1; |
3dc990bf SC |
1221 | |
1222 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); | |
82c230c2 SC |
1223 | if (len > 2) |
1224 | { | |
1225 | v >>= 16; | |
3dc990bf | 1226 | regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); |
82c230c2 SC |
1227 | } |
1228 | } | |
1229 | } | |
82c230c2 | 1230 | |
3dc990bf | 1231 | for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) |
82c230c2 SC |
1232 | { |
1233 | type = VALUE_TYPE (args[argnum]); | |
1234 | len = TYPE_LENGTH (type); | |
1235 | ||
22df305e SC |
1236 | if (len & 1) |
1237 | { | |
1238 | static char zero = 0; | |
1239 | ||
3dc990bf SC |
1240 | sp--; |
1241 | write_memory (sp, &zero, 1); | |
22df305e | 1242 | } |
3dc990bf SC |
1243 | val = (char*) VALUE_CONTENTS (args[argnum]); |
1244 | sp -= len; | |
1245 | write_memory (sp, val, len); | |
82c230c2 | 1246 | } |
3dc990bf SC |
1247 | |
1248 | /* Store return address. */ | |
1249 | sp -= 2; | |
1250 | store_unsigned_integer (buf, 2, bp_addr); | |
1251 | write_memory (sp, buf, 2); | |
1252 | ||
1253 | /* Finally, update the stack pointer... */ | |
1254 | sp -= STACK_CORRECTION; | |
1255 | regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); | |
1256 | ||
1257 | /* ...and fake a frame pointer. */ | |
1258 | regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); | |
1259 | ||
1260 | /* DWARF2/GCC uses the stack address *before* the function call as a | |
1261 | frame's CFA. */ | |
1262 | return sp + 2; | |
78073dd8 AC |
1263 | } |
1264 | ||
1265 | ||
4db73d49 SC |
1266 | /* Return the GDB type object for the "standard" data type |
1267 | of data in register N. */ | |
1268 | ||
82c230c2 | 1269 | static struct type * |
4db73d49 | 1270 | m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) |
82c230c2 | 1271 | { |
5706502a SC |
1272 | switch (reg_nr) |
1273 | { | |
1274 | case HARD_PAGE_REGNUM: | |
1275 | case HARD_A_REGNUM: | |
1276 | case HARD_B_REGNUM: | |
1277 | case HARD_CCR_REGNUM: | |
1278 | return builtin_type_uint8; | |
1279 | ||
548bcbec SC |
1280 | case M68HC12_HARD_PC_REGNUM: |
1281 | return builtin_type_uint32; | |
1282 | ||
5706502a SC |
1283 | default: |
1284 | return builtin_type_uint16; | |
1285 | } | |
82c230c2 SC |
1286 | } |
1287 | ||
82c230c2 | 1288 | static void |
4db73d49 SC |
1289 | m68hc11_store_return_value (struct type *type, struct regcache *regcache, |
1290 | const void *valbuf) | |
82c230c2 | 1291 | { |
22df305e SC |
1292 | int len; |
1293 | ||
1294 | len = TYPE_LENGTH (type); | |
1295 | ||
1296 | /* First argument is passed in D and X registers. */ | |
4db73d49 SC |
1297 | if (len <= 2) |
1298 | regcache_raw_write_part (regcache, HARD_D_REGNUM, 2 - len, len, valbuf); | |
1299 | else if (len <= 4) | |
22df305e | 1300 | { |
4db73d49 SC |
1301 | regcache_raw_write_part (regcache, HARD_X_REGNUM, 4 - len, |
1302 | len - 2, valbuf); | |
1303 | regcache_raw_write (regcache, HARD_D_REGNUM, (char*) valbuf + (len - 2)); | |
22df305e SC |
1304 | } |
1305 | else | |
1306 | error ("return of value > 4 is not supported."); | |
82c230c2 SC |
1307 | } |
1308 | ||
1309 | ||
ef2b8fcd | 1310 | /* Given a return value in `regcache' with a type `type', |
78073dd8 AC |
1311 | extract and copy its value into `valbuf'. */ |
1312 | ||
82c230c2 | 1313 | static void |
ef2b8fcd SC |
1314 | m68hc11_extract_return_value (struct type *type, struct regcache *regcache, |
1315 | void *valbuf) | |
78073dd8 | 1316 | { |
82c230c2 | 1317 | int len = TYPE_LENGTH (type); |
ef2b8fcd SC |
1318 | char buf[M68HC11_REG_SIZE]; |
1319 | ||
1320 | regcache_raw_read (regcache, HARD_D_REGNUM, buf); | |
22df305e | 1321 | switch (len) |
82c230c2 | 1322 | { |
22df305e | 1323 | case 1: |
ef2b8fcd | 1324 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1325 | break; |
ef2b8fcd | 1326 | |
22df305e | 1327 | case 2: |
ef2b8fcd | 1328 | memcpy (valbuf, buf, 2); |
22df305e | 1329 | break; |
ef2b8fcd | 1330 | |
22df305e | 1331 | case 3: |
ef2b8fcd SC |
1332 | memcpy ((char*) valbuf + 1, buf, 2); |
1333 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1334 | memcpy (valbuf, buf + 1, 1); | |
22df305e | 1335 | break; |
ef2b8fcd | 1336 | |
22df305e | 1337 | case 4: |
ef2b8fcd SC |
1338 | memcpy ((char*) valbuf + 2, buf, 2); |
1339 | regcache_raw_read (regcache, HARD_X_REGNUM, buf); | |
1340 | memcpy (valbuf, buf, 2); | |
22df305e SC |
1341 | break; |
1342 | ||
1343 | default: | |
82c230c2 SC |
1344 | error ("bad size for return value"); |
1345 | } | |
1346 | } | |
1347 | ||
1348 | /* Should call_function allocate stack space for a struct return? */ | |
1349 | static int | |
1350 | m68hc11_use_struct_convention (int gcc_p, struct type *type) | |
1351 | { | |
22df305e SC |
1352 | return (TYPE_CODE (type) == TYPE_CODE_STRUCT |
1353 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1354 | || TYPE_LENGTH (type) > 4); | |
82c230c2 SC |
1355 | } |
1356 | ||
1357 | static int | |
1358 | m68hc11_return_value_on_stack (struct type *type) | |
1359 | { | |
22df305e | 1360 | return TYPE_LENGTH (type) > 4; |
82c230c2 SC |
1361 | } |
1362 | ||
1363 | /* Extract from an array REGBUF containing the (raw) register state | |
1364 | the address in which a function should return its structure value, | |
1365 | as a CORE_ADDR (or an expression that can be used as one). */ | |
1366 | static CORE_ADDR | |
4db73d49 | 1367 | m68hc11_extract_struct_value_address (struct regcache *regcache) |
82c230c2 | 1368 | { |
4db73d49 SC |
1369 | char buf[M68HC11_REG_SIZE]; |
1370 | ||
1371 | regcache_cooked_read (regcache, HARD_D_REGNUM, buf); | |
1372 | return extract_unsigned_integer (buf, M68HC11_REG_SIZE); | |
82c230c2 SC |
1373 | } |
1374 | ||
7df11f59 SC |
1375 | /* Test whether the ELF symbol corresponds to a function using rtc or |
1376 | rti to return. */ | |
1377 | ||
1378 | static void | |
1379 | m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
1380 | { | |
1381 | unsigned char flags; | |
1382 | ||
1383 | flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; | |
1384 | if (flags & STO_M68HC12_FAR) | |
1385 | MSYMBOL_SET_RTC (msym); | |
1386 | if (flags & STO_M68HC12_INTERRUPT) | |
1387 | MSYMBOL_SET_RTI (msym); | |
1388 | } | |
1389 | ||
ea3881d9 SC |
1390 | static int |
1391 | gdb_print_insn_m68hc11 (bfd_vma memaddr, disassemble_info *info) | |
1392 | { | |
1393 | if (TARGET_ARCHITECTURE->arch == bfd_arch_m68hc11) | |
1394 | return print_insn_m68hc11 (memaddr, info); | |
1395 | else | |
1396 | return print_insn_m68hc12 (memaddr, info); | |
1397 | } | |
1398 | ||
b631436b SC |
1399 | \f |
1400 | ||
1401 | /* 68HC11/68HC12 register groups. | |
1402 | Identify real hard registers and soft registers used by gcc. */ | |
1403 | ||
1404 | static struct reggroup *m68hc11_soft_reggroup; | |
1405 | static struct reggroup *m68hc11_hard_reggroup; | |
1406 | ||
1407 | static void | |
1408 | m68hc11_init_reggroups (void) | |
1409 | { | |
1410 | m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); | |
1411 | m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); | |
1412 | } | |
1413 | ||
1414 | static void | |
1415 | m68hc11_add_reggroups (struct gdbarch *gdbarch) | |
1416 | { | |
1417 | reggroup_add (gdbarch, m68hc11_hard_reggroup); | |
1418 | reggroup_add (gdbarch, m68hc11_soft_reggroup); | |
1419 | reggroup_add (gdbarch, general_reggroup); | |
1420 | reggroup_add (gdbarch, float_reggroup); | |
1421 | reggroup_add (gdbarch, all_reggroup); | |
1422 | reggroup_add (gdbarch, save_reggroup); | |
1423 | reggroup_add (gdbarch, restore_reggroup); | |
1424 | reggroup_add (gdbarch, vector_reggroup); | |
1425 | reggroup_add (gdbarch, system_reggroup); | |
1426 | } | |
1427 | ||
1428 | static int | |
1429 | m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1430 | struct reggroup *group) | |
1431 | { | |
1432 | /* We must save the real hard register as well as gcc | |
1433 | soft registers including the frame pointer. */ | |
1434 | if (group == save_reggroup || group == restore_reggroup) | |
1435 | { | |
1436 | return (regnum <= gdbarch_num_regs (gdbarch) | |
1437 | || ((regnum == SOFT_FP_REGNUM | |
1438 | || regnum == SOFT_TMP_REGNUM | |
1439 | || regnum == SOFT_ZS_REGNUM | |
1440 | || regnum == SOFT_XY_REGNUM) | |
1441 | && m68hc11_register_name (regnum))); | |
1442 | } | |
1443 | ||
1444 | /* Group to identify gcc soft registers (d1..dN). */ | |
1445 | if (group == m68hc11_soft_reggroup) | |
1446 | { | |
1447 | return regnum >= SOFT_D1_REGNUM && m68hc11_register_name (regnum); | |
1448 | } | |
1449 | ||
1450 | if (group == m68hc11_hard_reggroup) | |
1451 | { | |
1452 | return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM | |
1453 | || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM | |
1454 | || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; | |
1455 | } | |
1456 | return default_register_reggroup_p (gdbarch, regnum, group); | |
1457 | } | |
1458 | ||
82c230c2 SC |
1459 | static struct gdbarch * |
1460 | m68hc11_gdbarch_init (struct gdbarch_info info, | |
1461 | struct gdbarch_list *arches) | |
1462 | { | |
82c230c2 SC |
1463 | struct gdbarch *gdbarch; |
1464 | struct gdbarch_tdep *tdep; | |
81967506 | 1465 | int elf_flags; |
82c230c2 SC |
1466 | |
1467 | soft_reg_initialized = 0; | |
81967506 SC |
1468 | |
1469 | /* Extract the elf_flags if available. */ | |
1470 | if (info.abfd != NULL | |
1471 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1472 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1473 | else | |
1474 | elf_flags = 0; | |
1475 | ||
82c230c2 SC |
1476 | /* try to find a pre-existing architecture */ |
1477 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1478 | arches != NULL; | |
1479 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1480 | { | |
81967506 SC |
1481 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
1482 | continue; | |
1483 | ||
82c230c2 SC |
1484 | return arches->gdbarch; |
1485 | } | |
1486 | ||
1487 | /* Need a new architecture. Fill in a target specific vector. */ | |
1488 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
1489 | gdbarch = gdbarch_alloc (&info, tdep); | |
81967506 | 1490 | tdep->elf_flags = elf_flags; |
ed99b3d0 | 1491 | |
5d1a66bd SC |
1492 | switch (info.bfd_arch_info->arch) |
1493 | { | |
1494 | case bfd_arch_m68hc11: | |
1495 | tdep->stack_correction = 1; | |
7df11f59 | 1496 | tdep->use_page_register = 0; |
908f682f | 1497 | tdep->prologue = m6811_prologue; |
548bcbec SC |
1498 | set_gdbarch_addr_bit (gdbarch, 16); |
1499 | set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); | |
1500 | set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); | |
1501 | set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); | |
5d1a66bd | 1502 | break; |
82c230c2 | 1503 | |
5d1a66bd SC |
1504 | case bfd_arch_m68hc12: |
1505 | tdep->stack_correction = 0; | |
7df11f59 | 1506 | tdep->use_page_register = elf_flags & E_M68HC12_BANKS; |
908f682f | 1507 | tdep->prologue = m6812_prologue; |
548bcbec SC |
1508 | set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); |
1509 | set_gdbarch_num_pseudo_regs (gdbarch, | |
1510 | elf_flags & E_M68HC12_BANKS | |
1511 | ? M68HC12_NUM_PSEUDO_REGS | |
1512 | : M68HC11_NUM_PSEUDO_REGS); | |
1513 | set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS | |
1514 | ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); | |
1515 | set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS | |
1516 | ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); | |
5d1a66bd SC |
1517 | break; |
1518 | ||
1519 | default: | |
1520 | break; | |
1521 | } | |
7d32ba20 SC |
1522 | |
1523 | /* Initially set everything according to the ABI. | |
1524 | Use 16-bit integers since it will be the case for most | |
1525 | programs. The size of these types should normally be set | |
1526 | according to the dwarf2 debug information. */ | |
82c230c2 | 1527 | set_gdbarch_short_bit (gdbarch, 16); |
81967506 | 1528 | set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); |
82c230c2 | 1529 | set_gdbarch_float_bit (gdbarch, 32); |
81967506 | 1530 | set_gdbarch_double_bit (gdbarch, elf_flags & E_M68HC11_F64 ? 64 : 32); |
2417dd25 | 1531 | set_gdbarch_long_double_bit (gdbarch, 64); |
82c230c2 SC |
1532 | set_gdbarch_long_bit (gdbarch, 32); |
1533 | set_gdbarch_ptr_bit (gdbarch, 16); | |
1534 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1535 | ||
b2a02dda SC |
1536 | /* Characters are unsigned. */ |
1537 | set_gdbarch_char_signed (gdbarch, 0); | |
1538 | ||
1ea653ae SC |
1539 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); |
1540 | set_gdbarch_unwind_sp (gdbarch, m68hc11_unwind_sp); | |
1541 | ||
82c230c2 SC |
1542 | /* Set register info. */ |
1543 | set_gdbarch_fp0_regnum (gdbarch, -1); | |
82c230c2 SC |
1544 | set_gdbarch_frame_args_skip (gdbarch, 0); |
1545 | ||
82c230c2 | 1546 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
82c230c2 | 1547 | |
82c230c2 | 1548 | set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); |
82c230c2 | 1549 | set_gdbarch_register_name (gdbarch, m68hc11_register_name); |
4db73d49 | 1550 | set_gdbarch_register_type (gdbarch, m68hc11_register_type); |
46ce284d AC |
1551 | set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); |
1552 | set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); | |
82c230c2 | 1553 | |
3dc990bf SC |
1554 | set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); |
1555 | ||
ef2b8fcd | 1556 | set_gdbarch_extract_return_value (gdbarch, m68hc11_extract_return_value); |
82c230c2 SC |
1557 | set_gdbarch_return_value_on_stack (gdbarch, m68hc11_return_value_on_stack); |
1558 | ||
4db73d49 SC |
1559 | set_gdbarch_store_return_value (gdbarch, m68hc11_store_return_value); |
1560 | set_gdbarch_extract_struct_value_address (gdbarch, m68hc11_extract_struct_value_address); | |
82c230c2 | 1561 | |
0880807f AC |
1562 | set_gdbarch_store_return_value (gdbarch, m68hc11_store_return_value); |
1563 | set_gdbarch_extract_struct_value_address (gdbarch, m68hc11_extract_struct_value_address); | |
82c230c2 | 1564 | set_gdbarch_use_struct_convention (gdbarch, m68hc11_use_struct_convention); |
82c230c2 SC |
1565 | set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); |
1566 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1567 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
1568 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1569 | set_gdbarch_breakpoint_from_pc (gdbarch, m68hc11_breakpoint_from_pc); | |
f27dd7fd | 1570 | set_gdbarch_deprecated_stack_align (gdbarch, m68hc11_stack_align); |
70ed8774 | 1571 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_m68hc11); |
82c230c2 | 1572 | |
b631436b SC |
1573 | m68hc11_add_reggroups (gdbarch); |
1574 | set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); | |
e286caf2 | 1575 | set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); |
b631436b | 1576 | |
1ea653ae SC |
1577 | /* Hook in the DWARF CFI frame unwinder. */ |
1578 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
1ea653ae | 1579 | |
1a241548 | 1580 | frame_unwind_append_sniffer (gdbarch, m68hc11_frame_sniffer); |
1ea653ae SC |
1581 | frame_base_set_default (gdbarch, &m68hc11_frame_base); |
1582 | ||
1583 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1584 | stack address must match the SP value returned by | |
1585 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
1586 | set_gdbarch_unwind_dummy_id (gdbarch, m68hc11_unwind_dummy_id); | |
1587 | ||
1588 | /* Return the unwound PC value. */ | |
1589 | set_gdbarch_unwind_pc (gdbarch, m68hc11_unwind_pc); | |
1590 | ||
7df11f59 SC |
1591 | /* Minsymbol frobbing. */ |
1592 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
1593 | m68hc11_elf_make_msymbol_special); | |
1594 | ||
82c230c2 | 1595 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
82c230c2 SC |
1596 | |
1597 | return gdbarch; | |
78073dd8 AC |
1598 | } |
1599 | ||
a78f21af AC |
1600 | extern initialize_file_ftype _initialize_m68hc11_tdep; /* -Wmissing-prototypes */ |
1601 | ||
78073dd8 | 1602 | void |
fba45db2 | 1603 | _initialize_m68hc11_tdep (void) |
78073dd8 | 1604 | { |
82c230c2 | 1605 | register_gdbarch_init (bfd_arch_m68hc11, m68hc11_gdbarch_init); |
ea3881d9 | 1606 | register_gdbarch_init (bfd_arch_m68hc12, m68hc11_gdbarch_init); |
b631436b | 1607 | m68hc11_init_reggroups (); |
78073dd8 | 1608 | |
e286caf2 SC |
1609 | deprecate_cmd (add_com ("regs", class_vars, show_regs, |
1610 | "Print all registers"), | |
1611 | "info registers"); | |
78073dd8 AC |
1612 | } |
1613 |