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2d1c1221 ME |
1 | /* Target-dependent code for Xilinx MicroBlaze. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2009-2014 Free Software Foundation, Inc. |
2d1c1221 ME |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "arch-utils.h" | |
22 | #include "dis-asm.h" | |
23 | #include "frame.h" | |
24 | #include "trad-frame.h" | |
25 | #include "symtab.h" | |
26 | #include "value.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "breakpoint.h" | |
29 | #include "inferior.h" | |
30 | #include "regcache.h" | |
31 | #include "target.h" | |
2d1c1221 ME |
32 | #include "frame-base.h" |
33 | #include "frame-unwind.h" | |
34 | #include "dwarf2-frame.h" | |
35 | #include "osabi.h" | |
2d1c1221 | 36 | #include "gdb_assert.h" |
0e9f083f | 37 | #include <string.h> |
2d1c1221 ME |
38 | #include "target-descriptions.h" |
39 | #include "opcodes/microblaze-opcm.h" | |
40 | #include "opcodes/microblaze-dis.h" | |
41 | #include "microblaze-tdep.h" | |
164224e9 ME |
42 | #include "remote.h" |
43 | ||
44 | #include "features/microblaze-with-stack-protect.c" | |
45 | #include "features/microblaze.c" | |
2d1c1221 ME |
46 | \f |
47 | /* Instruction macros used for analyzing the prologue. */ | |
48 | /* This set of instruction macros need to be changed whenever the | |
49 | prologue generated by the compiler could have more instructions or | |
50 | different type of instructions. | |
51 | This set also needs to be verified if it is complete. */ | |
52 | #define IS_RETURN(op) (op == rtsd || op == rtid) | |
53 | #define IS_UPDATE_SP(op, rd, ra) \ | |
025bb325 | 54 | ((op == addik || op == addi) && rd == REG_SP && ra == REG_SP) |
2d1c1221 | 55 | #define IS_SPILL_SP(op, rd, ra) \ |
025bb325 | 56 | ((op == swi || op == sw) && rd == REG_SP && ra == REG_SP) |
2d1c1221 | 57 | #define IS_SPILL_REG(op, rd, ra) \ |
025bb325 | 58 | ((op == swi || op == sw) && rd != REG_SP && ra == REG_SP) |
2d1c1221 | 59 | #define IS_ALSO_SPILL_REG(op, rd, ra, rb) \ |
025bb325 | 60 | ((op == swi || op == sw) && rd != REG_SP && ra == 0 && rb == REG_SP) |
2d1c1221 | 61 | #define IS_SETUP_FP(op, ra, rb) \ |
025bb325 | 62 | ((op == add || op == addik || op == addk) && ra == REG_SP && rb == 0) |
2d1c1221 | 63 | #define IS_SPILL_REG_FP(op, rd, ra, fpregnum) \ |
025bb325 | 64 | ((op == swi || op == sw) && rd != REG_SP && ra == fpregnum && ra != 0) |
2d1c1221 | 65 | #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ |
025bb325 | 66 | ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) |
2d1c1221 | 67 | |
2d1c1221 ME |
68 | /* The registers of the Xilinx microblaze processor. */ |
69 | ||
70 | static const char *microblaze_register_names[] = | |
71 | { | |
72 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
73 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
74 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
75 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
76 | "rpc", "rmsr", "rear", "resr", "rfsr", "rbtr", | |
77 | "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", | |
78 | "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", | |
164224e9 ME |
79 | "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", |
80 | "rslr", "rshr" | |
2d1c1221 ME |
81 | }; |
82 | ||
83 | #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) | |
84 | \f | |
ccce17b0 | 85 | static unsigned int microblaze_debug_flag = 0; |
2d1c1221 | 86 | |
693be288 | 87 | static void |
2d1c1221 ME |
88 | microblaze_debug (const char *fmt, ...) |
89 | { | |
90 | if (microblaze_debug_flag) | |
91 | { | |
92 | va_list args; | |
93 | ||
94 | va_start (args, fmt); | |
95 | printf_unfiltered ("MICROBLAZE: "); | |
96 | vprintf_unfiltered (fmt, args); | |
97 | va_end (args); | |
98 | } | |
99 | } | |
100 | \f | |
101 | /* Return the name of register REGNUM. */ | |
102 | ||
103 | static const char * | |
104 | microblaze_register_name (struct gdbarch *gdbarch, int regnum) | |
105 | { | |
106 | if (regnum >= 0 && regnum < MICROBLAZE_NUM_REGS) | |
107 | return microblaze_register_names[regnum]; | |
108 | return NULL; | |
109 | } | |
110 | ||
111 | static struct type * | |
112 | microblaze_register_type (struct gdbarch *gdbarch, int regnum) | |
113 | { | |
114 | if (regnum == MICROBLAZE_SP_REGNUM) | |
115 | return builtin_type (gdbarch)->builtin_data_ptr; | |
116 | ||
117 | if (regnum == MICROBLAZE_PC_REGNUM) | |
118 | return builtin_type (gdbarch)->builtin_func_ptr; | |
119 | ||
120 | return builtin_type (gdbarch)->builtin_int; | |
121 | } | |
122 | ||
123 | \f | |
124 | /* Fetch the instruction at PC. */ | |
125 | ||
693be288 | 126 | static unsigned long |
2d1c1221 ME |
127 | microblaze_fetch_instruction (CORE_ADDR pc) |
128 | { | |
f5656ead | 129 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
2d1c1221 ME |
130 | gdb_byte buf[4]; |
131 | ||
132 | /* If we can't read the instruction at PC, return zero. */ | |
133 | if (target_read_memory (pc, buf, sizeof (buf))) | |
134 | return 0; | |
135 | ||
136 | return extract_unsigned_integer (buf, 4, byte_order); | |
137 | } | |
138 | \f | |
139 | ||
140 | static CORE_ADDR | |
141 | microblaze_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
142 | CORE_ADDR funcaddr, | |
143 | struct value **args, int nargs, | |
144 | struct type *value_type, | |
145 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
146 | struct regcache *regcache) | |
147 | { | |
148 | error (_("push_dummy_code not implemented")); | |
149 | return sp; | |
150 | } | |
151 | ||
152 | ||
153 | static CORE_ADDR | |
154 | microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
155 | struct regcache *regcache, CORE_ADDR bp_addr, | |
156 | int nargs, struct value **args, CORE_ADDR sp, | |
157 | int struct_return, CORE_ADDR struct_addr) | |
158 | { | |
159 | error (_("store_arguments not implemented")); | |
160 | return sp; | |
161 | } | |
162 | ||
163 | static const gdb_byte * | |
164 | microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, | |
165 | int *len) | |
166 | { | |
167 | static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT; | |
168 | ||
169 | *len = sizeof (break_insn); | |
170 | return break_insn; | |
171 | } | |
172 | \f | |
173 | /* Allocate and initialize a frame cache. */ | |
174 | ||
175 | static struct microblaze_frame_cache * | |
176 | microblaze_alloc_frame_cache (void) | |
177 | { | |
178 | struct microblaze_frame_cache *cache; | |
2d1c1221 ME |
179 | |
180 | cache = FRAME_OBSTACK_ZALLOC (struct microblaze_frame_cache); | |
181 | ||
182 | /* Base address. */ | |
183 | cache->base = 0; | |
184 | cache->pc = 0; | |
185 | ||
186 | /* Frameless until proven otherwise. */ | |
187 | cache->frameless_p = 1; | |
188 | ||
189 | return cache; | |
190 | } | |
191 | ||
192 | /* The base of the current frame is actually in the stack pointer. | |
193 | This happens when there is no frame pointer (microblaze ABI does not | |
194 | require a frame pointer) or when we're stopped in the prologue or | |
195 | epilogue itself. In these cases, microblaze_analyze_prologue will need | |
196 | to update fi->frame before returning or analyzing the register | |
197 | save instructions. */ | |
198 | #define MICROBLAZE_MY_FRAME_IN_SP 0x1 | |
199 | ||
200 | /* The base of the current frame is in a frame pointer register. | |
201 | This register is noted in frame_extra_info->fp_regnum. | |
202 | ||
203 | Note that the existance of an FP might also indicate that the | |
204 | function has called alloca. */ | |
205 | #define MICROBLAZE_MY_FRAME_IN_FP 0x2 | |
206 | ||
207 | /* Function prologues on the Xilinx microblaze processors consist of: | |
208 | ||
209 | - adjustments to the stack pointer (r1) (addi r1, r1, imm) | |
210 | - making a copy of r1 into another register (a "frame" pointer) | |
211 | (add r?, r1, r0) | |
212 | - store word/multiples that use r1 or the frame pointer as the | |
213 | base address (swi r?, r1, imm OR swi r?, fp, imm) | |
214 | ||
215 | Note that microblaze really doesn't have a real frame pointer. | |
216 | Instead, the compiler may copy the SP into a register (usually | |
217 | r19) to act as an arg pointer. For our target-dependent purposes, | |
218 | the frame info's "frame" member will be the beginning of the | |
219 | frame. The SP could, in fact, point below this. | |
220 | ||
221 | The prologue ends when an instruction fails to meet either of | |
222 | these criteria. */ | |
223 | ||
224 | /* Analyze the prologue to determine where registers are saved, | |
225 | the end of the prologue, etc. Return the address of the first line | |
025bb325 | 226 | of "real" code (i.e., the end of the prologue). */ |
2d1c1221 ME |
227 | |
228 | static CORE_ADDR | |
229 | microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, | |
230 | CORE_ADDR current_pc, | |
231 | struct microblaze_frame_cache *cache) | |
232 | { | |
2c02bd72 | 233 | const char *name; |
2d1c1221 ME |
234 | CORE_ADDR func_addr, func_end, addr, stop, prologue_end_addr = 0; |
235 | unsigned long insn; | |
22e048c9 | 236 | int rd, ra, rb, imm; |
2d1c1221 ME |
237 | enum microblaze_instr op; |
238 | int flags = 0; | |
239 | int save_hidden_pointer_found = 0; | |
240 | int non_stack_instruction_found = 0; | |
241 | ||
025bb325 | 242 | /* Find the start of this function. */ |
2d1c1221 ME |
243 | find_pc_partial_function (pc, &name, &func_addr, &func_end); |
244 | if (func_addr < pc) | |
245 | pc = func_addr; | |
246 | ||
247 | if (current_pc < pc) | |
248 | return current_pc; | |
249 | ||
250 | /* Initialize info about frame. */ | |
251 | cache->framesize = 0; | |
252 | cache->fp_regnum = MICROBLAZE_SP_REGNUM; | |
253 | cache->frameless_p = 1; | |
254 | ||
255 | /* Start decoding the prologue. We start by checking two special cases: | |
256 | ||
257 | 1. We're about to return | |
258 | 2. We're at the first insn of the prologue. | |
259 | ||
260 | If we're about to return, our frame has already been deallocated. | |
261 | If we are stopped at the first instruction of a prologue, | |
025bb325 | 262 | then our frame has not yet been set up. */ |
2d1c1221 ME |
263 | |
264 | /* Get the first insn from memory. */ | |
265 | ||
266 | insn = microblaze_fetch_instruction (pc); | |
267 | op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); | |
268 | ||
269 | if (IS_RETURN(op)) | |
270 | return pc; | |
271 | ||
272 | /* Start at beginning of function and analyze until we get to the | |
273 | current pc, or the end of the function, whichever is first. */ | |
274 | stop = (current_pc < func_end ? current_pc : func_end); | |
275 | ||
276 | microblaze_debug ("Scanning prologue: name=%s, func_addr=%s, stop=%s\n", | |
277 | name, paddress (gdbarch, func_addr), | |
278 | paddress (gdbarch, stop)); | |
279 | ||
280 | for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE) | |
281 | { | |
282 | insn = microblaze_fetch_instruction (addr); | |
283 | op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); | |
284 | microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn); | |
285 | ||
286 | /* This code is very sensitive to what functions are present in the | |
287 | prologue. It assumes that the (addi, addik, swi, sw) can be the | |
288 | only instructions in the prologue. */ | |
289 | if (IS_UPDATE_SP(op, rd, ra)) | |
290 | { | |
291 | microblaze_debug ("got addi r1,r1,%d; contnuing\n", imm); | |
292 | if (cache->framesize) | |
293 | break; /* break if framesize already computed. */ | |
294 | cache->framesize = -imm; /* stack grows towards low memory. */ | |
295 | cache->frameless_p = 0; /* Frame found. */ | |
296 | save_hidden_pointer_found = 0; | |
297 | non_stack_instruction_found = 0; | |
298 | continue; | |
299 | } | |
300 | else if (IS_SPILL_SP(op, rd, ra)) | |
301 | { | |
302 | /* Spill stack pointer. */ | |
303 | cache->register_offsets[rd] = imm; /* SP spilled before updating. */ | |
304 | ||
305 | microblaze_debug ("swi r1 r1 %d, continuing\n", imm); | |
306 | save_hidden_pointer_found = 0; | |
307 | if (!cache->framesize) | |
308 | non_stack_instruction_found = 0; | |
309 | continue; | |
310 | } | |
311 | else if (IS_SPILL_REG(op, rd, ra)) | |
312 | { | |
313 | /* Spill register. */ | |
314 | cache->register_offsets[rd] = imm - cache->framesize; | |
315 | ||
316 | microblaze_debug ("swi %d r1 %d, continuing\n", rd, imm); | |
317 | save_hidden_pointer_found = 0; | |
318 | if (!cache->framesize) | |
319 | non_stack_instruction_found = 0; | |
320 | continue; | |
321 | } | |
322 | else if (IS_ALSO_SPILL_REG(op, rd, ra, rb)) | |
323 | { | |
324 | /* Spill register. */ | |
325 | cache->register_offsets[rd] = 0 - cache->framesize; | |
326 | ||
327 | microblaze_debug ("sw %d r0 r1, continuing\n", rd); | |
328 | save_hidden_pointer_found = 0; | |
329 | if (!cache->framesize) | |
330 | non_stack_instruction_found = 0; | |
331 | continue; | |
332 | } | |
333 | else if (IS_SETUP_FP(op, ra, rb)) | |
334 | { | |
335 | /* We have a frame pointer. Note the register which is | |
025bb325 | 336 | acting as the frame pointer. */ |
2d1c1221 ME |
337 | flags |= MICROBLAZE_MY_FRAME_IN_FP; |
338 | flags &= ~MICROBLAZE_MY_FRAME_IN_SP; | |
339 | cache->fp_regnum = rd; | |
340 | microblaze_debug ("Found a frame pointer: r%d\n", cache->fp_regnum); | |
341 | save_hidden_pointer_found = 0; | |
342 | if (!cache->framesize) | |
343 | non_stack_instruction_found = 0; | |
344 | continue; | |
345 | } | |
346 | else if (IS_SPILL_REG_FP(op, rd, ra, cache->fp_regnum)) | |
347 | { | |
348 | /* reg spilled after updating. */ | |
349 | cache->register_offsets[rd] = imm - cache->framesize; | |
350 | ||
351 | microblaze_debug ("swi %d %d %d, continuing\n", rd, ra, imm); | |
352 | save_hidden_pointer_found = 0; | |
353 | if (!cache->framesize) | |
354 | non_stack_instruction_found = 0; | |
355 | continue; | |
356 | } | |
357 | else if (IS_SAVE_HIDDEN_PTR(op, rd, ra, rb)) | |
358 | { | |
359 | /* If the first argument is a hidden pointer to the area where the | |
360 | return structure is to be saved, then it is saved as part of the | |
361 | prologue. */ | |
362 | ||
363 | microblaze_debug ("add %d %d %d, continuing\n", rd, ra, rb); | |
364 | save_hidden_pointer_found = 1; | |
365 | if (!cache->framesize) | |
366 | non_stack_instruction_found = 0; | |
367 | continue; | |
368 | } | |
369 | ||
370 | /* As a result of the modification in the next step where we continue | |
371 | to analyze the prologue till we reach a control flow instruction, | |
372 | we need another variable to store when exactly a non-stack | |
373 | instruction was encountered, which is the current definition | |
374 | of a prologue. */ | |
375 | if (!non_stack_instruction_found) | |
376 | prologue_end_addr = addr; | |
377 | non_stack_instruction_found = 1; | |
378 | ||
379 | /* When optimizations are enabled, it is not guaranteed that prologue | |
380 | instructions are not mixed in with other instructions from the | |
025bb325 | 381 | program. Some programs show this behavior at -O2. This can be |
2d1c1221 ME |
382 | avoided by adding -fno-schedule-insns2 switch as of now (edk 8.1) |
383 | In such cases, we scan the function until we see the first control | |
384 | instruction. */ | |
385 | ||
386 | { | |
387 | unsigned op = (unsigned)insn >> 26; | |
388 | ||
389 | /* continue if not control flow (branch, return). */ | |
390 | if (op != 0x26 && op != 0x27 && op != 0x2d && op != 0x2e && op != 0x2f) | |
391 | continue; | |
392 | else if (op == 0x2c) | |
393 | continue; /* continue if imm. */ | |
394 | } | |
395 | ||
025bb325 | 396 | /* This is not a prologue insn, so stop here. */ |
2d1c1221 ME |
397 | microblaze_debug ("insn is not a prologue insn -- ending scan\n"); |
398 | break; | |
399 | } | |
400 | ||
401 | microblaze_debug ("done analyzing prologue\n"); | |
402 | microblaze_debug ("prologue end = 0x%x\n", (int) addr); | |
403 | ||
404 | /* If the last instruction was an add rd, r5, r0 then don't count it as | |
405 | part of the prologue. */ | |
406 | if (save_hidden_pointer_found) | |
407 | prologue_end_addr -= INST_WORD_SIZE; | |
408 | ||
409 | return prologue_end_addr; | |
410 | } | |
411 | ||
412 | static CORE_ADDR | |
413 | microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
414 | { | |
415 | gdb_byte buf[4]; | |
416 | CORE_ADDR pc; | |
417 | ||
418 | frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf); | |
419 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); | |
420 | /* For sentinel frame, return address is actual PC. For other frames, | |
421 | return address is pc+8. This is a workaround because gcc does not | |
422 | generate correct return address in CIE. */ | |
423 | if (frame_relative_level (next_frame) >= 0) | |
424 | pc += 8; | |
425 | return pc; | |
426 | } | |
427 | ||
428 | /* Return PC of first real instruction of the function starting at | |
429 | START_PC. */ | |
430 | ||
693be288 | 431 | static CORE_ADDR |
2d1c1221 ME |
432 | microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
433 | { | |
434 | struct symtab_and_line sal; | |
435 | CORE_ADDR func_start, func_end, ostart_pc; | |
436 | struct microblaze_frame_cache cache; | |
437 | ||
438 | /* This is the preferred method, find the end of the prologue by | |
439 | using the debugging information. Debugging info does not always | |
440 | give the right answer since parameters are stored on stack after this. | |
441 | Always analyze the prologue. */ | |
442 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
443 | { | |
444 | sal = find_pc_line (func_start, 0); | |
445 | ||
446 | if (sal.end < func_end | |
447 | && start_pc <= sal.end) | |
448 | start_pc = sal.end; | |
449 | } | |
450 | ||
451 | ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, | |
452 | &cache); | |
453 | ||
454 | if (ostart_pc > start_pc) | |
455 | return ostart_pc; | |
456 | return start_pc; | |
457 | } | |
458 | ||
459 | /* Normal frames. */ | |
460 | ||
693be288 | 461 | static struct microblaze_frame_cache * |
2d1c1221 ME |
462 | microblaze_frame_cache (struct frame_info *next_frame, void **this_cache) |
463 | { | |
464 | struct microblaze_frame_cache *cache; | |
465 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
22e048c9 | 466 | CORE_ADDR func; |
2d1c1221 ME |
467 | int rn; |
468 | ||
469 | if (*this_cache) | |
470 | return *this_cache; | |
471 | ||
472 | cache = microblaze_alloc_frame_cache (); | |
473 | *this_cache = cache; | |
474 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
475 | ||
476 | /* Clear offsets to saved regs in frame. */ | |
477 | for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++) | |
478 | cache->register_offsets[rn] = -1; | |
479 | ||
480 | func = get_frame_func (next_frame); | |
481 | ||
482 | cache->pc = get_frame_address_in_block (next_frame); | |
483 | ||
484 | return cache; | |
485 | } | |
486 | ||
487 | static void | |
488 | microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
489 | struct frame_id *this_id) | |
490 | { | |
491 | struct microblaze_frame_cache *cache = | |
492 | microblaze_frame_cache (next_frame, this_cache); | |
493 | ||
494 | /* This marks the outermost frame. */ | |
495 | if (cache->base == 0) | |
496 | return; | |
497 | ||
498 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
499 | } | |
500 | ||
501 | static struct value * | |
502 | microblaze_frame_prev_register (struct frame_info *this_frame, | |
503 | void **this_cache, int regnum) | |
504 | { | |
505 | struct microblaze_frame_cache *cache = | |
506 | microblaze_frame_cache (this_frame, this_cache); | |
507 | ||
508 | if (cache->frameless_p) | |
509 | { | |
510 | if (regnum == MICROBLAZE_PC_REGNUM) | |
511 | regnum = 15; | |
512 | if (regnum == MICROBLAZE_SP_REGNUM) | |
513 | regnum = 1; | |
025bb325 MS |
514 | return trad_frame_get_prev_register (this_frame, |
515 | cache->saved_regs, regnum); | |
2d1c1221 ME |
516 | } |
517 | else | |
518 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
519 | regnum); | |
520 | ||
521 | } | |
522 | ||
523 | static const struct frame_unwind microblaze_frame_unwind = | |
524 | { | |
525 | NORMAL_FRAME, | |
8fbca658 | 526 | default_frame_unwind_stop_reason, |
2d1c1221 ME |
527 | microblaze_frame_this_id, |
528 | microblaze_frame_prev_register, | |
529 | NULL, | |
530 | default_frame_sniffer | |
531 | }; | |
532 | \f | |
533 | static CORE_ADDR | |
025bb325 MS |
534 | microblaze_frame_base_address (struct frame_info *next_frame, |
535 | void **this_cache) | |
2d1c1221 ME |
536 | { |
537 | struct microblaze_frame_cache *cache = | |
538 | microblaze_frame_cache (next_frame, this_cache); | |
539 | ||
540 | return cache->base; | |
541 | } | |
542 | ||
543 | static const struct frame_base microblaze_frame_base = | |
544 | { | |
545 | µblaze_frame_unwind, | |
546 | microblaze_frame_base_address, | |
547 | microblaze_frame_base_address, | |
548 | microblaze_frame_base_address | |
549 | }; | |
550 | \f | |
551 | /* Extract from an array REGBUF containing the (raw) register state, a | |
552 | function return value of TYPE, and copy that into VALBUF. */ | |
553 | static void | |
554 | microblaze_extract_return_value (struct type *type, struct regcache *regcache, | |
555 | gdb_byte *valbuf) | |
556 | { | |
557 | gdb_byte buf[8]; | |
558 | ||
559 | /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */ | |
560 | switch (TYPE_LENGTH (type)) | |
561 | { | |
562 | case 1: /* return last byte in the register. */ | |
563 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf); | |
564 | memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1); | |
565 | return; | |
566 | case 2: /* return last 2 bytes in register. */ | |
6425366c | 567 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf); |
2d1c1221 ME |
568 | memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2); |
569 | return; | |
570 | case 4: /* for sizes 4 or 8, copy the required length. */ | |
571 | case 8: | |
572 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf); | |
573 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf+4); | |
574 | memcpy (valbuf, buf, TYPE_LENGTH (type)); | |
575 | return; | |
576 | default: | |
577 | internal_error (__FILE__, __LINE__, | |
578 | _("Unsupported return value size requested")); | |
579 | } | |
580 | } | |
581 | ||
582 | /* Store the return value in VALBUF (of type TYPE) where the caller | |
583 | expects to see it. | |
584 | ||
585 | Integers up to four bytes are stored in r3. | |
586 | ||
587 | Longs are stored in r3 (most significant word) and r4 (least | |
588 | significant word). | |
589 | ||
025bb325 | 590 | Small structures are always returned on stack. */ |
2d1c1221 ME |
591 | |
592 | static void | |
593 | microblaze_store_return_value (struct type *type, struct regcache *regcache, | |
594 | const gdb_byte *valbuf) | |
595 | { | |
bad43aa5 | 596 | int len = TYPE_LENGTH (type); |
2d1c1221 ME |
597 | gdb_byte buf[8]; |
598 | ||
599 | memset (buf, 0, sizeof(buf)); | |
600 | ||
601 | /* Integral and pointer return values. */ | |
602 | ||
bad43aa5 | 603 | if (len > 4) |
2d1c1221 | 604 | { |
bad43aa5 | 605 | gdb_assert (len == 8); |
2d1c1221 ME |
606 | memcpy (buf, valbuf, 8); |
607 | regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf + 4); | |
608 | } | |
609 | else | |
610 | /* ??? Do we need to do any sign-extension here? */ | |
bad43aa5 | 611 | memcpy (buf + 4 - len, valbuf, len); |
2d1c1221 ME |
612 | |
613 | regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM, buf); | |
614 | } | |
615 | ||
616 | static enum return_value_convention | |
6a3a010b | 617 | microblaze_return_value (struct gdbarch *gdbarch, struct value *function, |
2d1c1221 ME |
618 | struct type *type, struct regcache *regcache, |
619 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
620 | { | |
621 | if (readbuf) | |
622 | microblaze_extract_return_value (type, regcache, readbuf); | |
623 | if (writebuf) | |
624 | microblaze_store_return_value (type, regcache, writebuf); | |
625 | ||
626 | return RETURN_VALUE_REGISTER_CONVENTION; | |
627 | } | |
628 | ||
629 | static int | |
630 | microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
631 | { | |
632 | return (TYPE_LENGTH (type) == 16); | |
633 | } | |
634 | ||
635 | static void | |
636 | microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) | |
637 | { | |
638 | regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc); | |
639 | } | |
640 | \f | |
641 | static int dwarf2_to_reg_map[78] = | |
642 | { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ | |
643 | 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ | |
644 | 8 /* r8 */, 9 /* r9 */, 10 /* r10 */, 11 /* r11 */, /* 8-11 */ | |
645 | 12 /* r12 */, 13 /* r13 */, 14 /* r14 */, 15 /* r15 */, /* 12-15 */ | |
646 | 16 /* r16 */, 17 /* r17 */, 18 /* r18 */, 19 /* r19 */, /* 16-19 */ | |
647 | 20 /* r20 */, 21 /* r21 */, 22 /* r22 */, 23 /* r23 */, /* 20-23 */ | |
648 | 24 /* r24 */, 25 /* r25 */, 26 /* r26 */, 27 /* r27 */, /* 24-25 */ | |
649 | 28 /* r28 */, 29 /* r29 */, 30 /* r30 */, 31 /* r31 */, /* 28-31 */ | |
650 | -1 /* $f0 */, -1 /* $f1 */, -1 /* $f2 */, -1 /* $f3 */, /* 32-35 */ | |
651 | -1 /* $f4 */, -1 /* $f5 */, -1 /* $f6 */, -1 /* $f7 */, /* 36-39 */ | |
652 | -1 /* $f8 */, -1 /* $f9 */, -1 /* $f10 */, -1 /* $f11 */, /* 40-43 */ | |
653 | -1 /* $f12 */, -1 /* $f13 */, -1 /* $f14 */, -1 /* $f15 */, /* 44-47 */ | |
654 | -1 /* $f16 */, -1 /* $f17 */, -1 /* $f18 */, -1 /* $f19 */, /* 48-51 */ | |
655 | -1 /* $f20 */, -1 /* $f21 */, -1 /* $f22 */, -1 /* $f23 */, /* 52-55 */ | |
656 | -1 /* $f24 */, -1 /* $f25 */, -1 /* $f26 */, -1 /* $f27 */, /* 56-59 */ | |
657 | -1 /* $f28 */, -1 /* $f29 */, -1 /* $f30 */, -1 /* $f31 */, /* 60-63 */ | |
658 | -1 /* hi */, -1 /* lo */, -1 /* accum*/, 33 /* rmsr */, /* 64-67 */ | |
659 | -1 /* $fcc1*/, -1 /* $fcc2*/, -1 /* $fcc3*/, -1 /* $fcc4*/, /* 68-71 */ | |
660 | -1 /* $fcc5*/, -1 /* $fcc6*/, -1 /* $fcc7*/, -1 /* $ap */, /* 72-75 */ | |
661 | -1 /* $rap */, -1 /* $frp */ /* 76-77 */ | |
662 | }; | |
663 | ||
664 | static int | |
665 | microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
666 | { | |
667 | gdb_assert (reg < sizeof (dwarf2_to_reg_map)); | |
668 | return dwarf2_to_reg_map[reg]; | |
669 | } | |
670 | ||
164224e9 ME |
671 | static void |
672 | microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) | |
673 | { | |
674 | register_remote_g_packet_guess (gdbarch, | |
675 | 4 * MICROBLAZE_NUM_CORE_REGS, | |
676 | tdesc_microblaze); | |
677 | ||
678 | register_remote_g_packet_guess (gdbarch, | |
679 | 4 * MICROBLAZE_NUM_REGS, | |
680 | tdesc_microblaze_with_stack_protect); | |
681 | } | |
682 | ||
2d1c1221 ME |
683 | static struct gdbarch * |
684 | microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
685 | { | |
686 | struct gdbarch_tdep *tdep; | |
687 | struct gdbarch *gdbarch; | |
164224e9 ME |
688 | struct tdesc_arch_data *tdesc_data = NULL; |
689 | const struct target_desc *tdesc = info.target_desc; | |
2d1c1221 ME |
690 | |
691 | /* If there is already a candidate, use it. */ | |
692 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
693 | if (arches != NULL) | |
694 | return arches->gdbarch; | |
164224e9 ME |
695 | if (tdesc == NULL) |
696 | tdesc = tdesc_microblaze; | |
697 | ||
698 | /* Check any target description for validity. */ | |
699 | if (tdesc_has_registers (tdesc)) | |
700 | { | |
701 | const struct tdesc_feature *feature; | |
702 | int valid_p; | |
703 | int i; | |
704 | ||
705 | feature = tdesc_find_feature (tdesc, | |
706 | "org.gnu.gdb.microblaze.core"); | |
707 | if (feature == NULL) | |
708 | return NULL; | |
709 | tdesc_data = tdesc_data_alloc (); | |
710 | ||
711 | valid_p = 1; | |
712 | for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++) | |
713 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
714 | microblaze_register_names[i]); | |
715 | feature = tdesc_find_feature (tdesc, | |
716 | "org.gnu.gdb.microblaze.stack-protect"); | |
717 | if (feature != NULL) | |
718 | { | |
719 | valid_p = 1; | |
720 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
721 | MICROBLAZE_SLR_REGNUM, | |
722 | "rslr"); | |
723 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
724 | MICROBLAZE_SHR_REGNUM, | |
725 | "rshr"); | |
726 | } | |
727 | } | |
2d1c1221 ME |
728 | |
729 | /* Allocate space for the new architecture. */ | |
70ba0933 | 730 | tdep = XNEW (struct gdbarch_tdep); |
2d1c1221 ME |
731 | gdbarch = gdbarch_alloc (&info, tdep); |
732 | ||
733 | set_gdbarch_long_double_bit (gdbarch, 128); | |
734 | ||
735 | set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS); | |
736 | set_gdbarch_register_name (gdbarch, microblaze_register_name); | |
737 | set_gdbarch_register_type (gdbarch, microblaze_register_type); | |
738 | ||
739 | /* Register numbers of various important registers. */ | |
740 | set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); | |
741 | set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); | |
742 | ||
743 | /* Map Dwarf2 registers to GDB registers. */ | |
744 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); | |
745 | ||
746 | /* Call dummy code. */ | |
747 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
748 | set_gdbarch_push_dummy_code (gdbarch, microblaze_push_dummy_code); | |
749 | set_gdbarch_push_dummy_call (gdbarch, microblaze_push_dummy_call); | |
750 | ||
751 | set_gdbarch_return_value (gdbarch, microblaze_return_value); | |
752 | set_gdbarch_stabs_argument_has_addr | |
753 | (gdbarch, microblaze_stabs_argument_has_addr); | |
754 | ||
755 | set_gdbarch_skip_prologue (gdbarch, microblaze_skip_prologue); | |
756 | ||
757 | /* Stack grows downward. */ | |
758 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
759 | ||
760 | set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc); | |
761 | ||
762 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
763 | ||
764 | set_gdbarch_print_insn (gdbarch, print_insn_microblaze); | |
765 | ||
766 | set_gdbarch_write_pc (gdbarch, microblaze_write_pc); | |
767 | ||
768 | set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); | |
769 | ||
164224e9 ME |
770 | microblaze_register_g_packet_guesses (gdbarch); |
771 | ||
2d1c1221 ME |
772 | frame_base_set_default (gdbarch, µblaze_frame_base); |
773 | ||
774 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
775 | gdbarch_init_osabi (info, gdbarch); | |
776 | ||
025bb325 | 777 | /* Unwind the frame. */ |
2d1c1221 ME |
778 | dwarf2_append_unwinders (gdbarch); |
779 | frame_unwind_append_unwinder (gdbarch, µblaze_frame_unwind); | |
780 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); | |
164224e9 ME |
781 | if (tdesc_data != NULL) |
782 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
2d1c1221 ME |
783 | |
784 | return gdbarch; | |
785 | } | |
786 | ||
787 | /* Provide a prototype to silence -Wmissing-prototypes. */ | |
788 | void _initialize_microblaze_tdep (void); | |
789 | ||
790 | void | |
791 | _initialize_microblaze_tdep (void) | |
792 | { | |
793 | register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init); | |
794 | ||
164224e9 ME |
795 | initialize_tdesc_microblaze_with_stack_protect (); |
796 | initialize_tdesc_microblaze (); | |
2d1c1221 | 797 | /* Debug this files internals. */ |
ccce17b0 YQ |
798 | add_setshow_zuinteger_cmd ("microblaze", class_maintenance, |
799 | µblaze_debug_flag, _("\ | |
2d1c1221 ME |
800 | Set microblaze debugging."), _("\ |
801 | Show microblaze debugging."), _("\ | |
802 | When non-zero, microblaze specific debugging is enabled."), | |
ccce17b0 YQ |
803 | NULL, |
804 | NULL, | |
805 | &setdebuglist, &showdebuglist); | |
2d1c1221 ME |
806 | |
807 | } |