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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
e2882c85 | 3 | Copyright (C) 2001-2018 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
d37eb719 | 23 | #include "inferior.h" |
6b753f60 | 24 | #include "mips-tdep.h" |
10d6c8cd | 25 | #include "target.h" |
28f5035f | 26 | #include "regcache.h" |
6798487f | 27 | #include "linux-nat-trad.h" |
d37eb719 | 28 | #include "mips-linux-tdep.h" |
822b6570 | 29 | #include "target-descriptions.h" |
2aa830e4 | 30 | |
dc60ece8 | 31 | #include "gdb_proc_service.h" |
3e00823e | 32 | #include "gregset.h" |
dc60ece8 | 33 | |
822b6570 | 34 | #include <sgidefs.h> |
5826e159 | 35 | #include "nat/gdb_ptrace.h" |
9be14b81 | 36 | #include <asm/ptrace.h> |
bcc0c096 | 37 | #include "inf-ptrace.h" |
d37eb719 | 38 | |
125f8a3d | 39 | #include "nat/mips-linux-watch.h" |
aaee2056 | 40 | |
dc60ece8 DJ |
41 | #ifndef PTRACE_GET_THREAD_AREA |
42 | #define PTRACE_GET_THREAD_AREA 25 | |
43 | #endif | |
44 | ||
f6ac5f3d PA |
45 | class mips_linux_nat_target final : public linux_nat_trad_target |
46 | { | |
47 | public: | |
48 | /* Add our register access methods. */ | |
49 | void fetch_registers (struct regcache *, int) override; | |
50 | void store_registers (struct regcache *, int) override; | |
51 | ||
52 | void close () override; | |
53 | ||
54 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
55 | ||
56 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
57 | struct expression *) override; | |
58 | ||
59 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
60 | struct expression *) override; | |
61 | ||
57810aa7 | 62 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 63 | |
57810aa7 | 64 | bool stopped_data_address (CORE_ADDR *) override; |
d37eb719 | 65 | |
f6ac5f3d | 66 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; |
d37eb719 | 67 | |
f6ac5f3d | 68 | const struct target_desc *read_description () override; |
b9412953 | 69 | |
f6ac5f3d PA |
70 | protected: |
71 | /* Override linux_nat_trad_target methods. */ | |
72 | CORE_ADDR register_u_offset (struct gdbarch *gdbarch, | |
73 | int regno, int store_p) override; | |
74 | ||
135340af PA |
75 | /* Override linux_nat_target low methods. */ |
76 | void low_new_thread (struct lwp_info *lp) override; | |
77 | ||
f6ac5f3d PA |
78 | private: |
79 | /* Helpers. See definitions. */ | |
80 | void mips64_regsets_store_registers (struct regcache *regcache, | |
81 | int regno); | |
82 | void mips64_regsets_fetch_registers (struct regcache *regcache, | |
83 | int regno); | |
84 | }; | |
85 | ||
86 | static mips_linux_nat_target the_mips_linux_nat_target; | |
87 | ||
88 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, | |
89 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
90 | static int have_ptrace_regsets = 1; | |
d37eb719 | 91 | |
dda0c97e | 92 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
93 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
94 | ||
95 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
96 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
97 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
98 | |
99 | static CORE_ADDR | |
7714d83a | 100 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 101 | { |
7714d83a | 102 | CORE_ADDR regaddr; |
dda0c97e | 103 | |
2eb4d78b | 104 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
105 | error (_("Bogon register number %d."), regno); |
106 | ||
7714d83a | 107 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 108 | regaddr = regno; |
7714d83a UW |
109 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
110 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
111 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
112 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 113 | regaddr = PC; |
7714d83a UW |
114 | else if (regno == mips_regnum (gdbarch)->cause) |
115 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
116 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
117 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
118 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 119 | regaddr = MMLO; |
7714d83a | 120 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 121 | regaddr = MMHI; |
7714d83a | 122 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 123 | regaddr = FPC_CSR; |
7714d83a UW |
124 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
125 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
126 | else if (mips_regnum (gdbarch)->dspacc != -1 |
127 | && regno >= mips_regnum (gdbarch)->dspacc | |
128 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
129 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
130 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
131 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
132 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
133 | regaddr = 0; | |
dda0c97e | 134 | else |
7714d83a | 135 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
136 | |
137 | return regaddr; | |
138 | } | |
139 | ||
140 | static CORE_ADDR | |
7714d83a | 141 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 142 | { |
7714d83a | 143 | CORE_ADDR regaddr; |
dda0c97e | 144 | |
2eb4d78b | 145 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
146 | error (_("Bogon register number %d."), regno); |
147 | ||
7714d83a | 148 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 149 | regaddr = regno; |
7714d83a UW |
150 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
151 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 152 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 153 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 154 | regaddr = MIPS64_PC; |
7714d83a UW |
155 | else if (regno == mips_regnum (gdbarch)->cause) |
156 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
157 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
158 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
159 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 160 | regaddr = MIPS64_MMLO; |
7714d83a | 161 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 162 | regaddr = MIPS64_MMHI; |
7714d83a | 163 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 164 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
165 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
166 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
167 | else if (mips_regnum (gdbarch)->dspacc != -1 |
168 | && regno >= mips_regnum (gdbarch)->dspacc | |
169 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
170 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
171 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
172 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
173 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
174 | regaddr = 0; | |
dda0c97e | 175 | else |
7714d83a | 176 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
177 | |
178 | return regaddr; | |
179 | } | |
180 | ||
dc60ece8 DJ |
181 | /* Fetch the thread-local storage pointer for libthread_db. */ |
182 | ||
183 | ps_err_e | |
754653a7 | 184 | ps_get_thread_area (struct ps_prochandle *ph, |
dc60ece8 DJ |
185 | lwpid_t lwpid, int idx, void **base) |
186 | { | |
187 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
188 | return PS_ERR; | |
189 | ||
190 | /* IDX is the bias from the thread pointer to the beginning of the | |
191 | thread descriptor. It has to be subtracted due to implementation | |
192 | quirks in libthread_db. */ | |
193 | *base = (void *) ((char *)*base - idx); | |
194 | ||
195 | return PS_OK; | |
196 | } | |
197 | ||
3e00823e UW |
198 | /* Wrapper functions. These are only used by libthread_db. */ |
199 | ||
200 | void | |
7f7fe91e | 201 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 202 | { |
ac7936df | 203 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 204 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 205 | else |
7f7fe91e | 206 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
207 | } |
208 | ||
209 | void | |
7f7fe91e UW |
210 | fill_gregset (const struct regcache *regcache, |
211 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 212 | { |
ac7936df | 213 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 214 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 215 | else |
7f7fe91e | 216 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
217 | } |
218 | ||
219 | void | |
7f7fe91e | 220 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 221 | { |
ac7936df | 222 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 223 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 224 | else |
025bb325 MS |
225 | mips64_supply_fpregset (regcache, |
226 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
227 | } |
228 | ||
229 | void | |
7f7fe91e UW |
230 | fill_fpregset (const struct regcache *regcache, |
231 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 232 | { |
ac7936df | 233 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 234 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 235 | else |
025bb325 MS |
236 | mips64_fill_fpregset (regcache, |
237 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
238 | } |
239 | ||
240 | ||
d37eb719 DJ |
241 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
242 | using PTRACE_GETREGS et al. */ | |
243 | ||
f6ac5f3d PA |
244 | void |
245 | mips_linux_nat_target::mips64_regsets_fetch_registers | |
246 | (struct regcache *regcache, int regno) | |
d37eb719 | 247 | { |
ac7936df | 248 | struct gdbarch *gdbarch = regcache->arch (); |
1faeff08 MR |
249 | int is_fp, is_dsp; |
250 | int have_dsp; | |
251 | int regi; | |
d37eb719 DJ |
252 | int tid; |
253 | ||
2eb4d78b UW |
254 | if (regno >= mips_regnum (gdbarch)->fp0 |
255 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 256 | is_fp = 1; |
2eb4d78b | 257 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 258 | is_fp = 1; |
2eb4d78b | 259 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
260 | is_fp = 1; |
261 | else | |
262 | is_fp = 0; | |
263 | ||
1faeff08 MR |
264 | /* DSP registers are optional and not a part of any set. */ |
265 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
266 | if (!have_dsp) | |
267 | is_dsp = 0; | |
268 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
269 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
270 | is_dsp = 1; | |
271 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
272 | is_dsp = 1; | |
273 | else | |
274 | is_dsp = 0; | |
275 | ||
bcc0c096 | 276 | tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
d37eb719 | 277 | |
1faeff08 | 278 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
279 | { |
280 | mips64_elf_gregset_t regs; | |
281 | ||
282 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
283 | { | |
284 | if (errno == EIO) | |
285 | { | |
286 | have_ptrace_regsets = 0; | |
287 | return; | |
288 | } | |
289 | perror_with_name (_("Couldn't get registers")); | |
290 | } | |
291 | ||
56be3814 | 292 | mips64_supply_gregset (regcache, |
28f5035f | 293 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
294 | } |
295 | ||
296 | if (regno == -1 || is_fp) | |
297 | { | |
298 | mips64_elf_fpregset_t fp_regs; | |
299 | ||
300 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
301 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
302 | { | |
303 | if (errno == EIO) | |
304 | { | |
305 | have_ptrace_regsets = 0; | |
306 | return; | |
307 | } | |
308 | perror_with_name (_("Couldn't get FP registers")); | |
309 | } | |
310 | ||
56be3814 | 311 | mips64_supply_fpregset (regcache, |
28f5035f | 312 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 313 | } |
1faeff08 MR |
314 | |
315 | if (is_dsp) | |
f6ac5f3d | 316 | linux_nat_trad_target::fetch_registers (regcache, regno); |
1faeff08 MR |
317 | else if (regno == -1 && have_dsp) |
318 | { | |
319 | for (regi = mips_regnum (gdbarch)->dspacc; | |
320 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
321 | regi++) | |
f6ac5f3d PA |
322 | linux_nat_trad_target::fetch_registers (regcache, regi); |
323 | linux_nat_trad_target::fetch_registers (regcache, | |
324 | mips_regnum (gdbarch)->dspctl); | |
1faeff08 | 325 | } |
d37eb719 DJ |
326 | } |
327 | ||
328 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
329 | using PTRACE_SETREGS et al. */ | |
330 | ||
f6ac5f3d PA |
331 | void |
332 | mips_linux_nat_target::mips64_regsets_store_registers | |
333 | (struct regcache *regcache, int regno) | |
d37eb719 | 334 | { |
ac7936df | 335 | struct gdbarch *gdbarch = regcache->arch (); |
1faeff08 MR |
336 | int is_fp, is_dsp; |
337 | int have_dsp; | |
338 | int regi; | |
d37eb719 DJ |
339 | int tid; |
340 | ||
2eb4d78b UW |
341 | if (regno >= mips_regnum (gdbarch)->fp0 |
342 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 343 | is_fp = 1; |
2eb4d78b | 344 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 345 | is_fp = 1; |
2eb4d78b | 346 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
347 | is_fp = 1; |
348 | else | |
349 | is_fp = 0; | |
350 | ||
1faeff08 MR |
351 | /* DSP registers are optional and not a part of any set. */ |
352 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
353 | if (!have_dsp) | |
354 | is_dsp = 0; | |
6ce4c112 | 355 | else if (regno >= mips_regnum (gdbarch)->dspacc |
1faeff08 MR |
356 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
357 | is_dsp = 1; | |
358 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
359 | is_dsp = 1; | |
360 | else | |
361 | is_dsp = 0; | |
362 | ||
bcc0c096 | 363 | tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
d37eb719 | 364 | |
1faeff08 | 365 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
366 | { |
367 | mips64_elf_gregset_t regs; | |
368 | ||
369 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
370 | perror_with_name (_("Couldn't get registers")); | |
371 | ||
56be3814 | 372 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
373 | |
374 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
375 | perror_with_name (_("Couldn't set registers")); | |
376 | } | |
377 | ||
378 | if (regno == -1 || is_fp) | |
379 | { | |
380 | mips64_elf_fpregset_t fp_regs; | |
381 | ||
382 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
383 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
384 | perror_with_name (_("Couldn't get FP registers")); | |
385 | ||
56be3814 | 386 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
387 | |
388 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
389 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
390 | perror_with_name (_("Couldn't set FP registers")); | |
391 | } | |
1faeff08 MR |
392 | |
393 | if (is_dsp) | |
f6ac5f3d | 394 | linux_nat_trad_target::store_registers (regcache, regno); |
1faeff08 MR |
395 | else if (regno == -1 && have_dsp) |
396 | { | |
397 | for (regi = mips_regnum (gdbarch)->dspacc; | |
398 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
399 | regi++) | |
f6ac5f3d PA |
400 | linux_nat_trad_target::store_registers (regcache, regi); |
401 | linux_nat_trad_target::store_registers (regcache, | |
402 | mips_regnum (gdbarch)->dspctl); | |
1faeff08 | 403 | } |
d37eb719 DJ |
404 | } |
405 | ||
406 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
407 | using any working method. */ | |
408 | ||
f6ac5f3d PA |
409 | void |
410 | mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) | |
d37eb719 DJ |
411 | { |
412 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
413 | if (have_ptrace_regsets) | |
f6ac5f3d | 414 | mips64_regsets_fetch_registers (regcache, regnum); |
d37eb719 DJ |
415 | |
416 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
417 | back to PTRACE_PEEKUSER. */ | |
418 | if (!have_ptrace_regsets) | |
f6ac5f3d | 419 | linux_nat_trad_target::fetch_registers (regcache, regnum); |
d37eb719 DJ |
420 | } |
421 | ||
422 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
423 | using any working method. */ | |
424 | ||
f6ac5f3d PA |
425 | void |
426 | mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum) | |
d37eb719 DJ |
427 | { |
428 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
429 | if (have_ptrace_regsets) | |
f6ac5f3d | 430 | mips64_regsets_store_registers (regcache, regnum); |
d37eb719 DJ |
431 | |
432 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
433 | back to PTRACE_PEEKUSER. */ | |
434 | if (!have_ptrace_regsets) | |
f6ac5f3d | 435 | linux_nat_trad_target::store_registers (regcache, regnum); |
d37eb719 DJ |
436 | } |
437 | ||
910122bf UW |
438 | /* Return the address in the core dump or inferior of register |
439 | REGNO. */ | |
440 | ||
f6ac5f3d PA |
441 | CORE_ADDR |
442 | mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch, | |
443 | int regno, int store_p) | |
910122bf | 444 | { |
7714d83a UW |
445 | if (mips_abi_regsize (gdbarch) == 8) |
446 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 447 | else |
7714d83a | 448 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
449 | } |
450 | ||
f6ac5f3d PA |
451 | const struct target_desc * |
452 | mips_linux_nat_target::read_description () | |
822b6570 | 453 | { |
1faeff08 MR |
454 | static int have_dsp = -1; |
455 | ||
456 | if (have_dsp < 0) | |
457 | { | |
458 | int tid; | |
459 | ||
460 | tid = ptid_get_lwp (inferior_ptid); | |
461 | if (tid == 0) | |
462 | tid = ptid_get_pid (inferior_ptid); | |
463 | ||
ac740bc7 | 464 | errno = 0; |
1faeff08 MR |
465 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); |
466 | switch (errno) | |
467 | { | |
468 | case 0: | |
469 | have_dsp = 1; | |
470 | break; | |
471 | case EIO: | |
472 | have_dsp = 0; | |
473 | break; | |
474 | default: | |
837a1b32 | 475 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
476 | break; |
477 | } | |
478 | } | |
479 | ||
81adfced DJ |
480 | /* Report that target registers are a size we know for sure |
481 | that we can get from ptrace. */ | |
482 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 483 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 484 | else |
1faeff08 | 485 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
486 | } |
487 | ||
b9412953 DD |
488 | /* -1 if the kernel and/or CPU do not support watch registers. |
489 | 1 if watch_readback is valid and we can read style, num_valid | |
490 | and the masks. | |
491 | 0 if we need to read the watch_readback. */ | |
492 | ||
493 | static int watch_readback_valid; | |
494 | ||
495 | /* Cached watch register read values. */ | |
496 | ||
497 | static struct pt_watch_regs watch_readback; | |
498 | ||
b9412953 DD |
499 | static struct mips_watchpoint *current_watches; |
500 | ||
501 | /* The current set of watch register values for writing the | |
502 | registers. */ | |
503 | ||
504 | static struct pt_watch_regs watch_mirror; | |
505 | ||
b9412953 DD |
506 | static void |
507 | mips_show_dr (const char *func, CORE_ADDR addr, | |
508 | int len, enum target_hw_bp_type type) | |
509 | { | |
510 | int i; | |
511 | ||
512 | puts_unfiltered (func); | |
513 | if (addr || len) | |
5af949e3 | 514 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
f5656ead | 515 | paddress (target_gdbarch (), addr), len, |
b9412953 DD |
516 | type == hw_write ? "data-write" |
517 | : (type == hw_read ? "data-read" | |
518 | : (type == hw_access ? "data-read/write" | |
519 | : (type == hw_execute ? "instruction-execute" | |
520 | : "??unknown??")))); | |
521 | puts_unfiltered (":\n"); | |
522 | ||
523 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 | 524 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
f5656ead | 525 | paddress (target_gdbarch (), |
b3436450 YQ |
526 | mips_linux_watch_get_watchlo (&watch_mirror, |
527 | i)), | |
f5656ead | 528 | paddress (target_gdbarch (), |
b3436450 YQ |
529 | mips_linux_watch_get_watchhi (&watch_mirror, |
530 | i))); | |
b9412953 DD |
531 | } |
532 | ||
b9412953 DD |
533 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can |
534 | handle the specified watch type. */ | |
535 | ||
f6ac5f3d PA |
536 | int |
537 | mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
538 | int cnt, int ot) | |
b9412953 DD |
539 | { |
540 | int i; | |
541 | uint32_t wanted_mask, irw_mask; | |
542 | ||
b3436450 YQ |
543 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
544 | &watch_readback, | |
545 | &watch_readback_valid, 0)) | |
b9412953 DD |
546 | return 0; |
547 | ||
548 | switch (type) | |
549 | { | |
550 | case bp_hardware_watchpoint: | |
551 | wanted_mask = W_MASK; | |
552 | break; | |
553 | case bp_read_watchpoint: | |
554 | wanted_mask = R_MASK; | |
555 | break; | |
556 | case bp_access_watchpoint: | |
557 | wanted_mask = R_MASK | W_MASK; | |
558 | break; | |
559 | default: | |
560 | return 0; | |
561 | } | |
562 | ||
b3436450 YQ |
563 | for (i = 0; |
564 | i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; | |
565 | i++) | |
b9412953 | 566 | { |
b3436450 | 567 | irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); |
b9412953 DD |
568 | if ((irw_mask & wanted_mask) == wanted_mask) |
569 | cnt--; | |
570 | } | |
571 | return (cnt == 0) ? 1 : 0; | |
572 | } | |
573 | ||
574 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
575 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 576 | register triggered. */ |
b9412953 | 577 | |
57810aa7 | 578 | bool |
f6ac5f3d | 579 | mips_linux_nat_target::stopped_by_watchpoint () |
b9412953 DD |
580 | { |
581 | int n; | |
582 | int num_valid; | |
583 | ||
b3436450 YQ |
584 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
585 | &watch_readback, | |
586 | &watch_readback_valid, 1)) | |
57810aa7 | 587 | return false; |
b9412953 | 588 | |
b3436450 | 589 | num_valid = mips_linux_watch_get_num_valid (&watch_readback); |
b9412953 DD |
590 | |
591 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
b3436450 | 592 | if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) |
57810aa7 | 593 | return true; |
b9412953 | 594 | |
57810aa7 | 595 | return false; |
b9412953 DD |
596 | } |
597 | ||
598 | /* Target to_stopped_data_address implementation. Set the address | |
599 | where the watch triggered (if known). Return 1 if the address was | |
600 | known. */ | |
601 | ||
57810aa7 | 602 | bool |
f6ac5f3d | 603 | mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr) |
b9412953 DD |
604 | { |
605 | /* On mips we don't know the low order 3 bits of the data address, | |
606 | so we must return false. */ | |
57810aa7 | 607 | return false; |
b9412953 DD |
608 | } |
609 | ||
b9412953 DD |
610 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if |
611 | the specified region can be covered by the watch registers. */ | |
612 | ||
f6ac5f3d PA |
613 | int |
614 | mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
b9412953 DD |
615 | { |
616 | struct pt_watch_regs dummy_regs; | |
617 | int i; | |
618 | ||
b3436450 YQ |
619 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
620 | &watch_readback, | |
621 | &watch_readback_valid, 0)) | |
b9412953 DD |
622 | return 0; |
623 | ||
624 | dummy_regs = watch_readback; | |
625 | /* Clear them out. */ | |
b3436450 YQ |
626 | for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) |
627 | mips_linux_watch_set_watchlo (&dummy_regs, i, 0); | |
628 | return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); | |
b9412953 DD |
629 | } |
630 | ||
b9412953 DD |
631 | /* Write the mirrored watch register values for each thread. */ |
632 | ||
633 | static int | |
634 | write_watchpoint_regs (void) | |
635 | { | |
636 | struct lwp_info *lp; | |
b9412953 DD |
637 | int tid; |
638 | ||
4c38200f | 639 | ALL_LWPS (lp) |
b9412953 | 640 | { |
4c38200f | 641 | tid = ptid_get_lwp (lp->ptid); |
aa58a496 | 642 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
643 | perror_with_name (_("Couldn't write debug register")); |
644 | } | |
645 | return 0; | |
646 | } | |
647 | ||
135340af PA |
648 | /* linux_nat_target::low_new_thread implementation. Write the |
649 | mirrored watch register values for the new thread. */ | |
b9412953 | 650 | |
135340af PA |
651 | void |
652 | mips_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
b9412953 | 653 | { |
339053c2 | 654 | long tid = lp->ptid.lwp (); |
b9412953 | 655 | |
7974a605 | 656 | if (!mips_linux_read_watch_registers (tid, |
b3436450 YQ |
657 | &watch_readback, |
658 | &watch_readback_valid, 0)) | |
b9412953 DD |
659 | return; |
660 | ||
aa58a496 | 661 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
662 | perror_with_name (_("Couldn't write debug register")); |
663 | } | |
664 | ||
b9412953 DD |
665 | /* Target to_insert_watchpoint implementation. Try to insert a new |
666 | watch. Return zero on success. */ | |
667 | ||
f6ac5f3d PA |
668 | int |
669 | mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
670 | enum target_hw_bp_type type, | |
671 | struct expression *cond) | |
b9412953 DD |
672 | { |
673 | struct pt_watch_regs regs; | |
674 | struct mips_watchpoint *new_watch; | |
675 | struct mips_watchpoint **pw; | |
676 | ||
677 | int i; | |
678 | int retval; | |
679 | ||
b3436450 YQ |
680 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
681 | &watch_readback, | |
682 | &watch_readback_valid, 0)) | |
b9412953 DD |
683 | return -1; |
684 | ||
685 | if (len <= 0) | |
686 | return -1; | |
687 | ||
688 | regs = watch_readback; | |
689 | /* Add the current watches. */ | |
b3436450 | 690 | mips_linux_watch_populate_regs (current_watches, ®s); |
b9412953 DD |
691 | |
692 | /* Now try to add the new watch. */ | |
b3436450 YQ |
693 | if (!mips_linux_watch_try_one_watch (®s, addr, len, |
694 | mips_linux_watch_type_to_irw (type))) | |
b9412953 DD |
695 | return -1; |
696 | ||
697 | /* It fit. Stick it on the end of the list. */ | |
8d749320 | 698 | new_watch = XNEW (struct mips_watchpoint); |
b9412953 DD |
699 | new_watch->addr = addr; |
700 | new_watch->len = len; | |
701 | new_watch->type = type; | |
702 | new_watch->next = NULL; | |
703 | ||
704 | pw = ¤t_watches; | |
705 | while (*pw != NULL) | |
706 | pw = &(*pw)->next; | |
707 | *pw = new_watch; | |
708 | ||
709 | watch_mirror = regs; | |
710 | retval = write_watchpoint_regs (); | |
711 | ||
c5e92cca | 712 | if (show_debug_regs) |
b9412953 DD |
713 | mips_show_dr ("insert_watchpoint", addr, len, type); |
714 | ||
715 | return retval; | |
716 | } | |
717 | ||
718 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
719 | Return zero on success. */ | |
720 | ||
f6ac5f3d PA |
721 | int |
722 | mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
723 | enum target_hw_bp_type type, | |
724 | struct expression *cond) | |
b9412953 DD |
725 | { |
726 | int retval; | |
727 | int deleted_one; | |
728 | ||
729 | struct mips_watchpoint **pw; | |
730 | struct mips_watchpoint *w; | |
731 | ||
732 | /* Search for a known watch that matches. Then unlink and free | |
733 | it. */ | |
734 | deleted_one = 0; | |
735 | pw = ¤t_watches; | |
736 | while ((w = *pw)) | |
737 | { | |
738 | if (w->addr == addr && w->len == len && w->type == type) | |
739 | { | |
740 | *pw = w->next; | |
741 | xfree (w); | |
742 | deleted_one = 1; | |
743 | break; | |
744 | } | |
745 | pw = &(w->next); | |
746 | } | |
747 | ||
748 | if (!deleted_one) | |
749 | return -1; /* We don't know about it, fail doing nothing. */ | |
750 | ||
751 | /* At this point watch_readback is known to be valid because we | |
752 | could not have added the watch without reading it. */ | |
753 | gdb_assert (watch_readback_valid == 1); | |
754 | ||
755 | watch_mirror = watch_readback; | |
b3436450 | 756 | mips_linux_watch_populate_regs (current_watches, &watch_mirror); |
b9412953 DD |
757 | |
758 | retval = write_watchpoint_regs (); | |
759 | ||
c5e92cca | 760 | if (show_debug_regs) |
b9412953 DD |
761 | mips_show_dr ("remove_watchpoint", addr, len, type); |
762 | ||
763 | return retval; | |
764 | } | |
765 | ||
766 | /* Target to_close implementation. Free any watches and call the | |
767 | super implementation. */ | |
768 | ||
f6ac5f3d PA |
769 | void |
770 | mips_linux_nat_target::close () | |
b9412953 DD |
771 | { |
772 | struct mips_watchpoint *w; | |
773 | struct mips_watchpoint *nw; | |
774 | ||
775 | /* Clean out the current_watches list. */ | |
776 | w = current_watches; | |
777 | while (w) | |
778 | { | |
779 | nw = w->next; | |
780 | xfree (w); | |
781 | w = nw; | |
782 | } | |
783 | current_watches = NULL; | |
784 | ||
f6ac5f3d | 785 | linux_nat_trad_target::close (); |
b9412953 DD |
786 | } |
787 | ||
10d6c8cd DJ |
788 | void |
789 | _initialize_mips_linux_nat (void) | |
790 | { | |
cbe54154 | 791 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
c5e92cca | 792 | &show_debug_regs, _("\ |
cbe54154 PA |
793 | Set whether to show variables that mirror the mips debug registers."), _("\ |
794 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
795 | Use \"on\" to enable, \"off\" to disable.\n\ |
796 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
797 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
798 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
799 | NULL, |
800 | NULL, | |
801 | &maintenance_set_cmdlist, | |
802 | &maintenance_show_cmdlist); | |
b9412953 | 803 | |
f6ac5f3d | 804 | linux_target = &the_mips_linux_nat_target; |
d9f719f1 | 805 | add_inf_child_target (&the_mips_linux_nat_target); |
10d6c8cd | 806 | } |