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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
61baf725 | 3 | Copyright (C) 2001-2017 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
d37eb719 | 23 | #include "inferior.h" |
6b753f60 | 24 | #include "mips-tdep.h" |
10d6c8cd | 25 | #include "target.h" |
28f5035f | 26 | #include "regcache.h" |
10d6c8cd | 27 | #include "linux-nat.h" |
d37eb719 | 28 | #include "mips-linux-tdep.h" |
822b6570 | 29 | #include "target-descriptions.h" |
2aa830e4 | 30 | |
dc60ece8 | 31 | #include "gdb_proc_service.h" |
3e00823e | 32 | #include "gregset.h" |
dc60ece8 | 33 | |
822b6570 | 34 | #include <sgidefs.h> |
5826e159 | 35 | #include "nat/gdb_ptrace.h" |
9be14b81 | 36 | #include <asm/ptrace.h> |
bcc0c096 | 37 | #include "inf-ptrace.h" |
d37eb719 | 38 | |
125f8a3d | 39 | #include "nat/mips-linux-watch.h" |
aaee2056 | 40 | |
81adfced | 41 | #include "features/mips-linux.c" |
1faeff08 | 42 | #include "features/mips-dsp-linux.c" |
81adfced | 43 | #include "features/mips64-linux.c" |
1faeff08 | 44 | #include "features/mips64-dsp-linux.c" |
81adfced | 45 | |
dc60ece8 DJ |
46 | #ifndef PTRACE_GET_THREAD_AREA |
47 | #define PTRACE_GET_THREAD_AREA 25 | |
48 | #endif | |
49 | ||
d37eb719 DJ |
50 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
51 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
52 | static int have_ptrace_regsets = 1; | |
53 | ||
54 | /* Saved function pointers to fetch and store a single register using | |
55 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ | |
56 | ||
b9412953 DD |
57 | static void (*super_fetch_registers) (struct target_ops *, |
58 | struct regcache *, int); | |
59 | static void (*super_store_registers) (struct target_ops *, | |
60 | struct regcache *, int); | |
61 | ||
93063aa6 | 62 | static void (*super_close) (struct target_ops *); |
d37eb719 | 63 | |
dda0c97e | 64 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
65 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
66 | ||
67 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
68 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
69 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
70 | |
71 | static CORE_ADDR | |
7714d83a | 72 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 73 | { |
7714d83a | 74 | CORE_ADDR regaddr; |
dda0c97e | 75 | |
2eb4d78b | 76 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
77 | error (_("Bogon register number %d."), regno); |
78 | ||
7714d83a | 79 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 80 | regaddr = regno; |
7714d83a UW |
81 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
82 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
83 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
84 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 85 | regaddr = PC; |
7714d83a UW |
86 | else if (regno == mips_regnum (gdbarch)->cause) |
87 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
88 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
89 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
90 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 91 | regaddr = MMLO; |
7714d83a | 92 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 93 | regaddr = MMHI; |
7714d83a | 94 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 95 | regaddr = FPC_CSR; |
7714d83a UW |
96 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
97 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
98 | else if (mips_regnum (gdbarch)->dspacc != -1 |
99 | && regno >= mips_regnum (gdbarch)->dspacc | |
100 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
101 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
102 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
103 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
104 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
105 | regaddr = 0; | |
dda0c97e | 106 | else |
7714d83a | 107 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
108 | |
109 | return regaddr; | |
110 | } | |
111 | ||
112 | static CORE_ADDR | |
7714d83a | 113 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 114 | { |
7714d83a | 115 | CORE_ADDR regaddr; |
dda0c97e | 116 | |
2eb4d78b | 117 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
118 | error (_("Bogon register number %d."), regno); |
119 | ||
7714d83a | 120 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 121 | regaddr = regno; |
7714d83a UW |
122 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
123 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 124 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 125 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 126 | regaddr = MIPS64_PC; |
7714d83a UW |
127 | else if (regno == mips_regnum (gdbarch)->cause) |
128 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
129 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
130 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
131 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 132 | regaddr = MIPS64_MMLO; |
7714d83a | 133 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 134 | regaddr = MIPS64_MMHI; |
7714d83a | 135 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 136 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
137 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
138 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
139 | else if (mips_regnum (gdbarch)->dspacc != -1 |
140 | && regno >= mips_regnum (gdbarch)->dspacc | |
141 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
142 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
143 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
144 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
145 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
146 | regaddr = 0; | |
dda0c97e | 147 | else |
7714d83a | 148 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
149 | |
150 | return regaddr; | |
151 | } | |
152 | ||
dc60ece8 DJ |
153 | /* Fetch the thread-local storage pointer for libthread_db. */ |
154 | ||
155 | ps_err_e | |
754653a7 | 156 | ps_get_thread_area (struct ps_prochandle *ph, |
dc60ece8 DJ |
157 | lwpid_t lwpid, int idx, void **base) |
158 | { | |
159 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
160 | return PS_ERR; | |
161 | ||
162 | /* IDX is the bias from the thread pointer to the beginning of the | |
163 | thread descriptor. It has to be subtracted due to implementation | |
164 | quirks in libthread_db. */ | |
165 | *base = (void *) ((char *)*base - idx); | |
166 | ||
167 | return PS_OK; | |
168 | } | |
169 | ||
3e00823e UW |
170 | /* Wrapper functions. These are only used by libthread_db. */ |
171 | ||
172 | void | |
7f7fe91e | 173 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 174 | { |
2eb4d78b | 175 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 176 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 177 | else |
7f7fe91e | 178 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
179 | } |
180 | ||
181 | void | |
7f7fe91e UW |
182 | fill_gregset (const struct regcache *regcache, |
183 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 184 | { |
2eb4d78b | 185 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 186 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 187 | else |
7f7fe91e | 188 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
189 | } |
190 | ||
191 | void | |
7f7fe91e | 192 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 193 | { |
2eb4d78b | 194 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 195 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 196 | else |
025bb325 MS |
197 | mips64_supply_fpregset (regcache, |
198 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
199 | } |
200 | ||
201 | void | |
7f7fe91e UW |
202 | fill_fpregset (const struct regcache *regcache, |
203 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 204 | { |
2eb4d78b | 205 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 206 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 207 | else |
025bb325 MS |
208 | mips64_fill_fpregset (regcache, |
209 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
210 | } |
211 | ||
212 | ||
d37eb719 DJ |
213 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
214 | using PTRACE_GETREGS et al. */ | |
215 | ||
216 | static void | |
1faeff08 MR |
217 | mips64_linux_regsets_fetch_registers (struct target_ops *ops, |
218 | struct regcache *regcache, int regno) | |
d37eb719 | 219 | { |
2eb4d78b | 220 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
221 | int is_fp, is_dsp; |
222 | int have_dsp; | |
223 | int regi; | |
d37eb719 DJ |
224 | int tid; |
225 | ||
2eb4d78b UW |
226 | if (regno >= mips_regnum (gdbarch)->fp0 |
227 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 228 | is_fp = 1; |
2eb4d78b | 229 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 230 | is_fp = 1; |
2eb4d78b | 231 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
232 | is_fp = 1; |
233 | else | |
234 | is_fp = 0; | |
235 | ||
1faeff08 MR |
236 | /* DSP registers are optional and not a part of any set. */ |
237 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
238 | if (!have_dsp) | |
239 | is_dsp = 0; | |
240 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
241 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
242 | is_dsp = 1; | |
243 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
244 | is_dsp = 1; | |
245 | else | |
246 | is_dsp = 0; | |
247 | ||
bcc0c096 | 248 | tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
d37eb719 | 249 | |
1faeff08 | 250 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
251 | { |
252 | mips64_elf_gregset_t regs; | |
253 | ||
254 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
255 | { | |
256 | if (errno == EIO) | |
257 | { | |
258 | have_ptrace_regsets = 0; | |
259 | return; | |
260 | } | |
261 | perror_with_name (_("Couldn't get registers")); | |
262 | } | |
263 | ||
56be3814 | 264 | mips64_supply_gregset (regcache, |
28f5035f | 265 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
266 | } |
267 | ||
268 | if (regno == -1 || is_fp) | |
269 | { | |
270 | mips64_elf_fpregset_t fp_regs; | |
271 | ||
272 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
273 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
274 | { | |
275 | if (errno == EIO) | |
276 | { | |
277 | have_ptrace_regsets = 0; | |
278 | return; | |
279 | } | |
280 | perror_with_name (_("Couldn't get FP registers")); | |
281 | } | |
282 | ||
56be3814 | 283 | mips64_supply_fpregset (regcache, |
28f5035f | 284 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 285 | } |
1faeff08 MR |
286 | |
287 | if (is_dsp) | |
288 | super_fetch_registers (ops, regcache, regno); | |
289 | else if (regno == -1 && have_dsp) | |
290 | { | |
291 | for (regi = mips_regnum (gdbarch)->dspacc; | |
292 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
293 | regi++) | |
294 | super_fetch_registers (ops, regcache, regi); | |
295 | super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
296 | } | |
d37eb719 DJ |
297 | } |
298 | ||
299 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
300 | using PTRACE_SETREGS et al. */ | |
301 | ||
302 | static void | |
1faeff08 MR |
303 | mips64_linux_regsets_store_registers (struct target_ops *ops, |
304 | struct regcache *regcache, int regno) | |
d37eb719 | 305 | { |
2eb4d78b | 306 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
307 | int is_fp, is_dsp; |
308 | int have_dsp; | |
309 | int regi; | |
d37eb719 DJ |
310 | int tid; |
311 | ||
2eb4d78b UW |
312 | if (regno >= mips_regnum (gdbarch)->fp0 |
313 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 314 | is_fp = 1; |
2eb4d78b | 315 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 316 | is_fp = 1; |
2eb4d78b | 317 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
318 | is_fp = 1; |
319 | else | |
320 | is_fp = 0; | |
321 | ||
1faeff08 MR |
322 | /* DSP registers are optional and not a part of any set. */ |
323 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
324 | if (!have_dsp) | |
325 | is_dsp = 0; | |
6ce4c112 | 326 | else if (regno >= mips_regnum (gdbarch)->dspacc |
1faeff08 MR |
327 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
328 | is_dsp = 1; | |
329 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
330 | is_dsp = 1; | |
331 | else | |
332 | is_dsp = 0; | |
333 | ||
bcc0c096 | 334 | tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
d37eb719 | 335 | |
1faeff08 | 336 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
337 | { |
338 | mips64_elf_gregset_t regs; | |
339 | ||
340 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
341 | perror_with_name (_("Couldn't get registers")); | |
342 | ||
56be3814 | 343 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
344 | |
345 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
346 | perror_with_name (_("Couldn't set registers")); | |
347 | } | |
348 | ||
349 | if (regno == -1 || is_fp) | |
350 | { | |
351 | mips64_elf_fpregset_t fp_regs; | |
352 | ||
353 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
354 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
355 | perror_with_name (_("Couldn't get FP registers")); | |
356 | ||
56be3814 | 357 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
358 | |
359 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
360 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
361 | perror_with_name (_("Couldn't set FP registers")); | |
362 | } | |
1faeff08 MR |
363 | |
364 | if (is_dsp) | |
365 | super_store_registers (ops, regcache, regno); | |
366 | else if (regno == -1 && have_dsp) | |
367 | { | |
368 | for (regi = mips_regnum (gdbarch)->dspacc; | |
369 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
370 | regi++) | |
371 | super_store_registers (ops, regcache, regi); | |
372 | super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
373 | } | |
d37eb719 DJ |
374 | } |
375 | ||
376 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
377 | using any working method. */ | |
378 | ||
379 | static void | |
28439f5e PA |
380 | mips64_linux_fetch_registers (struct target_ops *ops, |
381 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
382 | { |
383 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
384 | if (have_ptrace_regsets) | |
1faeff08 | 385 | mips64_linux_regsets_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
386 | |
387 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
388 | back to PTRACE_PEEKUSER. */ | |
389 | if (!have_ptrace_regsets) | |
a0740d21 | 390 | super_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
391 | } |
392 | ||
393 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
394 | using any working method. */ | |
395 | ||
396 | static void | |
28439f5e PA |
397 | mips64_linux_store_registers (struct target_ops *ops, |
398 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
399 | { |
400 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
401 | if (have_ptrace_regsets) | |
1faeff08 | 402 | mips64_linux_regsets_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
403 | |
404 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
405 | back to PTRACE_PEEKUSER. */ | |
406 | if (!have_ptrace_regsets) | |
a0740d21 | 407 | super_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
408 | } |
409 | ||
910122bf UW |
410 | /* Return the address in the core dump or inferior of register |
411 | REGNO. */ | |
412 | ||
413 | static CORE_ADDR | |
7714d83a | 414 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
910122bf | 415 | { |
7714d83a UW |
416 | if (mips_abi_regsize (gdbarch) == 8) |
417 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 418 | else |
7714d83a | 419 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
420 | } |
421 | ||
81adfced DJ |
422 | static const struct target_desc * |
423 | mips_linux_read_description (struct target_ops *ops) | |
822b6570 | 424 | { |
1faeff08 MR |
425 | static int have_dsp = -1; |
426 | ||
427 | if (have_dsp < 0) | |
428 | { | |
429 | int tid; | |
430 | ||
431 | tid = ptid_get_lwp (inferior_ptid); | |
432 | if (tid == 0) | |
433 | tid = ptid_get_pid (inferior_ptid); | |
434 | ||
ac740bc7 | 435 | errno = 0; |
1faeff08 MR |
436 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); |
437 | switch (errno) | |
438 | { | |
439 | case 0: | |
440 | have_dsp = 1; | |
441 | break; | |
442 | case EIO: | |
443 | have_dsp = 0; | |
444 | break; | |
445 | default: | |
837a1b32 | 446 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
447 | break; |
448 | } | |
449 | } | |
450 | ||
81adfced DJ |
451 | /* Report that target registers are a size we know for sure |
452 | that we can get from ptrace. */ | |
453 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 454 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 455 | else |
1faeff08 | 456 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
457 | } |
458 | ||
b9412953 DD |
459 | /* -1 if the kernel and/or CPU do not support watch registers. |
460 | 1 if watch_readback is valid and we can read style, num_valid | |
461 | and the masks. | |
462 | 0 if we need to read the watch_readback. */ | |
463 | ||
464 | static int watch_readback_valid; | |
465 | ||
466 | /* Cached watch register read values. */ | |
467 | ||
468 | static struct pt_watch_regs watch_readback; | |
469 | ||
b9412953 DD |
470 | static struct mips_watchpoint *current_watches; |
471 | ||
472 | /* The current set of watch register values for writing the | |
473 | registers. */ | |
474 | ||
475 | static struct pt_watch_regs watch_mirror; | |
476 | ||
b9412953 DD |
477 | static void |
478 | mips_show_dr (const char *func, CORE_ADDR addr, | |
479 | int len, enum target_hw_bp_type type) | |
480 | { | |
481 | int i; | |
482 | ||
483 | puts_unfiltered (func); | |
484 | if (addr || len) | |
5af949e3 | 485 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
f5656ead | 486 | paddress (target_gdbarch (), addr), len, |
b9412953 DD |
487 | type == hw_write ? "data-write" |
488 | : (type == hw_read ? "data-read" | |
489 | : (type == hw_access ? "data-read/write" | |
490 | : (type == hw_execute ? "instruction-execute" | |
491 | : "??unknown??")))); | |
492 | puts_unfiltered (":\n"); | |
493 | ||
494 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 | 495 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
f5656ead | 496 | paddress (target_gdbarch (), |
b3436450 YQ |
497 | mips_linux_watch_get_watchlo (&watch_mirror, |
498 | i)), | |
f5656ead | 499 | paddress (target_gdbarch (), |
b3436450 YQ |
500 | mips_linux_watch_get_watchhi (&watch_mirror, |
501 | i))); | |
b9412953 DD |
502 | } |
503 | ||
b9412953 DD |
504 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can |
505 | handle the specified watch type. */ | |
506 | ||
507 | static int | |
5461485a | 508 | mips_linux_can_use_hw_breakpoint (struct target_ops *self, |
f486487f SM |
509 | enum bptype type, |
510 | int cnt, int ot) | |
b9412953 DD |
511 | { |
512 | int i; | |
513 | uint32_t wanted_mask, irw_mask; | |
514 | ||
b3436450 YQ |
515 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
516 | &watch_readback, | |
517 | &watch_readback_valid, 0)) | |
b9412953 DD |
518 | return 0; |
519 | ||
520 | switch (type) | |
521 | { | |
522 | case bp_hardware_watchpoint: | |
523 | wanted_mask = W_MASK; | |
524 | break; | |
525 | case bp_read_watchpoint: | |
526 | wanted_mask = R_MASK; | |
527 | break; | |
528 | case bp_access_watchpoint: | |
529 | wanted_mask = R_MASK | W_MASK; | |
530 | break; | |
531 | default: | |
532 | return 0; | |
533 | } | |
534 | ||
b3436450 YQ |
535 | for (i = 0; |
536 | i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; | |
537 | i++) | |
b9412953 | 538 | { |
b3436450 | 539 | irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); |
b9412953 DD |
540 | if ((irw_mask & wanted_mask) == wanted_mask) |
541 | cnt--; | |
542 | } | |
543 | return (cnt == 0) ? 1 : 0; | |
544 | } | |
545 | ||
546 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
547 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 548 | register triggered. */ |
b9412953 DD |
549 | |
550 | static int | |
6a109b6b | 551 | mips_linux_stopped_by_watchpoint (struct target_ops *ops) |
b9412953 DD |
552 | { |
553 | int n; | |
554 | int num_valid; | |
555 | ||
b3436450 YQ |
556 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
557 | &watch_readback, | |
558 | &watch_readback_valid, 1)) | |
b9412953 DD |
559 | return 0; |
560 | ||
b3436450 | 561 | num_valid = mips_linux_watch_get_num_valid (&watch_readback); |
b9412953 DD |
562 | |
563 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
b3436450 | 564 | if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) |
b9412953 DD |
565 | return 1; |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /* Target to_stopped_data_address implementation. Set the address | |
571 | where the watch triggered (if known). Return 1 if the address was | |
572 | known. */ | |
573 | ||
574 | static int | |
575 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) | |
576 | { | |
577 | /* On mips we don't know the low order 3 bits of the data address, | |
578 | so we must return false. */ | |
579 | return 0; | |
580 | } | |
581 | ||
b9412953 DD |
582 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if |
583 | the specified region can be covered by the watch registers. */ | |
584 | ||
585 | static int | |
31568a15 TT |
586 | mips_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
587 | CORE_ADDR addr, int len) | |
b9412953 DD |
588 | { |
589 | struct pt_watch_regs dummy_regs; | |
590 | int i; | |
591 | ||
b3436450 YQ |
592 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
593 | &watch_readback, | |
594 | &watch_readback_valid, 0)) | |
b9412953 DD |
595 | return 0; |
596 | ||
597 | dummy_regs = watch_readback; | |
598 | /* Clear them out. */ | |
b3436450 YQ |
599 | for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) |
600 | mips_linux_watch_set_watchlo (&dummy_regs, i, 0); | |
601 | return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); | |
b9412953 DD |
602 | } |
603 | ||
b9412953 DD |
604 | /* Write the mirrored watch register values for each thread. */ |
605 | ||
606 | static int | |
607 | write_watchpoint_regs (void) | |
608 | { | |
609 | struct lwp_info *lp; | |
b9412953 DD |
610 | int tid; |
611 | ||
4c38200f | 612 | ALL_LWPS (lp) |
b9412953 | 613 | { |
4c38200f | 614 | tid = ptid_get_lwp (lp->ptid); |
aa58a496 | 615 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
616 | perror_with_name (_("Couldn't write debug register")); |
617 | } | |
618 | return 0; | |
619 | } | |
620 | ||
621 | /* linux_nat new_thread implementation. Write the mirrored watch | |
622 | register values for the new thread. */ | |
623 | ||
624 | static void | |
7b50312a | 625 | mips_linux_new_thread (struct lwp_info *lp) |
b9412953 DD |
626 | { |
627 | int tid; | |
628 | ||
b3436450 YQ |
629 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
630 | &watch_readback, | |
631 | &watch_readback_valid, 0)) | |
b9412953 DD |
632 | return; |
633 | ||
7b50312a | 634 | tid = ptid_get_lwp (lp->ptid); |
aa58a496 | 635 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
636 | perror_with_name (_("Couldn't write debug register")); |
637 | } | |
638 | ||
b9412953 DD |
639 | /* Target to_insert_watchpoint implementation. Try to insert a new |
640 | watch. Return zero on success. */ | |
641 | ||
642 | static int | |
7bb99c53 | 643 | mips_linux_insert_watchpoint (struct target_ops *self, |
f486487f SM |
644 | CORE_ADDR addr, int len, |
645 | enum target_hw_bp_type type, | |
0cf6dd15 | 646 | struct expression *cond) |
b9412953 DD |
647 | { |
648 | struct pt_watch_regs regs; | |
649 | struct mips_watchpoint *new_watch; | |
650 | struct mips_watchpoint **pw; | |
651 | ||
652 | int i; | |
653 | int retval; | |
654 | ||
b3436450 YQ |
655 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
656 | &watch_readback, | |
657 | &watch_readback_valid, 0)) | |
b9412953 DD |
658 | return -1; |
659 | ||
660 | if (len <= 0) | |
661 | return -1; | |
662 | ||
663 | regs = watch_readback; | |
664 | /* Add the current watches. */ | |
b3436450 | 665 | mips_linux_watch_populate_regs (current_watches, ®s); |
b9412953 DD |
666 | |
667 | /* Now try to add the new watch. */ | |
b3436450 YQ |
668 | if (!mips_linux_watch_try_one_watch (®s, addr, len, |
669 | mips_linux_watch_type_to_irw (type))) | |
b9412953 DD |
670 | return -1; |
671 | ||
672 | /* It fit. Stick it on the end of the list. */ | |
8d749320 | 673 | new_watch = XNEW (struct mips_watchpoint); |
b9412953 DD |
674 | new_watch->addr = addr; |
675 | new_watch->len = len; | |
676 | new_watch->type = type; | |
677 | new_watch->next = NULL; | |
678 | ||
679 | pw = ¤t_watches; | |
680 | while (*pw != NULL) | |
681 | pw = &(*pw)->next; | |
682 | *pw = new_watch; | |
683 | ||
684 | watch_mirror = regs; | |
685 | retval = write_watchpoint_regs (); | |
686 | ||
c5e92cca | 687 | if (show_debug_regs) |
b9412953 DD |
688 | mips_show_dr ("insert_watchpoint", addr, len, type); |
689 | ||
690 | return retval; | |
691 | } | |
692 | ||
693 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
694 | Return zero on success. */ | |
695 | ||
696 | static int | |
11b5219a | 697 | mips_linux_remove_watchpoint (struct target_ops *self, |
f486487f SM |
698 | CORE_ADDR addr, int len, |
699 | enum target_hw_bp_type type, | |
0cf6dd15 | 700 | struct expression *cond) |
b9412953 DD |
701 | { |
702 | int retval; | |
703 | int deleted_one; | |
704 | ||
705 | struct mips_watchpoint **pw; | |
706 | struct mips_watchpoint *w; | |
707 | ||
708 | /* Search for a known watch that matches. Then unlink and free | |
709 | it. */ | |
710 | deleted_one = 0; | |
711 | pw = ¤t_watches; | |
712 | while ((w = *pw)) | |
713 | { | |
714 | if (w->addr == addr && w->len == len && w->type == type) | |
715 | { | |
716 | *pw = w->next; | |
717 | xfree (w); | |
718 | deleted_one = 1; | |
719 | break; | |
720 | } | |
721 | pw = &(w->next); | |
722 | } | |
723 | ||
724 | if (!deleted_one) | |
725 | return -1; /* We don't know about it, fail doing nothing. */ | |
726 | ||
727 | /* At this point watch_readback is known to be valid because we | |
728 | could not have added the watch without reading it. */ | |
729 | gdb_assert (watch_readback_valid == 1); | |
730 | ||
731 | watch_mirror = watch_readback; | |
b3436450 | 732 | mips_linux_watch_populate_regs (current_watches, &watch_mirror); |
b9412953 DD |
733 | |
734 | retval = write_watchpoint_regs (); | |
735 | ||
c5e92cca | 736 | if (show_debug_regs) |
b9412953 DD |
737 | mips_show_dr ("remove_watchpoint", addr, len, type); |
738 | ||
739 | return retval; | |
740 | } | |
741 | ||
742 | /* Target to_close implementation. Free any watches and call the | |
743 | super implementation. */ | |
744 | ||
745 | static void | |
de90e03d | 746 | mips_linux_close (struct target_ops *self) |
b9412953 DD |
747 | { |
748 | struct mips_watchpoint *w; | |
749 | struct mips_watchpoint *nw; | |
750 | ||
751 | /* Clean out the current_watches list. */ | |
752 | w = current_watches; | |
753 | while (w) | |
754 | { | |
755 | nw = w->next; | |
756 | xfree (w); | |
757 | w = nw; | |
758 | } | |
759 | current_watches = NULL; | |
760 | ||
761 | if (super_close) | |
93063aa6 | 762 | super_close (self); |
b9412953 DD |
763 | } |
764 | ||
10d6c8cd DJ |
765 | void _initialize_mips_linux_nat (void); |
766 | ||
767 | void | |
768 | _initialize_mips_linux_nat (void) | |
769 | { | |
b9412953 DD |
770 | struct target_ops *t; |
771 | ||
cbe54154 | 772 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
c5e92cca | 773 | &show_debug_regs, _("\ |
cbe54154 PA |
774 | Set whether to show variables that mirror the mips debug registers."), _("\ |
775 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
776 | Use \"on\" to enable, \"off\" to disable.\n\ |
777 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
778 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
779 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
780 | NULL, |
781 | NULL, | |
782 | &maintenance_set_cmdlist, | |
783 | &maintenance_show_cmdlist); | |
b9412953 DD |
784 | |
785 | t = linux_trad_target (mips_linux_register_u_offset); | |
786 | ||
787 | super_close = t->to_close; | |
788 | t->to_close = mips_linux_close; | |
d37eb719 DJ |
789 | |
790 | super_fetch_registers = t->to_fetch_registers; | |
791 | super_store_registers = t->to_store_registers; | |
792 | ||
793 | t->to_fetch_registers = mips64_linux_fetch_registers; | |
794 | t->to_store_registers = mips64_linux_store_registers; | |
795 | ||
b9412953 DD |
796 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
797 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; | |
798 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; | |
799 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; | |
800 | t->to_stopped_data_address = mips_linux_stopped_data_address; | |
801 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; | |
802 | ||
81adfced | 803 | t->to_read_description = mips_linux_read_description; |
822b6570 | 804 | |
f973ed9c | 805 | linux_nat_add_target (t); |
b9412953 | 806 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
81adfced DJ |
807 | |
808 | /* Initialize the standard target descriptions. */ | |
809 | initialize_tdesc_mips_linux (); | |
1faeff08 | 810 | initialize_tdesc_mips_dsp_linux (); |
81adfced | 811 | initialize_tdesc_mips64_linux (); |
1faeff08 | 812 | initialize_tdesc_mips64_dsp_linux (); |
10d6c8cd | 813 | } |