Remove obsolete core-regset.c
[deliverable/binutils-gdb.git] / gdb / mips-linux-nat.c
CommitLineData
75c9abc6 1/* Native-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
61baf725 3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
2aa830e4
DJ
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ
19
20#include "defs.h"
b9412953
DD
21#include "command.h"
22#include "gdbcmd.h"
d37eb719 23#include "inferior.h"
6b753f60 24#include "mips-tdep.h"
10d6c8cd 25#include "target.h"
28f5035f 26#include "regcache.h"
10d6c8cd 27#include "linux-nat.h"
d37eb719 28#include "mips-linux-tdep.h"
822b6570 29#include "target-descriptions.h"
2aa830e4 30
dc60ece8 31#include "gdb_proc_service.h"
3e00823e 32#include "gregset.h"
dc60ece8 33
822b6570 34#include <sgidefs.h>
5826e159 35#include "nat/gdb_ptrace.h"
9be14b81 36#include <asm/ptrace.h>
bcc0c096 37#include "inf-ptrace.h"
d37eb719 38
125f8a3d 39#include "nat/mips-linux-watch.h"
aaee2056 40
dc60ece8
DJ
41#ifndef PTRACE_GET_THREAD_AREA
42#define PTRACE_GET_THREAD_AREA 25
43#endif
44
d37eb719
DJ
45/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
46 we'll clear this and use PTRACE_PEEKUSER instead. */
47static int have_ptrace_regsets = 1;
48
49/* Saved function pointers to fetch and store a single register using
50 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
51
b9412953
DD
52static void (*super_fetch_registers) (struct target_ops *,
53 struct regcache *, int);
54static void (*super_store_registers) (struct target_ops *,
55 struct regcache *, int);
56
93063aa6 57static void (*super_close) (struct target_ops *);
d37eb719 58
dda0c97e 59/* Map gdb internal register number to ptrace ``address''.
7714d83a
UW
60 These ``addresses'' are normally defined in <asm/ptrace.h>.
61
62 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
63 and there's no point in reading or setting MIPS_ZERO_REGNUM.
64 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
dda0c97e
UW
65
66static CORE_ADDR
7714d83a 67mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
dda0c97e 68{
7714d83a 69 CORE_ADDR regaddr;
dda0c97e 70
2eb4d78b 71 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
dda0c97e
UW
72 error (_("Bogon register number %d."), regno);
73
7714d83a 74 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
dda0c97e 75 regaddr = regno;
7714d83a
UW
76 else if ((regno >= mips_regnum (gdbarch)->fp0)
77 && (regno < mips_regnum (gdbarch)->fp0 + 32))
78 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
79 else if (regno == mips_regnum (gdbarch)->pc)
dda0c97e 80 regaddr = PC;
7714d83a
UW
81 else if (regno == mips_regnum (gdbarch)->cause)
82 regaddr = store? (CORE_ADDR) -1 : CAUSE;
83 else if (regno == mips_regnum (gdbarch)->badvaddr)
84 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
85 else if (regno == mips_regnum (gdbarch)->lo)
dda0c97e 86 regaddr = MMLO;
7714d83a 87 else if (regno == mips_regnum (gdbarch)->hi)
dda0c97e 88 regaddr = MMHI;
7714d83a 89 else if (regno == mips_regnum (gdbarch)->fp_control_status)
dda0c97e 90 regaddr = FPC_CSR;
7714d83a
UW
91 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
92 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
1faeff08
MR
93 else if (mips_regnum (gdbarch)->dspacc != -1
94 && regno >= mips_regnum (gdbarch)->dspacc
95 && regno < mips_regnum (gdbarch)->dspacc + 6)
96 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
97 else if (regno == mips_regnum (gdbarch)->dspctl)
98 regaddr = DSP_CONTROL;
822b6570
DJ
99 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
100 regaddr = 0;
dda0c97e 101 else
7714d83a 102 regaddr = (CORE_ADDR) -1;
dda0c97e
UW
103
104 return regaddr;
105}
106
107static CORE_ADDR
7714d83a 108mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
dda0c97e 109{
7714d83a 110 CORE_ADDR regaddr;
dda0c97e 111
2eb4d78b 112 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
dda0c97e
UW
113 error (_("Bogon register number %d."), regno);
114
7714d83a 115 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
dda0c97e 116 regaddr = regno;
7714d83a
UW
117 else if ((regno >= mips_regnum (gdbarch)->fp0)
118 && (regno < mips_regnum (gdbarch)->fp0 + 32))
2eb4d78b 119 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
7714d83a 120 else if (regno == mips_regnum (gdbarch)->pc)
dda0c97e 121 regaddr = MIPS64_PC;
7714d83a
UW
122 else if (regno == mips_regnum (gdbarch)->cause)
123 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
124 else if (regno == mips_regnum (gdbarch)->badvaddr)
125 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
126 else if (regno == mips_regnum (gdbarch)->lo)
dda0c97e 127 regaddr = MIPS64_MMLO;
7714d83a 128 else if (regno == mips_regnum (gdbarch)->hi)
dda0c97e 129 regaddr = MIPS64_MMHI;
7714d83a 130 else if (regno == mips_regnum (gdbarch)->fp_control_status)
dda0c97e 131 regaddr = MIPS64_FPC_CSR;
7714d83a
UW
132 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
133 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
1faeff08
MR
134 else if (mips_regnum (gdbarch)->dspacc != -1
135 && regno >= mips_regnum (gdbarch)->dspacc
136 && regno < mips_regnum (gdbarch)->dspacc + 6)
137 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
138 else if (regno == mips_regnum (gdbarch)->dspctl)
139 regaddr = DSP_CONTROL;
822b6570
DJ
140 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
141 regaddr = 0;
dda0c97e 142 else
7714d83a 143 regaddr = (CORE_ADDR) -1;
dda0c97e
UW
144
145 return regaddr;
146}
147
dc60ece8
DJ
148/* Fetch the thread-local storage pointer for libthread_db. */
149
150ps_err_e
754653a7 151ps_get_thread_area (struct ps_prochandle *ph,
dc60ece8
DJ
152 lwpid_t lwpid, int idx, void **base)
153{
154 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
155 return PS_ERR;
156
157 /* IDX is the bias from the thread pointer to the beginning of the
158 thread descriptor. It has to be subtracted due to implementation
159 quirks in libthread_db. */
160 *base = (void *) ((char *)*base - idx);
161
162 return PS_OK;
163}
164
3e00823e
UW
165/* Wrapper functions. These are only used by libthread_db. */
166
167void
7f7fe91e 168supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
3e00823e 169{
ac7936df 170 if (mips_isa_regsize (regcache->arch ()) == 4)
7f7fe91e 171 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
3e00823e 172 else
7f7fe91e 173 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
3e00823e
UW
174}
175
176void
7f7fe91e
UW
177fill_gregset (const struct regcache *regcache,
178 gdb_gregset_t *gregsetp, int regno)
3e00823e 179{
ac7936df 180 if (mips_isa_regsize (regcache->arch ()) == 4)
7f7fe91e 181 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
3e00823e 182 else
7f7fe91e 183 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
3e00823e
UW
184}
185
186void
7f7fe91e 187supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
3e00823e 188{
ac7936df 189 if (mips_isa_regsize (regcache->arch ()) == 4)
7f7fe91e 190 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
3e00823e 191 else
025bb325
MS
192 mips64_supply_fpregset (regcache,
193 (const mips64_elf_fpregset_t *) fpregsetp);
3e00823e
UW
194}
195
196void
7f7fe91e
UW
197fill_fpregset (const struct regcache *regcache,
198 gdb_fpregset_t *fpregsetp, int regno)
3e00823e 199{
ac7936df 200 if (mips_isa_regsize (regcache->arch ()) == 4)
7f7fe91e 201 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
3e00823e 202 else
025bb325
MS
203 mips64_fill_fpregset (regcache,
204 (mips64_elf_fpregset_t *) fpregsetp, regno);
3e00823e
UW
205}
206
207
d37eb719
DJ
208/* Fetch REGNO (or all registers if REGNO == -1) from the target
209 using PTRACE_GETREGS et al. */
210
211static void
1faeff08
MR
212mips64_linux_regsets_fetch_registers (struct target_ops *ops,
213 struct regcache *regcache, int regno)
d37eb719 214{
ac7936df 215 struct gdbarch *gdbarch = regcache->arch ();
1faeff08
MR
216 int is_fp, is_dsp;
217 int have_dsp;
218 int regi;
d37eb719
DJ
219 int tid;
220
2eb4d78b
UW
221 if (regno >= mips_regnum (gdbarch)->fp0
222 && regno <= mips_regnum (gdbarch)->fp0 + 32)
d37eb719 223 is_fp = 1;
2eb4d78b 224 else if (regno == mips_regnum (gdbarch)->fp_control_status)
d37eb719 225 is_fp = 1;
2eb4d78b 226 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ
227 is_fp = 1;
228 else
229 is_fp = 0;
230
1faeff08
MR
231 /* DSP registers are optional and not a part of any set. */
232 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
233 if (!have_dsp)
234 is_dsp = 0;
235 else if (regno >= mips_regnum (gdbarch)->dspacc
236 && regno < mips_regnum (gdbarch)->dspacc + 6)
237 is_dsp = 1;
238 else if (regno == mips_regnum (gdbarch)->dspctl)
239 is_dsp = 1;
240 else
241 is_dsp = 0;
242
bcc0c096 243 tid = get_ptrace_pid (regcache_get_ptid (regcache));
d37eb719 244
1faeff08 245 if (regno == -1 || (!is_fp && !is_dsp))
d37eb719
DJ
246 {
247 mips64_elf_gregset_t regs;
248
249 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
250 {
251 if (errno == EIO)
252 {
253 have_ptrace_regsets = 0;
254 return;
255 }
256 perror_with_name (_("Couldn't get registers"));
257 }
258
56be3814 259 mips64_supply_gregset (regcache,
28f5035f 260 (const mips64_elf_gregset_t *) &regs);
d37eb719
DJ
261 }
262
263 if (regno == -1 || is_fp)
264 {
265 mips64_elf_fpregset_t fp_regs;
266
267 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
268 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
269 {
270 if (errno == EIO)
271 {
272 have_ptrace_regsets = 0;
273 return;
274 }
275 perror_with_name (_("Couldn't get FP registers"));
276 }
277
56be3814 278 mips64_supply_fpregset (regcache,
28f5035f 279 (const mips64_elf_fpregset_t *) &fp_regs);
d37eb719 280 }
1faeff08
MR
281
282 if (is_dsp)
283 super_fetch_registers (ops, regcache, regno);
284 else if (regno == -1 && have_dsp)
285 {
286 for (regi = mips_regnum (gdbarch)->dspacc;
287 regi < mips_regnum (gdbarch)->dspacc + 6;
288 regi++)
289 super_fetch_registers (ops, regcache, regi);
290 super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
291 }
d37eb719
DJ
292}
293
294/* Store REGNO (or all registers if REGNO == -1) to the target
295 using PTRACE_SETREGS et al. */
296
297static void
1faeff08
MR
298mips64_linux_regsets_store_registers (struct target_ops *ops,
299 struct regcache *regcache, int regno)
d37eb719 300{
ac7936df 301 struct gdbarch *gdbarch = regcache->arch ();
1faeff08
MR
302 int is_fp, is_dsp;
303 int have_dsp;
304 int regi;
d37eb719
DJ
305 int tid;
306
2eb4d78b
UW
307 if (regno >= mips_regnum (gdbarch)->fp0
308 && regno <= mips_regnum (gdbarch)->fp0 + 32)
d37eb719 309 is_fp = 1;
2eb4d78b 310 else if (regno == mips_regnum (gdbarch)->fp_control_status)
d37eb719 311 is_fp = 1;
2eb4d78b 312 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ
313 is_fp = 1;
314 else
315 is_fp = 0;
316
1faeff08
MR
317 /* DSP registers are optional and not a part of any set. */
318 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
319 if (!have_dsp)
320 is_dsp = 0;
6ce4c112 321 else if (regno >= mips_regnum (gdbarch)->dspacc
1faeff08
MR
322 && regno < mips_regnum (gdbarch)->dspacc + 6)
323 is_dsp = 1;
324 else if (regno == mips_regnum (gdbarch)->dspctl)
325 is_dsp = 1;
326 else
327 is_dsp = 0;
328
bcc0c096 329 tid = get_ptrace_pid (regcache_get_ptid (regcache));
d37eb719 330
1faeff08 331 if (regno == -1 || (!is_fp && !is_dsp))
d37eb719
DJ
332 {
333 mips64_elf_gregset_t regs;
334
335 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
336 perror_with_name (_("Couldn't get registers"));
337
56be3814 338 mips64_fill_gregset (regcache, &regs, regno);
d37eb719
DJ
339
340 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
341 perror_with_name (_("Couldn't set registers"));
342 }
343
344 if (regno == -1 || is_fp)
345 {
346 mips64_elf_fpregset_t fp_regs;
347
348 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
349 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
350 perror_with_name (_("Couldn't get FP registers"));
351
56be3814 352 mips64_fill_fpregset (regcache, &fp_regs, regno);
d37eb719
DJ
353
354 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
355 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
356 perror_with_name (_("Couldn't set FP registers"));
357 }
1faeff08
MR
358
359 if (is_dsp)
360 super_store_registers (ops, regcache, regno);
361 else if (regno == -1 && have_dsp)
362 {
363 for (regi = mips_regnum (gdbarch)->dspacc;
364 regi < mips_regnum (gdbarch)->dspacc + 6;
365 regi++)
366 super_store_registers (ops, regcache, regi);
367 super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
368 }
d37eb719
DJ
369}
370
371/* Fetch REGNO (or all registers if REGNO == -1) from the target
372 using any working method. */
373
374static void
28439f5e
PA
375mips64_linux_fetch_registers (struct target_ops *ops,
376 struct regcache *regcache, int regnum)
d37eb719
DJ
377{
378 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
379 if (have_ptrace_regsets)
1faeff08 380 mips64_linux_regsets_fetch_registers (ops, regcache, regnum);
d37eb719
DJ
381
382 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
383 back to PTRACE_PEEKUSER. */
384 if (!have_ptrace_regsets)
a0740d21 385 super_fetch_registers (ops, regcache, regnum);
d37eb719
DJ
386}
387
388/* Store REGNO (or all registers if REGNO == -1) to the target
389 using any working method. */
390
391static void
28439f5e
PA
392mips64_linux_store_registers (struct target_ops *ops,
393 struct regcache *regcache, int regnum)
d37eb719
DJ
394{
395 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
396 if (have_ptrace_regsets)
1faeff08 397 mips64_linux_regsets_store_registers (ops, regcache, regnum);
d37eb719
DJ
398
399 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
400 back to PTRACE_PEEKUSER. */
401 if (!have_ptrace_regsets)
a0740d21 402 super_store_registers (ops, regcache, regnum);
d37eb719
DJ
403}
404
910122bf
UW
405/* Return the address in the core dump or inferior of register
406 REGNO. */
407
408static CORE_ADDR
7714d83a 409mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
910122bf 410{
7714d83a
UW
411 if (mips_abi_regsize (gdbarch) == 8)
412 return mips64_linux_register_addr (gdbarch, regno, store_p);
dda0c97e 413 else
7714d83a 414 return mips_linux_register_addr (gdbarch, regno, store_p);
910122bf
UW
415}
416
81adfced
DJ
417static const struct target_desc *
418mips_linux_read_description (struct target_ops *ops)
822b6570 419{
1faeff08
MR
420 static int have_dsp = -1;
421
422 if (have_dsp < 0)
423 {
424 int tid;
425
426 tid = ptid_get_lwp (inferior_ptid);
427 if (tid == 0)
428 tid = ptid_get_pid (inferior_ptid);
429
ac740bc7 430 errno = 0;
1faeff08
MR
431 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
432 switch (errno)
433 {
434 case 0:
435 have_dsp = 1;
436 break;
437 case EIO:
438 have_dsp = 0;
439 break;
440 default:
837a1b32 441 perror_with_name (_("Couldn't check DSP support"));
1faeff08
MR
442 break;
443 }
444 }
445
81adfced
DJ
446 /* Report that target registers are a size we know for sure
447 that we can get from ptrace. */
448 if (_MIPS_SIM == _ABIO32)
1faeff08 449 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
81adfced 450 else
1faeff08 451 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
822b6570
DJ
452}
453
b9412953
DD
454/* -1 if the kernel and/or CPU do not support watch registers.
455 1 if watch_readback is valid and we can read style, num_valid
456 and the masks.
457 0 if we need to read the watch_readback. */
458
459static int watch_readback_valid;
460
461/* Cached watch register read values. */
462
463static struct pt_watch_regs watch_readback;
464
b9412953
DD
465static struct mips_watchpoint *current_watches;
466
467/* The current set of watch register values for writing the
468 registers. */
469
470static struct pt_watch_regs watch_mirror;
471
b9412953
DD
472static void
473mips_show_dr (const char *func, CORE_ADDR addr,
474 int len, enum target_hw_bp_type type)
475{
476 int i;
477
478 puts_unfiltered (func);
479 if (addr || len)
5af949e3 480 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
f5656ead 481 paddress (target_gdbarch (), addr), len,
b9412953
DD
482 type == hw_write ? "data-write"
483 : (type == hw_read ? "data-read"
484 : (type == hw_access ? "data-read/write"
485 : (type == hw_execute ? "instruction-execute"
486 : "??unknown??"))));
487 puts_unfiltered (":\n");
488
489 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
5af949e3 490 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
f5656ead 491 paddress (target_gdbarch (),
b3436450
YQ
492 mips_linux_watch_get_watchlo (&watch_mirror,
493 i)),
f5656ead 494 paddress (target_gdbarch (),
b3436450
YQ
495 mips_linux_watch_get_watchhi (&watch_mirror,
496 i)));
b9412953
DD
497}
498
b9412953
DD
499/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
500 handle the specified watch type. */
501
502static int
5461485a 503mips_linux_can_use_hw_breakpoint (struct target_ops *self,
f486487f
SM
504 enum bptype type,
505 int cnt, int ot)
b9412953
DD
506{
507 int i;
508 uint32_t wanted_mask, irw_mask;
509
b3436450
YQ
510 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
511 &watch_readback,
512 &watch_readback_valid, 0))
b9412953
DD
513 return 0;
514
515 switch (type)
516 {
517 case bp_hardware_watchpoint:
518 wanted_mask = W_MASK;
519 break;
520 case bp_read_watchpoint:
521 wanted_mask = R_MASK;
522 break;
523 case bp_access_watchpoint:
524 wanted_mask = R_MASK | W_MASK;
525 break;
526 default:
527 return 0;
528 }
529
b3436450
YQ
530 for (i = 0;
531 i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
532 i++)
b9412953 533 {
b3436450 534 irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
b9412953
DD
535 if ((irw_mask & wanted_mask) == wanted_mask)
536 cnt--;
537 }
538 return (cnt == 0) ? 1 : 0;
539}
540
541/* Target to_stopped_by_watchpoint implementation. Return 1 if
542 stopped by watchpoint. The watchhi R and W bits indicate the watch
025bb325 543 register triggered. */
b9412953
DD
544
545static int
6a109b6b 546mips_linux_stopped_by_watchpoint (struct target_ops *ops)
b9412953
DD
547{
548 int n;
549 int num_valid;
550
b3436450
YQ
551 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
552 &watch_readback,
553 &watch_readback_valid, 1))
b9412953
DD
554 return 0;
555
b3436450 556 num_valid = mips_linux_watch_get_num_valid (&watch_readback);
b9412953
DD
557
558 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
b3436450 559 if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
b9412953
DD
560 return 1;
561
562 return 0;
563}
564
565/* Target to_stopped_data_address implementation. Set the address
566 where the watch triggered (if known). Return 1 if the address was
567 known. */
568
569static int
570mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
571{
572 /* On mips we don't know the low order 3 bits of the data address,
573 so we must return false. */
574 return 0;
575}
576
b9412953
DD
577/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
578 the specified region can be covered by the watch registers. */
579
580static int
31568a15
TT
581mips_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
582 CORE_ADDR addr, int len)
b9412953
DD
583{
584 struct pt_watch_regs dummy_regs;
585 int i;
586
b3436450
YQ
587 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
588 &watch_readback,
589 &watch_readback_valid, 0))
b9412953
DD
590 return 0;
591
592 dummy_regs = watch_readback;
593 /* Clear them out. */
b3436450
YQ
594 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
595 mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
596 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
b9412953
DD
597}
598
b9412953
DD
599/* Write the mirrored watch register values for each thread. */
600
601static int
602write_watchpoint_regs (void)
603{
604 struct lwp_info *lp;
b9412953
DD
605 int tid;
606
4c38200f 607 ALL_LWPS (lp)
b9412953 608 {
4c38200f 609 tid = ptid_get_lwp (lp->ptid);
aa58a496 610 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
b9412953
DD
611 perror_with_name (_("Couldn't write debug register"));
612 }
613 return 0;
614}
615
616/* linux_nat new_thread implementation. Write the mirrored watch
617 register values for the new thread. */
618
619static void
7b50312a 620mips_linux_new_thread (struct lwp_info *lp)
b9412953 621{
339053c2 622 long tid = lp->ptid.lwp ();
b9412953 623
7974a605 624 if (!mips_linux_read_watch_registers (tid,
b3436450
YQ
625 &watch_readback,
626 &watch_readback_valid, 0))
b9412953
DD
627 return;
628
aa58a496 629 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
b9412953
DD
630 perror_with_name (_("Couldn't write debug register"));
631}
632
b9412953
DD
633/* Target to_insert_watchpoint implementation. Try to insert a new
634 watch. Return zero on success. */
635
636static int
7bb99c53 637mips_linux_insert_watchpoint (struct target_ops *self,
f486487f
SM
638 CORE_ADDR addr, int len,
639 enum target_hw_bp_type type,
0cf6dd15 640 struct expression *cond)
b9412953
DD
641{
642 struct pt_watch_regs regs;
643 struct mips_watchpoint *new_watch;
644 struct mips_watchpoint **pw;
645
646 int i;
647 int retval;
648
b3436450
YQ
649 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
650 &watch_readback,
651 &watch_readback_valid, 0))
b9412953
DD
652 return -1;
653
654 if (len <= 0)
655 return -1;
656
657 regs = watch_readback;
658 /* Add the current watches. */
b3436450 659 mips_linux_watch_populate_regs (current_watches, &regs);
b9412953
DD
660
661 /* Now try to add the new watch. */
b3436450
YQ
662 if (!mips_linux_watch_try_one_watch (&regs, addr, len,
663 mips_linux_watch_type_to_irw (type)))
b9412953
DD
664 return -1;
665
666 /* It fit. Stick it on the end of the list. */
8d749320 667 new_watch = XNEW (struct mips_watchpoint);
b9412953
DD
668 new_watch->addr = addr;
669 new_watch->len = len;
670 new_watch->type = type;
671 new_watch->next = NULL;
672
673 pw = &current_watches;
674 while (*pw != NULL)
675 pw = &(*pw)->next;
676 *pw = new_watch;
677
678 watch_mirror = regs;
679 retval = write_watchpoint_regs ();
680
c5e92cca 681 if (show_debug_regs)
b9412953
DD
682 mips_show_dr ("insert_watchpoint", addr, len, type);
683
684 return retval;
685}
686
687/* Target to_remove_watchpoint implementation. Try to remove a watch.
688 Return zero on success. */
689
690static int
11b5219a 691mips_linux_remove_watchpoint (struct target_ops *self,
f486487f
SM
692 CORE_ADDR addr, int len,
693 enum target_hw_bp_type type,
0cf6dd15 694 struct expression *cond)
b9412953
DD
695{
696 int retval;
697 int deleted_one;
698
699 struct mips_watchpoint **pw;
700 struct mips_watchpoint *w;
701
702 /* Search for a known watch that matches. Then unlink and free
703 it. */
704 deleted_one = 0;
705 pw = &current_watches;
706 while ((w = *pw))
707 {
708 if (w->addr == addr && w->len == len && w->type == type)
709 {
710 *pw = w->next;
711 xfree (w);
712 deleted_one = 1;
713 break;
714 }
715 pw = &(w->next);
716 }
717
718 if (!deleted_one)
719 return -1; /* We don't know about it, fail doing nothing. */
720
721 /* At this point watch_readback is known to be valid because we
722 could not have added the watch without reading it. */
723 gdb_assert (watch_readback_valid == 1);
724
725 watch_mirror = watch_readback;
b3436450 726 mips_linux_watch_populate_regs (current_watches, &watch_mirror);
b9412953
DD
727
728 retval = write_watchpoint_regs ();
729
c5e92cca 730 if (show_debug_regs)
b9412953
DD
731 mips_show_dr ("remove_watchpoint", addr, len, type);
732
733 return retval;
734}
735
736/* Target to_close implementation. Free any watches and call the
737 super implementation. */
738
739static void
de90e03d 740mips_linux_close (struct target_ops *self)
b9412953
DD
741{
742 struct mips_watchpoint *w;
743 struct mips_watchpoint *nw;
744
745 /* Clean out the current_watches list. */
746 w = current_watches;
747 while (w)
748 {
749 nw = w->next;
750 xfree (w);
751 w = nw;
752 }
753 current_watches = NULL;
754
755 if (super_close)
93063aa6 756 super_close (self);
b9412953
DD
757}
758
10d6c8cd
DJ
759void
760_initialize_mips_linux_nat (void)
761{
b9412953
DD
762 struct target_ops *t;
763
cbe54154 764 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
c5e92cca 765 &show_debug_regs, _("\
cbe54154
PA
766Set whether to show variables that mirror the mips debug registers."), _("\
767Show whether to show variables that mirror the mips debug registers."), _("\
b9412953
DD
768Use \"on\" to enable, \"off\" to disable.\n\
769If enabled, the debug registers values are shown when GDB inserts\n\
770or removes a hardware breakpoint or watchpoint, and when the inferior\n\
771triggers a breakpoint or watchpoint."),
cbe54154
PA
772 NULL,
773 NULL,
774 &maintenance_set_cmdlist,
775 &maintenance_show_cmdlist);
b9412953
DD
776
777 t = linux_trad_target (mips_linux_register_u_offset);
778
779 super_close = t->to_close;
780 t->to_close = mips_linux_close;
d37eb719
DJ
781
782 super_fetch_registers = t->to_fetch_registers;
783 super_store_registers = t->to_store_registers;
784
785 t->to_fetch_registers = mips64_linux_fetch_registers;
786 t->to_store_registers = mips64_linux_store_registers;
787
b9412953
DD
788 t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint;
789 t->to_remove_watchpoint = mips_linux_remove_watchpoint;
790 t->to_insert_watchpoint = mips_linux_insert_watchpoint;
791 t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint;
792 t->to_stopped_data_address = mips_linux_stopped_data_address;
793 t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint;
794
81adfced 795 t->to_read_description = mips_linux_read_description;
822b6570 796
f973ed9c 797 linux_nat_add_target (t);
b9412953 798 linux_nat_set_new_thread (t, mips_linux_new_thread);
10d6c8cd 799}
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