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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
e2882c85 | 3 | Copyright (C) 2001-2018 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
d37eb719 | 23 | #include "inferior.h" |
6b753f60 | 24 | #include "mips-tdep.h" |
10d6c8cd | 25 | #include "target.h" |
28f5035f | 26 | #include "regcache.h" |
6798487f | 27 | #include "linux-nat-trad.h" |
d37eb719 | 28 | #include "mips-linux-tdep.h" |
822b6570 | 29 | #include "target-descriptions.h" |
2aa830e4 | 30 | |
dc60ece8 | 31 | #include "gdb_proc_service.h" |
3e00823e | 32 | #include "gregset.h" |
dc60ece8 | 33 | |
822b6570 | 34 | #include <sgidefs.h> |
5826e159 | 35 | #include "nat/gdb_ptrace.h" |
9be14b81 | 36 | #include <asm/ptrace.h> |
bcc0c096 | 37 | #include "inf-ptrace.h" |
d37eb719 | 38 | |
125f8a3d | 39 | #include "nat/mips-linux-watch.h" |
aaee2056 | 40 | |
dc60ece8 DJ |
41 | #ifndef PTRACE_GET_THREAD_AREA |
42 | #define PTRACE_GET_THREAD_AREA 25 | |
43 | #endif | |
44 | ||
f6ac5f3d PA |
45 | class mips_linux_nat_target final : public linux_nat_trad_target |
46 | { | |
47 | public: | |
48 | /* Add our register access methods. */ | |
49 | void fetch_registers (struct regcache *, int) override; | |
50 | void store_registers (struct regcache *, int) override; | |
51 | ||
52 | void close () override; | |
53 | ||
54 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
55 | ||
56 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
57 | struct expression *) override; | |
58 | ||
59 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
60 | struct expression *) override; | |
61 | ||
57810aa7 | 62 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 63 | |
57810aa7 | 64 | bool stopped_data_address (CORE_ADDR *) override; |
d37eb719 | 65 | |
f6ac5f3d | 66 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; |
d37eb719 | 67 | |
f6ac5f3d | 68 | const struct target_desc *read_description () override; |
b9412953 | 69 | |
f6ac5f3d PA |
70 | protected: |
71 | /* Override linux_nat_trad_target methods. */ | |
72 | CORE_ADDR register_u_offset (struct gdbarch *gdbarch, | |
73 | int regno, int store_p) override; | |
74 | ||
135340af PA |
75 | /* Override linux_nat_target low methods. */ |
76 | void low_new_thread (struct lwp_info *lp) override; | |
77 | ||
f6ac5f3d PA |
78 | private: |
79 | /* Helpers. See definitions. */ | |
80 | void mips64_regsets_store_registers (struct regcache *regcache, | |
81 | int regno); | |
82 | void mips64_regsets_fetch_registers (struct regcache *regcache, | |
83 | int regno); | |
84 | }; | |
85 | ||
86 | static mips_linux_nat_target the_mips_linux_nat_target; | |
87 | ||
88 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, | |
89 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
90 | static int have_ptrace_regsets = 1; | |
d37eb719 | 91 | |
dda0c97e | 92 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
93 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
94 | ||
95 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
96 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
97 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
98 | |
99 | static CORE_ADDR | |
7714d83a | 100 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 101 | { |
7714d83a | 102 | CORE_ADDR regaddr; |
dda0c97e | 103 | |
2eb4d78b | 104 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
105 | error (_("Bogon register number %d."), regno); |
106 | ||
7714d83a | 107 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 108 | regaddr = regno; |
7714d83a UW |
109 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
110 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
111 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
112 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 113 | regaddr = PC; |
7714d83a UW |
114 | else if (regno == mips_regnum (gdbarch)->cause) |
115 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
116 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
117 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
118 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 119 | regaddr = MMLO; |
7714d83a | 120 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 121 | regaddr = MMHI; |
7714d83a | 122 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 123 | regaddr = FPC_CSR; |
7714d83a UW |
124 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
125 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
126 | else if (mips_regnum (gdbarch)->dspacc != -1 |
127 | && regno >= mips_regnum (gdbarch)->dspacc | |
128 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
129 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
130 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
131 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
132 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
133 | regaddr = 0; | |
dda0c97e | 134 | else |
7714d83a | 135 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
136 | |
137 | return regaddr; | |
138 | } | |
139 | ||
140 | static CORE_ADDR | |
7714d83a | 141 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 142 | { |
7714d83a | 143 | CORE_ADDR regaddr; |
dda0c97e | 144 | |
2eb4d78b | 145 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
146 | error (_("Bogon register number %d."), regno); |
147 | ||
75d74cca MR |
148 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR |
149 | or PTRACE_POKEUSR. */ | |
150 | if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET)) | |
151 | return (CORE_ADDR) -1; | |
152 | ||
7714d83a | 153 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 154 | regaddr = regno; |
7714d83a UW |
155 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
156 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 157 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 158 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 159 | regaddr = MIPS64_PC; |
7714d83a UW |
160 | else if (regno == mips_regnum (gdbarch)->cause) |
161 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
162 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
163 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
164 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 165 | regaddr = MIPS64_MMLO; |
7714d83a | 166 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 167 | regaddr = MIPS64_MMHI; |
7714d83a | 168 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 169 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
170 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
171 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
172 | else if (mips_regnum (gdbarch)->dspacc != -1 |
173 | && regno >= mips_regnum (gdbarch)->dspacc | |
174 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
175 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
176 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
177 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
178 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
179 | regaddr = 0; | |
dda0c97e | 180 | else |
7714d83a | 181 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
182 | |
183 | return regaddr; | |
184 | } | |
185 | ||
dc60ece8 DJ |
186 | /* Fetch the thread-local storage pointer for libthread_db. */ |
187 | ||
188 | ps_err_e | |
754653a7 | 189 | ps_get_thread_area (struct ps_prochandle *ph, |
dc60ece8 DJ |
190 | lwpid_t lwpid, int idx, void **base) |
191 | { | |
192 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
193 | return PS_ERR; | |
194 | ||
195 | /* IDX is the bias from the thread pointer to the beginning of the | |
196 | thread descriptor. It has to be subtracted due to implementation | |
197 | quirks in libthread_db. */ | |
198 | *base = (void *) ((char *)*base - idx); | |
199 | ||
200 | return PS_OK; | |
201 | } | |
202 | ||
3e00823e UW |
203 | /* Wrapper functions. These are only used by libthread_db. */ |
204 | ||
205 | void | |
7f7fe91e | 206 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 207 | { |
ac7936df | 208 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 209 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 210 | else |
7f7fe91e | 211 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
212 | } |
213 | ||
214 | void | |
7f7fe91e UW |
215 | fill_gregset (const struct regcache *regcache, |
216 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 217 | { |
ac7936df | 218 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 219 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 220 | else |
7f7fe91e | 221 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
222 | } |
223 | ||
224 | void | |
7f7fe91e | 225 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 226 | { |
ac7936df | 227 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 228 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 229 | else |
025bb325 MS |
230 | mips64_supply_fpregset (regcache, |
231 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
232 | } |
233 | ||
234 | void | |
7f7fe91e UW |
235 | fill_fpregset (const struct regcache *regcache, |
236 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 237 | { |
ac7936df | 238 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 239 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 240 | else |
025bb325 MS |
241 | mips64_fill_fpregset (regcache, |
242 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
243 | } |
244 | ||
245 | ||
d37eb719 DJ |
246 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
247 | using PTRACE_GETREGS et al. */ | |
248 | ||
f6ac5f3d PA |
249 | void |
250 | mips_linux_nat_target::mips64_regsets_fetch_registers | |
251 | (struct regcache *regcache, int regno) | |
d37eb719 | 252 | { |
ac7936df | 253 | struct gdbarch *gdbarch = regcache->arch (); |
1faeff08 MR |
254 | int is_fp, is_dsp; |
255 | int have_dsp; | |
256 | int regi; | |
d37eb719 DJ |
257 | int tid; |
258 | ||
2eb4d78b UW |
259 | if (regno >= mips_regnum (gdbarch)->fp0 |
260 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 261 | is_fp = 1; |
2eb4d78b | 262 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 263 | is_fp = 1; |
2eb4d78b | 264 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
265 | is_fp = 1; |
266 | else | |
267 | is_fp = 0; | |
268 | ||
1faeff08 MR |
269 | /* DSP registers are optional and not a part of any set. */ |
270 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
271 | if (!have_dsp) | |
272 | is_dsp = 0; | |
273 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
274 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
275 | is_dsp = 1; | |
276 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
277 | is_dsp = 1; | |
278 | else | |
279 | is_dsp = 0; | |
280 | ||
bcc0c096 | 281 | tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
d37eb719 | 282 | |
1faeff08 | 283 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
284 | { |
285 | mips64_elf_gregset_t regs; | |
286 | ||
287 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
288 | { | |
289 | if (errno == EIO) | |
290 | { | |
291 | have_ptrace_regsets = 0; | |
292 | return; | |
293 | } | |
294 | perror_with_name (_("Couldn't get registers")); | |
295 | } | |
296 | ||
56be3814 | 297 | mips64_supply_gregset (regcache, |
28f5035f | 298 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
299 | } |
300 | ||
301 | if (regno == -1 || is_fp) | |
302 | { | |
303 | mips64_elf_fpregset_t fp_regs; | |
304 | ||
305 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
306 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
307 | { | |
308 | if (errno == EIO) | |
309 | { | |
310 | have_ptrace_regsets = 0; | |
311 | return; | |
312 | } | |
313 | perror_with_name (_("Couldn't get FP registers")); | |
314 | } | |
315 | ||
56be3814 | 316 | mips64_supply_fpregset (regcache, |
28f5035f | 317 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 318 | } |
1faeff08 MR |
319 | |
320 | if (is_dsp) | |
f6ac5f3d | 321 | linux_nat_trad_target::fetch_registers (regcache, regno); |
1faeff08 MR |
322 | else if (regno == -1 && have_dsp) |
323 | { | |
324 | for (regi = mips_regnum (gdbarch)->dspacc; | |
325 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
326 | regi++) | |
f6ac5f3d PA |
327 | linux_nat_trad_target::fetch_registers (regcache, regi); |
328 | linux_nat_trad_target::fetch_registers (regcache, | |
329 | mips_regnum (gdbarch)->dspctl); | |
1faeff08 | 330 | } |
d37eb719 DJ |
331 | } |
332 | ||
333 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
334 | using PTRACE_SETREGS et al. */ | |
335 | ||
f6ac5f3d PA |
336 | void |
337 | mips_linux_nat_target::mips64_regsets_store_registers | |
338 | (struct regcache *regcache, int regno) | |
d37eb719 | 339 | { |
ac7936df | 340 | struct gdbarch *gdbarch = regcache->arch (); |
1faeff08 MR |
341 | int is_fp, is_dsp; |
342 | int have_dsp; | |
343 | int regi; | |
d37eb719 DJ |
344 | int tid; |
345 | ||
2eb4d78b UW |
346 | if (regno >= mips_regnum (gdbarch)->fp0 |
347 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 348 | is_fp = 1; |
2eb4d78b | 349 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 350 | is_fp = 1; |
2eb4d78b | 351 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
352 | is_fp = 1; |
353 | else | |
354 | is_fp = 0; | |
355 | ||
1faeff08 MR |
356 | /* DSP registers are optional and not a part of any set. */ |
357 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
358 | if (!have_dsp) | |
359 | is_dsp = 0; | |
6ce4c112 | 360 | else if (regno >= mips_regnum (gdbarch)->dspacc |
1faeff08 MR |
361 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
362 | is_dsp = 1; | |
363 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
364 | is_dsp = 1; | |
365 | else | |
366 | is_dsp = 0; | |
367 | ||
bcc0c096 | 368 | tid = get_ptrace_pid (regcache_get_ptid (regcache)); |
d37eb719 | 369 | |
1faeff08 | 370 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
371 | { |
372 | mips64_elf_gregset_t regs; | |
373 | ||
374 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
375 | perror_with_name (_("Couldn't get registers")); | |
376 | ||
56be3814 | 377 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
378 | |
379 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
380 | perror_with_name (_("Couldn't set registers")); | |
381 | } | |
382 | ||
383 | if (regno == -1 || is_fp) | |
384 | { | |
385 | mips64_elf_fpregset_t fp_regs; | |
386 | ||
387 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
388 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
389 | perror_with_name (_("Couldn't get FP registers")); | |
390 | ||
56be3814 | 391 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
392 | |
393 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
394 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
395 | perror_with_name (_("Couldn't set FP registers")); | |
396 | } | |
1faeff08 MR |
397 | |
398 | if (is_dsp) | |
f6ac5f3d | 399 | linux_nat_trad_target::store_registers (regcache, regno); |
1faeff08 MR |
400 | else if (regno == -1 && have_dsp) |
401 | { | |
402 | for (regi = mips_regnum (gdbarch)->dspacc; | |
403 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
404 | regi++) | |
f6ac5f3d PA |
405 | linux_nat_trad_target::store_registers (regcache, regi); |
406 | linux_nat_trad_target::store_registers (regcache, | |
407 | mips_regnum (gdbarch)->dspctl); | |
1faeff08 | 408 | } |
d37eb719 DJ |
409 | } |
410 | ||
411 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
412 | using any working method. */ | |
413 | ||
f6ac5f3d PA |
414 | void |
415 | mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) | |
d37eb719 DJ |
416 | { |
417 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
418 | if (have_ptrace_regsets) | |
f6ac5f3d | 419 | mips64_regsets_fetch_registers (regcache, regnum); |
d37eb719 DJ |
420 | |
421 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
422 | back to PTRACE_PEEKUSER. */ | |
423 | if (!have_ptrace_regsets) | |
4e6ff0e1 MR |
424 | { |
425 | linux_nat_trad_target::fetch_registers (regcache, regnum); | |
426 | ||
427 | /* Fill the inaccessible zero register with zero. */ | |
428 | if (regnum == MIPS_ZERO_REGNUM || regnum == -1) | |
429 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); | |
430 | } | |
d37eb719 DJ |
431 | } |
432 | ||
433 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
434 | using any working method. */ | |
435 | ||
f6ac5f3d PA |
436 | void |
437 | mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum) | |
d37eb719 DJ |
438 | { |
439 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
440 | if (have_ptrace_regsets) | |
f6ac5f3d | 441 | mips64_regsets_store_registers (regcache, regnum); |
d37eb719 DJ |
442 | |
443 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
444 | back to PTRACE_PEEKUSER. */ | |
445 | if (!have_ptrace_regsets) | |
f6ac5f3d | 446 | linux_nat_trad_target::store_registers (regcache, regnum); |
d37eb719 DJ |
447 | } |
448 | ||
910122bf UW |
449 | /* Return the address in the core dump or inferior of register |
450 | REGNO. */ | |
451 | ||
f6ac5f3d PA |
452 | CORE_ADDR |
453 | mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch, | |
454 | int regno, int store_p) | |
910122bf | 455 | { |
7714d83a UW |
456 | if (mips_abi_regsize (gdbarch) == 8) |
457 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 458 | else |
7714d83a | 459 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
460 | } |
461 | ||
f6ac5f3d PA |
462 | const struct target_desc * |
463 | mips_linux_nat_target::read_description () | |
822b6570 | 464 | { |
1faeff08 MR |
465 | static int have_dsp = -1; |
466 | ||
467 | if (have_dsp < 0) | |
468 | { | |
469 | int tid; | |
470 | ||
471 | tid = ptid_get_lwp (inferior_ptid); | |
472 | if (tid == 0) | |
473 | tid = ptid_get_pid (inferior_ptid); | |
474 | ||
ac740bc7 | 475 | errno = 0; |
1faeff08 MR |
476 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); |
477 | switch (errno) | |
478 | { | |
479 | case 0: | |
480 | have_dsp = 1; | |
481 | break; | |
482 | case EIO: | |
483 | have_dsp = 0; | |
484 | break; | |
485 | default: | |
837a1b32 | 486 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
487 | break; |
488 | } | |
489 | } | |
490 | ||
81adfced DJ |
491 | /* Report that target registers are a size we know for sure |
492 | that we can get from ptrace. */ | |
493 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 494 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 495 | else |
1faeff08 | 496 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
497 | } |
498 | ||
b9412953 DD |
499 | /* -1 if the kernel and/or CPU do not support watch registers. |
500 | 1 if watch_readback is valid and we can read style, num_valid | |
501 | and the masks. | |
502 | 0 if we need to read the watch_readback. */ | |
503 | ||
504 | static int watch_readback_valid; | |
505 | ||
506 | /* Cached watch register read values. */ | |
507 | ||
508 | static struct pt_watch_regs watch_readback; | |
509 | ||
b9412953 DD |
510 | static struct mips_watchpoint *current_watches; |
511 | ||
512 | /* The current set of watch register values for writing the | |
513 | registers. */ | |
514 | ||
515 | static struct pt_watch_regs watch_mirror; | |
516 | ||
b9412953 DD |
517 | static void |
518 | mips_show_dr (const char *func, CORE_ADDR addr, | |
519 | int len, enum target_hw_bp_type type) | |
520 | { | |
521 | int i; | |
522 | ||
523 | puts_unfiltered (func); | |
524 | if (addr || len) | |
5af949e3 | 525 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
f5656ead | 526 | paddress (target_gdbarch (), addr), len, |
b9412953 DD |
527 | type == hw_write ? "data-write" |
528 | : (type == hw_read ? "data-read" | |
529 | : (type == hw_access ? "data-read/write" | |
530 | : (type == hw_execute ? "instruction-execute" | |
531 | : "??unknown??")))); | |
532 | puts_unfiltered (":\n"); | |
533 | ||
534 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 | 535 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
f5656ead | 536 | paddress (target_gdbarch (), |
b3436450 YQ |
537 | mips_linux_watch_get_watchlo (&watch_mirror, |
538 | i)), | |
f5656ead | 539 | paddress (target_gdbarch (), |
b3436450 YQ |
540 | mips_linux_watch_get_watchhi (&watch_mirror, |
541 | i))); | |
b9412953 DD |
542 | } |
543 | ||
b9412953 DD |
544 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can |
545 | handle the specified watch type. */ | |
546 | ||
f6ac5f3d PA |
547 | int |
548 | mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
549 | int cnt, int ot) | |
b9412953 DD |
550 | { |
551 | int i; | |
552 | uint32_t wanted_mask, irw_mask; | |
553 | ||
b3436450 YQ |
554 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
555 | &watch_readback, | |
556 | &watch_readback_valid, 0)) | |
b9412953 DD |
557 | return 0; |
558 | ||
559 | switch (type) | |
560 | { | |
561 | case bp_hardware_watchpoint: | |
562 | wanted_mask = W_MASK; | |
563 | break; | |
564 | case bp_read_watchpoint: | |
565 | wanted_mask = R_MASK; | |
566 | break; | |
567 | case bp_access_watchpoint: | |
568 | wanted_mask = R_MASK | W_MASK; | |
569 | break; | |
570 | default: | |
571 | return 0; | |
572 | } | |
573 | ||
b3436450 YQ |
574 | for (i = 0; |
575 | i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; | |
576 | i++) | |
b9412953 | 577 | { |
b3436450 | 578 | irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); |
b9412953 DD |
579 | if ((irw_mask & wanted_mask) == wanted_mask) |
580 | cnt--; | |
581 | } | |
582 | return (cnt == 0) ? 1 : 0; | |
583 | } | |
584 | ||
585 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
586 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 587 | register triggered. */ |
b9412953 | 588 | |
57810aa7 | 589 | bool |
f6ac5f3d | 590 | mips_linux_nat_target::stopped_by_watchpoint () |
b9412953 DD |
591 | { |
592 | int n; | |
593 | int num_valid; | |
594 | ||
b3436450 YQ |
595 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
596 | &watch_readback, | |
597 | &watch_readback_valid, 1)) | |
57810aa7 | 598 | return false; |
b9412953 | 599 | |
b3436450 | 600 | num_valid = mips_linux_watch_get_num_valid (&watch_readback); |
b9412953 DD |
601 | |
602 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
b3436450 | 603 | if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) |
57810aa7 | 604 | return true; |
b9412953 | 605 | |
57810aa7 | 606 | return false; |
b9412953 DD |
607 | } |
608 | ||
609 | /* Target to_stopped_data_address implementation. Set the address | |
610 | where the watch triggered (if known). Return 1 if the address was | |
611 | known. */ | |
612 | ||
57810aa7 | 613 | bool |
f6ac5f3d | 614 | mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr) |
b9412953 DD |
615 | { |
616 | /* On mips we don't know the low order 3 bits of the data address, | |
617 | so we must return false. */ | |
57810aa7 | 618 | return false; |
b9412953 DD |
619 | } |
620 | ||
b9412953 DD |
621 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if |
622 | the specified region can be covered by the watch registers. */ | |
623 | ||
f6ac5f3d PA |
624 | int |
625 | mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
b9412953 DD |
626 | { |
627 | struct pt_watch_regs dummy_regs; | |
628 | int i; | |
629 | ||
b3436450 YQ |
630 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
631 | &watch_readback, | |
632 | &watch_readback_valid, 0)) | |
b9412953 DD |
633 | return 0; |
634 | ||
635 | dummy_regs = watch_readback; | |
636 | /* Clear them out. */ | |
b3436450 YQ |
637 | for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) |
638 | mips_linux_watch_set_watchlo (&dummy_regs, i, 0); | |
639 | return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); | |
b9412953 DD |
640 | } |
641 | ||
b9412953 DD |
642 | /* Write the mirrored watch register values for each thread. */ |
643 | ||
644 | static int | |
645 | write_watchpoint_regs (void) | |
646 | { | |
647 | struct lwp_info *lp; | |
b9412953 DD |
648 | int tid; |
649 | ||
4c38200f | 650 | ALL_LWPS (lp) |
b9412953 | 651 | { |
4c38200f | 652 | tid = ptid_get_lwp (lp->ptid); |
aa58a496 | 653 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
654 | perror_with_name (_("Couldn't write debug register")); |
655 | } | |
656 | return 0; | |
657 | } | |
658 | ||
135340af PA |
659 | /* linux_nat_target::low_new_thread implementation. Write the |
660 | mirrored watch register values for the new thread. */ | |
b9412953 | 661 | |
135340af PA |
662 | void |
663 | mips_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
b9412953 | 664 | { |
339053c2 | 665 | long tid = lp->ptid.lwp (); |
b9412953 | 666 | |
7974a605 | 667 | if (!mips_linux_read_watch_registers (tid, |
b3436450 YQ |
668 | &watch_readback, |
669 | &watch_readback_valid, 0)) | |
b9412953 DD |
670 | return; |
671 | ||
aa58a496 | 672 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
673 | perror_with_name (_("Couldn't write debug register")); |
674 | } | |
675 | ||
b9412953 DD |
676 | /* Target to_insert_watchpoint implementation. Try to insert a new |
677 | watch. Return zero on success. */ | |
678 | ||
f6ac5f3d PA |
679 | int |
680 | mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
681 | enum target_hw_bp_type type, | |
682 | struct expression *cond) | |
b9412953 DD |
683 | { |
684 | struct pt_watch_regs regs; | |
685 | struct mips_watchpoint *new_watch; | |
686 | struct mips_watchpoint **pw; | |
687 | ||
688 | int i; | |
689 | int retval; | |
690 | ||
b3436450 YQ |
691 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
692 | &watch_readback, | |
693 | &watch_readback_valid, 0)) | |
b9412953 DD |
694 | return -1; |
695 | ||
696 | if (len <= 0) | |
697 | return -1; | |
698 | ||
699 | regs = watch_readback; | |
700 | /* Add the current watches. */ | |
b3436450 | 701 | mips_linux_watch_populate_regs (current_watches, ®s); |
b9412953 DD |
702 | |
703 | /* Now try to add the new watch. */ | |
b3436450 YQ |
704 | if (!mips_linux_watch_try_one_watch (®s, addr, len, |
705 | mips_linux_watch_type_to_irw (type))) | |
b9412953 DD |
706 | return -1; |
707 | ||
708 | /* It fit. Stick it on the end of the list. */ | |
8d749320 | 709 | new_watch = XNEW (struct mips_watchpoint); |
b9412953 DD |
710 | new_watch->addr = addr; |
711 | new_watch->len = len; | |
712 | new_watch->type = type; | |
713 | new_watch->next = NULL; | |
714 | ||
715 | pw = ¤t_watches; | |
716 | while (*pw != NULL) | |
717 | pw = &(*pw)->next; | |
718 | *pw = new_watch; | |
719 | ||
720 | watch_mirror = regs; | |
721 | retval = write_watchpoint_regs (); | |
722 | ||
c5e92cca | 723 | if (show_debug_regs) |
b9412953 DD |
724 | mips_show_dr ("insert_watchpoint", addr, len, type); |
725 | ||
726 | return retval; | |
727 | } | |
728 | ||
729 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
730 | Return zero on success. */ | |
731 | ||
f6ac5f3d PA |
732 | int |
733 | mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
734 | enum target_hw_bp_type type, | |
735 | struct expression *cond) | |
b9412953 DD |
736 | { |
737 | int retval; | |
738 | int deleted_one; | |
739 | ||
740 | struct mips_watchpoint **pw; | |
741 | struct mips_watchpoint *w; | |
742 | ||
743 | /* Search for a known watch that matches. Then unlink and free | |
744 | it. */ | |
745 | deleted_one = 0; | |
746 | pw = ¤t_watches; | |
747 | while ((w = *pw)) | |
748 | { | |
749 | if (w->addr == addr && w->len == len && w->type == type) | |
750 | { | |
751 | *pw = w->next; | |
752 | xfree (w); | |
753 | deleted_one = 1; | |
754 | break; | |
755 | } | |
756 | pw = &(w->next); | |
757 | } | |
758 | ||
759 | if (!deleted_one) | |
760 | return -1; /* We don't know about it, fail doing nothing. */ | |
761 | ||
762 | /* At this point watch_readback is known to be valid because we | |
763 | could not have added the watch without reading it. */ | |
764 | gdb_assert (watch_readback_valid == 1); | |
765 | ||
766 | watch_mirror = watch_readback; | |
b3436450 | 767 | mips_linux_watch_populate_regs (current_watches, &watch_mirror); |
b9412953 DD |
768 | |
769 | retval = write_watchpoint_regs (); | |
770 | ||
c5e92cca | 771 | if (show_debug_regs) |
b9412953 DD |
772 | mips_show_dr ("remove_watchpoint", addr, len, type); |
773 | ||
774 | return retval; | |
775 | } | |
776 | ||
777 | /* Target to_close implementation. Free any watches and call the | |
778 | super implementation. */ | |
779 | ||
f6ac5f3d PA |
780 | void |
781 | mips_linux_nat_target::close () | |
b9412953 DD |
782 | { |
783 | struct mips_watchpoint *w; | |
784 | struct mips_watchpoint *nw; | |
785 | ||
786 | /* Clean out the current_watches list. */ | |
787 | w = current_watches; | |
788 | while (w) | |
789 | { | |
790 | nw = w->next; | |
791 | xfree (w); | |
792 | w = nw; | |
793 | } | |
794 | current_watches = NULL; | |
795 | ||
f6ac5f3d | 796 | linux_nat_trad_target::close (); |
b9412953 DD |
797 | } |
798 | ||
10d6c8cd DJ |
799 | void |
800 | _initialize_mips_linux_nat (void) | |
801 | { | |
cbe54154 | 802 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
c5e92cca | 803 | &show_debug_regs, _("\ |
cbe54154 PA |
804 | Set whether to show variables that mirror the mips debug registers."), _("\ |
805 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
806 | Use \"on\" to enable, \"off\" to disable.\n\ |
807 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
808 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
809 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
810 | NULL, |
811 | NULL, | |
812 | &maintenance_set_cmdlist, | |
813 | &maintenance_show_cmdlist); | |
b9412953 | 814 | |
f6ac5f3d | 815 | linux_target = &the_mips_linux_nat_target; |
d9f719f1 | 816 | add_inf_child_target (&the_mips_linux_nat_target); |
10d6c8cd | 817 | } |