Add target_ops argument to to_post_attach
[deliverable/binutils-gdb.git] / gdb / mips-linux-nat.c
CommitLineData
75c9abc6 1/* Native-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
ecd75fc8 3 Copyright (C) 2001-2014 Free Software Foundation, Inc.
2aa830e4
DJ
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ
19
20#include "defs.h"
b9412953
DD
21#include "command.h"
22#include "gdbcmd.h"
23#include "gdb_assert.h"
d37eb719 24#include "inferior.h"
6b753f60 25#include "mips-tdep.h"
10d6c8cd 26#include "target.h"
28f5035f 27#include "regcache.h"
10d6c8cd 28#include "linux-nat.h"
d37eb719 29#include "mips-linux-tdep.h"
822b6570 30#include "target-descriptions.h"
2aa830e4 31
dc60ece8 32#include "gdb_proc_service.h"
3e00823e 33#include "gregset.h"
dc60ece8 34
822b6570 35#include <sgidefs.h>
d37eb719 36#include <sys/ptrace.h>
9be14b81 37#include <asm/ptrace.h>
d37eb719 38
aaee2056
YQ
39#include "mips-linux-watch.h"
40
81adfced 41#include "features/mips-linux.c"
1faeff08 42#include "features/mips-dsp-linux.c"
81adfced 43#include "features/mips64-linux.c"
1faeff08 44#include "features/mips64-dsp-linux.c"
81adfced 45
dc60ece8
DJ
46#ifndef PTRACE_GET_THREAD_AREA
47#define PTRACE_GET_THREAD_AREA 25
48#endif
49
d37eb719
DJ
50/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
51 we'll clear this and use PTRACE_PEEKUSER instead. */
52static int have_ptrace_regsets = 1;
53
b9412953
DD
54/* Whether or not to print the mirrored debug registers. */
55
56static int maint_show_dr;
57
d37eb719
DJ
58/* Saved function pointers to fetch and store a single register using
59 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
60
b9412953
DD
61static void (*super_fetch_registers) (struct target_ops *,
62 struct regcache *, int);
63static void (*super_store_registers) (struct target_ops *,
64 struct regcache *, int);
65
460014f5 66static void (*super_close) (void);
d37eb719 67
dda0c97e 68/* Map gdb internal register number to ptrace ``address''.
7714d83a
UW
69 These ``addresses'' are normally defined in <asm/ptrace.h>.
70
71 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
72 and there's no point in reading or setting MIPS_ZERO_REGNUM.
73 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
dda0c97e
UW
74
75static CORE_ADDR
7714d83a 76mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
dda0c97e 77{
7714d83a 78 CORE_ADDR regaddr;
dda0c97e 79
2eb4d78b 80 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
dda0c97e
UW
81 error (_("Bogon register number %d."), regno);
82
7714d83a 83 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
dda0c97e 84 regaddr = regno;
7714d83a
UW
85 else if ((regno >= mips_regnum (gdbarch)->fp0)
86 && (regno < mips_regnum (gdbarch)->fp0 + 32))
87 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
88 else if (regno == mips_regnum (gdbarch)->pc)
dda0c97e 89 regaddr = PC;
7714d83a
UW
90 else if (regno == mips_regnum (gdbarch)->cause)
91 regaddr = store? (CORE_ADDR) -1 : CAUSE;
92 else if (regno == mips_regnum (gdbarch)->badvaddr)
93 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
94 else if (regno == mips_regnum (gdbarch)->lo)
dda0c97e 95 regaddr = MMLO;
7714d83a 96 else if (regno == mips_regnum (gdbarch)->hi)
dda0c97e 97 regaddr = MMHI;
7714d83a 98 else if (regno == mips_regnum (gdbarch)->fp_control_status)
dda0c97e 99 regaddr = FPC_CSR;
7714d83a
UW
100 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
101 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
1faeff08
MR
102 else if (mips_regnum (gdbarch)->dspacc != -1
103 && regno >= mips_regnum (gdbarch)->dspacc
104 && regno < mips_regnum (gdbarch)->dspacc + 6)
105 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
106 else if (regno == mips_regnum (gdbarch)->dspctl)
107 regaddr = DSP_CONTROL;
822b6570
DJ
108 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
109 regaddr = 0;
dda0c97e 110 else
7714d83a 111 regaddr = (CORE_ADDR) -1;
dda0c97e
UW
112
113 return regaddr;
114}
115
116static CORE_ADDR
7714d83a 117mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
dda0c97e 118{
7714d83a 119 CORE_ADDR regaddr;
dda0c97e 120
2eb4d78b 121 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
dda0c97e
UW
122 error (_("Bogon register number %d."), regno);
123
7714d83a 124 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
dda0c97e 125 regaddr = regno;
7714d83a
UW
126 else if ((regno >= mips_regnum (gdbarch)->fp0)
127 && (regno < mips_regnum (gdbarch)->fp0 + 32))
2eb4d78b 128 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
7714d83a 129 else if (regno == mips_regnum (gdbarch)->pc)
dda0c97e 130 regaddr = MIPS64_PC;
7714d83a
UW
131 else if (regno == mips_regnum (gdbarch)->cause)
132 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
133 else if (regno == mips_regnum (gdbarch)->badvaddr)
134 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
135 else if (regno == mips_regnum (gdbarch)->lo)
dda0c97e 136 regaddr = MIPS64_MMLO;
7714d83a 137 else if (regno == mips_regnum (gdbarch)->hi)
dda0c97e 138 regaddr = MIPS64_MMHI;
7714d83a 139 else if (regno == mips_regnum (gdbarch)->fp_control_status)
dda0c97e 140 regaddr = MIPS64_FPC_CSR;
7714d83a
UW
141 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
142 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
1faeff08
MR
143 else if (mips_regnum (gdbarch)->dspacc != -1
144 && regno >= mips_regnum (gdbarch)->dspacc
145 && regno < mips_regnum (gdbarch)->dspacc + 6)
146 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
147 else if (regno == mips_regnum (gdbarch)->dspctl)
148 regaddr = DSP_CONTROL;
822b6570
DJ
149 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
150 regaddr = 0;
dda0c97e 151 else
7714d83a 152 regaddr = (CORE_ADDR) -1;
dda0c97e
UW
153
154 return regaddr;
155}
156
dc60ece8
DJ
157/* Fetch the thread-local storage pointer for libthread_db. */
158
159ps_err_e
160ps_get_thread_area (const struct ps_prochandle *ph,
161 lwpid_t lwpid, int idx, void **base)
162{
163 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
164 return PS_ERR;
165
166 /* IDX is the bias from the thread pointer to the beginning of the
167 thread descriptor. It has to be subtracted due to implementation
168 quirks in libthread_db. */
169 *base = (void *) ((char *)*base - idx);
170
171 return PS_OK;
172}
173
3e00823e
UW
174/* Wrapper functions. These are only used by libthread_db. */
175
176void
7f7fe91e 177supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
3e00823e 178{
2eb4d78b 179 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
7f7fe91e 180 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
3e00823e 181 else
7f7fe91e 182 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
3e00823e
UW
183}
184
185void
7f7fe91e
UW
186fill_gregset (const struct regcache *regcache,
187 gdb_gregset_t *gregsetp, int regno)
3e00823e 188{
2eb4d78b 189 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
7f7fe91e 190 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
3e00823e 191 else
7f7fe91e 192 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
3e00823e
UW
193}
194
195void
7f7fe91e 196supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
3e00823e 197{
2eb4d78b 198 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
7f7fe91e 199 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
3e00823e 200 else
025bb325
MS
201 mips64_supply_fpregset (regcache,
202 (const mips64_elf_fpregset_t *) fpregsetp);
3e00823e
UW
203}
204
205void
7f7fe91e
UW
206fill_fpregset (const struct regcache *regcache,
207 gdb_fpregset_t *fpregsetp, int regno)
3e00823e 208{
2eb4d78b 209 if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
7f7fe91e 210 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
3e00823e 211 else
025bb325
MS
212 mips64_fill_fpregset (regcache,
213 (mips64_elf_fpregset_t *) fpregsetp, regno);
3e00823e
UW
214}
215
216
d37eb719
DJ
217/* Fetch REGNO (or all registers if REGNO == -1) from the target
218 using PTRACE_GETREGS et al. */
219
220static void
1faeff08
MR
221mips64_linux_regsets_fetch_registers (struct target_ops *ops,
222 struct regcache *regcache, int regno)
d37eb719 223{
2eb4d78b 224 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1faeff08
MR
225 int is_fp, is_dsp;
226 int have_dsp;
227 int regi;
d37eb719
DJ
228 int tid;
229
2eb4d78b
UW
230 if (regno >= mips_regnum (gdbarch)->fp0
231 && regno <= mips_regnum (gdbarch)->fp0 + 32)
d37eb719 232 is_fp = 1;
2eb4d78b 233 else if (regno == mips_regnum (gdbarch)->fp_control_status)
d37eb719 234 is_fp = 1;
2eb4d78b 235 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ
236 is_fp = 1;
237 else
238 is_fp = 0;
239
1faeff08
MR
240 /* DSP registers are optional and not a part of any set. */
241 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
242 if (!have_dsp)
243 is_dsp = 0;
244 else if (regno >= mips_regnum (gdbarch)->dspacc
245 && regno < mips_regnum (gdbarch)->dspacc + 6)
246 is_dsp = 1;
247 else if (regno == mips_regnum (gdbarch)->dspctl)
248 is_dsp = 1;
249 else
250 is_dsp = 0;
251
d37eb719
DJ
252 tid = ptid_get_lwp (inferior_ptid);
253 if (tid == 0)
254 tid = ptid_get_pid (inferior_ptid);
255
1faeff08 256 if (regno == -1 || (!is_fp && !is_dsp))
d37eb719
DJ
257 {
258 mips64_elf_gregset_t regs;
259
260 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
261 {
262 if (errno == EIO)
263 {
264 have_ptrace_regsets = 0;
265 return;
266 }
267 perror_with_name (_("Couldn't get registers"));
268 }
269
56be3814 270 mips64_supply_gregset (regcache,
28f5035f 271 (const mips64_elf_gregset_t *) &regs);
d37eb719
DJ
272 }
273
274 if (regno == -1 || is_fp)
275 {
276 mips64_elf_fpregset_t fp_regs;
277
278 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
279 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
280 {
281 if (errno == EIO)
282 {
283 have_ptrace_regsets = 0;
284 return;
285 }
286 perror_with_name (_("Couldn't get FP registers"));
287 }
288
56be3814 289 mips64_supply_fpregset (regcache,
28f5035f 290 (const mips64_elf_fpregset_t *) &fp_regs);
d37eb719 291 }
1faeff08
MR
292
293 if (is_dsp)
294 super_fetch_registers (ops, regcache, regno);
295 else if (regno == -1 && have_dsp)
296 {
297 for (regi = mips_regnum (gdbarch)->dspacc;
298 regi < mips_regnum (gdbarch)->dspacc + 6;
299 regi++)
300 super_fetch_registers (ops, regcache, regi);
301 super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
302 }
d37eb719
DJ
303}
304
305/* Store REGNO (or all registers if REGNO == -1) to the target
306 using PTRACE_SETREGS et al. */
307
308static void
1faeff08
MR
309mips64_linux_regsets_store_registers (struct target_ops *ops,
310 struct regcache *regcache, int regno)
d37eb719 311{
2eb4d78b 312 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1faeff08
MR
313 int is_fp, is_dsp;
314 int have_dsp;
315 int regi;
d37eb719
DJ
316 int tid;
317
2eb4d78b
UW
318 if (regno >= mips_regnum (gdbarch)->fp0
319 && regno <= mips_regnum (gdbarch)->fp0 + 32)
d37eb719 320 is_fp = 1;
2eb4d78b 321 else if (regno == mips_regnum (gdbarch)->fp_control_status)
d37eb719 322 is_fp = 1;
2eb4d78b 323 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ
324 is_fp = 1;
325 else
326 is_fp = 0;
327
1faeff08
MR
328 /* DSP registers are optional and not a part of any set. */
329 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
330 if (!have_dsp)
331 is_dsp = 0;
6ce4c112 332 else if (regno >= mips_regnum (gdbarch)->dspacc
1faeff08
MR
333 && regno < mips_regnum (gdbarch)->dspacc + 6)
334 is_dsp = 1;
335 else if (regno == mips_regnum (gdbarch)->dspctl)
336 is_dsp = 1;
337 else
338 is_dsp = 0;
339
d37eb719
DJ
340 tid = ptid_get_lwp (inferior_ptid);
341 if (tid == 0)
342 tid = ptid_get_pid (inferior_ptid);
343
1faeff08 344 if (regno == -1 || (!is_fp && !is_dsp))
d37eb719
DJ
345 {
346 mips64_elf_gregset_t regs;
347
348 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
349 perror_with_name (_("Couldn't get registers"));
350
56be3814 351 mips64_fill_gregset (regcache, &regs, regno);
d37eb719
DJ
352
353 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
354 perror_with_name (_("Couldn't set registers"));
355 }
356
357 if (regno == -1 || is_fp)
358 {
359 mips64_elf_fpregset_t fp_regs;
360
361 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
362 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
363 perror_with_name (_("Couldn't get FP registers"));
364
56be3814 365 mips64_fill_fpregset (regcache, &fp_regs, regno);
d37eb719
DJ
366
367 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
368 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
369 perror_with_name (_("Couldn't set FP registers"));
370 }
1faeff08
MR
371
372 if (is_dsp)
373 super_store_registers (ops, regcache, regno);
374 else if (regno == -1 && have_dsp)
375 {
376 for (regi = mips_regnum (gdbarch)->dspacc;
377 regi < mips_regnum (gdbarch)->dspacc + 6;
378 regi++)
379 super_store_registers (ops, regcache, regi);
380 super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
381 }
d37eb719
DJ
382}
383
384/* Fetch REGNO (or all registers if REGNO == -1) from the target
385 using any working method. */
386
387static void
28439f5e
PA
388mips64_linux_fetch_registers (struct target_ops *ops,
389 struct regcache *regcache, int regnum)
d37eb719
DJ
390{
391 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
392 if (have_ptrace_regsets)
1faeff08 393 mips64_linux_regsets_fetch_registers (ops, regcache, regnum);
d37eb719
DJ
394
395 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
396 back to PTRACE_PEEKUSER. */
397 if (!have_ptrace_regsets)
a0740d21 398 super_fetch_registers (ops, regcache, regnum);
d37eb719
DJ
399}
400
401/* Store REGNO (or all registers if REGNO == -1) to the target
402 using any working method. */
403
404static void
28439f5e
PA
405mips64_linux_store_registers (struct target_ops *ops,
406 struct regcache *regcache, int regnum)
d37eb719
DJ
407{
408 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
409 if (have_ptrace_regsets)
1faeff08 410 mips64_linux_regsets_store_registers (ops, regcache, regnum);
d37eb719
DJ
411
412 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
413 back to PTRACE_PEEKUSER. */
414 if (!have_ptrace_regsets)
a0740d21 415 super_store_registers (ops, regcache, regnum);
d37eb719
DJ
416}
417
910122bf
UW
418/* Return the address in the core dump or inferior of register
419 REGNO. */
420
421static CORE_ADDR
7714d83a 422mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
910122bf 423{
7714d83a
UW
424 if (mips_abi_regsize (gdbarch) == 8)
425 return mips64_linux_register_addr (gdbarch, regno, store_p);
dda0c97e 426 else
7714d83a 427 return mips_linux_register_addr (gdbarch, regno, store_p);
910122bf
UW
428}
429
81adfced
DJ
430static const struct target_desc *
431mips_linux_read_description (struct target_ops *ops)
822b6570 432{
1faeff08
MR
433 static int have_dsp = -1;
434
435 if (have_dsp < 0)
436 {
437 int tid;
438
439 tid = ptid_get_lwp (inferior_ptid);
440 if (tid == 0)
441 tid = ptid_get_pid (inferior_ptid);
442
443 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
444 switch (errno)
445 {
446 case 0:
447 have_dsp = 1;
448 break;
449 case EIO:
450 have_dsp = 0;
451 break;
452 default:
837a1b32 453 perror_with_name (_("Couldn't check DSP support"));
1faeff08
MR
454 break;
455 }
456 }
457
81adfced
DJ
458 /* Report that target registers are a size we know for sure
459 that we can get from ptrace. */
460 if (_MIPS_SIM == _ABIO32)
1faeff08 461 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
81adfced 462 else
1faeff08 463 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
822b6570
DJ
464}
465
b9412953
DD
466/* -1 if the kernel and/or CPU do not support watch registers.
467 1 if watch_readback is valid and we can read style, num_valid
468 and the masks.
469 0 if we need to read the watch_readback. */
470
471static int watch_readback_valid;
472
473/* Cached watch register read values. */
474
475static struct pt_watch_regs watch_readback;
476
b9412953
DD
477static struct mips_watchpoint *current_watches;
478
479/* The current set of watch register values for writing the
480 registers. */
481
482static struct pt_watch_regs watch_mirror;
483
b9412953
DD
484static void
485mips_show_dr (const char *func, CORE_ADDR addr,
486 int len, enum target_hw_bp_type type)
487{
488 int i;
489
490 puts_unfiltered (func);
491 if (addr || len)
5af949e3 492 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
f5656ead 493 paddress (target_gdbarch (), addr), len,
b9412953
DD
494 type == hw_write ? "data-write"
495 : (type == hw_read ? "data-read"
496 : (type == hw_access ? "data-read/write"
497 : (type == hw_execute ? "instruction-execute"
498 : "??unknown??"))));
499 puts_unfiltered (":\n");
500
501 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
5af949e3 502 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
f5656ead 503 paddress (target_gdbarch (),
b3436450
YQ
504 mips_linux_watch_get_watchlo (&watch_mirror,
505 i)),
f5656ead 506 paddress (target_gdbarch (),
b3436450
YQ
507 mips_linux_watch_get_watchhi (&watch_mirror,
508 i)));
b9412953
DD
509}
510
b9412953
DD
511/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
512 handle the specified watch type. */
513
514static int
515mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
516{
517 int i;
518 uint32_t wanted_mask, irw_mask;
519
b3436450
YQ
520 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
521 &watch_readback,
522 &watch_readback_valid, 0))
b9412953
DD
523 return 0;
524
525 switch (type)
526 {
527 case bp_hardware_watchpoint:
528 wanted_mask = W_MASK;
529 break;
530 case bp_read_watchpoint:
531 wanted_mask = R_MASK;
532 break;
533 case bp_access_watchpoint:
534 wanted_mask = R_MASK | W_MASK;
535 break;
536 default:
537 return 0;
538 }
539
b3436450
YQ
540 for (i = 0;
541 i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
542 i++)
b9412953 543 {
b3436450 544 irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
b9412953
DD
545 if ((irw_mask & wanted_mask) == wanted_mask)
546 cnt--;
547 }
548 return (cnt == 0) ? 1 : 0;
549}
550
551/* Target to_stopped_by_watchpoint implementation. Return 1 if
552 stopped by watchpoint. The watchhi R and W bits indicate the watch
025bb325 553 register triggered. */
b9412953
DD
554
555static int
6a109b6b 556mips_linux_stopped_by_watchpoint (struct target_ops *ops)
b9412953
DD
557{
558 int n;
559 int num_valid;
560
b3436450
YQ
561 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
562 &watch_readback,
563 &watch_readback_valid, 1))
b9412953
DD
564 return 0;
565
b3436450 566 num_valid = mips_linux_watch_get_num_valid (&watch_readback);
b9412953
DD
567
568 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
b3436450 569 if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
b9412953
DD
570 return 1;
571
572 return 0;
573}
574
575/* Target to_stopped_data_address implementation. Set the address
576 where the watch triggered (if known). Return 1 if the address was
577 known. */
578
579static int
580mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
581{
582 /* On mips we don't know the low order 3 bits of the data address,
583 so we must return false. */
584 return 0;
585}
586
b9412953
DD
587/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
588 the specified region can be covered by the watch registers. */
589
590static int
591mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
592{
593 struct pt_watch_regs dummy_regs;
594 int i;
595
b3436450
YQ
596 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
597 &watch_readback,
598 &watch_readback_valid, 0))
b9412953
DD
599 return 0;
600
601 dummy_regs = watch_readback;
602 /* Clear them out. */
b3436450
YQ
603 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
604 mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
605 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
b9412953
DD
606}
607
b9412953
DD
608/* Write the mirrored watch register values for each thread. */
609
610static int
611write_watchpoint_regs (void)
612{
613 struct lwp_info *lp;
b9412953
DD
614 int tid;
615
4c38200f 616 ALL_LWPS (lp)
b9412953 617 {
4c38200f 618 tid = ptid_get_lwp (lp->ptid);
b9412953
DD
619 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
620 perror_with_name (_("Couldn't write debug register"));
621 }
622 return 0;
623}
624
625/* linux_nat new_thread implementation. Write the mirrored watch
626 register values for the new thread. */
627
628static void
7b50312a 629mips_linux_new_thread (struct lwp_info *lp)
b9412953
DD
630{
631 int tid;
632
b3436450
YQ
633 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
634 &watch_readback,
635 &watch_readback_valid, 0))
b9412953
DD
636 return;
637
7b50312a 638 tid = ptid_get_lwp (lp->ptid);
b9412953
DD
639 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1)
640 perror_with_name (_("Couldn't write debug register"));
641}
642
b9412953
DD
643/* Target to_insert_watchpoint implementation. Try to insert a new
644 watch. Return zero on success. */
645
646static int
0cf6dd15
TJB
647mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
648 struct expression *cond)
b9412953
DD
649{
650 struct pt_watch_regs regs;
651 struct mips_watchpoint *new_watch;
652 struct mips_watchpoint **pw;
653
654 int i;
655 int retval;
656
b3436450
YQ
657 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
658 &watch_readback,
659 &watch_readback_valid, 0))
b9412953
DD
660 return -1;
661
662 if (len <= 0)
663 return -1;
664
665 regs = watch_readback;
666 /* Add the current watches. */
b3436450 667 mips_linux_watch_populate_regs (current_watches, &regs);
b9412953
DD
668
669 /* Now try to add the new watch. */
b3436450
YQ
670 if (!mips_linux_watch_try_one_watch (&regs, addr, len,
671 mips_linux_watch_type_to_irw (type)))
b9412953
DD
672 return -1;
673
674 /* It fit. Stick it on the end of the list. */
675 new_watch = (struct mips_watchpoint *)
676 xmalloc (sizeof (struct mips_watchpoint));
677 new_watch->addr = addr;
678 new_watch->len = len;
679 new_watch->type = type;
680 new_watch->next = NULL;
681
682 pw = &current_watches;
683 while (*pw != NULL)
684 pw = &(*pw)->next;
685 *pw = new_watch;
686
687 watch_mirror = regs;
688 retval = write_watchpoint_regs ();
689
690 if (maint_show_dr)
691 mips_show_dr ("insert_watchpoint", addr, len, type);
692
693 return retval;
694}
695
696/* Target to_remove_watchpoint implementation. Try to remove a watch.
697 Return zero on success. */
698
699static int
0cf6dd15
TJB
700mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
701 struct expression *cond)
b9412953
DD
702{
703 int retval;
704 int deleted_one;
705
706 struct mips_watchpoint **pw;
707 struct mips_watchpoint *w;
708
709 /* Search for a known watch that matches. Then unlink and free
710 it. */
711 deleted_one = 0;
712 pw = &current_watches;
713 while ((w = *pw))
714 {
715 if (w->addr == addr && w->len == len && w->type == type)
716 {
717 *pw = w->next;
718 xfree (w);
719 deleted_one = 1;
720 break;
721 }
722 pw = &(w->next);
723 }
724
725 if (!deleted_one)
726 return -1; /* We don't know about it, fail doing nothing. */
727
728 /* At this point watch_readback is known to be valid because we
729 could not have added the watch without reading it. */
730 gdb_assert (watch_readback_valid == 1);
731
732 watch_mirror = watch_readback;
b3436450 733 mips_linux_watch_populate_regs (current_watches, &watch_mirror);
b9412953
DD
734
735 retval = write_watchpoint_regs ();
736
737 if (maint_show_dr)
738 mips_show_dr ("remove_watchpoint", addr, len, type);
739
740 return retval;
741}
742
743/* Target to_close implementation. Free any watches and call the
744 super implementation. */
745
746static void
de90e03d 747mips_linux_close (struct target_ops *self)
b9412953
DD
748{
749 struct mips_watchpoint *w;
750 struct mips_watchpoint *nw;
751
752 /* Clean out the current_watches list. */
753 w = current_watches;
754 while (w)
755 {
756 nw = w->next;
757 xfree (w);
758 w = nw;
759 }
760 current_watches = NULL;
761
762 if (super_close)
460014f5 763 super_close ();
b9412953
DD
764}
765
10d6c8cd
DJ
766void _initialize_mips_linux_nat (void);
767
768void
769_initialize_mips_linux_nat (void)
770{
b9412953
DD
771 struct target_ops *t;
772
cbe54154
PA
773 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
774 &maint_show_dr, _("\
775Set whether to show variables that mirror the mips debug registers."), _("\
776Show whether to show variables that mirror the mips debug registers."), _("\
b9412953
DD
777Use \"on\" to enable, \"off\" to disable.\n\
778If enabled, the debug registers values are shown when GDB inserts\n\
779or removes a hardware breakpoint or watchpoint, and when the inferior\n\
780triggers a breakpoint or watchpoint."),
cbe54154
PA
781 NULL,
782 NULL,
783 &maintenance_set_cmdlist,
784 &maintenance_show_cmdlist);
b9412953
DD
785
786 t = linux_trad_target (mips_linux_register_u_offset);
787
788 super_close = t->to_close;
789 t->to_close = mips_linux_close;
d37eb719
DJ
790
791 super_fetch_registers = t->to_fetch_registers;
792 super_store_registers = t->to_store_registers;
793
794 t->to_fetch_registers = mips64_linux_fetch_registers;
795 t->to_store_registers = mips64_linux_store_registers;
796
b9412953
DD
797 t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint;
798 t->to_remove_watchpoint = mips_linux_remove_watchpoint;
799 t->to_insert_watchpoint = mips_linux_insert_watchpoint;
800 t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint;
801 t->to_stopped_data_address = mips_linux_stopped_data_address;
802 t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint;
803
81adfced 804 t->to_read_description = mips_linux_read_description;
822b6570 805
f973ed9c 806 linux_nat_add_target (t);
b9412953 807 linux_nat_set_new_thread (t, mips_linux_new_thread);
81adfced
DJ
808
809 /* Initialize the standard target descriptions. */
810 initialize_tdesc_mips_linux ();
1faeff08 811 initialize_tdesc_mips_dsp_linux ();
81adfced 812 initialize_tdesc_mips64_linux ();
1faeff08 813 initialize_tdesc_mips64_dsp_linux ();
10d6c8cd 814}
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