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Introduce ref_ptr::new_reference
[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
e2882c85 3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
2aa830e4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ		 19
20#include "defs.h"
21#include "gdbcore.h"
22#include "target.h"
23#include "solib-svr4.h"
19ed69dd 24#include "osabi.h"
96f026fc 25#include "mips-tdep.h"
6de918a6 26#include "frame.h"
2fdf551c 27#include "regcache.h"
5792a79b
DJ		 28#include "trad-frame.h"
29#include "tramp-frame.h"
e6bb342a 30#include "gdbtypes.h"
3e5d3a5a 31#include "objfiles.h"
5ea03926 32#include "solib.h"
7d522c90 33#include "solist.h"
982e9687 34#include "symtab.h"
822b6570 35#include "target-descriptions.h"
50e8a0d5 36#include "regset.h"
d37eb719 37#include "mips-linux-tdep.h"
db5f024e 38#include "glibc-tdep.h"
a5ee0f0c 39#include "linux-tdep.h"
385203ed 40#include "xml-syscall.h"
232b8704 41#include "gdb_signals.h"
2aa830e4 42
032bb6ea
YQ		 43#include "features/mips-linux.c"
44#include "features/mips-dsp-linux.c"
45#include "features/mips64-linux.c"
46#include "features/mips64-dsp-linux.c"
47
7d522c90
DJ		 48static struct target_so_ops mips_svr4_so_ops;
49
eb14d406
SDJ		 50/* This enum represents the signals' numbers on the MIPS
51 architecture. It just contains the signal definitions which are
52 different from the generic implementation.
53
54 It is derived from the file <arch/mips/include/uapi/asm/signal.h>,
55 from the Linux kernel tree. */
56
57enum
58 {
59 MIPS_LINUX_SIGEMT = 7,
60 MIPS_LINUX_SIGBUS = 10,
61 MIPS_LINUX_SIGSYS = 12,
62 MIPS_LINUX_SIGUSR1 = 16,
63 MIPS_LINUX_SIGUSR2 = 17,
64 MIPS_LINUX_SIGCHLD = 18,
65 MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD,
66 MIPS_LINUX_SIGPWR = 19,
67 MIPS_LINUX_SIGWINCH = 20,
68 MIPS_LINUX_SIGURG = 21,
69 MIPS_LINUX_SIGIO = 22,
70 MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO,
71 MIPS_LINUX_SIGSTOP = 23,
72 MIPS_LINUX_SIGTSTP = 24,
73 MIPS_LINUX_SIGCONT = 25,
74 MIPS_LINUX_SIGTTIN = 26,
75 MIPS_LINUX_SIGTTOU = 27,
76 MIPS_LINUX_SIGVTALRM = 28,
77 MIPS_LINUX_SIGPROF = 29,
78 MIPS_LINUX_SIGXCPU = 30,
79 MIPS_LINUX_SIGXFSZ = 31,
80
81 MIPS_LINUX_SIGRTMIN = 32,
82 MIPS_LINUX_SIGRT64 = 64,
83 MIPS_LINUX_SIGRTMAX = 127,
84 };
85
2aa830e4 86/* Figure out where the longjmp will land.
295093a4
MS		 87 We expect the first arg to be a pointer to the jmp_buf structure
88 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
89 at. The pc is copied into PC. This routine returns 1 on
90 success. */
2aa830e4 91
19ed69dd
KB		 92#define MIPS_LINUX_JB_ELEMENT_SIZE 4
93#define MIPS_LINUX_JB_PC 0
94
95static int
60ade65d 96mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2aa830e4
DJ		 97{
98 CORE_ADDR jb_addr;
2eb4d78b 99 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 100 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e362b510 101 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
2aa830e4 102
60ade65d 103 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
2aa830e4 104
7d266584
MR		 105 if (target_read_memory ((jb_addr
106 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
2eb4d78b 107 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
2aa830e4
DJ		 108 return 0;
109
819844ad 110 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 111 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
112 byte_order);
2aa830e4
DJ		 113
114 return 1;
115}
116
4246e332 117/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 118 for regcache_raw_supply(). This is needed when mips_isa_regsize()
119 is 8. */
96f026fc
KB		 120
121static void
28f5035f 122supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
96f026fc 123{
b057297a 124 regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true);
96f026fc
KB		 125}
126
2aa830e4
DJ		 127/* Unpack an elf_gregset_t into GDB's register cache. */
128
d37eb719 129void
28f5035f
UW		 130mips_supply_gregset (struct regcache *regcache,
131 const mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 132{
133 int regi;
28f5035f 134 const mips_elf_greg_t *regp = *gregsetp;
ac7936df 135 struct gdbarch *gdbarch = regcache->arch ();
bf072999 136
822b6570 137 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
28f5035f 138 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
2aa830e4 139
2eb4d78b 140 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 141 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
142
2eb4d78b
UW		 143 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
144 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
56cea623 145
2eb4d78b 146 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 147 regp + EF_CP0_EPC);
2eb4d78b 148 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 149 regp + EF_CP0_BADVADDR);
150 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
2eb4d78b 151 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 152 regp + EF_CP0_CAUSE);
2aa830e4 153
1faeff08 154 /* Fill the inaccessible zero register with zero. */
27bfc1d1 155 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
2aa830e4
DJ		 156}
157
50e8a0d5
HZ		 158static void
159mips_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 160 struct regcache *regcache,
161 int regnum, const void *gregs, size_t len)
50e8a0d5 162{
1528345d 163 gdb_assert (len >= sizeof (mips_elf_gregset_t));
50e8a0d5
HZ		 164
165 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
166}
167
2aa830e4
DJ		 168/* Pack our registers (or one register) into an elf_gregset_t. */
169
d37eb719 170void
28f5035f
UW		 171mips_fill_gregset (const struct regcache *regcache,
172 mips_elf_gregset_t *gregsetp, int regno)
2aa830e4 173{
ac7936df 174 struct gdbarch *gdbarch = regcache->arch ();
2aa830e4 175 int regaddr, regi;
d37eb719 176 mips_elf_greg_t *regp = *gregsetp;
96f026fc 177 void *dst;
2aa830e4
DJ		 178
179 if (regno == -1)
180 {
d37eb719 181 memset (regp, 0, sizeof (mips_elf_gregset_t));
822b6570 182 for (regi = 1; regi < 32; regi++)
28f5035f 183 mips_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 184 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
185 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
186 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
187 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
28f5035f 188 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 189 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 190 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
2aa830e4
DJ		 191 return;
192 }
193
822b6570 194 if (regno > 0 && regno < 32)
2aa830e4 195 {
2aa830e4 196 dst = regp + regno + EF_REG0;
28f5035f 197 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 198 return;
199 }
200
2eb4d78b
UW		 201 if (regno == mips_regnum (gdbarch)->lo)
202 regaddr = EF_LO;
203 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 204 regaddr = EF_HI;
2eb4d78b 205 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 206 regaddr = EF_CP0_EPC;
2eb4d78b 207 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 208 regaddr = EF_CP0_BADVADDR;
24e05951 209 else if (regno == MIPS_PS_REGNUM)
56cea623 210 regaddr = EF_CP0_STATUS;
2eb4d78b 211 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 212 regaddr = EF_CP0_CAUSE;
2eb4d78b 213 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 214 && regno == MIPS_RESTART_REGNUM)
215 regaddr = EF_REG0;
56cea623
AC		 216 else
217 regaddr = -1;
2aa830e4
DJ		 218
219 if (regaddr != -1)
220 {
2aa830e4 221 dst = regp + regaddr;
28f5035f 222 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 223 }
224}
225
50e8a0d5
HZ		 226static void
227mips_fill_gregset_wrapper (const struct regset *regset,
228 const struct regcache *regcache,
229 int regnum, void *gregs, size_t len)
230{
1528345d 231 gdb_assert (len >= sizeof (mips_elf_gregset_t));
50e8a0d5
HZ		 232
233 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
234}
235
2aa830e4
DJ		 236/* Likewise, unpack an elf_fpregset_t. */
237
d37eb719 238void
28f5035f
UW		 239mips_supply_fpregset (struct regcache *regcache,
240 const mips_elf_fpregset_t *fpregsetp)
2aa830e4 241{
ac7936df 242 struct gdbarch *gdbarch = regcache->arch ();
52f0bd74 243 int regi;
2aa830e4
DJ		 244
245 for (regi = 0; regi < 32; regi++)
3e8c568d 246 regcache_raw_supply (regcache,
2eb4d78b 247 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 248 *fpregsetp + regi);
2aa830e4 249
28f5035f 250 regcache_raw_supply (regcache,
2eb4d78b 251 mips_regnum (gdbarch)->fp_control_status,
28f5035f 252 *fpregsetp + 32);
2aa830e4 253
295093a4 254 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
27bfc1d1
AH		 255 regcache->raw_supply_zeroed
256 (mips_regnum (gdbarch)->fp_implementation_revision);
2aa830e4
DJ		 257}
258
50e8a0d5
HZ		 259static void
260mips_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 261 struct regcache *regcache,
262 int regnum, const void *gregs, size_t len)
50e8a0d5 263{
1528345d 264 gdb_assert (len >= sizeof (mips_elf_fpregset_t));
50e8a0d5
HZ		 265
266 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs);
267}
268
2aa830e4
DJ		 269/* Likewise, pack one or all floating point registers into an
270 elf_fpregset_t. */
271
d37eb719 272void
28f5035f
UW		 273mips_fill_fpregset (const struct regcache *regcache,
274 mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4 275{
ac7936df 276 struct gdbarch *gdbarch = regcache->arch ();
22e048c9 277 char *to;
2aa830e4 278
2eb4d78b
UW		 279 if ((regno >= gdbarch_fp0_regnum (gdbarch))
280 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
2aa830e4 281 {
2eb4d78b 282 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
28f5035f 283 regcache_raw_collect (regcache, regno, to);
2aa830e4 284 }
2eb4d78b 285 else if (regno == mips_regnum (gdbarch)->fp_control_status)
2aa830e4 286 {
2aa830e4 287 to = (char *) (*fpregsetp + 32);
28f5035f 288 regcache_raw_collect (regcache, regno, to);
2aa830e4
DJ		 289 }
290 else if (regno == -1)
291 {
292 int regi;
293
294 for (regi = 0; regi < 32; regi++)
3e8c568d 295 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 296 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 297 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 298 mips_regnum (gdbarch)->fp_control_status);
2aa830e4
DJ		 299 }
300}
301
50e8a0d5
HZ		 302static void
303mips_fill_fpregset_wrapper (const struct regset *regset,
304 const struct regcache *regcache,
305 int regnum, void *gregs, size_t len)
306{
1528345d 307 gdb_assert (len >= sizeof (mips_elf_fpregset_t));
50e8a0d5
HZ		 308
309 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum);
310}
311
96f026fc
KB		 312/* Support for 64-bit ABIs. */
313
96f026fc 314/* Figure out where the longjmp will land.
295093a4
MS		 315 We expect the first arg to be a pointer to the jmp_buf structure
316 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
317 at. The pc is copied into PC. This routine returns 1 on
318 success. */
96f026fc
KB		 319
320/* Details about jmp_buf. */
321
322#define MIPS64_LINUX_JB_PC 0
323
324static int
60ade65d 325mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
96f026fc
KB		 326{
327 CORE_ADDR jb_addr;
2eb4d78b 328 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 329 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
709476c3
SM		 330 gdb_byte *buf
331 = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
2eb4d78b 332 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
96f026fc 333
60ade65d 334 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
96f026fc
KB		 335
336 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
819844ad 337 buf,
2eb4d78b 338 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
96f026fc
KB		 339 return 0;
340
819844ad 341 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 342 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
343 byte_order);
96f026fc
KB		 344
345 return 1;
346}
347
d37eb719
DJ		 348/* Register set support functions. These operate on standard 64-bit
349 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
350 target will still use the 64-bit format for PTRACE_GETREGS. */
351
352/* Supply a 64-bit register. */
96f026fc 353
63807e1d 354static void
28f5035f
UW		 355supply_64bit_reg (struct regcache *regcache, int regnum,
356 const gdb_byte *buf)
d37eb719 357{
ac7936df 358 struct gdbarch *gdbarch = regcache->arch ();
2eb4d78b
UW		 359 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
360 && register_size (gdbarch, regnum) == 4)
28f5035f 361 regcache_raw_supply (regcache, regnum, buf + 4);
d37eb719 362 else
28f5035f 363 regcache_raw_supply (regcache, regnum, buf);
d37eb719
DJ		 364}
365
366/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
367
368void
28f5035f
UW		 369mips64_supply_gregset (struct regcache *regcache,
370 const mips64_elf_gregset_t *gregsetp)
96f026fc
KB		 371{
372 int regi;
28f5035f 373 const mips64_elf_greg_t *regp = *gregsetp;
ac7936df 374 struct gdbarch *gdbarch = regcache->arch ();
96f026fc 375
822b6570 376 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
28f5035f 377 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
7d266584 378 (const gdb_byte *) (regp + regi));
28f5035f 379
2eb4d78b 380 if (mips_linux_restart_reg_p (gdbarch))
822b6570 381 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
7d266584 382 (const gdb_byte *) (regp + MIPS64_EF_REG0));
822b6570 383
2eb4d78b 384 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
28f5035f 385 (const gdb_byte *) (regp + MIPS64_EF_LO));
2eb4d78b 386 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
28f5035f
UW		 387 (const gdb_byte *) (regp + MIPS64_EF_HI));
388
2eb4d78b 389 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 390 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
2eb4d78b 391 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 392 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
393 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
394 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
2eb4d78b 395 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 396 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc 397
1faeff08 398 /* Fill the inaccessible zero register with zero. */
27bfc1d1 399 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
96f026fc
KB		 400}
401
50e8a0d5
HZ		 402static void
403mips64_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 404 struct regcache *regcache,
405 int regnum, const void *gregs, size_t len)
50e8a0d5 406{
1528345d 407 gdb_assert (len >= sizeof (mips64_elf_gregset_t));
50e8a0d5
HZ		 408
409 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
410}
411
d37eb719 412/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 413
d37eb719 414void
28f5035f
UW		 415mips64_fill_gregset (const struct regcache *regcache,
416 mips64_elf_gregset_t *gregsetp, int regno)
96f026fc 417{
ac7936df 418 struct gdbarch *gdbarch = regcache->arch ();
96f026fc
KB		 419 int regaddr, regi;
420 mips64_elf_greg_t *regp = *gregsetp;
2ba93934 421 void *dst;
96f026fc
KB		 422
423 if (regno == -1)
424 {
425 memset (regp, 0, sizeof (mips64_elf_gregset_t));
822b6570 426 for (regi = 1; regi < 32; regi++)
7d266584 427 mips64_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 428 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
429 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
430 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
025bb325
MS		 431 mips64_fill_gregset (regcache, gregsetp,
432 mips_regnum (gdbarch)->badvaddr);
28f5035f 433 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 434 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 435 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
96f026fc
KB		 436 return;
437 }
438
822b6570 439 if (regno > 0 && regno < 32)
d37eb719 440 regaddr = regno + MIPS64_EF_REG0;
2eb4d78b 441 else if (regno == mips_regnum (gdbarch)->lo)
56cea623 442 regaddr = MIPS64_EF_LO;
2eb4d78b 443 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 444 regaddr = MIPS64_EF_HI;
2eb4d78b 445 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 446 regaddr = MIPS64_EF_CP0_EPC;
2eb4d78b 447 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 448 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 449 else if (regno == MIPS_PS_REGNUM)
56cea623 450 regaddr = MIPS64_EF_CP0_STATUS;
2eb4d78b 451 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 452 regaddr = MIPS64_EF_CP0_CAUSE;
2eb4d78b 453 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 454 && regno == MIPS_RESTART_REGNUM)
455 regaddr = MIPS64_EF_REG0;
56cea623
AC		 456 else
457 regaddr = -1;
96f026fc
KB		 458
459 if (regaddr != -1)
460 {
461 dst = regp + regaddr;
b057297a 462 regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true);
96f026fc
KB		 463 }
464}
465
50e8a0d5
HZ		 466static void
467mips64_fill_gregset_wrapper (const struct regset *regset,
468 const struct regcache *regcache,
469 int regnum, void *gregs, size_t len)
470{
1528345d 471 gdb_assert (len >= sizeof (mips64_elf_gregset_t));
50e8a0d5
HZ		 472
473 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
474}
475
96f026fc
KB		 476/* Likewise, unpack an elf_fpregset_t. */
477
d37eb719 478void
28f5035f
UW		 479mips64_supply_fpregset (struct regcache *regcache,
480 const mips64_elf_fpregset_t *fpregsetp)
96f026fc 481{
ac7936df 482 struct gdbarch *gdbarch = regcache->arch ();
52f0bd74 483 int regi;
96f026fc 484
d37eb719
DJ		 485 /* See mips_linux_o32_sigframe_init for a description of the
486 peculiar FP register layout. */
2eb4d78b 487 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
d37eb719
DJ		 488 for (regi = 0; regi < 32; regi++)
489 {
7d266584
MR		 490 const gdb_byte *reg_ptr
491 = (const gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 492 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 493 reg_ptr += 4;
3e8c568d 494 regcache_raw_supply (regcache,
2eb4d78b 495 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 496 reg_ptr);
d37eb719
DJ		 497 }
498 else
499 for (regi = 0; regi < 32; regi++)
3e8c568d 500 regcache_raw_supply (regcache,
2eb4d78b 501 gdbarch_fp0_regnum (gdbarch) + regi,
7d266584 502 (const char *) (*fpregsetp + regi));
d37eb719 503
2eb4d78b 504 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
7d266584 505 (const gdb_byte *) (*fpregsetp + 32));
d37eb719
DJ		 506
507 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
508 include it - but the result of PTRACE_GETFPREGS does. The best we
509 can do is to assume that its value is present. */
28f5035f 510 supply_32bit_reg (regcache,
2eb4d78b 511 mips_regnum (gdbarch)->fp_implementation_revision,
7d266584 512 (const gdb_byte *) (*fpregsetp + 32) + 4);
96f026fc
KB		 513}
514
50e8a0d5
HZ		 515static void
516mips64_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 517 struct regcache *regcache,
518 int regnum, const void *gregs, size_t len)
50e8a0d5 519{
1528345d 520 gdb_assert (len >= sizeof (mips64_elf_fpregset_t));
50e8a0d5
HZ		 521
522 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
523}
524
96f026fc
KB		 525/* Likewise, pack one or all floating point registers into an
526 elf_fpregset_t. */
527
d37eb719 528void
28f5035f
UW		 529mips64_fill_fpregset (const struct regcache *regcache,
530 mips64_elf_fpregset_t *fpregsetp, int regno)
96f026fc 531{
ac7936df 532 struct gdbarch *gdbarch = regcache->arch ();
d37eb719 533 gdb_byte *to;
96f026fc 534
2eb4d78b
UW		 535 if ((regno >= gdbarch_fp0_regnum (gdbarch))
536 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
96f026fc 537 {
d37eb719
DJ		 538 /* See mips_linux_o32_sigframe_init for a description of the
539 peculiar FP register layout. */
2eb4d78b 540 if (register_size (gdbarch, regno) == 4)
d37eb719 541 {
2eb4d78b 542 int regi = regno - gdbarch_fp0_regnum (gdbarch);
d37eb719
DJ		 543
544 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 545 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 546 to += 4;
28f5035f 547 regcache_raw_collect (regcache, regno, to);
d37eb719
DJ		 548 }
549 else
550 {
025bb325
MS		 551 to = (gdb_byte *) (*fpregsetp + regno
552 - gdbarch_fp0_regnum (gdbarch));
28f5035f 553 regcache_raw_collect (regcache, regno, to);
d37eb719 554 }
96f026fc 555 }
2eb4d78b 556 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96f026fc 557 {
d37eb719 558 to = (gdb_byte *) (*fpregsetp + 32);
b057297a 559 regcache->raw_collect_integer (regno, to, 4, true);
d37eb719 560 }
2eb4d78b 561 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719 562 {
d37eb719 563 to = (gdb_byte *) (*fpregsetp + 32) + 4;
b057297a 564 regcache->raw_collect_integer (regno, to, 4, true);
96f026fc
KB		 565 }
566 else if (regno == -1)
567 {
568 int regi;
569
570 for (regi = 0; regi < 32; regi++)
3e8c568d 571 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 572 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 573 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 574 mips_regnum (gdbarch)->fp_control_status);
28f5035f 575 mips64_fill_fpregset (regcache, fpregsetp,
7d266584 576 mips_regnum (gdbarch)->fp_implementation_revision);
96f026fc
KB		 577 }
578}
579
50e8a0d5
HZ		 580static void
581mips64_fill_fpregset_wrapper (const struct regset *regset,
582 const struct regcache *regcache,
583 int regnum, void *gregs, size_t len)
584{
1528345d 585 gdb_assert (len >= sizeof (mips64_elf_fpregset_t));
96f026fc 586
50e8a0d5
HZ		 587 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
588}
2aa830e4 589
b7195f27
AA		 590static const struct regset mips_linux_gregset =
591 {
592 NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper
593 };
594
595static const struct regset mips64_linux_gregset =
596 {
597 NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper
598 };
599
600static const struct regset mips_linux_fpregset =
601 {
602 NULL, mips_supply_fpregset_wrapper, mips_fill_fpregset_wrapper
603 };
604
605static const struct regset mips64_linux_fpregset =
606 {
607 NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper
608 };
609
d4036235
AA		 610static void
611mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
612 iterate_over_regset_sections_cb *cb,
613 void *cb_data,
614 const struct regcache *regcache)
2aa830e4 615{
d4036235 616 if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4)
2aa830e4 617 {
d4036235
AA		 618 cb (".reg", sizeof (mips_elf_gregset_t), &mips_linux_gregset,
619 NULL, cb_data);
620 cb (".reg2", sizeof (mips_elf_fpregset_t), &mips_linux_fpregset,
621 NULL, cb_data);
2aa830e4 622 }
d4036235 623 else
2aa830e4 624 {
d4036235
AA		 625 cb (".reg", sizeof (mips64_elf_gregset_t), &mips64_linux_gregset,
626 NULL, cb_data);
627 cb (".reg2", sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset,
628 NULL, cb_data);
2aa830e4 629 }
50e8a0d5 630}
2aa830e4 631
4eb0ad19
DJ		 632static const struct target_desc *
633mips_linux_core_read_description (struct gdbarch *gdbarch,
634 struct target_ops *target,
635 bfd *abfd)
636{
637 asection *section = bfd_get_section_by_name (abfd, ".reg");
638 if (! section)
639 return NULL;
640
641 switch (bfd_section_size (abfd, section))
642 {
643 case sizeof (mips_elf_gregset_t):
644 return mips_tdesc_gp32;
645
646 case sizeof (mips64_elf_gregset_t):
647 return mips_tdesc_gp64;
648
649 default:
650 return NULL;
651 }
652}
653
96f026fc 654
295093a4 655/* Check the code at PC for a dynamic linker lazy resolution stub.
3e5d3a5a
MR		 656 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs"
657 section uniformly since version 2.15. If the pc is in that section,
658 then we are in such a stub. Before that ".stub" was used in 32-bit
659 ELF binaries, however we do not bother checking for that since we
660 have never had and that case should be extremely rare these days.
661 Instead we pattern-match on the code generated by GNU ld. They look
662 like this:
6de918a6
DJ		 663
664 lw t9,0x8010(gp)
665 addu t7,ra
666 jalr t9,ra
667 addiu t8,zero,INDEX
668
3e5d3a5a
MR		 669 (with the appropriate doubleword instructions for N64). As any lazy
670 resolution stubs in microMIPS binaries will always be in a
671 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */
6de918a6
DJ		 672
673static int
3e5d3a5a 674mips_linux_in_dynsym_stub (CORE_ADDR pc)
6de918a6 675{
e362b510 676 gdb_byte buf[28], *p;
6de918a6 677 ULONGEST insn, insn1;
f5656ead
TT		 678 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64);
679 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
6de918a6 680
3e5d3a5a
MR		 681 if (in_mips_stubs_section (pc))
682 return 1;
683
6de918a6
DJ		 684 read_memory (pc - 12, buf, 28);
685
686 if (n64)
687 {
688 /* ld t9,0x8010(gp) */
689 insn1 = 0xdf998010;
690 }
691 else
692 {
693 /* lw t9,0x8010(gp) */
694 insn1 = 0x8f998010;
695 }
696
697 p = buf + 12;
698 while (p >= buf)
699 {
e17a4113 700 insn = extract_unsigned_integer (p, 4, byte_order);
6de918a6
DJ		 701 if (insn == insn1)
702 break;
703 p -= 4;
704 }
705 if (p < buf)
706 return 0;
707
e17a4113 708 insn = extract_unsigned_integer (p + 4, 4, byte_order);
6de918a6
DJ		 709 if (n64)
710 {
93084fcd
SD		 711 /* 'daddu t7,ra' or 'or t7, ra, zero'*/
712 if (insn != 0x03e0782d || insn != 0x03e07825)
6de918a6 713 return 0;
93084fcd 714
6de918a6
DJ		 715 }
716 else
717 {
93084fcd
SD		 718 /* 'addu t7,ra' or 'or t7, ra, zero'*/
719 if (insn != 0x03e07821 || insn != 0x03e07825)
6de918a6 720 return 0;
93084fcd 721
6de918a6 722 }
295093a4 723
e17a4113 724 insn = extract_unsigned_integer (p + 8, 4, byte_order);
6de918a6
DJ		 725 /* jalr t9,ra */
726 if (insn != 0x0320f809)
727 return 0;
728
e17a4113 729 insn = extract_unsigned_integer (p + 12, 4, byte_order);
6de918a6
DJ		 730 if (n64)
731 {
732 /* daddiu t8,zero,0 */
733 if ((insn & 0xffff0000) != 0x64180000)
734 return 0;
735 }
736 else
737 {
738 /* addiu t8,zero,0 */
739 if ((insn & 0xffff0000) != 0x24180000)
740 return 0;
741 }
742
3e5d3a5a 743 return 1;
6de918a6
DJ		 744}
745
295093a4 746/* Return non-zero iff PC belongs to the dynamic linker resolution
db5f024e 747 code, a PLT entry, or a lazy binding stub. */
6de918a6 748
7d522c90 749static int
6de918a6
DJ		 750mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
751{
295093a4 752 /* Check whether PC is in the dynamic linker. This also checks
db5f024e 753 whether it is in the .plt section, used by non-PIC executables. */
7d522c90 754 if (svr4_in_dynsym_resolve_code (pc))
6de918a6
DJ		 755 return 1;
756
3e5d3a5a
MR		 757 /* Likewise for the stubs. They live in the .MIPS.stubs section these
758 days, so we check if the PC is within, than fall back to a pattern
759 match. */
760 if (mips_linux_in_dynsym_stub (pc))
6de918a6
DJ		 761 return 1;
762
763 return 0;
764}
765
766/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
767 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
768 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba 769 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
db5f024e
DJ		 770 "__dl_runtime_resolve" directly. An unresolved lazy binding
771 stub will point to _dl_runtime_resolve, which will first call
c4c5b7ba
AC		 772 __dl_runtime_resolve, and then pass control to the resolved
773 function. */
6de918a6
DJ		 774
775static CORE_ADDR
776mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
777{
3b7344d5 778 struct bound_minimal_symbol resolver;
6de918a6
DJ		 779
780 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
781
77e371c0 782 if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc)
c7ce8faa 783 return frame_unwind_caller_pc (get_current_frame ());
6de918a6 784
db5f024e 785 return glibc_skip_solib_resolver (gdbarch, pc);
295093a4 786}
6de918a6 787
5792a79b
DJ		 788/* Signal trampoline support. There are four supported layouts for a
789 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
790 n64 rt_sigframe. We handle them all independently; not the most
791 efficient way, but simplest. First, declare all the unwinders. */
792
793static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 794 struct frame_info *this_frame,
5792a79b
DJ		 795 struct trad_frame_cache *this_cache,
796 CORE_ADDR func);
797
798static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 799 struct frame_info *this_frame,
5792a79b
DJ		 800 struct trad_frame_cache *this_cache,
801 CORE_ADDR func);
802
858339f2
MR		 803static int mips_linux_sigframe_validate (const struct tramp_frame *self,
804 struct frame_info *this_frame,
805 CORE_ADDR *pc);
806
807static int micromips_linux_sigframe_validate (const struct tramp_frame *self,
808 struct frame_info *this_frame,
809 CORE_ADDR *pc);
810
5792a79b
DJ		 811#define MIPS_NR_LINUX 4000
812#define MIPS_NR_N64_LINUX 5000
813#define MIPS_NR_N32_LINUX 6000
814
815#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
816#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
817#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
818#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
819
820#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
821#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
822#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
823#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
824#define MIPS_INST_SYSCALL 0x0000000c
825
858339f2
MR		 826#define MICROMIPS_INST_LI_V0 0x3040
827#define MICROMIPS_INST_POOL32A 0x0000
828#define MICROMIPS_INST_SYSCALL 0x8b7c
829
2cd8546d
AC		 830static const struct tramp_frame mips_linux_o32_sigframe = {
831 SIGTRAMP_FRAME,
5792a79b 832 4,
2cd8546d
AC		 833 {
834 { MIPS_INST_LI_V0_SIGRETURN, -1 },
835 { MIPS_INST_SYSCALL, -1 },
836 { TRAMP_SENTINEL_INSN, -1 }
837 },
858339f2
MR		 838 mips_linux_o32_sigframe_init,
839 mips_linux_sigframe_validate
5792a79b
DJ		 840};
841
2cd8546d
AC		 842static const struct tramp_frame mips_linux_o32_rt_sigframe = {
843 SIGTRAMP_FRAME,
5792a79b 844 4,
2cd8546d
AC		 845 {
846 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
847 { MIPS_INST_SYSCALL, -1 },
848 { TRAMP_SENTINEL_INSN, -1 } },
858339f2
MR		 849 mips_linux_o32_sigframe_init,
850 mips_linux_sigframe_validate
5792a79b
DJ		 851};
852
2cd8546d
AC		 853static const struct tramp_frame mips_linux_n32_rt_sigframe = {
854 SIGTRAMP_FRAME,
5792a79b 855 4,
2cd8546d
AC		 856 {
857 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
858 { MIPS_INST_SYSCALL, -1 },
859 { TRAMP_SENTINEL_INSN, -1 }
860 },
858339f2
MR		 861 mips_linux_n32n64_sigframe_init,
862 mips_linux_sigframe_validate
5792a79b
DJ		 863};
864
2cd8546d
AC		 865static const struct tramp_frame mips_linux_n64_rt_sigframe = {
866 SIGTRAMP_FRAME,
5792a79b 867 4,
fcbd8a5c
TS		 868 {
869 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
870 { MIPS_INST_SYSCALL, -1 },
871 { TRAMP_SENTINEL_INSN, -1 }
872 },
858339f2
MR		 873 mips_linux_n32n64_sigframe_init,
874 mips_linux_sigframe_validate
875};
876
877static const struct tramp_frame micromips_linux_o32_sigframe = {
878 SIGTRAMP_FRAME,
879 2,
880 {
881 { MICROMIPS_INST_LI_V0, -1 },
882 { MIPS_NR_sigreturn, -1 },
883 { MICROMIPS_INST_POOL32A, -1 },
884 { MICROMIPS_INST_SYSCALL, -1 },
885 { TRAMP_SENTINEL_INSN, -1 }
886 },
887 mips_linux_o32_sigframe_init,
888 micromips_linux_sigframe_validate
889};
890
891static const struct tramp_frame micromips_linux_o32_rt_sigframe = {
892 SIGTRAMP_FRAME,
893 2,
894 {
895 { MICROMIPS_INST_LI_V0, -1 },
896 { MIPS_NR_rt_sigreturn, -1 },
897 { MICROMIPS_INST_POOL32A, -1 },
898 { MICROMIPS_INST_SYSCALL, -1 },
899 { TRAMP_SENTINEL_INSN, -1 }
900 },
901 mips_linux_o32_sigframe_init,
902 micromips_linux_sigframe_validate
903};
904
905static const struct tramp_frame micromips_linux_n32_rt_sigframe = {
906 SIGTRAMP_FRAME,
907 2,
908 {
909 { MICROMIPS_INST_LI_V0, -1 },
910 { MIPS_NR_N32_rt_sigreturn, -1 },
911 { MICROMIPS_INST_POOL32A, -1 },
912 { MICROMIPS_INST_SYSCALL, -1 },
913 { TRAMP_SENTINEL_INSN, -1 }
914 },
915 mips_linux_n32n64_sigframe_init,
916 micromips_linux_sigframe_validate
917};
918
919static const struct tramp_frame micromips_linux_n64_rt_sigframe = {
920 SIGTRAMP_FRAME,
921 2,
922 {
923 { MICROMIPS_INST_LI_V0, -1 },
924 { MIPS_NR_N64_rt_sigreturn, -1 },
925 { MICROMIPS_INST_POOL32A, -1 },
926 { MICROMIPS_INST_SYSCALL, -1 },
927 { TRAMP_SENTINEL_INSN, -1 }
928 },
929 mips_linux_n32n64_sigframe_init,
930 micromips_linux_sigframe_validate
5792a79b
DJ		 931};
932
933/* *INDENT-OFF* */
934/* The unwinder for o32 signal frames. The legacy structures look
935 like this:
936
937 struct sigframe {
938 u32 sf_ass[4]; [argument save space for o32]
eb195664 939 u32 sf_code[2]; [signal trampoline or fill]
5792a79b
DJ		 940 struct sigcontext sf_sc;
941 sigset_t sf_mask;
942 };
943
d0e64392
MR		 944 Pre-2.6.12 sigcontext:
945
5792a79b
DJ		 946 struct sigcontext {
947 unsigned int sc_regmask; [Unused]
948 unsigned int sc_status;
949 unsigned long long sc_pc;
950 unsigned long long sc_regs[32];
951 unsigned long long sc_fpregs[32];
952 unsigned int sc_ownedfp;
953 unsigned int sc_fpc_csr;
954 unsigned int sc_fpc_eir; [Unused]
955 unsigned int sc_used_math;
956 unsigned int sc_ssflags; [Unused]
957 [Alignment hole of four bytes]
958 unsigned long long sc_mdhi;
959 unsigned long long sc_mdlo;
960
961 unsigned int sc_cause; [Unused]
962 unsigned int sc_badvaddr; [Unused]
963
964 unsigned long sc_sigset[4]; [kernel's sigset_t]
965 };
966
d0e64392
MR		 967 Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
968
969 struct sigcontext {
970 unsigned int sc_regmask; [Unused]
971 unsigned int sc_status; [Unused]
972 unsigned long long sc_pc;
973 unsigned long long sc_regs[32];
974 unsigned long long sc_fpregs[32];
975 unsigned int sc_acx;
976 unsigned int sc_fpc_csr;
977 unsigned int sc_fpc_eir; [Unused]
978 unsigned int sc_used_math;
979 unsigned int sc_dsp;
980 [Alignment hole of four bytes]
981 unsigned long long sc_mdhi;
982 unsigned long long sc_mdlo;
983 unsigned long sc_hi1;
984 unsigned long sc_lo1;
985 unsigned long sc_hi2;
986 unsigned long sc_lo2;
987 unsigned long sc_hi3;
988 unsigned long sc_lo3;
989 };
990
5792a79b
DJ		 991 The RT signal frames look like this:
992
993 struct rt_sigframe {
994 u32 rs_ass[4]; [argument save space for o32]
eb195664 995 u32 rs_code[2] [signal trampoline or fill]
5792a79b
DJ		 996 struct siginfo rs_info;
997 struct ucontext rs_uc;
998 };
999
1000 struct ucontext {
1001 unsigned long uc_flags;
1002 struct ucontext *uc_link;
1003 stack_t uc_stack;
1004 [Alignment hole of four bytes]
1005 struct sigcontext uc_mcontext;
1006 sigset_t uc_sigmask;
1007 }; */
1008/* *INDENT-ON* */
1009
5792a79b
DJ		 1010#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
1011
1012#define RTSIGFRAME_SIGINFO_SIZE 128
1013#define STACK_T_SIZE (3 * 4)
1014#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
1015#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1016 + RTSIGFRAME_SIGINFO_SIZE \
1017 + UCONTEXT_SIGCONTEXT_OFFSET)
1018
1019#define SIGCONTEXT_PC (1 * 8)
1020#define SIGCONTEXT_REGS (2 * 8)
1021#define SIGCONTEXT_FPREGS (34 * 8)
1022#define SIGCONTEXT_FPCSR (66 * 8 + 4)
d0e64392 1023#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
5792a79b
DJ		 1024#define SIGCONTEXT_HI (69 * 8)
1025#define SIGCONTEXT_LO (70 * 8)
1026#define SIGCONTEXT_CAUSE (71 * 8 + 0)
1027#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
d0e64392
MR		 1028#define SIGCONTEXT_HI1 (71 * 8 + 0)
1029#define SIGCONTEXT_LO1 (71 * 8 + 4)
1030#define SIGCONTEXT_HI2 (72 * 8 + 0)
1031#define SIGCONTEXT_LO2 (72 * 8 + 4)
1032#define SIGCONTEXT_HI3 (73 * 8 + 0)
1033#define SIGCONTEXT_LO3 (73 * 8 + 4)
5792a79b
DJ		 1034
1035#define SIGCONTEXT_REG_SIZE 8
1036
1037static void
1038mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 1039 struct frame_info *this_frame,
5792a79b
DJ		 1040 struct trad_frame_cache *this_cache,
1041 CORE_ADDR func)
1042{
b8a22b94 1043 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1044 int ireg;
eb195664
DD		 1045 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1046 CORE_ADDR sigcontext_base;
2eb4d78b 1047 const struct mips_regnum *regs = mips_regnum (gdbarch);
37c4d197 1048 CORE_ADDR regs_base;
5792a79b 1049
858339f2
MR		 1050 if (self == &mips_linux_o32_sigframe
1051 || self == &micromips_linux_o32_sigframe)
eb195664 1052 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1053 else
eb195664 1054 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 1055
1056 /* I'm not proud of this hack. Eventually we will have the
1057 infrastructure to indicate the size of saved registers on a
1058 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 1059 bytes but we only want four. Use regs_base to access any
1060 64-bit fields. */
2eb4d78b 1061 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
37c4d197
DJ		 1062 regs_base = sigcontext_base + 4;
1063 else
1064 regs_base = sigcontext_base;
5792a79b 1065
2eb4d78b 1066 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1067 trad_frame_set_reg_addr (this_cache,
1068 (MIPS_RESTART_REGNUM
2eb4d78b 1069 + gdbarch_num_regs (gdbarch)),
822b6570 1070 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 1071
1072 for (ireg = 1; ireg < 32; ireg++)
295093a4 1073 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1074 (ireg + MIPS_ZERO_REGNUM
1075 + gdbarch_num_regs (gdbarch)),
1076 (regs_base + SIGCONTEXT_REGS
1077 + ireg * SIGCONTEXT_REG_SIZE));
5792a79b 1078
37c4d197
DJ		 1079 /* The way that floating point registers are saved, unfortunately,
1080 depends on the architecture the kernel is built for. For the r3000 and
1081 tx39, four bytes of each register are at the beginning of each of the
1082 32 eight byte slots. For everything else, the registers are saved
1083 using double precision; only the even-numbered slots are initialized,
1084 and the high bits are the odd-numbered register. Assume the latter
1085 layout, since we can't tell, and it's much more common. Which bits are
1086 the "high" bits depends on endianness. */
5792a79b 1087 for (ireg = 0; ireg < 32; ireg++)
2eb4d78b 1088 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
f57d151a 1089 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1090 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1091 (sigcontext_base + SIGCONTEXT_FPREGS + 4
1092 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
37c4d197 1093 else
f57d151a 1094 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1095 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1096 (sigcontext_base + SIGCONTEXT_FPREGS
1097 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
5792a79b 1098
f57d151a 1099 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1100 regs->pc + gdbarch_num_regs (gdbarch),
37c4d197 1101 regs_base + SIGCONTEXT_PC);
5792a79b 1102
295093a4 1103 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1104 (regs->fp_control_status
1105 + gdbarch_num_regs (gdbarch)),
5792a79b 1106 sigcontext_base + SIGCONTEXT_FPCSR);
d0e64392
MR		 1107
1108 if (regs->dspctl != -1)
1109 trad_frame_set_reg_addr (this_cache,
1110 regs->dspctl + gdbarch_num_regs (gdbarch),
1111 sigcontext_base + SIGCONTEXT_DSPCTL);
1112
f57d151a 1113 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1114 regs->hi + gdbarch_num_regs (gdbarch),
37c4d197 1115 regs_base + SIGCONTEXT_HI);
f57d151a 1116 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1117 regs->lo + gdbarch_num_regs (gdbarch),
37c4d197 1118 regs_base + SIGCONTEXT_LO);
d0e64392
MR		 1119
1120 if (regs->dspacc != -1)
1121 {
1122 trad_frame_set_reg_addr (this_cache,
1123 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1124 sigcontext_base + SIGCONTEXT_HI1);
1125 trad_frame_set_reg_addr (this_cache,
1126 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1127 sigcontext_base + SIGCONTEXT_LO1);
1128 trad_frame_set_reg_addr (this_cache,
1129 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1130 sigcontext_base + SIGCONTEXT_HI2);
1131 trad_frame_set_reg_addr (this_cache,
1132 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1133 sigcontext_base + SIGCONTEXT_LO2);
1134 trad_frame_set_reg_addr (this_cache,
1135 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1136 sigcontext_base + SIGCONTEXT_HI3);
1137 trad_frame_set_reg_addr (this_cache,
1138 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1139 sigcontext_base + SIGCONTEXT_LO3);
1140 }
1141 else
1142 {
1143 trad_frame_set_reg_addr (this_cache,
1144 regs->cause + gdbarch_num_regs (gdbarch),
1145 sigcontext_base + SIGCONTEXT_CAUSE);
1146 trad_frame_set_reg_addr (this_cache,
1147 regs->badvaddr + gdbarch_num_regs (gdbarch),
1148 sigcontext_base + SIGCONTEXT_BADVADDR);
1149 }
5792a79b
DJ		 1150
1151 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1152 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1153}
1154
1155/* *INDENT-OFF* */
1156/* For N32/N64 things look different. There is no non-rt signal frame.
1157
1158 struct rt_sigframe_n32 {
1159 u32 rs_ass[4]; [ argument save space for o32 ]
eb195664 1160 u32 rs_code[2]; [ signal trampoline or fill ]
5792a79b
DJ		 1161 struct siginfo rs_info;
1162 struct ucontextn32 rs_uc;
1163 };
1164
1165 struct ucontextn32 {
1166 u32 uc_flags;
1167 s32 uc_link;
1168 stack32_t uc_stack;
1169 struct sigcontext uc_mcontext;
1170 sigset_t uc_sigmask; [ mask last for extensibility ]
1171 };
295093a4 1172
e741f4d4 1173 struct rt_sigframe {
5792a79b
DJ		 1174 u32 rs_ass[4]; [ argument save space for o32 ]
1175 u32 rs_code[2]; [ signal trampoline ]
1176 struct siginfo rs_info;
1177 struct ucontext rs_uc;
1178 };
1179
1180 struct ucontext {
1181 unsigned long uc_flags;
1182 struct ucontext *uc_link;
1183 stack_t uc_stack;
1184 struct sigcontext uc_mcontext;
1185 sigset_t uc_sigmask; [ mask last for extensibility ]
1186 };
1187
1188 And the sigcontext is different (this is for both n32 and n64):
1189
1190 struct sigcontext {
1191 unsigned long long sc_regs[32];
1192 unsigned long long sc_fpregs[32];
1193 unsigned long long sc_mdhi;
e741f4d4
DJ		 1194 unsigned long long sc_hi1;
1195 unsigned long long sc_hi2;
1196 unsigned long long sc_hi3;
5792a79b 1197 unsigned long long sc_mdlo;
e741f4d4
DJ		 1198 unsigned long long sc_lo1;
1199 unsigned long long sc_lo2;
1200 unsigned long long sc_lo3;
5792a79b 1201 unsigned long long sc_pc;
5792a79b 1202 unsigned int sc_fpc_csr;
5792a79b 1203 unsigned int sc_used_math;
e741f4d4
DJ		 1204 unsigned int sc_dsp;
1205 unsigned int sc_reserved;
1206 };
1207
1208 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1209 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1210 included too. */
5792a79b
DJ		 1211/* *INDENT-ON* */
1212
1213#define N32_STACK_T_SIZE STACK_T_SIZE
1214#define N64_STACK_T_SIZE (2 * 8 + 4)
1215#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1216#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1217#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1218 + RTSIGFRAME_SIGINFO_SIZE \
1219 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1220#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1221 + RTSIGFRAME_SIGINFO_SIZE \
1222 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1223
1224#define N64_SIGCONTEXT_REGS (0 * 8)
1225#define N64_SIGCONTEXT_FPREGS (32 * 8)
1226#define N64_SIGCONTEXT_HI (64 * 8)
d0e64392
MR		 1227#define N64_SIGCONTEXT_HI1 (65 * 8)
1228#define N64_SIGCONTEXT_HI2 (66 * 8)
1229#define N64_SIGCONTEXT_HI3 (67 * 8)
e741f4d4 1230#define N64_SIGCONTEXT_LO (68 * 8)
d0e64392
MR		 1231#define N64_SIGCONTEXT_LO1 (69 * 8)
1232#define N64_SIGCONTEXT_LO2 (70 * 8)
1233#define N64_SIGCONTEXT_LO3 (71 * 8)
e741f4d4 1234#define N64_SIGCONTEXT_PC (72 * 8)
d0e64392
MR		 1235#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
1236#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
5792a79b
DJ		 1237
1238#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1239
5792a79b
DJ		 1240static void
1241mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 1242 struct frame_info *this_frame,
5792a79b
DJ		 1243 struct trad_frame_cache *this_cache,
1244 CORE_ADDR func)
1245{
b8a22b94 1246 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1247 int ireg;
eb195664
DD		 1248 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1249 CORE_ADDR sigcontext_base;
2eb4d78b 1250 const struct mips_regnum *regs = mips_regnum (gdbarch);
5792a79b 1251
858339f2
MR		 1252 if (self == &mips_linux_n32_rt_sigframe
1253 || self == &micromips_linux_n32_rt_sigframe)
eb195664 1254 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1255 else
eb195664 1256 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1257
2eb4d78b 1258 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1259 trad_frame_set_reg_addr (this_cache,
1260 (MIPS_RESTART_REGNUM
2eb4d78b 1261 + gdbarch_num_regs (gdbarch)),
822b6570 1262 sigcontext_base + N64_SIGCONTEXT_REGS);
5792a79b
DJ		 1263
1264 for (ireg = 1; ireg < 32; ireg++)
295093a4 1265 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1266 (ireg + MIPS_ZERO_REGNUM
1267 + gdbarch_num_regs (gdbarch)),
1268 (sigcontext_base + N64_SIGCONTEXT_REGS
1269 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b
DJ		 1270
1271 for (ireg = 0; ireg < 32; ireg++)
f57d151a 1272 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1273 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1274 (sigcontext_base + N64_SIGCONTEXT_FPREGS
1275 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b 1276
f57d151a 1277 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1278 regs->pc + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1279 sigcontext_base + N64_SIGCONTEXT_PC);
1280
295093a4 1281 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1282 (regs->fp_control_status
1283 + gdbarch_num_regs (gdbarch)),
5792a79b 1284 sigcontext_base + N64_SIGCONTEXT_FPCSR);
d0e64392 1285
f57d151a 1286 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1287 regs->hi + gdbarch_num_regs (gdbarch),
5792a79b 1288 sigcontext_base + N64_SIGCONTEXT_HI);
f57d151a 1289 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1290 regs->lo + gdbarch_num_regs (gdbarch),
5792a79b 1291 sigcontext_base + N64_SIGCONTEXT_LO);
5792a79b 1292
d0e64392
MR		 1293 if (regs->dspacc != -1)
1294 {
1295 trad_frame_set_reg_addr (this_cache,
1296 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1297 sigcontext_base + N64_SIGCONTEXT_HI1);
1298 trad_frame_set_reg_addr (this_cache,
1299 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1300 sigcontext_base + N64_SIGCONTEXT_LO1);
1301 trad_frame_set_reg_addr (this_cache,
1302 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1303 sigcontext_base + N64_SIGCONTEXT_HI2);
1304 trad_frame_set_reg_addr (this_cache,
1305 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1306 sigcontext_base + N64_SIGCONTEXT_LO2);
1307 trad_frame_set_reg_addr (this_cache,
1308 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1309 sigcontext_base + N64_SIGCONTEXT_HI3);
1310 trad_frame_set_reg_addr (this_cache,
1311 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1312 sigcontext_base + N64_SIGCONTEXT_LO3);
1313 }
1314 if (regs->dspctl != -1)
1315 trad_frame_set_reg_addr (this_cache,
1316 regs->dspctl + gdbarch_num_regs (gdbarch),
1317 sigcontext_base + N64_SIGCONTEXT_DSPCTL);
1318
5792a79b 1319 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1320 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1321}
1322
858339f2
MR		 1323/* Implement struct tramp_frame's "validate" method for standard MIPS code. */
1324
1325static int
1326mips_linux_sigframe_validate (const struct tramp_frame *self,
1327 struct frame_info *this_frame,
1328 CORE_ADDR *pc)
1329{
1330 return mips_pc_is_mips (*pc);
1331}
1332
1333/* Implement struct tramp_frame's "validate" method for microMIPS code. */
1334
1335static int
1336micromips_linux_sigframe_validate (const struct tramp_frame *self,
1337 struct frame_info *this_frame,
1338 CORE_ADDR *pc)
1339{
3e29f34a
MR		 1340 if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc))
1341 {
1342 *pc = mips_unmake_compact_addr (*pc);
1343 return 1;
1344 }
1345 else
1346 return 0;
858339f2
MR		 1347}
1348
5a439849
MR		 1349/* Implement the "write_pc" gdbarch method. */
1350
822b6570 1351static void
61a1198a 1352mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
822b6570 1353{
ac7936df 1354 struct gdbarch *gdbarch = regcache->arch ();
5a439849
MR		 1355
1356 mips_write_pc (regcache, pc);
822b6570
DJ		 1357
1358 /* Clear the syscall restart flag. */
2eb4d78b 1359 if (mips_linux_restart_reg_p (gdbarch))
61a1198a 1360 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
822b6570
DJ		 1361}
1362
1363/* Return 1 if MIPS_RESTART_REGNUM is usable. */
1364
1365int
1366mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1367{
1368 /* If we do not have a target description with registers, then
1369 MIPS_RESTART_REGNUM will not be included in the register set. */
1370 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1371 return 0;
1372
1373 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1374 either be GPR-sized or missing. */
1375 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1376}
9f62d0e2 1377
e38d4e1a
DJ		 1378/* When FRAME is at a syscall instruction, return the PC of the next
1379 instruction to be executed. */
1380
63807e1d 1381static CORE_ADDR
e38d4e1a
DJ		 1382mips_linux_syscall_next_pc (struct frame_info *frame)
1383{
1384 CORE_ADDR pc = get_frame_pc (frame);
1385 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1386
1387 /* If we are about to make a sigreturn syscall, use the unwinder to
1388 decode the signal frame. */
1389 if (v0 == MIPS_NR_sigreturn
1390 || v0 == MIPS_NR_rt_sigreturn
1391 || v0 == MIPS_NR_N64_rt_sigreturn
1392 || v0 == MIPS_NR_N32_rt_sigreturn)
c7ce8faa 1393 return frame_unwind_caller_pc (get_current_frame ());
e38d4e1a
DJ		 1394
1395 return pc + 4;
1396}
1397
385203ed
DD		 1398/* Return the current system call's number present in the
1399 v0 register. When the function fails, it returns -1. */
1400
1401static LONGEST
1402mips_linux_get_syscall_number (struct gdbarch *gdbarch,
1403 ptid_t ptid)
1404{
1405 struct regcache *regcache = get_thread_regcache (ptid);
1406 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1407 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1408 int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
1409 /* The content of a register */
1410 gdb_byte buf[8];
1411 /* The result */
1412 LONGEST ret;
1413
1414 /* Make sure we're in a known ABI */
1415 gdb_assert (tdep->mips_abi == MIPS_ABI_O32
1416 || tdep->mips_abi == MIPS_ABI_N32
1417 || tdep->mips_abi == MIPS_ABI_N64);
1418
1419 gdb_assert (regsize <= sizeof (buf));
1420
1421 /* Getting the system call number from the register.
1422 syscall number is in v0 or $2. */
1423 regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
1424
1425 ret = extract_signed_integer (buf, regsize, byte_order);
1426
1427 return ret;
1428}
1429
eb14d406
SDJ		 1430/* Implementation of `gdbarch_gdb_signal_to_target', as defined in
1431 gdbarch.h. */
1432
1433static int
1434mips_gdb_signal_to_target (struct gdbarch *gdbarch,
1435 enum gdb_signal signal)
1436{
1437 switch (signal)
1438 {
1439 case GDB_SIGNAL_EMT:
1440 return MIPS_LINUX_SIGEMT;
1441
1442 case GDB_SIGNAL_BUS:
1443 return MIPS_LINUX_SIGBUS;
1444
1445 case GDB_SIGNAL_SYS:
1446 return MIPS_LINUX_SIGSYS;
1447
1448 case GDB_SIGNAL_USR1:
1449 return MIPS_LINUX_SIGUSR1;
1450
1451 case GDB_SIGNAL_USR2:
1452 return MIPS_LINUX_SIGUSR2;
1453
1454 case GDB_SIGNAL_CHLD:
1455 return MIPS_LINUX_SIGCHLD;
1456
1457 case GDB_SIGNAL_PWR:
1458 return MIPS_LINUX_SIGPWR;
1459
1460 case GDB_SIGNAL_WINCH:
1461 return MIPS_LINUX_SIGWINCH;
1462
1463 case GDB_SIGNAL_URG:
1464 return MIPS_LINUX_SIGURG;
1465
1466 case GDB_SIGNAL_IO:
1467 return MIPS_LINUX_SIGIO;
1468
1469 case GDB_SIGNAL_POLL:
1470 return MIPS_LINUX_SIGPOLL;
1471
1472 case GDB_SIGNAL_STOP:
1473 return MIPS_LINUX_SIGSTOP;
1474
1475 case GDB_SIGNAL_TSTP:
1476 return MIPS_LINUX_SIGTSTP;
1477
1478 case GDB_SIGNAL_CONT:
1479 return MIPS_LINUX_SIGCONT;
1480
1481 case GDB_SIGNAL_TTIN:
1482 return MIPS_LINUX_SIGTTIN;
1483
1484 case GDB_SIGNAL_TTOU:
1485 return MIPS_LINUX_SIGTTOU;
1486
1487 case GDB_SIGNAL_VTALRM:
1488 return MIPS_LINUX_SIGVTALRM;
1489
1490 case GDB_SIGNAL_PROF:
1491 return MIPS_LINUX_SIGPROF;
1492
1493 case GDB_SIGNAL_XCPU:
1494 return MIPS_LINUX_SIGXCPU;
1495
1496 case GDB_SIGNAL_XFSZ:
1497 return MIPS_LINUX_SIGXFSZ;
1498
1499 /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>,
1500 therefore we have to handle it here. */
1501 case GDB_SIGNAL_REALTIME_32:
1502 return MIPS_LINUX_SIGRTMIN;
1503 }
1504
1505 if (signal >= GDB_SIGNAL_REALTIME_33
1506 && signal <= GDB_SIGNAL_REALTIME_63)
1507 {
1508 int offset = signal - GDB_SIGNAL_REALTIME_33;
1509
1510 return MIPS_LINUX_SIGRTMIN + 1 + offset;
1511 }
1512 else if (signal >= GDB_SIGNAL_REALTIME_64
1513 && signal <= GDB_SIGNAL_REALTIME_127)
1514 {
1515 int offset = signal - GDB_SIGNAL_REALTIME_64;
1516
1517 return MIPS_LINUX_SIGRT64 + offset;
1518 }
1519
1520 return linux_gdb_signal_to_target (gdbarch, signal);
1521}
1522
7d266584 1523/* Translate signals based on MIPS signal values.
232b8704
ME		 1524 Adapted from gdb/common/signals.c. */
1525
1526static enum gdb_signal
eb14d406 1527mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal)
232b8704 1528{
eb14d406 1529 switch (signal)
232b8704 1530 {
eb14d406 1531 case MIPS_LINUX_SIGEMT:
232b8704 1532 return GDB_SIGNAL_EMT;
eb14d406
SDJ		 1533
1534 case MIPS_LINUX_SIGBUS:
232b8704 1535 return GDB_SIGNAL_BUS;
eb14d406
SDJ		 1536
1537 case MIPS_LINUX_SIGSYS:
232b8704 1538 return GDB_SIGNAL_SYS;
eb14d406
SDJ		 1539
1540 case MIPS_LINUX_SIGUSR1:
232b8704 1541 return GDB_SIGNAL_USR1;
eb14d406
SDJ		 1542
1543 case MIPS_LINUX_SIGUSR2:
232b8704 1544 return GDB_SIGNAL_USR2;
eb14d406
SDJ		 1545
1546 case MIPS_LINUX_SIGCHLD:
232b8704 1547 return GDB_SIGNAL_CHLD;
eb14d406
SDJ		 1548
1549 case MIPS_LINUX_SIGPWR:
232b8704 1550 return GDB_SIGNAL_PWR;
eb14d406
SDJ		 1551
1552 case MIPS_LINUX_SIGWINCH:
232b8704 1553 return GDB_SIGNAL_WINCH;
eb14d406
SDJ		 1554
1555 case MIPS_LINUX_SIGURG:
232b8704 1556 return GDB_SIGNAL_URG;
eb14d406
SDJ		 1557
1558 /* No way to differentiate between SIGIO and SIGPOLL.
1559 Therefore, we just handle the first one. */
1560 case MIPS_LINUX_SIGIO:
1561 return GDB_SIGNAL_IO;
1562
1563 case MIPS_LINUX_SIGSTOP:
232b8704 1564 return GDB_SIGNAL_STOP;
eb14d406
SDJ		 1565
1566 case MIPS_LINUX_SIGTSTP:
232b8704 1567 return GDB_SIGNAL_TSTP;
eb14d406
SDJ		 1568
1569 case MIPS_LINUX_SIGCONT:
232b8704 1570 return GDB_SIGNAL_CONT;
eb14d406
SDJ		 1571
1572 case MIPS_LINUX_SIGTTIN:
232b8704 1573 return GDB_SIGNAL_TTIN;
eb14d406
SDJ		 1574
1575 case MIPS_LINUX_SIGTTOU:
232b8704 1576 return GDB_SIGNAL_TTOU;
eb14d406
SDJ		 1577
1578 case MIPS_LINUX_SIGVTALRM:
232b8704 1579 return GDB_SIGNAL_VTALRM;
eb14d406
SDJ		 1580
1581 case MIPS_LINUX_SIGPROF:
232b8704 1582 return GDB_SIGNAL_PROF;
eb14d406
SDJ		 1583
1584 case MIPS_LINUX_SIGXCPU:
232b8704 1585 return GDB_SIGNAL_XCPU;
eb14d406
SDJ		 1586
1587 case MIPS_LINUX_SIGXFSZ:
232b8704 1588 return GDB_SIGNAL_XFSZ;
eb14d406 1589 }
232b8704 1590
eb14d406 1591 if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX)
232b8704
ME		 1592 {
1593 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
1594 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
eb14d406
SDJ		 1595 int offset = signal - MIPS_LINUX_SIGRTMIN;
1596
1597 if (offset == 0)
232b8704 1598 return GDB_SIGNAL_REALTIME_32;
eb14d406
SDJ		 1599 else if (offset < 32)
1600 return (enum gdb_signal) (offset - 1
1601 + (int) GDB_SIGNAL_REALTIME_33);
232b8704 1602 else
eb14d406
SDJ		 1603 return (enum gdb_signal) (offset - 32
1604 + (int) GDB_SIGNAL_REALTIME_64);
232b8704
ME		 1605 }
1606
eb14d406 1607 return linux_gdb_signal_from_target (gdbarch, signal);
232b8704
ME		 1608}
1609
5792a79b
DJ		 1610/* Initialize one of the GNU/Linux OS ABIs. */
1611
19ed69dd 1612static void
295093a4
MS		 1613mips_linux_init_abi (struct gdbarch_info info,
1614 struct gdbarch *gdbarch)
19ed69dd 1615{
96f026fc
KB		 1616 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1617 enum mips_abi abi = mips_abi (gdbarch);
0dba2a6c 1618 struct tdesc_arch_data *tdesc_data = info.tdesc_data;
96f026fc 1619
a5ee0f0c
PA		 1620 linux_init_abi (info, gdbarch);
1621
385203ed
DD		 1622 /* Get the syscall number from the arch's register. */
1623 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
1624
96f026fc
KB		 1625 switch (abi)
1626 {
1627 case MIPS_ABI_O32:
1628 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1629 mips_linux_get_longjmp_target);
96f026fc 1630 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1631 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
858339f2
MR		 1632 tramp_frame_prepend_unwinder (gdbarch, &micromips_linux_o32_sigframe);
1633 tramp_frame_prepend_unwinder (gdbarch,
1634 &micromips_linux_o32_rt_sigframe);
fb2be677
AC		 1635 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1636 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
458c8db8 1637 set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml");
96f026fc
KB		 1638 break;
1639 case MIPS_ABI_N32:
1640 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1641 mips_linux_get_longjmp_target);
96f026fc 1642 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1643 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
d05f6826
DJ		 1644 set_gdbarch_long_double_bit (gdbarch, 128);
1645 /* These floatformats should probably be renamed. MIPS uses
1646 the same 128-bit IEEE floating point format that IA-64 uses,
1647 except that the quiet/signalling NaN bit is reversed (GDB
1648 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1649 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
858339f2
MR		 1650 tramp_frame_prepend_unwinder (gdbarch,
1651 &micromips_linux_n32_rt_sigframe);
fb2be677 1652 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
458c8db8 1653 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml");
96f026fc
KB		 1654 break;
1655 case MIPS_ABI_N64:
1656 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1657 mips64_linux_get_longjmp_target);
96f026fc 1658 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1659 (gdbarch, svr4_lp64_fetch_link_map_offsets);
d05f6826
DJ		 1660 set_gdbarch_long_double_bit (gdbarch, 128);
1661 /* These floatformats should probably be renamed. MIPS uses
1662 the same 128-bit IEEE floating point format that IA-64 uses,
1663 except that the quiet/signalling NaN bit is reversed (GDB
1664 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1665 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
858339f2
MR		 1666 tramp_frame_prepend_unwinder (gdbarch,
1667 &micromips_linux_n64_rt_sigframe);
fb2be677 1668 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
458c8db8 1669 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml");
96f026fc
KB		 1670 break;
1671 default:
96f026fc
KB		 1672 break;
1673 }
6de918a6
DJ		 1674
1675 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1676
0d0266c6 1677 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1678
1679 /* Enable TLS support. */
1680 set_gdbarch_fetch_tls_load_module_address (gdbarch,
7d266584 1681 svr4_fetch_objfile_link_map);
7d522c90
DJ		 1682
1683 /* Initialize this lazily, to avoid an initialization order
1684 dependency on solib-svr4.c's _initialize routine. */
1685 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1686 {
1687 mips_svr4_so_ops = svr4_so_ops;
1688 mips_svr4_so_ops.in_dynsym_resolve_code
1689 = mips_linux_in_dynsym_resolve_code;
1690 }
1691 set_solib_ops (gdbarch, &mips_svr4_so_ops);
822b6570
DJ		 1692
1693 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1694
4eb0ad19
DJ		 1695 set_gdbarch_core_read_description (gdbarch,
1696 mips_linux_core_read_description);
1697
d4036235
AA		 1698 set_gdbarch_iterate_over_regset_sections
1699 (gdbarch, mips_linux_iterate_over_regset_sections);
50e8a0d5 1700
232b8704
ME		 1701 set_gdbarch_gdb_signal_from_target (gdbarch,
1702 mips_gdb_signal_from_target);
1703
eb14d406
SDJ		 1704 set_gdbarch_gdb_signal_to_target (gdbarch,
1705 mips_gdb_signal_to_target);
1706
e38d4e1a
DJ		 1707 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1708
822b6570
DJ		 1709 if (tdesc_data)
1710 {
1711 const struct tdesc_feature *feature;
1712
1713 /* If we have target-described registers, then we can safely
1714 reserve a number for MIPS_RESTART_REGNUM (whether it is
1715 described or not). */
1716 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1717 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
cf233303 1718 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
822b6570
DJ		 1719
1720 /* If it's present, then assign it to the reserved number. */
1721 feature = tdesc_find_feature (info.target_desc,
1722 "org.gnu.gdb.mips.linux");
1723 if (feature != NULL)
1724 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1725 "restart");
1726 }
19ed69dd
KB		 1727}
1728
2aa830e4 1729void
d1bacddc 1730_initialize_mips_linux_tdep (void)
2aa830e4 1731{
96f026fc
KB		 1732 const struct bfd_arch_info *arch_info;
1733
96f026fc
KB		 1734 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1735 arch_info != NULL;
1736 arch_info = arch_info->next)
1737 {
295093a4
MS		 1738 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1739 GDB_OSABI_LINUX,
96f026fc
KB		 1740 mips_linux_init_abi);
1741 }
032bb6ea
YQ		 1742
1743 /* Initialize the standard target descriptions. */
1744 initialize_tdesc_mips_linux ();
1745 initialize_tdesc_mips_dsp_linux ();
1746 initialize_tdesc_mips64_linux ();
1747 initialize_tdesc_mips64_dsp_linux ();
2aa830e4 1748}
GDB Binutils - Deliverables
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