Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
2aa830e4 DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
2aa830e4 DJ |
22 | |
23 | #include "defs.h" | |
24 | #include "gdbcore.h" | |
25 | #include "target.h" | |
26 | #include "solib-svr4.h" | |
19ed69dd | 27 | #include "osabi.h" |
96f026fc | 28 | #include "mips-tdep.h" |
19ed69dd | 29 | #include "gdb_string.h" |
96f026fc | 30 | #include "gdb_assert.h" |
6de918a6 | 31 | #include "frame.h" |
2fdf551c | 32 | #include "regcache.h" |
5792a79b DJ |
33 | #include "trad-frame.h" |
34 | #include "tramp-frame.h" | |
e6bb342a | 35 | #include "gdbtypes.h" |
5ea03926 | 36 | #include "solib.h" |
7d522c90 DJ |
37 | #include "solib-svr4.h" |
38 | #include "solist.h" | |
982e9687 | 39 | #include "symtab.h" |
d37eb719 | 40 | #include "mips-linux-tdep.h" |
2aa830e4 | 41 | |
7d522c90 DJ |
42 | static struct target_so_ops mips_svr4_so_ops; |
43 | ||
2aa830e4 | 44 | /* Figure out where the longjmp will land. |
295093a4 MS |
45 | We expect the first arg to be a pointer to the jmp_buf structure |
46 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
47 | at. The pc is copied into PC. This routine returns 1 on | |
48 | success. */ | |
2aa830e4 | 49 | |
19ed69dd KB |
50 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
51 | #define MIPS_LINUX_JB_PC 0 | |
52 | ||
53 | static int | |
2aa830e4 DJ |
54 | mips_linux_get_longjmp_target (CORE_ADDR *pc) |
55 | { | |
56 | CORE_ADDR jb_addr; | |
819844ad | 57 | char buf[gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 58 | |
613e114f | 59 | jb_addr = read_register (MIPS_A0_REGNUM); |
2aa830e4 | 60 | |
bf072999 | 61 | if (target_read_memory (jb_addr |
819844ad UW |
62 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
63 | buf, | |
64 | gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) | |
2aa830e4 DJ |
65 | return 0; |
66 | ||
819844ad UW |
67 | *pc = extract_unsigned_integer (buf, |
68 | gdbarch_ptr_bit (current_gdbarch) | |
69 | / TARGET_CHAR_BIT); | |
2aa830e4 DJ |
70 | |
71 | return 1; | |
72 | } | |
73 | ||
4246e332 | 74 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
75 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
76 | is 8. */ | |
96f026fc KB |
77 | |
78 | static void | |
28f5035f | 79 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 80 | { |
d37eb719 | 81 | gdb_byte buf[MAX_REGISTER_SIZE]; |
3acba339 | 82 | store_signed_integer (buf, register_size (current_gdbarch, regnum), |
96f026fc | 83 | extract_signed_integer (addr, 4)); |
28f5035f | 84 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
85 | } |
86 | ||
2aa830e4 DJ |
87 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
88 | ||
d37eb719 | 89 | void |
28f5035f UW |
90 | mips_supply_gregset (struct regcache *regcache, |
91 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
92 | { |
93 | int regi; | |
28f5035f | 94 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 95 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 96 | |
d9d9c31f | 97 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
98 | |
99 | for (regi = EF_REG0; regi <= EF_REG31; regi++) | |
28f5035f | 100 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 101 | |
28f5035f UW |
102 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->lo, |
103 | regp + EF_LO); | |
104 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
105 | regp + EF_HI); | |
56cea623 | 106 | |
28f5035f UW |
107 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->pc, |
108 | regp + EF_CP0_EPC); | |
109 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
110 | regp + EF_CP0_BADVADDR); | |
111 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
112 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
113 | regp + EF_CP0_CAUSE); | |
2aa830e4 DJ |
114 | |
115 | /* Fill inaccessible registers with zero. */ | |
28f5035f | 116 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 MS |
117 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
118 | regi < MIPS_LAST_EMBED_REGNUM; | |
119 | regi++) | |
28f5035f | 120 | regcache_raw_supply (regcache, regi, zerobuf); |
2aa830e4 DJ |
121 | } |
122 | ||
123 | /* Pack our registers (or one register) into an elf_gregset_t. */ | |
124 | ||
d37eb719 | 125 | void |
28f5035f UW |
126 | mips_fill_gregset (const struct regcache *regcache, |
127 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 DJ |
128 | { |
129 | int regaddr, regi; | |
d37eb719 | 130 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 131 | void *dst; |
2aa830e4 DJ |
132 | |
133 | if (regno == -1) | |
134 | { | |
d37eb719 | 135 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
2aa830e4 | 136 | for (regi = 0; regi < 32; regi++) |
28f5035f UW |
137 | mips_fill_gregset (regcache, gregsetp, regi); |
138 | mips_fill_gregset (regcache, gregsetp, | |
139 | mips_regnum (current_gdbarch)->lo); | |
140 | mips_fill_gregset (regcache, gregsetp, | |
141 | mips_regnum (current_gdbarch)->hi); | |
142 | mips_fill_gregset (regcache, gregsetp, | |
143 | mips_regnum (current_gdbarch)->pc); | |
144 | mips_fill_gregset (regcache, gregsetp, | |
145 | mips_regnum (current_gdbarch)->badvaddr); | |
146 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); | |
147 | mips_fill_gregset (regcache, gregsetp, | |
148 | mips_regnum (current_gdbarch)->cause); | |
2aa830e4 DJ |
149 | return; |
150 | } | |
151 | ||
152 | if (regno < 32) | |
153 | { | |
2aa830e4 | 154 | dst = regp + regno + EF_REG0; |
28f5035f | 155 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
156 | return; |
157 | } | |
158 | ||
56cea623 AC |
159 | if (regno == mips_regnum (current_gdbarch)->lo) |
160 | regaddr = EF_LO; | |
161 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
162 | regaddr = EF_HI; | |
163 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
164 | regaddr = EF_CP0_EPC; | |
165 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
166 | regaddr = EF_CP0_BADVADDR; | |
24e05951 | 167 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
168 | regaddr = EF_CP0_STATUS; |
169 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
170 | regaddr = EF_CP0_CAUSE; | |
171 | else | |
172 | regaddr = -1; | |
2aa830e4 DJ |
173 | |
174 | if (regaddr != -1) | |
175 | { | |
2aa830e4 | 176 | dst = regp + regaddr; |
28f5035f | 177 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
178 | } |
179 | } | |
180 | ||
181 | /* Likewise, unpack an elf_fpregset_t. */ | |
182 | ||
d37eb719 | 183 | void |
28f5035f UW |
184 | mips_supply_fpregset (struct regcache *regcache, |
185 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 186 | { |
52f0bd74 | 187 | int regi; |
d9d9c31f | 188 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 189 | |
d9d9c31f | 190 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
191 | |
192 | for (regi = 0; regi < 32; regi++) | |
28f5035f | 193 | regcache_raw_supply (regcache, FP0_REGNUM + regi, *fpregsetp + regi); |
2aa830e4 | 194 | |
28f5035f | 195 | regcache_raw_supply (regcache, |
23a6d369 | 196 | mips_regnum (current_gdbarch)->fp_control_status, |
28f5035f | 197 | *fpregsetp + 32); |
2aa830e4 | 198 | |
295093a4 | 199 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 200 | regcache_raw_supply (regcache, |
23a6d369 AC |
201 | mips_regnum (current_gdbarch)->fp_implementation_revision, |
202 | zerobuf); | |
2aa830e4 DJ |
203 | } |
204 | ||
205 | /* Likewise, pack one or all floating point registers into an | |
206 | elf_fpregset_t. */ | |
207 | ||
d37eb719 | 208 | void |
28f5035f UW |
209 | mips_fill_fpregset (const struct regcache *regcache, |
210 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 DJ |
211 | { |
212 | char *from, *to; | |
213 | ||
214 | if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32)) | |
215 | { | |
2aa830e4 | 216 | to = (char *) (*fpregsetp + regno - FP0_REGNUM); |
28f5035f | 217 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 218 | } |
56cea623 | 219 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
2aa830e4 | 220 | { |
2aa830e4 | 221 | to = (char *) (*fpregsetp + 32); |
28f5035f | 222 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
223 | } |
224 | else if (regno == -1) | |
225 | { | |
226 | int regi; | |
227 | ||
228 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
229 | mips_fill_fpregset (regcache, fpregsetp, FP0_REGNUM + regi); |
230 | mips_fill_fpregset (regcache, fpregsetp, | |
9f62d0e2 | 231 | mips_regnum (current_gdbarch)->fp_control_status); |
2aa830e4 DJ |
232 | } |
233 | } | |
234 | ||
96f026fc KB |
235 | /* Support for 64-bit ABIs. */ |
236 | ||
96f026fc | 237 | /* Figure out where the longjmp will land. |
295093a4 MS |
238 | We expect the first arg to be a pointer to the jmp_buf structure |
239 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
240 | at. The pc is copied into PC. This routine returns 1 on | |
241 | success. */ | |
96f026fc KB |
242 | |
243 | /* Details about jmp_buf. */ | |
244 | ||
245 | #define MIPS64_LINUX_JB_PC 0 | |
246 | ||
247 | static int | |
248 | mips64_linux_get_longjmp_target (CORE_ADDR *pc) | |
249 | { | |
250 | CORE_ADDR jb_addr; | |
819844ad UW |
251 | void *buf = alloca (gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT); |
252 | int element_size = gdbarch_ptr_bit (current_gdbarch) == 32 ? 4 : 8; | |
96f026fc | 253 | |
613e114f | 254 | jb_addr = read_register (MIPS_A0_REGNUM); |
96f026fc KB |
255 | |
256 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad UW |
257 | buf, |
258 | gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) | |
96f026fc KB |
259 | return 0; |
260 | ||
819844ad UW |
261 | *pc = extract_unsigned_integer (buf, |
262 | gdbarch_ptr_bit (current_gdbarch) | |
263 | / TARGET_CHAR_BIT); | |
96f026fc KB |
264 | |
265 | return 1; | |
266 | } | |
267 | ||
d37eb719 DJ |
268 | /* Register set support functions. These operate on standard 64-bit |
269 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
270 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
271 | ||
272 | /* Supply a 64-bit register. */ | |
96f026fc | 273 | |
d37eb719 | 274 | void |
28f5035f UW |
275 | supply_64bit_reg (struct regcache *regcache, int regnum, |
276 | const gdb_byte *buf) | |
d37eb719 DJ |
277 | { |
278 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG | |
279 | && register_size (current_gdbarch, regnum) == 4) | |
28f5035f | 280 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 281 | else |
28f5035f | 282 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
283 | } |
284 | ||
285 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
286 | ||
287 | void | |
28f5035f UW |
288 | mips64_supply_gregset (struct regcache *regcache, |
289 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
290 | { |
291 | int regi; | |
28f5035f | 292 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 293 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
96f026fc | 294 | |
d9d9c31f | 295 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc KB |
296 | |
297 | for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++) | |
28f5035f UW |
298 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
299 | (const gdb_byte *)(regp + regi)); | |
300 | ||
301 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->lo, | |
302 | (const gdb_byte *) (regp + MIPS64_EF_LO)); | |
303 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->hi, | |
304 | (const gdb_byte *) (regp + MIPS64_EF_HI)); | |
305 | ||
306 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->pc, | |
307 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); | |
308 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, | |
309 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); | |
310 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
311 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
312 | supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->cause, | |
313 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); | |
96f026fc KB |
314 | |
315 | /* Fill inaccessible registers with zero. */ | |
28f5035f | 316 | regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); |
295093a4 MS |
317 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
318 | regi < MIPS_LAST_EMBED_REGNUM; | |
319 | regi++) | |
28f5035f | 320 | regcache_raw_supply (regcache, regi, zerobuf); |
96f026fc KB |
321 | } |
322 | ||
d37eb719 | 323 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 324 | |
d37eb719 | 325 | void |
28f5035f UW |
326 | mips64_fill_gregset (const struct regcache *regcache, |
327 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc KB |
328 | { |
329 | int regaddr, regi; | |
330 | mips64_elf_greg_t *regp = *gregsetp; | |
331 | void *src, *dst; | |
332 | ||
333 | if (regno == -1) | |
334 | { | |
335 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
336 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
337 | mips64_fill_gregset (regcache, gregsetp, regi); |
338 | mips64_fill_gregset (regcache, gregsetp, | |
339 | mips_regnum (current_gdbarch)->lo); | |
340 | mips64_fill_gregset (regcache, gregsetp, | |
341 | mips_regnum (current_gdbarch)->hi); | |
342 | mips64_fill_gregset (regcache, gregsetp, | |
343 | mips_regnum (current_gdbarch)->pc); | |
344 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 345 | mips_regnum (current_gdbarch)->badvaddr); |
28f5035f UW |
346 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
347 | mips64_fill_gregset (regcache, gregsetp, | |
295093a4 | 348 | mips_regnum (current_gdbarch)->cause); |
96f026fc KB |
349 | return; |
350 | } | |
351 | ||
352 | if (regno < 32) | |
d37eb719 DJ |
353 | regaddr = regno + MIPS64_EF_REG0; |
354 | else if (regno == mips_regnum (current_gdbarch)->lo) | |
56cea623 AC |
355 | regaddr = MIPS64_EF_LO; |
356 | else if (regno == mips_regnum (current_gdbarch)->hi) | |
357 | regaddr = MIPS64_EF_HI; | |
358 | else if (regno == mips_regnum (current_gdbarch)->pc) | |
359 | regaddr = MIPS64_EF_CP0_EPC; | |
360 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) | |
361 | regaddr = MIPS64_EF_CP0_BADVADDR; | |
24e05951 | 362 | else if (regno == MIPS_PS_REGNUM) |
56cea623 AC |
363 | regaddr = MIPS64_EF_CP0_STATUS; |
364 | else if (regno == mips_regnum (current_gdbarch)->cause) | |
365 | regaddr = MIPS64_EF_CP0_CAUSE; | |
366 | else | |
367 | regaddr = -1; | |
96f026fc KB |
368 | |
369 | if (regaddr != -1) | |
370 | { | |
d37eb719 DJ |
371 | gdb_byte buf[MAX_REGISTER_SIZE]; |
372 | LONGEST val; | |
373 | ||
28f5035f | 374 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
375 | val = extract_signed_integer (buf, |
376 | register_size (current_gdbarch, regno)); | |
96f026fc | 377 | dst = regp + regaddr; |
d37eb719 | 378 | store_signed_integer (dst, 8, val); |
96f026fc KB |
379 | } |
380 | } | |
381 | ||
382 | /* Likewise, unpack an elf_fpregset_t. */ | |
383 | ||
d37eb719 | 384 | void |
28f5035f UW |
385 | mips64_supply_fpregset (struct regcache *regcache, |
386 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 387 | { |
52f0bd74 | 388 | int regi; |
96f026fc | 389 | |
d37eb719 DJ |
390 | /* See mips_linux_o32_sigframe_init for a description of the |
391 | peculiar FP register layout. */ | |
392 | if (register_size (current_gdbarch, FP0_REGNUM) == 4) | |
393 | for (regi = 0; regi < 32; regi++) | |
394 | { | |
28f5035f | 395 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
4c6b5505 UW |
396 | if ((gdbarch_byte_order (current_gdbarch) |
397 | == BFD_ENDIAN_BIG) != (regi & 1)) | |
d37eb719 | 398 | reg_ptr += 4; |
28f5035f | 399 | regcache_raw_supply (regcache, FP0_REGNUM + regi, reg_ptr); |
d37eb719 DJ |
400 | } |
401 | else | |
402 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
403 | regcache_raw_supply (regcache, FP0_REGNUM + regi, |
404 | (const char *)(*fpregsetp + regi)); | |
d37eb719 | 405 | |
28f5035f UW |
406 | supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->fp_control_status, |
407 | (const gdb_byte *)(*fpregsetp + 32)); | |
d37eb719 DJ |
408 | |
409 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
410 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
411 | can do is to assume that its value is present. */ | |
28f5035f UW |
412 | supply_32bit_reg (regcache, |
413 | mips_regnum (current_gdbarch)->fp_implementation_revision, | |
414 | (const gdb_byte *)(*fpregsetp + 32) + 4); | |
96f026fc KB |
415 | } |
416 | ||
417 | /* Likewise, pack one or all floating point registers into an | |
418 | elf_fpregset_t. */ | |
419 | ||
d37eb719 | 420 | void |
28f5035f UW |
421 | mips64_fill_fpregset (const struct regcache *regcache, |
422 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 423 | { |
d37eb719 | 424 | gdb_byte *to; |
96f026fc KB |
425 | |
426 | if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32)) | |
427 | { | |
d37eb719 DJ |
428 | /* See mips_linux_o32_sigframe_init for a description of the |
429 | peculiar FP register layout. */ | |
430 | if (register_size (current_gdbarch, regno) == 4) | |
431 | { | |
432 | int regi = regno - FP0_REGNUM; | |
433 | ||
434 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
4c6b5505 UW |
435 | if ((gdbarch_byte_order (current_gdbarch) |
436 | == BFD_ENDIAN_BIG) != (regi & 1)) | |
d37eb719 | 437 | to += 4; |
28f5035f | 438 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
439 | } |
440 | else | |
441 | { | |
442 | to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM); | |
28f5035f | 443 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 444 | } |
96f026fc | 445 | } |
56cea623 | 446 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
96f026fc | 447 | { |
d37eb719 DJ |
448 | gdb_byte buf[MAX_REGISTER_SIZE]; |
449 | LONGEST val; | |
450 | ||
28f5035f | 451 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
452 | val = extract_signed_integer (buf, |
453 | register_size (current_gdbarch, regno)); | |
454 | to = (gdb_byte *) (*fpregsetp + 32); | |
455 | store_signed_integer (to, 4, val); | |
456 | } | |
457 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) | |
458 | { | |
459 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
460 | LONGEST val; | |
461 | ||
28f5035f | 462 | regcache_raw_collect (regcache, regno, buf); |
d37eb719 DJ |
463 | val = extract_signed_integer (buf, |
464 | register_size (current_gdbarch, regno)); | |
465 | to = (gdb_byte *) (*fpregsetp + 32) + 4; | |
466 | store_signed_integer (to, 4, val); | |
96f026fc KB |
467 | } |
468 | else if (regno == -1) | |
469 | { | |
470 | int regi; | |
471 | ||
472 | for (regi = 0; regi < 32; regi++) | |
28f5035f UW |
473 | mips64_fill_fpregset (regcache, fpregsetp, FP0_REGNUM + regi); |
474 | mips64_fill_fpregset (regcache, fpregsetp, | |
d37eb719 | 475 | mips_regnum (current_gdbarch)->fp_control_status); |
28f5035f UW |
476 | mips64_fill_fpregset (regcache, fpregsetp, |
477 | (mips_regnum (current_gdbarch) | |
478 | ->fp_implementation_revision)); | |
96f026fc KB |
479 | } |
480 | } | |
481 | ||
482 | ||
2aa830e4 DJ |
483 | /* Use a local version of this function to get the correct types for |
484 | regsets, until multi-arch core support is ready. */ | |
485 | ||
486 | static void | |
9eefc95f UW |
487 | fetch_core_registers (struct regcache *regcache, |
488 | char *core_reg_sect, unsigned core_reg_size, | |
2aa830e4 DJ |
489 | int which, CORE_ADDR reg_addr) |
490 | { | |
d37eb719 DJ |
491 | mips_elf_gregset_t gregset; |
492 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
493 | mips64_elf_gregset_t gregset64; |
494 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 DJ |
495 | |
496 | if (which == 0) | |
497 | { | |
96f026fc | 498 | if (core_reg_size == sizeof (gregset)) |
2aa830e4 | 499 | { |
96f026fc | 500 | memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); |
9eefc95f | 501 | mips_supply_gregset (regcache, |
28f5035f | 502 | (const mips_elf_gregset_t *) &gregset); |
96f026fc KB |
503 | } |
504 | else if (core_reg_size == sizeof (gregset64)) | |
505 | { | |
506 | memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64)); | |
9eefc95f | 507 | mips64_supply_gregset (regcache, |
28f5035f | 508 | (const mips64_elf_gregset_t *) &gregset64); |
2aa830e4 DJ |
509 | } |
510 | else | |
511 | { | |
8a3fe4f8 | 512 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
513 | } |
514 | } | |
515 | else if (which == 2) | |
516 | { | |
96f026fc | 517 | if (core_reg_size == sizeof (fpregset)) |
2aa830e4 | 518 | { |
96f026fc | 519 | memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); |
9eefc95f | 520 | mips_supply_fpregset (regcache, |
28f5035f | 521 | (const mips_elf_fpregset_t *) &fpregset); |
96f026fc KB |
522 | } |
523 | else if (core_reg_size == sizeof (fpregset64)) | |
524 | { | |
295093a4 MS |
525 | memcpy ((char *) &fpregset64, core_reg_sect, |
526 | sizeof (fpregset64)); | |
9eefc95f | 527 | mips64_supply_fpregset (regcache, |
28f5035f | 528 | (const mips64_elf_fpregset_t *) &fpregset64); |
2aa830e4 DJ |
529 | } |
530 | else | |
531 | { | |
8a3fe4f8 | 532 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
533 | } |
534 | } | |
535 | } | |
536 | ||
537 | /* Register that we are able to handle ELF file formats using standard | |
538 | procfs "regset" structures. */ | |
539 | ||
540 | static struct core_fns regset_core_fns = | |
541 | { | |
542 | bfd_target_elf_flavour, /* core_flavour */ | |
543 | default_check_format, /* check_format */ | |
544 | default_core_sniffer, /* core_sniffer */ | |
545 | fetch_core_registers, /* core_read_registers */ | |
546 | NULL /* next */ | |
547 | }; | |
548 | ||
96f026fc | 549 | |
295093a4 MS |
550 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
551 | Because they aren't in the .plt section, we pattern-match on the | |
552 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
553 | |
554 | lw t9,0x8010(gp) | |
555 | addu t7,ra | |
556 | jalr t9,ra | |
557 | addiu t8,zero,INDEX | |
558 | ||
295093a4 MS |
559 | (with the appropriate doubleword instructions for N64). Also |
560 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
561 | |
562 | static int | |
563 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
564 | { | |
565 | unsigned char buf[28], *p; | |
566 | ULONGEST insn, insn1; | |
567 | int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64); | |
568 | ||
569 | read_memory (pc - 12, buf, 28); | |
570 | ||
571 | if (n64) | |
572 | { | |
573 | /* ld t9,0x8010(gp) */ | |
574 | insn1 = 0xdf998010; | |
575 | } | |
576 | else | |
577 | { | |
578 | /* lw t9,0x8010(gp) */ | |
579 | insn1 = 0x8f998010; | |
580 | } | |
581 | ||
582 | p = buf + 12; | |
583 | while (p >= buf) | |
584 | { | |
585 | insn = extract_unsigned_integer (p, 4); | |
586 | if (insn == insn1) | |
587 | break; | |
588 | p -= 4; | |
589 | } | |
590 | if (p < buf) | |
591 | return 0; | |
592 | ||
593 | insn = extract_unsigned_integer (p + 4, 4); | |
594 | if (n64) | |
595 | { | |
596 | /* daddu t7,ra */ | |
597 | if (insn != 0x03e0782d) | |
598 | return 0; | |
599 | } | |
600 | else | |
601 | { | |
602 | /* addu t7,ra */ | |
603 | if (insn != 0x03e07821) | |
604 | return 0; | |
605 | } | |
295093a4 | 606 | |
6de918a6 DJ |
607 | insn = extract_unsigned_integer (p + 8, 4); |
608 | /* jalr t9,ra */ | |
609 | if (insn != 0x0320f809) | |
610 | return 0; | |
611 | ||
612 | insn = extract_unsigned_integer (p + 12, 4); | |
613 | if (n64) | |
614 | { | |
615 | /* daddiu t8,zero,0 */ | |
616 | if ((insn & 0xffff0000) != 0x64180000) | |
617 | return 0; | |
618 | } | |
619 | else | |
620 | { | |
621 | /* addiu t8,zero,0 */ | |
622 | if ((insn & 0xffff0000) != 0x24180000) | |
623 | return 0; | |
624 | } | |
625 | ||
626 | return (insn & 0xffff); | |
627 | } | |
628 | ||
295093a4 MS |
629 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
630 | code or to a stub. */ | |
6de918a6 | 631 | |
7d522c90 | 632 | static int |
6de918a6 DJ |
633 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
634 | { | |
295093a4 MS |
635 | /* Check whether PC is in the dynamic linker. This also checks |
636 | whether it is in the .plt section, which MIPS does not use. */ | |
7d522c90 | 637 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
638 | return 1; |
639 | ||
295093a4 MS |
640 | /* Pattern match for the stub. It would be nice if there were a |
641 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
642 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
643 | return 1; | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
649 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
650 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba AC |
651 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
652 | "__dl_runtime_resolve" directly. An unresolved PLT entry will | |
653 | point to _dl_runtime_resolve, which will first call | |
654 | __dl_runtime_resolve, and then pass control to the resolved | |
655 | function. */ | |
6de918a6 DJ |
656 | |
657 | static CORE_ADDR | |
658 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
659 | { | |
660 | struct minimal_symbol *resolver; | |
661 | ||
662 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
663 | ||
664 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
295093a4 | 665 | return frame_pc_unwind (get_current_frame ()); |
6de918a6 DJ |
666 | |
667 | return 0; | |
295093a4 | 668 | } |
6de918a6 | 669 | |
5792a79b DJ |
670 | /* Signal trampoline support. There are four supported layouts for a |
671 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
672 | n64 rt_sigframe. We handle them all independently; not the most | |
673 | efficient way, but simplest. First, declare all the unwinders. */ | |
674 | ||
675 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
676 | struct frame_info *next_frame, | |
677 | struct trad_frame_cache *this_cache, | |
678 | CORE_ADDR func); | |
679 | ||
680 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
681 | struct frame_info *next_frame, | |
682 | struct trad_frame_cache *this_cache, | |
683 | CORE_ADDR func); | |
684 | ||
685 | #define MIPS_NR_LINUX 4000 | |
686 | #define MIPS_NR_N64_LINUX 5000 | |
687 | #define MIPS_NR_N32_LINUX 6000 | |
688 | ||
689 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
690 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
691 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
692 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
693 | ||
694 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
695 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
696 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
697 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
698 | #define MIPS_INST_SYSCALL 0x0000000c | |
699 | ||
2cd8546d AC |
700 | static const struct tramp_frame mips_linux_o32_sigframe = { |
701 | SIGTRAMP_FRAME, | |
5792a79b | 702 | 4, |
2cd8546d AC |
703 | { |
704 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
705 | { MIPS_INST_SYSCALL, -1 }, | |
706 | { TRAMP_SENTINEL_INSN, -1 } | |
707 | }, | |
5792a79b DJ |
708 | mips_linux_o32_sigframe_init |
709 | }; | |
710 | ||
2cd8546d AC |
711 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
712 | SIGTRAMP_FRAME, | |
5792a79b | 713 | 4, |
2cd8546d AC |
714 | { |
715 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
716 | { MIPS_INST_SYSCALL, -1 }, | |
717 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
718 | mips_linux_o32_sigframe_init |
719 | }; | |
720 | ||
2cd8546d AC |
721 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
722 | SIGTRAMP_FRAME, | |
5792a79b | 723 | 4, |
2cd8546d AC |
724 | { |
725 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
726 | { MIPS_INST_SYSCALL, -1 }, | |
727 | { TRAMP_SENTINEL_INSN, -1 } | |
728 | }, | |
5792a79b DJ |
729 | mips_linux_n32n64_sigframe_init |
730 | }; | |
731 | ||
2cd8546d AC |
732 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
733 | SIGTRAMP_FRAME, | |
5792a79b | 734 | 4, |
fcbd8a5c TS |
735 | { |
736 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
737 | { MIPS_INST_SYSCALL, -1 }, | |
738 | { TRAMP_SENTINEL_INSN, -1 } | |
739 | }, | |
5792a79b DJ |
740 | mips_linux_n32n64_sigframe_init |
741 | }; | |
742 | ||
743 | /* *INDENT-OFF* */ | |
744 | /* The unwinder for o32 signal frames. The legacy structures look | |
745 | like this: | |
746 | ||
747 | struct sigframe { | |
748 | u32 sf_ass[4]; [argument save space for o32] | |
749 | u32 sf_code[2]; [signal trampoline] | |
750 | struct sigcontext sf_sc; | |
751 | sigset_t sf_mask; | |
752 | }; | |
753 | ||
754 | struct sigcontext { | |
755 | unsigned int sc_regmask; [Unused] | |
756 | unsigned int sc_status; | |
757 | unsigned long long sc_pc; | |
758 | unsigned long long sc_regs[32]; | |
759 | unsigned long long sc_fpregs[32]; | |
760 | unsigned int sc_ownedfp; | |
761 | unsigned int sc_fpc_csr; | |
762 | unsigned int sc_fpc_eir; [Unused] | |
763 | unsigned int sc_used_math; | |
764 | unsigned int sc_ssflags; [Unused] | |
765 | [Alignment hole of four bytes] | |
766 | unsigned long long sc_mdhi; | |
767 | unsigned long long sc_mdlo; | |
768 | ||
769 | unsigned int sc_cause; [Unused] | |
770 | unsigned int sc_badvaddr; [Unused] | |
771 | ||
772 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
773 | }; | |
774 | ||
775 | The RT signal frames look like this: | |
776 | ||
777 | struct rt_sigframe { | |
778 | u32 rs_ass[4]; [argument save space for o32] | |
779 | u32 rs_code[2] [signal trampoline] | |
780 | struct siginfo rs_info; | |
781 | struct ucontext rs_uc; | |
782 | }; | |
783 | ||
784 | struct ucontext { | |
785 | unsigned long uc_flags; | |
786 | struct ucontext *uc_link; | |
787 | stack_t uc_stack; | |
788 | [Alignment hole of four bytes] | |
789 | struct sigcontext uc_mcontext; | |
790 | sigset_t uc_sigmask; | |
791 | }; */ | |
792 | /* *INDENT-ON* */ | |
793 | ||
794 | #define SIGFRAME_CODE_OFFSET (4 * 4) | |
795 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) | |
796 | ||
797 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
798 | #define STACK_T_SIZE (3 * 4) | |
799 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
800 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
801 | + RTSIGFRAME_SIGINFO_SIZE \ | |
802 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
803 | ||
804 | #define SIGCONTEXT_PC (1 * 8) | |
805 | #define SIGCONTEXT_REGS (2 * 8) | |
806 | #define SIGCONTEXT_FPREGS (34 * 8) | |
807 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
808 | #define SIGCONTEXT_HI (69 * 8) | |
809 | #define SIGCONTEXT_LO (70 * 8) | |
810 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
811 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
812 | ||
813 | #define SIGCONTEXT_REG_SIZE 8 | |
814 | ||
815 | static void | |
816 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
817 | struct frame_info *next_frame, | |
818 | struct trad_frame_cache *this_cache, | |
819 | CORE_ADDR func) | |
820 | { | |
821 | int ireg, reg_position; | |
822 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
823 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
37c4d197 | 824 | CORE_ADDR regs_base; |
5792a79b DJ |
825 | |
826 | if (self == &mips_linux_o32_sigframe) | |
827 | sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET; | |
828 | else | |
829 | sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 MS |
830 | |
831 | /* I'm not proud of this hack. Eventually we will have the | |
832 | infrastructure to indicate the size of saved registers on a | |
833 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
834 | bytes but we only want four. Use regs_base to access any |
835 | 64-bit fields. */ | |
4c6b5505 | 836 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
837 | regs_base = sigcontext_base + 4; |
838 | else | |
839 | regs_base = sigcontext_base; | |
5792a79b DJ |
840 | |
841 | #if 0 | |
f57d151a UW |
842 | trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM |
843 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 844 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
845 | #endif |
846 | ||
847 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 848 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
849 | ireg + MIPS_ZERO_REGNUM |
850 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 851 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
852 | + ireg * SIGCONTEXT_REG_SIZE); |
853 | ||
37c4d197 DJ |
854 | /* The way that floating point registers are saved, unfortunately, |
855 | depends on the architecture the kernel is built for. For the r3000 and | |
856 | tx39, four bytes of each register are at the beginning of each of the | |
857 | 32 eight byte slots. For everything else, the registers are saved | |
858 | using double precision; only the even-numbered slots are initialized, | |
859 | and the high bits are the odd-numbered register. Assume the latter | |
860 | layout, since we can't tell, and it's much more common. Which bits are | |
861 | the "high" bits depends on endianness. */ | |
5792a79b | 862 | for (ireg = 0; ireg < 32; ireg++) |
4c6b5505 | 863 | if ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a UW |
864 | trad_frame_set_reg_addr (this_cache, |
865 | ireg + regs->fp0 + | |
866 | gdbarch_num_regs (current_gdbarch), | |
37c4d197 DJ |
867 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
868 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
869 | else | |
f57d151a UW |
870 | trad_frame_set_reg_addr (this_cache, |
871 | ireg + regs->fp0 | |
872 | + gdbarch_num_regs (current_gdbarch), | |
37c4d197 DJ |
873 | sigcontext_base + SIGCONTEXT_FPREGS |
874 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b | 875 | |
f57d151a UW |
876 | trad_frame_set_reg_addr (this_cache, |
877 | regs->pc + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 878 | regs_base + SIGCONTEXT_PC); |
5792a79b | 879 | |
295093a4 | 880 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
881 | regs->fp_control_status |
882 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 883 | sigcontext_base + SIGCONTEXT_FPCSR); |
f57d151a UW |
884 | trad_frame_set_reg_addr (this_cache, |
885 | regs->hi + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 886 | regs_base + SIGCONTEXT_HI); |
f57d151a UW |
887 | trad_frame_set_reg_addr (this_cache, |
888 | regs->lo + gdbarch_num_regs (current_gdbarch), | |
37c4d197 | 889 | regs_base + SIGCONTEXT_LO); |
f57d151a UW |
890 | trad_frame_set_reg_addr (this_cache, |
891 | regs->cause + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 892 | sigcontext_base + SIGCONTEXT_CAUSE); |
f57d151a UW |
893 | trad_frame_set_reg_addr (this_cache, |
894 | regs->badvaddr + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
895 | sigcontext_base + SIGCONTEXT_BADVADDR); |
896 | ||
897 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
898 | trad_frame_set_id (this_cache, | |
295093a4 MS |
899 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
900 | func)); | |
5792a79b DJ |
901 | } |
902 | ||
903 | /* *INDENT-OFF* */ | |
904 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
905 | ||
906 | struct rt_sigframe_n32 { | |
907 | u32 rs_ass[4]; [ argument save space for o32 ] | |
908 | u32 rs_code[2]; [ signal trampoline ] | |
909 | struct siginfo rs_info; | |
910 | struct ucontextn32 rs_uc; | |
911 | }; | |
912 | ||
913 | struct ucontextn32 { | |
914 | u32 uc_flags; | |
915 | s32 uc_link; | |
916 | stack32_t uc_stack; | |
917 | struct sigcontext uc_mcontext; | |
918 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
919 | }; | |
295093a4 | 920 | |
5792a79b DJ |
921 | struct rt_sigframe_n32 { |
922 | u32 rs_ass[4]; [ argument save space for o32 ] | |
923 | u32 rs_code[2]; [ signal trampoline ] | |
924 | struct siginfo rs_info; | |
925 | struct ucontext rs_uc; | |
926 | }; | |
927 | ||
928 | struct ucontext { | |
929 | unsigned long uc_flags; | |
930 | struct ucontext *uc_link; | |
931 | stack_t uc_stack; | |
932 | struct sigcontext uc_mcontext; | |
933 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
934 | }; | |
935 | ||
936 | And the sigcontext is different (this is for both n32 and n64): | |
937 | ||
938 | struct sigcontext { | |
939 | unsigned long long sc_regs[32]; | |
940 | unsigned long long sc_fpregs[32]; | |
941 | unsigned long long sc_mdhi; | |
942 | unsigned long long sc_mdlo; | |
943 | unsigned long long sc_pc; | |
944 | unsigned int sc_status; | |
945 | unsigned int sc_fpc_csr; | |
946 | unsigned int sc_fpc_eir; | |
947 | unsigned int sc_used_math; | |
948 | unsigned int sc_cause; | |
949 | unsigned int sc_badvaddr; | |
950 | }; */ | |
951 | /* *INDENT-ON* */ | |
952 | ||
953 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
954 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
955 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
956 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
957 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
958 | + RTSIGFRAME_SIGINFO_SIZE \ | |
959 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
960 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
961 | + RTSIGFRAME_SIGINFO_SIZE \ | |
962 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
963 | ||
964 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
965 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
966 | #define N64_SIGCONTEXT_HI (64 * 8) | |
967 | #define N64_SIGCONTEXT_LO (65 * 8) | |
968 | #define N64_SIGCONTEXT_PC (66 * 8) | |
969 | #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4) | |
970 | #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4) | |
971 | #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4) | |
972 | #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4) | |
973 | ||
974 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 975 | |
5792a79b DJ |
976 | static void |
977 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
978 | struct frame_info *next_frame, | |
979 | struct trad_frame_cache *this_cache, | |
980 | CORE_ADDR func) | |
981 | { | |
982 | int ireg, reg_position; | |
983 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; | |
984 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); | |
985 | ||
986 | if (self == &mips_linux_n32_rt_sigframe) | |
987 | sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET; | |
988 | else | |
989 | sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET; | |
295093a4 | 990 | |
5792a79b | 991 | #if 0 |
f57d151a UW |
992 | trad_frame_set_reg_addr (this_cache, |
993 | ORIG_ZERO_REGNUM | |
994 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
995 | sigcontext_base + N64_SIGCONTEXT_REGS); |
996 | #endif | |
997 | ||
998 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 999 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
1000 | ireg + MIPS_ZERO_REGNUM |
1001 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1002 | sigcontext_base + N64_SIGCONTEXT_REGS |
1003 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1004 | ||
1005 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a UW |
1006 | trad_frame_set_reg_addr (this_cache, |
1007 | ireg + regs->fp0 | |
1008 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1009 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
1010 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1011 | ||
f57d151a UW |
1012 | trad_frame_set_reg_addr (this_cache, |
1013 | regs->pc + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1014 | sigcontext_base + N64_SIGCONTEXT_PC); |
1015 | ||
295093a4 | 1016 | trad_frame_set_reg_addr (this_cache, |
f57d151a UW |
1017 | regs->fp_control_status |
1018 | + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1019 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
f57d151a UW |
1020 | trad_frame_set_reg_addr (this_cache, |
1021 | regs->hi + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1022 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a UW |
1023 | trad_frame_set_reg_addr (this_cache, |
1024 | regs->lo + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1025 | sigcontext_base + N64_SIGCONTEXT_LO); |
f57d151a UW |
1026 | trad_frame_set_reg_addr (this_cache, |
1027 | regs->cause + gdbarch_num_regs (current_gdbarch), | |
5792a79b | 1028 | sigcontext_base + N64_SIGCONTEXT_CAUSE); |
f57d151a UW |
1029 | trad_frame_set_reg_addr (this_cache, |
1030 | regs->badvaddr + gdbarch_num_regs (current_gdbarch), | |
5792a79b DJ |
1031 | sigcontext_base + N64_SIGCONTEXT_BADVADDR); |
1032 | ||
1033 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
1034 | trad_frame_set_id (this_cache, | |
295093a4 MS |
1035 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
1036 | func)); | |
5792a79b DJ |
1037 | } |
1038 | ||
9f62d0e2 | 1039 | |
5792a79b DJ |
1040 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1041 | ||
19ed69dd | 1042 | static void |
295093a4 MS |
1043 | mips_linux_init_abi (struct gdbarch_info info, |
1044 | struct gdbarch *gdbarch) | |
19ed69dd | 1045 | { |
96f026fc KB |
1046 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1047 | enum mips_abi abi = mips_abi (gdbarch); | |
1048 | ||
1049 | switch (abi) | |
1050 | { | |
1051 | case MIPS_ABI_O32: | |
1052 | set_gdbarch_get_longjmp_target (gdbarch, | |
1053 | mips_linux_get_longjmp_target); | |
1054 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1055 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1056 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1057 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
96f026fc KB |
1058 | break; |
1059 | case MIPS_ABI_N32: | |
1060 | set_gdbarch_get_longjmp_target (gdbarch, | |
1061 | mips_linux_get_longjmp_target); | |
1062 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1063 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1064 | set_gdbarch_long_double_bit (gdbarch, 128); |
1065 | /* These floatformats should probably be renamed. MIPS uses | |
1066 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1067 | except that the quiet/signalling NaN bit is reversed (GDB | |
1068 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1069 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1070 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
96f026fc KB |
1071 | break; |
1072 | case MIPS_ABI_N64: | |
1073 | set_gdbarch_get_longjmp_target (gdbarch, | |
1074 | mips64_linux_get_longjmp_target); | |
1075 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1076 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1077 | set_gdbarch_long_double_bit (gdbarch, 128); |
1078 | /* These floatformats should probably be renamed. MIPS uses | |
1079 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1080 | except that the quiet/signalling NaN bit is reversed (GDB | |
1081 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1082 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1083 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
96f026fc KB |
1084 | break; |
1085 | default: | |
e2e0b3e5 | 1086 | internal_error (__FILE__, __LINE__, _("can't handle ABI")); |
96f026fc KB |
1087 | break; |
1088 | } | |
6de918a6 | 1089 | |
982e9687 | 1090 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
6de918a6 DJ |
1091 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); |
1092 | ||
0d0266c6 | 1093 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1094 | |
1095 | /* Enable TLS support. */ | |
1096 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1097 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1098 | |
1099 | /* Initialize this lazily, to avoid an initialization order | |
1100 | dependency on solib-svr4.c's _initialize routine. */ | |
1101 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1102 | { | |
1103 | mips_svr4_so_ops = svr4_so_ops; | |
1104 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1105 | = mips_linux_in_dynsym_resolve_code; | |
1106 | } | |
1107 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
19ed69dd KB |
1108 | } |
1109 | ||
2aa830e4 | 1110 | void |
d1bacddc | 1111 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1112 | { |
96f026fc KB |
1113 | const struct bfd_arch_info *arch_info; |
1114 | ||
96f026fc KB |
1115 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1116 | arch_info != NULL; | |
1117 | arch_info = arch_info->next) | |
1118 | { | |
295093a4 MS |
1119 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1120 | GDB_OSABI_LINUX, | |
96f026fc KB |
1121 | mips_linux_init_abi); |
1122 | } | |
1123 | ||
00e32a35 | 1124 | deprecated_add_core_fns (®set_core_fns); |
2aa830e4 | 1125 | } |