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import strstr and strerror modules
[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
28e7fd62 3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
2aa830e4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ		 19
20#include "defs.h"
21#include "gdbcore.h"
22#include "target.h"
23#include "solib-svr4.h"
19ed69dd 24#include "osabi.h"
96f026fc 25#include "mips-tdep.h"
19ed69dd 26#include "gdb_string.h"
96f026fc 27#include "gdb_assert.h"
6de918a6 28#include "frame.h"
2fdf551c 29#include "regcache.h"
5792a79b
DJ		 30#include "trad-frame.h"
31#include "tramp-frame.h"
e6bb342a 32#include "gdbtypes.h"
3e5d3a5a 33#include "objfiles.h"
5ea03926 34#include "solib.h"
7d522c90
DJ		 35#include "solib-svr4.h"
36#include "solist.h"
982e9687 37#include "symtab.h"
822b6570 38#include "target-descriptions.h"
50e8a0d5 39#include "regset.h"
d37eb719 40#include "mips-linux-tdep.h"
db5f024e 41#include "glibc-tdep.h"
a5ee0f0c 42#include "linux-tdep.h"
385203ed 43#include "xml-syscall.h"
232b8704 44#include "gdb_signals.h"
2aa830e4 45
7d522c90
DJ		 46static struct target_so_ops mips_svr4_so_ops;
47
eb14d406
SDJ		 48/* This enum represents the signals' numbers on the MIPS
49 architecture. It just contains the signal definitions which are
50 different from the generic implementation.
51
52 It is derived from the file <arch/mips/include/uapi/asm/signal.h>,
53 from the Linux kernel tree. */
54
55enum
56 {
57 MIPS_LINUX_SIGEMT = 7,
58 MIPS_LINUX_SIGBUS = 10,
59 MIPS_LINUX_SIGSYS = 12,
60 MIPS_LINUX_SIGUSR1 = 16,
61 MIPS_LINUX_SIGUSR2 = 17,
62 MIPS_LINUX_SIGCHLD = 18,
63 MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD,
64 MIPS_LINUX_SIGPWR = 19,
65 MIPS_LINUX_SIGWINCH = 20,
66 MIPS_LINUX_SIGURG = 21,
67 MIPS_LINUX_SIGIO = 22,
68 MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO,
69 MIPS_LINUX_SIGSTOP = 23,
70 MIPS_LINUX_SIGTSTP = 24,
71 MIPS_LINUX_SIGCONT = 25,
72 MIPS_LINUX_SIGTTIN = 26,
73 MIPS_LINUX_SIGTTOU = 27,
74 MIPS_LINUX_SIGVTALRM = 28,
75 MIPS_LINUX_SIGPROF = 29,
76 MIPS_LINUX_SIGXCPU = 30,
77 MIPS_LINUX_SIGXFSZ = 31,
78
79 MIPS_LINUX_SIGRTMIN = 32,
80 MIPS_LINUX_SIGRT64 = 64,
81 MIPS_LINUX_SIGRTMAX = 127,
82 };
83
2aa830e4 84/* Figure out where the longjmp will land.
295093a4
MS		 85 We expect the first arg to be a pointer to the jmp_buf structure
86 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
87 at. The pc is copied into PC. This routine returns 1 on
88 success. */
2aa830e4 89
19ed69dd
KB		 90#define MIPS_LINUX_JB_ELEMENT_SIZE 4
91#define MIPS_LINUX_JB_PC 0
92
93static int
60ade65d 94mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2aa830e4
DJ		 95{
96 CORE_ADDR jb_addr;
2eb4d78b 97 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 98 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e362b510 99 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
2aa830e4 100
60ade65d 101 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
2aa830e4 102
7d266584
MR		 103 if (target_read_memory ((jb_addr
104 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
2eb4d78b 105 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
2aa830e4
DJ		 106 return 0;
107
819844ad 108 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 109 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
110 byte_order);
2aa830e4
DJ		 111
112 return 1;
113}
114
4246e332 115/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 116 for regcache_raw_supply(). This is needed when mips_isa_regsize()
117 is 8. */
96f026fc
KB		 118
119static void
28f5035f 120supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
96f026fc 121{
e17a4113
UW		 122 struct gdbarch *gdbarch = get_regcache_arch (regcache);
123 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 124 gdb_byte buf[MAX_REGISTER_SIZE];
e17a4113 125 store_signed_integer (buf, register_size (gdbarch, regnum), byte_order,
7d266584 126 extract_signed_integer (addr, 4, byte_order));
28f5035f 127 regcache_raw_supply (regcache, regnum, buf);
96f026fc
KB		 128}
129
2aa830e4
DJ		 130/* Unpack an elf_gregset_t into GDB's register cache. */
131
d37eb719 132void
28f5035f
UW		 133mips_supply_gregset (struct regcache *regcache,
134 const mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 135{
136 int regi;
28f5035f 137 const mips_elf_greg_t *regp = *gregsetp;
d9d9c31f 138 char zerobuf[MAX_REGISTER_SIZE];
2eb4d78b 139 struct gdbarch *gdbarch = get_regcache_arch (regcache);
bf072999 140
d9d9c31f 141 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4 142
822b6570 143 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
28f5035f 144 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
2aa830e4 145
2eb4d78b 146 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 147 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
148
2eb4d78b
UW		 149 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
150 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
56cea623 151
2eb4d78b 152 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 153 regp + EF_CP0_EPC);
2eb4d78b 154 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 155 regp + EF_CP0_BADVADDR);
156 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
2eb4d78b 157 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 158 regp + EF_CP0_CAUSE);
2aa830e4 159
1faeff08 160 /* Fill the inaccessible zero register with zero. */
822b6570 161 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
2aa830e4
DJ		 162}
163
50e8a0d5
HZ		 164static void
165mips_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 166 struct regcache *regcache,
167 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 168{
169 gdb_assert (len == sizeof (mips_elf_gregset_t));
170
171 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
172}
173
2aa830e4
DJ		 174/* Pack our registers (or one register) into an elf_gregset_t. */
175
d37eb719 176void
28f5035f
UW		 177mips_fill_gregset (const struct regcache *regcache,
178 mips_elf_gregset_t *gregsetp, int regno)
2aa830e4 179{
2eb4d78b 180 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2aa830e4 181 int regaddr, regi;
d37eb719 182 mips_elf_greg_t *regp = *gregsetp;
96f026fc 183 void *dst;
2aa830e4
DJ		 184
185 if (regno == -1)
186 {
d37eb719 187 memset (regp, 0, sizeof (mips_elf_gregset_t));
822b6570 188 for (regi = 1; regi < 32; regi++)
28f5035f 189 mips_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 190 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
191 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
192 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
193 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
28f5035f 194 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 195 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 196 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
2aa830e4
DJ		 197 return;
198 }
199
822b6570 200 if (regno > 0 && regno < 32)
2aa830e4 201 {
2aa830e4 202 dst = regp + regno + EF_REG0;
28f5035f 203 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 204 return;
205 }
206
2eb4d78b
UW		 207 if (regno == mips_regnum (gdbarch)->lo)
208 regaddr = EF_LO;
209 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 210 regaddr = EF_HI;
2eb4d78b 211 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 212 regaddr = EF_CP0_EPC;
2eb4d78b 213 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 214 regaddr = EF_CP0_BADVADDR;
24e05951 215 else if (regno == MIPS_PS_REGNUM)
56cea623 216 regaddr = EF_CP0_STATUS;
2eb4d78b 217 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 218 regaddr = EF_CP0_CAUSE;
2eb4d78b 219 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 220 && regno == MIPS_RESTART_REGNUM)
221 regaddr = EF_REG0;
56cea623
AC		 222 else
223 regaddr = -1;
2aa830e4
DJ		 224
225 if (regaddr != -1)
226 {
2aa830e4 227 dst = regp + regaddr;
28f5035f 228 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 229 }
230}
231
50e8a0d5
HZ		 232static void
233mips_fill_gregset_wrapper (const struct regset *regset,
234 const struct regcache *regcache,
235 int regnum, void *gregs, size_t len)
236{
237 gdb_assert (len == sizeof (mips_elf_gregset_t));
238
239 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
240}
241
2aa830e4
DJ		 242/* Likewise, unpack an elf_fpregset_t. */
243
d37eb719 244void
28f5035f
UW		 245mips_supply_fpregset (struct regcache *regcache,
246 const mips_elf_fpregset_t *fpregsetp)
2aa830e4 247{
2eb4d78b 248 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 249 int regi;
d9d9c31f 250 char zerobuf[MAX_REGISTER_SIZE];
bf072999 251
d9d9c31f 252 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 253
254 for (regi = 0; regi < 32; regi++)
3e8c568d 255 regcache_raw_supply (regcache,
2eb4d78b 256 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 257 *fpregsetp + regi);
2aa830e4 258
28f5035f 259 regcache_raw_supply (regcache,
2eb4d78b 260 mips_regnum (gdbarch)->fp_control_status,
28f5035f 261 *fpregsetp + 32);
2aa830e4 262
295093a4 263 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
28f5035f 264 regcache_raw_supply (regcache,
2eb4d78b 265 mips_regnum (gdbarch)->fp_implementation_revision,
23a6d369 266 zerobuf);
2aa830e4
DJ		 267}
268
50e8a0d5
HZ		 269static void
270mips_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 271 struct regcache *regcache,
272 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 273{
274 gdb_assert (len == sizeof (mips_elf_fpregset_t));
275
276 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs);
277}
278
2aa830e4
DJ		 279/* Likewise, pack one or all floating point registers into an
280 elf_fpregset_t. */
281
d37eb719 282void
28f5035f
UW		 283mips_fill_fpregset (const struct regcache *regcache,
284 mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4 285{
2eb4d78b 286 struct gdbarch *gdbarch = get_regcache_arch (regcache);
22e048c9 287 char *to;
2aa830e4 288
2eb4d78b
UW		 289 if ((regno >= gdbarch_fp0_regnum (gdbarch))
290 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
2aa830e4 291 {
2eb4d78b 292 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
28f5035f 293 regcache_raw_collect (regcache, regno, to);
2aa830e4 294 }
2eb4d78b 295 else if (regno == mips_regnum (gdbarch)->fp_control_status)
2aa830e4 296 {
2aa830e4 297 to = (char *) (*fpregsetp + 32);
28f5035f 298 regcache_raw_collect (regcache, regno, to);
2aa830e4
DJ		 299 }
300 else if (regno == -1)
301 {
302 int regi;
303
304 for (regi = 0; regi < 32; regi++)
3e8c568d 305 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 306 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 307 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 308 mips_regnum (gdbarch)->fp_control_status);
2aa830e4
DJ		 309 }
310}
311
50e8a0d5
HZ		 312static void
313mips_fill_fpregset_wrapper (const struct regset *regset,
314 const struct regcache *regcache,
315 int regnum, void *gregs, size_t len)
316{
317 gdb_assert (len == sizeof (mips_elf_fpregset_t));
318
319 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum);
320}
321
96f026fc
KB		 322/* Support for 64-bit ABIs. */
323
96f026fc 324/* Figure out where the longjmp will land.
295093a4
MS		 325 We expect the first arg to be a pointer to the jmp_buf structure
326 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
327 at. The pc is copied into PC. This routine returns 1 on
328 success. */
96f026fc
KB		 329
330/* Details about jmp_buf. */
331
332#define MIPS64_LINUX_JB_PC 0
333
334static int
60ade65d 335mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
96f026fc
KB		 336{
337 CORE_ADDR jb_addr;
2eb4d78b 338 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 339 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2eb4d78b
UW		 340 void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
341 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
96f026fc 342
60ade65d 343 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
96f026fc
KB		 344
345 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
819844ad 346 buf,
2eb4d78b 347 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
96f026fc
KB		 348 return 0;
349
819844ad 350 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 351 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
352 byte_order);
96f026fc
KB		 353
354 return 1;
355}
356
d37eb719
DJ		 357/* Register set support functions. These operate on standard 64-bit
358 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
359 target will still use the 64-bit format for PTRACE_GETREGS. */
360
361/* Supply a 64-bit register. */
96f026fc 362
63807e1d 363static void
28f5035f
UW		 364supply_64bit_reg (struct regcache *regcache, int regnum,
365 const gdb_byte *buf)
d37eb719 366{
2eb4d78b
UW		 367 struct gdbarch *gdbarch = get_regcache_arch (regcache);
368 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
369 && register_size (gdbarch, regnum) == 4)
28f5035f 370 regcache_raw_supply (regcache, regnum, buf + 4);
d37eb719 371 else
28f5035f 372 regcache_raw_supply (regcache, regnum, buf);
d37eb719
DJ		 373}
374
375/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
376
377void
28f5035f
UW		 378mips64_supply_gregset (struct regcache *regcache,
379 const mips64_elf_gregset_t *gregsetp)
96f026fc
KB		 380{
381 int regi;
28f5035f 382 const mips64_elf_greg_t *regp = *gregsetp;
d37eb719 383 gdb_byte zerobuf[MAX_REGISTER_SIZE];
2eb4d78b 384 struct gdbarch *gdbarch = get_regcache_arch (regcache);
96f026fc 385
d9d9c31f 386 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc 387
822b6570 388 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
28f5035f 389 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
7d266584 390 (const gdb_byte *) (regp + regi));
28f5035f 391
2eb4d78b 392 if (mips_linux_restart_reg_p (gdbarch))
822b6570 393 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
7d266584 394 (const gdb_byte *) (regp + MIPS64_EF_REG0));
822b6570 395
2eb4d78b 396 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
28f5035f 397 (const gdb_byte *) (regp + MIPS64_EF_LO));
2eb4d78b 398 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
28f5035f
UW		 399 (const gdb_byte *) (regp + MIPS64_EF_HI));
400
2eb4d78b 401 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 402 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
2eb4d78b 403 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 404 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
405 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
406 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
2eb4d78b 407 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 408 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc 409
1faeff08 410 /* Fill the inaccessible zero register with zero. */
822b6570 411 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
96f026fc
KB		 412}
413
50e8a0d5
HZ		 414static void
415mips64_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 416 struct regcache *regcache,
417 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 418{
419 gdb_assert (len == sizeof (mips64_elf_gregset_t));
420
421 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
422}
423
d37eb719 424/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 425
d37eb719 426void
28f5035f
UW		 427mips64_fill_gregset (const struct regcache *regcache,
428 mips64_elf_gregset_t *gregsetp, int regno)
96f026fc 429{
2eb4d78b 430 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 431 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
96f026fc
KB		 432 int regaddr, regi;
433 mips64_elf_greg_t *regp = *gregsetp;
2ba93934 434 void *dst;
96f026fc
KB		 435
436 if (regno == -1)
437 {
438 memset (regp, 0, sizeof (mips64_elf_gregset_t));
822b6570 439 for (regi = 1; regi < 32; regi++)
7d266584 440 mips64_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 441 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
442 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
443 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
025bb325
MS		 444 mips64_fill_gregset (regcache, gregsetp,
445 mips_regnum (gdbarch)->badvaddr);
28f5035f 446 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 447 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 448 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
96f026fc
KB		 449 return;
450 }
451
822b6570 452 if (regno > 0 && regno < 32)
d37eb719 453 regaddr = regno + MIPS64_EF_REG0;
2eb4d78b 454 else if (regno == mips_regnum (gdbarch)->lo)
56cea623 455 regaddr = MIPS64_EF_LO;
2eb4d78b 456 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 457 regaddr = MIPS64_EF_HI;
2eb4d78b 458 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 459 regaddr = MIPS64_EF_CP0_EPC;
2eb4d78b 460 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 461 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 462 else if (regno == MIPS_PS_REGNUM)
56cea623 463 regaddr = MIPS64_EF_CP0_STATUS;
2eb4d78b 464 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 465 regaddr = MIPS64_EF_CP0_CAUSE;
2eb4d78b 466 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 467 && regno == MIPS_RESTART_REGNUM)
468 regaddr = MIPS64_EF_REG0;
56cea623
AC		 469 else
470 regaddr = -1;
96f026fc
KB		 471
472 if (regaddr != -1)
473 {
d37eb719
DJ		 474 gdb_byte buf[MAX_REGISTER_SIZE];
475 LONGEST val;
476
28f5035f 477 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 478 val = extract_signed_integer (buf, register_size (gdbarch, regno),
479 byte_order);
96f026fc 480 dst = regp + regaddr;
e17a4113 481 store_signed_integer (dst, 8, byte_order, val);
96f026fc
KB		 482 }
483}
484
50e8a0d5
HZ		 485static void
486mips64_fill_gregset_wrapper (const struct regset *regset,
487 const struct regcache *regcache,
488 int regnum, void *gregs, size_t len)
489{
490 gdb_assert (len == sizeof (mips64_elf_gregset_t));
491
492 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
493}
494
96f026fc
KB		 495/* Likewise, unpack an elf_fpregset_t. */
496
d37eb719 497void
28f5035f
UW		 498mips64_supply_fpregset (struct regcache *regcache,
499 const mips64_elf_fpregset_t *fpregsetp)
96f026fc 500{
2eb4d78b 501 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 502 int regi;
96f026fc 503
d37eb719
DJ		 504 /* See mips_linux_o32_sigframe_init for a description of the
505 peculiar FP register layout. */
2eb4d78b 506 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
d37eb719
DJ		 507 for (regi = 0; regi < 32; regi++)
508 {
7d266584
MR		 509 const gdb_byte *reg_ptr
510 = (const gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 511 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 512 reg_ptr += 4;
3e8c568d 513 regcache_raw_supply (regcache,
2eb4d78b 514 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 515 reg_ptr);
d37eb719
DJ		 516 }
517 else
518 for (regi = 0; regi < 32; regi++)
3e8c568d 519 regcache_raw_supply (regcache,
2eb4d78b 520 gdbarch_fp0_regnum (gdbarch) + regi,
7d266584 521 (const char *) (*fpregsetp + regi));
d37eb719 522
2eb4d78b 523 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
7d266584 524 (const gdb_byte *) (*fpregsetp + 32));
d37eb719
DJ		 525
526 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
527 include it - but the result of PTRACE_GETFPREGS does. The best we
528 can do is to assume that its value is present. */
28f5035f 529 supply_32bit_reg (regcache,
2eb4d78b 530 mips_regnum (gdbarch)->fp_implementation_revision,
7d266584 531 (const gdb_byte *) (*fpregsetp + 32) + 4);
96f026fc
KB		 532}
533
50e8a0d5
HZ		 534static void
535mips64_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 536 struct regcache *regcache,
537 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 538{
539 gdb_assert (len == sizeof (mips64_elf_fpregset_t));
540
541 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
542}
543
96f026fc
KB		 544/* Likewise, pack one or all floating point registers into an
545 elf_fpregset_t. */
546
d37eb719 547void
28f5035f
UW		 548mips64_fill_fpregset (const struct regcache *regcache,
549 mips64_elf_fpregset_t *fpregsetp, int regno)
96f026fc 550{
2eb4d78b 551 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 552 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 553 gdb_byte *to;
96f026fc 554
2eb4d78b
UW		 555 if ((regno >= gdbarch_fp0_regnum (gdbarch))
556 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
96f026fc 557 {
d37eb719
DJ		 558 /* See mips_linux_o32_sigframe_init for a description of the
559 peculiar FP register layout. */
2eb4d78b 560 if (register_size (gdbarch, regno) == 4)
d37eb719 561 {
2eb4d78b 562 int regi = regno - gdbarch_fp0_regnum (gdbarch);
d37eb719
DJ		 563
564 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 565 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 566 to += 4;
28f5035f 567 regcache_raw_collect (regcache, regno, to);
d37eb719
DJ		 568 }
569 else
570 {
025bb325
MS		 571 to = (gdb_byte *) (*fpregsetp + regno
572 - gdbarch_fp0_regnum (gdbarch));
28f5035f 573 regcache_raw_collect (regcache, regno, to);
d37eb719 574 }
96f026fc 575 }
2eb4d78b 576 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96f026fc 577 {
d37eb719
DJ		 578 gdb_byte buf[MAX_REGISTER_SIZE];
579 LONGEST val;
580
28f5035f 581 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 582 val = extract_signed_integer (buf, register_size (gdbarch, regno),
583 byte_order);
d37eb719 584 to = (gdb_byte *) (*fpregsetp + 32);
e17a4113 585 store_signed_integer (to, 4, byte_order, val);
d37eb719 586 }
2eb4d78b 587 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ		 588 {
589 gdb_byte buf[MAX_REGISTER_SIZE];
590 LONGEST val;
591
28f5035f 592 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 593 val = extract_signed_integer (buf, register_size (gdbarch, regno),
594 byte_order);
d37eb719 595 to = (gdb_byte *) (*fpregsetp + 32) + 4;
e17a4113 596 store_signed_integer (to, 4, byte_order, val);
96f026fc
KB		 597 }
598 else if (regno == -1)
599 {
600 int regi;
601
602 for (regi = 0; regi < 32; regi++)
3e8c568d 603 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 604 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 605 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 606 mips_regnum (gdbarch)->fp_control_status);
28f5035f 607 mips64_fill_fpregset (regcache, fpregsetp,
7d266584 608 mips_regnum (gdbarch)->fp_implementation_revision);
96f026fc
KB		 609 }
610}
611
50e8a0d5
HZ		 612static void
613mips64_fill_fpregset_wrapper (const struct regset *regset,
614 const struct regcache *regcache,
615 int regnum, void *gregs, size_t len)
616{
617 gdb_assert (len == sizeof (mips64_elf_fpregset_t));
96f026fc 618
50e8a0d5
HZ		 619 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
620}
2aa830e4 621
693be288 622static const struct regset *
50e8a0d5 623mips_linux_regset_from_core_section (struct gdbarch *gdbarch,
7d266584 624 const char *sect_name, size_t sect_size)
2aa830e4 625{
50e8a0d5 626 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
d37eb719
DJ		 627 mips_elf_gregset_t gregset;
628 mips_elf_fpregset_t fpregset;
96f026fc
KB		 629 mips64_elf_gregset_t gregset64;
630 mips64_elf_fpregset_t fpregset64;
2aa830e4 631
50e8a0d5 632 if (strcmp (sect_name, ".reg") == 0)
2aa830e4 633 {
50e8a0d5 634 if (sect_size == sizeof (gregset))
2aa830e4 635 {
50e8a0d5
HZ		 636 if (tdep->gregset == NULL)
637 tdep->gregset = regset_alloc (gdbarch,
7d266584
MR		 638 mips_supply_gregset_wrapper,
639 mips_fill_gregset_wrapper);
50e8a0d5 640 return tdep->gregset;
96f026fc 641 }
50e8a0d5 642 else if (sect_size == sizeof (gregset64))
96f026fc 643 {
50e8a0d5
HZ		 644 if (tdep->gregset64 == NULL)
645 tdep->gregset64 = regset_alloc (gdbarch,
7d266584
MR		 646 mips64_supply_gregset_wrapper,
647 mips64_fill_gregset_wrapper);
50e8a0d5 648 return tdep->gregset64;
2aa830e4
DJ		 649 }
650 else
651 {
8a3fe4f8 652 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 653 }
654 }
50e8a0d5 655 else if (strcmp (sect_name, ".reg2") == 0)
2aa830e4 656 {
50e8a0d5 657 if (sect_size == sizeof (fpregset))
2aa830e4 658 {
50e8a0d5
HZ		 659 if (tdep->fpregset == NULL)
660 tdep->fpregset = regset_alloc (gdbarch,
7d266584
MR		 661 mips_supply_fpregset_wrapper,
662 mips_fill_fpregset_wrapper);
50e8a0d5 663 return tdep->fpregset;
96f026fc 664 }
50e8a0d5 665 else if (sect_size == sizeof (fpregset64))
96f026fc 666 {
50e8a0d5
HZ		 667 if (tdep->fpregset64 == NULL)
668 tdep->fpregset64 = regset_alloc (gdbarch,
7d266584
MR		 669 mips64_supply_fpregset_wrapper,
670 mips64_fill_fpregset_wrapper);
50e8a0d5 671 return tdep->fpregset64;
2aa830e4
DJ		 672 }
673 else
674 {
8a3fe4f8 675 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 676 }
677 }
2aa830e4 678
50e8a0d5
HZ		 679 return NULL;
680}
2aa830e4 681
4eb0ad19
DJ		 682static const struct target_desc *
683mips_linux_core_read_description (struct gdbarch *gdbarch,
684 struct target_ops *target,
685 bfd *abfd)
686{
687 asection *section = bfd_get_section_by_name (abfd, ".reg");
688 if (! section)
689 return NULL;
690
691 switch (bfd_section_size (abfd, section))
692 {
693 case sizeof (mips_elf_gregset_t):
694 return mips_tdesc_gp32;
695
696 case sizeof (mips64_elf_gregset_t):
697 return mips_tdesc_gp64;
698
699 default:
700 return NULL;
701 }
702}
703
96f026fc 704
295093a4 705/* Check the code at PC for a dynamic linker lazy resolution stub.
3e5d3a5a
MR		 706 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs"
707 section uniformly since version 2.15. If the pc is in that section,
708 then we are in such a stub. Before that ".stub" was used in 32-bit
709 ELF binaries, however we do not bother checking for that since we
710 have never had and that case should be extremely rare these days.
711 Instead we pattern-match on the code generated by GNU ld. They look
712 like this:
6de918a6
DJ		 713
714 lw t9,0x8010(gp)
715 addu t7,ra
716 jalr t9,ra
717 addiu t8,zero,INDEX
718
3e5d3a5a
MR		 719 (with the appropriate doubleword instructions for N64). As any lazy
720 resolution stubs in microMIPS binaries will always be in a
721 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */
6de918a6
DJ		 722
723static int
3e5d3a5a 724mips_linux_in_dynsym_stub (CORE_ADDR pc)
6de918a6 725{
e362b510 726 gdb_byte buf[28], *p;
6de918a6 727 ULONGEST insn, insn1;
f5656ead
TT		 728 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64);
729 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
6de918a6 730
3e5d3a5a
MR		 731 if (in_mips_stubs_section (pc))
732 return 1;
733
6de918a6
DJ		 734 read_memory (pc - 12, buf, 28);
735
736 if (n64)
737 {
738 /* ld t9,0x8010(gp) */
739 insn1 = 0xdf998010;
740 }
741 else
742 {
743 /* lw t9,0x8010(gp) */
744 insn1 = 0x8f998010;
745 }
746
747 p = buf + 12;
748 while (p >= buf)
749 {
e17a4113 750 insn = extract_unsigned_integer (p, 4, byte_order);
6de918a6
DJ		 751 if (insn == insn1)
752 break;
753 p -= 4;
754 }
755 if (p < buf)
756 return 0;
757
e17a4113 758 insn = extract_unsigned_integer (p + 4, 4, byte_order);
6de918a6
DJ		 759 if (n64)
760 {
761 /* daddu t7,ra */
762 if (insn != 0x03e0782d)
763 return 0;
764 }
765 else
766 {
767 /* addu t7,ra */
768 if (insn != 0x03e07821)
769 return 0;
770 }
295093a4 771
e17a4113 772 insn = extract_unsigned_integer (p + 8, 4, byte_order);
6de918a6
DJ		 773 /* jalr t9,ra */
774 if (insn != 0x0320f809)
775 return 0;
776
e17a4113 777 insn = extract_unsigned_integer (p + 12, 4, byte_order);
6de918a6
DJ		 778 if (n64)
779 {
780 /* daddiu t8,zero,0 */
781 if ((insn & 0xffff0000) != 0x64180000)
782 return 0;
783 }
784 else
785 {
786 /* addiu t8,zero,0 */
787 if ((insn & 0xffff0000) != 0x24180000)
788 return 0;
789 }
790
3e5d3a5a 791 return 1;
6de918a6
DJ		 792}
793
295093a4 794/* Return non-zero iff PC belongs to the dynamic linker resolution
db5f024e 795 code, a PLT entry, or a lazy binding stub. */
6de918a6 796
7d522c90 797static int
6de918a6
DJ		 798mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
799{
295093a4 800 /* Check whether PC is in the dynamic linker. This also checks
db5f024e 801 whether it is in the .plt section, used by non-PIC executables. */
7d522c90 802 if (svr4_in_dynsym_resolve_code (pc))
6de918a6
DJ		 803 return 1;
804
3e5d3a5a
MR		 805 /* Likewise for the stubs. They live in the .MIPS.stubs section these
806 days, so we check if the PC is within, than fall back to a pattern
807 match. */
808 if (mips_linux_in_dynsym_stub (pc))
6de918a6
DJ		 809 return 1;
810
811 return 0;
812}
813
814/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
815 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
816 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba 817 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
db5f024e
DJ		 818 "__dl_runtime_resolve" directly. An unresolved lazy binding
819 stub will point to _dl_runtime_resolve, which will first call
c4c5b7ba
AC		 820 __dl_runtime_resolve, and then pass control to the resolved
821 function. */
6de918a6
DJ		 822
823static CORE_ADDR
824mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
825{
826 struct minimal_symbol *resolver;
827
828 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
829
830 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
c7ce8faa 831 return frame_unwind_caller_pc (get_current_frame ());
6de918a6 832
db5f024e 833 return glibc_skip_solib_resolver (gdbarch, pc);
295093a4 834}
6de918a6 835
5792a79b
DJ		 836/* Signal trampoline support. There are four supported layouts for a
837 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
838 n64 rt_sigframe. We handle them all independently; not the most
839 efficient way, but simplest. First, declare all the unwinders. */
840
841static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 842 struct frame_info *this_frame,
5792a79b
DJ		 843 struct trad_frame_cache *this_cache,
844 CORE_ADDR func);
845
846static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 847 struct frame_info *this_frame,
5792a79b
DJ		 848 struct trad_frame_cache *this_cache,
849 CORE_ADDR func);
850
851#define MIPS_NR_LINUX 4000
852#define MIPS_NR_N64_LINUX 5000
853#define MIPS_NR_N32_LINUX 6000
854
855#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
856#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
857#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
858#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
859
860#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
861#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
862#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
863#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
864#define MIPS_INST_SYSCALL 0x0000000c
865
2cd8546d
AC		 866static const struct tramp_frame mips_linux_o32_sigframe = {
867 SIGTRAMP_FRAME,
5792a79b 868 4,
2cd8546d
AC		 869 {
870 { MIPS_INST_LI_V0_SIGRETURN, -1 },
871 { MIPS_INST_SYSCALL, -1 },
872 { TRAMP_SENTINEL_INSN, -1 }
873 },
5792a79b
DJ		 874 mips_linux_o32_sigframe_init
875};
876
2cd8546d
AC		 877static const struct tramp_frame mips_linux_o32_rt_sigframe = {
878 SIGTRAMP_FRAME,
5792a79b 879 4,
2cd8546d
AC		 880 {
881 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
882 { MIPS_INST_SYSCALL, -1 },
883 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 884 mips_linux_o32_sigframe_init
885};
886
2cd8546d
AC		 887static const struct tramp_frame mips_linux_n32_rt_sigframe = {
888 SIGTRAMP_FRAME,
5792a79b 889 4,
2cd8546d
AC		 890 {
891 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
892 { MIPS_INST_SYSCALL, -1 },
893 { TRAMP_SENTINEL_INSN, -1 }
894 },
5792a79b
DJ		 895 mips_linux_n32n64_sigframe_init
896};
897
2cd8546d
AC		 898static const struct tramp_frame mips_linux_n64_rt_sigframe = {
899 SIGTRAMP_FRAME,
5792a79b 900 4,
fcbd8a5c
TS		 901 {
902 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
903 { MIPS_INST_SYSCALL, -1 },
904 { TRAMP_SENTINEL_INSN, -1 }
905 },
5792a79b
DJ		 906 mips_linux_n32n64_sigframe_init
907};
908
909/* *INDENT-OFF* */
910/* The unwinder for o32 signal frames. The legacy structures look
911 like this:
912
913 struct sigframe {
914 u32 sf_ass[4]; [argument save space for o32]
eb195664 915 u32 sf_code[2]; [signal trampoline or fill]
5792a79b
DJ		 916 struct sigcontext sf_sc;
917 sigset_t sf_mask;
918 };
919
d0e64392
MR		 920 Pre-2.6.12 sigcontext:
921
5792a79b
DJ		 922 struct sigcontext {
923 unsigned int sc_regmask; [Unused]
924 unsigned int sc_status;
925 unsigned long long sc_pc;
926 unsigned long long sc_regs[32];
927 unsigned long long sc_fpregs[32];
928 unsigned int sc_ownedfp;
929 unsigned int sc_fpc_csr;
930 unsigned int sc_fpc_eir; [Unused]
931 unsigned int sc_used_math;
932 unsigned int sc_ssflags; [Unused]
933 [Alignment hole of four bytes]
934 unsigned long long sc_mdhi;
935 unsigned long long sc_mdlo;
936
937 unsigned int sc_cause; [Unused]
938 unsigned int sc_badvaddr; [Unused]
939
940 unsigned long sc_sigset[4]; [kernel's sigset_t]
941 };
942
d0e64392
MR		 943 Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
944
945 struct sigcontext {
946 unsigned int sc_regmask; [Unused]
947 unsigned int sc_status; [Unused]
948 unsigned long long sc_pc;
949 unsigned long long sc_regs[32];
950 unsigned long long sc_fpregs[32];
951 unsigned int sc_acx;
952 unsigned int sc_fpc_csr;
953 unsigned int sc_fpc_eir; [Unused]
954 unsigned int sc_used_math;
955 unsigned int sc_dsp;
956 [Alignment hole of four bytes]
957 unsigned long long sc_mdhi;
958 unsigned long long sc_mdlo;
959 unsigned long sc_hi1;
960 unsigned long sc_lo1;
961 unsigned long sc_hi2;
962 unsigned long sc_lo2;
963 unsigned long sc_hi3;
964 unsigned long sc_lo3;
965 };
966
5792a79b
DJ		 967 The RT signal frames look like this:
968
969 struct rt_sigframe {
970 u32 rs_ass[4]; [argument save space for o32]
eb195664 971 u32 rs_code[2] [signal trampoline or fill]
5792a79b
DJ		 972 struct siginfo rs_info;
973 struct ucontext rs_uc;
974 };
975
976 struct ucontext {
977 unsigned long uc_flags;
978 struct ucontext *uc_link;
979 stack_t uc_stack;
980 [Alignment hole of four bytes]
981 struct sigcontext uc_mcontext;
982 sigset_t uc_sigmask;
983 }; */
984/* *INDENT-ON* */
985
5792a79b
DJ		 986#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
987
988#define RTSIGFRAME_SIGINFO_SIZE 128
989#define STACK_T_SIZE (3 * 4)
990#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
991#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
992 + RTSIGFRAME_SIGINFO_SIZE \
993 + UCONTEXT_SIGCONTEXT_OFFSET)
994
995#define SIGCONTEXT_PC (1 * 8)
996#define SIGCONTEXT_REGS (2 * 8)
997#define SIGCONTEXT_FPREGS (34 * 8)
998#define SIGCONTEXT_FPCSR (66 * 8 + 4)
d0e64392 999#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
5792a79b
DJ		 1000#define SIGCONTEXT_HI (69 * 8)
1001#define SIGCONTEXT_LO (70 * 8)
1002#define SIGCONTEXT_CAUSE (71 * 8 + 0)
1003#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
d0e64392
MR		 1004#define SIGCONTEXT_HI1 (71 * 8 + 0)
1005#define SIGCONTEXT_LO1 (71 * 8 + 4)
1006#define SIGCONTEXT_HI2 (72 * 8 + 0)
1007#define SIGCONTEXT_LO2 (72 * 8 + 4)
1008#define SIGCONTEXT_HI3 (73 * 8 + 0)
1009#define SIGCONTEXT_LO3 (73 * 8 + 4)
5792a79b
DJ		 1010
1011#define SIGCONTEXT_REG_SIZE 8
1012
1013static void
1014mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 1015 struct frame_info *this_frame,
5792a79b
DJ		 1016 struct trad_frame_cache *this_cache,
1017 CORE_ADDR func)
1018{
b8a22b94 1019 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1020 int ireg;
eb195664
DD		 1021 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1022 CORE_ADDR sigcontext_base;
2eb4d78b 1023 const struct mips_regnum *regs = mips_regnum (gdbarch);
37c4d197 1024 CORE_ADDR regs_base;
5792a79b
DJ		 1025
1026 if (self == &mips_linux_o32_sigframe)
eb195664 1027 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1028 else
eb195664 1029 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 1030
1031 /* I'm not proud of this hack. Eventually we will have the
1032 infrastructure to indicate the size of saved registers on a
1033 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 1034 bytes but we only want four. Use regs_base to access any
1035 64-bit fields. */
2eb4d78b 1036 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
37c4d197
DJ		 1037 regs_base = sigcontext_base + 4;
1038 else
1039 regs_base = sigcontext_base;
5792a79b 1040
2eb4d78b 1041 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1042 trad_frame_set_reg_addr (this_cache,
1043 (MIPS_RESTART_REGNUM
2eb4d78b 1044 + gdbarch_num_regs (gdbarch)),
822b6570 1045 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 1046
1047 for (ireg = 1; ireg < 32; ireg++)
295093a4 1048 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1049 (ireg + MIPS_ZERO_REGNUM
1050 + gdbarch_num_regs (gdbarch)),
1051 (regs_base + SIGCONTEXT_REGS
1052 + ireg * SIGCONTEXT_REG_SIZE));
5792a79b 1053
37c4d197
DJ		 1054 /* The way that floating point registers are saved, unfortunately,
1055 depends on the architecture the kernel is built for. For the r3000 and
1056 tx39, four bytes of each register are at the beginning of each of the
1057 32 eight byte slots. For everything else, the registers are saved
1058 using double precision; only the even-numbered slots are initialized,
1059 and the high bits are the odd-numbered register. Assume the latter
1060 layout, since we can't tell, and it's much more common. Which bits are
1061 the "high" bits depends on endianness. */
5792a79b 1062 for (ireg = 0; ireg < 32; ireg++)
2eb4d78b 1063 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
f57d151a 1064 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1065 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1066 (sigcontext_base + SIGCONTEXT_FPREGS + 4
1067 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
37c4d197 1068 else
f57d151a 1069 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1070 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1071 (sigcontext_base + SIGCONTEXT_FPREGS
1072 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
5792a79b 1073
f57d151a 1074 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1075 regs->pc + gdbarch_num_regs (gdbarch),
37c4d197 1076 regs_base + SIGCONTEXT_PC);
5792a79b 1077
295093a4 1078 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1079 (regs->fp_control_status
1080 + gdbarch_num_regs (gdbarch)),
5792a79b 1081 sigcontext_base + SIGCONTEXT_FPCSR);
d0e64392
MR		 1082
1083 if (regs->dspctl != -1)
1084 trad_frame_set_reg_addr (this_cache,
1085 regs->dspctl + gdbarch_num_regs (gdbarch),
1086 sigcontext_base + SIGCONTEXT_DSPCTL);
1087
f57d151a 1088 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1089 regs->hi + gdbarch_num_regs (gdbarch),
37c4d197 1090 regs_base + SIGCONTEXT_HI);
f57d151a 1091 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1092 regs->lo + gdbarch_num_regs (gdbarch),
37c4d197 1093 regs_base + SIGCONTEXT_LO);
d0e64392
MR		 1094
1095 if (regs->dspacc != -1)
1096 {
1097 trad_frame_set_reg_addr (this_cache,
1098 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1099 sigcontext_base + SIGCONTEXT_HI1);
1100 trad_frame_set_reg_addr (this_cache,
1101 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1102 sigcontext_base + SIGCONTEXT_LO1);
1103 trad_frame_set_reg_addr (this_cache,
1104 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1105 sigcontext_base + SIGCONTEXT_HI2);
1106 trad_frame_set_reg_addr (this_cache,
1107 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1108 sigcontext_base + SIGCONTEXT_LO2);
1109 trad_frame_set_reg_addr (this_cache,
1110 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1111 sigcontext_base + SIGCONTEXT_HI3);
1112 trad_frame_set_reg_addr (this_cache,
1113 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1114 sigcontext_base + SIGCONTEXT_LO3);
1115 }
1116 else
1117 {
1118 trad_frame_set_reg_addr (this_cache,
1119 regs->cause + gdbarch_num_regs (gdbarch),
1120 sigcontext_base + SIGCONTEXT_CAUSE);
1121 trad_frame_set_reg_addr (this_cache,
1122 regs->badvaddr + gdbarch_num_regs (gdbarch),
1123 sigcontext_base + SIGCONTEXT_BADVADDR);
1124 }
5792a79b
DJ		 1125
1126 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1127 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1128}
1129
1130/* *INDENT-OFF* */
1131/* For N32/N64 things look different. There is no non-rt signal frame.
1132
1133 struct rt_sigframe_n32 {
1134 u32 rs_ass[4]; [ argument save space for o32 ]
eb195664 1135 u32 rs_code[2]; [ signal trampoline or fill ]
5792a79b
DJ		 1136 struct siginfo rs_info;
1137 struct ucontextn32 rs_uc;
1138 };
1139
1140 struct ucontextn32 {
1141 u32 uc_flags;
1142 s32 uc_link;
1143 stack32_t uc_stack;
1144 struct sigcontext uc_mcontext;
1145 sigset_t uc_sigmask; [ mask last for extensibility ]
1146 };
295093a4 1147
e741f4d4 1148 struct rt_sigframe {
5792a79b
DJ		 1149 u32 rs_ass[4]; [ argument save space for o32 ]
1150 u32 rs_code[2]; [ signal trampoline ]
1151 struct siginfo rs_info;
1152 struct ucontext rs_uc;
1153 };
1154
1155 struct ucontext {
1156 unsigned long uc_flags;
1157 struct ucontext *uc_link;
1158 stack_t uc_stack;
1159 struct sigcontext uc_mcontext;
1160 sigset_t uc_sigmask; [ mask last for extensibility ]
1161 };
1162
1163 And the sigcontext is different (this is for both n32 and n64):
1164
1165 struct sigcontext {
1166 unsigned long long sc_regs[32];
1167 unsigned long long sc_fpregs[32];
1168 unsigned long long sc_mdhi;
e741f4d4
DJ		 1169 unsigned long long sc_hi1;
1170 unsigned long long sc_hi2;
1171 unsigned long long sc_hi3;
5792a79b 1172 unsigned long long sc_mdlo;
e741f4d4
DJ		 1173 unsigned long long sc_lo1;
1174 unsigned long long sc_lo2;
1175 unsigned long long sc_lo3;
5792a79b 1176 unsigned long long sc_pc;
5792a79b 1177 unsigned int sc_fpc_csr;
5792a79b 1178 unsigned int sc_used_math;
e741f4d4
DJ		 1179 unsigned int sc_dsp;
1180 unsigned int sc_reserved;
1181 };
1182
1183 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1184 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1185 included too. */
5792a79b
DJ		 1186/* *INDENT-ON* */
1187
1188#define N32_STACK_T_SIZE STACK_T_SIZE
1189#define N64_STACK_T_SIZE (2 * 8 + 4)
1190#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1191#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1192#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1193 + RTSIGFRAME_SIGINFO_SIZE \
1194 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1195#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1196 + RTSIGFRAME_SIGINFO_SIZE \
1197 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1198
1199#define N64_SIGCONTEXT_REGS (0 * 8)
1200#define N64_SIGCONTEXT_FPREGS (32 * 8)
1201#define N64_SIGCONTEXT_HI (64 * 8)
d0e64392
MR		 1202#define N64_SIGCONTEXT_HI1 (65 * 8)
1203#define N64_SIGCONTEXT_HI2 (66 * 8)
1204#define N64_SIGCONTEXT_HI3 (67 * 8)
e741f4d4 1205#define N64_SIGCONTEXT_LO (68 * 8)
d0e64392
MR		 1206#define N64_SIGCONTEXT_LO1 (69 * 8)
1207#define N64_SIGCONTEXT_LO2 (70 * 8)
1208#define N64_SIGCONTEXT_LO3 (71 * 8)
e741f4d4 1209#define N64_SIGCONTEXT_PC (72 * 8)
d0e64392
MR		 1210#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
1211#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
5792a79b
DJ		 1212
1213#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1214
5792a79b
DJ		 1215static void
1216mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 1217 struct frame_info *this_frame,
5792a79b
DJ		 1218 struct trad_frame_cache *this_cache,
1219 CORE_ADDR func)
1220{
b8a22b94 1221 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1222 int ireg;
eb195664
DD		 1223 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1224 CORE_ADDR sigcontext_base;
2eb4d78b 1225 const struct mips_regnum *regs = mips_regnum (gdbarch);
5792a79b
DJ		 1226
1227 if (self == &mips_linux_n32_rt_sigframe)
eb195664 1228 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1229 else
eb195664 1230 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1231
2eb4d78b 1232 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1233 trad_frame_set_reg_addr (this_cache,
1234 (MIPS_RESTART_REGNUM
2eb4d78b 1235 + gdbarch_num_regs (gdbarch)),
822b6570 1236 sigcontext_base + N64_SIGCONTEXT_REGS);
5792a79b
DJ		 1237
1238 for (ireg = 1; ireg < 32; ireg++)
295093a4 1239 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1240 (ireg + MIPS_ZERO_REGNUM
1241 + gdbarch_num_regs (gdbarch)),
1242 (sigcontext_base + N64_SIGCONTEXT_REGS
1243 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b
DJ		 1244
1245 for (ireg = 0; ireg < 32; ireg++)
f57d151a 1246 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1247 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1248 (sigcontext_base + N64_SIGCONTEXT_FPREGS
1249 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b 1250
f57d151a 1251 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1252 regs->pc + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1253 sigcontext_base + N64_SIGCONTEXT_PC);
1254
295093a4 1255 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1256 (regs->fp_control_status
1257 + gdbarch_num_regs (gdbarch)),
5792a79b 1258 sigcontext_base + N64_SIGCONTEXT_FPCSR);
d0e64392 1259
f57d151a 1260 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1261 regs->hi + gdbarch_num_regs (gdbarch),
5792a79b 1262 sigcontext_base + N64_SIGCONTEXT_HI);
f57d151a 1263 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1264 regs->lo + gdbarch_num_regs (gdbarch),
5792a79b 1265 sigcontext_base + N64_SIGCONTEXT_LO);
5792a79b 1266
d0e64392
MR		 1267 if (regs->dspacc != -1)
1268 {
1269 trad_frame_set_reg_addr (this_cache,
1270 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1271 sigcontext_base + N64_SIGCONTEXT_HI1);
1272 trad_frame_set_reg_addr (this_cache,
1273 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1274 sigcontext_base + N64_SIGCONTEXT_LO1);
1275 trad_frame_set_reg_addr (this_cache,
1276 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1277 sigcontext_base + N64_SIGCONTEXT_HI2);
1278 trad_frame_set_reg_addr (this_cache,
1279 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1280 sigcontext_base + N64_SIGCONTEXT_LO2);
1281 trad_frame_set_reg_addr (this_cache,
1282 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1283 sigcontext_base + N64_SIGCONTEXT_HI3);
1284 trad_frame_set_reg_addr (this_cache,
1285 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1286 sigcontext_base + N64_SIGCONTEXT_LO3);
1287 }
1288 if (regs->dspctl != -1)
1289 trad_frame_set_reg_addr (this_cache,
1290 regs->dspctl + gdbarch_num_regs (gdbarch),
1291 sigcontext_base + N64_SIGCONTEXT_DSPCTL);
1292
5792a79b 1293 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1294 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1295}
1296
5a439849
MR		 1297/* Implement the "write_pc" gdbarch method. */
1298
822b6570 1299static void
61a1198a 1300mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
822b6570 1301{
2eb4d78b 1302 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5a439849
MR		 1303
1304 mips_write_pc (regcache, pc);
822b6570
DJ		 1305
1306 /* Clear the syscall restart flag. */
2eb4d78b 1307 if (mips_linux_restart_reg_p (gdbarch))
61a1198a 1308 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
822b6570
DJ		 1309}
1310
1311/* Return 1 if MIPS_RESTART_REGNUM is usable. */
1312
1313int
1314mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1315{
1316 /* If we do not have a target description with registers, then
1317 MIPS_RESTART_REGNUM will not be included in the register set. */
1318 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1319 return 0;
1320
1321 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1322 either be GPR-sized or missing. */
1323 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1324}
9f62d0e2 1325
e38d4e1a
DJ		 1326/* When FRAME is at a syscall instruction, return the PC of the next
1327 instruction to be executed. */
1328
63807e1d 1329static CORE_ADDR
e38d4e1a
DJ		 1330mips_linux_syscall_next_pc (struct frame_info *frame)
1331{
1332 CORE_ADDR pc = get_frame_pc (frame);
1333 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1334
1335 /* If we are about to make a sigreturn syscall, use the unwinder to
1336 decode the signal frame. */
1337 if (v0 == MIPS_NR_sigreturn
1338 || v0 == MIPS_NR_rt_sigreturn
1339 || v0 == MIPS_NR_N64_rt_sigreturn
1340 || v0 == MIPS_NR_N32_rt_sigreturn)
c7ce8faa 1341 return frame_unwind_caller_pc (get_current_frame ());
e38d4e1a
DJ		 1342
1343 return pc + 4;
1344}
1345
385203ed
DD		 1346/* Return the current system call's number present in the
1347 v0 register. When the function fails, it returns -1. */
1348
1349static LONGEST
1350mips_linux_get_syscall_number (struct gdbarch *gdbarch,
1351 ptid_t ptid)
1352{
1353 struct regcache *regcache = get_thread_regcache (ptid);
1354 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1355 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1356 int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
1357 /* The content of a register */
1358 gdb_byte buf[8];
1359 /* The result */
1360 LONGEST ret;
1361
1362 /* Make sure we're in a known ABI */
1363 gdb_assert (tdep->mips_abi == MIPS_ABI_O32
1364 || tdep->mips_abi == MIPS_ABI_N32
1365 || tdep->mips_abi == MIPS_ABI_N64);
1366
1367 gdb_assert (regsize <= sizeof (buf));
1368
1369 /* Getting the system call number from the register.
1370 syscall number is in v0 or $2. */
1371 regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
1372
1373 ret = extract_signed_integer (buf, regsize, byte_order);
1374
1375 return ret;
1376}
1377
eb14d406
SDJ		 1378/* Implementation of `gdbarch_gdb_signal_to_target', as defined in
1379 gdbarch.h. */
1380
1381static int
1382mips_gdb_signal_to_target (struct gdbarch *gdbarch,
1383 enum gdb_signal signal)
1384{
1385 switch (signal)
1386 {
1387 case GDB_SIGNAL_EMT:
1388 return MIPS_LINUX_SIGEMT;
1389
1390 case GDB_SIGNAL_BUS:
1391 return MIPS_LINUX_SIGBUS;
1392
1393 case GDB_SIGNAL_SYS:
1394 return MIPS_LINUX_SIGSYS;
1395
1396 case GDB_SIGNAL_USR1:
1397 return MIPS_LINUX_SIGUSR1;
1398
1399 case GDB_SIGNAL_USR2:
1400 return MIPS_LINUX_SIGUSR2;
1401
1402 case GDB_SIGNAL_CHLD:
1403 return MIPS_LINUX_SIGCHLD;
1404
1405 case GDB_SIGNAL_PWR:
1406 return MIPS_LINUX_SIGPWR;
1407
1408 case GDB_SIGNAL_WINCH:
1409 return MIPS_LINUX_SIGWINCH;
1410
1411 case GDB_SIGNAL_URG:
1412 return MIPS_LINUX_SIGURG;
1413
1414 case GDB_SIGNAL_IO:
1415 return MIPS_LINUX_SIGIO;
1416
1417 case GDB_SIGNAL_POLL:
1418 return MIPS_LINUX_SIGPOLL;
1419
1420 case GDB_SIGNAL_STOP:
1421 return MIPS_LINUX_SIGSTOP;
1422
1423 case GDB_SIGNAL_TSTP:
1424 return MIPS_LINUX_SIGTSTP;
1425
1426 case GDB_SIGNAL_CONT:
1427 return MIPS_LINUX_SIGCONT;
1428
1429 case GDB_SIGNAL_TTIN:
1430 return MIPS_LINUX_SIGTTIN;
1431
1432 case GDB_SIGNAL_TTOU:
1433 return MIPS_LINUX_SIGTTOU;
1434
1435 case GDB_SIGNAL_VTALRM:
1436 return MIPS_LINUX_SIGVTALRM;
1437
1438 case GDB_SIGNAL_PROF:
1439 return MIPS_LINUX_SIGPROF;
1440
1441 case GDB_SIGNAL_XCPU:
1442 return MIPS_LINUX_SIGXCPU;
1443
1444 case GDB_SIGNAL_XFSZ:
1445 return MIPS_LINUX_SIGXFSZ;
1446
1447 /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>,
1448 therefore we have to handle it here. */
1449 case GDB_SIGNAL_REALTIME_32:
1450 return MIPS_LINUX_SIGRTMIN;
1451 }
1452
1453 if (signal >= GDB_SIGNAL_REALTIME_33
1454 && signal <= GDB_SIGNAL_REALTIME_63)
1455 {
1456 int offset = signal - GDB_SIGNAL_REALTIME_33;
1457
1458 return MIPS_LINUX_SIGRTMIN + 1 + offset;
1459 }
1460 else if (signal >= GDB_SIGNAL_REALTIME_64
1461 && signal <= GDB_SIGNAL_REALTIME_127)
1462 {
1463 int offset = signal - GDB_SIGNAL_REALTIME_64;
1464
1465 return MIPS_LINUX_SIGRT64 + offset;
1466 }
1467
1468 return linux_gdb_signal_to_target (gdbarch, signal);
1469}
1470
7d266584 1471/* Translate signals based on MIPS signal values.
232b8704
ME		 1472 Adapted from gdb/common/signals.c. */
1473
1474static enum gdb_signal
eb14d406 1475mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal)
232b8704 1476{
eb14d406 1477 switch (signal)
232b8704 1478 {
eb14d406 1479 case MIPS_LINUX_SIGEMT:
232b8704 1480 return GDB_SIGNAL_EMT;
eb14d406
SDJ		 1481
1482 case MIPS_LINUX_SIGBUS:
232b8704 1483 return GDB_SIGNAL_BUS;
eb14d406
SDJ		 1484
1485 case MIPS_LINUX_SIGSYS:
232b8704 1486 return GDB_SIGNAL_SYS;
eb14d406
SDJ		 1487
1488 case MIPS_LINUX_SIGUSR1:
232b8704 1489 return GDB_SIGNAL_USR1;
eb14d406
SDJ		 1490
1491 case MIPS_LINUX_SIGUSR2:
232b8704 1492 return GDB_SIGNAL_USR2;
eb14d406
SDJ		 1493
1494 case MIPS_LINUX_SIGCHLD:
232b8704 1495 return GDB_SIGNAL_CHLD;
eb14d406
SDJ		 1496
1497 case MIPS_LINUX_SIGPWR:
232b8704 1498 return GDB_SIGNAL_PWR;
eb14d406
SDJ		 1499
1500 case MIPS_LINUX_SIGWINCH:
232b8704 1501 return GDB_SIGNAL_WINCH;
eb14d406
SDJ		 1502
1503 case MIPS_LINUX_SIGURG:
232b8704 1504 return GDB_SIGNAL_URG;
eb14d406
SDJ		 1505
1506 /* No way to differentiate between SIGIO and SIGPOLL.
1507 Therefore, we just handle the first one. */
1508 case MIPS_LINUX_SIGIO:
1509 return GDB_SIGNAL_IO;
1510
1511 case MIPS_LINUX_SIGSTOP:
232b8704 1512 return GDB_SIGNAL_STOP;
eb14d406
SDJ		 1513
1514 case MIPS_LINUX_SIGTSTP:
232b8704 1515 return GDB_SIGNAL_TSTP;
eb14d406
SDJ		 1516
1517 case MIPS_LINUX_SIGCONT:
232b8704 1518 return GDB_SIGNAL_CONT;
eb14d406
SDJ		 1519
1520 case MIPS_LINUX_SIGTTIN:
232b8704 1521 return GDB_SIGNAL_TTIN;
eb14d406
SDJ		 1522
1523 case MIPS_LINUX_SIGTTOU:
232b8704 1524 return GDB_SIGNAL_TTOU;
eb14d406
SDJ		 1525
1526 case MIPS_LINUX_SIGVTALRM:
232b8704 1527 return GDB_SIGNAL_VTALRM;
eb14d406
SDJ		 1528
1529 case MIPS_LINUX_SIGPROF:
232b8704 1530 return GDB_SIGNAL_PROF;
eb14d406
SDJ		 1531
1532 case MIPS_LINUX_SIGXCPU:
232b8704 1533 return GDB_SIGNAL_XCPU;
eb14d406
SDJ		 1534
1535 case MIPS_LINUX_SIGXFSZ:
232b8704 1536 return GDB_SIGNAL_XFSZ;
eb14d406 1537 }
232b8704 1538
eb14d406 1539 if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX)
232b8704
ME		 1540 {
1541 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
1542 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
eb14d406
SDJ		 1543 int offset = signal - MIPS_LINUX_SIGRTMIN;
1544
1545 if (offset == 0)
232b8704 1546 return GDB_SIGNAL_REALTIME_32;
eb14d406
SDJ		 1547 else if (offset < 32)
1548 return (enum gdb_signal) (offset - 1
1549 + (int) GDB_SIGNAL_REALTIME_33);
232b8704 1550 else
eb14d406
SDJ		 1551 return (enum gdb_signal) (offset - 32
1552 + (int) GDB_SIGNAL_REALTIME_64);
232b8704
ME		 1553 }
1554
eb14d406 1555 return linux_gdb_signal_from_target (gdbarch, signal);
232b8704
ME		 1556}
1557
5792a79b
DJ		 1558/* Initialize one of the GNU/Linux OS ABIs. */
1559
19ed69dd 1560static void
295093a4
MS		 1561mips_linux_init_abi (struct gdbarch_info info,
1562 struct gdbarch *gdbarch)
19ed69dd 1563{
96f026fc
KB		 1564 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1565 enum mips_abi abi = mips_abi (gdbarch);
822b6570 1566 struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info;
96f026fc 1567
a5ee0f0c
PA		 1568 linux_init_abi (info, gdbarch);
1569
385203ed
DD		 1570 /* Get the syscall number from the arch's register. */
1571 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
1572
96f026fc
KB		 1573 switch (abi)
1574 {
1575 case MIPS_ABI_O32:
1576 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1577 mips_linux_get_longjmp_target);
96f026fc 1578 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1579 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
fb2be677
AC		 1580 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1581 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
385203ed 1582 set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml");
96f026fc
KB		 1583 break;
1584 case MIPS_ABI_N32:
1585 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1586 mips_linux_get_longjmp_target);
96f026fc 1587 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1588 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
d05f6826
DJ		 1589 set_gdbarch_long_double_bit (gdbarch, 128);
1590 /* These floatformats should probably be renamed. MIPS uses
1591 the same 128-bit IEEE floating point format that IA-64 uses,
1592 except that the quiet/signalling NaN bit is reversed (GDB
1593 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1594 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
fb2be677 1595 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
385203ed 1596 set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml");
96f026fc
KB		 1597 break;
1598 case MIPS_ABI_N64:
1599 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1600 mips64_linux_get_longjmp_target);
96f026fc 1601 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1602 (gdbarch, svr4_lp64_fetch_link_map_offsets);
d05f6826
DJ		 1603 set_gdbarch_long_double_bit (gdbarch, 128);
1604 /* These floatformats should probably be renamed. MIPS uses
1605 the same 128-bit IEEE floating point format that IA-64 uses,
1606 except that the quiet/signalling NaN bit is reversed (GDB
1607 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1608 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
fb2be677 1609 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
385203ed 1610 set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml");
96f026fc
KB		 1611 break;
1612 default:
96f026fc
KB		 1613 break;
1614 }
6de918a6
DJ		 1615
1616 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1617
0d0266c6 1618 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1619
1620 /* Enable TLS support. */
1621 set_gdbarch_fetch_tls_load_module_address (gdbarch,
7d266584 1622 svr4_fetch_objfile_link_map);
7d522c90
DJ		 1623
1624 /* Initialize this lazily, to avoid an initialization order
1625 dependency on solib-svr4.c's _initialize routine. */
1626 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1627 {
1628 mips_svr4_so_ops = svr4_so_ops;
1629 mips_svr4_so_ops.in_dynsym_resolve_code
1630 = mips_linux_in_dynsym_resolve_code;
1631 }
1632 set_solib_ops (gdbarch, &mips_svr4_so_ops);
822b6570
DJ		 1633
1634 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1635
4eb0ad19
DJ		 1636 set_gdbarch_core_read_description (gdbarch,
1637 mips_linux_core_read_description);
1638
50e8a0d5
HZ		 1639 set_gdbarch_regset_from_core_section (gdbarch,
1640 mips_linux_regset_from_core_section);
1641
232b8704
ME		 1642 set_gdbarch_gdb_signal_from_target (gdbarch,
1643 mips_gdb_signal_from_target);
1644
eb14d406
SDJ		 1645 set_gdbarch_gdb_signal_to_target (gdbarch,
1646 mips_gdb_signal_to_target);
1647
e38d4e1a
DJ		 1648 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1649
822b6570
DJ		 1650 if (tdesc_data)
1651 {
1652 const struct tdesc_feature *feature;
1653
1654 /* If we have target-described registers, then we can safely
1655 reserve a number for MIPS_RESTART_REGNUM (whether it is
1656 described or not). */
1657 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1658 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
cf233303 1659 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
822b6570
DJ		 1660
1661 /* If it's present, then assign it to the reserved number. */
1662 feature = tdesc_find_feature (info.target_desc,
1663 "org.gnu.gdb.mips.linux");
1664 if (feature != NULL)
1665 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1666 "restart");
1667 }
19ed69dd
KB		 1668}
1669
63807e1d
PA		 1670/* Provide a prototype to silence -Wmissing-prototypes. */
1671extern initialize_file_ftype _initialize_mips_linux_tdep;
1672
2aa830e4 1673void
d1bacddc 1674_initialize_mips_linux_tdep (void)
2aa830e4 1675{
96f026fc
KB		 1676 const struct bfd_arch_info *arch_info;
1677
96f026fc
KB		 1678 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1679 arch_info != NULL;
1680 arch_info = arch_info->next)
1681 {
295093a4
MS		 1682 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1683 GDB_OSABI_LINUX,
96f026fc
KB		 1684 mips_linux_init_abi);
1685 }
2aa830e4 1686}
GDB Binutils - Deliverables
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