Commit | Line | Data |
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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
0b302171 | 3 | Copyright (C) 2001-2002, 2004-2012 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
19ed69dd | 26 | #include "gdb_string.h" |
96f026fc | 27 | #include "gdb_assert.h" |
6de918a6 | 28 | #include "frame.h" |
2fdf551c | 29 | #include "regcache.h" |
5792a79b DJ |
30 | #include "trad-frame.h" |
31 | #include "tramp-frame.h" | |
e6bb342a | 32 | #include "gdbtypes.h" |
5ea03926 | 33 | #include "solib.h" |
7d522c90 DJ |
34 | #include "solib-svr4.h" |
35 | #include "solist.h" | |
982e9687 | 36 | #include "symtab.h" |
822b6570 | 37 | #include "target-descriptions.h" |
50e8a0d5 | 38 | #include "regset.h" |
d37eb719 | 39 | #include "mips-linux-tdep.h" |
db5f024e | 40 | #include "glibc-tdep.h" |
a5ee0f0c | 41 | #include "linux-tdep.h" |
385203ed | 42 | #include "xml-syscall.h" |
2aa830e4 | 43 | |
7d522c90 DJ |
44 | static struct target_so_ops mips_svr4_so_ops; |
45 | ||
2aa830e4 | 46 | /* Figure out where the longjmp will land. |
295093a4 MS |
47 | We expect the first arg to be a pointer to the jmp_buf structure |
48 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
49 | at. The pc is copied into PC. This routine returns 1 on | |
50 | success. */ | |
2aa830e4 | 51 | |
19ed69dd KB |
52 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
53 | #define MIPS_LINUX_JB_PC 0 | |
54 | ||
55 | static int | |
60ade65d | 56 | mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
2aa830e4 DJ |
57 | { |
58 | CORE_ADDR jb_addr; | |
2eb4d78b | 59 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 60 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b | 61 | char buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 62 | |
60ade65d | 63 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 64 | |
bf072999 | 65 | if (target_read_memory (jb_addr |
819844ad | 66 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
2eb4d78b | 67 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
68 | return 0; |
69 | ||
819844ad | 70 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
71 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
72 | byte_order); | |
2aa830e4 DJ |
73 | |
74 | return 1; | |
75 | } | |
76 | ||
4246e332 | 77 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
78 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
79 | is 8. */ | |
96f026fc KB |
80 | |
81 | static void | |
28f5035f | 82 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 83 | { |
e17a4113 UW |
84 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
85 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d37eb719 | 86 | gdb_byte buf[MAX_REGISTER_SIZE]; |
e17a4113 UW |
87 | store_signed_integer (buf, register_size (gdbarch, regnum), byte_order, |
88 | extract_signed_integer (addr, 4, byte_order)); | |
28f5035f | 89 | regcache_raw_supply (regcache, regnum, buf); |
96f026fc KB |
90 | } |
91 | ||
2aa830e4 DJ |
92 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
93 | ||
d37eb719 | 94 | void |
28f5035f UW |
95 | mips_supply_gregset (struct regcache *regcache, |
96 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
97 | { |
98 | int regi; | |
28f5035f | 99 | const mips_elf_greg_t *regp = *gregsetp; |
d9d9c31f | 100 | char zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 101 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
bf072999 | 102 | |
d9d9c31f | 103 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 | 104 | |
822b6570 | 105 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 106 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 107 | |
2eb4d78b | 108 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
109 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
110 | ||
2eb4d78b UW |
111 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
112 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 113 | |
2eb4d78b | 114 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 115 | regp + EF_CP0_EPC); |
2eb4d78b | 116 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
117 | regp + EF_CP0_BADVADDR); |
118 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 119 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 120 | regp + EF_CP0_CAUSE); |
2aa830e4 | 121 | |
1faeff08 | 122 | /* Fill the inaccessible zero register with zero. */ |
822b6570 | 123 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
2aa830e4 DJ |
124 | } |
125 | ||
50e8a0d5 HZ |
126 | static void |
127 | mips_supply_gregset_wrapper (const struct regset *regset, | |
128 | struct regcache *regcache, | |
129 | int regnum, const void *gregs, size_t len) | |
130 | { | |
131 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
132 | ||
133 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
134 | } | |
135 | ||
2aa830e4 DJ |
136 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
137 | ||
d37eb719 | 138 | void |
28f5035f UW |
139 | mips_fill_gregset (const struct regcache *regcache, |
140 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 141 | { |
2eb4d78b | 142 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2aa830e4 | 143 | int regaddr, regi; |
d37eb719 | 144 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 145 | void *dst; |
2aa830e4 DJ |
146 | |
147 | if (regno == -1) | |
148 | { | |
d37eb719 | 149 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 150 | for (regi = 1; regi < 32; regi++) |
28f5035f | 151 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
152 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
153 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
154 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
155 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 156 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 157 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 158 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
159 | return; |
160 | } | |
161 | ||
822b6570 | 162 | if (regno > 0 && regno < 32) |
2aa830e4 | 163 | { |
2aa830e4 | 164 | dst = regp + regno + EF_REG0; |
28f5035f | 165 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
166 | return; |
167 | } | |
168 | ||
2eb4d78b UW |
169 | if (regno == mips_regnum (gdbarch)->lo) |
170 | regaddr = EF_LO; | |
171 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 172 | regaddr = EF_HI; |
2eb4d78b | 173 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 174 | regaddr = EF_CP0_EPC; |
2eb4d78b | 175 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 176 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 177 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 178 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 179 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 180 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 181 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
182 | && regno == MIPS_RESTART_REGNUM) |
183 | regaddr = EF_REG0; | |
56cea623 AC |
184 | else |
185 | regaddr = -1; | |
2aa830e4 DJ |
186 | |
187 | if (regaddr != -1) | |
188 | { | |
2aa830e4 | 189 | dst = regp + regaddr; |
28f5035f | 190 | regcache_raw_collect (regcache, regno, dst); |
2aa830e4 DJ |
191 | } |
192 | } | |
193 | ||
50e8a0d5 HZ |
194 | static void |
195 | mips_fill_gregset_wrapper (const struct regset *regset, | |
196 | const struct regcache *regcache, | |
197 | int regnum, void *gregs, size_t len) | |
198 | { | |
199 | gdb_assert (len == sizeof (mips_elf_gregset_t)); | |
200 | ||
201 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
202 | } | |
203 | ||
2aa830e4 DJ |
204 | /* Likewise, unpack an elf_fpregset_t. */ |
205 | ||
d37eb719 | 206 | void |
28f5035f UW |
207 | mips_supply_fpregset (struct regcache *regcache, |
208 | const mips_elf_fpregset_t *fpregsetp) | |
2aa830e4 | 209 | { |
2eb4d78b | 210 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 211 | int regi; |
d9d9c31f | 212 | char zerobuf[MAX_REGISTER_SIZE]; |
bf072999 | 213 | |
d9d9c31f | 214 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
2aa830e4 DJ |
215 | |
216 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 217 | regcache_raw_supply (regcache, |
2eb4d78b | 218 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 219 | *fpregsetp + regi); |
2aa830e4 | 220 | |
28f5035f | 221 | regcache_raw_supply (regcache, |
2eb4d78b | 222 | mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 223 | *fpregsetp + 32); |
2aa830e4 | 224 | |
295093a4 | 225 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
28f5035f | 226 | regcache_raw_supply (regcache, |
2eb4d78b | 227 | mips_regnum (gdbarch)->fp_implementation_revision, |
23a6d369 | 228 | zerobuf); |
2aa830e4 DJ |
229 | } |
230 | ||
50e8a0d5 HZ |
231 | static void |
232 | mips_supply_fpregset_wrapper (const struct regset *regset, | |
233 | struct regcache *regcache, | |
234 | int regnum, const void *gregs, size_t len) | |
235 | { | |
236 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
237 | ||
238 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs); | |
239 | } | |
240 | ||
2aa830e4 DJ |
241 | /* Likewise, pack one or all floating point registers into an |
242 | elf_fpregset_t. */ | |
243 | ||
d37eb719 | 244 | void |
28f5035f UW |
245 | mips_fill_fpregset (const struct regcache *regcache, |
246 | mips_elf_fpregset_t *fpregsetp, int regno) | |
2aa830e4 | 247 | { |
2eb4d78b | 248 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
22e048c9 | 249 | char *to; |
2aa830e4 | 250 | |
2eb4d78b UW |
251 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
252 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
2aa830e4 | 253 | { |
2eb4d78b | 254 | to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch)); |
28f5035f | 255 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 | 256 | } |
2eb4d78b | 257 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
2aa830e4 | 258 | { |
2aa830e4 | 259 | to = (char *) (*fpregsetp + 32); |
28f5035f | 260 | regcache_raw_collect (regcache, regno, to); |
2aa830e4 DJ |
261 | } |
262 | else if (regno == -1) | |
263 | { | |
264 | int regi; | |
265 | ||
266 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 267 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 268 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 269 | mips_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 270 | mips_regnum (gdbarch)->fp_control_status); |
2aa830e4 DJ |
271 | } |
272 | } | |
273 | ||
50e8a0d5 HZ |
274 | static void |
275 | mips_fill_fpregset_wrapper (const struct regset *regset, | |
276 | const struct regcache *regcache, | |
277 | int regnum, void *gregs, size_t len) | |
278 | { | |
279 | gdb_assert (len == sizeof (mips_elf_fpregset_t)); | |
280 | ||
281 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum); | |
282 | } | |
283 | ||
96f026fc KB |
284 | /* Support for 64-bit ABIs. */ |
285 | ||
96f026fc | 286 | /* Figure out where the longjmp will land. |
295093a4 MS |
287 | We expect the first arg to be a pointer to the jmp_buf structure |
288 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
289 | at. The pc is copied into PC. This routine returns 1 on | |
290 | success. */ | |
96f026fc KB |
291 | |
292 | /* Details about jmp_buf. */ | |
293 | ||
294 | #define MIPS64_LINUX_JB_PC 0 | |
295 | ||
296 | static int | |
60ade65d | 297 | mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
96f026fc KB |
298 | { |
299 | CORE_ADDR jb_addr; | |
2eb4d78b | 300 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 301 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2eb4d78b UW |
302 | void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); |
303 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; | |
96f026fc | 304 | |
60ade65d | 305 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
306 | |
307 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 308 | buf, |
2eb4d78b | 309 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
310 | return 0; |
311 | ||
819844ad | 312 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
313 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
314 | byte_order); | |
96f026fc KB |
315 | |
316 | return 1; | |
317 | } | |
318 | ||
d37eb719 DJ |
319 | /* Register set support functions. These operate on standard 64-bit |
320 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
321 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
322 | ||
323 | /* Supply a 64-bit register. */ | |
96f026fc | 324 | |
63807e1d | 325 | static void |
28f5035f UW |
326 | supply_64bit_reg (struct regcache *regcache, int regnum, |
327 | const gdb_byte *buf) | |
d37eb719 | 328 | { |
2eb4d78b UW |
329 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
330 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG | |
331 | && register_size (gdbarch, regnum) == 4) | |
28f5035f | 332 | regcache_raw_supply (regcache, regnum, buf + 4); |
d37eb719 | 333 | else |
28f5035f | 334 | regcache_raw_supply (regcache, regnum, buf); |
d37eb719 DJ |
335 | } |
336 | ||
337 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
338 | ||
339 | void | |
28f5035f UW |
340 | mips64_supply_gregset (struct regcache *regcache, |
341 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
342 | { |
343 | int regi; | |
28f5035f | 344 | const mips64_elf_greg_t *regp = *gregsetp; |
d37eb719 | 345 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
2eb4d78b | 346 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
96f026fc | 347 | |
d9d9c31f | 348 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
96f026fc | 349 | |
822b6570 | 350 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f UW |
351 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
352 | (const gdb_byte *)(regp + regi)); | |
353 | ||
2eb4d78b | 354 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
355 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
356 | (const gdb_byte *)(regp + MIPS64_EF_REG0)); | |
357 | ||
2eb4d78b | 358 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 359 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 360 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
361 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
362 | ||
2eb4d78b | 363 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 364 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 365 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
366 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
367 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
368 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 369 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 370 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc | 371 | |
1faeff08 | 372 | /* Fill the inaccessible zero register with zero. */ |
822b6570 | 373 | regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); |
96f026fc KB |
374 | } |
375 | ||
50e8a0d5 HZ |
376 | static void |
377 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
378 | struct regcache *regcache, | |
379 | int regnum, const void *gregs, size_t len) | |
380 | { | |
381 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
382 | ||
383 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
384 | } | |
385 | ||
d37eb719 | 386 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 387 | |
d37eb719 | 388 | void |
28f5035f UW |
389 | mips64_fill_gregset (const struct regcache *regcache, |
390 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 391 | { |
2eb4d78b | 392 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 393 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96f026fc KB |
394 | int regaddr, regi; |
395 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 396 | void *dst; |
96f026fc KB |
397 | |
398 | if (regno == -1) | |
399 | { | |
400 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 401 | for (regi = 1; regi < 32; regi++) |
28f5035f | 402 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
403 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
404 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
405 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
406 | mips64_fill_gregset (regcache, gregsetp, |
407 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 408 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 409 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 410 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
411 | return; |
412 | } | |
413 | ||
822b6570 | 414 | if (regno > 0 && regno < 32) |
d37eb719 | 415 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 416 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 417 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 418 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 419 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 420 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 421 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 422 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 423 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 424 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 425 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 426 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 427 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 428 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
429 | && regno == MIPS_RESTART_REGNUM) |
430 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
431 | else |
432 | regaddr = -1; | |
96f026fc KB |
433 | |
434 | if (regaddr != -1) | |
435 | { | |
d37eb719 DJ |
436 | gdb_byte buf[MAX_REGISTER_SIZE]; |
437 | LONGEST val; | |
438 | ||
28f5035f | 439 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
440 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
441 | byte_order); | |
96f026fc | 442 | dst = regp + regaddr; |
e17a4113 | 443 | store_signed_integer (dst, 8, byte_order, val); |
96f026fc KB |
444 | } |
445 | } | |
446 | ||
50e8a0d5 HZ |
447 | static void |
448 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
449 | const struct regcache *regcache, | |
450 | int regnum, void *gregs, size_t len) | |
451 | { | |
452 | gdb_assert (len == sizeof (mips64_elf_gregset_t)); | |
453 | ||
454 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
455 | } | |
456 | ||
96f026fc KB |
457 | /* Likewise, unpack an elf_fpregset_t. */ |
458 | ||
d37eb719 | 459 | void |
28f5035f UW |
460 | mips64_supply_fpregset (struct regcache *regcache, |
461 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 462 | { |
2eb4d78b | 463 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
52f0bd74 | 464 | int regi; |
96f026fc | 465 | |
d37eb719 DJ |
466 | /* See mips_linux_o32_sigframe_init for a description of the |
467 | peculiar FP register layout. */ | |
2eb4d78b | 468 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
469 | for (regi = 0; regi < 32; regi++) |
470 | { | |
28f5035f | 471 | const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); |
2eb4d78b | 472 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 473 | reg_ptr += 4; |
3e8c568d | 474 | regcache_raw_supply (regcache, |
2eb4d78b | 475 | gdbarch_fp0_regnum (gdbarch) + regi, |
3e8c568d | 476 | reg_ptr); |
d37eb719 DJ |
477 | } |
478 | else | |
479 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 480 | regcache_raw_supply (regcache, |
2eb4d78b | 481 | gdbarch_fp0_regnum (gdbarch) + regi, |
28f5035f | 482 | (const char *)(*fpregsetp + regi)); |
d37eb719 | 483 | |
2eb4d78b | 484 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
28f5035f | 485 | (const gdb_byte *)(*fpregsetp + 32)); |
d37eb719 DJ |
486 | |
487 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
488 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
489 | can do is to assume that its value is present. */ | |
28f5035f | 490 | supply_32bit_reg (regcache, |
2eb4d78b | 491 | mips_regnum (gdbarch)->fp_implementation_revision, |
28f5035f | 492 | (const gdb_byte *)(*fpregsetp + 32) + 4); |
96f026fc KB |
493 | } |
494 | ||
50e8a0d5 HZ |
495 | static void |
496 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
497 | struct regcache *regcache, | |
498 | int regnum, const void *gregs, size_t len) | |
499 | { | |
500 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
501 | ||
502 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
503 | } | |
504 | ||
96f026fc KB |
505 | /* Likewise, pack one or all floating point registers into an |
506 | elf_fpregset_t. */ | |
507 | ||
d37eb719 | 508 | void |
28f5035f UW |
509 | mips64_fill_fpregset (const struct regcache *regcache, |
510 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 511 | { |
2eb4d78b | 512 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 513 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d37eb719 | 514 | gdb_byte *to; |
96f026fc | 515 | |
2eb4d78b UW |
516 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
517 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 518 | { |
d37eb719 DJ |
519 | /* See mips_linux_o32_sigframe_init for a description of the |
520 | peculiar FP register layout. */ | |
2eb4d78b | 521 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 522 | { |
2eb4d78b | 523 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
524 | |
525 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 526 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 527 | to += 4; |
28f5035f | 528 | regcache_raw_collect (regcache, regno, to); |
d37eb719 DJ |
529 | } |
530 | else | |
531 | { | |
025bb325 MS |
532 | to = (gdb_byte *) (*fpregsetp + regno |
533 | - gdbarch_fp0_regnum (gdbarch)); | |
28f5035f | 534 | regcache_raw_collect (regcache, regno, to); |
d37eb719 | 535 | } |
96f026fc | 536 | } |
2eb4d78b | 537 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 538 | { |
d37eb719 DJ |
539 | gdb_byte buf[MAX_REGISTER_SIZE]; |
540 | LONGEST val; | |
541 | ||
28f5035f | 542 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
543 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
544 | byte_order); | |
d37eb719 | 545 | to = (gdb_byte *) (*fpregsetp + 32); |
e17a4113 | 546 | store_signed_integer (to, 4, byte_order, val); |
d37eb719 | 547 | } |
2eb4d78b | 548 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
549 | { |
550 | gdb_byte buf[MAX_REGISTER_SIZE]; | |
551 | LONGEST val; | |
552 | ||
28f5035f | 553 | regcache_raw_collect (regcache, regno, buf); |
e17a4113 UW |
554 | val = extract_signed_integer (buf, register_size (gdbarch, regno), |
555 | byte_order); | |
d37eb719 | 556 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
e17a4113 | 557 | store_signed_integer (to, 4, byte_order, val); |
96f026fc KB |
558 | } |
559 | else if (regno == -1) | |
560 | { | |
561 | int regi; | |
562 | ||
563 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 564 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 565 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 566 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 567 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 568 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b UW |
569 | (mips_regnum (gdbarch) |
570 | ->fp_implementation_revision)); | |
96f026fc KB |
571 | } |
572 | } | |
573 | ||
50e8a0d5 HZ |
574 | static void |
575 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
576 | const struct regcache *regcache, | |
577 | int regnum, void *gregs, size_t len) | |
578 | { | |
579 | gdb_assert (len == sizeof (mips64_elf_fpregset_t)); | |
96f026fc | 580 | |
50e8a0d5 HZ |
581 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
582 | } | |
2aa830e4 | 583 | |
693be288 | 584 | static const struct regset * |
50e8a0d5 HZ |
585 | mips_linux_regset_from_core_section (struct gdbarch *gdbarch, |
586 | const char *sect_name, size_t sect_size) | |
2aa830e4 | 587 | { |
50e8a0d5 | 588 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d37eb719 DJ |
589 | mips_elf_gregset_t gregset; |
590 | mips_elf_fpregset_t fpregset; | |
96f026fc KB |
591 | mips64_elf_gregset_t gregset64; |
592 | mips64_elf_fpregset_t fpregset64; | |
2aa830e4 | 593 | |
50e8a0d5 | 594 | if (strcmp (sect_name, ".reg") == 0) |
2aa830e4 | 595 | { |
50e8a0d5 | 596 | if (sect_size == sizeof (gregset)) |
2aa830e4 | 597 | { |
50e8a0d5 HZ |
598 | if (tdep->gregset == NULL) |
599 | tdep->gregset = regset_alloc (gdbarch, | |
600 | mips_supply_gregset_wrapper, | |
601 | mips_fill_gregset_wrapper); | |
602 | return tdep->gregset; | |
96f026fc | 603 | } |
50e8a0d5 | 604 | else if (sect_size == sizeof (gregset64)) |
96f026fc | 605 | { |
50e8a0d5 HZ |
606 | if (tdep->gregset64 == NULL) |
607 | tdep->gregset64 = regset_alloc (gdbarch, | |
608 | mips64_supply_gregset_wrapper, | |
609 | mips64_fill_gregset_wrapper); | |
610 | return tdep->gregset64; | |
2aa830e4 DJ |
611 | } |
612 | else | |
613 | { | |
8a3fe4f8 | 614 | warning (_("wrong size gregset struct in core file")); |
2aa830e4 DJ |
615 | } |
616 | } | |
50e8a0d5 | 617 | else if (strcmp (sect_name, ".reg2") == 0) |
2aa830e4 | 618 | { |
50e8a0d5 | 619 | if (sect_size == sizeof (fpregset)) |
2aa830e4 | 620 | { |
50e8a0d5 HZ |
621 | if (tdep->fpregset == NULL) |
622 | tdep->fpregset = regset_alloc (gdbarch, | |
623 | mips_supply_fpregset_wrapper, | |
624 | mips_fill_fpregset_wrapper); | |
625 | return tdep->fpregset; | |
96f026fc | 626 | } |
50e8a0d5 | 627 | else if (sect_size == sizeof (fpregset64)) |
96f026fc | 628 | { |
50e8a0d5 HZ |
629 | if (tdep->fpregset64 == NULL) |
630 | tdep->fpregset64 = regset_alloc (gdbarch, | |
631 | mips64_supply_fpregset_wrapper, | |
632 | mips64_fill_fpregset_wrapper); | |
633 | return tdep->fpregset64; | |
2aa830e4 DJ |
634 | } |
635 | else | |
636 | { | |
8a3fe4f8 | 637 | warning (_("wrong size fpregset struct in core file")); |
2aa830e4 DJ |
638 | } |
639 | } | |
2aa830e4 | 640 | |
50e8a0d5 HZ |
641 | return NULL; |
642 | } | |
2aa830e4 | 643 | |
4eb0ad19 DJ |
644 | static const struct target_desc * |
645 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
646 | struct target_ops *target, | |
647 | bfd *abfd) | |
648 | { | |
649 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
650 | if (! section) | |
651 | return NULL; | |
652 | ||
653 | switch (bfd_section_size (abfd, section)) | |
654 | { | |
655 | case sizeof (mips_elf_gregset_t): | |
656 | return mips_tdesc_gp32; | |
657 | ||
658 | case sizeof (mips64_elf_gregset_t): | |
659 | return mips_tdesc_gp64; | |
660 | ||
661 | default: | |
662 | return NULL; | |
663 | } | |
664 | } | |
665 | ||
96f026fc | 666 | |
295093a4 MS |
667 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
668 | Because they aren't in the .plt section, we pattern-match on the | |
669 | code generated by GNU ld. They look like this: | |
6de918a6 DJ |
670 | |
671 | lw t9,0x8010(gp) | |
672 | addu t7,ra | |
673 | jalr t9,ra | |
674 | addiu t8,zero,INDEX | |
675 | ||
295093a4 MS |
676 | (with the appropriate doubleword instructions for N64). Also |
677 | return the dynamic symbol index used in the last instruction. */ | |
6de918a6 DJ |
678 | |
679 | static int | |
680 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) | |
681 | { | |
682 | unsigned char buf[28], *p; | |
683 | ULONGEST insn, insn1; | |
1cf3db46 | 684 | int n64 = (mips_abi (target_gdbarch) == MIPS_ABI_N64); |
e17a4113 | 685 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch); |
6de918a6 DJ |
686 | |
687 | read_memory (pc - 12, buf, 28); | |
688 | ||
689 | if (n64) | |
690 | { | |
691 | /* ld t9,0x8010(gp) */ | |
692 | insn1 = 0xdf998010; | |
693 | } | |
694 | else | |
695 | { | |
696 | /* lw t9,0x8010(gp) */ | |
697 | insn1 = 0x8f998010; | |
698 | } | |
699 | ||
700 | p = buf + 12; | |
701 | while (p >= buf) | |
702 | { | |
e17a4113 | 703 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
704 | if (insn == insn1) |
705 | break; | |
706 | p -= 4; | |
707 | } | |
708 | if (p < buf) | |
709 | return 0; | |
710 | ||
e17a4113 | 711 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
712 | if (n64) |
713 | { | |
714 | /* daddu t7,ra */ | |
715 | if (insn != 0x03e0782d) | |
716 | return 0; | |
717 | } | |
718 | else | |
719 | { | |
720 | /* addu t7,ra */ | |
721 | if (insn != 0x03e07821) | |
722 | return 0; | |
723 | } | |
295093a4 | 724 | |
e17a4113 | 725 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
726 | /* jalr t9,ra */ |
727 | if (insn != 0x0320f809) | |
728 | return 0; | |
729 | ||
e17a4113 | 730 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
731 | if (n64) |
732 | { | |
733 | /* daddiu t8,zero,0 */ | |
734 | if ((insn & 0xffff0000) != 0x64180000) | |
735 | return 0; | |
736 | } | |
737 | else | |
738 | { | |
739 | /* addiu t8,zero,0 */ | |
740 | if ((insn & 0xffff0000) != 0x24180000) | |
741 | return 0; | |
742 | } | |
743 | ||
744 | return (insn & 0xffff); | |
745 | } | |
746 | ||
295093a4 | 747 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 748 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 749 | |
7d522c90 | 750 | static int |
6de918a6 DJ |
751 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
752 | { | |
295093a4 | 753 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 754 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 755 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
756 | return 1; |
757 | ||
295093a4 MS |
758 | /* Pattern match for the stub. It would be nice if there were a |
759 | more efficient way to avoid this check. */ | |
6de918a6 DJ |
760 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
761 | return 1; | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
767 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
768 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 769 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
770 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
771 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
772 | __dl_runtime_resolve, and then pass control to the resolved |
773 | function. */ | |
6de918a6 DJ |
774 | |
775 | static CORE_ADDR | |
776 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
777 | { | |
778 | struct minimal_symbol *resolver; | |
779 | ||
780 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
781 | ||
782 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) | |
c7ce8faa | 783 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 784 | |
db5f024e | 785 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 786 | } |
6de918a6 | 787 | |
5792a79b DJ |
788 | /* Signal trampoline support. There are four supported layouts for a |
789 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
790 | n64 rt_sigframe. We handle them all independently; not the most | |
791 | efficient way, but simplest. First, declare all the unwinders. */ | |
792 | ||
793 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 794 | struct frame_info *this_frame, |
5792a79b DJ |
795 | struct trad_frame_cache *this_cache, |
796 | CORE_ADDR func); | |
797 | ||
798 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 799 | struct frame_info *this_frame, |
5792a79b DJ |
800 | struct trad_frame_cache *this_cache, |
801 | CORE_ADDR func); | |
802 | ||
803 | #define MIPS_NR_LINUX 4000 | |
804 | #define MIPS_NR_N64_LINUX 5000 | |
805 | #define MIPS_NR_N32_LINUX 6000 | |
806 | ||
807 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
808 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
809 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
810 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
811 | ||
812 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
813 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
814 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
815 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
816 | #define MIPS_INST_SYSCALL 0x0000000c | |
817 | ||
2cd8546d AC |
818 | static const struct tramp_frame mips_linux_o32_sigframe = { |
819 | SIGTRAMP_FRAME, | |
5792a79b | 820 | 4, |
2cd8546d AC |
821 | { |
822 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, | |
823 | { MIPS_INST_SYSCALL, -1 }, | |
824 | { TRAMP_SENTINEL_INSN, -1 } | |
825 | }, | |
5792a79b DJ |
826 | mips_linux_o32_sigframe_init |
827 | }; | |
828 | ||
2cd8546d AC |
829 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
830 | SIGTRAMP_FRAME, | |
5792a79b | 831 | 4, |
2cd8546d AC |
832 | { |
833 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, | |
834 | { MIPS_INST_SYSCALL, -1 }, | |
835 | { TRAMP_SENTINEL_INSN, -1 } }, | |
5792a79b DJ |
836 | mips_linux_o32_sigframe_init |
837 | }; | |
838 | ||
2cd8546d AC |
839 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
840 | SIGTRAMP_FRAME, | |
5792a79b | 841 | 4, |
2cd8546d AC |
842 | { |
843 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, | |
844 | { MIPS_INST_SYSCALL, -1 }, | |
845 | { TRAMP_SENTINEL_INSN, -1 } | |
846 | }, | |
5792a79b DJ |
847 | mips_linux_n32n64_sigframe_init |
848 | }; | |
849 | ||
2cd8546d AC |
850 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
851 | SIGTRAMP_FRAME, | |
5792a79b | 852 | 4, |
fcbd8a5c TS |
853 | { |
854 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, | |
855 | { MIPS_INST_SYSCALL, -1 }, | |
856 | { TRAMP_SENTINEL_INSN, -1 } | |
857 | }, | |
5792a79b DJ |
858 | mips_linux_n32n64_sigframe_init |
859 | }; | |
860 | ||
861 | /* *INDENT-OFF* */ | |
862 | /* The unwinder for o32 signal frames. The legacy structures look | |
863 | like this: | |
864 | ||
865 | struct sigframe { | |
866 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 867 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
868 | struct sigcontext sf_sc; |
869 | sigset_t sf_mask; | |
870 | }; | |
871 | ||
d0e64392 MR |
872 | Pre-2.6.12 sigcontext: |
873 | ||
5792a79b DJ |
874 | struct sigcontext { |
875 | unsigned int sc_regmask; [Unused] | |
876 | unsigned int sc_status; | |
877 | unsigned long long sc_pc; | |
878 | unsigned long long sc_regs[32]; | |
879 | unsigned long long sc_fpregs[32]; | |
880 | unsigned int sc_ownedfp; | |
881 | unsigned int sc_fpc_csr; | |
882 | unsigned int sc_fpc_eir; [Unused] | |
883 | unsigned int sc_used_math; | |
884 | unsigned int sc_ssflags; [Unused] | |
885 | [Alignment hole of four bytes] | |
886 | unsigned long long sc_mdhi; | |
887 | unsigned long long sc_mdlo; | |
888 | ||
889 | unsigned int sc_cause; [Unused] | |
890 | unsigned int sc_badvaddr; [Unused] | |
891 | ||
892 | unsigned long sc_sigset[4]; [kernel's sigset_t] | |
893 | }; | |
894 | ||
d0e64392 MR |
895 | Post-2.6.12 sigcontext (SmartMIPS/DSP support added): |
896 | ||
897 | struct sigcontext { | |
898 | unsigned int sc_regmask; [Unused] | |
899 | unsigned int sc_status; [Unused] | |
900 | unsigned long long sc_pc; | |
901 | unsigned long long sc_regs[32]; | |
902 | unsigned long long sc_fpregs[32]; | |
903 | unsigned int sc_acx; | |
904 | unsigned int sc_fpc_csr; | |
905 | unsigned int sc_fpc_eir; [Unused] | |
906 | unsigned int sc_used_math; | |
907 | unsigned int sc_dsp; | |
908 | [Alignment hole of four bytes] | |
909 | unsigned long long sc_mdhi; | |
910 | unsigned long long sc_mdlo; | |
911 | unsigned long sc_hi1; | |
912 | unsigned long sc_lo1; | |
913 | unsigned long sc_hi2; | |
914 | unsigned long sc_lo2; | |
915 | unsigned long sc_hi3; | |
916 | unsigned long sc_lo3; | |
917 | }; | |
918 | ||
5792a79b DJ |
919 | The RT signal frames look like this: |
920 | ||
921 | struct rt_sigframe { | |
922 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 923 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
924 | struct siginfo rs_info; |
925 | struct ucontext rs_uc; | |
926 | }; | |
927 | ||
928 | struct ucontext { | |
929 | unsigned long uc_flags; | |
930 | struct ucontext *uc_link; | |
931 | stack_t uc_stack; | |
932 | [Alignment hole of four bytes] | |
933 | struct sigcontext uc_mcontext; | |
934 | sigset_t uc_sigmask; | |
935 | }; */ | |
936 | /* *INDENT-ON* */ | |
937 | ||
5792a79b DJ |
938 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
939 | ||
940 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
941 | #define STACK_T_SIZE (3 * 4) | |
942 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
943 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
944 | + RTSIGFRAME_SIGINFO_SIZE \ | |
945 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
946 | ||
947 | #define SIGCONTEXT_PC (1 * 8) | |
948 | #define SIGCONTEXT_REGS (2 * 8) | |
949 | #define SIGCONTEXT_FPREGS (34 * 8) | |
950 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
d0e64392 | 951 | #define SIGCONTEXT_DSPCTL (68 * 8 + 0) |
5792a79b DJ |
952 | #define SIGCONTEXT_HI (69 * 8) |
953 | #define SIGCONTEXT_LO (70 * 8) | |
954 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
955 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
d0e64392 MR |
956 | #define SIGCONTEXT_HI1 (71 * 8 + 0) |
957 | #define SIGCONTEXT_LO1 (71 * 8 + 4) | |
958 | #define SIGCONTEXT_HI2 (72 * 8 + 0) | |
959 | #define SIGCONTEXT_LO2 (72 * 8 + 4) | |
960 | #define SIGCONTEXT_HI3 (73 * 8 + 0) | |
961 | #define SIGCONTEXT_LO3 (73 * 8 + 4) | |
5792a79b DJ |
962 | |
963 | #define SIGCONTEXT_REG_SIZE 8 | |
964 | ||
965 | static void | |
966 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 967 | struct frame_info *this_frame, |
5792a79b DJ |
968 | struct trad_frame_cache *this_cache, |
969 | CORE_ADDR func) | |
970 | { | |
b8a22b94 | 971 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 972 | int ireg; |
eb195664 DD |
973 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
974 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 975 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 976 | CORE_ADDR regs_base; |
5792a79b DJ |
977 | |
978 | if (self == &mips_linux_o32_sigframe) | |
eb195664 | 979 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 980 | else |
eb195664 | 981 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
982 | |
983 | /* I'm not proud of this hack. Eventually we will have the | |
984 | infrastructure to indicate the size of saved registers on a | |
985 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
986 | bytes but we only want four. Use regs_base to access any |
987 | 64-bit fields. */ | |
2eb4d78b | 988 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
989 | regs_base = sigcontext_base + 4; |
990 | else | |
991 | regs_base = sigcontext_base; | |
5792a79b | 992 | |
2eb4d78b | 993 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
994 | trad_frame_set_reg_addr (this_cache, |
995 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 996 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 997 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
998 | |
999 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1000 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1001 | ireg + MIPS_ZERO_REGNUM |
2eb4d78b | 1002 | + gdbarch_num_regs (gdbarch), |
37c4d197 | 1003 | regs_base + SIGCONTEXT_REGS |
5792a79b DJ |
1004 | + ireg * SIGCONTEXT_REG_SIZE); |
1005 | ||
37c4d197 DJ |
1006 | /* The way that floating point registers are saved, unfortunately, |
1007 | depends on the architecture the kernel is built for. For the r3000 and | |
1008 | tx39, four bytes of each register are at the beginning of each of the | |
1009 | 32 eight byte slots. For everything else, the registers are saved | |
1010 | using double precision; only the even-numbered slots are initialized, | |
1011 | and the high bits are the odd-numbered register. Assume the latter | |
1012 | layout, since we can't tell, and it's much more common. Which bits are | |
1013 | the "high" bits depends on endianness. */ | |
5792a79b | 1014 | for (ireg = 0; ireg < 32; ireg++) |
2eb4d78b | 1015 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a UW |
1016 | trad_frame_set_reg_addr (this_cache, |
1017 | ireg + regs->fp0 + | |
2eb4d78b | 1018 | gdbarch_num_regs (gdbarch), |
37c4d197 DJ |
1019 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
1020 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
1021 | else | |
f57d151a UW |
1022 | trad_frame_set_reg_addr (this_cache, |
1023 | ireg + regs->fp0 | |
2eb4d78b | 1024 | + gdbarch_num_regs (gdbarch), |
37c4d197 DJ |
1025 | sigcontext_base + SIGCONTEXT_FPREGS |
1026 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); | |
5792a79b | 1027 | |
f57d151a | 1028 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1029 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1030 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1031 | |
295093a4 | 1032 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1033 | regs->fp_control_status |
2eb4d78b | 1034 | + gdbarch_num_regs (gdbarch), |
5792a79b | 1035 | sigcontext_base + SIGCONTEXT_FPCSR); |
d0e64392 MR |
1036 | |
1037 | if (regs->dspctl != -1) | |
1038 | trad_frame_set_reg_addr (this_cache, | |
1039 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1040 | sigcontext_base + SIGCONTEXT_DSPCTL); | |
1041 | ||
f57d151a | 1042 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1043 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1044 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1045 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1046 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1047 | regs_base + SIGCONTEXT_LO); |
d0e64392 MR |
1048 | |
1049 | if (regs->dspacc != -1) | |
1050 | { | |
1051 | trad_frame_set_reg_addr (this_cache, | |
1052 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1053 | sigcontext_base + SIGCONTEXT_HI1); | |
1054 | trad_frame_set_reg_addr (this_cache, | |
1055 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1056 | sigcontext_base + SIGCONTEXT_LO1); | |
1057 | trad_frame_set_reg_addr (this_cache, | |
1058 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1059 | sigcontext_base + SIGCONTEXT_HI2); | |
1060 | trad_frame_set_reg_addr (this_cache, | |
1061 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1062 | sigcontext_base + SIGCONTEXT_LO2); | |
1063 | trad_frame_set_reg_addr (this_cache, | |
1064 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1065 | sigcontext_base + SIGCONTEXT_HI3); | |
1066 | trad_frame_set_reg_addr (this_cache, | |
1067 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1068 | sigcontext_base + SIGCONTEXT_LO3); | |
1069 | } | |
1070 | else | |
1071 | { | |
1072 | trad_frame_set_reg_addr (this_cache, | |
1073 | regs->cause + gdbarch_num_regs (gdbarch), | |
1074 | sigcontext_base + SIGCONTEXT_CAUSE); | |
1075 | trad_frame_set_reg_addr (this_cache, | |
1076 | regs->badvaddr + gdbarch_num_regs (gdbarch), | |
1077 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
1078 | } | |
5792a79b DJ |
1079 | |
1080 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1081 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1082 | } |
1083 | ||
1084 | /* *INDENT-OFF* */ | |
1085 | /* For N32/N64 things look different. There is no non-rt signal frame. | |
1086 | ||
1087 | struct rt_sigframe_n32 { | |
1088 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1089 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1090 | struct siginfo rs_info; |
1091 | struct ucontextn32 rs_uc; | |
1092 | }; | |
1093 | ||
1094 | struct ucontextn32 { | |
1095 | u32 uc_flags; | |
1096 | s32 uc_link; | |
1097 | stack32_t uc_stack; | |
1098 | struct sigcontext uc_mcontext; | |
1099 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1100 | }; | |
295093a4 | 1101 | |
e741f4d4 | 1102 | struct rt_sigframe { |
5792a79b DJ |
1103 | u32 rs_ass[4]; [ argument save space for o32 ] |
1104 | u32 rs_code[2]; [ signal trampoline ] | |
1105 | struct siginfo rs_info; | |
1106 | struct ucontext rs_uc; | |
1107 | }; | |
1108 | ||
1109 | struct ucontext { | |
1110 | unsigned long uc_flags; | |
1111 | struct ucontext *uc_link; | |
1112 | stack_t uc_stack; | |
1113 | struct sigcontext uc_mcontext; | |
1114 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1115 | }; | |
1116 | ||
1117 | And the sigcontext is different (this is for both n32 and n64): | |
1118 | ||
1119 | struct sigcontext { | |
1120 | unsigned long long sc_regs[32]; | |
1121 | unsigned long long sc_fpregs[32]; | |
1122 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1123 | unsigned long long sc_hi1; |
1124 | unsigned long long sc_hi2; | |
1125 | unsigned long long sc_hi3; | |
5792a79b | 1126 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1127 | unsigned long long sc_lo1; |
1128 | unsigned long long sc_lo2; | |
1129 | unsigned long long sc_lo3; | |
5792a79b | 1130 | unsigned long long sc_pc; |
5792a79b | 1131 | unsigned int sc_fpc_csr; |
5792a79b | 1132 | unsigned int sc_used_math; |
e741f4d4 DJ |
1133 | unsigned int sc_dsp; |
1134 | unsigned int sc_reserved; | |
1135 | }; | |
1136 | ||
1137 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1138 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1139 | included too. */ | |
5792a79b DJ |
1140 | /* *INDENT-ON* */ |
1141 | ||
1142 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1143 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1144 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1145 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1146 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1147 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1148 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1149 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1150 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1151 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1152 | ||
1153 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1154 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1155 | #define N64_SIGCONTEXT_HI (64 * 8) | |
d0e64392 MR |
1156 | #define N64_SIGCONTEXT_HI1 (65 * 8) |
1157 | #define N64_SIGCONTEXT_HI2 (66 * 8) | |
1158 | #define N64_SIGCONTEXT_HI3 (67 * 8) | |
e741f4d4 | 1159 | #define N64_SIGCONTEXT_LO (68 * 8) |
d0e64392 MR |
1160 | #define N64_SIGCONTEXT_LO1 (69 * 8) |
1161 | #define N64_SIGCONTEXT_LO2 (70 * 8) | |
1162 | #define N64_SIGCONTEXT_LO3 (71 * 8) | |
e741f4d4 | 1163 | #define N64_SIGCONTEXT_PC (72 * 8) |
d0e64392 MR |
1164 | #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) |
1165 | #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) | |
5792a79b DJ |
1166 | |
1167 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1168 | |
5792a79b DJ |
1169 | static void |
1170 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
b8a22b94 | 1171 | struct frame_info *this_frame, |
5792a79b DJ |
1172 | struct trad_frame_cache *this_cache, |
1173 | CORE_ADDR func) | |
1174 | { | |
b8a22b94 | 1175 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1176 | int ireg; |
eb195664 DD |
1177 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1178 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1179 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b DJ |
1180 | |
1181 | if (self == &mips_linux_n32_rt_sigframe) | |
eb195664 | 1182 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1183 | else |
eb195664 | 1184 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1185 | |
2eb4d78b | 1186 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1187 | trad_frame_set_reg_addr (this_cache, |
1188 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1189 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1190 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1191 | |
1192 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1193 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1194 | ireg + MIPS_ZERO_REGNUM |
2eb4d78b | 1195 | + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1196 | sigcontext_base + N64_SIGCONTEXT_REGS |
1197 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1198 | ||
1199 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a UW |
1200 | trad_frame_set_reg_addr (this_cache, |
1201 | ireg + regs->fp0 | |
2eb4d78b | 1202 | + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1203 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
1204 | + ireg * N64_SIGCONTEXT_REG_SIZE); | |
1205 | ||
f57d151a | 1206 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1207 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1208 | sigcontext_base + N64_SIGCONTEXT_PC); |
1209 | ||
295093a4 | 1210 | trad_frame_set_reg_addr (this_cache, |
f57d151a | 1211 | regs->fp_control_status |
2eb4d78b | 1212 | + gdbarch_num_regs (gdbarch), |
5792a79b | 1213 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
d0e64392 | 1214 | |
f57d151a | 1215 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1216 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1217 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1218 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1219 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1220 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b | 1221 | |
d0e64392 MR |
1222 | if (regs->dspacc != -1) |
1223 | { | |
1224 | trad_frame_set_reg_addr (this_cache, | |
1225 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1226 | sigcontext_base + N64_SIGCONTEXT_HI1); | |
1227 | trad_frame_set_reg_addr (this_cache, | |
1228 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1229 | sigcontext_base + N64_SIGCONTEXT_LO1); | |
1230 | trad_frame_set_reg_addr (this_cache, | |
1231 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1232 | sigcontext_base + N64_SIGCONTEXT_HI2); | |
1233 | trad_frame_set_reg_addr (this_cache, | |
1234 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1235 | sigcontext_base + N64_SIGCONTEXT_LO2); | |
1236 | trad_frame_set_reg_addr (this_cache, | |
1237 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1238 | sigcontext_base + N64_SIGCONTEXT_HI3); | |
1239 | trad_frame_set_reg_addr (this_cache, | |
1240 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1241 | sigcontext_base + N64_SIGCONTEXT_LO3); | |
1242 | } | |
1243 | if (regs->dspctl != -1) | |
1244 | trad_frame_set_reg_addr (this_cache, | |
1245 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1246 | sigcontext_base + N64_SIGCONTEXT_DSPCTL); | |
1247 | ||
5792a79b | 1248 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
eb195664 | 1249 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1250 | } |
1251 | ||
5a439849 MR |
1252 | /* Implement the "write_pc" gdbarch method. */ |
1253 | ||
822b6570 | 1254 | static void |
61a1198a | 1255 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1256 | { |
2eb4d78b | 1257 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
5a439849 MR |
1258 | |
1259 | mips_write_pc (regcache, pc); | |
822b6570 DJ |
1260 | |
1261 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1262 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1263 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1264 | } |
1265 | ||
1266 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1267 | ||
1268 | int | |
1269 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1270 | { | |
1271 | /* If we do not have a target description with registers, then | |
1272 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1273 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1274 | return 0; | |
1275 | ||
1276 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1277 | either be GPR-sized or missing. */ | |
1278 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1279 | } | |
9f62d0e2 | 1280 | |
e38d4e1a DJ |
1281 | /* When FRAME is at a syscall instruction, return the PC of the next |
1282 | instruction to be executed. */ | |
1283 | ||
63807e1d | 1284 | static CORE_ADDR |
e38d4e1a DJ |
1285 | mips_linux_syscall_next_pc (struct frame_info *frame) |
1286 | { | |
1287 | CORE_ADDR pc = get_frame_pc (frame); | |
1288 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1289 | ||
1290 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1291 | decode the signal frame. */ | |
1292 | if (v0 == MIPS_NR_sigreturn | |
1293 | || v0 == MIPS_NR_rt_sigreturn | |
1294 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1295 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1296 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1297 | |
1298 | return pc + 4; | |
1299 | } | |
1300 | ||
385203ed DD |
1301 | /* Return the current system call's number present in the |
1302 | v0 register. When the function fails, it returns -1. */ | |
1303 | ||
1304 | static LONGEST | |
1305 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
1306 | ptid_t ptid) | |
1307 | { | |
1308 | struct regcache *regcache = get_thread_regcache (ptid); | |
1309 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1310 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1311 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1312 | /* The content of a register */ | |
1313 | gdb_byte buf[8]; | |
1314 | /* The result */ | |
1315 | LONGEST ret; | |
1316 | ||
1317 | /* Make sure we're in a known ABI */ | |
1318 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1319 | || tdep->mips_abi == MIPS_ABI_N32 | |
1320 | || tdep->mips_abi == MIPS_ABI_N64); | |
1321 | ||
1322 | gdb_assert (regsize <= sizeof (buf)); | |
1323 | ||
1324 | /* Getting the system call number from the register. | |
1325 | syscall number is in v0 or $2. */ | |
1326 | regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf); | |
1327 | ||
1328 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1329 | ||
1330 | return ret; | |
1331 | } | |
1332 | ||
5792a79b DJ |
1333 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1334 | ||
19ed69dd | 1335 | static void |
295093a4 MS |
1336 | mips_linux_init_abi (struct gdbarch_info info, |
1337 | struct gdbarch *gdbarch) | |
19ed69dd | 1338 | { |
96f026fc KB |
1339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1340 | enum mips_abi abi = mips_abi (gdbarch); | |
822b6570 | 1341 | struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; |
96f026fc | 1342 | |
a5ee0f0c PA |
1343 | linux_init_abi (info, gdbarch); |
1344 | ||
385203ed DD |
1345 | /* Get the syscall number from the arch's register. */ |
1346 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1347 | ||
96f026fc KB |
1348 | switch (abi) |
1349 | { | |
1350 | case MIPS_ABI_O32: | |
1351 | set_gdbarch_get_longjmp_target (gdbarch, | |
1352 | mips_linux_get_longjmp_target); | |
1353 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1354 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
fb2be677 AC |
1355 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1356 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
385203ed | 1357 | set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1358 | break; |
1359 | case MIPS_ABI_N32: | |
1360 | set_gdbarch_get_longjmp_target (gdbarch, | |
1361 | mips_linux_get_longjmp_target); | |
1362 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1363 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
d05f6826 DJ |
1364 | set_gdbarch_long_double_bit (gdbarch, 128); |
1365 | /* These floatformats should probably be renamed. MIPS uses | |
1366 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1367 | except that the quiet/signalling NaN bit is reversed (GDB | |
1368 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1369 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1370 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
385203ed | 1371 | set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1372 | break; |
1373 | case MIPS_ABI_N64: | |
1374 | set_gdbarch_get_longjmp_target (gdbarch, | |
1375 | mips64_linux_get_longjmp_target); | |
1376 | set_solib_svr4_fetch_link_map_offsets | |
76a9d10f | 1377 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
d05f6826 DJ |
1378 | set_gdbarch_long_double_bit (gdbarch, 128); |
1379 | /* These floatformats should probably be renamed. MIPS uses | |
1380 | the same 128-bit IEEE floating point format that IA-64 uses, | |
1381 | except that the quiet/signalling NaN bit is reversed (GDB | |
1382 | does not distinguish between quiet and signalling NaNs). */ | |
8da61cc4 | 1383 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
fb2be677 | 1384 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
385203ed | 1385 | set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1386 | break; |
1387 | default: | |
96f026fc KB |
1388 | break; |
1389 | } | |
6de918a6 DJ |
1390 | |
1391 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1392 | ||
0d0266c6 | 1393 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1394 | |
1395 | /* Enable TLS support. */ | |
1396 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1397 | svr4_fetch_objfile_link_map); | |
7d522c90 DJ |
1398 | |
1399 | /* Initialize this lazily, to avoid an initialization order | |
1400 | dependency on solib-svr4.c's _initialize routine. */ | |
1401 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1402 | { | |
1403 | mips_svr4_so_ops = svr4_so_ops; | |
1404 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1405 | = mips_linux_in_dynsym_resolve_code; | |
1406 | } | |
1407 | set_solib_ops (gdbarch, &mips_svr4_so_ops); | |
822b6570 DJ |
1408 | |
1409 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1410 | ||
4eb0ad19 DJ |
1411 | set_gdbarch_core_read_description (gdbarch, |
1412 | mips_linux_core_read_description); | |
1413 | ||
50e8a0d5 HZ |
1414 | set_gdbarch_regset_from_core_section (gdbarch, |
1415 | mips_linux_regset_from_core_section); | |
1416 | ||
e38d4e1a DJ |
1417 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1418 | ||
822b6570 DJ |
1419 | if (tdesc_data) |
1420 | { | |
1421 | const struct tdesc_feature *feature; | |
1422 | ||
1423 | /* If we have target-described registers, then we can safely | |
1424 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1425 | described or not). */ | |
1426 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1427 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
cf233303 | 1428 | set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); |
822b6570 DJ |
1429 | |
1430 | /* If it's present, then assign it to the reserved number. */ | |
1431 | feature = tdesc_find_feature (info.target_desc, | |
1432 | "org.gnu.gdb.mips.linux"); | |
1433 | if (feature != NULL) | |
1434 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1435 | "restart"); | |
1436 | } | |
19ed69dd KB |
1437 | } |
1438 | ||
63807e1d PA |
1439 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1440 | extern initialize_file_ftype _initialize_mips_linux_tdep; | |
1441 | ||
2aa830e4 | 1442 | void |
d1bacddc | 1443 | _initialize_mips_linux_tdep (void) |
2aa830e4 | 1444 | { |
96f026fc KB |
1445 | const struct bfd_arch_info *arch_info; |
1446 | ||
96f026fc KB |
1447 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1448 | arch_info != NULL; | |
1449 | arch_info = arch_info->next) | |
1450 | { | |
295093a4 MS |
1451 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1452 | GDB_OSABI_LINUX, | |
96f026fc KB |
1453 | mips_linux_init_abi); |
1454 | } | |
2aa830e4 | 1455 | } |