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* config/nm-linux.h: Do not include <signal.h>.
[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
76a9d10f
MK		 3 Copyright (C) 2001, 2002, 2004, 2005, 2006
4 Free Software Foundation, Inc.
2aa830e4
DJ		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
2aa830e4
DJ		 22
23#include "defs.h"
24#include "gdbcore.h"
25#include "target.h"
26#include "solib-svr4.h"
19ed69dd 27#include "osabi.h"
96f026fc 28#include "mips-tdep.h"
19ed69dd 29#include "gdb_string.h"
96f026fc 30#include "gdb_assert.h"
6de918a6 31#include "frame.h"
2fdf551c 32#include "regcache.h"
5792a79b
DJ		 33#include "trad-frame.h"
34#include "tramp-frame.h"
d05f6826 35#include "floatformat.h"
5ea03926 36#include "solib.h"
d37eb719 37#include "mips-linux-tdep.h"
2aa830e4
DJ		 38
39/* Figure out where the longjmp will land.
295093a4
MS		 40 We expect the first arg to be a pointer to the jmp_buf structure
41 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
42 at. The pc is copied into PC. This routine returns 1 on
43 success. */
2aa830e4 44
19ed69dd
KB		 45#define MIPS_LINUX_JB_ELEMENT_SIZE 4
46#define MIPS_LINUX_JB_PC 0
47
48static int
2aa830e4
DJ		 49mips_linux_get_longjmp_target (CORE_ADDR *pc)
50{
51 CORE_ADDR jb_addr;
52 char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
53
613e114f 54 jb_addr = read_register (MIPS_A0_REGNUM);
2aa830e4 55
bf072999
DJ		 56 if (target_read_memory (jb_addr
57 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
58 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
2aa830e4
DJ		 59 return 0;
60
7c0b4a20 61 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
2aa830e4
DJ		 62
63 return 1;
64}
65
4246e332 66/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 67 for regcache_raw_supply(). This is needed when mips_isa_regsize()
68 is 8. */
96f026fc
KB		 69
70static void
71supply_32bit_reg (int regnum, const void *addr)
72{
d37eb719 73 gdb_byte buf[MAX_REGISTER_SIZE];
3acba339 74 store_signed_integer (buf, register_size (current_gdbarch, regnum),
96f026fc 75 extract_signed_integer (addr, 4));
23a6d369 76 regcache_raw_supply (current_regcache, regnum, buf);
96f026fc
KB		 77}
78
2aa830e4
DJ		 79/* Unpack an elf_gregset_t into GDB's register cache. */
80
d37eb719
DJ		 81void
82mips_supply_gregset (mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 83{
84 int regi;
d37eb719 85 mips_elf_greg_t *regp = *gregsetp;
d9d9c31f 86 char zerobuf[MAX_REGISTER_SIZE];
bf072999 87
d9d9c31f 88 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 89
90 for (regi = EF_REG0; regi <= EF_REG31; regi++)
96f026fc 91 supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi));
2aa830e4 92
56cea623
AC		 93 supply_32bit_reg (mips_regnum (current_gdbarch)->lo,
94 (char *)(regp + EF_LO));
95 supply_32bit_reg (mips_regnum (current_gdbarch)->hi,
96 (char *)(regp + EF_HI));
97
98 supply_32bit_reg (mips_regnum (current_gdbarch)->pc,
99 (char *)(regp + EF_CP0_EPC));
100 supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr,
101 (char *)(regp + EF_CP0_BADVADDR));
24e05951 102 supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS));
56cea623
AC		 103 supply_32bit_reg (mips_regnum (current_gdbarch)->cause,
104 (char *)(regp + EF_CP0_CAUSE));
2aa830e4
DJ		 105
106 /* Fill inaccessible registers with zero. */
613e114f 107 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 108 for (regi = MIPS_FIRST_EMBED_REGNUM;
109 regi < MIPS_LAST_EMBED_REGNUM;
110 regi++)
23a6d369 111 regcache_raw_supply (current_regcache, regi, zerobuf);
2aa830e4
DJ		 112}
113
114/* Pack our registers (or one register) into an elf_gregset_t. */
115
d37eb719
DJ		 116void
117mips_fill_gregset (mips_elf_gregset_t *gregsetp, int regno)
2aa830e4
DJ		 118{
119 int regaddr, regi;
d37eb719 120 mips_elf_greg_t *regp = *gregsetp;
96f026fc 121 void *dst;
2aa830e4
DJ		 122
123 if (regno == -1)
124 {
d37eb719 125 memset (regp, 0, sizeof (mips_elf_gregset_t));
2aa830e4 126 for (regi = 0; regi < 32; regi++)
9f62d0e2
DJ		 127 mips_fill_gregset (gregsetp, regi);
128 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
129 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
130 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
131 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr);
132 mips_fill_gregset (gregsetp, MIPS_PS_REGNUM);
133 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause);
2aa830e4
DJ		 134
135 return;
136 }
137
138 if (regno < 32)
139 {
2aa830e4 140 dst = regp + regno + EF_REG0;
822c9732 141 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 142 return;
143 }
144
56cea623
AC		 145 if (regno == mips_regnum (current_gdbarch)->lo)
146 regaddr = EF_LO;
147 else if (regno == mips_regnum (current_gdbarch)->hi)
148 regaddr = EF_HI;
149 else if (regno == mips_regnum (current_gdbarch)->pc)
150 regaddr = EF_CP0_EPC;
151 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
152 regaddr = EF_CP0_BADVADDR;
24e05951 153 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 154 regaddr = EF_CP0_STATUS;
155 else if (regno == mips_regnum (current_gdbarch)->cause)
156 regaddr = EF_CP0_CAUSE;
157 else
158 regaddr = -1;
2aa830e4
DJ		 159
160 if (regaddr != -1)
161 {
2aa830e4 162 dst = regp + regaddr;
822c9732 163 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 164 }
165}
166
167/* Likewise, unpack an elf_fpregset_t. */
168
d37eb719
DJ		 169void
170mips_supply_fpregset (mips_elf_fpregset_t *fpregsetp)
2aa830e4 171{
52f0bd74 172 int regi;
d9d9c31f 173 char zerobuf[MAX_REGISTER_SIZE];
bf072999 174
d9d9c31f 175 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 176
177 for (regi = 0; regi < 32; regi++)
23a6d369
AC		 178 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
179 (char *)(*fpregsetp + regi));
2aa830e4 180
23a6d369
AC		 181 regcache_raw_supply (current_regcache,
182 mips_regnum (current_gdbarch)->fp_control_status,
183 (char *)(*fpregsetp + 32));
2aa830e4 184
295093a4 185 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
23a6d369
AC		 186 regcache_raw_supply (current_regcache,
187 mips_regnum (current_gdbarch)->fp_implementation_revision,
188 zerobuf);
2aa830e4
DJ		 189}
190
191/* Likewise, pack one or all floating point registers into an
192 elf_fpregset_t. */
193
d37eb719
DJ		 194void
195mips_fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4
DJ		 196{
197 char *from, *to;
198
199 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
200 {
2aa830e4 201 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
2fdf551c 202 regcache_raw_collect (current_regcache, regno, to);
2aa830e4 203 }
56cea623 204 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 205 {
2aa830e4 206 to = (char *) (*fpregsetp + 32);
2fdf551c 207 regcache_raw_collect (current_regcache, regno, to);
2aa830e4
DJ		 208 }
209 else if (regno == -1)
210 {
211 int regi;
212
213 for (regi = 0; regi < 32; regi++)
9f62d0e2
DJ		 214 mips_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
215 mips_fill_fpregset (fpregsetp,
216 mips_regnum (current_gdbarch)->fp_control_status);
2aa830e4
DJ		 217 }
218}
219
220/* Map gdb internal register number to ptrace ``address''.
221 These ``addresses'' are normally defined in <asm/ptrace.h>. */
222
96f026fc
KB		 223static CORE_ADDR
224mips_linux_register_addr (int regno, CORE_ADDR blockend)
2aa830e4
DJ		 225{
226 int regaddr;
227
228 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 229 error (_("Bogon register number %d."), regno);
2aa830e4
DJ		 230
231 if (regno < 32)
232 regaddr = regno;
56cea623
AC		 233 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
234 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
235 regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0);
236 else if (regno == mips_regnum (current_gdbarch)->pc)
2aa830e4 237 regaddr = PC;
56cea623 238 else if (regno == mips_regnum (current_gdbarch)->cause)
2aa830e4 239 regaddr = CAUSE;
56cea623 240 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
2aa830e4 241 regaddr = BADVADDR;
56cea623 242 else if (regno == mips_regnum (current_gdbarch)->lo)
2aa830e4 243 regaddr = MMLO;
56cea623 244 else if (regno == mips_regnum (current_gdbarch)->hi)
2aa830e4 245 regaddr = MMHI;
56cea623 246 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 247 regaddr = FPC_CSR;
56cea623 248 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
2aa830e4
DJ		 249 regaddr = FPC_EIR;
250 else
8a3fe4f8 251 error (_("Unknowable register number %d."), regno);
2aa830e4
DJ		 252
253 return regaddr;
254}
255
96f026fc
KB		 256/* Support for 64-bit ABIs. */
257
96f026fc 258/* Figure out where the longjmp will land.
295093a4
MS		 259 We expect the first arg to be a pointer to the jmp_buf structure
260 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
261 at. The pc is copied into PC. This routine returns 1 on
262 success. */
96f026fc
KB		 263
264/* Details about jmp_buf. */
265
266#define MIPS64_LINUX_JB_PC 0
267
268static int
269mips64_linux_get_longjmp_target (CORE_ADDR *pc)
270{
271 CORE_ADDR jb_addr;
272 void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
273 int element_size = TARGET_PTR_BIT == 32 ? 4 : 8;
274
613e114f 275 jb_addr = read_register (MIPS_A0_REGNUM);
96f026fc
KB		 276
277 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
278 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
279 return 0;
280
7c0b4a20 281 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
96f026fc
KB		 282
283 return 1;
284}
285
d37eb719
DJ		 286/* Register set support functions. These operate on standard 64-bit
287 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
288 target will still use the 64-bit format for PTRACE_GETREGS. */
289
290/* Supply a 64-bit register. */
96f026fc 291
d37eb719
DJ		 292void
293supply_64bit_reg (int regnum, const gdb_byte *buf)
294{
295 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
296 && register_size (current_gdbarch, regnum) == 4)
297 regcache_raw_supply (current_regcache, regnum, buf + 4);
298 else
299 regcache_raw_supply (current_regcache, regnum, buf);
300}
301
302/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
303
304void
96f026fc
KB		 305mips64_supply_gregset (mips64_elf_gregset_t *gregsetp)
306{
307 int regi;
308 mips64_elf_greg_t *regp = *gregsetp;
d37eb719 309 gdb_byte zerobuf[MAX_REGISTER_SIZE];
96f026fc 310
d9d9c31f 311 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc
KB		 312
313 for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
d37eb719
DJ		 314 supply_64bit_reg (regi - MIPS64_EF_REG0, (gdb_byte *)(regp + regi));
315
316 supply_64bit_reg (mips_regnum (current_gdbarch)->lo,
317 (gdb_byte *) (regp + MIPS64_EF_LO));
318 supply_64bit_reg (mips_regnum (current_gdbarch)->hi,
319 (gdb_byte *) (regp + MIPS64_EF_HI));
320
321 supply_64bit_reg (mips_regnum (current_gdbarch)->pc,
322 (gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
323 supply_64bit_reg (mips_regnum (current_gdbarch)->badvaddr,
324 (gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
325 supply_64bit_reg (MIPS_PS_REGNUM,
326 (gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
327 supply_64bit_reg (mips_regnum (current_gdbarch)->cause,
328 (gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc
KB		 329
330 /* Fill inaccessible registers with zero. */
613e114f 331 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 332 for (regi = MIPS_FIRST_EMBED_REGNUM;
333 regi < MIPS_LAST_EMBED_REGNUM;
334 regi++)
23a6d369 335 regcache_raw_supply (current_regcache, regi, zerobuf);
96f026fc
KB		 336}
337
d37eb719 338/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 339
d37eb719 340void
96f026fc
KB		 341mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno)
342{
343 int regaddr, regi;
344 mips64_elf_greg_t *regp = *gregsetp;
345 void *src, *dst;
346
347 if (regno == -1)
348 {
349 memset (regp, 0, sizeof (mips64_elf_gregset_t));
350 for (regi = 0; regi < 32; regi++)
351 mips64_fill_gregset (gregsetp, regi);
56cea623
AC		 352 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
353 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
354 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
295093a4
MS		 355 mips64_fill_gregset (gregsetp,
356 mips_regnum (current_gdbarch)->badvaddr);
24e05951 357 mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM);
295093a4
MS		 358 mips64_fill_gregset (gregsetp,
359 mips_regnum (current_gdbarch)->cause);
96f026fc
KB		 360
361 return;
362 }
363
364 if (regno < 32)
d37eb719
DJ		 365 regaddr = regno + MIPS64_EF_REG0;
366 else if (regno == mips_regnum (current_gdbarch)->lo)
56cea623
AC		 367 regaddr = MIPS64_EF_LO;
368 else if (regno == mips_regnum (current_gdbarch)->hi)
369 regaddr = MIPS64_EF_HI;
370 else if (regno == mips_regnum (current_gdbarch)->pc)
371 regaddr = MIPS64_EF_CP0_EPC;
372 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
373 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 374 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 375 regaddr = MIPS64_EF_CP0_STATUS;
376 else if (regno == mips_regnum (current_gdbarch)->cause)
377 regaddr = MIPS64_EF_CP0_CAUSE;
378 else
379 regaddr = -1;
96f026fc
KB		 380
381 if (regaddr != -1)
382 {
d37eb719
DJ		 383 gdb_byte buf[MAX_REGISTER_SIZE];
384 LONGEST val;
385
386 regcache_raw_collect (current_regcache, regno, buf);
387 val = extract_signed_integer (buf,
388 register_size (current_gdbarch, regno));
96f026fc 389 dst = regp + regaddr;
d37eb719 390 store_signed_integer (dst, 8, val);
96f026fc
KB		 391 }
392}
393
394/* Likewise, unpack an elf_fpregset_t. */
395
d37eb719 396void
96f026fc
KB		 397mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp)
398{
52f0bd74 399 int regi;
96f026fc 400
d37eb719
DJ		 401 /* See mips_linux_o32_sigframe_init for a description of the
402 peculiar FP register layout. */
403 if (register_size (current_gdbarch, FP0_REGNUM) == 4)
404 for (regi = 0; regi < 32; regi++)
405 {
406 gdb_byte *reg_ptr = (gdb_byte *) (*fpregsetp + (regi & ~1));
407 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1))
408 reg_ptr += 4;
409 regcache_raw_supply (current_regcache, FP0_REGNUM + regi, reg_ptr);
410 }
411 else
412 for (regi = 0; regi < 32; regi++)
413 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
414 (char *)(*fpregsetp + regi));
415
416 supply_32bit_reg (mips_regnum (current_gdbarch)->fp_control_status,
417 (gdb_byte *)(*fpregsetp + 32));
418
419 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
420 include it - but the result of PTRACE_GETFPREGS does. The best we
421 can do is to assume that its value is present. */
422 supply_32bit_reg (mips_regnum (current_gdbarch)->fp_implementation_revision,
423 (gdb_byte *)(*fpregsetp + 32) + 4);
96f026fc
KB		 424}
425
426/* Likewise, pack one or all floating point registers into an
427 elf_fpregset_t. */
428
d37eb719 429void
96f026fc
KB		 430mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno)
431{
d37eb719 432 gdb_byte *to;
96f026fc
KB		 433
434 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
435 {
d37eb719
DJ		 436 /* See mips_linux_o32_sigframe_init for a description of the
437 peculiar FP register layout. */
438 if (register_size (current_gdbarch, regno) == 4)
439 {
440 int regi = regno - FP0_REGNUM;
441
442 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
443 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1))
444 to += 4;
445 regcache_raw_collect (current_regcache, regno, to);
446 }
447 else
448 {
449 to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM);
450 regcache_raw_collect (current_regcache, regno, to);
451 }
96f026fc 452 }
56cea623 453 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 454 {
d37eb719
DJ		 455 gdb_byte buf[MAX_REGISTER_SIZE];
456 LONGEST val;
457
458 regcache_raw_collect (current_regcache, regno, buf);
459 val = extract_signed_integer (buf,
460 register_size (current_gdbarch, regno));
461 to = (gdb_byte *) (*fpregsetp + 32);
462 store_signed_integer (to, 4, val);
463 }
464 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
465 {
466 gdb_byte buf[MAX_REGISTER_SIZE];
467 LONGEST val;
468
469 regcache_raw_collect (current_regcache, regno, buf);
470 val = extract_signed_integer (buf,
471 register_size (current_gdbarch, regno));
472 to = (gdb_byte *) (*fpregsetp + 32) + 4;
473 store_signed_integer (to, 4, val);
96f026fc
KB		 474 }
475 else if (regno == -1)
476 {
477 int regi;
478
479 for (regi = 0; regi < 32; regi++)
480 mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
d37eb719
DJ		 481 mips64_fill_fpregset (fpregsetp,
482 mips_regnum (current_gdbarch)->fp_control_status);
483 mips64_fill_fpregset (fpregsetp, (mips_regnum (current_gdbarch)
484 ->fp_implementation_revision));
96f026fc
KB		 485 }
486}
487
488
489/* Map gdb internal register number to ptrace ``address''.
490 These ``addresses'' are normally defined in <asm/ptrace.h>. */
491
492static CORE_ADDR
493mips64_linux_register_addr (int regno, CORE_ADDR blockend)
494{
495 int regaddr;
496
497 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 498 error (_("Bogon register number %d."), regno);
96f026fc
KB		 499
500 if (regno < 32)
501 regaddr = regno;
56cea623
AC		 502 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
503 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
96f026fc 504 regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM);
56cea623 505 else if (regno == mips_regnum (current_gdbarch)->pc)
96f026fc 506 regaddr = MIPS64_PC;
56cea623 507 else if (regno == mips_regnum (current_gdbarch)->cause)
96f026fc 508 regaddr = MIPS64_CAUSE;
56cea623 509 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
96f026fc 510 regaddr = MIPS64_BADVADDR;
56cea623 511 else if (regno == mips_regnum (current_gdbarch)->lo)
96f026fc 512 regaddr = MIPS64_MMLO;
56cea623 513 else if (regno == mips_regnum (current_gdbarch)->hi)
96f026fc 514 regaddr = MIPS64_MMHI;
56cea623 515 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 516 regaddr = MIPS64_FPC_CSR;
56cea623 517 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
96f026fc
KB		 518 regaddr = MIPS64_FPC_EIR;
519 else
8a3fe4f8 520 error (_("Unknowable register number %d."), regno);
96f026fc
KB		 521
522 return regaddr;
523}
524
2aa830e4
DJ		 525/* Use a local version of this function to get the correct types for
526 regsets, until multi-arch core support is ready. */
527
528static void
529fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
530 int which, CORE_ADDR reg_addr)
531{
d37eb719
DJ		 532 mips_elf_gregset_t gregset;
533 mips_elf_fpregset_t fpregset;
96f026fc
KB		 534 mips64_elf_gregset_t gregset64;
535 mips64_elf_fpregset_t fpregset64;
2aa830e4
DJ		 536
537 if (which == 0)
538 {
96f026fc 539 if (core_reg_size == sizeof (gregset))
2aa830e4 540 {
96f026fc 541 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
9f62d0e2 542 mips_supply_gregset (&gregset);
96f026fc
KB		 543 }
544 else if (core_reg_size == sizeof (gregset64))
545 {
546 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
547 mips64_supply_gregset (&gregset64);
2aa830e4
DJ		 548 }
549 else
550 {
8a3fe4f8 551 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 552 }
553 }
554 else if (which == 2)
555 {
96f026fc 556 if (core_reg_size == sizeof (fpregset))
2aa830e4 557 {
96f026fc 558 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
9f62d0e2 559 mips_supply_fpregset (&fpregset);
96f026fc
KB		 560 }
561 else if (core_reg_size == sizeof (fpregset64))
562 {
295093a4
MS		 563 memcpy ((char *) &fpregset64, core_reg_sect,
564 sizeof (fpregset64));
96f026fc 565 mips64_supply_fpregset (&fpregset64);
2aa830e4
DJ		 566 }
567 else
568 {
8a3fe4f8 569 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 570 }
571 }
572}
573
574/* Register that we are able to handle ELF file formats using standard
575 procfs "regset" structures. */
576
577static struct core_fns regset_core_fns =
578{
579 bfd_target_elf_flavour, /* core_flavour */
580 default_check_format, /* check_format */
581 default_core_sniffer, /* core_sniffer */
582 fetch_core_registers, /* core_read_registers */
583 NULL /* next */
584};
585
295093a4
MS		 586/* Handle for obtaining pointer to the current register_addr()
587 function for a given architecture. */
96f026fc
KB		 588static struct gdbarch_data *register_addr_data;
589
590CORE_ADDR
591register_addr (int regno, CORE_ADDR blockend)
592{
593 CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) =
594 gdbarch_data (current_gdbarch, register_addr_data);
595
596 gdb_assert (register_addr_ptr != 0);
597
598 return register_addr_ptr (regno, blockend);
599}
600
601static void
602set_mips_linux_register_addr (struct gdbarch *gdbarch,
295093a4
MS		 603 CORE_ADDR (*register_addr_ptr) (int,
604 CORE_ADDR))
96f026fc 605{
295093a4
MS		 606 deprecated_set_gdbarch_data (gdbarch, register_addr_data,
607 register_addr_ptr);
96f026fc
KB		 608}
609
610static void *
611init_register_addr_data (struct gdbarch *gdbarch)
612{
613 return 0;
614}
615
295093a4
MS		 616/* Check the code at PC for a dynamic linker lazy resolution stub.
617 Because they aren't in the .plt section, we pattern-match on the
618 code generated by GNU ld. They look like this:
6de918a6
DJ		 619
620 lw t9,0x8010(gp)
621 addu t7,ra
622 jalr t9,ra
623 addiu t8,zero,INDEX
624
295093a4
MS		 625 (with the appropriate doubleword instructions for N64). Also
626 return the dynamic symbol index used in the last instruction. */
6de918a6
DJ		 627
628static int
629mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
630{
631 unsigned char buf[28], *p;
632 ULONGEST insn, insn1;
633 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
634
635 read_memory (pc - 12, buf, 28);
636
637 if (n64)
638 {
639 /* ld t9,0x8010(gp) */
640 insn1 = 0xdf998010;
641 }
642 else
643 {
644 /* lw t9,0x8010(gp) */
645 insn1 = 0x8f998010;
646 }
647
648 p = buf + 12;
649 while (p >= buf)
650 {
651 insn = extract_unsigned_integer (p, 4);
652 if (insn == insn1)
653 break;
654 p -= 4;
655 }
656 if (p < buf)
657 return 0;
658
659 insn = extract_unsigned_integer (p + 4, 4);
660 if (n64)
661 {
662 /* daddu t7,ra */
663 if (insn != 0x03e0782d)
664 return 0;
665 }
666 else
667 {
668 /* addu t7,ra */
669 if (insn != 0x03e07821)
670 return 0;
671 }
295093a4 672
6de918a6
DJ		 673 insn = extract_unsigned_integer (p + 8, 4);
674 /* jalr t9,ra */
675 if (insn != 0x0320f809)
676 return 0;
677
678 insn = extract_unsigned_integer (p + 12, 4);
679 if (n64)
680 {
681 /* daddiu t8,zero,0 */
682 if ((insn & 0xffff0000) != 0x64180000)
683 return 0;
684 }
685 else
686 {
687 /* addiu t8,zero,0 */
688 if ((insn & 0xffff0000) != 0x24180000)
689 return 0;
690 }
691
692 return (insn & 0xffff);
693}
694
295093a4
MS		 695/* Return non-zero iff PC belongs to the dynamic linker resolution
696 code or to a stub. */
6de918a6
DJ		 697
698int
699mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
700{
295093a4
MS		 701 /* Check whether PC is in the dynamic linker. This also checks
702 whether it is in the .plt section, which MIPS does not use. */
6de918a6
DJ		 703 if (in_solib_dynsym_resolve_code (pc))
704 return 1;
705
295093a4
MS		 706 /* Pattern match for the stub. It would be nice if there were a
707 more efficient way to avoid this check. */
6de918a6
DJ		 708 if (mips_linux_in_dynsym_stub (pc, NULL))
709 return 1;
710
711 return 0;
712}
713
714/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
715 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
716 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba
AC		 717 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
718 "__dl_runtime_resolve" directly. An unresolved PLT entry will
719 point to _dl_runtime_resolve, which will first call
720 __dl_runtime_resolve, and then pass control to the resolved
721 function. */
6de918a6
DJ		 722
723static CORE_ADDR
724mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
725{
726 struct minimal_symbol *resolver;
727
728 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
729
730 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
295093a4 731 return frame_pc_unwind (get_current_frame ());
6de918a6
DJ		 732
733 return 0;
295093a4 734}
6de918a6 735
5792a79b
DJ		 736/* Signal trampoline support. There are four supported layouts for a
737 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
738 n64 rt_sigframe. We handle them all independently; not the most
739 efficient way, but simplest. First, declare all the unwinders. */
740
741static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
742 struct frame_info *next_frame,
743 struct trad_frame_cache *this_cache,
744 CORE_ADDR func);
745
746static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
747 struct frame_info *next_frame,
748 struct trad_frame_cache *this_cache,
749 CORE_ADDR func);
750
751#define MIPS_NR_LINUX 4000
752#define MIPS_NR_N64_LINUX 5000
753#define MIPS_NR_N32_LINUX 6000
754
755#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
756#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
757#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
758#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
759
760#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
761#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
762#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
763#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
764#define MIPS_INST_SYSCALL 0x0000000c
765
2cd8546d
AC		 766static const struct tramp_frame mips_linux_o32_sigframe = {
767 SIGTRAMP_FRAME,
5792a79b 768 4,
2cd8546d
AC		 769 {
770 { MIPS_INST_LI_V0_SIGRETURN, -1 },
771 { MIPS_INST_SYSCALL, -1 },
772 { TRAMP_SENTINEL_INSN, -1 }
773 },
5792a79b
DJ		 774 mips_linux_o32_sigframe_init
775};
776
2cd8546d
AC		 777static const struct tramp_frame mips_linux_o32_rt_sigframe = {
778 SIGTRAMP_FRAME,
5792a79b 779 4,
2cd8546d
AC		 780 {
781 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
782 { MIPS_INST_SYSCALL, -1 },
783 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 784 mips_linux_o32_sigframe_init
785};
786
2cd8546d
AC		 787static const struct tramp_frame mips_linux_n32_rt_sigframe = {
788 SIGTRAMP_FRAME,
5792a79b 789 4,
2cd8546d
AC		 790 {
791 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
792 { MIPS_INST_SYSCALL, -1 },
793 { TRAMP_SENTINEL_INSN, -1 }
794 },
5792a79b
DJ		 795 mips_linux_n32n64_sigframe_init
796};
797
2cd8546d
AC		 798static const struct tramp_frame mips_linux_n64_rt_sigframe = {
799 SIGTRAMP_FRAME,
5792a79b 800 4,
295093a4
MS		 801 { MIPS_INST_LI_V0_N64_RT_SIGRETURN,
802 MIPS_INST_SYSCALL,
803 TRAMP_SENTINEL_INSN },
5792a79b
DJ		 804 mips_linux_n32n64_sigframe_init
805};
806
807/* *INDENT-OFF* */
808/* The unwinder for o32 signal frames. The legacy structures look
809 like this:
810
811 struct sigframe {
812 u32 sf_ass[4]; [argument save space for o32]
813 u32 sf_code[2]; [signal trampoline]
814 struct sigcontext sf_sc;
815 sigset_t sf_mask;
816 };
817
818 struct sigcontext {
819 unsigned int sc_regmask; [Unused]
820 unsigned int sc_status;
821 unsigned long long sc_pc;
822 unsigned long long sc_regs[32];
823 unsigned long long sc_fpregs[32];
824 unsigned int sc_ownedfp;
825 unsigned int sc_fpc_csr;
826 unsigned int sc_fpc_eir; [Unused]
827 unsigned int sc_used_math;
828 unsigned int sc_ssflags; [Unused]
829 [Alignment hole of four bytes]
830 unsigned long long sc_mdhi;
831 unsigned long long sc_mdlo;
832
833 unsigned int sc_cause; [Unused]
834 unsigned int sc_badvaddr; [Unused]
835
836 unsigned long sc_sigset[4]; [kernel's sigset_t]
837 };
838
839 The RT signal frames look like this:
840
841 struct rt_sigframe {
842 u32 rs_ass[4]; [argument save space for o32]
843 u32 rs_code[2] [signal trampoline]
844 struct siginfo rs_info;
845 struct ucontext rs_uc;
846 };
847
848 struct ucontext {
849 unsigned long uc_flags;
850 struct ucontext *uc_link;
851 stack_t uc_stack;
852 [Alignment hole of four bytes]
853 struct sigcontext uc_mcontext;
854 sigset_t uc_sigmask;
855 }; */
856/* *INDENT-ON* */
857
858#define SIGFRAME_CODE_OFFSET (4 * 4)
859#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
860
861#define RTSIGFRAME_SIGINFO_SIZE 128
862#define STACK_T_SIZE (3 * 4)
863#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
864#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
865 + RTSIGFRAME_SIGINFO_SIZE \
866 + UCONTEXT_SIGCONTEXT_OFFSET)
867
868#define SIGCONTEXT_PC (1 * 8)
869#define SIGCONTEXT_REGS (2 * 8)
870#define SIGCONTEXT_FPREGS (34 * 8)
871#define SIGCONTEXT_FPCSR (66 * 8 + 4)
872#define SIGCONTEXT_HI (69 * 8)
873#define SIGCONTEXT_LO (70 * 8)
874#define SIGCONTEXT_CAUSE (71 * 8 + 0)
875#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
876
877#define SIGCONTEXT_REG_SIZE 8
878
879static void
880mips_linux_o32_sigframe_init (const struct tramp_frame *self,
881 struct frame_info *next_frame,
882 struct trad_frame_cache *this_cache,
883 CORE_ADDR func)
884{
885 int ireg, reg_position;
886 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
887 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
37c4d197 888 CORE_ADDR regs_base;
5792a79b
DJ		 889
890 if (self == &mips_linux_o32_sigframe)
891 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
892 else
893 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 894
895 /* I'm not proud of this hack. Eventually we will have the
896 infrastructure to indicate the size of saved registers on a
897 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 898 bytes but we only want four. Use regs_base to access any
899 64-bit fields. */
5792a79b 900 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
37c4d197
DJ		 901 regs_base = sigcontext_base + 4;
902 else
903 regs_base = sigcontext_base;
5792a79b
DJ		 904
905#if 0
906 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
37c4d197 907 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 908#endif
909
910 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 911 trad_frame_set_reg_addr (this_cache,
912 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
37c4d197 913 regs_base + SIGCONTEXT_REGS
5792a79b
DJ		 914 + ireg * SIGCONTEXT_REG_SIZE);
915
37c4d197
DJ		 916 /* The way that floating point registers are saved, unfortunately,
917 depends on the architecture the kernel is built for. For the r3000 and
918 tx39, four bytes of each register are at the beginning of each of the
919 32 eight byte slots. For everything else, the registers are saved
920 using double precision; only the even-numbered slots are initialized,
921 and the high bits are the odd-numbered register. Assume the latter
922 layout, since we can't tell, and it's much more common. Which bits are
923 the "high" bits depends on endianness. */
5792a79b 924 for (ireg = 0; ireg < 32; ireg++)
37c4d197
DJ		 925 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1))
926 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
927 sigcontext_base + SIGCONTEXT_FPREGS + 4
928 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
929 else
930 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
931 sigcontext_base + SIGCONTEXT_FPREGS
932 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
5792a79b
DJ		 933
934 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
37c4d197 935 regs_base + SIGCONTEXT_PC);
5792a79b 936
295093a4
MS		 937 trad_frame_set_reg_addr (this_cache,
938 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 939 sigcontext_base + SIGCONTEXT_FPCSR);
940 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
37c4d197 941 regs_base + SIGCONTEXT_HI);
5792a79b 942 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
37c4d197 943 regs_base + SIGCONTEXT_LO);
5792a79b
DJ		 944 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
945 sigcontext_base + SIGCONTEXT_CAUSE);
946 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
947 sigcontext_base + SIGCONTEXT_BADVADDR);
948
949 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
950 trad_frame_set_id (this_cache,
295093a4
MS		 951 frame_id_build (func - SIGFRAME_CODE_OFFSET,
952 func));
5792a79b
DJ		 953}
954
955/* *INDENT-OFF* */
956/* For N32/N64 things look different. There is no non-rt signal frame.
957
958 struct rt_sigframe_n32 {
959 u32 rs_ass[4]; [ argument save space for o32 ]
960 u32 rs_code[2]; [ signal trampoline ]
961 struct siginfo rs_info;
962 struct ucontextn32 rs_uc;
963 };
964
965 struct ucontextn32 {
966 u32 uc_flags;
967 s32 uc_link;
968 stack32_t uc_stack;
969 struct sigcontext uc_mcontext;
970 sigset_t uc_sigmask; [ mask last for extensibility ]
971 };
295093a4 972
5792a79b
DJ		 973 struct rt_sigframe_n32 {
974 u32 rs_ass[4]; [ argument save space for o32 ]
975 u32 rs_code[2]; [ signal trampoline ]
976 struct siginfo rs_info;
977 struct ucontext rs_uc;
978 };
979
980 struct ucontext {
981 unsigned long uc_flags;
982 struct ucontext *uc_link;
983 stack_t uc_stack;
984 struct sigcontext uc_mcontext;
985 sigset_t uc_sigmask; [ mask last for extensibility ]
986 };
987
988 And the sigcontext is different (this is for both n32 and n64):
989
990 struct sigcontext {
991 unsigned long long sc_regs[32];
992 unsigned long long sc_fpregs[32];
993 unsigned long long sc_mdhi;
994 unsigned long long sc_mdlo;
995 unsigned long long sc_pc;
996 unsigned int sc_status;
997 unsigned int sc_fpc_csr;
998 unsigned int sc_fpc_eir;
999 unsigned int sc_used_math;
1000 unsigned int sc_cause;
1001 unsigned int sc_badvaddr;
1002 }; */
1003/* *INDENT-ON* */
1004
1005#define N32_STACK_T_SIZE STACK_T_SIZE
1006#define N64_STACK_T_SIZE (2 * 8 + 4)
1007#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1008#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1009#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1010 + RTSIGFRAME_SIGINFO_SIZE \
1011 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1012#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1013 + RTSIGFRAME_SIGINFO_SIZE \
1014 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1015
1016#define N64_SIGCONTEXT_REGS (0 * 8)
1017#define N64_SIGCONTEXT_FPREGS (32 * 8)
1018#define N64_SIGCONTEXT_HI (64 * 8)
1019#define N64_SIGCONTEXT_LO (65 * 8)
1020#define N64_SIGCONTEXT_PC (66 * 8)
1021#define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1022#define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1023#define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1024#define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1025
1026#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1027
5792a79b
DJ		 1028static void
1029mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1030 struct frame_info *next_frame,
1031 struct trad_frame_cache *this_cache,
1032 CORE_ADDR func)
1033{
1034 int ireg, reg_position;
1035 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
1036 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
1037
1038 if (self == &mips_linux_n32_rt_sigframe)
1039 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
1040 else
1041 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1042
5792a79b
DJ		 1043#if 0
1044 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
1045 sigcontext_base + N64_SIGCONTEXT_REGS);
1046#endif
1047
1048 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 1049 trad_frame_set_reg_addr (this_cache,
1050 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
5792a79b
DJ		 1051 sigcontext_base + N64_SIGCONTEXT_REGS
1052 + ireg * N64_SIGCONTEXT_REG_SIZE);
1053
1054 for (ireg = 0; ireg < 32; ireg++)
1055 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1056 sigcontext_base + N64_SIGCONTEXT_FPREGS
1057 + ireg * N64_SIGCONTEXT_REG_SIZE);
1058
1059 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1060 sigcontext_base + N64_SIGCONTEXT_PC);
1061
295093a4
MS		 1062 trad_frame_set_reg_addr (this_cache,
1063 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 1064 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1065 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1066 sigcontext_base + N64_SIGCONTEXT_HI);
1067 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1068 sigcontext_base + N64_SIGCONTEXT_LO);
1069 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1070 sigcontext_base + N64_SIGCONTEXT_CAUSE);
1071 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1072 sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1073
1074 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1075 trad_frame_set_id (this_cache,
295093a4
MS		 1076 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1077 func));
5792a79b
DJ		 1078}
1079
9f62d0e2
DJ		 1080/* Wrapper functions. These are only used by libthread_db. */
1081
1082void
d37eb719 1083supply_gregset (mips_elf_gregset_t *gregsetp)
9f62d0e2
DJ		 1084{
1085 if (mips_isa_regsize (current_gdbarch) == 4)
1086 mips_supply_gregset (gregsetp);
1087 else
1088 mips64_supply_gregset ((void *) gregsetp);
1089}
1090
1091void
d37eb719 1092fill_gregset (mips_elf_gregset_t *gregsetp, int regno)
9f62d0e2
DJ		 1093{
1094 if (mips_isa_regsize (current_gdbarch) == 4)
1095 mips_fill_gregset (gregsetp, regno);
1096 else
1097 mips64_fill_gregset ((void *) gregsetp, regno);
1098}
1099
1100/* Likewise, unpack an elf_fpregset_t. */
1101
1102void
d37eb719 1103supply_fpregset (mips_elf_fpregset_t *fpregsetp)
9f62d0e2
DJ		 1104{
1105 if (mips_isa_regsize (current_gdbarch) == 4)
1106 mips_supply_fpregset (fpregsetp);
1107 else
1108 mips64_supply_fpregset ((void *) fpregsetp);
1109}
1110
1111/* Likewise, pack one or all floating point registers into an
1112 elf_fpregset_t. */
1113
1114void
d37eb719 1115fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno)
9f62d0e2
DJ		 1116{
1117 if (mips_isa_regsize (current_gdbarch) == 4)
1118 mips_fill_fpregset (fpregsetp, regno);
1119 else
1120 mips64_fill_fpregset ((void *) fpregsetp, regno);
1121}
1122
5792a79b
DJ		 1123/* Initialize one of the GNU/Linux OS ABIs. */
1124
19ed69dd 1125static void
295093a4
MS		 1126mips_linux_init_abi (struct gdbarch_info info,
1127 struct gdbarch *gdbarch)
19ed69dd 1128{
96f026fc
KB		 1129 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1130 enum mips_abi abi = mips_abi (gdbarch);
1131
1132 switch (abi)
1133 {
1134 case MIPS_ABI_O32:
1135 set_gdbarch_get_longjmp_target (gdbarch,
1136 mips_linux_get_longjmp_target);
1137 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1138 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1139 set_mips_linux_register_addr (gdbarch, mips_linux_register_addr);
fb2be677
AC		 1140 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1141 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
96f026fc
KB		 1142 break;
1143 case MIPS_ABI_N32:
1144 set_gdbarch_get_longjmp_target (gdbarch,
1145 mips_linux_get_longjmp_target);
1146 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1147 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1148 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1149 set_gdbarch_long_double_bit (gdbarch, 128);
1150 /* These floatformats should probably be renamed. MIPS uses
1151 the same 128-bit IEEE floating point format that IA-64 uses,
1152 except that the quiet/signalling NaN bit is reversed (GDB
1153 does not distinguish between quiet and signalling NaNs). */
1154 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1155 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1156 else
1157 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1158 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
96f026fc
KB		 1159 break;
1160 case MIPS_ABI_N64:
1161 set_gdbarch_get_longjmp_target (gdbarch,
1162 mips64_linux_get_longjmp_target);
1163 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1164 (gdbarch, svr4_lp64_fetch_link_map_offsets);
96f026fc 1165 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1166 set_gdbarch_long_double_bit (gdbarch, 128);
1167 /* These floatformats should probably be renamed. MIPS uses
1168 the same 128-bit IEEE floating point format that IA-64 uses,
1169 except that the quiet/signalling NaN bit is reversed (GDB
1170 does not distinguish between quiet and signalling NaNs). */
1171 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1172 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1173 else
1174 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1175 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
96f026fc
KB		 1176 break;
1177 default:
e2e0b3e5 1178 internal_error (__FILE__, __LINE__, _("can't handle ABI"));
96f026fc
KB		 1179 break;
1180 }
6de918a6
DJ		 1181
1182 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1183
0d0266c6 1184 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1185
1186 /* Enable TLS support. */
1187 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1188 svr4_fetch_objfile_link_map);
19ed69dd
KB		 1189}
1190
2aa830e4 1191void
d1bacddc 1192_initialize_mips_linux_tdep (void)
2aa830e4 1193{
96f026fc
KB		 1194 const struct bfd_arch_info *arch_info;
1195
1196 register_addr_data =
030f20e1 1197 gdbarch_data_register_post_init (init_register_addr_data);
96f026fc
KB		 1198
1199 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1200 arch_info != NULL;
1201 arch_info = arch_info->next)
1202 {
295093a4
MS		 1203 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1204 GDB_OSABI_LINUX,
96f026fc
KB		 1205 mips_linux_init_abi);
1206 }
1207
00e32a35 1208 deprecated_add_core_fns (&regset_core_fns);
2aa830e4 1209}
GDB Binutils - Deliverables
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