Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
edfae063 AC |
47 | #include "frame-unwind.h" |
48 | #include "frame-base.h" | |
49 | #include "trad-frame.h" | |
7d9b040b | 50 | #include "infcall.h" |
fed7ba43 | 51 | #include "floatformat.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
2bd0c3d7 | 54 | #include "dwarf2-frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
4cc0665f MR |
63 | static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR); |
64 | static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
65 | int); | |
66 | static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
67 | int); | |
68 | ||
24e05951 | 69 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
70 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
71 | #define ST0_FR (1 << 26) | |
72 | ||
b0069a17 AC |
73 | /* The sizes of floating point registers. */ |
74 | ||
75 | enum | |
76 | { | |
77 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
78 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
79 | }; | |
80 | ||
1a69e1e4 DJ |
81 | enum |
82 | { | |
83 | MIPS32_REGSIZE = 4, | |
84 | MIPS64_REGSIZE = 8 | |
85 | }; | |
0dadbba0 | 86 | |
2e4ebe70 DJ |
87 | static const char *mips_abi_string; |
88 | ||
40478521 | 89 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
90 | "auto", |
91 | "n32", | |
92 | "o32", | |
28d169de | 93 | "n64", |
2e4ebe70 DJ |
94 | "o64", |
95 | "eabi32", | |
96 | "eabi64", | |
97 | NULL | |
98 | }; | |
99 | ||
4cc0665f MR |
100 | /* For backwards compatibility we default to MIPS16. This flag is |
101 | overridden as soon as unambiguous ELF file flags tell us the | |
102 | compressed ISA encoding used. */ | |
103 | static const char mips_compression_mips16[] = "mips16"; | |
104 | static const char mips_compression_micromips[] = "micromips"; | |
105 | static const char *const mips_compression_strings[] = | |
106 | { | |
107 | mips_compression_mips16, | |
108 | mips_compression_micromips, | |
109 | NULL | |
110 | }; | |
111 | ||
112 | static const char *mips_compression_string = mips_compression_mips16; | |
113 | ||
f8b73d13 DJ |
114 | /* The standard register names, and all the valid aliases for them. */ |
115 | struct register_alias | |
116 | { | |
117 | const char *name; | |
118 | int regnum; | |
119 | }; | |
120 | ||
121 | /* Aliases for o32 and most other ABIs. */ | |
122 | const struct register_alias mips_o32_aliases[] = { | |
123 | { "ta0", 12 }, | |
124 | { "ta1", 13 }, | |
125 | { "ta2", 14 }, | |
126 | { "ta3", 15 } | |
127 | }; | |
128 | ||
129 | /* Aliases for n32 and n64. */ | |
130 | const struct register_alias mips_n32_n64_aliases[] = { | |
131 | { "ta0", 8 }, | |
132 | { "ta1", 9 }, | |
133 | { "ta2", 10 }, | |
134 | { "ta3", 11 } | |
135 | }; | |
136 | ||
137 | /* Aliases for ABI-independent registers. */ | |
138 | const struct register_alias mips_register_aliases[] = { | |
139 | /* The architecture manuals specify these ABI-independent names for | |
140 | the GPRs. */ | |
141 | #define R(n) { "r" #n, n } | |
142 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
143 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
144 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
145 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
146 | #undef R | |
147 | ||
148 | /* k0 and k1 are sometimes called these instead (for "kernel | |
149 | temp"). */ | |
150 | { "kt0", 26 }, | |
151 | { "kt1", 27 }, | |
152 | ||
153 | /* This is the traditional GDB name for the CP0 status register. */ | |
154 | { "sr", MIPS_PS_REGNUM }, | |
155 | ||
156 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
157 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
158 | ||
159 | /* This is the traditional GDB name for the FCSR. */ | |
160 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
161 | }; | |
162 | ||
865093a3 AR |
163 | const struct register_alias mips_numeric_register_aliases[] = { |
164 | #define R(n) { #n, n } | |
165 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
166 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
167 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
168 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
169 | #undef R | |
170 | }; | |
171 | ||
c906108c SS |
172 | #ifndef MIPS_DEFAULT_FPU_TYPE |
173 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
174 | #endif | |
175 | static int mips_fpu_type_auto = 1; | |
176 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 177 | |
ccce17b0 | 178 | static unsigned int mips_debug = 0; |
7a292a7a | 179 | |
29709017 DJ |
180 | /* Properties (for struct target_desc) describing the g/G packet |
181 | layout. */ | |
182 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
183 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
184 | ||
4eb0ad19 DJ |
185 | struct target_desc *mips_tdesc_gp32; |
186 | struct target_desc *mips_tdesc_gp64; | |
187 | ||
56cea623 AC |
188 | const struct mips_regnum * |
189 | mips_regnum (struct gdbarch *gdbarch) | |
190 | { | |
191 | return gdbarch_tdep (gdbarch)->regnum; | |
192 | } | |
193 | ||
194 | static int | |
195 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
196 | { | |
197 | return mips_regnum (gdbarch)->fp0 + 12; | |
198 | } | |
199 | ||
004159a2 MR |
200 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
201 | or cooked. Otherwise return 0. */ | |
202 | ||
203 | static int | |
204 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
205 | { | |
206 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
207 | ||
208 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
209 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
210 | } | |
211 | ||
74ed0bb4 MD |
212 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
213 | == MIPS_ABI_EABI32 \ | |
214 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 215 | |
025bb325 MS |
216 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
217 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 218 | |
025bb325 MS |
219 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
220 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 221 | |
74ed0bb4 | 222 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 223 | |
d1973055 KB |
224 | /* Return the MIPS ABI associated with GDBARCH. */ |
225 | enum mips_abi | |
226 | mips_abi (struct gdbarch *gdbarch) | |
227 | { | |
228 | return gdbarch_tdep (gdbarch)->mips_abi; | |
229 | } | |
230 | ||
4246e332 | 231 | int |
1b13c4f6 | 232 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 233 | { |
29709017 DJ |
234 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
235 | ||
236 | /* If we know how big the registers are, use that size. */ | |
237 | if (tdep->register_size_valid_p) | |
238 | return tdep->register_size; | |
239 | ||
240 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
241 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
242 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
243 | } | |
244 | ||
025bb325 | 245 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 246 | |
e6bc2e8a | 247 | unsigned int |
13326b4e | 248 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 249 | { |
1a69e1e4 DJ |
250 | switch (mips_abi (gdbarch)) |
251 | { | |
252 | case MIPS_ABI_EABI32: | |
253 | case MIPS_ABI_O32: | |
254 | return 4; | |
255 | case MIPS_ABI_N32: | |
256 | case MIPS_ABI_N64: | |
257 | case MIPS_ABI_O64: | |
258 | case MIPS_ABI_EABI64: | |
259 | return 8; | |
260 | case MIPS_ABI_UNKNOWN: | |
261 | case MIPS_ABI_LAST: | |
262 | default: | |
263 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
264 | } | |
d929b26f AC |
265 | } |
266 | ||
4cc0665f MR |
267 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
268 | are some functions to handle addresses associated with compressed | |
269 | code including but not limited to testing, setting, or clearing | |
270 | bit 0 of such addresses. */ | |
742c84f6 | 271 | |
4cc0665f MR |
272 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
273 | ||
274 | static int | |
275 | is_mips16_isa (struct gdbarch *gdbarch) | |
276 | { | |
277 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
278 | } | |
279 | ||
280 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
281 | ||
282 | static int | |
283 | is_micromips_isa (struct gdbarch *gdbarch) | |
284 | { | |
285 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
286 | } | |
287 | ||
288 | /* Return one iff ADDR denotes compressed code. */ | |
289 | ||
290 | static int | |
291 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
292 | { |
293 | return ((addr) & 1); | |
294 | } | |
295 | ||
4cc0665f MR |
296 | /* Return one iff ADDR denotes standard ISA code. */ |
297 | ||
298 | static int | |
299 | is_mips_addr (CORE_ADDR addr) | |
300 | { | |
301 | return !is_compact_addr (addr); | |
302 | } | |
303 | ||
304 | /* Return one iff ADDR denotes MIPS16 code. */ | |
305 | ||
306 | static int | |
307 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
308 | { | |
309 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
310 | } | |
311 | ||
312 | /* Return one iff ADDR denotes microMIPS code. */ | |
313 | ||
314 | static int | |
315 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
316 | { | |
317 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
318 | } | |
319 | ||
320 | /* Strip the ISA (compression) bit off from ADDR. */ | |
321 | ||
742c84f6 | 322 | static CORE_ADDR |
4cc0665f | 323 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
324 | { |
325 | return ((addr) & ~(CORE_ADDR) 1); | |
326 | } | |
327 | ||
4cc0665f MR |
328 | /* Add the ISA (compression) bit to ADDR. */ |
329 | ||
742c84f6 | 330 | static CORE_ADDR |
4cc0665f | 331 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
332 | { |
333 | return ((addr) | (CORE_ADDR) 1); | |
334 | } | |
335 | ||
71b8ef93 | 336 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
337 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
338 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 339 | |
4cc0665f MR |
340 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
341 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
342 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
343 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
344 | symbols only; for synthetic symbols such as for PLT stubs that have |
345 | no ELF-private part at all the MIPS BFD backend arranges for this | |
346 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 347 | |
4cc0665f MR |
348 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
349 | in a minimal symbol. */ | |
5a89d8aa | 350 | |
5a89d8aa | 351 | static void |
6d82d43b AC |
352 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
353 | { | |
4cc0665f | 354 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 355 | unsigned char st_other; |
4cc0665f | 356 | |
1bbce132 MR |
357 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
358 | st_other = elfsym->internal_elf_sym.st_other; | |
359 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
360 | st_other = sym->udata.i; | |
361 | else | |
4cc0665f MR |
362 | return; |
363 | ||
1bbce132 | 364 | if (ELF_ST_IS_MICROMIPS (st_other)) |
4cc0665f | 365 | MSYMBOL_TARGET_FLAG_2 (msym) = 1; |
1bbce132 | 366 | else if (ELF_ST_IS_MIPS16 (st_other)) |
4cc0665f MR |
367 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
368 | } | |
369 | ||
370 | /* Return one iff MSYM refers to standard ISA code. */ | |
371 | ||
372 | static int | |
373 | msymbol_is_mips (struct minimal_symbol *msym) | |
374 | { | |
375 | return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym)); | |
5a89d8aa MS |
376 | } |
377 | ||
4cc0665f MR |
378 | /* Return one iff MSYM refers to MIPS16 code. */ |
379 | ||
71b8ef93 | 380 | static int |
4cc0665f | 381 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 382 | { |
b887350f | 383 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
384 | } |
385 | ||
4cc0665f MR |
386 | /* Return one iff MSYM refers to microMIPS code. */ |
387 | ||
388 | static int | |
389 | msymbol_is_micromips (struct minimal_symbol *msym) | |
390 | { | |
391 | return MSYMBOL_TARGET_FLAG_2 (msym); | |
392 | } | |
393 | ||
88658117 AC |
394 | /* XFER a value from the big/little/left end of the register. |
395 | Depending on the size of the value it might occupy the entire | |
396 | register or just part of it. Make an allowance for this, aligning | |
397 | things accordingly. */ | |
398 | ||
399 | static void | |
ba32f989 DJ |
400 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
401 | int reg_num, int length, | |
870cd05e MK |
402 | enum bfd_endian endian, gdb_byte *in, |
403 | const gdb_byte *out, int buf_offset) | |
88658117 | 404 | { |
88658117 | 405 | int reg_offset = 0; |
72a155b4 UW |
406 | |
407 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
408 | /* Need to transfer the left or right part of the register, based on |
409 | the targets byte order. */ | |
88658117 AC |
410 | switch (endian) |
411 | { | |
412 | case BFD_ENDIAN_BIG: | |
72a155b4 | 413 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
414 | break; |
415 | case BFD_ENDIAN_LITTLE: | |
416 | reg_offset = 0; | |
417 | break; | |
6d82d43b | 418 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
419 | reg_offset = 0; |
420 | break; | |
421 | default: | |
e2e0b3e5 | 422 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
423 | } |
424 | if (mips_debug) | |
cb1d2653 AC |
425 | fprintf_unfiltered (gdb_stderr, |
426 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
427 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
428 | if (mips_debug && out != NULL) |
429 | { | |
430 | int i; | |
cb1d2653 | 431 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 432 | for (i = 0; i < length; i++) |
cb1d2653 | 433 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
434 | } |
435 | if (in != NULL) | |
6d82d43b AC |
436 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
437 | in + buf_offset); | |
88658117 | 438 | if (out != NULL) |
6d82d43b AC |
439 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
440 | out + buf_offset); | |
88658117 AC |
441 | if (mips_debug && in != NULL) |
442 | { | |
443 | int i; | |
cb1d2653 | 444 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 445 | for (i = 0; i < length; i++) |
cb1d2653 | 446 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
447 | } |
448 | if (mips_debug) | |
449 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
450 | } | |
451 | ||
dd824b04 DJ |
452 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
453 | compatiblity mode. A return value of 1 means that we have | |
454 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
455 | ||
456 | static int | |
9c9acae0 | 457 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 458 | { |
72a155b4 | 459 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
460 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
461 | meaningful. */ | |
72a155b4 | 462 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
463 | return 0; |
464 | ||
465 | #if 0 | |
466 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
467 | in all the places we deal with FP registers. PR gdb/413. */ | |
468 | /* Otherwise check the FR bit in the status register - it controls | |
469 | the FP compatiblity mode. If it is clear we are in compatibility | |
470 | mode. */ | |
9c9acae0 | 471 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
472 | return 1; |
473 | #endif | |
361d1df0 | 474 | |
dd824b04 DJ |
475 | return 0; |
476 | } | |
477 | ||
7a292a7a | 478 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 479 | |
74ed0bb4 | 480 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 481 | |
a14ed312 | 482 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 483 | |
025bb325 | 484 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
485 | |
486 | static struct cmd_list_element *setmipscmdlist = NULL; | |
487 | static struct cmd_list_element *showmipscmdlist = NULL; | |
488 | ||
5e2e9765 KB |
489 | /* Integer registers 0 thru 31 are handled explicitly by |
490 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 491 | are listed in the following tables. */ |
691c0433 | 492 | |
6d82d43b AC |
493 | enum |
494 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
495 | |
496 | /* Generic MIPS. */ | |
497 | ||
498 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
499 | "sr", "lo", "hi", "bad", "cause", "pc", |
500 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
501 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
502 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
503 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 504 | "fsr", "fir", |
691c0433 AC |
505 | }; |
506 | ||
507 | /* Names of IDT R3041 registers. */ | |
508 | ||
509 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
510 | "sr", "lo", "hi", "bad", "cause", "pc", |
511 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
512 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
513 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
514 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
515 | "fsr", "fir", "", /*"fp" */ "", | |
516 | "", "", "bus", "ccfg", "", "", "", "", | |
517 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
518 | }; |
519 | ||
520 | /* Names of tx39 registers. */ | |
521 | ||
522 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
523 | "sr", "lo", "hi", "bad", "cause", "pc", |
524 | "", "", "", "", "", "", "", "", | |
525 | "", "", "", "", "", "", "", "", | |
526 | "", "", "", "", "", "", "", "", | |
527 | "", "", "", "", "", "", "", "", | |
528 | "", "", "", "", | |
529 | "", "", "", "", "", "", "", "", | |
1faeff08 | 530 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
531 | }; |
532 | ||
533 | /* Names of IRIX registers. */ | |
534 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
535 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
536 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
537 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
538 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
539 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
540 | }; |
541 | ||
44099a67 | 542 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
543 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
544 | "sr", "lo", "hi", "bad", "cause", "pc", | |
545 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
546 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
547 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
548 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
549 | "fsr", "fir" | |
550 | }; | |
551 | ||
cce74817 | 552 | |
5e2e9765 | 553 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 554 | static const char * |
d93859e2 | 555 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 556 | { |
d93859e2 | 557 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
558 | /* GPR names for all ABIs other than n32/n64. */ |
559 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
560 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
561 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
562 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
563 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
564 | }; |
565 | ||
566 | /* GPR names for n32 and n64 ABIs. */ | |
567 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
568 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
569 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
570 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
571 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
572 | }; |
573 | ||
d93859e2 | 574 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 575 | |
f57d151a | 576 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
577 | but then don't make the raw register names visible. This (upper) |
578 | range of user visible register numbers are the pseudo-registers. | |
579 | ||
580 | This approach was adopted accommodate the following scenario: | |
581 | It is possible to debug a 64-bit device using a 32-bit | |
582 | programming model. In such instances, the raw registers are | |
583 | configured to be 64-bits wide, while the pseudo registers are | |
584 | configured to be 32-bits wide. The registers that the user | |
585 | sees - the pseudo registers - match the users expectations | |
586 | given the programming model being used. */ | |
d93859e2 UW |
587 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
588 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
589 | return ""; |
590 | ||
5e2e9765 KB |
591 | /* The MIPS integer registers are always mapped from 0 to 31. The |
592 | names of the registers (which reflects the conventions regarding | |
593 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 594 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
595 | { |
596 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 597 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 598 | else |
a4b8ebc8 | 599 | return mips_gpr_names[rawnum]; |
5e2e9765 | 600 | } |
d93859e2 UW |
601 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
602 | return tdesc_register_name (gdbarch, rawnum); | |
603 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
604 | { |
605 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
606 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
607 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
608 | return ""; | |
691c0433 | 609 | } |
5e2e9765 KB |
610 | else |
611 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 612 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 613 | } |
5e2e9765 | 614 | |
a4b8ebc8 | 615 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 616 | |
a4b8ebc8 AC |
617 | static int |
618 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
619 | struct reggroup *reggroup) | |
620 | { | |
621 | int vector_p; | |
622 | int float_p; | |
623 | int raw_p; | |
72a155b4 UW |
624 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
625 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
626 | if (reggroup == all_reggroup) |
627 | return pseudo; | |
628 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
629 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
630 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
631 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
632 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
633 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
634 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
635 | return 0; |
636 | if (reggroup == float_reggroup) | |
637 | return float_p && pseudo; | |
638 | if (reggroup == vector_reggroup) | |
639 | return vector_p && pseudo; | |
640 | if (reggroup == general_reggroup) | |
641 | return (!vector_p && !float_p) && pseudo; | |
642 | /* Save the pseudo registers. Need to make certain that any code | |
643 | extracting register values from a saved register cache also uses | |
644 | pseudo registers. */ | |
645 | if (reggroup == save_reggroup) | |
646 | return raw_p && pseudo; | |
647 | /* Restore the same pseudo register. */ | |
648 | if (reggroup == restore_reggroup) | |
649 | return raw_p && pseudo; | |
6d82d43b | 650 | return 0; |
a4b8ebc8 AC |
651 | } |
652 | ||
f8b73d13 DJ |
653 | /* Return the groups that a MIPS register can be categorised into. |
654 | This version is only used if we have a target description which | |
655 | describes real registers (and their groups). */ | |
656 | ||
657 | static int | |
658 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
659 | struct reggroup *reggroup) | |
660 | { | |
661 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
662 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
663 | int ret; | |
664 | ||
665 | /* Only save, restore, and display the pseudo registers. Need to | |
666 | make certain that any code extracting register values from a | |
667 | saved register cache also uses pseudo registers. | |
668 | ||
669 | Note: saving and restoring the pseudo registers is slightly | |
670 | strange; if we have 64 bits, we should save and restore all | |
671 | 64 bits. But this is hard and has little benefit. */ | |
672 | if (!pseudo) | |
673 | return 0; | |
674 | ||
675 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
676 | if (ret != -1) | |
677 | return ret; | |
678 | ||
679 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
680 | } | |
681 | ||
a4b8ebc8 | 682 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 683 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 684 | registers. Take care of alignment and size problems. */ |
c5aa993b | 685 | |
05d1431c | 686 | static enum register_status |
a4b8ebc8 | 687 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 688 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 689 | { |
72a155b4 UW |
690 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
691 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
692 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 693 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 694 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
695 | else if (register_size (gdbarch, rawnum) > |
696 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 697 | { |
8bdf35dc | 698 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 699 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 700 | else |
8bdf35dc KB |
701 | { |
702 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
703 | LONGEST regval; | |
05d1431c PA |
704 | enum register_status status; |
705 | ||
706 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
707 | if (status == REG_VALID) | |
708 | store_signed_integer (buf, 4, byte_order, regval); | |
709 | return status; | |
8bdf35dc | 710 | } |
47ebcfbe AC |
711 | } |
712 | else | |
e2e0b3e5 | 713 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
714 | } |
715 | ||
716 | static void | |
6d82d43b AC |
717 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
718 | struct regcache *regcache, int cookednum, | |
47a35522 | 719 | const gdb_byte *buf) |
a4b8ebc8 | 720 | { |
72a155b4 UW |
721 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
722 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
723 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 724 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 725 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
726 | else if (register_size (gdbarch, rawnum) > |
727 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 728 | { |
8bdf35dc | 729 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
730 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
731 | else | |
8bdf35dc KB |
732 | { |
733 | /* Sign extend the shortened version of the register prior | |
734 | to placing it in the raw register. This is required for | |
735 | some mips64 parts in order to avoid unpredictable behavior. */ | |
736 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
737 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
738 | regcache_raw_write_signed (regcache, rawnum, regval); | |
739 | } | |
47ebcfbe AC |
740 | } |
741 | else | |
e2e0b3e5 | 742 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 743 | } |
c5aa993b | 744 | |
175ff332 HZ |
745 | static int |
746 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
747 | struct agent_expr *ax, int reg) | |
748 | { | |
749 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
750 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
751 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
752 | ||
753 | ax_reg_mask (ax, rawnum); | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
758 | static int | |
759 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
760 | struct agent_expr *ax, int reg) | |
761 | { | |
762 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
763 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
764 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
765 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
766 | { | |
767 | ax_reg (ax, rawnum); | |
768 | ||
769 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
770 | { | |
771 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
772 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
773 | { | |
774 | ax_const_l (ax, 32); | |
775 | ax_simple (ax, aop_lsh); | |
776 | } | |
777 | ax_const_l (ax, 32); | |
778 | ax_simple (ax, aop_rsh_signed); | |
779 | } | |
780 | } | |
781 | else | |
782 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
4cc0665f | 787 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 788 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
789 | |
790 | /* Heuristic_proc_start may hunt through the text section for a long | |
791 | time across a 2400 baud serial line. Allows the user to limit this | |
792 | search. */ | |
793 | ||
44096aee | 794 | static int heuristic_fence_post = 0; |
c906108c | 795 | |
46cd78fb | 796 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
797 | register N. NOTE: This defines the pseudo register type so need to |
798 | rebuild the architecture vector. */ | |
43e526b9 JM |
799 | |
800 | static int mips64_transfers_32bit_regs_p = 0; | |
801 | ||
719ec221 AC |
802 | static void |
803 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
804 | struct cmd_list_element *c) | |
43e526b9 | 805 | { |
719ec221 AC |
806 | struct gdbarch_info info; |
807 | gdbarch_info_init (&info); | |
808 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
809 | instead of relying on globals. Doing that would let generic code | |
810 | handle the search for this specific architecture. */ | |
811 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 812 | { |
719ec221 | 813 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 814 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 815 | } |
a4b8ebc8 AC |
816 | } |
817 | ||
47ebcfbe | 818 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 819 | |
ee51a8c7 KB |
820 | /* This predicate tests for the case of an 8 byte floating point |
821 | value that is being transferred to or from a pair of floating point | |
822 | registers each of which are (or are considered to be) only 4 bytes | |
823 | wide. */ | |
ff2e87ac | 824 | static int |
ee51a8c7 KB |
825 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
826 | struct type *type) | |
ff2e87ac | 827 | { |
0abe36f5 MD |
828 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
829 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 830 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 831 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
832 | } |
833 | ||
ee51a8c7 KB |
834 | /* This predicate tests for the case of a value of less than 8 |
835 | bytes in width that is being transfered to or from an 8 byte | |
836 | general purpose register. */ | |
837 | static int | |
838 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
839 | struct type *type) | |
840 | { | |
841 | int num_regs = gdbarch_num_regs (gdbarch); | |
842 | ||
843 | return (register_size (gdbarch, regnum) == 8 | |
844 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
845 | && TYPE_LENGTH (type) < 8); | |
846 | } | |
847 | ||
848 | static int | |
025bb325 MS |
849 | mips_convert_register_p (struct gdbarch *gdbarch, |
850 | int regnum, struct type *type) | |
ee51a8c7 | 851 | { |
eaa05d59 MR |
852 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
853 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
854 | } |
855 | ||
8dccd430 | 856 | static int |
ff2e87ac | 857 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
858 | struct type *type, gdb_byte *to, |
859 | int *optimizedp, int *unavailablep) | |
102182a9 | 860 | { |
ee51a8c7 KB |
861 | struct gdbarch *gdbarch = get_frame_arch (frame); |
862 | ||
863 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
864 | { | |
865 | get_frame_register (frame, regnum + 0, to + 4); | |
866 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
867 | |
868 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
869 | optimizedp, unavailablep)) | |
870 | return 0; | |
871 | ||
872 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
873 | optimizedp, unavailablep)) | |
874 | return 0; | |
875 | *optimizedp = *unavailablep = 0; | |
876 | return 1; | |
ee51a8c7 KB |
877 | } |
878 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
879 | { | |
880 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
881 | CORE_ADDR offset; |
882 | ||
883 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
884 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
885 | optimizedp, unavailablep)) | |
886 | return 0; | |
887 | ||
888 | *optimizedp = *unavailablep = 0; | |
889 | return 1; | |
ee51a8c7 KB |
890 | } |
891 | else | |
892 | { | |
893 | internal_error (__FILE__, __LINE__, | |
894 | _("mips_register_to_value: unrecognized case")); | |
895 | } | |
102182a9 MS |
896 | } |
897 | ||
42c466d7 | 898 | static void |
ff2e87ac | 899 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 900 | struct type *type, const gdb_byte *from) |
102182a9 | 901 | { |
ee51a8c7 KB |
902 | struct gdbarch *gdbarch = get_frame_arch (frame); |
903 | ||
904 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
905 | { | |
906 | put_frame_register (frame, regnum + 0, from + 4); | |
907 | put_frame_register (frame, regnum + 1, from + 0); | |
908 | } | |
909 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
910 | { | |
911 | gdb_byte fill[8]; | |
912 | int len = TYPE_LENGTH (type); | |
913 | ||
914 | /* Sign extend values, irrespective of type, that are stored to | |
915 | a 64-bit general purpose register. (32-bit unsigned values | |
916 | are stored as signed quantities within a 64-bit register. | |
917 | When performing an operation, in compiled code, that combines | |
918 | a 32-bit unsigned value with a signed 64-bit value, a type | |
919 | conversion is first performed that zeroes out the high 32 bits.) */ | |
920 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
921 | { | |
922 | if (from[0] & 0x80) | |
923 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
924 | else | |
925 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
926 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
927 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
928 | } | |
929 | else | |
930 | { | |
931 | if (from[len-1] & 0x80) | |
932 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
933 | else | |
934 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
935 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
936 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
937 | } | |
938 | } | |
939 | else | |
940 | { | |
941 | internal_error (__FILE__, __LINE__, | |
942 | _("mips_value_to_register: unrecognized case")); | |
943 | } | |
102182a9 MS |
944 | } |
945 | ||
a4b8ebc8 AC |
946 | /* Return the GDB type object for the "standard" data type of data in |
947 | register REG. */ | |
78fde5f8 KB |
948 | |
949 | static struct type * | |
a4b8ebc8 AC |
950 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
951 | { | |
72a155b4 | 952 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 953 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 954 | { |
5ef80fb0 | 955 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 956 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 957 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 958 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 959 | else |
27067745 | 960 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 961 | } |
72a155b4 | 962 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
963 | { |
964 | /* The raw or ISA registers. These are all sized according to | |
965 | the ISA regsize. */ | |
966 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 967 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 968 | else |
df4df182 | 969 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 970 | } |
78fde5f8 | 971 | else |
d5ac5a39 | 972 | { |
1faeff08 MR |
973 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
974 | ||
d5ac5a39 AC |
975 | /* The cooked or ABI registers. These are sized according to |
976 | the ABI (with a few complications). */ | |
1faeff08 MR |
977 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
978 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
979 | return builtin_type (gdbarch)->builtin_int32; | |
980 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
981 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
982 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
983 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
984 | /* The pseudo/cooked view of the embedded registers is always |
985 | 32-bit. The raw view is handled below. */ | |
df4df182 | 986 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
987 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
988 | /* The target, while possibly using a 64-bit register buffer, | |
989 | is only transfering 32-bits of each integer register. | |
990 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 991 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
992 | else if (mips_abi_regsize (gdbarch) == 4) |
993 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
994 | 32- or 64-bit). */ | |
df4df182 | 995 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
996 | else |
997 | /* 64-bit ABI. */ | |
df4df182 | 998 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 999 | } |
78fde5f8 KB |
1000 | } |
1001 | ||
f8b73d13 DJ |
1002 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1003 | ABI-level view. This function is only called if there is a target | |
1004 | description which includes registers, so we know precisely the | |
1005 | types of hardware registers. */ | |
1006 | ||
1007 | static struct type * | |
1008 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1009 | { | |
1010 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1011 | int rawnum = regnum % num_regs; |
1012 | struct type *rawtype; | |
1013 | ||
1014 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1015 | ||
1016 | /* Absent registers are still absent. */ | |
1017 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1018 | if (TYPE_LENGTH (rawtype) == 0) | |
1019 | return rawtype; | |
1020 | ||
de13fcf2 | 1021 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1022 | /* Present the floating point registers however the hardware did; |
1023 | do not try to convert between FPU layouts. */ | |
1024 | return rawtype; | |
1025 | ||
f8b73d13 DJ |
1026 | /* Use pointer types for registers if we can. For n32 we can not, |
1027 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1028 | if (mips_abi_regsize (gdbarch) |
1029 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1030 | { |
1faeff08 MR |
1031 | if (rawnum == MIPS_SP_REGNUM |
1032 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1033 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1034 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1035 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1036 | } |
1037 | ||
1038 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1039 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1040 | || rawnum == mips_regnum (gdbarch)->lo | |
1041 | || rawnum == mips_regnum (gdbarch)->hi | |
1042 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1043 | || rawnum == mips_regnum (gdbarch)->cause | |
1044 | || rawnum == mips_regnum (gdbarch)->pc | |
1045 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1046 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1047 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1048 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1049 | |
1faeff08 MR |
1050 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
1051 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
1052 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
1053 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
1054 | { | |
1055 | /* The pseudo/cooked view of embedded registers is always | |
1056 | 32-bit, even if the target transfers 64-bit values for them. | |
1057 | New targets relying on XML descriptions should only transfer | |
1058 | the necessary 32 bits, but older versions of GDB expected 64, | |
1059 | so allow the target to provide 64 bits without interfering | |
1060 | with the displayed type. */ | |
1061 | return builtin_type (gdbarch)->builtin_int32; | |
1062 | } | |
1063 | ||
f8b73d13 DJ |
1064 | /* For all other registers, pass through the hardware type. */ |
1065 | return rawtype; | |
1066 | } | |
bcb0cc15 | 1067 | |
025bb325 | 1068 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1069 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1070 | |
1071 | static int | |
480d3dd2 | 1072 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1073 | { |
1074 | switch (mask_address_var) | |
1075 | { | |
7f19b9a2 | 1076 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1077 | return 1; |
7f19b9a2 | 1078 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1079 | return 0; |
1080 | break; | |
7f19b9a2 | 1081 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1082 | return tdep->default_mask_address_p; |
4014092b | 1083 | default: |
025bb325 MS |
1084 | internal_error (__FILE__, __LINE__, |
1085 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1086 | return -1; |
361d1df0 | 1087 | } |
4014092b AC |
1088 | } |
1089 | ||
1090 | static void | |
08546159 AC |
1091 | show_mask_address (struct ui_file *file, int from_tty, |
1092 | struct cmd_list_element *c, const char *value) | |
4014092b | 1093 | { |
f5656ead | 1094 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); |
08546159 AC |
1095 | |
1096 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1097 | switch (mask_address_var) |
1098 | { | |
7f19b9a2 | 1099 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1100 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1101 | break; | |
7f19b9a2 | 1102 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1103 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1104 | break; | |
7f19b9a2 | 1105 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1106 | printf_filtered |
1107 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1108 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1109 | break; |
1110 | default: | |
e2e0b3e5 | 1111 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1112 | break; |
361d1df0 | 1113 | } |
4014092b | 1114 | } |
c906108c | 1115 | |
4cc0665f MR |
1116 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1117 | function. */ | |
1118 | ||
1119 | int | |
1120 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1121 | { | |
7cbd4a93 | 1122 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1123 | |
1124 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1125 | stored by elfread.c in the high bit of the info field. Use this | |
1126 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1127 | of the address is clear, then this is a standard MIPS function. */ | |
1128 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
1129 | if (sym.minsym) |
1130 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1131 | else |
1132 | return is_mips_addr (memaddr); | |
1133 | } | |
1134 | ||
c906108c SS |
1135 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1136 | ||
0fe7e7c8 | 1137 | int |
4cc0665f | 1138 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1139 | { |
7cbd4a93 | 1140 | struct bound_minimal_symbol sym; |
c906108c | 1141 | |
91912e4d MR |
1142 | /* A flag indicating that this is a MIPS16 function is stored by |
1143 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1144 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1145 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
1146 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
1147 | if (sym.minsym) |
1148 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1149 | else |
1150 | return is_mips16_addr (gdbarch, memaddr); | |
1151 | } | |
1152 | ||
1153 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1154 | ||
1155 | int | |
1156 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1157 | { | |
7cbd4a93 | 1158 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1159 | |
1160 | /* A flag indicating that this is a microMIPS function is stored by | |
1161 | elfread.c in the high bit of the info field. Use this to decide | |
1162 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1163 | is set, then ELF file flags will tell if this is a microMIPS | |
1164 | function. */ | |
1165 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
1166 | if (sym.minsym) |
1167 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1168 | else |
1169 | return is_micromips_addr (gdbarch, memaddr); | |
1170 | } | |
1171 | ||
1172 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1173 | is in. */ | |
1174 | ||
1175 | static enum mips_isa | |
1176 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1177 | { | |
7cbd4a93 | 1178 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1179 | |
1180 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1181 | is stored by elfread.c in the high bit of the info field. Use | |
1182 | this to decide if the function is MIPS16 or microMIPS or normal | |
1183 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1184 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
c906108c | 1185 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 | 1186 | if (sym.minsym) |
4cc0665f | 1187 | { |
7cbd4a93 | 1188 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1189 | return ISA_MICROMIPS; |
7cbd4a93 | 1190 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1191 | return ISA_MIPS16; |
1192 | else | |
1193 | return ISA_MIPS; | |
1194 | } | |
c906108c | 1195 | else |
4cc0665f MR |
1196 | { |
1197 | if (is_mips_addr (memaddr)) | |
1198 | return ISA_MIPS; | |
1199 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1200 | return ISA_MICROMIPS; | |
1201 | else | |
1202 | return ISA_MIPS16; | |
1203 | } | |
c906108c SS |
1204 | } |
1205 | ||
14132e89 MR |
1206 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1207 | ||
1208 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1209 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1210 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1211 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1212 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1213 | ||
1214 | /* This is used as a PIC thunk prefix. */ | |
1215 | ||
1216 | static const char mips_str_pic[] = ".pic."; | |
1217 | ||
1218 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1219 | trampoline) that should be treated as a temporary frame. */ | |
1220 | ||
1221 | static int | |
1222 | mips_in_frame_stub (CORE_ADDR pc) | |
1223 | { | |
1224 | CORE_ADDR start_addr; | |
1225 | const char *name; | |
1226 | ||
1227 | /* Find the starting address of the function containing the PC. */ | |
1228 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1229 | return 0; | |
1230 | ||
1231 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
1232 | if (strncmp (name, mips_str_mips16_call_stub, | |
1233 | strlen (mips_str_mips16_call_stub)) == 0) | |
1234 | return 1; | |
1235 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
1236 | if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
1237 | return 1; | |
1238 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
1239 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) | |
1240 | return 1; | |
1241 | ||
1242 | return 0; /* Not a stub. */ | |
1243 | } | |
1244 | ||
b2fa5097 | 1245 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1246 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1247 | |
1248 | static CORE_ADDR | |
61a1198a | 1249 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1250 | { |
8376de04 | 1251 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
70242eb1 | 1252 | LONGEST pc; |
8376de04 | 1253 | |
61a1198a | 1254 | regcache_cooked_read_signed (regcache, regnum, &pc); |
4cc0665f MR |
1255 | if (is_compact_addr (pc)) |
1256 | pc = unmake_compact_addr (pc); | |
61a1198a | 1257 | return pc; |
b6cb9035 AC |
1258 | } |
1259 | ||
58dfe9ff AC |
1260 | static CORE_ADDR |
1261 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1262 | { | |
14132e89 | 1263 | CORE_ADDR pc; |
930bd0e0 | 1264 | |
8376de04 | 1265 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
4cc0665f MR |
1266 | if (is_compact_addr (pc)) |
1267 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1268 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1269 | intermediate frames. In this case we can get the caller's address | |
1270 | from $ra, or if $ra contains an address within a thunk as well, then | |
1271 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1272 | and thus the caller's address is in $s2. */ | |
1273 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1274 | { | |
1275 | pc = frame_unwind_register_signed | |
1276 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
4cc0665f MR |
1277 | if (is_compact_addr (pc)) |
1278 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1279 | if (mips_in_frame_stub (pc)) |
1280 | { | |
1281 | pc = frame_unwind_register_signed | |
1282 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
4cc0665f MR |
1283 | if (is_compact_addr (pc)) |
1284 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1285 | } |
1286 | } | |
930bd0e0 | 1287 | return pc; |
edfae063 AC |
1288 | } |
1289 | ||
30244cd8 UW |
1290 | static CORE_ADDR |
1291 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1292 | { | |
72a155b4 UW |
1293 | return frame_unwind_register_signed |
1294 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1295 | } |
1296 | ||
b8a22b94 | 1297 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1298 | dummy frame. The frame ID's base needs to match the TOS value |
1299 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1300 | breakpoint. */ | |
1301 | ||
1302 | static struct frame_id | |
b8a22b94 | 1303 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1304 | { |
f57d151a | 1305 | return frame_id_build |
b8a22b94 DJ |
1306 | (get_frame_register_signed (this_frame, |
1307 | gdbarch_num_regs (gdbarch) | |
1308 | + MIPS_SP_REGNUM), | |
1309 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1310 | } |
1311 | ||
5a439849 MR |
1312 | /* Implement the "write_pc" gdbarch method. */ |
1313 | ||
1314 | void | |
61a1198a | 1315 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1316 | { |
8376de04 MR |
1317 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1318 | ||
4cc0665f | 1319 | if (mips_pc_is_mips (pc)) |
930bd0e0 | 1320 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
4cc0665f MR |
1321 | else |
1322 | regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc)); | |
6c997a34 | 1323 | } |
c906108c | 1324 | |
4cc0665f MR |
1325 | /* Fetch and return instruction from the specified location. Handle |
1326 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1327 | |
d37cca3d | 1328 | static ULONGEST |
4cc0665f MR |
1329 | mips_fetch_instruction (struct gdbarch *gdbarch, |
1330 | enum mips_isa isa, CORE_ADDR addr, int *statusp) | |
c906108c | 1331 | { |
e17a4113 | 1332 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1333 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1334 | int instlen; |
1335 | int status; | |
1336 | ||
4cc0665f | 1337 | switch (isa) |
c906108c | 1338 | { |
4cc0665f MR |
1339 | case ISA_MICROMIPS: |
1340 | case ISA_MIPS16: | |
95ac2dcf | 1341 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1342 | addr = unmake_compact_addr (addr); |
1343 | break; | |
1344 | case ISA_MIPS: | |
1345 | instlen = MIPS_INSN32_SIZE; | |
1346 | break; | |
1347 | default: | |
1348 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1349 | break; | |
c906108c | 1350 | } |
8defab1a | 1351 | status = target_read_memory (addr, buf, instlen); |
4cc0665f MR |
1352 | if (statusp != NULL) |
1353 | *statusp = status; | |
c906108c | 1354 | if (status) |
4cc0665f MR |
1355 | { |
1356 | if (statusp == NULL) | |
1357 | memory_error (status, addr); | |
1358 | return 0; | |
1359 | } | |
e17a4113 | 1360 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1361 | } |
1362 | ||
025bb325 | 1363 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1364 | #define mips32_op(x) (x >> 26) |
1365 | #define itype_op(x) (x >> 26) | |
1366 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1367 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1368 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1369 | |
e135b889 DJ |
1370 | #define jtype_op(x) (x >> 26) |
1371 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1372 | |
e135b889 DJ |
1373 | #define rtype_op(x) (x >> 26) |
1374 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1375 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1376 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1377 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1378 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1379 | |
4cc0665f MR |
1380 | /* MicroMIPS instruction fields. */ |
1381 | #define micromips_op(x) ((x) >> 10) | |
1382 | ||
1383 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1384 | bit and the size respectively of the field extracted. */ | |
1385 | #define b0s4_imm(x) ((x) & 0xf) | |
1386 | #define b0s5_imm(x) ((x) & 0x1f) | |
1387 | #define b0s5_reg(x) ((x) & 0x1f) | |
1388 | #define b0s7_imm(x) ((x) & 0x7f) | |
1389 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1390 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1391 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1392 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1393 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1394 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1395 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1396 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1397 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1398 | ||
1399 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1400 | respectively of the field extracted. */ | |
1401 | #define b0s6_op(x) ((x) & 0x3f) | |
1402 | #define b0s11_op(x) ((x) & 0x7ff) | |
1403 | #define b0s12_imm(x) ((x) & 0xfff) | |
1404 | #define b0s16_imm(x) ((x) & 0xffff) | |
1405 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1406 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1407 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1408 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1409 | ||
1410 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1411 | instruction set. */ | |
1412 | ||
1413 | static int | |
1414 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1415 | { | |
1416 | switch (isa) | |
1417 | { | |
1418 | case ISA_MICROMIPS: | |
1419 | if (micromips_op (insn) == 0x1f) | |
1420 | return 3 * MIPS_INSN16_SIZE; | |
1421 | else if (((micromips_op (insn) & 0x4) == 0x4) | |
1422 | || ((micromips_op (insn) & 0x7) == 0x0)) | |
1423 | return 2 * MIPS_INSN16_SIZE; | |
1424 | else | |
1425 | return MIPS_INSN16_SIZE; | |
1426 | case ISA_MIPS16: | |
1427 | if ((insn & 0xf800) == 0xf000) | |
1428 | return 2 * MIPS_INSN16_SIZE; | |
1429 | else | |
1430 | return MIPS_INSN16_SIZE; | |
1431 | case ISA_MIPS: | |
1432 | return MIPS_INSN32_SIZE; | |
1433 | } | |
1434 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1435 | } | |
1436 | ||
06987e64 MK |
1437 | static LONGEST |
1438 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1439 | { |
06987e64 | 1440 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1441 | } |
1442 | ||
a385295e MR |
1443 | /* Determine the address of the next instruction executed after the INST |
1444 | floating condition branch instruction at PC. COUNT specifies the | |
1445 | number of the floating condition bits tested by the branch. */ | |
1446 | ||
1447 | static CORE_ADDR | |
1448 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1449 | ULONGEST inst, CORE_ADDR pc, int count) | |
1450 | { | |
1451 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1452 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1453 | int tf = itype_rt (inst) & 1; | |
1454 | int mask = (1 << count) - 1; | |
1455 | ULONGEST fcs; | |
1456 | int cond; | |
1457 | ||
1458 | if (fcsr == -1) | |
1459 | /* No way to handle; it'll most likely trap anyway. */ | |
1460 | return pc; | |
1461 | ||
1462 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1463 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1464 | ||
1465 | if (((cond >> cnum) & mask) != mask * !tf) | |
1466 | pc += mips32_relative_offset (inst); | |
1467 | else | |
1468 | pc += 4; | |
1469 | ||
1470 | return pc; | |
1471 | } | |
1472 | ||
f94363d7 AP |
1473 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1474 | ||
1475 | static int | |
1476 | is_octeon (struct gdbarch *gdbarch) | |
1477 | { | |
1478 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1479 | ||
1480 | return (info->mach == bfd_mach_mips_octeon | |
1481 | || info->mach == bfd_mach_mips_octeonp | |
1482 | || info->mach == bfd_mach_mips_octeon2); | |
1483 | } | |
1484 | ||
1485 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1486 | ||
1487 | static int | |
1488 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1489 | { | |
1490 | if (!is_octeon (gdbarch)) | |
1491 | return 0; | |
1492 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1493 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1494 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1495 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1496 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1497 | return 1; | |
1498 | return 0; | |
1499 | } | |
1500 | ||
1501 | ||
f49e4e6d MS |
1502 | /* Determine where to set a single step breakpoint while considering |
1503 | branch prediction. */ | |
78a59c2f | 1504 | |
5a89d8aa | 1505 | static CORE_ADDR |
0b1b3e42 | 1506 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1507 | { |
e17a4113 | 1508 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1509 | unsigned long inst; |
1510 | int op; | |
4cc0665f | 1511 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1512 | op = itype_op (inst); |
025bb325 MS |
1513 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1514 | instruction. */ | |
c5aa993b | 1515 | { |
4f5bcb50 | 1516 | if (op >> 2 == 5) |
6d82d43b | 1517 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1518 | { |
4f5bcb50 | 1519 | switch (op & 0x03) |
c906108c | 1520 | { |
e135b889 DJ |
1521 | case 0: /* BEQL */ |
1522 | goto equal_branch; | |
1523 | case 1: /* BNEL */ | |
1524 | goto neq_branch; | |
1525 | case 2: /* BLEZL */ | |
1526 | goto less_branch; | |
313628cc | 1527 | case 3: /* BGTZL */ |
e135b889 | 1528 | goto greater_branch; |
c5aa993b JM |
1529 | default: |
1530 | pc += 4; | |
c906108c SS |
1531 | } |
1532 | } | |
4f5bcb50 | 1533 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1534 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e | 1535 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
4f5bcb50 | 1536 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1537 | && (itype_rt (inst) & 2) == 0) |
1538 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1539 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
4f5bcb50 | 1540 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1541 | && (itype_rt (inst) & 2) == 0) |
1542 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1543 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
4f5bcb50 | 1544 | else if (op == 29) |
9e8da49c MR |
1545 | /* JALX: 011101 */ |
1546 | /* The new PC will be alternate mode. */ | |
1547 | { | |
1548 | unsigned long reg; | |
1549 | ||
1550 | reg = jtype_target (inst) << 2; | |
1551 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1552 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1553 | } | |
f94363d7 AP |
1554 | else if (is_octeon_bbit_op (op, gdbarch)) |
1555 | { | |
1556 | int bit, branch_if; | |
1557 | ||
1558 | branch_if = op == 58 || op == 62; | |
1559 | bit = itype_rt (inst); | |
1560 | ||
1561 | /* Take into account the *32 instructions. */ | |
1562 | if (op == 54 || op == 62) | |
1563 | bit += 32; | |
1564 | ||
1565 | if (((get_frame_register_signed (frame, | |
1566 | itype_rs (inst)) >> bit) & 1) | |
1567 | == branch_if) | |
1568 | pc += mips32_relative_offset (inst) + 4; | |
1569 | else | |
1570 | pc += 8; /* After the delay slot. */ | |
1571 | } | |
1572 | ||
c5aa993b | 1573 | else |
025bb325 | 1574 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1575 | } |
1576 | else | |
025bb325 | 1577 | { /* This gets way messy. */ |
c5aa993b | 1578 | |
025bb325 | 1579 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1580 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1581 | { |
c5aa993b JM |
1582 | case 0: /* SPECIAL */ |
1583 | op = rtype_funct (inst); | |
1584 | switch (op) | |
1585 | { | |
1586 | case 8: /* JR */ | |
1587 | case 9: /* JALR */ | |
025bb325 | 1588 | /* Set PC to that address. */ |
0b1b3e42 | 1589 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1590 | break; |
e38d4e1a DJ |
1591 | case 12: /* SYSCALL */ |
1592 | { | |
1593 | struct gdbarch_tdep *tdep; | |
1594 | ||
1595 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1596 | if (tdep->syscall_next_pc != NULL) | |
1597 | pc = tdep->syscall_next_pc (frame); | |
1598 | else | |
1599 | pc += 4; | |
1600 | } | |
1601 | break; | |
c5aa993b JM |
1602 | default: |
1603 | pc += 4; | |
1604 | } | |
1605 | ||
6d82d43b | 1606 | break; /* end SPECIAL */ |
025bb325 | 1607 | case 1: /* REGIMM */ |
c906108c | 1608 | { |
e135b889 DJ |
1609 | op = itype_rt (inst); /* branch condition */ |
1610 | switch (op) | |
c906108c | 1611 | { |
c5aa993b | 1612 | case 0: /* BLTZ */ |
e135b889 DJ |
1613 | case 2: /* BLTZL */ |
1614 | case 16: /* BLTZAL */ | |
c5aa993b | 1615 | case 18: /* BLTZALL */ |
c906108c | 1616 | less_branch: |
0b1b3e42 | 1617 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1618 | pc += mips32_relative_offset (inst) + 4; |
1619 | else | |
1620 | pc += 8; /* after the delay slot */ | |
1621 | break; | |
e135b889 | 1622 | case 1: /* BGEZ */ |
c5aa993b JM |
1623 | case 3: /* BGEZL */ |
1624 | case 17: /* BGEZAL */ | |
1625 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1626 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1627 | pc += mips32_relative_offset (inst) + 4; |
1628 | else | |
1629 | pc += 8; /* after the delay slot */ | |
1630 | break; | |
a385295e MR |
1631 | case 0x1c: /* BPOSGE32 */ |
1632 | case 0x1e: /* BPOSGE64 */ | |
1633 | pc += 4; | |
1634 | if (itype_rs (inst) == 0) | |
1635 | { | |
1636 | unsigned int pos = (op & 2) ? 64 : 32; | |
1637 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1638 | ||
1639 | if (dspctl == -1) | |
1640 | /* No way to handle; it'll most likely trap anyway. */ | |
1641 | break; | |
1642 | ||
1643 | if ((get_frame_register_unsigned (frame, | |
1644 | dspctl) & 0x7f) >= pos) | |
1645 | pc += mips32_relative_offset (inst); | |
1646 | else | |
1647 | pc += 4; | |
1648 | } | |
1649 | break; | |
e135b889 | 1650 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1651 | default: |
1652 | pc += 4; | |
c906108c SS |
1653 | } |
1654 | } | |
6d82d43b | 1655 | break; /* end REGIMM */ |
c5aa993b JM |
1656 | case 2: /* J */ |
1657 | case 3: /* JAL */ | |
1658 | { | |
1659 | unsigned long reg; | |
1660 | reg = jtype_target (inst) << 2; | |
025bb325 | 1661 | /* Upper four bits get never changed... */ |
5b652102 | 1662 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1663 | } |
c5aa993b | 1664 | break; |
e135b889 | 1665 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1666 | equal_branch: |
0b1b3e42 UW |
1667 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1668 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1669 | pc += mips32_relative_offset (inst) + 4; |
1670 | else | |
1671 | pc += 8; | |
1672 | break; | |
e135b889 | 1673 | case 5: /* BNE, BNEL */ |
c5aa993b | 1674 | neq_branch: |
0b1b3e42 UW |
1675 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1676 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1677 | pc += mips32_relative_offset (inst) + 4; |
1678 | else | |
1679 | pc += 8; | |
1680 | break; | |
e135b889 | 1681 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1682 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1683 | pc += mips32_relative_offset (inst) + 4; |
1684 | else | |
1685 | pc += 8; | |
1686 | break; | |
1687 | case 7: | |
e135b889 DJ |
1688 | default: |
1689 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1690 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1691 | pc += mips32_relative_offset (inst) + 4; |
1692 | else | |
1693 | pc += 8; | |
1694 | break; | |
c5aa993b JM |
1695 | } /* switch */ |
1696 | } /* else */ | |
1697 | return pc; | |
1698 | } /* mips32_next_pc */ | |
c906108c | 1699 | |
4cc0665f MR |
1700 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1701 | INSN. */ | |
1702 | ||
1703 | static LONGEST | |
1704 | micromips_relative_offset7 (ULONGEST insn) | |
1705 | { | |
1706 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1707 | } | |
1708 | ||
1709 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1710 | INSN. */ | |
1711 | ||
1712 | static LONGEST | |
1713 | micromips_relative_offset10 (ULONGEST insn) | |
1714 | { | |
1715 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1716 | } | |
1717 | ||
1718 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1719 | INSN. */ | |
1720 | ||
1721 | static LONGEST | |
1722 | micromips_relative_offset16 (ULONGEST insn) | |
1723 | { | |
1724 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1725 | } | |
1726 | ||
1727 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1728 | ||
1729 | static int | |
1730 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1731 | { | |
1732 | ULONGEST insn; | |
1733 | ||
1734 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1735 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1736 | } | |
1737 | ||
1738 | /* Calculate the address of the next microMIPS instruction to execute | |
1739 | after the INSN coprocessor 1 conditional branch instruction at the | |
1740 | address PC. COUNT denotes the number of coprocessor condition bits | |
1741 | examined by the branch. */ | |
1742 | ||
1743 | static CORE_ADDR | |
1744 | micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1745 | ULONGEST insn, CORE_ADDR pc, int count) | |
1746 | { | |
1747 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1748 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1749 | int tf = b5s5_op (insn >> 16) & 1; | |
1750 | int mask = (1 << count) - 1; | |
1751 | ULONGEST fcs; | |
1752 | int cond; | |
1753 | ||
1754 | if (fcsr == -1) | |
1755 | /* No way to handle; it'll most likely trap anyway. */ | |
1756 | return pc; | |
1757 | ||
1758 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1759 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1760 | ||
1761 | if (((cond >> cnum) & mask) != mask * !tf) | |
1762 | pc += micromips_relative_offset16 (insn); | |
1763 | else | |
1764 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1765 | ||
1766 | return pc; | |
1767 | } | |
1768 | ||
1769 | /* Calculate the address of the next microMIPS instruction to execute | |
1770 | after the instruction at the address PC. */ | |
1771 | ||
1772 | static CORE_ADDR | |
1773 | micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
1774 | { | |
1775 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1776 | ULONGEST insn; | |
1777 | ||
1778 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1779 | pc += MIPS_INSN16_SIZE; | |
1780 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1781 | { | |
1782 | /* 48-bit instructions. */ | |
1783 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
1784 | /* No branch or jump instructions in this category. */ | |
1785 | pc += 2 * MIPS_INSN16_SIZE; | |
1786 | break; | |
1787 | ||
1788 | /* 32-bit instructions. */ | |
1789 | case 2 * MIPS_INSN16_SIZE: | |
1790 | insn <<= 16; | |
1791 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1792 | pc += MIPS_INSN16_SIZE; | |
1793 | switch (micromips_op (insn >> 16)) | |
1794 | { | |
1795 | case 0x00: /* POOL32A: bits 000000 */ | |
1796 | if (b0s6_op (insn) == 0x3c | |
1797 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1798 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1799 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1800 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
1801 | pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); | |
1802 | break; | |
1803 | ||
1804 | case 0x10: /* POOL32I: bits 010000 */ | |
1805 | switch (b5s5_op (insn >> 16)) | |
1806 | { | |
1807 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1808 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1809 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
1810 | if (get_frame_register_signed (frame, | |
1811 | b0s5_reg (insn >> 16)) < 0) | |
1812 | pc += micromips_relative_offset16 (insn); | |
1813 | else | |
1814 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1815 | break; | |
1816 | ||
1817 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1818 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1819 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
1820 | if (get_frame_register_signed (frame, | |
1821 | b0s5_reg (insn >> 16)) >= 0) | |
1822 | pc += micromips_relative_offset16 (insn); | |
1823 | else | |
1824 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1825 | break; | |
1826 | ||
1827 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
1828 | if (get_frame_register_signed (frame, | |
1829 | b0s5_reg (insn >> 16)) <= 0) | |
1830 | pc += micromips_relative_offset16 (insn); | |
1831 | else | |
1832 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1833 | break; | |
1834 | ||
1835 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
1836 | if (get_frame_register_signed (frame, | |
1837 | b0s5_reg (insn >> 16)) != 0) | |
1838 | pc += micromips_relative_offset16 (insn); | |
1839 | break; | |
1840 | ||
1841 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
1842 | if (get_frame_register_signed (frame, | |
1843 | b0s5_reg (insn >> 16)) > 0) | |
1844 | pc += micromips_relative_offset16 (insn); | |
1845 | else | |
1846 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1847 | break; | |
1848 | ||
1849 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
1850 | if (get_frame_register_signed (frame, | |
1851 | b0s5_reg (insn >> 16)) == 0) | |
1852 | pc += micromips_relative_offset16 (insn); | |
1853 | break; | |
1854 | ||
1855 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1856 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1857 | if (((insn >> 16) & 0x3) == 0x0) | |
1858 | /* BC2F, BC2T: don't know how to handle these. */ | |
1859 | break; | |
1860 | break; | |
1861 | ||
1862 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1863 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1864 | { | |
1865 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1866 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1867 | ||
1868 | if (dspctl == -1) | |
1869 | /* No way to handle; it'll most likely trap anyway. */ | |
1870 | break; | |
1871 | ||
1872 | if ((get_frame_register_unsigned (frame, | |
1873 | dspctl) & 0x7f) >= pos) | |
1874 | pc += micromips_relative_offset16 (insn); | |
1875 | else | |
1876 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1877 | } | |
1878 | break; | |
1879 | ||
1880 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1881 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1882 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1883 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1884 | if (((insn >> 16) & 0x2) == 0x0) | |
1885 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, | |
1886 | ((insn >> 16) & 0x1) + 1); | |
1887 | break; | |
1888 | ||
1889 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1890 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1891 | if (((insn >> 16) & 0x3) == 0x1) | |
1892 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); | |
1893 | break; | |
1894 | } | |
1895 | break; | |
1896 | ||
1897 | case 0x1d: /* JALS: bits 011101 */ | |
1898 | case 0x35: /* J: bits 110101 */ | |
1899 | case 0x3d: /* JAL: bits 111101 */ | |
1900 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1901 | break; | |
1902 | ||
1903 | case 0x25: /* BEQ: bits 100101 */ | |
1904 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1905 | == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1906 | pc += micromips_relative_offset16 (insn); | |
1907 | else | |
1908 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1909 | break; | |
1910 | ||
1911 | case 0x2d: /* BNE: bits 101101 */ | |
1912 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1913 | != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1914 | pc += micromips_relative_offset16 (insn); | |
1915 | else | |
1916 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1917 | break; | |
1918 | ||
1919 | case 0x3c: /* JALX: bits 111100 */ | |
1920 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
1921 | break; | |
1922 | } | |
1923 | break; | |
1924 | ||
1925 | /* 16-bit instructions. */ | |
1926 | case MIPS_INSN16_SIZE: | |
1927 | switch (micromips_op (insn)) | |
1928 | { | |
1929 | case 0x11: /* POOL16C: bits 010001 */ | |
1930 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
1931 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
1932 | pc = get_frame_register_signed (frame, b0s5_reg (insn)); | |
1933 | else if (b5s5_op (insn) == 0x18) | |
1934 | /* JRADDIUSP: bits 010001 11000 */ | |
1935 | pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); | |
1936 | break; | |
1937 | ||
1938 | case 0x23: /* BEQZ16: bits 100011 */ | |
1939 | { | |
1940 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1941 | ||
1942 | if (get_frame_register_signed (frame, rs) == 0) | |
1943 | pc += micromips_relative_offset7 (insn); | |
1944 | else | |
1945 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1946 | } | |
1947 | break; | |
1948 | ||
1949 | case 0x2b: /* BNEZ16: bits 101011 */ | |
1950 | { | |
1951 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1952 | ||
1953 | if (get_frame_register_signed (frame, rs) != 0) | |
1954 | pc += micromips_relative_offset7 (insn); | |
1955 | else | |
1956 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1957 | } | |
1958 | break; | |
1959 | ||
1960 | case 0x33: /* B16: bits 110011 */ | |
1961 | pc += micromips_relative_offset10 (insn); | |
1962 | break; | |
1963 | } | |
1964 | break; | |
1965 | } | |
1966 | ||
1967 | return pc; | |
1968 | } | |
1969 | ||
c906108c | 1970 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
1971 | mips 16 variant, but fortunately, there fewer instructions. We have |
1972 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1973 | 32 bit instructions. We dont want to set a single step instruction | |
1974 | on the extend instruction either. */ | |
c906108c SS |
1975 | |
1976 | /* Lots of mips16 instruction formats */ | |
1977 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1978 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1979 | enum mips16_inst_fmts |
1980 | { | |
c5aa993b JM |
1981 | itype, /* 0 immediate 5,10 */ |
1982 | ritype, /* 1 5,3,8 */ | |
1983 | rrtype, /* 2 5,3,3,5 */ | |
1984 | rritype, /* 3 5,3,3,5 */ | |
1985 | rrrtype, /* 4 5,3,3,3,2 */ | |
1986 | rriatype, /* 5 5,3,3,1,4 */ | |
1987 | shifttype, /* 6 5,3,3,3,2 */ | |
1988 | i8type, /* 7 5,3,8 */ | |
1989 | i8movtype, /* 8 5,3,3,5 */ | |
1990 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1991 | i64type, /* 10 5,3,8 */ | |
1992 | ri64type, /* 11 5,3,3,5 */ | |
1993 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1994 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1995 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1996 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1997 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1998 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1999 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2000 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2001 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2002 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2003 | }; | |
12f02c2a | 2004 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2005 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2006 | struct upk_mips16 |
6d82d43b AC |
2007 | { |
2008 | CORE_ADDR offset; | |
025bb325 | 2009 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2010 | unsigned int regy; |
2011 | }; | |
c906108c SS |
2012 | |
2013 | ||
12f02c2a | 2014 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2015 | for the bits which make up the immediate extension. */ |
c906108c | 2016 | |
12f02c2a AC |
2017 | static CORE_ADDR |
2018 | extended_offset (unsigned int extension) | |
c906108c | 2019 | { |
12f02c2a | 2020 | CORE_ADDR value; |
130854df | 2021 | |
4c2051c6 | 2022 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2023 | value = value << 6; |
4c2051c6 | 2024 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2025 | value = value << 5; |
130854df MR |
2026 | value |= extension & 0x1f; /* Extract 4:0. */ |
2027 | ||
c5aa993b | 2028 | return value; |
c906108c SS |
2029 | } |
2030 | ||
2031 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2032 | instruction. It won't malfunction, but why make excess remote memory |
2033 | references? If the immediate operands get sign extended or something, | |
2034 | do it after the extension is performed. */ | |
c906108c | 2035 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2036 | when the offset is to be used in relative addressing. */ |
c906108c | 2037 | |
12f02c2a | 2038 | static unsigned int |
e17a4113 | 2039 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2040 | { |
e17a4113 | 2041 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2042 | gdb_byte buf[8]; |
a2fb2cee MR |
2043 | |
2044 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2045 | target_read_memory (pc, buf, 2); |
e17a4113 | 2046 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2047 | } |
2048 | ||
2049 | static void | |
e17a4113 | 2050 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2051 | unsigned int extension, |
2052 | unsigned int inst, | |
6d82d43b | 2053 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2054 | { |
12f02c2a AC |
2055 | CORE_ADDR offset; |
2056 | int regx; | |
2057 | int regy; | |
2058 | switch (insn_format) | |
c906108c | 2059 | { |
c5aa993b | 2060 | case itype: |
c906108c | 2061 | { |
12f02c2a AC |
2062 | CORE_ADDR value; |
2063 | if (extension) | |
c5aa993b | 2064 | { |
4c2051c6 MR |
2065 | value = extended_offset ((extension << 16) | inst); |
2066 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2067 | } |
2068 | else | |
c5aa993b | 2069 | { |
12f02c2a | 2070 | value = inst & 0x7ff; |
4c2051c6 | 2071 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2072 | } |
12f02c2a AC |
2073 | offset = value; |
2074 | regx = -1; | |
2075 | regy = -1; | |
c906108c | 2076 | } |
c5aa993b JM |
2077 | break; |
2078 | case ritype: | |
2079 | case i8type: | |
025bb325 | 2080 | { /* A register identifier and an offset. */ |
c906108c | 2081 | /* Most of the fields are the same as I type but the |
025bb325 | 2082 | immediate value is of a different length. */ |
12f02c2a AC |
2083 | CORE_ADDR value; |
2084 | if (extension) | |
c906108c | 2085 | { |
4c2051c6 MR |
2086 | value = extended_offset ((extension << 16) | inst); |
2087 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2088 | } |
c5aa993b JM |
2089 | else |
2090 | { | |
4c2051c6 MR |
2091 | value = inst & 0xff; /* 8 bits */ |
2092 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2093 | } |
12f02c2a | 2094 | offset = value; |
4c2051c6 | 2095 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2096 | regy = -1; |
c5aa993b | 2097 | break; |
c906108c | 2098 | } |
c5aa993b | 2099 | case jalxtype: |
c906108c | 2100 | { |
c5aa993b | 2101 | unsigned long value; |
12f02c2a AC |
2102 | unsigned int nexthalf; |
2103 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2104 | value = value << 16; |
4cc0665f MR |
2105 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2106 | /* Low bit still set. */ | |
c5aa993b | 2107 | value |= nexthalf; |
12f02c2a AC |
2108 | offset = value; |
2109 | regx = -1; | |
2110 | regy = -1; | |
c5aa993b | 2111 | break; |
c906108c SS |
2112 | } |
2113 | default: | |
e2e0b3e5 | 2114 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2115 | } |
12f02c2a AC |
2116 | upk->offset = offset; |
2117 | upk->regx = regx; | |
2118 | upk->regy = regy; | |
c906108c SS |
2119 | } |
2120 | ||
2121 | ||
c5aa993b JM |
2122 | static CORE_ADDR |
2123 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2124 | { |
5b652102 | 2125 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
2126 | } |
2127 | ||
12f02c2a | 2128 | static CORE_ADDR |
0b1b3e42 | 2129 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 2130 | unsigned int extension, unsigned int insn) |
c906108c | 2131 | { |
e17a4113 | 2132 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
2133 | int op = (insn >> 11); |
2134 | switch (op) | |
c906108c | 2135 | { |
6d82d43b | 2136 | case 2: /* Branch */ |
12f02c2a | 2137 | { |
12f02c2a | 2138 | struct upk_mips16 upk; |
e17a4113 | 2139 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 2140 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
2141 | break; |
2142 | } | |
025bb325 MS |
2143 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2144 | instructions. */ | |
12f02c2a AC |
2145 | { |
2146 | struct upk_mips16 upk; | |
e17a4113 | 2147 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
2148 | pc = add_offset_16 (pc, upk.offset); |
2149 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 2150 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2151 | else |
2152 | pc |= 0x01; | |
2153 | break; | |
2154 | } | |
6d82d43b | 2155 | case 4: /* beqz */ |
12f02c2a AC |
2156 | { |
2157 | struct upk_mips16 upk; | |
2158 | int reg; | |
e17a4113 | 2159 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2160 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2161 | if (reg == 0) |
2162 | pc += (upk.offset << 1) + 2; | |
2163 | else | |
2164 | pc += 2; | |
2165 | break; | |
2166 | } | |
6d82d43b | 2167 | case 5: /* bnez */ |
12f02c2a AC |
2168 | { |
2169 | struct upk_mips16 upk; | |
2170 | int reg; | |
e17a4113 | 2171 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2172 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2173 | if (reg != 0) |
2174 | pc += (upk.offset << 1) + 2; | |
2175 | else | |
2176 | pc += 2; | |
2177 | break; | |
2178 | } | |
6d82d43b | 2179 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2180 | { |
2181 | struct upk_mips16 upk; | |
2182 | int reg; | |
e17a4113 | 2183 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2184 | /* upk.regx contains the opcode */ |
0b1b3e42 | 2185 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
2186 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2187 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
2188 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
2189 | pc += (upk.offset << 1) + 2; | |
2190 | else | |
2191 | pc += 2; | |
2192 | break; | |
2193 | } | |
6d82d43b | 2194 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2195 | { |
2196 | struct upk_mips16 upk; | |
2197 | /* upk.fmt = rrtype; */ | |
2198 | op = insn & 0x1f; | |
2199 | if (op == 0) | |
c5aa993b | 2200 | { |
12f02c2a AC |
2201 | int reg; |
2202 | upk.regx = (insn >> 8) & 0x07; | |
2203 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2204 | if ((upk.regy & 1) == 0) |
4cc0665f | 2205 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2206 | else |
2207 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 2208 | pc = get_frame_register_signed (frame, reg); |
c906108c | 2209 | } |
12f02c2a | 2210 | else |
c5aa993b | 2211 | pc += 2; |
12f02c2a AC |
2212 | break; |
2213 | } | |
2214 | case 30: | |
2215 | /* This is an instruction extension. Fetch the real instruction | |
2216 | (which follows the extension) and decode things based on | |
025bb325 | 2217 | that. */ |
12f02c2a AC |
2218 | { |
2219 | pc += 2; | |
e17a4113 UW |
2220 | pc = extended_mips16_next_pc (frame, pc, insn, |
2221 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
2222 | break; |
2223 | } | |
2224 | default: | |
2225 | { | |
2226 | pc += 2; | |
2227 | break; | |
2228 | } | |
c906108c | 2229 | } |
c5aa993b | 2230 | return pc; |
12f02c2a | 2231 | } |
c906108c | 2232 | |
5a89d8aa | 2233 | static CORE_ADDR |
0b1b3e42 | 2234 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 2235 | { |
e17a4113 UW |
2236 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2237 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 2238 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
2239 | } |
2240 | ||
2241 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2242 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2243 | It works by decoding the current instruction and predicting where a |
1aee363c | 2244 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2245 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2246 | static CORE_ADDR |
0b1b3e42 | 2247 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2248 | { |
4cc0665f MR |
2249 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2250 | ||
2251 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
0b1b3e42 | 2252 | return mips16_next_pc (frame, pc); |
4cc0665f MR |
2253 | else if (mips_pc_is_micromips (gdbarch, pc)) |
2254 | return micromips_next_pc (frame, pc); | |
c5aa993b | 2255 | else |
0b1b3e42 | 2256 | return mips32_next_pc (frame, pc); |
12f02c2a | 2257 | } |
c906108c | 2258 | |
edfae063 AC |
2259 | struct mips_frame_cache |
2260 | { | |
2261 | CORE_ADDR base; | |
2262 | struct trad_frame_saved_reg *saved_regs; | |
2263 | }; | |
2264 | ||
29639122 JB |
2265 | /* Set a register's saved stack address in temp_saved_regs. If an |
2266 | address has already been set for this register, do nothing; this | |
2267 | way we will only recognize the first save of a given register in a | |
2268 | function prologue. | |
eec63939 | 2269 | |
f57d151a UW |
2270 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2271 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2272 | Strictly speaking, only the second range is used as it is only second | |
2273 | range (the ABI instead of ISA registers) that comes into play when finding | |
2274 | saved registers in a frame. */ | |
eec63939 AC |
2275 | |
2276 | static void | |
74ed0bb4 MD |
2277 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2278 | int regnum, CORE_ADDR offset) | |
eec63939 | 2279 | { |
29639122 JB |
2280 | if (this_cache != NULL |
2281 | && this_cache->saved_regs[regnum].addr == -1) | |
2282 | { | |
74ed0bb4 MD |
2283 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2284 | = offset; | |
2285 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2286 | = offset; | |
29639122 | 2287 | } |
eec63939 AC |
2288 | } |
2289 | ||
eec63939 | 2290 | |
29639122 JB |
2291 | /* Fetch the immediate value from a MIPS16 instruction. |
2292 | If the previous instruction was an EXTEND, use it to extend | |
2293 | the upper bits of the immediate value. This is a helper function | |
2294 | for mips16_scan_prologue. */ | |
eec63939 | 2295 | |
29639122 JB |
2296 | static int |
2297 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2298 | unsigned short inst, /* current instruction */ | |
2299 | int nbits, /* number of bits in imm field */ | |
2300 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2301 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2302 | { |
29639122 | 2303 | int offset; |
eec63939 | 2304 | |
29639122 JB |
2305 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2306 | { | |
2307 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2308 | if (offset & 0x8000) /* check for negative extend */ | |
2309 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2310 | return offset | (inst & 0x1f); | |
2311 | } | |
eec63939 | 2312 | else |
29639122 JB |
2313 | { |
2314 | int max_imm = 1 << nbits; | |
2315 | int mask = max_imm - 1; | |
2316 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2317 | |
29639122 JB |
2318 | offset = inst & mask; |
2319 | if (is_signed && (offset & sign_bit)) | |
2320 | offset = 0 - (max_imm - offset); | |
2321 | return offset * scale; | |
2322 | } | |
2323 | } | |
eec63939 | 2324 | |
65596487 | 2325 | |
29639122 JB |
2326 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2327 | the associated FRAME_CACHE if not null. | |
2328 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2329 | |
29639122 | 2330 | static CORE_ADDR |
e17a4113 UW |
2331 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2332 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2333 | struct frame_info *this_frame, |
29639122 JB |
2334 | struct mips_frame_cache *this_cache) |
2335 | { | |
2336 | CORE_ADDR cur_pc; | |
025bb325 | 2337 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2338 | CORE_ADDR sp; |
2339 | long frame_offset = 0; /* Size of stack frame. */ | |
2340 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2341 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2342 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2343 | unsigned inst = 0; /* current instruction */ |
2344 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2345 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 2346 | int reg, offset; |
a343eb3c | 2347 | |
29639122 JB |
2348 | int extend_bytes = 0; |
2349 | int prev_extend_bytes; | |
2350 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 2351 | |
29639122 | 2352 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2353 | THIS_FRAME. */ |
2354 | if (this_frame != NULL) | |
2355 | sp = get_frame_register_signed (this_frame, | |
2356 | gdbarch_num_regs (gdbarch) | |
2357 | + MIPS_SP_REGNUM); | |
29639122 JB |
2358 | else |
2359 | sp = 0; | |
eec63939 | 2360 | |
29639122 JB |
2361 | if (limit_pc > start_pc + 200) |
2362 | limit_pc = start_pc + 200; | |
eec63939 | 2363 | |
95ac2dcf | 2364 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
2365 | { |
2366 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2367 | the immediate offset extension from it in mips16_get_imm. */ | |
2368 | prev_inst = inst; | |
eec63939 | 2369 | |
025bb325 | 2370 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2371 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2372 | cur_pc, NULL); | |
eec63939 | 2373 | |
29639122 JB |
2374 | /* Normally we ignore extend instructions. However, if it is |
2375 | not followed by a valid prologue instruction, then this | |
2376 | instruction is not part of the prologue either. We must | |
2377 | remember in this case to adjust the end_prologue_addr back | |
2378 | over the extend. */ | |
2379 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2380 | { | |
95ac2dcf | 2381 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2382 | continue; |
2383 | } | |
eec63939 | 2384 | |
29639122 JB |
2385 | prev_extend_bytes = extend_bytes; |
2386 | extend_bytes = 0; | |
eec63939 | 2387 | |
29639122 JB |
2388 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2389 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2390 | { | |
2391 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2392 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2393 | frame_offset -= offset; |
2394 | else | |
2395 | /* Exit loop if a positive stack adjustment is found, which | |
2396 | usually means that the stack cleanup code in the function | |
2397 | epilogue is reached. */ | |
2398 | break; | |
2399 | } | |
2400 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2401 | { | |
2402 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2403 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2404 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2405 | } |
2406 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2407 | { | |
2408 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2409 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2410 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2411 | } |
2412 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2413 | { | |
2414 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2415 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2416 | } |
2417 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2418 | { | |
2419 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2420 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2421 | } |
2422 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2423 | { | |
2424 | frame_addr = sp; | |
2425 | frame_reg = 17; | |
2426 | } | |
2427 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2428 | { | |
2429 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2430 | frame_addr = sp + offset; | |
2431 | frame_reg = 17; | |
2432 | frame_adjust = offset; | |
2433 | } | |
2434 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2435 | { | |
2436 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2437 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2438 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2439 | } |
2440 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2441 | { | |
2442 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2443 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2444 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2445 | } |
2446 | else if ((inst & 0xf81f) == 0xe809 | |
2447 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2448 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2449 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2450 | { | |
025bb325 | 2451 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2452 | if (prev_extend_bytes) /* extend */ |
2453 | save_inst |= prev_inst << 16; | |
2454 | } | |
29639122 | 2455 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 2456 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
2457 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2458 | { | |
2459 | /* This instruction is part of the prologue, but we don't | |
2460 | need to do anything special to handle it. */ | |
2461 | } | |
2462 | else | |
2463 | { | |
2464 | /* This instruction is not an instruction typically found | |
2465 | in a prologue, so we must have reached the end of the | |
2466 | prologue. */ | |
2467 | if (end_prologue_addr == 0) | |
2468 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
2469 | } | |
2470 | } | |
eec63939 | 2471 | |
29639122 JB |
2472 | /* The entry instruction is typically the first instruction in a function, |
2473 | and it stores registers at offsets relative to the value of the old SP | |
2474 | (before the prologue). But the value of the sp parameter to this | |
2475 | function is the new SP (after the prologue has been executed). So we | |
2476 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2477 | and can calculate what the old SP must have been. */ |
29639122 JB |
2478 | if (entry_inst != 0) |
2479 | { | |
2480 | int areg_count = (entry_inst >> 8) & 7; | |
2481 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2482 | |
29639122 JB |
2483 | /* The entry instruction always subtracts 32 from the SP. */ |
2484 | frame_offset += 32; | |
2485 | ||
2486 | /* Now we can calculate what the SP must have been at the | |
2487 | start of the function prologue. */ | |
2488 | sp += frame_offset; | |
2489 | ||
2490 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2491 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2492 | { | |
74ed0bb4 | 2493 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2494 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2495 | } |
2496 | ||
2497 | /* Check if the ra register was pushed on the stack. */ | |
2498 | offset = -4; | |
2499 | if (entry_inst & 0x20) | |
2500 | { | |
74ed0bb4 | 2501 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2502 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2503 | } |
2504 | ||
2505 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2506 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2507 | { | |
74ed0bb4 | 2508 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2509 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2510 | } |
2511 | } | |
2512 | ||
2207132d MR |
2513 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2514 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2515 | size of the frame is specified as an immediate field of instruction | |
2516 | and an extended variation exists which lets additional registers and | |
2517 | frame space to be specified. The instruction always treats registers | |
2518 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2519 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2520 | { | |
2521 | static int args_table[16] = { | |
2522 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2523 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2524 | }; | |
2525 | static int astatic_table[16] = { | |
2526 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2527 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2528 | }; | |
2529 | int aregs = (save_inst >> 16) & 0xf; | |
2530 | int xsregs = (save_inst >> 24) & 0x7; | |
2531 | int args = args_table[aregs]; | |
2532 | int astatic = astatic_table[aregs]; | |
2533 | long frame_size; | |
2534 | ||
2535 | if (args < 0) | |
2536 | { | |
2537 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2538 | args = 0; | |
2539 | } | |
2540 | if (astatic < 0) | |
2541 | { | |
2542 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2543 | astatic = 0; | |
2544 | } | |
2545 | ||
2546 | /* For standard SAVE the frame size of 0 means 128. */ | |
2547 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2548 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2549 | frame_size = 16; | |
2550 | frame_size *= 8; | |
2551 | frame_offset += frame_size; | |
2552 | ||
2553 | /* Now we can calculate what the SP must have been at the | |
2554 | start of the function prologue. */ | |
2555 | sp += frame_offset; | |
2556 | ||
2557 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2558 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2559 | { | |
74ed0bb4 | 2560 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2561 | offset += mips_abi_regsize (gdbarch); |
2562 | } | |
2563 | ||
2564 | offset = -4; | |
2565 | ||
2566 | /* Check if the RA register was pushed on the stack. */ | |
2567 | if (save_inst & 0x40) | |
2568 | { | |
74ed0bb4 | 2569 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2570 | offset -= mips_abi_regsize (gdbarch); |
2571 | } | |
2572 | ||
2573 | /* Check if the S8 register was pushed on the stack. */ | |
2574 | if (xsregs > 6) | |
2575 | { | |
74ed0bb4 | 2576 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2577 | offset -= mips_abi_regsize (gdbarch); |
2578 | xsregs--; | |
2579 | } | |
2580 | /* Check if S2-S7 were pushed on the stack. */ | |
2581 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2582 | { | |
74ed0bb4 | 2583 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2584 | offset -= mips_abi_regsize (gdbarch); |
2585 | } | |
2586 | ||
2587 | /* Check if the S1 register was pushed on the stack. */ | |
2588 | if (save_inst & 0x10) | |
2589 | { | |
74ed0bb4 | 2590 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2591 | offset -= mips_abi_regsize (gdbarch); |
2592 | } | |
2593 | /* Check if the S0 register was pushed on the stack. */ | |
2594 | if (save_inst & 0x20) | |
2595 | { | |
74ed0bb4 | 2596 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2597 | offset -= mips_abi_regsize (gdbarch); |
2598 | } | |
2599 | ||
4cc0665f MR |
2600 | /* Check if A0-A3 were pushed on the stack. */ |
2601 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2602 | { | |
2603 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2604 | offset -= mips_abi_regsize (gdbarch); | |
2605 | } | |
2606 | } | |
2607 | ||
2608 | if (this_cache != NULL) | |
2609 | { | |
2610 | this_cache->base = | |
2611 | (get_frame_register_signed (this_frame, | |
2612 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2613 | + frame_offset - frame_adjust); | |
2614 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2615 | be able to get rid of the assignment below, evetually. But it's | |
2616 | still needed for now. */ | |
2617 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2618 | + mips_regnum (gdbarch)->pc] | |
2619 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2620 | } | |
2621 | ||
2622 | /* If we didn't reach the end of the prologue when scanning the function | |
2623 | instructions, then set end_prologue_addr to the address of the | |
2624 | instruction immediately after the last one we scanned. */ | |
2625 | if (end_prologue_addr == 0) | |
2626 | end_prologue_addr = cur_pc; | |
2627 | ||
2628 | return end_prologue_addr; | |
2629 | } | |
2630 | ||
2631 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2632 | Procedures that use the 32-bit instruction set are handled by the | |
2633 | mips_insn32 unwinder. */ | |
2634 | ||
2635 | static struct mips_frame_cache * | |
2636 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2637 | { | |
2638 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2639 | struct mips_frame_cache *cache; | |
2640 | ||
2641 | if ((*this_cache) != NULL) | |
2642 | return (*this_cache); | |
2643 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2644 | (*this_cache) = cache; | |
2645 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2646 | ||
2647 | /* Analyze the function prologue. */ | |
2648 | { | |
2649 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2650 | CORE_ADDR start_addr; | |
2651 | ||
2652 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2653 | if (start_addr == 0) | |
2654 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2655 | /* We can't analyze the prologue if we couldn't find the begining | |
2656 | of the function. */ | |
2657 | if (start_addr == 0) | |
2658 | return cache; | |
2659 | ||
2660 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); | |
2661 | } | |
2662 | ||
2663 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2664 | trad_frame_set_value (cache->saved_regs, | |
2665 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2666 | cache->base); | |
2667 | ||
2668 | return (*this_cache); | |
2669 | } | |
2670 | ||
2671 | static void | |
2672 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2673 | struct frame_id *this_id) | |
2674 | { | |
2675 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2676 | this_cache); | |
2677 | /* This marks the outermost frame. */ | |
2678 | if (info->base == 0) | |
2679 | return; | |
2680 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2681 | } | |
2682 | ||
2683 | static struct value * | |
2684 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2685 | void **this_cache, int regnum) | |
2686 | { | |
2687 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2688 | this_cache); | |
2689 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2690 | } | |
2691 | ||
2692 | static int | |
2693 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2694 | struct frame_info *this_frame, void **this_cache) | |
2695 | { | |
2696 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2697 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2698 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2699 | return 1; | |
2700 | return 0; | |
2701 | } | |
2702 | ||
2703 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2704 | { | |
2705 | NORMAL_FRAME, | |
2706 | default_frame_unwind_stop_reason, | |
2707 | mips_insn16_frame_this_id, | |
2708 | mips_insn16_frame_prev_register, | |
2709 | NULL, | |
2710 | mips_insn16_frame_sniffer | |
2711 | }; | |
2712 | ||
2713 | static CORE_ADDR | |
2714 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2715 | void **this_cache) | |
2716 | { | |
2717 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2718 | this_cache); | |
2719 | return info->base; | |
2720 | } | |
2721 | ||
2722 | static const struct frame_base mips_insn16_frame_base = | |
2723 | { | |
2724 | &mips_insn16_frame_unwind, | |
2725 | mips_insn16_frame_base_address, | |
2726 | mips_insn16_frame_base_address, | |
2727 | mips_insn16_frame_base_address | |
2728 | }; | |
2729 | ||
2730 | static const struct frame_base * | |
2731 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2732 | { | |
2733 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2734 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2735 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2736 | return &mips_insn16_frame_base; | |
2737 | else | |
2738 | return NULL; | |
2739 | } | |
2740 | ||
2741 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2742 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2743 | interpreted directly, and then multiplied by 4. */ | |
2744 | ||
2745 | static int | |
2746 | micromips_decode_imm9 (int imm) | |
2747 | { | |
2748 | imm = (imm ^ 0x100) - 0x100; | |
2749 | if (imm > -3 && imm < 2) | |
2750 | imm ^= 0x100; | |
2751 | return imm << 2; | |
2752 | } | |
2753 | ||
2754 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2755 | the address of the first instruction past the prologue. */ | |
2756 | ||
2757 | static CORE_ADDR | |
2758 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2759 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2760 | struct frame_info *this_frame, | |
2761 | struct mips_frame_cache *this_cache) | |
2762 | { | |
2763 | CORE_ADDR end_prologue_addr = 0; | |
2764 | int prev_non_prologue_insn = 0; | |
2765 | int frame_reg = MIPS_SP_REGNUM; | |
2766 | int this_non_prologue_insn; | |
2767 | int non_prologue_insns = 0; | |
2768 | long frame_offset = 0; /* Size of stack frame. */ | |
2769 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2770 | CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ | |
2771 | CORE_ADDR prev_pc; | |
2772 | CORE_ADDR cur_pc; | |
2773 | ULONGEST insn; /* current instruction */ | |
2774 | CORE_ADDR sp; | |
2775 | long offset; | |
2776 | long sp_adj; | |
2777 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2778 | int reglist; | |
2779 | int breg; | |
2780 | int dreg; | |
2781 | int sreg; | |
2782 | int treg; | |
2783 | int loc; | |
2784 | int op; | |
2785 | int s; | |
2786 | int i; | |
2787 | ||
2788 | /* Can be called when there's no process, and hence when there's no | |
2789 | THIS_FRAME. */ | |
2790 | if (this_frame != NULL) | |
2791 | sp = get_frame_register_signed (this_frame, | |
2792 | gdbarch_num_regs (gdbarch) | |
2793 | + MIPS_SP_REGNUM); | |
2794 | else | |
2795 | sp = 0; | |
2796 | ||
2797 | if (limit_pc > start_pc + 200) | |
2798 | limit_pc = start_pc + 200; | |
2799 | prev_pc = start_pc; | |
2800 | ||
2801 | /* Permit at most one non-prologue non-control-transfer instruction | |
2802 | in the middle which may have been reordered by the compiler for | |
2803 | optimisation. */ | |
2804 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2805 | { | |
2806 | this_non_prologue_insn = 0; | |
2807 | sp_adj = 0; | |
2808 | loc = 0; | |
2809 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2810 | loc += MIPS_INSN16_SIZE; | |
2811 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2812 | { | |
2813 | /* 48-bit instructions. */ | |
2814 | case 3 * MIPS_INSN16_SIZE: | |
2815 | /* No prologue instructions in this category. */ | |
2816 | this_non_prologue_insn = 1; | |
2817 | loc += 2 * MIPS_INSN16_SIZE; | |
2818 | break; | |
2819 | ||
2820 | /* 32-bit instructions. */ | |
2821 | case 2 * MIPS_INSN16_SIZE: | |
2822 | insn <<= 16; | |
2823 | insn |= mips_fetch_instruction (gdbarch, | |
2824 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2825 | loc += MIPS_INSN16_SIZE; | |
2826 | switch (micromips_op (insn >> 16)) | |
2827 | { | |
2828 | /* Record $sp/$fp adjustment. */ | |
2829 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2830 | case 0x0: /* POOL32A: bits 000000 */ | |
2831 | case 0x16: /* POOL32S: bits 010110 */ | |
2832 | op = b0s11_op (insn); | |
2833 | sreg = b0s5_reg (insn >> 16); | |
2834 | treg = b5s5_reg (insn >> 16); | |
2835 | dreg = b11s5_reg (insn); | |
2836 | if (op == 0x1d0 | |
2837 | /* SUBU: bits 000000 00111010000 */ | |
2838 | /* DSUBU: bits 010110 00111010000 */ | |
2839 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
2840 | && treg == 3) | |
2841 | /* (D)SUBU $sp, $v1 */ | |
2842 | sp_adj = v1_off; | |
2843 | else if (op != 0x150 | |
2844 | /* ADDU: bits 000000 00101010000 */ | |
2845 | /* DADDU: bits 010110 00101010000 */ | |
2846 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
2847 | this_non_prologue_insn = 1; | |
2848 | break; | |
2849 | ||
2850 | case 0x8: /* POOL32B: bits 001000 */ | |
2851 | op = b12s4_op (insn); | |
2852 | breg = b0s5_reg (insn >> 16); | |
2853 | reglist = sreg = b5s5_reg (insn >> 16); | |
2854 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
2855 | if ((op == 0x9 || op == 0xc) | |
2856 | /* SWP: bits 001000 1001 */ | |
2857 | /* SDP: bits 001000 1100 */ | |
2858 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
2859 | /* S[DW]P reg,offset($sp) */ | |
2860 | { | |
2861 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
2862 | set_reg_offset (gdbarch, this_cache, | |
2863 | sreg, sp + offset); | |
2864 | set_reg_offset (gdbarch, this_cache, | |
2865 | sreg + 1, sp + offset + s); | |
2866 | } | |
2867 | else if ((op == 0xd || op == 0xf) | |
2868 | /* SWM: bits 001000 1101 */ | |
2869 | /* SDM: bits 001000 1111 */ | |
2870 | && breg == MIPS_SP_REGNUM | |
2871 | /* SWM reglist,offset($sp) */ | |
2872 | && ((reglist >= 1 && reglist <= 9) | |
2873 | || (reglist >= 16 && reglist <= 25))) | |
2874 | { | |
2875 | int sreglist = min(reglist & 0xf, 8); | |
2876 | ||
2877 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
2878 | for (i = 0; i < sreglist; i++) | |
2879 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
2880 | if ((reglist & 0xf) > 8) | |
2881 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
2882 | if ((reglist & 0x10) == 0x10) | |
2883 | set_reg_offset (gdbarch, this_cache, | |
2884 | MIPS_RA_REGNUM, sp + s * i++); | |
2885 | } | |
2886 | else | |
2887 | this_non_prologue_insn = 1; | |
2888 | break; | |
2889 | ||
2890 | /* Record $sp/$fp adjustment. */ | |
2891 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
2892 | case 0xc: /* ADDIU: bits 001100 */ | |
2893 | case 0x17: /* DADDIU: bits 010111 */ | |
2894 | sreg = b0s5_reg (insn >> 16); | |
2895 | dreg = b5s5_reg (insn >> 16); | |
2896 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2897 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
2898 | /* (D)ADDIU $sp, imm */ | |
2899 | sp_adj = offset; | |
2900 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2901 | /* (D)ADDIU $fp, $sp, imm */ | |
2902 | { | |
2903 | frame_addr = sp + offset; | |
2904 | frame_adjust = offset; | |
2905 | frame_reg = 30; | |
2906 | } | |
2907 | else if (sreg != 28 || dreg != 28) | |
2908 | /* (D)ADDIU $gp, imm */ | |
2909 | this_non_prologue_insn = 1; | |
2910 | break; | |
2911 | ||
2912 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 2913 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
2914 | case 0x10: /* POOL32I: bits 010000 */ |
2915 | if (b5s5_op (insn >> 16) == 0xd | |
2916 | /* LUI: bits 010000 001101 */ | |
2917 | && b0s5_reg (insn >> 16) == 3) | |
2918 | /* LUI $v1, imm */ | |
2919 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
2920 | else if (b5s5_op (insn >> 16) != 0xd | |
2921 | /* LUI: bits 010000 001101 */ | |
2922 | || b0s5_reg (insn >> 16) != 28) | |
2923 | /* LUI $gp, imm */ | |
2924 | this_non_prologue_insn = 1; | |
2925 | break; | |
2926 | ||
2927 | /* ORI $v1 is used for larger $sp adjustments. */ | |
2928 | case 0x14: /* ORI: bits 010100 */ | |
2929 | sreg = b0s5_reg (insn >> 16); | |
2930 | dreg = b5s5_reg (insn >> 16); | |
2931 | if (sreg == 3 && dreg == 3) | |
2932 | /* ORI $v1, imm */ | |
2933 | v1_off |= b0s16_imm (insn); | |
2934 | else | |
2935 | this_non_prologue_insn = 1; | |
2936 | break; | |
2937 | ||
2938 | case 0x26: /* SWC1: bits 100110 */ | |
2939 | case 0x2e: /* SDC1: bits 101110 */ | |
2940 | breg = b0s5_reg (insn >> 16); | |
2941 | if (breg != MIPS_SP_REGNUM) | |
2942 | /* S[DW]C1 reg,offset($sp) */ | |
2943 | this_non_prologue_insn = 1; | |
2944 | break; | |
2945 | ||
2946 | case 0x36: /* SD: bits 110110 */ | |
2947 | case 0x3e: /* SW: bits 111110 */ | |
2948 | breg = b0s5_reg (insn >> 16); | |
2949 | sreg = b5s5_reg (insn >> 16); | |
2950 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2951 | if (breg == MIPS_SP_REGNUM) | |
2952 | /* S[DW] reg,offset($sp) */ | |
2953 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2954 | else | |
2955 | this_non_prologue_insn = 1; | |
2956 | break; | |
2957 | ||
2958 | default: | |
2959 | this_non_prologue_insn = 1; | |
2960 | break; | |
2961 | } | |
2962 | break; | |
2963 | ||
2964 | /* 16-bit instructions. */ | |
2965 | case MIPS_INSN16_SIZE: | |
2966 | switch (micromips_op (insn)) | |
2967 | { | |
2968 | case 0x3: /* MOVE: bits 000011 */ | |
2969 | sreg = b0s5_reg (insn); | |
2970 | dreg = b5s5_reg (insn); | |
2971 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2972 | /* MOVE $fp, $sp */ | |
2973 | { | |
2974 | frame_addr = sp; | |
2975 | frame_reg = 30; | |
2976 | } | |
2977 | else if ((sreg & 0x1c) != 0x4) | |
2978 | /* MOVE reg, $a0-$a3 */ | |
2979 | this_non_prologue_insn = 1; | |
2980 | break; | |
2981 | ||
2982 | case 0x11: /* POOL16C: bits 010001 */ | |
2983 | if (b6s4_op (insn) == 0x5) | |
2984 | /* SWM: bits 010001 0101 */ | |
2985 | { | |
2986 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
2987 | reglist = b4s2_regl (insn); | |
2988 | for (i = 0; i <= reglist; i++) | |
2989 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
2990 | set_reg_offset (gdbarch, this_cache, | |
2991 | MIPS_RA_REGNUM, sp + 4 * i++); | |
2992 | } | |
2993 | else | |
2994 | this_non_prologue_insn = 1; | |
2995 | break; | |
2996 | ||
2997 | case 0x13: /* POOL16D: bits 010011 */ | |
2998 | if ((insn & 0x1) == 0x1) | |
2999 | /* ADDIUSP: bits 010011 1 */ | |
3000 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3001 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3002 | /* ADDIUS5: bits 010011 0 */ | |
3003 | /* ADDIUS5 $sp, imm */ | |
3004 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3005 | else | |
3006 | this_non_prologue_insn = 1; | |
3007 | break; | |
3008 | ||
3009 | case 0x32: /* SWSP: bits 110010 */ | |
3010 | offset = b0s5_imm (insn) << 2; | |
3011 | sreg = b5s5_reg (insn); | |
3012 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3013 | break; | |
3014 | ||
3015 | default: | |
3016 | this_non_prologue_insn = 1; | |
3017 | break; | |
3018 | } | |
3019 | break; | |
3020 | } | |
3021 | if (sp_adj < 0) | |
3022 | frame_offset -= sp_adj; | |
3023 | ||
3024 | non_prologue_insns += this_non_prologue_insn; | |
3025 | /* Enough non-prologue insns seen or positive stack adjustment? */ | |
3026 | if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0)) | |
2207132d | 3027 | { |
4cc0665f MR |
3028 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
3029 | break; | |
2207132d | 3030 | } |
4cc0665f MR |
3031 | prev_non_prologue_insn = this_non_prologue_insn; |
3032 | prev_pc = cur_pc; | |
2207132d MR |
3033 | } |
3034 | ||
29639122 JB |
3035 | if (this_cache != NULL) |
3036 | { | |
3037 | this_cache->base = | |
4cc0665f | 3038 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3039 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3040 | + frame_offset - frame_adjust); |
29639122 | 3041 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3042 | be able to get rid of the assignment below, evetually. But it's |
3043 | still needed for now. */ | |
72a155b4 UW |
3044 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3045 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3046 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3047 | } |
3048 | ||
3049 | /* If we didn't reach the end of the prologue when scanning the function | |
3050 | instructions, then set end_prologue_addr to the address of the | |
4cc0665f MR |
3051 | instruction immediately after the last one we scanned. Unless the |
3052 | last one looked like a non-prologue instruction (and we looked ahead), | |
3053 | in which case use its address instead. */ | |
29639122 | 3054 | if (end_prologue_addr == 0) |
4cc0665f | 3055 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
29639122 JB |
3056 | |
3057 | return end_prologue_addr; | |
eec63939 AC |
3058 | } |
3059 | ||
4cc0665f | 3060 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3061 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3062 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3063 | |
3064 | static struct mips_frame_cache * | |
4cc0665f | 3065 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3066 | { |
e17a4113 | 3067 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3068 | struct mips_frame_cache *cache; |
eec63939 AC |
3069 | |
3070 | if ((*this_cache) != NULL) | |
3071 | return (*this_cache); | |
4cc0665f | 3072 | |
29639122 JB |
3073 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3074 | (*this_cache) = cache; | |
b8a22b94 | 3075 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3076 | |
29639122 JB |
3077 | /* Analyze the function prologue. */ |
3078 | { | |
b8a22b94 | 3079 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3080 | CORE_ADDR start_addr; |
eec63939 | 3081 | |
29639122 JB |
3082 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3083 | if (start_addr == 0) | |
4cc0665f | 3084 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3085 | /* We can't analyze the prologue if we couldn't find the begining |
3086 | of the function. */ | |
3087 | if (start_addr == 0) | |
3088 | return cache; | |
eec63939 | 3089 | |
4cc0665f | 3090 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 | 3091 | } |
4cc0665f | 3092 | |
3e8c568d | 3093 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3094 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3095 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3096 | cache->base); |
eec63939 | 3097 | |
29639122 | 3098 | return (*this_cache); |
eec63939 AC |
3099 | } |
3100 | ||
3101 | static void | |
4cc0665f MR |
3102 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3103 | struct frame_id *this_id) | |
eec63939 | 3104 | { |
4cc0665f MR |
3105 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3106 | this_cache); | |
21327321 DJ |
3107 | /* This marks the outermost frame. */ |
3108 | if (info->base == 0) | |
3109 | return; | |
b8a22b94 | 3110 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3111 | } |
3112 | ||
b8a22b94 | 3113 | static struct value * |
4cc0665f MR |
3114 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3115 | void **this_cache, int regnum) | |
eec63939 | 3116 | { |
4cc0665f MR |
3117 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3118 | this_cache); | |
b8a22b94 DJ |
3119 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3120 | } | |
3121 | ||
3122 | static int | |
4cc0665f MR |
3123 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3124 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3125 | { |
4cc0665f | 3126 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3127 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3128 | |
3129 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3130 | return 1; |
3131 | return 0; | |
eec63939 AC |
3132 | } |
3133 | ||
4cc0665f | 3134 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3135 | { |
3136 | NORMAL_FRAME, | |
8fbca658 | 3137 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3138 | mips_micro_frame_this_id, |
3139 | mips_micro_frame_prev_register, | |
b8a22b94 | 3140 | NULL, |
4cc0665f | 3141 | mips_micro_frame_sniffer |
eec63939 AC |
3142 | }; |
3143 | ||
eec63939 | 3144 | static CORE_ADDR |
4cc0665f MR |
3145 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3146 | void **this_cache) | |
eec63939 | 3147 | { |
4cc0665f MR |
3148 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3149 | this_cache); | |
29639122 | 3150 | return info->base; |
eec63939 AC |
3151 | } |
3152 | ||
4cc0665f | 3153 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3154 | { |
4cc0665f MR |
3155 | &mips_micro_frame_unwind, |
3156 | mips_micro_frame_base_address, | |
3157 | mips_micro_frame_base_address, | |
3158 | mips_micro_frame_base_address | |
eec63939 AC |
3159 | }; |
3160 | ||
3161 | static const struct frame_base * | |
4cc0665f | 3162 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3163 | { |
4cc0665f | 3164 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3165 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3166 | |
3167 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3168 | return &mips_micro_frame_base; | |
eec63939 AC |
3169 | else |
3170 | return NULL; | |
edfae063 AC |
3171 | } |
3172 | ||
29639122 JB |
3173 | /* Mark all the registers as unset in the saved_regs array |
3174 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3175 | ||
74ed0bb4 MD |
3176 | static void |
3177 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3178 | { |
29639122 JB |
3179 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3180 | return; | |
3181 | ||
3182 | { | |
74ed0bb4 | 3183 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3184 | int i; |
64159455 | 3185 | |
29639122 JB |
3186 | for (i = 0; i < num_regs; i++) |
3187 | { | |
3188 | this_cache->saved_regs[i].addr = -1; | |
3189 | } | |
3190 | } | |
c906108c SS |
3191 | } |
3192 | ||
025bb325 | 3193 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3194 | the associated FRAME_CACHE if not null. |
3195 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3196 | |
875e1767 | 3197 | static CORE_ADDR |
e17a4113 UW |
3198 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3199 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3200 | struct frame_info *this_frame, |
29639122 | 3201 | struct mips_frame_cache *this_cache) |
c906108c | 3202 | { |
29639122 | 3203 | CORE_ADDR cur_pc; |
025bb325 MS |
3204 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3205 | frame-pointer. */ | |
29639122 JB |
3206 | CORE_ADDR sp; |
3207 | long frame_offset; | |
3208 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3209 | |
29639122 JB |
3210 | CORE_ADDR end_prologue_addr = 0; |
3211 | int seen_sp_adjust = 0; | |
3212 | int load_immediate_bytes = 0; | |
db5f024e | 3213 | int in_delay_slot = 0; |
7d1e6fb8 | 3214 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3215 | |
29639122 | 3216 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3217 | THIS_FRAME. */ |
3218 | if (this_frame != NULL) | |
3219 | sp = get_frame_register_signed (this_frame, | |
3220 | gdbarch_num_regs (gdbarch) | |
3221 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3222 | else |
29639122 | 3223 | sp = 0; |
9022177c | 3224 | |
29639122 JB |
3225 | if (limit_pc > start_pc + 200) |
3226 | limit_pc = start_pc + 200; | |
9022177c | 3227 | |
29639122 | 3228 | restart: |
9022177c | 3229 | |
29639122 | 3230 | frame_offset = 0; |
95ac2dcf | 3231 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3232 | { |
29639122 JB |
3233 | unsigned long inst, high_word, low_word; |
3234 | int reg; | |
9022177c | 3235 | |
025bb325 | 3236 | /* Fetch the instruction. */ |
4cc0665f MR |
3237 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3238 | cur_pc, NULL); | |
9022177c | 3239 | |
29639122 JB |
3240 | /* Save some code by pre-extracting some useful fields. */ |
3241 | high_word = (inst >> 16) & 0xffff; | |
3242 | low_word = inst & 0xffff; | |
3243 | reg = high_word & 0x1f; | |
fe29b929 | 3244 | |
025bb325 | 3245 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3246 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3247 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3248 | { | |
025bb325 | 3249 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
3250 | frame_offset += 0x10000 - low_word; |
3251 | else | |
3252 | /* Exit loop if a positive stack adjustment is found, which | |
3253 | usually means that the stack cleanup code in the function | |
3254 | epilogue is reached. */ | |
3255 | break; | |
3256 | seen_sp_adjust = 1; | |
3257 | } | |
7d1e6fb8 KB |
3258 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3259 | && !regsize_is_64_bits) | |
29639122 | 3260 | { |
74ed0bb4 | 3261 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 3262 | } |
7d1e6fb8 KB |
3263 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3264 | && regsize_is_64_bits) | |
29639122 JB |
3265 | { |
3266 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 3267 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
3268 | } |
3269 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3270 | { | |
3271 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
3272 | if ((long) low_word != frame_offset) | |
3273 | frame_addr = sp + low_word; | |
b8a22b94 | 3274 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3275 | { |
3276 | unsigned alloca_adjust; | |
a4b8ebc8 | 3277 | |
29639122 | 3278 | frame_reg = 30; |
b8a22b94 DJ |
3279 | frame_addr = get_frame_register_signed |
3280 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3281 | frame_offset = 0; |
d2ca4222 | 3282 | |
29639122 JB |
3283 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
3284 | if (alloca_adjust > 0) | |
3285 | { | |
025bb325 | 3286 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3287 | an alloca or somethings similar. Fix sp to |
3288 | "pre-alloca" value, and try again. */ | |
3289 | sp += alloca_adjust; | |
3290 | /* Need to reset the status of all registers. Otherwise, | |
3291 | we will hit a guard that prevents the new address | |
3292 | for each register to be recomputed during the second | |
3293 | pass. */ | |
74ed0bb4 | 3294 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3295 | goto restart; |
3296 | } | |
3297 | } | |
3298 | } | |
3299 | /* move $30,$sp. With different versions of gas this will be either | |
3300 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3301 | Accept any one of these. */ | |
3302 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3303 | { | |
3304 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3305 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3306 | { |
3307 | unsigned alloca_adjust; | |
c906108c | 3308 | |
29639122 | 3309 | frame_reg = 30; |
b8a22b94 DJ |
3310 | frame_addr = get_frame_register_signed |
3311 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3312 | |
29639122 JB |
3313 | alloca_adjust = (unsigned) (frame_addr - sp); |
3314 | if (alloca_adjust > 0) | |
3315 | { | |
025bb325 | 3316 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3317 | an alloca or somethings similar. Fix sp to |
3318 | "pre-alloca" value, and try again. */ | |
3319 | sp = frame_addr; | |
3320 | /* Need to reset the status of all registers. Otherwise, | |
3321 | we will hit a guard that prevents the new address | |
3322 | for each register to be recomputed during the second | |
3323 | pass. */ | |
74ed0bb4 | 3324 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3325 | goto restart; |
3326 | } | |
3327 | } | |
3328 | } | |
7d1e6fb8 KB |
3329 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3330 | && !regsize_is_64_bits) | |
29639122 | 3331 | { |
74ed0bb4 | 3332 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
3333 | } |
3334 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3335 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3336 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3337 | || high_word == 0x3c1c /* lui $gp,n */ | |
3338 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3339 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3340 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3341 | ) | |
19080931 MR |
3342 | { |
3343 | /* These instructions are part of the prologue, but we don't | |
3344 | need to do anything special to handle them. */ | |
3345 | } | |
29639122 JB |
3346 | /* The instructions below load $at or $t0 with an immediate |
3347 | value in preparation for a stack adjustment via | |
025bb325 | 3348 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3349 | initialize a local variable, so we accept them only before |
3350 | a stack adjustment instruction was seen. */ | |
3351 | else if (!seen_sp_adjust | |
19080931 MR |
3352 | && (high_word == 0x3c01 /* lui $at,n */ |
3353 | || high_word == 0x3c08 /* lui $t0,n */ | |
3354 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3355 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3356 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3357 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3358 | )) | |
3359 | { | |
3360 | if (end_prologue_addr == 0) | |
3361 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
3362 | } | |
29639122 | 3363 | else |
19080931 MR |
3364 | { |
3365 | /* This instruction is not an instruction typically found | |
3366 | in a prologue, so we must have reached the end of the | |
3367 | prologue. */ | |
3368 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
3369 | loop now? Why would we need to continue scanning the function | |
3370 | instructions? */ | |
3371 | if (end_prologue_addr == 0) | |
3372 | end_prologue_addr = cur_pc; | |
3373 | ||
3374 | /* Check for branches and jumps. For now, only jump to | |
3375 | register are caught (i.e. returns). */ | |
3376 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
3377 | in_delay_slot = 1; | |
3378 | } | |
db5f024e DJ |
3379 | |
3380 | /* If the previous instruction was a jump, we must have reached | |
3381 | the end of the prologue by now. Stop scanning so that we do | |
3382 | not go past the function return. */ | |
3383 | if (in_delay_slot) | |
3384 | break; | |
a4b8ebc8 | 3385 | } |
c906108c | 3386 | |
29639122 JB |
3387 | if (this_cache != NULL) |
3388 | { | |
3389 | this_cache->base = | |
b8a22b94 DJ |
3390 | (get_frame_register_signed (this_frame, |
3391 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3392 | + frame_offset); |
3393 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3394 | this assignment below, eventually. But it's still needed | |
3395 | for now. */ | |
72a155b4 UW |
3396 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3397 | + mips_regnum (gdbarch)->pc] | |
3398 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3399 | + MIPS_RA_REGNUM]; |
29639122 | 3400 | } |
c906108c | 3401 | |
29639122 JB |
3402 | /* If we didn't reach the end of the prologue when scanning the function |
3403 | instructions, then set end_prologue_addr to the address of the | |
3404 | instruction immediately after the last one we scanned. */ | |
3405 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
3406 | we may as well be careful and do our best if we have a null | |
3407 | end_prologue_addr. */ | |
3408 | if (end_prologue_addr == 0) | |
3409 | end_prologue_addr = cur_pc; | |
3410 | ||
3411 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3412 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3413 | if the load immediate was not followed by a stack adjustment. */ |
3414 | if (load_immediate_bytes && !seen_sp_adjust) | |
3415 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3416 | |
29639122 | 3417 | return end_prologue_addr; |
c906108c SS |
3418 | } |
3419 | ||
29639122 JB |
3420 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3421 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3422 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3423 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3424 | |
29639122 | 3425 | static struct mips_frame_cache * |
b8a22b94 | 3426 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3427 | { |
e17a4113 | 3428 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3429 | struct mips_frame_cache *cache; |
c906108c | 3430 | |
29639122 JB |
3431 | if ((*this_cache) != NULL) |
3432 | return (*this_cache); | |
c5aa993b | 3433 | |
29639122 JB |
3434 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3435 | (*this_cache) = cache; | |
b8a22b94 | 3436 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3437 | |
29639122 JB |
3438 | /* Analyze the function prologue. */ |
3439 | { | |
b8a22b94 | 3440 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3441 | CORE_ADDR start_addr; |
c906108c | 3442 | |
29639122 JB |
3443 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3444 | if (start_addr == 0) | |
e17a4113 | 3445 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3446 | /* We can't analyze the prologue if we couldn't find the begining |
3447 | of the function. */ | |
3448 | if (start_addr == 0) | |
3449 | return cache; | |
c5aa993b | 3450 | |
e17a4113 | 3451 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
3452 | } |
3453 | ||
3e8c568d | 3454 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3455 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3456 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3457 | cache->base); |
c5aa993b | 3458 | |
29639122 | 3459 | return (*this_cache); |
c906108c SS |
3460 | } |
3461 | ||
29639122 | 3462 | static void |
b8a22b94 | 3463 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3464 | struct frame_id *this_id) |
c906108c | 3465 | { |
b8a22b94 | 3466 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3467 | this_cache); |
21327321 DJ |
3468 | /* This marks the outermost frame. */ |
3469 | if (info->base == 0) | |
3470 | return; | |
b8a22b94 | 3471 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3472 | } |
c906108c | 3473 | |
b8a22b94 DJ |
3474 | static struct value * |
3475 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3476 | void **this_cache, int regnum) | |
29639122 | 3477 | { |
b8a22b94 | 3478 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3479 | this_cache); |
b8a22b94 DJ |
3480 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3481 | } | |
3482 | ||
3483 | static int | |
3484 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3485 | struct frame_info *this_frame, void **this_cache) | |
3486 | { | |
3487 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3488 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3489 | return 1; |
3490 | return 0; | |
c906108c SS |
3491 | } |
3492 | ||
29639122 JB |
3493 | static const struct frame_unwind mips_insn32_frame_unwind = |
3494 | { | |
3495 | NORMAL_FRAME, | |
8fbca658 | 3496 | default_frame_unwind_stop_reason, |
29639122 | 3497 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3498 | mips_insn32_frame_prev_register, |
3499 | NULL, | |
3500 | mips_insn32_frame_sniffer | |
29639122 | 3501 | }; |
c906108c | 3502 | |
1c645fec | 3503 | static CORE_ADDR |
b8a22b94 | 3504 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3505 | void **this_cache) |
c906108c | 3506 | { |
b8a22b94 | 3507 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3508 | this_cache); |
3509 | return info->base; | |
3510 | } | |
c906108c | 3511 | |
29639122 JB |
3512 | static const struct frame_base mips_insn32_frame_base = |
3513 | { | |
3514 | &mips_insn32_frame_unwind, | |
3515 | mips_insn32_frame_base_address, | |
3516 | mips_insn32_frame_base_address, | |
3517 | mips_insn32_frame_base_address | |
3518 | }; | |
1c645fec | 3519 | |
29639122 | 3520 | static const struct frame_base * |
b8a22b94 | 3521 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3522 | { |
b8a22b94 | 3523 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3524 | if (mips_pc_is_mips (pc)) |
29639122 | 3525 | return &mips_insn32_frame_base; |
a65bbe44 | 3526 | else |
29639122 JB |
3527 | return NULL; |
3528 | } | |
a65bbe44 | 3529 | |
29639122 | 3530 | static struct trad_frame_cache * |
b8a22b94 | 3531 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3532 | { |
3533 | CORE_ADDR pc; | |
3534 | CORE_ADDR start_addr; | |
3535 | CORE_ADDR stack_addr; | |
3536 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3537 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3538 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3539 | |
29639122 JB |
3540 | if ((*this_cache) != NULL) |
3541 | return (*this_cache); | |
b8a22b94 | 3542 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3543 | (*this_cache) = this_trad_cache; |
1c645fec | 3544 | |
29639122 | 3545 | /* The return address is in the link register. */ |
3e8c568d | 3546 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3547 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3548 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3549 | |
29639122 JB |
3550 | /* Frame ID, since it's a frameless / stackless function, no stack |
3551 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3552 | pc = get_frame_pc (this_frame); |
29639122 | 3553 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3554 | stack_addr = get_frame_register_signed (this_frame, |
3555 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3556 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3557 | |
29639122 JB |
3558 | /* Assume that the frame's base is the same as the |
3559 | stack-pointer. */ | |
3560 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3561 | |
29639122 JB |
3562 | return this_trad_cache; |
3563 | } | |
c906108c | 3564 | |
29639122 | 3565 | static void |
b8a22b94 | 3566 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3567 | struct frame_id *this_id) |
3568 | { | |
3569 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3570 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3571 | trad_frame_get_id (this_trad_cache, this_id); |
3572 | } | |
c906108c | 3573 | |
b8a22b94 DJ |
3574 | static struct value * |
3575 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3576 | void **this_cache, int regnum) | |
29639122 JB |
3577 | { |
3578 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3579 | = mips_stub_frame_cache (this_frame, this_cache); |
3580 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3581 | } |
c906108c | 3582 | |
b8a22b94 DJ |
3583 | static int |
3584 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3585 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3586 | { |
aa6c981f | 3587 | gdb_byte dummy[4]; |
979b38e0 | 3588 | struct obj_section *s; |
b8a22b94 | 3589 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3590 | struct bound_minimal_symbol msym; |
979b38e0 | 3591 | |
aa6c981f | 3592 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3593 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3594 | return 1; | |
aa6c981f | 3595 | |
3e5d3a5a | 3596 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3597 | return 1; |
979b38e0 | 3598 | |
db5f024e DJ |
3599 | /* Calling a PIC function from a non-PIC function passes through a |
3600 | stub. The stub for foo is named ".pic.foo". */ | |
3601 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3602 | if (msym.minsym != NULL |
efd66ac6 TT |
3603 | && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL |
3604 | && strncmp (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) == 0) | |
db5f024e DJ |
3605 | return 1; |
3606 | ||
b8a22b94 | 3607 | return 0; |
29639122 | 3608 | } |
c906108c | 3609 | |
b8a22b94 DJ |
3610 | static const struct frame_unwind mips_stub_frame_unwind = |
3611 | { | |
3612 | NORMAL_FRAME, | |
8fbca658 | 3613 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3614 | mips_stub_frame_this_id, |
3615 | mips_stub_frame_prev_register, | |
3616 | NULL, | |
3617 | mips_stub_frame_sniffer | |
3618 | }; | |
3619 | ||
29639122 | 3620 | static CORE_ADDR |
b8a22b94 | 3621 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3622 | void **this_cache) |
3623 | { | |
3624 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3625 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3626 | return trad_frame_get_this_base (this_trad_cache); |
3627 | } | |
0fce0821 | 3628 | |
29639122 JB |
3629 | static const struct frame_base mips_stub_frame_base = |
3630 | { | |
3631 | &mips_stub_frame_unwind, | |
3632 | mips_stub_frame_base_address, | |
3633 | mips_stub_frame_base_address, | |
3634 | mips_stub_frame_base_address | |
3635 | }; | |
3636 | ||
3637 | static const struct frame_base * | |
b8a22b94 | 3638 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3639 | { |
b8a22b94 | 3640 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3641 | return &mips_stub_frame_base; |
3642 | else | |
3643 | return NULL; | |
3644 | } | |
3645 | ||
29639122 | 3646 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3647 | |
29639122 | 3648 | static CORE_ADDR |
24568a2c | 3649 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3650 | { |
24568a2c | 3651 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3652 | |
4cc0665f MR |
3653 | if (is_compact_addr (addr)) |
3654 | addr = unmake_compact_addr (addr); | |
930bd0e0 | 3655 | |
29639122 JB |
3656 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3657 | /* This hack is a work-around for existing boards using PMON, the | |
3658 | simulator, and any other 64-bit targets that doesn't have true | |
3659 | 64-bit addressing. On these targets, the upper 32 bits of | |
3660 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3661 | likely to have been sign extended to all 1s by instruction | |
3662 | sequences that load 32-bit addresses. For example, a typical | |
3663 | piece of code that loads an address is this: | |
65596487 | 3664 | |
29639122 JB |
3665 | lui $r2, <upper 16 bits> |
3666 | ori $r2, <lower 16 bits> | |
65596487 | 3667 | |
29639122 JB |
3668 | But the lui sign-extends the value such that the upper 32 bits |
3669 | may be all 1s. The workaround is simply to mask off these | |
3670 | bits. In the future, gcc may be changed to support true 64-bit | |
3671 | addressing, and this masking will have to be disabled. */ | |
3672 | return addr &= 0xffffffffUL; | |
3673 | else | |
3674 | return addr; | |
65596487 JB |
3675 | } |
3676 | ||
3d5f6d12 DJ |
3677 | |
3678 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3679 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3680 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3681 | the sequence. */ | |
3682 | ||
4cc0665f MR |
3683 | /* Instructions used during single-stepping of atomic sequences, standard |
3684 | ISA version. */ | |
3685 | #define LL_OPCODE 0x30 | |
3686 | #define LLD_OPCODE 0x34 | |
3687 | #define SC_OPCODE 0x38 | |
3688 | #define SCD_OPCODE 0x3c | |
3689 | ||
3d5f6d12 | 3690 | static int |
4cc0665f MR |
3691 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
3692 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
3693 | { |
3694 | CORE_ADDR breaks[2] = {-1, -1}; | |
3695 | CORE_ADDR loc = pc; | |
3696 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3697 | ULONGEST insn; |
3d5f6d12 DJ |
3698 | int insn_count; |
3699 | int index; | |
3700 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3701 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3702 | ||
4cc0665f | 3703 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3704 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3705 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
3706 | return 0; | |
3707 | ||
3708 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3709 | instructions. */ | |
3710 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3711 | { | |
3712 | int is_branch = 0; | |
3713 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3714 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3715 | |
3716 | /* Assume that there is at most one branch in the atomic | |
3717 | sequence. If a branch is found, put a breakpoint in its | |
3718 | destination address. */ | |
3719 | switch (itype_op (insn)) | |
3720 | { | |
3721 | case 0: /* SPECIAL */ | |
3722 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 3723 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3724 | break; |
3725 | case 1: /* REGIMM */ | |
a385295e MR |
3726 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3727 | || ((itype_rt (insn) & 0x1e) == 0 | |
3728 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3729 | break; |
3730 | case 2: /* J */ | |
3731 | case 3: /* JAL */ | |
025bb325 | 3732 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3733 | case 4: /* BEQ */ |
3734 | case 5: /* BNE */ | |
3735 | case 6: /* BLEZ */ | |
3736 | case 7: /* BGTZ */ | |
3737 | case 20: /* BEQL */ | |
3738 | case 21: /* BNEL */ | |
3739 | case 22: /* BLEZL */ | |
3740 | case 23: /* BGTTL */ | |
3741 | is_branch = 1; | |
3742 | break; | |
3743 | case 17: /* COP1 */ | |
a385295e MR |
3744 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3745 | && (itype_rt (insn) & 0x2) == 0); | |
3746 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3747 | break; | |
3748 | /* Fall through. */ | |
3d5f6d12 DJ |
3749 | case 18: /* COP2 */ |
3750 | case 19: /* COP3 */ | |
3751 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3752 | break; | |
3753 | } | |
3754 | if (is_branch) | |
3755 | { | |
3756 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3757 | if (last_breakpoint >= 1) | |
3758 | return 0; /* More than one branch found, fallback to the | |
3759 | standard single-step code. */ | |
3760 | breaks[1] = branch_bp; | |
3761 | last_breakpoint++; | |
3762 | } | |
3763 | ||
3764 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3765 | break; | |
3766 | } | |
3767 | ||
3768 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3769 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
3770 | return 0; | |
3771 | ||
3772 | loc += MIPS_INSN32_SIZE; | |
3773 | ||
3774 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3775 | breaks[0] = loc; | |
3776 | ||
3777 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3778 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3779 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3780 | last_breakpoint = 0; | |
3781 | ||
3782 | /* Effectively inserts the breakpoints. */ | |
3783 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 3784 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
3785 | |
3786 | return 1; | |
3787 | } | |
3788 | ||
4cc0665f MR |
3789 | static int |
3790 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3791 | struct address_space *aspace, | |
3792 | CORE_ADDR pc) | |
3793 | { | |
3794 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3795 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3796 | CORE_ADDR breaks[2] = {-1, -1}; | |
4b844a38 AT |
3797 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
3798 | destination. */ | |
4cc0665f MR |
3799 | CORE_ADDR loc = pc; |
3800 | int sc_found = 0; | |
3801 | ULONGEST insn; | |
3802 | int insn_count; | |
3803 | int index; | |
3804 | ||
3805 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3806 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3807 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
3808 | return 0; | |
3809 | loc += MIPS_INSN16_SIZE; | |
3810 | insn <<= 16; | |
3811 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3812 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
3813 | return 0; | |
3814 | loc += MIPS_INSN16_SIZE; | |
3815 | ||
3816 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
3817 | that no atomic sequence is longer than "atomic_sequence_length" | |
3818 | instructions. */ | |
3819 | for (insn_count = 0; | |
3820 | !sc_found && insn_count < atomic_sequence_length; | |
3821 | ++insn_count) | |
3822 | { | |
3823 | int is_branch = 0; | |
3824 | ||
3825 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3826 | loc += MIPS_INSN16_SIZE; | |
3827 | ||
3828 | /* Assume that there is at most one conditional branch in the | |
3829 | atomic sequence. If a branch is found, put a breakpoint in | |
3830 | its destination address. */ | |
3831 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3832 | { | |
3833 | /* 48-bit instructions. */ | |
3834 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
3835 | loc += 2 * MIPS_INSN16_SIZE; | |
3836 | break; | |
3837 | ||
3838 | /* 32-bit instructions. */ | |
3839 | case 2 * MIPS_INSN16_SIZE: | |
3840 | switch (micromips_op (insn)) | |
3841 | { | |
3842 | case 0x10: /* POOL32I: bits 010000 */ | |
3843 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
3844 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
3845 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
3846 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
3847 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
3848 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
3849 | || (insn & 0x3) != 0x0) | |
3850 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
3851 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
3852 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
3853 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
3854 | || (insn & 0x3) != 0x0) | |
3855 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
3856 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
3857 | || (insn & 0x3) != 0x1)) | |
3858 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
3859 | break; | |
3860 | /* Fall through. */ | |
3861 | ||
3862 | case 0x25: /* BEQ: bits 100101 */ | |
3863 | case 0x2d: /* BNE: bits 101101 */ | |
3864 | insn <<= 16; | |
3865 | insn |= mips_fetch_instruction (gdbarch, | |
3866 | ISA_MICROMIPS, loc, NULL); | |
3867 | branch_bp = (loc + MIPS_INSN16_SIZE | |
3868 | + micromips_relative_offset16 (insn)); | |
3869 | is_branch = 1; | |
3870 | break; | |
3871 | ||
3872 | case 0x00: /* POOL32A: bits 000000 */ | |
3873 | insn <<= 16; | |
3874 | insn |= mips_fetch_instruction (gdbarch, | |
3875 | ISA_MICROMIPS, loc, NULL); | |
3876 | if (b0s6_op (insn) != 0x3c | |
3877 | /* POOL32Axf: bits 000000 ... 111100 */ | |
3878 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
3879 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
3880 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
3881 | break; | |
3882 | /* Fall through. */ | |
3883 | ||
3884 | case 0x1d: /* JALS: bits 011101 */ | |
3885 | case 0x35: /* J: bits 110101 */ | |
3886 | case 0x3d: /* JAL: bits 111101 */ | |
3887 | case 0x3c: /* JALX: bits 111100 */ | |
3888 | return 0; /* Fall back to the standard single-step code. */ | |
3889 | ||
3890 | case 0x18: /* POOL32C: bits 011000 */ | |
3891 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
3892 | /* SC, SCD: bits 011000 1x11 */ | |
3893 | sc_found = 1; | |
3894 | break; | |
3895 | } | |
3896 | loc += MIPS_INSN16_SIZE; | |
3897 | break; | |
3898 | ||
3899 | /* 16-bit instructions. */ | |
3900 | case MIPS_INSN16_SIZE: | |
3901 | switch (micromips_op (insn)) | |
3902 | { | |
3903 | case 0x23: /* BEQZ16: bits 100011 */ | |
3904 | case 0x2b: /* BNEZ16: bits 101011 */ | |
3905 | branch_bp = loc + micromips_relative_offset7 (insn); | |
3906 | is_branch = 1; | |
3907 | break; | |
3908 | ||
3909 | case 0x11: /* POOL16C: bits 010001 */ | |
3910 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
3911 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
3912 | && b5s5_op (insn) != 0x18) | |
3913 | /* JRADDIUSP: bits 010001 11000 */ | |
3914 | break; | |
3915 | return 0; /* Fall back to the standard single-step code. */ | |
3916 | ||
3917 | case 0x33: /* B16: bits 110011 */ | |
3918 | return 0; /* Fall back to the standard single-step code. */ | |
3919 | } | |
3920 | break; | |
3921 | } | |
3922 | if (is_branch) | |
3923 | { | |
3924 | if (last_breakpoint >= 1) | |
3925 | return 0; /* More than one branch found, fallback to the | |
3926 | standard single-step code. */ | |
3927 | breaks[1] = branch_bp; | |
3928 | last_breakpoint++; | |
3929 | } | |
3930 | } | |
3931 | if (!sc_found) | |
3932 | return 0; | |
3933 | ||
3934 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3935 | breaks[0] = loc; | |
3936 | ||
3937 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
3938 | placed (branch instruction's destination) in the atomic sequence */ | |
3939 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
3940 | last_breakpoint = 0; | |
3941 | ||
3942 | /* Effectively inserts the breakpoints. */ | |
3943 | for (index = 0; index <= last_breakpoint; index++) | |
3373342d | 3944 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
4cc0665f MR |
3945 | |
3946 | return 1; | |
3947 | } | |
3948 | ||
3949 | static int | |
3950 | deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3951 | struct address_space *aspace, CORE_ADDR pc) | |
3952 | { | |
3953 | if (mips_pc_is_mips (pc)) | |
3954 | return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3955 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
3956 | return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3957 | else | |
3958 | return 0; | |
3959 | } | |
3960 | ||
29639122 JB |
3961 | /* mips_software_single_step() is called just before we want to resume |
3962 | the inferior, if we want to single-step it but there is no hardware | |
3963 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 3964 | the target of the coming instruction and breakpoint it. */ |
29639122 | 3965 | |
e6590a1b | 3966 | int |
0b1b3e42 | 3967 | mips_software_single_step (struct frame_info *frame) |
c906108c | 3968 | { |
a6d9a66e | 3969 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 3970 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 3971 | CORE_ADDR pc, next_pc; |
65596487 | 3972 | |
0b1b3e42 | 3973 | pc = get_frame_pc (frame); |
6c95b8df | 3974 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
3975 | return 1; |
3976 | ||
0b1b3e42 | 3977 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 3978 | |
6c95b8df | 3979 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 3980 | return 1; |
29639122 | 3981 | } |
a65bbe44 | 3982 | |
29639122 | 3983 | /* Test whether the PC points to the return instruction at the |
025bb325 | 3984 | end of a function. */ |
65596487 | 3985 | |
29639122 | 3986 | static int |
e17a4113 | 3987 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 3988 | { |
6321c22a MR |
3989 | ULONGEST insn; |
3990 | ULONGEST hint; | |
3991 | ||
3992 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
3993 | called for MIPS16 functions. And likewise microMIPS ones. */ |
3994 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 3995 | |
4cc0665f | 3996 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
3997 | hint = 0x7c0; |
3998 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 3999 | } |
c906108c | 4000 | |
c906108c | 4001 | |
29639122 JB |
4002 | /* This fencepost looks highly suspicious to me. Removing it also |
4003 | seems suspicious as it could affect remote debugging across serial | |
4004 | lines. */ | |
c906108c | 4005 | |
29639122 | 4006 | static CORE_ADDR |
74ed0bb4 | 4007 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4008 | { |
4009 | CORE_ADDR start_pc; | |
4010 | CORE_ADDR fence; | |
4011 | int instlen; | |
4012 | int seen_adjsp = 0; | |
d6b48e9c | 4013 | struct inferior *inf; |
65596487 | 4014 | |
74ed0bb4 | 4015 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4016 | start_pc = pc; |
4017 | fence = start_pc - heuristic_fence_post; | |
4018 | if (start_pc == 0) | |
4019 | return 0; | |
65596487 | 4020 | |
44096aee | 4021 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4022 | fence = VM_MIN_ADDRESS; |
65596487 | 4023 | |
4cc0665f | 4024 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4025 | |
d6b48e9c PA |
4026 | inf = current_inferior (); |
4027 | ||
025bb325 | 4028 | /* Search back for previous return. */ |
29639122 JB |
4029 | for (start_pc -= instlen;; start_pc -= instlen) |
4030 | if (start_pc < fence) | |
4031 | { | |
4032 | /* It's not clear to me why we reach this point when | |
4033 | stop_soon, but with this test, at least we | |
4034 | don't print out warnings for every child forked (eg, on | |
4035 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4036 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4037 | { |
4038 | static int blurb_printed = 0; | |
98b4dd94 | 4039 | |
5af949e3 UW |
4040 | warning (_("GDB can't find the start of the function at %s."), |
4041 | paddress (gdbarch, pc)); | |
29639122 JB |
4042 | |
4043 | if (!blurb_printed) | |
4044 | { | |
4045 | /* This actually happens frequently in embedded | |
4046 | development, when you first connect to a board | |
4047 | and your stack pointer and pc are nowhere in | |
4048 | particular. This message needs to give people | |
4049 | in that situation enough information to | |
4050 | determine that it's no big deal. */ | |
4051 | printf_filtered ("\n\ | |
5af949e3 | 4052 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4053 | and thus can't determine the size of that function's stack frame.\n\ |
4054 | This means that GDB may be unable to access that stack frame, or\n\ | |
4055 | the frames below it.\n\ | |
4056 | This problem is most likely caused by an invalid program counter or\n\ | |
4057 | stack pointer.\n\ | |
4058 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4059 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4060 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4061 | heuristic-fence-post' command.\n", |
4062 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4063 | blurb_printed = 1; |
4064 | } | |
4065 | } | |
4066 | ||
4067 | return 0; | |
4068 | } | |
4cc0665f | 4069 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4070 | { |
4071 | unsigned short inst; | |
4072 | ||
4073 | /* On MIPS16, any one of the following is likely to be the | |
4074 | start of a function: | |
193774b3 MR |
4075 | extend save |
4076 | save | |
29639122 JB |
4077 | entry |
4078 | addiu sp,-n | |
4079 | daddiu sp,-n | |
025bb325 | 4080 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4081 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4082 | if ((inst & 0xff80) == 0x6480) /* save */ |
4083 | { | |
4084 | if (start_pc - instlen >= fence) | |
4085 | { | |
4cc0665f MR |
4086 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4087 | start_pc - instlen, NULL); | |
193774b3 MR |
4088 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4089 | start_pc -= instlen; | |
4090 | } | |
4091 | break; | |
4092 | } | |
4093 | else if (((inst & 0xf81f) == 0xe809 | |
4094 | && (inst & 0x700) != 0x700) /* entry */ | |
4095 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4096 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4097 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4098 | break; |
4099 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4100 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4101 | seen_adjsp = 1; | |
4102 | else | |
4103 | seen_adjsp = 0; | |
4104 | } | |
4cc0665f MR |
4105 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4106 | { | |
4107 | ULONGEST insn; | |
4108 | int stop = 0; | |
4109 | long offset; | |
4110 | int dreg; | |
4111 | int sreg; | |
4112 | ||
4113 | /* On microMIPS, any one of the following is likely to be the | |
4114 | start of a function: | |
4115 | ADDIUSP -imm | |
4116 | (D)ADDIU $sp, -imm | |
4117 | LUI $gp, imm */ | |
4118 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4119 | switch (micromips_op (insn)) | |
4120 | { | |
4121 | case 0xc: /* ADDIU: bits 001100 */ | |
4122 | case 0x17: /* DADDIU: bits 010111 */ | |
4123 | sreg = b0s5_reg (insn); | |
4124 | dreg = b5s5_reg (insn); | |
4125 | insn <<= 16; | |
4126 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4127 | pc + MIPS_INSN16_SIZE, NULL); | |
4128 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4129 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4130 | /* (D)ADDIU $sp, imm */ | |
4131 | && offset < 0) | |
4132 | stop = 1; | |
4133 | break; | |
4134 | ||
4135 | case 0x10: /* POOL32I: bits 010000 */ | |
4136 | if (b5s5_op (insn) == 0xd | |
4137 | /* LUI: bits 010000 001101 */ | |
4138 | && b0s5_reg (insn >> 16) == 28) | |
4139 | /* LUI $gp, imm */ | |
4140 | stop = 1; | |
4141 | break; | |
4142 | ||
4143 | case 0x13: /* POOL16D: bits 010011 */ | |
4144 | if ((insn & 0x1) == 0x1) | |
4145 | /* ADDIUSP: bits 010011 1 */ | |
4146 | { | |
4147 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4148 | if (offset < 0) | |
4149 | /* ADDIUSP -imm */ | |
4150 | stop = 1; | |
4151 | } | |
4152 | else | |
4153 | /* ADDIUS5: bits 010011 0 */ | |
4154 | { | |
4155 | dreg = b5s5_reg (insn); | |
4156 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4157 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4158 | /* ADDIUS5 $sp, -imm */ | |
4159 | stop = 1; | |
4160 | } | |
4161 | break; | |
4162 | } | |
4163 | if (stop) | |
4164 | break; | |
4165 | } | |
e17a4113 | 4166 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4167 | { |
4c7d22cb | 4168 | /* Skip return and its delay slot. */ |
95ac2dcf | 4169 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4170 | break; |
4171 | } | |
4172 | ||
4173 | return start_pc; | |
c906108c SS |
4174 | } |
4175 | ||
6c0d6680 DJ |
4176 | struct mips_objfile_private |
4177 | { | |
4178 | bfd_size_type size; | |
4179 | char *contents; | |
4180 | }; | |
4181 | ||
f09ded24 AC |
4182 | /* According to the current ABI, should the type be passed in a |
4183 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4184 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4185 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4186 | arguments into integer registers. */ |
f09ded24 AC |
4187 | |
4188 | static int | |
74ed0bb4 MD |
4189 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4190 | struct type *arg_type) | |
f09ded24 AC |
4191 | { |
4192 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4193 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4194 | && (typecode == TYPE_CODE_STRUCT |
4195 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4196 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4197 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4198 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4199 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4200 | } |
4201 | ||
49e790b0 | 4202 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4203 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4204 | |
4205 | static int | |
4206 | mips_type_needs_double_align (struct type *type) | |
4207 | { | |
4208 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4209 | |
49e790b0 DJ |
4210 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4211 | return 1; | |
4212 | else if (typecode == TYPE_CODE_STRUCT) | |
4213 | { | |
4214 | if (TYPE_NFIELDS (type) < 1) | |
4215 | return 0; | |
4216 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4217 | } | |
4218 | else if (typecode == TYPE_CODE_UNION) | |
4219 | { | |
361d1df0 | 4220 | int i, n; |
49e790b0 DJ |
4221 | |
4222 | n = TYPE_NFIELDS (type); | |
4223 | for (i = 0; i < n; i++) | |
4224 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4225 | return 1; | |
4226 | return 0; | |
4227 | } | |
4228 | return 0; | |
4229 | } | |
4230 | ||
dc604539 AC |
4231 | /* Adjust the address downward (direction of stack growth) so that it |
4232 | is correctly aligned for a new stack frame. */ | |
4233 | static CORE_ADDR | |
4234 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4235 | { | |
5b03f266 | 4236 | return align_down (addr, 16); |
dc604539 AC |
4237 | } |
4238 | ||
8ae38c14 | 4239 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4240 | |
4241 | static CORE_ADDR | |
4242 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4243 | CORE_ADDR funaddr, struct value **args, | |
4244 | int nargs, struct type *value_type, | |
4245 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4246 | struct regcache *regcache) | |
4247 | { | |
2c76a0c7 | 4248 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4249 | CORE_ADDR nop_addr; |
4250 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4251 | |
4252 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4253 | bp_slot = sp - sizeof (nop_insn); |
4254 | ||
4255 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4256 | triggering an address error exception on processors that only | |
4257 | support microMIPS execution. */ | |
4258 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4259 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4260 | |
4261 | /* The breakpoint layer automatically adjusts the address of | |
4262 | breakpoints inserted in a branch delay slot. With enough | |
4263 | bad luck, the 4 bytes located just before our breakpoint | |
4264 | instruction could look like a branch instruction, and thus | |
4265 | trigger the adjustement, and break the function call entirely. | |
4266 | So, we reserve those 4 bytes and write a nop instruction | |
4267 | to prevent that from happening. */ | |
2e81047f | 4268 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4269 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4270 | sp = mips_frame_align (gdbarch, nop_addr); | |
4271 | ||
4272 | /* Inferior resumes at the function entry point. */ | |
4273 | *real_pc = funaddr; | |
4274 | ||
4275 | return sp; | |
4276 | } | |
4277 | ||
f7ab6ec6 | 4278 | static CORE_ADDR |
7d9b040b | 4279 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4280 | struct regcache *regcache, CORE_ADDR bp_addr, |
4281 | int nargs, struct value **args, CORE_ADDR sp, | |
4282 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4283 | { |
4284 | int argreg; | |
4285 | int float_argreg; | |
4286 | int argnum; | |
4287 | int len = 0; | |
4288 | int stack_offset = 0; | |
e17a4113 | 4289 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4290 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 4291 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 4292 | |
25ab4790 AC |
4293 | /* For shared libraries, "t9" needs to point at the function |
4294 | address. */ | |
4c7d22cb | 4295 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4296 | |
4297 | /* Set the return address register to point to the entry point of | |
4298 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4299 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4300 | |
c906108c | 4301 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4302 | are properly aligned. The stack has to be at least 64-bit |
4303 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4304 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4305 | aligned, so we round to this widest known alignment. */ | |
4306 | ||
5b03f266 AC |
4307 | sp = align_down (sp, 16); |
4308 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4309 | |
46e0f506 | 4310 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4311 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4312 | passed in registers, but that's OK. */ |
c906108c | 4313 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 4314 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 4315 | sp -= align_up (len, 16); |
c906108c | 4316 | |
9ace0497 | 4317 | if (mips_debug) |
6d82d43b | 4318 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4319 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4320 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4321 | |
c906108c | 4322 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4323 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4324 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4325 | |
46e0f506 | 4326 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4327 | if (struct_return) |
9ace0497 AC |
4328 | { |
4329 | if (mips_debug) | |
4330 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4331 | "mips_eabi_push_dummy_call: " |
4332 | "struct_return reg=%d %s\n", | |
5af949e3 | 4333 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4334 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4335 | } |
c906108c SS |
4336 | |
4337 | /* Now load as many as possible of the first arguments into | |
4338 | registers, and push the rest onto the stack. Loop thru args | |
4339 | from first to last. */ | |
4340 | for (argnum = 0; argnum < nargs; argnum++) | |
4341 | { | |
47a35522 MK |
4342 | const gdb_byte *val; |
4343 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 4344 | struct value *arg = args[argnum]; |
4991999e | 4345 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4346 | int len = TYPE_LENGTH (arg_type); |
4347 | enum type_code typecode = TYPE_CODE (arg_type); | |
4348 | ||
9ace0497 AC |
4349 | if (mips_debug) |
4350 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4351 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4352 | argnum + 1, len, (int) typecode); |
9ace0497 | 4353 | |
930bd0e0 KB |
4354 | /* Function pointer arguments to mips16 code need to be made into |
4355 | mips16 pointers. */ | |
4356 | if (typecode == TYPE_CODE_PTR | |
4357 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4358 | { | |
4359 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4360 | len, byte_order); | |
4cc0665f MR |
4361 | if (mips_pc_is_mips (addr)) |
4362 | val = value_contents (arg); | |
4363 | else | |
930bd0e0 KB |
4364 | { |
4365 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 4366 | make_compact_addr (addr)); |
930bd0e0 KB |
4367 | val = valbuf; |
4368 | } | |
930bd0e0 | 4369 | } |
c906108c | 4370 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4371 | reference. */ |
930bd0e0 | 4372 | else if (len > regsize |
9ace0497 | 4373 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4374 | { |
e17a4113 UW |
4375 | store_unsigned_integer (valbuf, regsize, byte_order, |
4376 | value_address (arg)); | |
c906108c | 4377 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 4378 | len = regsize; |
c906108c | 4379 | val = valbuf; |
9ace0497 AC |
4380 | if (mips_debug) |
4381 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4382 | } |
4383 | else | |
47a35522 | 4384 | val = value_contents (arg); |
c906108c SS |
4385 | |
4386 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4387 | even-numbered floating point register. Round the FP register |
4388 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4389 | left. Non MIPS_EABI targets also pass the FP in the integer |
4390 | registers so also round up normal registers. */ | |
74ed0bb4 | 4391 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4392 | { |
4393 | if ((float_argreg & 1)) | |
4394 | float_argreg++; | |
4395 | } | |
c906108c SS |
4396 | |
4397 | /* Floating point arguments passed in registers have to be | |
4398 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4399 | are passed in register pairs; the even register gets |
4400 | the low word, and the odd register gets the high word. | |
4401 | On non-EABI processors, the first two floating point arguments are | |
4402 | also copied to general registers, because MIPS16 functions | |
4403 | don't use float registers for arguments. This duplication of | |
4404 | arguments in general registers can't hurt non-MIPS16 functions | |
4405 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4406 | /* MIPS_EABI squeezes a struct that contains a single floating |
4407 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4408 | stack. */ |
74ed0bb4 MD |
4409 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4410 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4411 | { |
6da397e0 KB |
4412 | /* EABI32 will pass doubles in consecutive registers, even on |
4413 | 64-bit cores. At one time, we used to check the size of | |
4414 | `float_argreg' to determine whether or not to pass doubles | |
4415 | in consecutive registers, but this is not sufficient for | |
4416 | making the ABI determination. */ | |
4417 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4418 | { |
72a155b4 | 4419 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4420 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4421 | long regval; |
c906108c SS |
4422 | |
4423 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4424 | regval = extract_signed_integer (val + low_offset, |
4425 | 4, byte_order); | |
9ace0497 | 4426 | if (mips_debug) |
acdb74a0 | 4427 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4428 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4429 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4430 | |
4431 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4432 | regval = extract_signed_integer (val + 4 - low_offset, |
4433 | 4, byte_order); | |
9ace0497 | 4434 | if (mips_debug) |
acdb74a0 | 4435 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4436 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4437 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4438 | } |
4439 | else | |
4440 | { | |
4441 | /* This is a floating point value that fits entirely | |
4442 | in a single register. */ | |
53a5351d | 4443 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4444 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4445 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4446 | if (mips_debug) |
acdb74a0 | 4447 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4448 | float_argreg, phex (regval, len)); |
a8852dc5 | 4449 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4450 | } |
4451 | } | |
4452 | else | |
4453 | { | |
4454 | /* Copy the argument to general registers or the stack in | |
4455 | register-sized pieces. Large arguments are split between | |
4456 | registers and stack. */ | |
1a69e1e4 DJ |
4457 | /* Note: structs whose size is not a multiple of regsize |
4458 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4459 | them in registers where gcc sometimes puts them on the |
4460 | stack. For maximum compatibility, we will put them in | |
4461 | both places. */ | |
1a69e1e4 | 4462 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 4463 | |
f09ded24 | 4464 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4465 | register are only written to memory. */ |
c906108c SS |
4466 | while (len > 0) |
4467 | { | |
ebafbe83 | 4468 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4469 | int stack_used_p = 0; |
1a69e1e4 | 4470 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 4471 | |
acdb74a0 AC |
4472 | if (mips_debug) |
4473 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4474 | partial_len); | |
4475 | ||
566f0f7a | 4476 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4477 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4478 | || odd_sized_struct |
74ed0bb4 | 4479 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4480 | { |
c906108c | 4481 | /* Should shorter than int integer values be |
025bb325 | 4482 | promoted to int before being stored? */ |
c906108c | 4483 | int longword_offset = 0; |
9ace0497 | 4484 | CORE_ADDR addr; |
566f0f7a | 4485 | stack_used_p = 1; |
72a155b4 | 4486 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4487 | { |
1a69e1e4 | 4488 | if (regsize == 8 |
480d3dd2 AC |
4489 | && (typecode == TYPE_CODE_INT |
4490 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4491 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 4492 | longword_offset = regsize - len; |
480d3dd2 AC |
4493 | else if ((typecode == TYPE_CODE_STRUCT |
4494 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
4495 | && TYPE_LENGTH (arg_type) < regsize) |
4496 | longword_offset = regsize - len; | |
7a292a7a | 4497 | } |
c5aa993b | 4498 | |
9ace0497 AC |
4499 | if (mips_debug) |
4500 | { | |
5af949e3 UW |
4501 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4502 | paddress (gdbarch, stack_offset)); | |
4503 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4504 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4505 | } |
361d1df0 | 4506 | |
9ace0497 AC |
4507 | addr = sp + stack_offset + longword_offset; |
4508 | ||
4509 | if (mips_debug) | |
4510 | { | |
4511 | int i; | |
5af949e3 UW |
4512 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4513 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4514 | for (i = 0; i < partial_len; i++) |
4515 | { | |
6d82d43b | 4516 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4517 | val[i] & 0xff); |
9ace0497 AC |
4518 | } |
4519 | } | |
4520 | write_memory (addr, val, partial_len); | |
c906108c SS |
4521 | } |
4522 | ||
f09ded24 AC |
4523 | /* Note!!! This is NOT an else clause. Odd sized |
4524 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4525 | arguments will not. */ |
566f0f7a | 4526 | /* Write this portion of the argument to a general |
6d82d43b | 4527 | purpose register. */ |
74ed0bb4 MD |
4528 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4529 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4530 | { |
6d82d43b | 4531 | LONGEST regval = |
a8852dc5 | 4532 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4533 | |
9ace0497 | 4534 | if (mips_debug) |
acdb74a0 | 4535 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4536 | argreg, |
1a69e1e4 | 4537 | phex (regval, regsize)); |
a8852dc5 | 4538 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4539 | argreg++; |
c906108c | 4540 | } |
c5aa993b | 4541 | |
c906108c SS |
4542 | len -= partial_len; |
4543 | val += partial_len; | |
4544 | ||
b021a221 MS |
4545 | /* Compute the offset into the stack at which we will |
4546 | copy the next parameter. | |
566f0f7a | 4547 | |
566f0f7a | 4548 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4549 | only needs to be adjusted when it has been used. */ |
c906108c | 4550 | |
46e0f506 | 4551 | if (stack_used_p) |
1a69e1e4 | 4552 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
4553 | } |
4554 | } | |
9ace0497 AC |
4555 | if (mips_debug) |
4556 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4557 | } |
4558 | ||
f10683bb | 4559 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4560 | |
0f71a2f6 JM |
4561 | /* Return adjusted stack pointer. */ |
4562 | return sp; | |
4563 | } | |
4564 | ||
a1f5b845 | 4565 | /* Determine the return value convention being used. */ |
6d82d43b | 4566 | |
9c8fdbfa | 4567 | static enum return_value_convention |
6a3a010b | 4568 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4569 | struct type *type, struct regcache *regcache, |
47a35522 | 4570 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4571 | { |
609ba780 JM |
4572 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4573 | int fp_return_type = 0; | |
4574 | int offset, regnum, xfer; | |
4575 | ||
9c8fdbfa AC |
4576 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4577 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4578 | |
4579 | /* Floating point type? */ | |
4580 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4581 | { | |
4582 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4583 | fp_return_type = 1; | |
4584 | /* Structs with a single field of float type | |
4585 | are returned in a floating point register. */ | |
4586 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4587 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4588 | && TYPE_NFIELDS (type) == 1) | |
4589 | { | |
4590 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4591 | ||
4592 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4593 | fp_return_type = 1; | |
4594 | } | |
4595 | } | |
4596 | ||
4597 | if (fp_return_type) | |
4598 | { | |
4599 | /* A floating-point value belongs in the least significant part | |
4600 | of FP0/FP1. */ | |
4601 | if (mips_debug) | |
4602 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4603 | regnum = mips_regnum (gdbarch)->fp0; | |
4604 | } | |
4605 | else | |
4606 | { | |
4607 | /* An integer value goes in V0/V1. */ | |
4608 | if (mips_debug) | |
4609 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4610 | regnum = MIPS_V0_REGNUM; | |
4611 | } | |
4612 | for (offset = 0; | |
4613 | offset < TYPE_LENGTH (type); | |
4614 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4615 | { | |
4616 | xfer = mips_abi_regsize (gdbarch); | |
4617 | if (offset + xfer > TYPE_LENGTH (type)) | |
4618 | xfer = TYPE_LENGTH (type) - offset; | |
4619 | mips_xfer_register (gdbarch, regcache, | |
4620 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4621 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4622 | offset); | |
4623 | } | |
4624 | ||
9c8fdbfa | 4625 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4626 | } |
4627 | ||
6d82d43b AC |
4628 | |
4629 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4630 | |
8d26208a DJ |
4631 | /* Search for a naturally aligned double at OFFSET inside a struct |
4632 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4633 | registers. */ | |
4634 | ||
4635 | static int | |
74ed0bb4 MD |
4636 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4637 | int offset) | |
8d26208a DJ |
4638 | { |
4639 | int i; | |
4640 | ||
4641 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4642 | return 0; | |
4643 | ||
74ed0bb4 | 4644 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4645 | return 0; |
4646 | ||
4647 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4648 | return 0; | |
4649 | ||
4650 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4651 | { | |
4652 | int pos; | |
4653 | struct type *field_type; | |
4654 | ||
4655 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4656 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4657 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4658 | continue; | |
4659 | ||
4660 | /* If we have gone past the offset, there is no double to pass. */ | |
4661 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4662 | if (pos > offset) | |
4663 | return 0; | |
4664 | ||
4665 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4666 | ||
4667 | /* If this field is entirely before the requested offset, go | |
4668 | on to the next one. */ | |
4669 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4670 | continue; | |
4671 | ||
4672 | /* If this is our special aligned double, we can stop. */ | |
4673 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4674 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4675 | return 1; | |
4676 | ||
4677 | /* This field starts at or before the requested offset, and | |
4678 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4679 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4680 | } |
4681 | ||
4682 | return 0; | |
4683 | } | |
4684 | ||
f7ab6ec6 | 4685 | static CORE_ADDR |
7d9b040b | 4686 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4687 | struct regcache *regcache, CORE_ADDR bp_addr, |
4688 | int nargs, struct value **args, CORE_ADDR sp, | |
4689 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4690 | { |
4691 | int argreg; | |
4692 | int float_argreg; | |
4693 | int argnum; | |
4694 | int len = 0; | |
4695 | int stack_offset = 0; | |
e17a4113 | 4696 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4697 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4698 | |
25ab4790 AC |
4699 | /* For shared libraries, "t9" needs to point at the function |
4700 | address. */ | |
4c7d22cb | 4701 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4702 | |
4703 | /* Set the return address register to point to the entry point of | |
4704 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4705 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4706 | |
cb3d25d1 MS |
4707 | /* First ensure that the stack and structure return address (if any) |
4708 | are properly aligned. The stack has to be at least 64-bit | |
4709 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4710 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4711 | aligned, so we round to this widest known alignment. */ | |
4712 | ||
5b03f266 AC |
4713 | sp = align_down (sp, 16); |
4714 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4715 | |
4716 | /* Now make space on the stack for the args. */ | |
4717 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4718 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4719 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4720 | |
4721 | if (mips_debug) | |
6d82d43b | 4722 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4723 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4724 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4725 | |
4726 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4727 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4728 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4729 | |
46e0f506 | 4730 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4731 | if (struct_return) |
4732 | { | |
4733 | if (mips_debug) | |
4734 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4735 | "mips_n32n64_push_dummy_call: " |
4736 | "struct_return reg=%d %s\n", | |
5af949e3 | 4737 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4738 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4739 | } |
4740 | ||
4741 | /* Now load as many as possible of the first arguments into | |
4742 | registers, and push the rest onto the stack. Loop thru args | |
4743 | from first to last. */ | |
4744 | for (argnum = 0; argnum < nargs; argnum++) | |
4745 | { | |
47a35522 | 4746 | const gdb_byte *val; |
cb3d25d1 | 4747 | struct value *arg = args[argnum]; |
4991999e | 4748 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4749 | int len = TYPE_LENGTH (arg_type); |
4750 | enum type_code typecode = TYPE_CODE (arg_type); | |
4751 | ||
4752 | if (mips_debug) | |
4753 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4754 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4755 | argnum + 1, len, (int) typecode); |
4756 | ||
47a35522 | 4757 | val = value_contents (arg); |
cb3d25d1 | 4758 | |
5b68030f JM |
4759 | /* A 128-bit long double value requires an even-odd pair of |
4760 | floating-point registers. */ | |
4761 | if (len == 16 | |
4762 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4763 | && (float_argreg & 1)) | |
4764 | { | |
4765 | float_argreg++; | |
4766 | argreg++; | |
4767 | } | |
4768 | ||
74ed0bb4 MD |
4769 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4770 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4771 | { |
4772 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4773 | in a single register or a pair of registers. */ |
4774 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4775 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4776 | if (mips_debug) |
4777 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4778 | float_argreg, phex (regval, reglen)); |
8d26208a | 4779 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4780 | |
4781 | if (mips_debug) | |
4782 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4783 | argreg, phex (regval, reglen)); |
9c9acae0 | 4784 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4785 | float_argreg++; |
4786 | argreg++; | |
5b68030f JM |
4787 | if (len == 16) |
4788 | { | |
e17a4113 UW |
4789 | regval = extract_unsigned_integer (val + reglen, |
4790 | reglen, byte_order); | |
5b68030f JM |
4791 | if (mips_debug) |
4792 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4793 | float_argreg, phex (regval, reglen)); | |
4794 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4795 | ||
4796 | if (mips_debug) | |
4797 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4798 | argreg, phex (regval, reglen)); | |
4799 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4800 | float_argreg++; | |
4801 | argreg++; | |
4802 | } | |
cb3d25d1 MS |
4803 | } |
4804 | else | |
4805 | { | |
4806 | /* Copy the argument to general registers or the stack in | |
4807 | register-sized pieces. Large arguments are split between | |
4808 | registers and stack. */ | |
ab2e1992 MR |
4809 | /* For N32/N64, structs, unions, or other composite types are |
4810 | treated as a sequence of doublewords, and are passed in integer | |
4811 | or floating point registers as though they were simple scalar | |
4812 | parameters to the extent that they fit, with any excess on the | |
4813 | stack packed according to the normal memory layout of the | |
4814 | object. | |
4815 | The caller does not reserve space for the register arguments; | |
4816 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4817 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4818 | register are only written to memory. */ |
cb3d25d1 MS |
4819 | while (len > 0) |
4820 | { | |
ad018eee | 4821 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4822 | int stack_used_p = 0; |
1a69e1e4 | 4823 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4824 | |
4825 | if (mips_debug) | |
4826 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4827 | partial_len); | |
4828 | ||
74ed0bb4 MD |
4829 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
4830 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 4831 | |
cb3d25d1 | 4832 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4833 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
4834 | { |
4835 | /* Should shorter than int integer values be | |
025bb325 | 4836 | promoted to int before being stored? */ |
cb3d25d1 MS |
4837 | int longword_offset = 0; |
4838 | CORE_ADDR addr; | |
4839 | stack_used_p = 1; | |
72a155b4 | 4840 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 4841 | { |
1a69e1e4 | 4842 | if ((typecode == TYPE_CODE_INT |
5b68030f | 4843 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
4844 | && len <= 4) |
4845 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
4846 | } |
4847 | ||
4848 | if (mips_debug) | |
4849 | { | |
5af949e3 UW |
4850 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4851 | paddress (gdbarch, stack_offset)); | |
4852 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4853 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
4854 | } |
4855 | ||
4856 | addr = sp + stack_offset + longword_offset; | |
4857 | ||
4858 | if (mips_debug) | |
4859 | { | |
4860 | int i; | |
5af949e3 UW |
4861 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4862 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
4863 | for (i = 0; i < partial_len; i++) |
4864 | { | |
6d82d43b | 4865 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
4866 | val[i] & 0xff); |
4867 | } | |
4868 | } | |
4869 | write_memory (addr, val, partial_len); | |
4870 | } | |
4871 | ||
4872 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 4873 | structs may go thru BOTH paths. */ |
cb3d25d1 | 4874 | /* Write this portion of the argument to a general |
6d82d43b | 4875 | purpose register. */ |
74ed0bb4 | 4876 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 4877 | { |
5863b5d5 MR |
4878 | LONGEST regval; |
4879 | ||
4880 | /* Sign extend pointers, 32-bit integers and signed | |
4881 | 16-bit and 8-bit integers; everything else is taken | |
4882 | as is. */ | |
4883 | ||
4884 | if ((partial_len == 4 | |
4885 | && (typecode == TYPE_CODE_PTR | |
4886 | || typecode == TYPE_CODE_INT)) | |
4887 | || (partial_len < 4 | |
4888 | && typecode == TYPE_CODE_INT | |
4889 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
4890 | regval = extract_signed_integer (val, partial_len, |
4891 | byte_order); | |
5863b5d5 | 4892 | else |
e17a4113 UW |
4893 | regval = extract_unsigned_integer (val, partial_len, |
4894 | byte_order); | |
cb3d25d1 MS |
4895 | |
4896 | /* A non-floating-point argument being passed in a | |
4897 | general register. If a struct or union, and if | |
4898 | the remaining length is smaller than the register | |
4899 | size, we have to adjust the register value on | |
4900 | big endian targets. | |
4901 | ||
4902 | It does not seem to be necessary to do the | |
1a69e1e4 | 4903 | same for integral types. */ |
cb3d25d1 | 4904 | |
72a155b4 | 4905 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4906 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4907 | && (typecode == TYPE_CODE_STRUCT |
4908 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4909 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4910 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
4911 | |
4912 | if (mips_debug) | |
4913 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4914 | argreg, | |
1a69e1e4 | 4915 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4916 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 4917 | |
74ed0bb4 | 4918 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
4919 | TYPE_LENGTH (arg_type) - len)) |
4920 | { | |
4921 | if (mips_debug) | |
4922 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
4923 | float_argreg, | |
4924 | phex (regval, MIPS64_REGSIZE)); | |
4925 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
4926 | regval); | |
4927 | } | |
4928 | ||
4929 | float_argreg++; | |
cb3d25d1 MS |
4930 | argreg++; |
4931 | } | |
4932 | ||
4933 | len -= partial_len; | |
4934 | val += partial_len; | |
4935 | ||
b021a221 MS |
4936 | /* Compute the offset into the stack at which we will |
4937 | copy the next parameter. | |
cb3d25d1 MS |
4938 | |
4939 | In N32 (N64?), the stack_offset only needs to be | |
4940 | adjusted when it has been used. */ | |
4941 | ||
4942 | if (stack_used_p) | |
1a69e1e4 | 4943 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
4944 | } |
4945 | } | |
4946 | if (mips_debug) | |
4947 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4948 | } | |
4949 | ||
f10683bb | 4950 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4951 | |
cb3d25d1 MS |
4952 | /* Return adjusted stack pointer. */ |
4953 | return sp; | |
4954 | } | |
4955 | ||
6d82d43b | 4956 | static enum return_value_convention |
6a3a010b | 4957 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 4958 | struct type *type, struct regcache *regcache, |
47a35522 | 4959 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 4960 | { |
72a155b4 | 4961 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
4962 | |
4963 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
4964 | ||
4965 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
4966 | if needed), as appropriate for the type. Composite results (struct, | |
4967 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
4968 | following rules: | |
4969 | ||
4970 | * A struct with only one or two floating point fields is returned in $f0 | |
4971 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
4972 | case. | |
4973 | ||
f08877ba | 4974 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
4975 | $2 (first 64 bits) and $3 (remainder, if necessary). |
4976 | ||
4977 | * Larger composite results are handled by converting the function to a | |
4978 | procedure with an implicit first parameter, which is a pointer to an area | |
4979 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
4980 | that all composite results be handled by conversion to implicit first | |
4981 | parameters. The MIPS/SGI Fortran implementation has always made a | |
4982 | specific exception to return COMPLEX results in the floating point | |
4983 | registers.] */ | |
4984 | ||
f08877ba | 4985 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 4986 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
4987 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4988 | && TYPE_LENGTH (type) == 16 | |
4989 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4990 | { | |
4991 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
4992 | two registers are used in the same as memory order, so the | |
4993 | eight bytes with the lower memory address are in $f0. */ | |
4994 | if (mips_debug) | |
4995 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 4996 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4997 | (gdbarch_num_regs (gdbarch) |
4998 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 4999 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5000 | readbuf, writebuf, 0); |
ba32f989 | 5001 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5002 | (gdbarch_num_regs (gdbarch) |
5003 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 5004 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5005 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
5006 | writebuf ? writebuf + 8 : writebuf, 0); |
5007 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5008 | } | |
6d82d43b AC |
5009 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
5010 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5011 | { | |
59aa1faa | 5012 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
5013 | if (mips_debug) |
5014 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 5015 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5016 | (gdbarch_num_regs (gdbarch) |
5017 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 5018 | TYPE_LENGTH (type), |
72a155b4 | 5019 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5020 | readbuf, writebuf, 0); |
6d82d43b AC |
5021 | return RETURN_VALUE_REGISTER_CONVENTION; |
5022 | } | |
5023 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5024 | && TYPE_NFIELDS (type) <= 2 | |
5025 | && TYPE_NFIELDS (type) >= 1 | |
5026 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 5027 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
5028 | == TYPE_CODE_FLT)) |
5029 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 5030 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 5031 | == TYPE_CODE_FLT) |
b18bb924 | 5032 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 5033 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5034 | { |
5035 | /* A struct that contains one or two floats. Each value is part | |
5036 | in the least significant part of their floating point | |
5b68030f | 5037 | register (or GPR, for soft float). */ |
6d82d43b AC |
5038 | int regnum; |
5039 | int field; | |
5b68030f JM |
5040 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5041 | ? mips_regnum (gdbarch)->fp0 | |
5042 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
5043 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5044 | { | |
5045 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5046 | / TARGET_CHAR_BIT); | |
5047 | if (mips_debug) | |
5048 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5049 | offset); | |
5b68030f JM |
5050 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5051 | { | |
5052 | /* A 16-byte long double field goes in two consecutive | |
5053 | registers. */ | |
5054 | mips_xfer_register (gdbarch, regcache, | |
5055 | gdbarch_num_regs (gdbarch) + regnum, | |
5056 | 8, | |
5057 | gdbarch_byte_order (gdbarch), | |
5058 | readbuf, writebuf, offset); | |
5059 | mips_xfer_register (gdbarch, regcache, | |
5060 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5061 | 8, | |
5062 | gdbarch_byte_order (gdbarch), | |
5063 | readbuf, writebuf, offset + 8); | |
5064 | } | |
5065 | else | |
5066 | mips_xfer_register (gdbarch, regcache, | |
5067 | gdbarch_num_regs (gdbarch) + regnum, | |
5068 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5069 | gdbarch_byte_order (gdbarch), | |
5070 | readbuf, writebuf, offset); | |
6d82d43b AC |
5071 | } |
5072 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5073 | } | |
5074 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5075 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5076 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5077 | { |
f08877ba | 5078 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5079 | regardless of the byte order. I.e. DO NOT USE |
5080 | mips_xfer_lower. */ | |
5081 | int offset; | |
5082 | int regnum; | |
4c7d22cb | 5083 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5084 | offset < TYPE_LENGTH (type); |
72a155b4 | 5085 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5086 | { |
72a155b4 | 5087 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5088 | if (offset + xfer > TYPE_LENGTH (type)) |
5089 | xfer = TYPE_LENGTH (type) - offset; | |
5090 | if (mips_debug) | |
5091 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5092 | offset, xfer, regnum); | |
ba32f989 DJ |
5093 | mips_xfer_register (gdbarch, regcache, |
5094 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5095 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5096 | offset); | |
6d82d43b AC |
5097 | } |
5098 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5099 | } | |
5100 | else | |
5101 | { | |
5102 | /* A scalar extract each part but least-significant-byte | |
5103 | justified. */ | |
5104 | int offset; | |
5105 | int regnum; | |
4c7d22cb | 5106 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5107 | offset < TYPE_LENGTH (type); |
72a155b4 | 5108 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5109 | { |
72a155b4 | 5110 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5111 | if (offset + xfer > TYPE_LENGTH (type)) |
5112 | xfer = TYPE_LENGTH (type) - offset; | |
5113 | if (mips_debug) | |
5114 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5115 | offset, xfer, regnum); | |
ba32f989 DJ |
5116 | mips_xfer_register (gdbarch, regcache, |
5117 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5118 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5119 | readbuf, writebuf, offset); |
6d82d43b AC |
5120 | } |
5121 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5122 | } | |
5123 | } | |
5124 | ||
6a3a010b MR |
5125 | /* Which registers to use for passing floating-point values between |
5126 | function calls, one of floating-point, general and both kinds of | |
5127 | registers. O32 and O64 use different register kinds for standard | |
5128 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5129 | not know what kind of code is being used (e.g. no debug information) | |
5130 | easier we sometimes use both kinds. */ | |
5131 | ||
5132 | enum mips_fval_reg | |
5133 | { | |
5134 | mips_fval_fpr, | |
5135 | mips_fval_gpr, | |
5136 | mips_fval_both | |
5137 | }; | |
5138 | ||
6d82d43b AC |
5139 | /* O32 ABI stuff. */ |
5140 | ||
5141 | static CORE_ADDR | |
7d9b040b | 5142 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5143 | struct regcache *regcache, CORE_ADDR bp_addr, |
5144 | int nargs, struct value **args, CORE_ADDR sp, | |
5145 | int struct_return, CORE_ADDR struct_addr) | |
5146 | { | |
5147 | int argreg; | |
5148 | int float_argreg; | |
5149 | int argnum; | |
5150 | int len = 0; | |
5151 | int stack_offset = 0; | |
e17a4113 | 5152 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5153 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5154 | |
5155 | /* For shared libraries, "t9" needs to point at the function | |
5156 | address. */ | |
4c7d22cb | 5157 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5158 | |
5159 | /* Set the return address register to point to the entry point of | |
5160 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5161 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5162 | |
5163 | /* First ensure that the stack and structure return address (if any) | |
5164 | are properly aligned. The stack has to be at least 64-bit | |
5165 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5166 | aligned. For n32 and n64, stack frames need to be 128-bit |
5167 | aligned, so we round to this widest known alignment. */ | |
5168 | ||
5b03f266 AC |
5169 | sp = align_down (sp, 16); |
5170 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5171 | |
5172 | /* Now make space on the stack for the args. */ | |
5173 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5174 | { |
5175 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 MR |
5176 | |
5177 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5178 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5179 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5180 | /* Allocate space on the stack. */ |
354ecfd5 | 5181 | len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); |
968b5391 | 5182 | } |
5b03f266 | 5183 | sp -= align_up (len, 16); |
ebafbe83 MS |
5184 | |
5185 | if (mips_debug) | |
6d82d43b | 5186 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5187 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5188 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5189 | |
5190 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5191 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5192 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5193 | |
bcb0cc15 | 5194 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5195 | if (struct_return) |
5196 | { | |
5197 | if (mips_debug) | |
5198 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5199 | "mips_o32_push_dummy_call: " |
5200 | "struct_return reg=%d %s\n", | |
5af949e3 | 5201 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5202 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5203 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5204 | } |
5205 | ||
5206 | /* Now load as many as possible of the first arguments into | |
5207 | registers, and push the rest onto the stack. Loop thru args | |
5208 | from first to last. */ | |
5209 | for (argnum = 0; argnum < nargs; argnum++) | |
5210 | { | |
47a35522 | 5211 | const gdb_byte *val; |
ebafbe83 | 5212 | struct value *arg = args[argnum]; |
4991999e | 5213 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5214 | int len = TYPE_LENGTH (arg_type); |
5215 | enum type_code typecode = TYPE_CODE (arg_type); | |
5216 | ||
5217 | if (mips_debug) | |
5218 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5219 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5220 | argnum + 1, len, (int) typecode); |
5221 | ||
47a35522 | 5222 | val = value_contents (arg); |
46cac009 AC |
5223 | |
5224 | /* 32-bit ABIs always start floating point arguments in an | |
5225 | even-numbered floating point register. Round the FP register | |
5226 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5227 | left. O32 targets also pass the FP in the integer registers |
5228 | so also round up normal registers. */ | |
74ed0bb4 | 5229 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5230 | { |
5231 | if ((float_argreg & 1)) | |
5232 | float_argreg++; | |
5233 | } | |
5234 | ||
5235 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5236 | treated specially. On 32-bit architectures, doubles are |
5237 | passed in register pairs; the even FP register gets the | |
5238 | low word, and the odd FP register gets the high word. | |
5239 | On O32, the first two floating point arguments are also | |
5240 | copied to general registers, following their memory order, | |
5241 | because MIPS16 functions don't use float registers for | |
5242 | arguments. This duplication of arguments in general | |
5243 | registers can't hurt non-MIPS16 functions, because those | |
5244 | registers are normally skipped. */ | |
46cac009 | 5245 | |
74ed0bb4 MD |
5246 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5247 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5248 | { |
8b07f6d8 | 5249 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5250 | { |
6a3a010b MR |
5251 | int freg_offset = gdbarch_byte_order (gdbarch) |
5252 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5253 | unsigned long regval; |
5254 | ||
6a3a010b MR |
5255 | /* First word. */ |
5256 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5257 | if (mips_debug) |
5258 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5259 | float_argreg + freg_offset, |
5260 | phex (regval, 4)); | |
025bb325 | 5261 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5262 | float_argreg++ + freg_offset, |
5263 | regval); | |
46cac009 AC |
5264 | if (mips_debug) |
5265 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5266 | argreg, phex (regval, 4)); | |
9c9acae0 | 5267 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5268 | |
6a3a010b MR |
5269 | /* Second word. */ |
5270 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5271 | if (mips_debug) |
5272 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5273 | float_argreg - freg_offset, |
5274 | phex (regval, 4)); | |
025bb325 | 5275 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5276 | float_argreg++ - freg_offset, |
5277 | regval); | |
46cac009 AC |
5278 | if (mips_debug) |
5279 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5280 | argreg, phex (regval, 4)); | |
9c9acae0 | 5281 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5282 | } |
5283 | else | |
5284 | { | |
5285 | /* This is a floating point value that fits entirely | |
5286 | in a single register. */ | |
5287 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5288 | above to ensure that it is even register aligned. */ |
e17a4113 | 5289 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5290 | if (mips_debug) |
5291 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5292 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5293 | regcache_cooked_write_unsigned (regcache, |
5294 | float_argreg++, regval); | |
5b68030f JM |
5295 | /* Although two FP registers are reserved for each |
5296 | argument, only one corresponding integer register is | |
5297 | reserved. */ | |
46cac009 AC |
5298 | if (mips_debug) |
5299 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5300 | argreg, phex (regval, len)); | |
5b68030f | 5301 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5302 | } |
5303 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5304 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5305 | } |
5306 | else | |
5307 | { | |
5308 | /* Copy the argument to general registers or the stack in | |
5309 | register-sized pieces. Large arguments are split between | |
5310 | registers and stack. */ | |
1a69e1e4 DJ |
5311 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5312 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5313 | them in registers where gcc sometimes puts them on the |
5314 | stack. For maximum compatibility, we will put them in | |
5315 | both places. */ | |
1a69e1e4 DJ |
5316 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5317 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5318 | /* Structures should be aligned to eight bytes (even arg registers) |
5319 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5320 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5321 | { |
5322 | if ((argreg & 1)) | |
968b5391 MR |
5323 | { |
5324 | argreg++; | |
1a69e1e4 | 5325 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5326 | } |
46cac009 | 5327 | } |
46cac009 AC |
5328 | while (len > 0) |
5329 | { | |
5330 | /* Remember if the argument was written to the stack. */ | |
5331 | int stack_used_p = 0; | |
1a69e1e4 | 5332 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5333 | |
5334 | if (mips_debug) | |
5335 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5336 | partial_len); | |
5337 | ||
5338 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5339 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5340 | || odd_sized_struct) |
46cac009 AC |
5341 | { |
5342 | /* Should shorter than int integer values be | |
025bb325 | 5343 | promoted to int before being stored? */ |
46cac009 AC |
5344 | int longword_offset = 0; |
5345 | CORE_ADDR addr; | |
5346 | stack_used_p = 1; | |
46cac009 AC |
5347 | |
5348 | if (mips_debug) | |
5349 | { | |
5af949e3 UW |
5350 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5351 | paddress (gdbarch, stack_offset)); | |
5352 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5353 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5354 | } |
5355 | ||
5356 | addr = sp + stack_offset + longword_offset; | |
5357 | ||
5358 | if (mips_debug) | |
5359 | { | |
5360 | int i; | |
5af949e3 UW |
5361 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5362 | paddress (gdbarch, addr)); | |
46cac009 AC |
5363 | for (i = 0; i < partial_len; i++) |
5364 | { | |
6d82d43b | 5365 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5366 | val[i] & 0xff); |
5367 | } | |
5368 | } | |
5369 | write_memory (addr, val, partial_len); | |
5370 | } | |
5371 | ||
5372 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5373 | structs may go thru BOTH paths. */ |
46cac009 | 5374 | /* Write this portion of the argument to a general |
6d82d43b | 5375 | purpose register. */ |
74ed0bb4 | 5376 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5377 | { |
e17a4113 UW |
5378 | LONGEST regval = extract_signed_integer (val, partial_len, |
5379 | byte_order); | |
4246e332 | 5380 | /* Value may need to be sign extended, because |
1b13c4f6 | 5381 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5382 | |
5383 | /* A non-floating-point argument being passed in a | |
5384 | general register. If a struct or union, and if | |
5385 | the remaining length is smaller than the register | |
5386 | size, we have to adjust the register value on | |
5387 | big endian targets. | |
5388 | ||
5389 | It does not seem to be necessary to do the | |
5390 | same for integral types. | |
5391 | ||
5392 | Also don't do this adjustment on O64 binaries. | |
5393 | ||
5394 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5395 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5396 | mips_abi_regsize(), generates a left shift |
5397 | as part of storing the argument in a register | |
5398 | (the left shift isn't generated when | |
1b13c4f6 | 5399 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5400 | it is quite possible that this is GCC |
5401 | contradicting the LE/O32 ABI, GDB has not been | |
5402 | adjusted to accommodate this. Either someone | |
5403 | needs to demonstrate that the LE/O32 ABI | |
5404 | specifies such a left shift OR this new ABI gets | |
5405 | identified as such and GDB gets tweaked | |
5406 | accordingly. */ | |
5407 | ||
72a155b4 | 5408 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5409 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5410 | && (typecode == TYPE_CODE_STRUCT |
5411 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5412 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5413 | * TARGET_CHAR_BIT); |
46cac009 AC |
5414 | |
5415 | if (mips_debug) | |
5416 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5417 | argreg, | |
1a69e1e4 | 5418 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5419 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5420 | argreg++; |
5421 | ||
5422 | /* Prevent subsequent floating point arguments from | |
5423 | being passed in floating point registers. */ | |
74ed0bb4 | 5424 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5425 | } |
5426 | ||
5427 | len -= partial_len; | |
5428 | val += partial_len; | |
5429 | ||
b021a221 MS |
5430 | /* Compute the offset into the stack at which we will |
5431 | copy the next parameter. | |
46cac009 | 5432 | |
6d82d43b AC |
5433 | In older ABIs, the caller reserved space for |
5434 | registers that contained arguments. This was loosely | |
5435 | refered to as their "home". Consequently, space is | |
5436 | always allocated. */ | |
46cac009 | 5437 | |
1a69e1e4 | 5438 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5439 | } |
5440 | } | |
5441 | if (mips_debug) | |
5442 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5443 | } | |
5444 | ||
f10683bb | 5445 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5446 | |
46cac009 AC |
5447 | /* Return adjusted stack pointer. */ |
5448 | return sp; | |
5449 | } | |
5450 | ||
6d82d43b | 5451 | static enum return_value_convention |
6a3a010b | 5452 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5453 | struct type *type, struct regcache *regcache, |
47a35522 | 5454 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5455 | { |
6a3a010b | 5456 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5457 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5458 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5459 | enum mips_fval_reg fval_reg; |
6d82d43b | 5460 | |
6a3a010b | 5461 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5462 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5463 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5464 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5465 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5466 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5467 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5468 | { | |
6a3a010b MR |
5469 | /* A single-precision floating-point value. If reading in or copying, |
5470 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5471 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5472 | and GPR2. We do not support reading in with no function known, if | |
5473 | this safety check ever triggers, then we'll have to try harder. */ | |
5474 | gdb_assert (function || !readbuf); | |
6d82d43b | 5475 | if (mips_debug) |
6a3a010b MR |
5476 | switch (fval_reg) |
5477 | { | |
5478 | case mips_fval_fpr: | |
5479 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5480 | break; | |
5481 | case mips_fval_gpr: | |
5482 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5483 | break; | |
5484 | case mips_fval_both: | |
5485 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5486 | break; | |
5487 | } | |
5488 | if (fval_reg != mips_fval_gpr) | |
5489 | mips_xfer_register (gdbarch, regcache, | |
5490 | (gdbarch_num_regs (gdbarch) | |
5491 | + mips_regnum (gdbarch)->fp0), | |
5492 | TYPE_LENGTH (type), | |
5493 | gdbarch_byte_order (gdbarch), | |
5494 | readbuf, writebuf, 0); | |
5495 | if (fval_reg != mips_fval_fpr) | |
5496 | mips_xfer_register (gdbarch, regcache, | |
5497 | gdbarch_num_regs (gdbarch) + 2, | |
5498 | TYPE_LENGTH (type), | |
5499 | gdbarch_byte_order (gdbarch), | |
5500 | readbuf, writebuf, 0); | |
6d82d43b AC |
5501 | return RETURN_VALUE_REGISTER_CONVENTION; |
5502 | } | |
5503 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5504 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5505 | { | |
6a3a010b MR |
5506 | /* A double-precision floating-point value. If reading in or copying, |
5507 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5508 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5509 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5510 | no function known, if this safety check ever triggers, then we'll | |
5511 | have to try harder. */ | |
5512 | gdb_assert (function || !readbuf); | |
6d82d43b | 5513 | if (mips_debug) |
6a3a010b MR |
5514 | switch (fval_reg) |
5515 | { | |
5516 | case mips_fval_fpr: | |
5517 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5518 | break; | |
5519 | case mips_fval_gpr: | |
5520 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5521 | break; | |
5522 | case mips_fval_both: | |
5523 | fprintf_unfiltered (gdb_stderr, | |
5524 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5525 | break; | |
5526 | } | |
5527 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5528 | { |
6a3a010b MR |
5529 | /* The most significant part goes in FP1, and the least significant |
5530 | in FP0. */ | |
5531 | switch (gdbarch_byte_order (gdbarch)) | |
5532 | { | |
5533 | case BFD_ENDIAN_LITTLE: | |
5534 | mips_xfer_register (gdbarch, regcache, | |
5535 | (gdbarch_num_regs (gdbarch) | |
5536 | + mips_regnum (gdbarch)->fp0 + 0), | |
5537 | 4, gdbarch_byte_order (gdbarch), | |
5538 | readbuf, writebuf, 0); | |
5539 | mips_xfer_register (gdbarch, regcache, | |
5540 | (gdbarch_num_regs (gdbarch) | |
5541 | + mips_regnum (gdbarch)->fp0 + 1), | |
5542 | 4, gdbarch_byte_order (gdbarch), | |
5543 | readbuf, writebuf, 4); | |
5544 | break; | |
5545 | case BFD_ENDIAN_BIG: | |
5546 | mips_xfer_register (gdbarch, regcache, | |
5547 | (gdbarch_num_regs (gdbarch) | |
5548 | + mips_regnum (gdbarch)->fp0 + 1), | |
5549 | 4, gdbarch_byte_order (gdbarch), | |
5550 | readbuf, writebuf, 0); | |
5551 | mips_xfer_register (gdbarch, regcache, | |
5552 | (gdbarch_num_regs (gdbarch) | |
5553 | + mips_regnum (gdbarch)->fp0 + 0), | |
5554 | 4, gdbarch_byte_order (gdbarch), | |
5555 | readbuf, writebuf, 4); | |
5556 | break; | |
5557 | default: | |
5558 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5559 | } | |
5560 | } | |
5561 | if (fval_reg != mips_fval_fpr) | |
5562 | { | |
5563 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5564 | following these registers' memory order. */ | |
ba32f989 | 5565 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5566 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5567 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5568 | readbuf, writebuf, 0); |
ba32f989 | 5569 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5570 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5571 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5572 | readbuf, writebuf, 4); |
6d82d43b AC |
5573 | } |
5574 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5575 | } | |
5576 | #if 0 | |
5577 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5578 | && TYPE_NFIELDS (type) <= 2 | |
5579 | && TYPE_NFIELDS (type) >= 1 | |
5580 | && ((TYPE_NFIELDS (type) == 1 | |
5581 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5582 | == TYPE_CODE_FLT)) | |
5583 | || (TYPE_NFIELDS (type) == 2 | |
5584 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5585 | == TYPE_CODE_FLT) | |
5586 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5587 | == TYPE_CODE_FLT))) | |
5588 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5589 | { | |
5590 | /* A struct that contains one or two floats. Each value is part | |
5591 | in the least significant part of their floating point | |
5592 | register.. */ | |
870cd05e | 5593 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
5594 | int regnum; |
5595 | int field; | |
72a155b4 | 5596 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5597 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5598 | { | |
5599 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5600 | / TARGET_CHAR_BIT); | |
5601 | if (mips_debug) | |
5602 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5603 | offset); | |
ba32f989 DJ |
5604 | mips_xfer_register (gdbarch, regcache, |
5605 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5606 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5607 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5608 | readbuf, writebuf, offset); |
6d82d43b AC |
5609 | } |
5610 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5611 | } | |
5612 | #endif | |
5613 | #if 0 | |
5614 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5615 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5616 | { | |
5617 | /* A structure or union. Extract the left justified value, | |
5618 | regardless of the byte order. I.e. DO NOT USE | |
5619 | mips_xfer_lower. */ | |
5620 | int offset; | |
5621 | int regnum; | |
4c7d22cb | 5622 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5623 | offset < TYPE_LENGTH (type); |
72a155b4 | 5624 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5625 | { |
72a155b4 | 5626 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5627 | if (offset + xfer > TYPE_LENGTH (type)) |
5628 | xfer = TYPE_LENGTH (type) - offset; | |
5629 | if (mips_debug) | |
5630 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5631 | offset, xfer, regnum); | |
ba32f989 DJ |
5632 | mips_xfer_register (gdbarch, regcache, |
5633 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5634 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5635 | } | |
5636 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5637 | } | |
5638 | #endif | |
5639 | else | |
5640 | { | |
5641 | /* A scalar extract each part but least-significant-byte | |
5642 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5643 | the ISA. */ |
6d82d43b AC |
5644 | int offset; |
5645 | int regnum; | |
4c7d22cb | 5646 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5647 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5648 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5649 | { |
1a69e1e4 | 5650 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5651 | if (offset + xfer > TYPE_LENGTH (type)) |
5652 | xfer = TYPE_LENGTH (type) - offset; | |
5653 | if (mips_debug) | |
5654 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5655 | offset, xfer, regnum); | |
ba32f989 DJ |
5656 | mips_xfer_register (gdbarch, regcache, |
5657 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5658 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5659 | readbuf, writebuf, offset); |
6d82d43b AC |
5660 | } |
5661 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5662 | } | |
5663 | } | |
5664 | ||
5665 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5666 | ABI. */ | |
46cac009 AC |
5667 | |
5668 | static CORE_ADDR | |
7d9b040b | 5669 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5670 | struct regcache *regcache, CORE_ADDR bp_addr, |
5671 | int nargs, | |
5672 | struct value **args, CORE_ADDR sp, | |
5673 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5674 | { |
5675 | int argreg; | |
5676 | int float_argreg; | |
5677 | int argnum; | |
5678 | int len = 0; | |
5679 | int stack_offset = 0; | |
e17a4113 | 5680 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5681 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5682 | |
25ab4790 AC |
5683 | /* For shared libraries, "t9" needs to point at the function |
5684 | address. */ | |
4c7d22cb | 5685 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5686 | |
5687 | /* Set the return address register to point to the entry point of | |
5688 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5689 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5690 | |
46cac009 AC |
5691 | /* First ensure that the stack and structure return address (if any) |
5692 | are properly aligned. The stack has to be at least 64-bit | |
5693 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5694 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5695 | aligned, so we round to this widest known alignment. */ | |
5696 | ||
5b03f266 AC |
5697 | sp = align_down (sp, 16); |
5698 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5699 | |
5700 | /* Now make space on the stack for the args. */ | |
5701 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5702 | { |
5703 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
968b5391 | 5704 | |
968b5391 | 5705 | /* Allocate space on the stack. */ |
354ecfd5 | 5706 | len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); |
968b5391 | 5707 | } |
5b03f266 | 5708 | sp -= align_up (len, 16); |
46cac009 AC |
5709 | |
5710 | if (mips_debug) | |
6d82d43b | 5711 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5712 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5713 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5714 | |
5715 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5716 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5717 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5718 | |
5719 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5720 | if (struct_return) | |
5721 | { | |
5722 | if (mips_debug) | |
5723 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5724 | "mips_o64_push_dummy_call: " |
5725 | "struct_return reg=%d %s\n", | |
5af949e3 | 5726 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5727 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5728 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5729 | } |
5730 | ||
5731 | /* Now load as many as possible of the first arguments into | |
5732 | registers, and push the rest onto the stack. Loop thru args | |
5733 | from first to last. */ | |
5734 | for (argnum = 0; argnum < nargs; argnum++) | |
5735 | { | |
47a35522 | 5736 | const gdb_byte *val; |
930bd0e0 | 5737 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 5738 | struct value *arg = args[argnum]; |
4991999e | 5739 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5740 | int len = TYPE_LENGTH (arg_type); |
5741 | enum type_code typecode = TYPE_CODE (arg_type); | |
5742 | ||
5743 | if (mips_debug) | |
5744 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5745 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5746 | argnum + 1, len, (int) typecode); |
5747 | ||
47a35522 | 5748 | val = value_contents (arg); |
ebafbe83 | 5749 | |
930bd0e0 KB |
5750 | /* Function pointer arguments to mips16 code need to be made into |
5751 | mips16 pointers. */ | |
5752 | if (typecode == TYPE_CODE_PTR | |
5753 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
5754 | { | |
5755 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
5756 | len, byte_order); | |
4cc0665f | 5757 | if (!mips_pc_is_mips (addr)) |
930bd0e0 KB |
5758 | { |
5759 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 5760 | make_compact_addr (addr)); |
930bd0e0 KB |
5761 | val = valbuf; |
5762 | } | |
5763 | } | |
5764 | ||
ebafbe83 | 5765 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5766 | treated specially. On 32-bit architectures, doubles are |
5767 | passed in register pairs; the even FP register gets the | |
5768 | low word, and the odd FP register gets the high word. | |
5769 | On O64, the first two floating point arguments are also | |
5770 | copied to general registers, because MIPS16 functions | |
5771 | don't use float registers for arguments. This duplication | |
5772 | of arguments in general registers can't hurt non-MIPS16 | |
5773 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5774 | |
74ed0bb4 MD |
5775 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5776 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5777 | { |
e17a4113 | 5778 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5779 | if (mips_debug) |
5780 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5781 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5782 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5783 | if (mips_debug) |
5784 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5785 | argreg, phex (regval, len)); | |
9c9acae0 | 5786 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5787 | argreg++; |
ebafbe83 | 5788 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5789 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5790 | } |
5791 | else | |
5792 | { | |
5793 | /* Copy the argument to general registers or the stack in | |
5794 | register-sized pieces. Large arguments are split between | |
5795 | registers and stack. */ | |
1a69e1e4 | 5796 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5797 | are treated specially: Irix cc passes them in registers |
5798 | where gcc sometimes puts them on the stack. For maximum | |
5799 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5800 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5801 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5802 | while (len > 0) |
5803 | { | |
5804 | /* Remember if the argument was written to the stack. */ | |
5805 | int stack_used_p = 0; | |
1a69e1e4 | 5806 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5807 | |
5808 | if (mips_debug) | |
5809 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5810 | partial_len); | |
5811 | ||
5812 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5813 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5814 | || odd_sized_struct) |
ebafbe83 MS |
5815 | { |
5816 | /* Should shorter than int integer values be | |
025bb325 | 5817 | promoted to int before being stored? */ |
ebafbe83 MS |
5818 | int longword_offset = 0; |
5819 | CORE_ADDR addr; | |
5820 | stack_used_p = 1; | |
72a155b4 | 5821 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5822 | { |
1a69e1e4 DJ |
5823 | if ((typecode == TYPE_CODE_INT |
5824 | || typecode == TYPE_CODE_PTR | |
5825 | || typecode == TYPE_CODE_FLT) | |
5826 | && len <= 4) | |
5827 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5828 | } |
5829 | ||
5830 | if (mips_debug) | |
5831 | { | |
5af949e3 UW |
5832 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5833 | paddress (gdbarch, stack_offset)); | |
5834 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5835 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5836 | } |
5837 | ||
5838 | addr = sp + stack_offset + longword_offset; | |
5839 | ||
5840 | if (mips_debug) | |
5841 | { | |
5842 | int i; | |
5af949e3 UW |
5843 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5844 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5845 | for (i = 0; i < partial_len; i++) |
5846 | { | |
6d82d43b | 5847 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
5848 | val[i] & 0xff); |
5849 | } | |
5850 | } | |
5851 | write_memory (addr, val, partial_len); | |
5852 | } | |
5853 | ||
5854 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5855 | structs may go thru BOTH paths. */ |
ebafbe83 | 5856 | /* Write this portion of the argument to a general |
6d82d43b | 5857 | purpose register. */ |
74ed0bb4 | 5858 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 5859 | { |
e17a4113 UW |
5860 | LONGEST regval = extract_signed_integer (val, partial_len, |
5861 | byte_order); | |
4246e332 | 5862 | /* Value may need to be sign extended, because |
1b13c4f6 | 5863 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
5864 | |
5865 | /* A non-floating-point argument being passed in a | |
5866 | general register. If a struct or union, and if | |
5867 | the remaining length is smaller than the register | |
5868 | size, we have to adjust the register value on | |
5869 | big endian targets. | |
5870 | ||
5871 | It does not seem to be necessary to do the | |
025bb325 | 5872 | same for integral types. */ |
480d3dd2 | 5873 | |
72a155b4 | 5874 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5875 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5876 | && (typecode == TYPE_CODE_STRUCT |
5877 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5878 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5879 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
5880 | |
5881 | if (mips_debug) | |
5882 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5883 | argreg, | |
1a69e1e4 | 5884 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5885 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
5886 | argreg++; |
5887 | ||
5888 | /* Prevent subsequent floating point arguments from | |
5889 | being passed in floating point registers. */ | |
74ed0bb4 | 5890 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
5891 | } |
5892 | ||
5893 | len -= partial_len; | |
5894 | val += partial_len; | |
5895 | ||
b021a221 MS |
5896 | /* Compute the offset into the stack at which we will |
5897 | copy the next parameter. | |
ebafbe83 | 5898 | |
6d82d43b AC |
5899 | In older ABIs, the caller reserved space for |
5900 | registers that contained arguments. This was loosely | |
5901 | refered to as their "home". Consequently, space is | |
5902 | always allocated. */ | |
ebafbe83 | 5903 | |
1a69e1e4 | 5904 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
5905 | } |
5906 | } | |
5907 | if (mips_debug) | |
5908 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5909 | } | |
5910 | ||
f10683bb | 5911 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5912 | |
ebafbe83 MS |
5913 | /* Return adjusted stack pointer. */ |
5914 | return sp; | |
5915 | } | |
5916 | ||
9c8fdbfa | 5917 | static enum return_value_convention |
6a3a010b | 5918 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 5919 | struct type *type, struct regcache *regcache, |
47a35522 | 5920 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5921 | { |
6a3a010b | 5922 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5923 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5924 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5925 | enum mips_fval_reg fval_reg; |
7a076fd2 | 5926 | |
6a3a010b | 5927 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
5928 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5929 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5930 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5931 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 5932 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 5933 | { |
6a3a010b MR |
5934 | /* A floating-point value. If reading in or copying, then we get it |
5935 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
5936 | If writing out only, then we put it to both FP0 and GPR2. We do | |
5937 | not support reading in with no function known, if this safety | |
5938 | check ever triggers, then we'll have to try harder. */ | |
5939 | gdb_assert (function || !readbuf); | |
7a076fd2 | 5940 | if (mips_debug) |
6a3a010b MR |
5941 | switch (fval_reg) |
5942 | { | |
5943 | case mips_fval_fpr: | |
5944 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5945 | break; | |
5946 | case mips_fval_gpr: | |
5947 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5948 | break; | |
5949 | case mips_fval_both: | |
5950 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5951 | break; | |
5952 | } | |
5953 | if (fval_reg != mips_fval_gpr) | |
5954 | mips_xfer_register (gdbarch, regcache, | |
5955 | (gdbarch_num_regs (gdbarch) | |
5956 | + mips_regnum (gdbarch)->fp0), | |
5957 | TYPE_LENGTH (type), | |
5958 | gdbarch_byte_order (gdbarch), | |
5959 | readbuf, writebuf, 0); | |
5960 | if (fval_reg != mips_fval_fpr) | |
5961 | mips_xfer_register (gdbarch, regcache, | |
5962 | gdbarch_num_regs (gdbarch) + 2, | |
5963 | TYPE_LENGTH (type), | |
5964 | gdbarch_byte_order (gdbarch), | |
5965 | readbuf, writebuf, 0); | |
7a076fd2 FF |
5966 | return RETURN_VALUE_REGISTER_CONVENTION; |
5967 | } | |
5968 | else | |
5969 | { | |
5970 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 5971 | justified. */ |
7a076fd2 FF |
5972 | int offset; |
5973 | int regnum; | |
5974 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
5975 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 5976 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 5977 | { |
1a69e1e4 | 5978 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
5979 | if (offset + xfer > TYPE_LENGTH (type)) |
5980 | xfer = TYPE_LENGTH (type) - offset; | |
5981 | if (mips_debug) | |
5982 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5983 | offset, xfer, regnum); | |
ba32f989 DJ |
5984 | mips_xfer_register (gdbarch, regcache, |
5985 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5986 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5987 | readbuf, writebuf, offset); |
7a076fd2 FF |
5988 | } |
5989 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5990 | } | |
6d82d43b AC |
5991 | } |
5992 | ||
dd824b04 DJ |
5993 | /* Floating point register management. |
5994 | ||
5995 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
5996 | 64bit operations, these early MIPS cpus treat fp register pairs | |
5997 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
5998 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
5999 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6000 | double precision floats into two 32-bit chunks and store them in | |
6001 | consecutive fp regs. To display 64-bit floats stored in this | |
6002 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6003 | Throw in user-configurable endianness and you have a real mess. | |
6004 | ||
6005 | The way this works is: | |
6006 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6007 | double-precision value will be split across two logical registers. | |
6008 | The lower-numbered logical register will hold the low-order bits, | |
6009 | regardless of the processor's endianness. | |
6010 | - If we are on a 64-bit processor, and we are looking for a | |
6011 | single-precision value, it will be in the low ordered bits | |
6012 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6013 | save slot in memory. | |
6014 | - If we are in 64-bit mode, everything is straightforward. | |
6015 | ||
6016 | Note that this code only deals with "live" registers at the top of the | |
6017 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6018 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6019 | interface that can deal with dynamic saved register sizes -- fp |
6020 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6021 | and below). */ | |
6022 | ||
6023 | /* Copy a 32-bit single-precision value from the current frame | |
6024 | into rare_buffer. */ | |
6025 | ||
6026 | static void | |
e11c53d2 | 6027 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 6028 | gdb_byte *rare_buffer) |
dd824b04 | 6029 | { |
72a155b4 UW |
6030 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6031 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 6032 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 6033 | |
ca9d61b9 | 6034 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6035 | error (_("can't read register %d (%s)"), |
72a155b4 | 6036 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6037 | if (raw_size == 8) |
6038 | { | |
6039 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 6040 | 32 bits. */ |
dd824b04 DJ |
6041 | int offset; |
6042 | ||
72a155b4 | 6043 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6044 | offset = 4; |
6045 | else | |
6046 | offset = 0; | |
6047 | ||
6048 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6049 | } | |
6050 | else | |
6051 | { | |
6052 | memcpy (rare_buffer, raw_buffer, 4); | |
6053 | } | |
6054 | } | |
6055 | ||
6056 | /* Copy a 64-bit double-precision value from the current frame into | |
6057 | rare_buffer. This may include getting half of it from the next | |
6058 | register. */ | |
6059 | ||
6060 | static void | |
e11c53d2 | 6061 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6062 | gdb_byte *rare_buffer) |
dd824b04 | 6063 | { |
72a155b4 UW |
6064 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6065 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6066 | |
9c9acae0 | 6067 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6068 | { |
6069 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6070 | all 64 bits. */ |
ca9d61b9 | 6071 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6072 | error (_("can't read register %d (%s)"), |
72a155b4 | 6073 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6074 | } |
6075 | else | |
6076 | { | |
72a155b4 | 6077 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6078 | |
72a155b4 | 6079 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6080 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6081 | _("mips_read_fp_register_double: bad access to " |
6082 | "odd-numbered FP register")); | |
dd824b04 DJ |
6083 | |
6084 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6085 | each register. */ |
72a155b4 | 6086 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6087 | { |
e11c53d2 AC |
6088 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6089 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6090 | } |
361d1df0 | 6091 | else |
dd824b04 | 6092 | { |
e11c53d2 AC |
6093 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6094 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6095 | } |
6096 | } | |
6097 | } | |
6098 | ||
c906108c | 6099 | static void |
e11c53d2 AC |
6100 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6101 | int regnum) | |
025bb325 | 6102 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6103 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6104 | gdb_byte *raw_buffer; |
025bb325 | 6105 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 6106 | int inv1, inv2; |
c5aa993b | 6107 | |
025bb325 MS |
6108 | raw_buffer = alloca (2 * register_size (gdbarch, |
6109 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 6110 | |
72a155b4 | 6111 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6112 | fprintf_filtered (file, "%*s", |
72a155b4 | 6113 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6114 | ""); |
f0ef6b29 | 6115 | |
72a155b4 | 6116 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6117 | { |
79a45b7d TT |
6118 | struct value_print_options opts; |
6119 | ||
f0ef6b29 KB |
6120 | /* 4-byte registers: Print hex and floating. Also print even |
6121 | numbered registers as doubles. */ | |
e11c53d2 | 6122 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
6123 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6124 | raw_buffer, &inv1); | |
c5aa993b | 6125 | |
79a45b7d | 6126 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6127 | print_scalar_formatted (raw_buffer, |
6128 | builtin_type (gdbarch)->builtin_uint32, | |
6129 | &opts, 'w', file); | |
dd824b04 | 6130 | |
e11c53d2 | 6131 | fprintf_filtered (file, " flt: "); |
1adad886 | 6132 | if (inv1) |
e11c53d2 | 6133 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 6134 | else |
e11c53d2 | 6135 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6136 | |
72a155b4 | 6137 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6138 | { |
e11c53d2 | 6139 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6140 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6141 | raw_buffer, &inv2); | |
1adad886 | 6142 | |
e11c53d2 | 6143 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6144 | if (inv2) |
e11c53d2 | 6145 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 6146 | else |
e11c53d2 | 6147 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 6148 | } |
c906108c SS |
6149 | } |
6150 | else | |
dd824b04 | 6151 | { |
79a45b7d TT |
6152 | struct value_print_options opts; |
6153 | ||
f0ef6b29 | 6154 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6155 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
6156 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6157 | raw_buffer, &inv1); | |
c906108c | 6158 | |
e11c53d2 | 6159 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6160 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6161 | raw_buffer, &inv2); | |
f0ef6b29 | 6162 | |
79a45b7d | 6163 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6164 | print_scalar_formatted (raw_buffer, |
6165 | builtin_type (gdbarch)->builtin_uint64, | |
6166 | &opts, 'g', file); | |
f0ef6b29 | 6167 | |
e11c53d2 | 6168 | fprintf_filtered (file, " flt: "); |
1adad886 | 6169 | if (inv1) |
e11c53d2 | 6170 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 6171 | else |
e11c53d2 | 6172 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6173 | |
e11c53d2 | 6174 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6175 | if (inv2) |
e11c53d2 | 6176 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 6177 | else |
e11c53d2 | 6178 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
6179 | } |
6180 | } | |
6181 | ||
6182 | static void | |
e11c53d2 | 6183 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6184 | int regnum) |
f0ef6b29 | 6185 | { |
a4b8ebc8 | 6186 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6187 | struct value_print_options opts; |
de15c4ab | 6188 | struct value *val; |
1adad886 | 6189 | |
004159a2 | 6190 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6191 | { |
e11c53d2 | 6192 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6193 | return; |
6194 | } | |
6195 | ||
de15c4ab | 6196 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6197 | |
72a155b4 | 6198 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6199 | |
6200 | /* The problem with printing numeric register names (r26, etc.) is that | |
6201 | the user can't use them on input. Probably the best solution is to | |
6202 | fix it so that either the numeric or the funky (a2, etc.) names | |
6203 | are accepted on input. */ | |
6204 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6205 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6206 | else |
e11c53d2 | 6207 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6208 | |
79a45b7d | 6209 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
6210 | val_print_scalar_formatted (value_type (val), |
6211 | value_contents_for_printing (val), | |
6212 | value_embedded_offset (val), | |
6213 | val, | |
6214 | &opts, 0, file); | |
c906108c SS |
6215 | } |
6216 | ||
f0ef6b29 KB |
6217 | /* Replacement for generic do_registers_info. |
6218 | Print regs in pretty columns. */ | |
6219 | ||
6220 | static int | |
e11c53d2 AC |
6221 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6222 | int regnum) | |
f0ef6b29 | 6223 | { |
e11c53d2 AC |
6224 | fprintf_filtered (file, " "); |
6225 | mips_print_fp_register (file, frame, regnum); | |
6226 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6227 | return regnum + 1; |
6228 | } | |
6229 | ||
6230 | ||
025bb325 | 6231 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6232 | |
6233 | static int | |
e11c53d2 | 6234 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6235 | int start_regnum) |
c906108c | 6236 | { |
a4b8ebc8 | 6237 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6238 | /* Do values for GP (int) regs. */ |
47a35522 | 6239 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
6240 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6241 | per row. */ | |
c906108c | 6242 | int col, byte; |
a4b8ebc8 | 6243 | int regnum; |
c906108c | 6244 | |
025bb325 | 6245 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6246 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6247 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6248 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6249 | regnum++) |
c906108c | 6250 | { |
72a155b4 | 6251 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6252 | continue; /* unused register */ |
004159a2 | 6253 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6254 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6255 | /* Large registers are handled separately. */ |
72a155b4 | 6256 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6257 | { |
6258 | if (col > 0) | |
6259 | break; /* End the row before this register. */ | |
6260 | ||
6261 | /* Print this register on a row by itself. */ | |
6262 | mips_print_register (file, frame, regnum); | |
6263 | fprintf_filtered (file, "\n"); | |
6264 | return regnum + 1; | |
6265 | } | |
d05f6826 DJ |
6266 | if (col == 0) |
6267 | fprintf_filtered (file, " "); | |
6d82d43b | 6268 | fprintf_filtered (file, |
72a155b4 UW |
6269 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6270 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6271 | col++; |
6272 | } | |
d05f6826 DJ |
6273 | |
6274 | if (col == 0) | |
6275 | return regnum; | |
6276 | ||
025bb325 | 6277 | /* Print the R0 to R31 names. */ |
72a155b4 | 6278 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6279 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6280 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6281 | else |
6282 | fprintf_filtered (file, "\n "); | |
c906108c | 6283 | |
025bb325 | 6284 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6285 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6286 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6287 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6288 | regnum++) |
c906108c | 6289 | { |
72a155b4 | 6290 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6291 | continue; /* unused register */ |
004159a2 | 6292 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6293 | break; /* End row: reached FP register. */ |
72a155b4 | 6294 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6295 | break; /* End row: large register. */ |
6296 | ||
c906108c | 6297 | /* OK: get the data in raw format. */ |
ca9d61b9 | 6298 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 6299 | error (_("can't read register %d (%s)"), |
72a155b4 | 6300 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 6301 | /* pad small registers */ |
4246e332 | 6302 | for (byte = 0; |
72a155b4 UW |
6303 | byte < (mips_abi_regsize (gdbarch) |
6304 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 6305 | printf_filtered (" "); |
025bb325 | 6306 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6307 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6308 | for (byte = |
72a155b4 UW |
6309 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6310 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6311 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6312 | else |
72a155b4 | 6313 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6314 | byte >= 0; byte--) |
47a35522 | 6315 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6316 | fprintf_filtered (file, " "); |
c906108c SS |
6317 | col++; |
6318 | } | |
025bb325 | 6319 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6320 | fprintf_filtered (file, "\n"); |
c906108c SS |
6321 | |
6322 | return regnum; | |
6323 | } | |
6324 | ||
025bb325 | 6325 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6326 | |
bf1f5b4c | 6327 | static void |
e11c53d2 AC |
6328 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6329 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6330 | { |
025bb325 | 6331 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6332 | { |
72a155b4 UW |
6333 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6334 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6335 | error (_("Not a valid register for the current processor type")); |
c906108c | 6336 | |
0cc93a06 | 6337 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6338 | fprintf_filtered (file, "\n"); |
c906108c | 6339 | } |
c5aa993b | 6340 | else |
025bb325 | 6341 | /* Do all (or most) registers. */ |
c906108c | 6342 | { |
72a155b4 UW |
6343 | regnum = gdbarch_num_regs (gdbarch); |
6344 | while (regnum < gdbarch_num_regs (gdbarch) | |
6345 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6346 | { |
004159a2 | 6347 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6348 | { |
025bb325 | 6349 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6350 | regnum = print_fp_register_row (file, frame, regnum); |
6351 | else | |
025bb325 | 6352 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6353 | } |
c906108c | 6354 | else |
e11c53d2 | 6355 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6356 | } |
6357 | } | |
6358 | } | |
6359 | ||
63807e1d | 6360 | static int |
3352ef37 AC |
6361 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6362 | struct frame_info *frame) | |
c906108c | 6363 | { |
e17a4113 | 6364 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 6365 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6366 | struct address_space *aspace; |
6367 | enum mips_isa isa; | |
6368 | ULONGEST insn; | |
6369 | int status; | |
6370 | int size; | |
6371 | ||
6372 | if ((mips_pc_is_mips (pc) | |
6373 | && !mips32_instruction_has_delay_slot (gdbarch, pc)) | |
6374 | || (mips_pc_is_micromips (gdbarch, pc) | |
6375 | && !micromips_instruction_has_delay_slot (gdbarch, pc, 0)) | |
6376 | || (mips_pc_is_mips16 (gdbarch, pc) | |
6377 | && !mips16_instruction_has_delay_slot (gdbarch, pc, 0))) | |
06648491 MK |
6378 | return 0; |
6379 | ||
4cc0665f MR |
6380 | isa = mips_pc_isa (gdbarch, pc); |
6381 | /* _has_delay_slot above will have validated the read. */ | |
6382 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6383 | size = mips_insn_size (isa, insn); | |
6384 | aspace = get_frame_address_space (frame); | |
6385 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; | |
c906108c SS |
6386 | } |
6387 | ||
6d82d43b AC |
6388 | /* To skip prologues, I use this predicate. Returns either PC itself |
6389 | if the code at PC does not look like a function prologue; otherwise | |
6390 | returns an address that (if we're lucky) follows the prologue. If | |
6391 | LENIENT, then we must skip everything which is involved in setting | |
6392 | up the frame (it's OK to skip more, just so long as we don't skip | |
6393 | anything which might clobber the registers which are being saved. | |
6394 | We must skip more in the case where part of the prologue is in the | |
6395 | delay slot of a non-prologue instruction). */ | |
6396 | ||
6397 | static CORE_ADDR | |
6093d2eb | 6398 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6399 | { |
8b622e6a AC |
6400 | CORE_ADDR limit_pc; |
6401 | CORE_ADDR func_addr; | |
6402 | ||
6d82d43b AC |
6403 | /* See if we can determine the end of the prologue via the symbol table. |
6404 | If so, then return either PC, or the PC after the prologue, whichever | |
6405 | is greater. */ | |
8b622e6a AC |
6406 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6407 | { | |
d80b854b UW |
6408 | CORE_ADDR post_prologue_pc |
6409 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
6410 | if (post_prologue_pc != 0) |
6411 | return max (pc, post_prologue_pc); | |
6412 | } | |
6d82d43b AC |
6413 | |
6414 | /* Can't determine prologue from the symbol table, need to examine | |
6415 | instructions. */ | |
6416 | ||
98b4dd94 JB |
6417 | /* Find an upper limit on the function prologue using the debug |
6418 | information. If the debug information could not be used to provide | |
6419 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6420 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6421 | if (limit_pc == 0) |
6422 | limit_pc = pc + 100; /* Magic. */ | |
6423 | ||
4cc0665f | 6424 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6425 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6426 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6427 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6428 | else |
e17a4113 | 6429 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6430 | } |
6431 | ||
97ab0fdd MR |
6432 | /* Check whether the PC is in a function epilogue (32-bit version). |
6433 | This is a helper function for mips_in_function_epilogue_p. */ | |
6434 | static int | |
e17a4113 | 6435 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6436 | { |
6437 | CORE_ADDR func_addr = 0, func_end = 0; | |
6438 | ||
6439 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6440 | { | |
6441 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6442 | CORE_ADDR addr = func_end - 12; | |
6443 | ||
6444 | if (addr < func_addr + 4) | |
6445 | addr = func_addr + 4; | |
6446 | if (pc < addr) | |
6447 | return 0; | |
6448 | ||
6449 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6450 | { | |
6451 | unsigned long high_word; | |
6452 | unsigned long inst; | |
6453 | ||
4cc0665f | 6454 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6455 | high_word = (inst >> 16) & 0xffff; |
6456 | ||
6457 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6458 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6459 | && inst != 0x03e00008 /* jr $ra */ | |
6460 | && inst != 0x00000000) /* nop */ | |
6461 | return 0; | |
6462 | } | |
6463 | ||
6464 | return 1; | |
6465 | } | |
6466 | ||
6467 | return 0; | |
6468 | } | |
6469 | ||
4cc0665f MR |
6470 | /* Check whether the PC is in a function epilogue (microMIPS version). |
6471 | This is a helper function for mips_in_function_epilogue_p. */ | |
6472 | ||
6473 | static int | |
6474 | micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6475 | { | |
6476 | CORE_ADDR func_addr = 0; | |
6477 | CORE_ADDR func_end = 0; | |
6478 | CORE_ADDR addr; | |
6479 | ULONGEST insn; | |
6480 | long offset; | |
6481 | int dreg; | |
6482 | int sreg; | |
6483 | int loc; | |
6484 | ||
6485 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6486 | return 0; | |
6487 | ||
6488 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6489 | addr = func_end - 12; | |
6490 | ||
6491 | if (addr < func_addr + 2) | |
6492 | addr = func_addr + 2; | |
6493 | if (pc < addr) | |
6494 | return 0; | |
6495 | ||
6496 | for (; pc < func_end; pc += loc) | |
6497 | { | |
6498 | loc = 0; | |
6499 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6500 | loc += MIPS_INSN16_SIZE; | |
6501 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6502 | { | |
6503 | /* 48-bit instructions. */ | |
6504 | case 3 * MIPS_INSN16_SIZE: | |
6505 | /* No epilogue instructions in this category. */ | |
6506 | return 0; | |
6507 | ||
6508 | /* 32-bit instructions. */ | |
6509 | case 2 * MIPS_INSN16_SIZE: | |
6510 | insn <<= 16; | |
6511 | insn |= mips_fetch_instruction (gdbarch, | |
6512 | ISA_MICROMIPS, pc + loc, NULL); | |
6513 | loc += MIPS_INSN16_SIZE; | |
6514 | switch (micromips_op (insn >> 16)) | |
6515 | { | |
6516 | case 0xc: /* ADDIU: bits 001100 */ | |
6517 | case 0x17: /* DADDIU: bits 010111 */ | |
6518 | sreg = b0s5_reg (insn >> 16); | |
6519 | dreg = b5s5_reg (insn >> 16); | |
6520 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6521 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6522 | /* (D)ADDIU $sp, imm */ | |
6523 | && offset >= 0) | |
6524 | break; | |
6525 | return 0; | |
6526 | ||
6527 | default: | |
6528 | return 0; | |
6529 | } | |
6530 | break; | |
6531 | ||
6532 | /* 16-bit instructions. */ | |
6533 | case MIPS_INSN16_SIZE: | |
6534 | switch (micromips_op (insn)) | |
6535 | { | |
6536 | case 0x3: /* MOVE: bits 000011 */ | |
6537 | sreg = b0s5_reg (insn); | |
6538 | dreg = b5s5_reg (insn); | |
6539 | if (sreg == 0 && dreg == 0) | |
6540 | /* MOVE $zero, $zero aka NOP */ | |
6541 | break; | |
6542 | return 0; | |
6543 | ||
6544 | case 0x11: /* POOL16C: bits 010001 */ | |
6545 | if (b5s5_op (insn) == 0x18 | |
6546 | /* JRADDIUSP: bits 010011 11000 */ | |
6547 | || (b5s5_op (insn) == 0xd | |
6548 | /* JRC: bits 010011 01101 */ | |
6549 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6550 | /* JRC $ra */ | |
6551 | break; | |
6552 | return 0; | |
6553 | ||
6554 | case 0x13: /* POOL16D: bits 010011 */ | |
6555 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6556 | if ((insn & 0x1) == 0x1 | |
6557 | /* ADDIUSP: bits 010011 1 */ | |
6558 | && offset > 0) | |
6559 | break; | |
6560 | return 0; | |
6561 | ||
6562 | default: | |
6563 | return 0; | |
6564 | } | |
6565 | } | |
6566 | } | |
6567 | ||
6568 | return 1; | |
6569 | } | |
6570 | ||
97ab0fdd MR |
6571 | /* Check whether the PC is in a function epilogue (16-bit version). |
6572 | This is a helper function for mips_in_function_epilogue_p. */ | |
6573 | static int | |
e17a4113 | 6574 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6575 | { |
6576 | CORE_ADDR func_addr = 0, func_end = 0; | |
6577 | ||
6578 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6579 | { | |
6580 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6581 | CORE_ADDR addr = func_end - 12; | |
6582 | ||
6583 | if (addr < func_addr + 4) | |
6584 | addr = func_addr + 4; | |
6585 | if (pc < addr) | |
6586 | return 0; | |
6587 | ||
6588 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6589 | { | |
6590 | unsigned short inst; | |
6591 | ||
4cc0665f | 6592 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6593 | |
6594 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6595 | continue; | |
6596 | ||
6597 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6598 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6599 | && inst != 0xe820 /* jr $ra */ | |
6600 | && inst != 0xe8a0 /* jrc $ra */ | |
6601 | && inst != 0x6500) /* nop */ | |
6602 | return 0; | |
6603 | } | |
6604 | ||
6605 | return 1; | |
6606 | } | |
6607 | ||
6608 | return 0; | |
6609 | } | |
6610 | ||
6611 | /* The epilogue is defined here as the area at the end of a function, | |
6612 | after an instruction which destroys the function's stack frame. */ | |
6613 | static int | |
6614 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6615 | { | |
4cc0665f | 6616 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6617 | return mips16_in_function_epilogue_p (gdbarch, pc); |
4cc0665f MR |
6618 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6619 | return micromips_in_function_epilogue_p (gdbarch, pc); | |
97ab0fdd | 6620 | else |
e17a4113 | 6621 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
6622 | } |
6623 | ||
025bb325 | 6624 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6625 | used for all MIPS-specific commands. */ |
6626 | ||
a5ea2558 | 6627 | static void |
acdb74a0 | 6628 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
6629 | { |
6630 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6631 | } | |
6632 | ||
a5ea2558 | 6633 | static void |
acdb74a0 | 6634 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 6635 | { |
6d82d43b AC |
6636 | printf_unfiltered |
6637 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6638 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6639 | } | |
6640 | ||
c906108c SS |
6641 | /* Commands to show/set the MIPS FPU type. */ |
6642 | ||
c906108c | 6643 | static void |
acdb74a0 | 6644 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 6645 | { |
c906108c | 6646 | char *fpu; |
6ca0852e | 6647 | |
f5656ead | 6648 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e UW |
6649 | { |
6650 | printf_unfiltered | |
6651 | ("The MIPS floating-point coprocessor is unknown " | |
6652 | "because the current architecture is not MIPS.\n"); | |
6653 | return; | |
6654 | } | |
6655 | ||
f5656ead | 6656 | switch (MIPS_FPU_TYPE (target_gdbarch ())) |
c906108c SS |
6657 | { |
6658 | case MIPS_FPU_SINGLE: | |
6659 | fpu = "single-precision"; | |
6660 | break; | |
6661 | case MIPS_FPU_DOUBLE: | |
6662 | fpu = "double-precision"; | |
6663 | break; | |
6664 | case MIPS_FPU_NONE: | |
6665 | fpu = "absent (none)"; | |
6666 | break; | |
93d56215 | 6667 | default: |
e2e0b3e5 | 6668 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6669 | } |
6670 | if (mips_fpu_type_auto) | |
025bb325 MS |
6671 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6672 | "is set automatically (currently %s)\n", | |
6673 | fpu); | |
c906108c | 6674 | else |
6d82d43b AC |
6675 | printf_unfiltered |
6676 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6677 | } |
6678 | ||
6679 | ||
c906108c | 6680 | static void |
acdb74a0 | 6681 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 6682 | { |
025bb325 MS |
6683 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6684 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6685 | show_mipsfpu_command (args, from_tty); |
6686 | } | |
6687 | ||
c906108c | 6688 | static void |
acdb74a0 | 6689 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 6690 | { |
8d5838b5 AC |
6691 | struct gdbarch_info info; |
6692 | gdbarch_info_init (&info); | |
c906108c SS |
6693 | mips_fpu_type = MIPS_FPU_SINGLE; |
6694 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6695 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6696 | instead of relying on globals. Doing that would let generic code | |
6697 | handle the search for this specific architecture. */ | |
6698 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6699 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6700 | } |
6701 | ||
c906108c | 6702 | static void |
acdb74a0 | 6703 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 6704 | { |
8d5838b5 AC |
6705 | struct gdbarch_info info; |
6706 | gdbarch_info_init (&info); | |
c906108c SS |
6707 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6708 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6709 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6710 | instead of relying on globals. Doing that would let generic code | |
6711 | handle the search for this specific architecture. */ | |
6712 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6713 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6714 | } |
6715 | ||
c906108c | 6716 | static void |
acdb74a0 | 6717 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 6718 | { |
8d5838b5 AC |
6719 | struct gdbarch_info info; |
6720 | gdbarch_info_init (&info); | |
c906108c SS |
6721 | mips_fpu_type = MIPS_FPU_NONE; |
6722 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6723 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6724 | instead of relying on globals. Doing that would let generic code | |
6725 | handle the search for this specific architecture. */ | |
6726 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6727 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6728 | } |
6729 | ||
c906108c | 6730 | static void |
acdb74a0 | 6731 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
6732 | { |
6733 | mips_fpu_type_auto = 1; | |
6734 | } | |
6735 | ||
c906108c | 6736 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
6737 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
6738 | the relevant processor still exists (it dates back to '94) and | |
6739 | secondly this is not the way to do this. The processor type should | |
6740 | be set by forcing an architecture change. */ | |
c906108c | 6741 | |
691c0433 AC |
6742 | void |
6743 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 6744 | { |
bb486190 UW |
6745 | struct regcache *regcache = get_current_regcache (); |
6746 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
6747 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 6748 | ULONGEST prid; |
c906108c | 6749 | |
bb486190 | 6750 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 6751 | if ((prid & ~0xf) == 0x700) |
691c0433 | 6752 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
6753 | } |
6754 | ||
6755 | /* Just like reinit_frame_cache, but with the right arguments to be | |
6756 | callable as an sfunc. */ | |
6757 | ||
6758 | static void | |
acdb74a0 AC |
6759 | reinit_frame_cache_sfunc (char *args, int from_tty, |
6760 | struct cmd_list_element *c) | |
c906108c SS |
6761 | { |
6762 | reinit_frame_cache (); | |
6763 | } | |
6764 | ||
a89aa300 AC |
6765 | static int |
6766 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6767 | { |
4cc0665f MR |
6768 | struct gdbarch *gdbarch = info->application_data; |
6769 | ||
d31431ed AC |
6770 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6771 | disassembler needs to be able to locally determine the ISA, and | |
6772 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6773 | work. */ | |
4cc0665f | 6774 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6775 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6776 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6777 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6778 | |
6779 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6780 | memaddr &= (info->mach == bfd_mach_mips16 |
6781 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6782 | |
e5ab0dce | 6783 | /* Set the disassembler options. */ |
9dae60cc | 6784 | if (!info->disassembler_options) |
e5ab0dce AC |
6785 | /* This string is not recognized explicitly by the disassembler, |
6786 | but it tells the disassembler to not try to guess the ABI from | |
6787 | the bfd elf headers, such that, if the user overrides the ABI | |
6788 | of a program linked as NewABI, the disassembly will follow the | |
6789 | register naming conventions specified by the user. */ | |
6790 | info->disassembler_options = "gpr-names=32"; | |
6791 | ||
c906108c | 6792 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 6793 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
6794 | return print_insn_big_mips (memaddr, info); |
6795 | else | |
6796 | return print_insn_little_mips (memaddr, info); | |
6797 | } | |
6798 | ||
9dae60cc UW |
6799 | static int |
6800 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
6801 | { | |
6802 | /* Set up the disassembler info, so that we get the right | |
6803 | register names from libopcodes. */ | |
6804 | info->disassembler_options = "gpr-names=n32"; | |
6805 | info->flavour = bfd_target_elf_flavour; | |
6806 | ||
6807 | return gdb_print_insn_mips (memaddr, info); | |
6808 | } | |
6809 | ||
6810 | static int | |
6811 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
6812 | { | |
6813 | /* Set up the disassembler info, so that we get the right | |
6814 | register names from libopcodes. */ | |
6815 | info->disassembler_options = "gpr-names=64"; | |
6816 | info->flavour = bfd_target_elf_flavour; | |
6817 | ||
6818 | return gdb_print_insn_mips (memaddr, info); | |
6819 | } | |
6820 | ||
025bb325 MS |
6821 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
6822 | program counter value to determine whether a 16- or 32-bit breakpoint | |
6823 | should be used. It returns a pointer to a string of bytes that encode a | |
6824 | breakpoint instruction, stores the length of the string to *lenptr, and | |
6825 | adjusts pc (if necessary) to point to the actual memory location where | |
6826 | the breakpoint should be inserted. */ | |
c906108c | 6827 | |
47a35522 | 6828 | static const gdb_byte * |
025bb325 MS |
6829 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
6830 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 6831 | { |
4cc0665f MR |
6832 | CORE_ADDR pc = *pcptr; |
6833 | ||
67d57894 | 6834 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 6835 | { |
4cc0665f | 6836 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6837 | { |
47a35522 | 6838 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
4cc0665f | 6839 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6840 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
6841 | return mips16_big_breakpoint; |
6842 | } | |
4cc0665f MR |
6843 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6844 | { | |
6845 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
6846 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
6847 | ULONGEST insn; | |
6848 | int status; | |
6849 | int size; | |
6850 | ||
6851 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6852 | size = status ? 2 | |
6853 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6854 | *pcptr = unmake_compact_addr (pc); | |
6855 | *lenptr = size; | |
6856 | return (size == 2) ? micromips16_big_breakpoint | |
6857 | : micromips32_big_breakpoint; | |
6858 | } | |
c906108c SS |
6859 | else |
6860 | { | |
aaab4dba AC |
6861 | /* The IDT board uses an unusual breakpoint value, and |
6862 | sometimes gets confused when it sees the usual MIPS | |
6863 | breakpoint instruction. */ | |
47a35522 MK |
6864 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
6865 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
6866 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 6867 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 6868 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 6869 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 6870 | |
c5aa993b | 6871 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
6872 | |
6873 | if (strcmp (target_shortname, "mips") == 0) | |
6874 | return idt_big_breakpoint; | |
6875 | else if (strcmp (target_shortname, "ddb") == 0 | |
6876 | || strcmp (target_shortname, "pmon") == 0 | |
6877 | || strcmp (target_shortname, "lsi") == 0) | |
6878 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
6879 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
6880 | return irix_big_breakpoint; | |
c906108c SS |
6881 | else |
6882 | return big_breakpoint; | |
6883 | } | |
6884 | } | |
6885 | else | |
6886 | { | |
4cc0665f | 6887 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6888 | { |
47a35522 | 6889 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
4cc0665f | 6890 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6891 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
6892 | return mips16_little_breakpoint; |
6893 | } | |
4cc0665f MR |
6894 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6895 | { | |
6896 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
6897 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
6898 | ULONGEST insn; | |
6899 | int status; | |
6900 | int size; | |
6901 | ||
6902 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6903 | size = status ? 2 | |
6904 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6905 | *pcptr = unmake_compact_addr (pc); | |
6906 | *lenptr = size; | |
6907 | return (size == 2) ? micromips16_little_breakpoint | |
6908 | : micromips32_little_breakpoint; | |
6909 | } | |
c906108c SS |
6910 | else |
6911 | { | |
47a35522 MK |
6912 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
6913 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
6914 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 6915 | |
c5aa993b | 6916 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
6917 | |
6918 | if (strcmp (target_shortname, "mips") == 0) | |
6919 | return idt_little_breakpoint; | |
6920 | else if (strcmp (target_shortname, "ddb") == 0 | |
6921 | || strcmp (target_shortname, "pmon") == 0 | |
6922 | || strcmp (target_shortname, "lsi") == 0) | |
6923 | return pmon_little_breakpoint; | |
6924 | else | |
6925 | return little_breakpoint; | |
6926 | } | |
6927 | } | |
6928 | } | |
6929 | ||
4cc0665f MR |
6930 | /* Determine the remote breakpoint kind suitable for the PC. The following |
6931 | kinds are used: | |
6932 | ||
6933 | * 2 -- 16-bit MIPS16 mode breakpoint, | |
6934 | ||
6935 | * 3 -- 16-bit microMIPS mode breakpoint, | |
6936 | ||
6937 | * 4 -- 32-bit standard MIPS mode breakpoint, | |
6938 | ||
6939 | * 5 -- 32-bit microMIPS mode breakpoint. */ | |
6940 | ||
6941 | static void | |
6942 | mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
6943 | int *kindptr) | |
6944 | { | |
6945 | CORE_ADDR pc = *pcptr; | |
6946 | ||
6947 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
6948 | { | |
6949 | *pcptr = unmake_compact_addr (pc); | |
6950 | *kindptr = 2; | |
6951 | } | |
6952 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
6953 | { | |
6954 | ULONGEST insn; | |
6955 | int status; | |
6956 | int size; | |
6957 | ||
6958 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6959 | size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6960 | *pcptr = unmake_compact_addr (pc); | |
6961 | *kindptr = size | 1; | |
6962 | } | |
6963 | else | |
6964 | *kindptr = 4; | |
6965 | } | |
6966 | ||
c8cef75f MR |
6967 | /* Return non-zero if the ADDR instruction has a branch delay slot |
6968 | (i.e. it is a jump or branch instruction). This function is based | |
6969 | on mips32_next_pc. */ | |
6970 | ||
6971 | static int | |
6972 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
6973 | { | |
c8cef75f MR |
6974 | unsigned long inst; |
6975 | int status; | |
6976 | int op; | |
a385295e MR |
6977 | int rs; |
6978 | int rt; | |
c8cef75f | 6979 | |
4cc0665f | 6980 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
c8cef75f MR |
6981 | if (status) |
6982 | return 0; | |
6983 | ||
c8cef75f MR |
6984 | op = itype_op (inst); |
6985 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
6986 | { |
6987 | rs = itype_rs (inst); | |
6988 | rt = itype_rt (inst); | |
f94363d7 AP |
6989 | return (is_octeon_bbit_op (op, gdbarch) |
6990 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
6991 | || op == 29 /* JALX: bits 011101 */ |
6992 | || (op == 17 | |
6993 | && (rs == 8 | |
c8cef75f | 6994 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
6995 | || (rs == 9 && (rt & 0x2) == 0) |
6996 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
6997 | || (rs == 10 && (rt & 0x2) == 0)))); | |
6998 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
6999 | } | |
c8cef75f MR |
7000 | else |
7001 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7002 | { | |
7003 | case 0: /* SPECIAL */ | |
7004 | op = rtype_funct (inst); | |
7005 | return (op == 8 /* JR */ | |
7006 | || op == 9); /* JALR */ | |
7007 | break; /* end SPECIAL */ | |
7008 | case 1: /* REGIMM */ | |
a385295e MR |
7009 | rs = itype_rs (inst); |
7010 | rt = itype_rt (inst); /* branch condition */ | |
7011 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7012 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7013 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7014 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7015 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7016 | break; /* end REGIMM */ |
7017 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7018 | return 1; | |
7019 | break; | |
7020 | } | |
7021 | } | |
7022 | ||
7023 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
7024 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
7025 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
7026 | ||
4cc0665f MR |
7027 | static int |
7028 | micromips_instruction_has_delay_slot (struct gdbarch *gdbarch, | |
7029 | CORE_ADDR addr, int mustbe32) | |
7030 | { | |
7031 | ULONGEST insn; | |
7032 | int status; | |
7033 | ||
7034 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7035 | if (status) | |
7036 | return 0; | |
7037 | ||
7038 | if (!mustbe32) /* 16-bit instructions. */ | |
7039 | return (micromips_op (insn) == 0x11 | |
7040 | /* POOL16C: bits 010001 */ | |
7041 | && (b5s5_op (insn) == 0xc | |
7042 | /* JR16: bits 010001 01100 */ | |
7043 | || (b5s5_op (insn) & 0x1e) == 0xe)) | |
7044 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7045 | || (micromips_op (insn) & 0x37) == 0x23 | |
7046 | /* BEQZ16, BNEZ16: bits 10x011 */ | |
7047 | || micromips_op (insn) == 0x33; | |
7048 | /* B16: bits 110011 */ | |
7049 | ||
7050 | /* 32-bit instructions. */ | |
7051 | if (micromips_op (insn) == 0x0) | |
7052 | /* POOL32A: bits 000000 */ | |
7053 | { | |
7054 | insn <<= 16; | |
7055 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7056 | if (status) | |
7057 | return 0; | |
7058 | return b0s6_op (insn) == 0x3c | |
7059 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7060 | && (b6s10_ext (insn) & 0x2bf) == 0x3c; | |
7061 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7062 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7063 | } | |
7064 | ||
7065 | return (micromips_op (insn) == 0x10 | |
7066 | /* POOL32I: bits 010000 */ | |
7067 | && ((b5s5_op (insn) & 0x1c) == 0x0 | |
7068 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
7069 | || (b5s5_op (insn) & 0x1d) == 0x4 | |
7070 | /* BLEZ, BGTZ: bits 010000 001x0 */ | |
7071 | || (b5s5_op (insn) & 0x1d) == 0x11 | |
7072 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
7073 | || ((b5s5_op (insn) & 0x1e) == 0x14 | |
7074 | && (insn & 0x3) == 0x0) | |
7075 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
7076 | || (b5s5_op (insn) & 0x1e) == 0x1a | |
7077 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
7078 | || ((b5s5_op (insn) & 0x1e) == 0x1c | |
7079 | && (insn & 0x3) == 0x0) | |
7080 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
7081 | || ((b5s5_op (insn) & 0x1c) == 0x1c | |
7082 | && (insn & 0x3) == 0x1))) | |
7083 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
7084 | || (micromips_op (insn) & 0x1f) == 0x1d | |
7085 | /* JALS, JAL: bits x11101 */ | |
7086 | || (micromips_op (insn) & 0x37) == 0x25 | |
7087 | /* BEQ, BNE: bits 10x101 */ | |
7088 | || micromips_op (insn) == 0x35 | |
7089 | /* J: bits 110101 */ | |
7090 | || micromips_op (insn) == 0x3c; | |
7091 | /* JALX: bits 111100 */ | |
7092 | } | |
7093 | ||
c8cef75f MR |
7094 | static int |
7095 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
7096 | int mustbe32) | |
7097 | { | |
c8cef75f MR |
7098 | unsigned short inst; |
7099 | int status; | |
7100 | ||
4cc0665f | 7101 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); |
c8cef75f MR |
7102 | if (status) |
7103 | return 0; | |
7104 | ||
c8cef75f MR |
7105 | if (!mustbe32) |
7106 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
7107 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
7108 | } | |
7109 | ||
7110 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
7111 | This assumes KSSEG exists. */ | |
7112 | ||
7113 | static CORE_ADDR | |
7114 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7115 | { | |
7116 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7117 | int segsize; | |
7118 | ||
7119 | if (sizeof (CORE_ADDR) == 8) | |
7120 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7121 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7122 | though in that case this is dead code). */ | |
7123 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7124 | { | |
7125 | case 3: | |
7126 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7127 | segsize = 29; /* 32-bit compatibility segment */ | |
7128 | else | |
7129 | segsize = 62; /* xkseg */ | |
7130 | break; | |
7131 | case 2: /* xkphys */ | |
7132 | segsize = 59; | |
7133 | break; | |
7134 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7135 | segsize = 62; | |
7136 | break; | |
7137 | } | |
7138 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7139 | segsize = 29; | |
7140 | else | |
7141 | segsize = 31; /* user segment */ | |
7142 | mask <<= segsize; | |
7143 | return bpaddr & mask; | |
7144 | } | |
7145 | ||
7146 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7147 | it backwards if necessary. Return the address of the new location. */ | |
7148 | ||
7149 | static CORE_ADDR | |
7150 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7151 | { | |
22e048c9 | 7152 | CORE_ADDR prev_addr; |
c8cef75f MR |
7153 | CORE_ADDR boundary; |
7154 | CORE_ADDR func_addr; | |
7155 | ||
7156 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7157 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7158 | the instruction in the branch delay slot, the PC will point to | |
7159 | the branch instruction. Since the PC doesn't match any known | |
7160 | breakpoints, GDB reports a trap exception. | |
7161 | ||
7162 | There are two possible fixes for this problem. | |
7163 | ||
7164 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7165 | Cause register (which indicates the last exception occurred in a | |
7166 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7167 | the instruction in the branch delay slot. | |
7168 | ||
7169 | 2) When the user sets the breakpoint, don't allow him to set the | |
7170 | breakpoint on the instruction in the branch delay slot. Instead | |
7171 | move the breakpoint to the branch instruction (which will have | |
7172 | the same result). | |
7173 | ||
7174 | The problem with the first solution is that if the user then | |
7175 | single-steps the processor, the branch instruction will get | |
7176 | skipped (since GDB thinks the PC is on the instruction in the | |
7177 | branch delay slot). | |
7178 | ||
7179 | So, we'll use the second solution. To do this we need to know if | |
7180 | the instruction we're trying to set the breakpoint on is in the | |
7181 | branch delay slot. */ | |
7182 | ||
7183 | boundary = mips_segment_boundary (bpaddr); | |
7184 | ||
7185 | /* Make sure we don't scan back before the beginning of the current | |
7186 | function, since we may fetch constant data or insns that look like | |
7187 | a jump. Of course we might do that anyway if the compiler has | |
7188 | moved constants inline. :-( */ | |
7189 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7190 | && func_addr > boundary && func_addr <= bpaddr) | |
7191 | boundary = func_addr; | |
7192 | ||
4cc0665f | 7193 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7194 | { |
7195 | if (bpaddr == boundary) | |
7196 | return bpaddr; | |
7197 | ||
7198 | /* If the previous instruction has a branch delay slot, we have | |
7199 | to move the breakpoint to the branch instruction. */ | |
7200 | prev_addr = bpaddr - 4; | |
7201 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
7202 | bpaddr = prev_addr; | |
7203 | } | |
7204 | else | |
7205 | { | |
4cc0665f | 7206 | int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7207 | CORE_ADDR addr, jmpaddr; |
7208 | int i; | |
7209 | ||
4cc0665f | 7210 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7211 | |
7212 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7213 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7214 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7215 | The microMIPS ASE has a whole range of jumps and branches |
7216 | with delay slots, some of which take 4 bytes and some take | |
7217 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7218 | FIXME: We have to assume that bpaddr is not the second half |
7219 | of an extended instruction. */ | |
4cc0665f MR |
7220 | instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7221 | ? micromips_instruction_has_delay_slot | |
7222 | : mips16_instruction_has_delay_slot); | |
c8cef75f MR |
7223 | |
7224 | jmpaddr = 0; | |
7225 | addr = bpaddr; | |
7226 | for (i = 1; i < 4; i++) | |
7227 | { | |
4cc0665f | 7228 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7229 | break; |
4cc0665f MR |
7230 | addr -= MIPS_INSN16_SIZE; |
7231 | if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0)) | |
c8cef75f MR |
7232 | /* Looks like a JR/JALR at [target-1], but it could be |
7233 | the second word of a previous JAL/JALX, so record it | |
7234 | and check back one more. */ | |
7235 | jmpaddr = addr; | |
4cc0665f | 7236 | else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7237 | { |
7238 | if (i == 2) | |
7239 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7240 | be the second word of a previous JAL/JALX, record it, | |
7241 | and check back one more. */ | |
7242 | jmpaddr = addr; | |
7243 | else | |
7244 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7245 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7246 | ||
7247 | >-3: JAL | |
7248 | -2: JAL-ext (can't be JAL/JALX) | |
7249 | -1: bdslot (can't be JR/JALR) | |
7250 | 0: target insn | |
7251 | ||
7252 | Of course it could be another JAL-ext which looks | |
7253 | like a JAL, but in that case we'd have broken out | |
7254 | of this loop at [target-2]: | |
7255 | ||
7256 | -4: JAL | |
7257 | >-3: JAL-ext | |
7258 | -2: bdslot (can't be jmp) | |
7259 | -1: JR/JALR | |
7260 | 0: target insn */ | |
7261 | jmpaddr = 0; | |
7262 | } | |
7263 | else | |
7264 | { | |
7265 | /* Not a jump instruction: if we're at [target-1] this | |
7266 | could be the second word of a JAL/JALX, so continue; | |
7267 | otherwise we're done. */ | |
7268 | if (i > 1) | |
7269 | break; | |
7270 | } | |
7271 | } | |
7272 | ||
7273 | if (jmpaddr) | |
7274 | bpaddr = jmpaddr; | |
7275 | } | |
7276 | ||
7277 | return bpaddr; | |
7278 | } | |
7279 | ||
14132e89 MR |
7280 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7281 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7282 | ||
7283 | static int | |
7284 | mips_is_stub_suffix (const char *suffix, int zero) | |
7285 | { | |
7286 | switch (suffix[0]) | |
7287 | { | |
7288 | case '0': | |
7289 | return zero && suffix[1] == '\0'; | |
7290 | case '1': | |
7291 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7292 | case '2': | |
7293 | case '5': | |
7294 | case '6': | |
7295 | case '9': | |
7296 | return suffix[1] == '\0'; | |
7297 | default: | |
7298 | return 0; | |
7299 | } | |
7300 | } | |
7301 | ||
7302 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7303 | call stubs, one of sf, df, sc, or dc. */ | |
7304 | ||
7305 | static int | |
7306 | mips_is_stub_mode (const char *mode) | |
7307 | { | |
7308 | return ((mode[0] == 's' || mode[0] == 'd') | |
7309 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7310 | } | |
7311 | ||
7312 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7313 | bar might have a name like __fn_stub_bar, and might look like this: | |
7314 | ||
7315 | mfc1 $4, $f13 | |
7316 | mfc1 $5, $f12 | |
7317 | mfc1 $6, $f15 | |
7318 | mfc1 $7, $f14 | |
7319 | ||
7320 | followed by (or interspersed with): | |
7321 | ||
7322 | j bar | |
7323 | ||
7324 | or: | |
7325 | ||
7326 | lui $25, %hi(bar) | |
7327 | addiu $25, $25, %lo(bar) | |
7328 | jr $25 | |
7329 | ||
7330 | ($1 may be used in old code; for robustness we accept any register) | |
7331 | or, in PIC code: | |
7332 | ||
7333 | lui $28, %hi(_gp_disp) | |
7334 | addiu $28, $28, %lo(_gp_disp) | |
7335 | addu $28, $28, $25 | |
7336 | lw $25, %got(bar) | |
7337 | addiu $25, $25, %lo(bar) | |
7338 | jr $25 | |
7339 | ||
7340 | In the case of a __call_stub_bar stub, the sequence to set up | |
7341 | arguments might look like this: | |
7342 | ||
7343 | mtc1 $4, $f13 | |
7344 | mtc1 $5, $f12 | |
7345 | mtc1 $6, $f15 | |
7346 | mtc1 $7, $f14 | |
7347 | ||
7348 | followed by (or interspersed with) one of the jump sequences above. | |
7349 | ||
7350 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7351 | of J or JR, respectively, followed by: | |
7352 | ||
7353 | mfc1 $2, $f0 | |
7354 | mfc1 $3, $f1 | |
7355 | jr $18 | |
7356 | ||
7357 | We are at the beginning of the stub here, and scan down and extract | |
7358 | the target address from the jump immediate instruction or, if a jump | |
7359 | register instruction is used, from the register referred. Return | |
7360 | the value of PC calculated or 0 if inconclusive. | |
7361 | ||
7362 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7363 | ||
7364 | static CORE_ADDR | |
7365 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7366 | { | |
7367 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7368 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7369 | int addrreg = MIPS_ZERO_REGNUM; | |
7370 | CORE_ADDR start_pc = pc; | |
7371 | CORE_ADDR target_pc = 0; | |
7372 | CORE_ADDR addr = 0; | |
7373 | CORE_ADDR gp = 0; | |
7374 | int status = 0; | |
7375 | int i; | |
7376 | ||
7377 | for (i = 0; | |
7378 | status == 0 && target_pc == 0 && i < 20; | |
7379 | i++, pc += MIPS_INSN32_SIZE) | |
7380 | { | |
4cc0665f | 7381 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7382 | CORE_ADDR imm; |
7383 | int rt; | |
7384 | int rs; | |
7385 | int rd; | |
7386 | ||
7387 | switch (itype_op (inst)) | |
7388 | { | |
7389 | case 0: /* SPECIAL */ | |
7390 | switch (rtype_funct (inst)) | |
7391 | { | |
7392 | case 8: /* JR */ | |
7393 | case 9: /* JALR */ | |
7394 | rs = rtype_rs (inst); | |
7395 | if (rs == MIPS_GP_REGNUM) | |
7396 | target_pc = gp; /* Hmm... */ | |
7397 | else if (rs == addrreg) | |
7398 | target_pc = addr; | |
7399 | break; | |
7400 | ||
7401 | case 0x21: /* ADDU */ | |
7402 | rt = rtype_rt (inst); | |
7403 | rs = rtype_rs (inst); | |
7404 | rd = rtype_rd (inst); | |
7405 | if (rd == MIPS_GP_REGNUM | |
7406 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7407 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7408 | gp += start_pc; | |
7409 | break; | |
7410 | } | |
7411 | break; | |
7412 | ||
7413 | case 2: /* J */ | |
7414 | case 3: /* JAL */ | |
7415 | target_pc = jtype_target (inst) << 2; | |
7416 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7417 | break; | |
7418 | ||
7419 | case 9: /* ADDIU */ | |
7420 | rt = itype_rt (inst); | |
7421 | rs = itype_rs (inst); | |
7422 | if (rt == rs) | |
7423 | { | |
7424 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7425 | if (rt == MIPS_GP_REGNUM) | |
7426 | gp += imm; | |
7427 | else if (rt == addrreg) | |
7428 | addr += imm; | |
7429 | } | |
7430 | break; | |
7431 | ||
7432 | case 0xf: /* LUI */ | |
7433 | rt = itype_rt (inst); | |
7434 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7435 | if (rt == MIPS_GP_REGNUM) | |
7436 | gp = imm; | |
7437 | else if (rt != MIPS_ZERO_REGNUM) | |
7438 | { | |
7439 | addrreg = rt; | |
7440 | addr = imm; | |
7441 | } | |
7442 | break; | |
7443 | ||
7444 | case 0x23: /* LW */ | |
7445 | rt = itype_rt (inst); | |
7446 | rs = itype_rs (inst); | |
7447 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7448 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7449 | { | |
7450 | gdb_byte buf[4]; | |
7451 | ||
7452 | memset (buf, 0, sizeof (buf)); | |
7453 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7454 | addrreg = rt; | |
7455 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7456 | } | |
7457 | break; | |
7458 | } | |
7459 | } | |
7460 | ||
7461 | return target_pc; | |
7462 | } | |
7463 | ||
7464 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7465 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7466 | cases which must be handled: |
7467 | ||
14132e89 MR |
7468 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7469 | and the target PC is in $31 ($ra). | |
c906108c | 7470 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7471 | and the target PC is in $2. |
7472 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7473 | i.e. before the JALR instruction, this is effectively a call stub | |
7474 | and the target PC is in $2. Otherwise this is effectively | |
7475 | a return stub and the target PC is in $18. | |
7476 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7477 | JAL or JALR instruction, this is effectively a call stub and the | |
7478 | target PC is buried in the instruction stream. Otherwise this | |
7479 | is effectively a return stub and the target PC is in $18. | |
7480 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7481 | stub and the target PC is buried in the instruction stream. | |
7482 | ||
7483 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7484 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7485 | gory details. */ |
c906108c | 7486 | |
757a7cc6 | 7487 | static CORE_ADDR |
db5f024e | 7488 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7489 | { |
e17a4113 | 7490 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7491 | CORE_ADDR start_addr; |
14132e89 MR |
7492 | const char *name; |
7493 | size_t prefixlen; | |
c906108c SS |
7494 | |
7495 | /* Find the starting address and name of the function containing the PC. */ | |
7496 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7497 | return 0; | |
7498 | ||
14132e89 MR |
7499 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7500 | and the target PC is in $31 ($ra). */ | |
7501 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7502 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7503 | && mips_is_stub_mode (name + prefixlen) | |
7504 | && name[prefixlen + 2] == '\0') | |
7505 | return get_frame_register_signed | |
7506 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7507 | ||
7508 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7509 | call/return stubs. */ | |
7510 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7511 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7512 | { |
7513 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7514 | and the target PC is in $2. */ | |
14132e89 MR |
7515 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7516 | return get_frame_register_signed | |
7517 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7518 | |
14132e89 MR |
7519 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7520 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7521 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7522 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7523 | else if (mips_is_stub_mode (name + prefixlen) |
7524 | && name[prefixlen + 2] == '_' | |
7525 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7526 | { |
7527 | if (pc == start_addr) | |
14132e89 MR |
7528 | /* This is the 'call' part of a call stub. The return |
7529 | address is in $2. */ | |
7530 | return get_frame_register_signed | |
7531 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7532 | else |
7533 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7534 | address is in $18. */ |
7535 | return get_frame_register_signed | |
7536 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7537 | } |
14132e89 MR |
7538 | else |
7539 | return 0; /* Not a stub. */ | |
7540 | } | |
7541 | ||
7542 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7543 | compiler-generated call or call/return stubs. */ | |
7544 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 | |
7545 | || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
7546 | { | |
7547 | if (pc == start_addr) | |
7548 | /* This is the 'call' part of a call stub. Call this helper | |
7549 | to scan through this code for interesting instructions | |
7550 | and determine the final PC. */ | |
7551 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7552 | else | |
7553 | /* This is the 'return' part of a call stub. The return address | |
7554 | is in $18. */ | |
7555 | return get_frame_register_signed | |
7556 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7557 | } |
14132e89 MR |
7558 | |
7559 | return 0; /* Not a stub. */ | |
7560 | } | |
7561 | ||
7562 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7563 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7564 | ||
7565 | static int | |
7566 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7567 | { | |
7568 | CORE_ADDR start_addr; | |
7569 | size_t prefixlen; | |
7570 | ||
7571 | /* Find the starting address of the function containing the PC. */ | |
7572 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7573 | return 0; | |
7574 | ||
7575 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7576 | the start, i.e. after the JALR instruction, this is effectively | |
7577 | a return stub. */ | |
7578 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7579 | if (pc != start_addr | |
7580 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7581 | && mips_is_stub_mode (name + prefixlen) | |
7582 | && name[prefixlen + 2] == '_' | |
7583 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7584 | return 1; | |
7585 | ||
7586 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7587 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7588 | prefixlen = strlen (mips_str_call_fp_stub); | |
7589 | if (pc != start_addr | |
7590 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7591 | return 1; | |
7592 | ||
7593 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7594 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7595 | or the call stub path will trigger in handle_inferior_event causing | |
7596 | it to go astray. */ | |
7597 | prefixlen = strlen (mips_str_pic); | |
7598 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7599 | name += prefixlen; | |
7600 | ||
7601 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7602 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7603 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7604 | && mips_is_stub_mode (name + prefixlen) | |
7605 | && name[prefixlen + 2] == '\0') | |
7606 | return 1; | |
7607 | ||
7608 | return 0; /* Not a stub. */ | |
c906108c SS |
7609 | } |
7610 | ||
db5f024e DJ |
7611 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7612 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7613 | so that $t9 has the correct value at function entry. */ | |
7614 | ||
7615 | static CORE_ADDR | |
7616 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7617 | { | |
e17a4113 UW |
7618 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7619 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7620 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7621 | int i; |
7622 | gdb_byte stub_code[16]; | |
7623 | int32_t stub_words[4]; | |
7624 | ||
7625 | /* The stub for foo is named ".pic.foo", and is either two | |
7626 | instructions inserted before foo or a three instruction sequence | |
7627 | which jumps to foo. */ | |
7628 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7629 | if (msym.minsym == NULL |
77e371c0 | 7630 | || BMSYMBOL_VALUE_ADDRESS (msym) != pc |
efd66ac6 TT |
7631 | || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL |
7632 | || strncmp (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.", 5) != 0) | |
db5f024e DJ |
7633 | return 0; |
7634 | ||
7635 | /* A two-instruction header. */ | |
7cbd4a93 | 7636 | if (MSYMBOL_SIZE (msym.minsym) == 8) |
db5f024e DJ |
7637 | return pc + 8; |
7638 | ||
7639 | /* A three-instruction (plus delay slot) trampoline. */ | |
7cbd4a93 | 7640 | if (MSYMBOL_SIZE (msym.minsym) == 16) |
db5f024e DJ |
7641 | { |
7642 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7643 | return 0; | |
7644 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7645 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7646 | 4, byte_order); | |
db5f024e DJ |
7647 | |
7648 | /* A stub contains these instructions: | |
7649 | lui t9, %hi(target) | |
7650 | j target | |
7651 | addiu t9, t9, %lo(target) | |
7652 | nop | |
7653 | ||
7654 | This works even for N64, since stubs are only generated with | |
7655 | -msym32. */ | |
7656 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7657 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7658 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7659 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7660 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7661 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7662 | } |
7663 | ||
7664 | /* Not a recognized stub. */ | |
7665 | return 0; | |
7666 | } | |
7667 | ||
7668 | static CORE_ADDR | |
7669 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7670 | { | |
14132e89 | 7671 | CORE_ADDR requested_pc = pc; |
db5f024e | 7672 | CORE_ADDR target_pc; |
14132e89 MR |
7673 | CORE_ADDR new_pc; |
7674 | ||
7675 | do | |
7676 | { | |
7677 | target_pc = pc; | |
db5f024e | 7678 | |
14132e89 MR |
7679 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7680 | if (new_pc) | |
7681 | { | |
7682 | pc = new_pc; | |
4cc0665f MR |
7683 | if (is_compact_addr (pc)) |
7684 | pc = unmake_compact_addr (pc); | |
14132e89 | 7685 | } |
db5f024e | 7686 | |
14132e89 MR |
7687 | new_pc = find_solib_trampoline_target (frame, pc); |
7688 | if (new_pc) | |
7689 | { | |
7690 | pc = new_pc; | |
4cc0665f MR |
7691 | if (is_compact_addr (pc)) |
7692 | pc = unmake_compact_addr (pc); | |
14132e89 | 7693 | } |
db5f024e | 7694 | |
14132e89 MR |
7695 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7696 | if (new_pc) | |
7697 | { | |
7698 | pc = new_pc; | |
4cc0665f MR |
7699 | if (is_compact_addr (pc)) |
7700 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
7701 | } |
7702 | } | |
7703 | while (pc != target_pc); | |
db5f024e | 7704 | |
14132e89 | 7705 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7706 | } |
7707 | ||
a4b8ebc8 | 7708 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7709 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7710 | |
7711 | static int | |
d3f73121 | 7712 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7713 | { |
a4b8ebc8 | 7714 | int regnum; |
2f38ef89 | 7715 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7716 | regnum = num; |
2f38ef89 | 7717 | else if (num >= 38 && num < 70) |
d3f73121 | 7718 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7719 | else if (num == 70) |
d3f73121 | 7720 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7721 | else if (num == 71) |
d3f73121 | 7722 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7723 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7724 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7725 | else |
a4b8ebc8 AC |
7726 | /* This will hopefully (eventually) provoke a warning. Should |
7727 | we be calling complaint() here? */ | |
d3f73121 MD |
7728 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7729 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
7730 | } |
7731 | ||
2f38ef89 | 7732 | |
a4b8ebc8 | 7733 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7734 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7735 | |
7736 | static int | |
d3f73121 | 7737 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7738 | { |
a4b8ebc8 | 7739 | int regnum; |
2f38ef89 | 7740 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7741 | regnum = num; |
2f38ef89 | 7742 | else if (num >= 32 && num < 64) |
d3f73121 | 7743 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7744 | else if (num == 64) |
d3f73121 | 7745 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7746 | else if (num == 65) |
d3f73121 | 7747 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7748 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7749 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7750 | else |
a4b8ebc8 AC |
7751 | /* This will hopefully (eventually) provoke a warning. Should we |
7752 | be calling complaint() here? */ | |
d3f73121 MD |
7753 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7754 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
7755 | } |
7756 | ||
7757 | static int | |
e7faf938 | 7758 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7759 | { |
7760 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7761 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7762 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7763 | decide if it is valid. Should instead define a standard sim/gdb | |
7764 | register numbering scheme. */ | |
e7faf938 MD |
7765 | if (gdbarch_register_name (gdbarch, |
7766 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7767 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7768 | gdbarch_num_regs (gdbarch) |
7769 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7770 | return regnum; |
7771 | else | |
6d82d43b | 7772 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7773 | } |
7774 | ||
2f38ef89 | 7775 | |
4844f454 CV |
7776 | /* Convert an integer into an address. Extracting the value signed |
7777 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7778 | |
7779 | static CORE_ADDR | |
79dd2d24 | 7780 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7781 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7782 | { |
e17a4113 UW |
7783 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7784 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7785 | } |
7786 | ||
82e91389 DJ |
7787 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7788 | than most other architectures; we just need to be explicit about it, | |
7789 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7790 | an assertion failure. */ | |
7791 | ||
7792 | static void | |
a54fba4c MD |
7793 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7794 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7795 | { |
7796 | *reg = MIPS_SP_REGNUM; | |
7797 | *offset = 0; | |
7798 | } | |
7799 | ||
caaa3122 DJ |
7800 | static void |
7801 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7802 | { | |
7803 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7804 | const char *name = bfd_get_section_name (abfd, sect); | |
7805 | ||
7806 | if (*abip != MIPS_ABI_UNKNOWN) | |
7807 | return; | |
7808 | ||
7809 | if (strncmp (name, ".mdebug.", 8) != 0) | |
7810 | return; | |
7811 | ||
7812 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7813 | *abip = MIPS_ABI_O32; | |
7814 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7815 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7816 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7817 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7818 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7819 | *abip = MIPS_ABI_O64; | |
7820 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7821 | *abip = MIPS_ABI_EABI32; | |
7822 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7823 | *abip = MIPS_ABI_EABI64; | |
7824 | else | |
8a3fe4f8 | 7825 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7826 | } |
7827 | ||
22e47e37 FF |
7828 | static void |
7829 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
7830 | { | |
7831 | int *lbp = (int *) obj; | |
7832 | const char *name = bfd_get_section_name (abfd, sect); | |
7833 | ||
7834 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
7835 | *lbp = 32; | |
7836 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
7837 | *lbp = 64; | |
7838 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
7839 | warning (_("unrecognized .gcc_compiled_longXX")); | |
7840 | } | |
7841 | ||
2e4ebe70 DJ |
7842 | static enum mips_abi |
7843 | global_mips_abi (void) | |
7844 | { | |
7845 | int i; | |
7846 | ||
7847 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
7848 | if (mips_abi_strings[i] == mips_abi_string) | |
7849 | return (enum mips_abi) i; | |
7850 | ||
e2e0b3e5 | 7851 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
7852 | } |
7853 | ||
4cc0665f MR |
7854 | /* Return the default compressed instruction set, either of MIPS16 |
7855 | or microMIPS, selected when none could have been determined from | |
7856 | the ELF header of the binary being executed (or no binary has been | |
7857 | selected. */ | |
7858 | ||
7859 | static enum mips_isa | |
7860 | global_mips_compression (void) | |
7861 | { | |
7862 | int i; | |
7863 | ||
7864 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
7865 | if (mips_compression_strings[i] == mips_compression_string) | |
7866 | return (enum mips_isa) i; | |
7867 | ||
7868 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
7869 | } | |
7870 | ||
29709017 DJ |
7871 | static void |
7872 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
7873 | { | |
29709017 DJ |
7874 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
7875 | assume that's what we've got. */ | |
4eb0ad19 DJ |
7876 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
7877 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7878 | |
7879 | /* If the size matches the full set of registers GDB traditionally | |
7880 | knows about, including floating point, for either 32-bit or | |
7881 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
7882 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
7883 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7884 | |
7885 | /* Otherwise we don't have a useful guess. */ | |
7886 | } | |
7887 | ||
f8b73d13 DJ |
7888 | static struct value * |
7889 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
7890 | { | |
7891 | const int *reg_p = baton; | |
7892 | return value_of_register (*reg_p, frame); | |
7893 | } | |
7894 | ||
c2d11a7d | 7895 | static struct gdbarch * |
6d82d43b | 7896 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 7897 | { |
c2d11a7d JM |
7898 | struct gdbarch *gdbarch; |
7899 | struct gdbarch_tdep *tdep; | |
7900 | int elf_flags; | |
2e4ebe70 | 7901 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 7902 | int i, num_regs; |
8d5838b5 | 7903 | enum mips_fpu_type fpu_type; |
f8b73d13 | 7904 | struct tdesc_arch_data *tdesc_data = NULL; |
d929bc19 | 7905 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
1faeff08 MR |
7906 | const char **reg_names; |
7907 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 7908 | enum mips_isa mips_isa; |
1faeff08 MR |
7909 | int dspacc; |
7910 | int dspctl; | |
7911 | ||
7912 | /* Fill in the OS dependent register numbers and names. */ | |
7913 | if (info.osabi == GDB_OSABI_IRIX) | |
7914 | { | |
7915 | mips_regnum.fp0 = 32; | |
7916 | mips_regnum.pc = 64; | |
7917 | mips_regnum.cause = 65; | |
7918 | mips_regnum.badvaddr = 66; | |
7919 | mips_regnum.hi = 67; | |
7920 | mips_regnum.lo = 68; | |
7921 | mips_regnum.fp_control_status = 69; | |
7922 | mips_regnum.fp_implementation_revision = 70; | |
7923 | mips_regnum.dspacc = dspacc = -1; | |
7924 | mips_regnum.dspctl = dspctl = -1; | |
7925 | num_regs = 71; | |
7926 | reg_names = mips_irix_reg_names; | |
7927 | } | |
7928 | else if (info.osabi == GDB_OSABI_LINUX) | |
7929 | { | |
7930 | mips_regnum.fp0 = 38; | |
7931 | mips_regnum.pc = 37; | |
7932 | mips_regnum.cause = 36; | |
7933 | mips_regnum.badvaddr = 35; | |
7934 | mips_regnum.hi = 34; | |
7935 | mips_regnum.lo = 33; | |
7936 | mips_regnum.fp_control_status = 70; | |
7937 | mips_regnum.fp_implementation_revision = 71; | |
7938 | mips_regnum.dspacc = -1; | |
7939 | mips_regnum.dspctl = -1; | |
7940 | dspacc = 72; | |
7941 | dspctl = 78; | |
7942 | num_regs = 79; | |
7943 | reg_names = mips_linux_reg_names; | |
7944 | } | |
7945 | else | |
7946 | { | |
7947 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
7948 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
7949 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
7950 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
7951 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
7952 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
7953 | mips_regnum.fp_control_status = 70; | |
7954 | mips_regnum.fp_implementation_revision = 71; | |
7955 | mips_regnum.dspacc = dspacc = -1; | |
7956 | mips_regnum.dspctl = dspctl = -1; | |
7957 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
7958 | if (info.bfd_arch_info != NULL | |
7959 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
7960 | reg_names = mips_tx39_reg_names; | |
7961 | else | |
7962 | reg_names = mips_generic_reg_names; | |
7963 | } | |
f8b73d13 DJ |
7964 | |
7965 | /* Check any target description for validity. */ | |
7966 | if (tdesc_has_registers (info.target_desc)) | |
7967 | { | |
7968 | static const char *const mips_gprs[] = { | |
7969 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
7970 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
7971 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
7972 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
7973 | }; | |
7974 | static const char *const mips_fprs[] = { | |
7975 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
7976 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
7977 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
7978 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
7979 | }; | |
7980 | ||
7981 | const struct tdesc_feature *feature; | |
7982 | int valid_p; | |
7983 | ||
7984 | feature = tdesc_find_feature (info.target_desc, | |
7985 | "org.gnu.gdb.mips.cpu"); | |
7986 | if (feature == NULL) | |
7987 | return NULL; | |
7988 | ||
7989 | tdesc_data = tdesc_data_alloc (); | |
7990 | ||
7991 | valid_p = 1; | |
7992 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
7993 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
7994 | mips_gprs[i]); | |
7995 | ||
7996 | ||
7997 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7998 | mips_regnum.lo, "lo"); |
f8b73d13 | 7999 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8000 | mips_regnum.hi, "hi"); |
f8b73d13 | 8001 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 8002 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
8003 | |
8004 | if (!valid_p) | |
8005 | { | |
8006 | tdesc_data_cleanup (tdesc_data); | |
8007 | return NULL; | |
8008 | } | |
8009 | ||
8010 | feature = tdesc_find_feature (info.target_desc, | |
8011 | "org.gnu.gdb.mips.cp0"); | |
8012 | if (feature == NULL) | |
8013 | { | |
8014 | tdesc_data_cleanup (tdesc_data); | |
8015 | return NULL; | |
8016 | } | |
8017 | ||
8018 | valid_p = 1; | |
8019 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8020 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
8021 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
8022 | MIPS_PS_REGNUM, "status"); | |
8023 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8024 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
8025 | |
8026 | if (!valid_p) | |
8027 | { | |
8028 | tdesc_data_cleanup (tdesc_data); | |
8029 | return NULL; | |
8030 | } | |
8031 | ||
8032 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8033 | backend is not prepared for that, though. */ | |
8034 | feature = tdesc_find_feature (info.target_desc, | |
8035 | "org.gnu.gdb.mips.fpu"); | |
8036 | if (feature == NULL) | |
8037 | { | |
8038 | tdesc_data_cleanup (tdesc_data); | |
8039 | return NULL; | |
8040 | } | |
8041 | ||
8042 | valid_p = 1; | |
8043 | for (i = 0; i < 32; i++) | |
8044 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8045 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8046 | |
8047 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8048 | mips_regnum.fp_control_status, |
8049 | "fcsr"); | |
8050 | valid_p | |
8051 | &= tdesc_numbered_register (feature, tdesc_data, | |
8052 | mips_regnum.fp_implementation_revision, | |
8053 | "fir"); | |
f8b73d13 DJ |
8054 | |
8055 | if (!valid_p) | |
8056 | { | |
8057 | tdesc_data_cleanup (tdesc_data); | |
8058 | return NULL; | |
8059 | } | |
8060 | ||
1faeff08 MR |
8061 | if (dspacc >= 0) |
8062 | { | |
8063 | feature = tdesc_find_feature (info.target_desc, | |
8064 | "org.gnu.gdb.mips.dsp"); | |
8065 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8066 | if (feature != NULL) | |
8067 | { | |
8068 | i = 0; | |
8069 | valid_p = 1; | |
8070 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8071 | dspacc + i++, "hi1"); | |
8072 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8073 | dspacc + i++, "lo1"); | |
8074 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8075 | dspacc + i++, "hi2"); | |
8076 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8077 | dspacc + i++, "lo2"); | |
8078 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8079 | dspacc + i++, "hi3"); | |
8080 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8081 | dspacc + i++, "lo3"); | |
8082 | ||
8083 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8084 | dspctl, "dspctl"); | |
8085 | ||
8086 | if (!valid_p) | |
8087 | { | |
8088 | tdesc_data_cleanup (tdesc_data); | |
8089 | return NULL; | |
8090 | } | |
8091 | ||
8092 | mips_regnum.dspacc = dspacc; | |
8093 | mips_regnum.dspctl = dspctl; | |
8094 | } | |
8095 | } | |
8096 | ||
f8b73d13 DJ |
8097 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8098 | when only 32-bit registers are provided. */ | |
1faeff08 | 8099 | reg_names = NULL; |
f8b73d13 | 8100 | } |
c2d11a7d | 8101 | |
ec03c1ac AC |
8102 | /* First of all, extract the elf_flags, if available. */ |
8103 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8104 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8105 | else if (arches != NULL) |
8106 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8107 | else |
8108 | elf_flags = 0; | |
8109 | if (gdbarch_debug) | |
8110 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8111 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8112 | |
102182a9 | 8113 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8114 | switch ((elf_flags & EF_MIPS_ABI)) |
8115 | { | |
8116 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8117 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8118 | break; |
8119 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8120 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8121 | break; |
8122 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8123 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8124 | break; |
8125 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8126 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8127 | break; |
8128 | default: | |
acdb74a0 | 8129 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8130 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8131 | else |
ec03c1ac | 8132 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8133 | break; |
8134 | } | |
acdb74a0 | 8135 | |
caaa3122 | 8136 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8137 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8138 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8139 | |
dc305454 | 8140 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8141 | MIPS architecture (if there is one). */ |
8142 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8143 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8144 | |
32a6503c | 8145 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8146 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8147 | && info.bfd_arch_info != NULL |
8148 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8149 | { | |
8150 | switch (info.bfd_arch_info->mach) | |
8151 | { | |
8152 | case bfd_mach_mips3900: | |
ec03c1ac | 8153 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8154 | break; |
8155 | case bfd_mach_mips4100: | |
8156 | case bfd_mach_mips5000: | |
ec03c1ac | 8157 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8158 | break; |
1d06468c EZ |
8159 | case bfd_mach_mips8000: |
8160 | case bfd_mach_mips10000: | |
32a6503c KB |
8161 | /* On Irix, ELF64 executables use the N64 ABI. The |
8162 | pseudo-sections which describe the ABI aren't present | |
8163 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
8164 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
8165 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 8166 | found_abi = MIPS_ABI_N64; |
28d169de | 8167 | else |
ec03c1ac | 8168 | found_abi = MIPS_ABI_N32; |
1d06468c | 8169 | break; |
bf64bfd6 AC |
8170 | } |
8171 | } | |
2e4ebe70 | 8172 | |
26c53e50 DJ |
8173 | /* Default 64-bit objects to N64 instead of O32. */ |
8174 | if (found_abi == MIPS_ABI_UNKNOWN | |
8175 | && info.abfd != NULL | |
8176 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8177 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8178 | found_abi = MIPS_ABI_N64; | |
8179 | ||
ec03c1ac AC |
8180 | if (gdbarch_debug) |
8181 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8182 | found_abi); | |
8183 | ||
8184 | /* What has the user specified from the command line? */ | |
8185 | wanted_abi = global_mips_abi (); | |
8186 | if (gdbarch_debug) | |
8187 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8188 | wanted_abi); | |
2e4ebe70 DJ |
8189 | |
8190 | /* Now that we have found what the ABI for this binary would be, | |
8191 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8192 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8193 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8194 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8195 | mips_abi = found_abi; | |
8196 | else | |
8197 | mips_abi = MIPS_ABI_O32; | |
8198 | if (gdbarch_debug) | |
8199 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8200 | mips_abi); | |
2e4ebe70 | 8201 | |
4cc0665f MR |
8202 | /* Determine the default compressed ISA. */ |
8203 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8204 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8205 | mips_isa = ISA_MICROMIPS; | |
8206 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8207 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8208 | mips_isa = ISA_MIPS16; | |
8209 | else | |
8210 | mips_isa = global_mips_compression (); | |
8211 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8212 | ||
ec03c1ac | 8213 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8214 | if (gdbarch_debug) |
ec03c1ac | 8215 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8216 | "mips_gdbarch_init: " |
8217 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8218 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8219 | |
8d5838b5 | 8220 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8221 | #ifdef HAVE_ELF |
8222 | if (info.abfd | |
8223 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8224 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8225 | Tag_GNU_MIPS_ABI_FP); | |
8226 | #endif /* HAVE_ELF */ | |
8227 | ||
8d5838b5 AC |
8228 | if (!mips_fpu_type_auto) |
8229 | fpu_type = mips_fpu_type; | |
d929bc19 | 8230 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8231 | { |
8232 | switch (elf_fpu_type) | |
8233 | { | |
d929bc19 | 8234 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8235 | fpu_type = MIPS_FPU_DOUBLE; |
8236 | break; | |
d929bc19 | 8237 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8238 | fpu_type = MIPS_FPU_SINGLE; |
8239 | break; | |
d929bc19 | 8240 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8241 | default: |
8242 | /* Soft float or unknown. */ | |
8243 | fpu_type = MIPS_FPU_NONE; | |
8244 | break; | |
8245 | } | |
8246 | } | |
8d5838b5 AC |
8247 | else if (info.bfd_arch_info != NULL |
8248 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8249 | switch (info.bfd_arch_info->mach) | |
8250 | { | |
8251 | case bfd_mach_mips3900: | |
8252 | case bfd_mach_mips4100: | |
8253 | case bfd_mach_mips4111: | |
a9d61c86 | 8254 | case bfd_mach_mips4120: |
8d5838b5 AC |
8255 | fpu_type = MIPS_FPU_NONE; |
8256 | break; | |
8257 | case bfd_mach_mips4650: | |
8258 | fpu_type = MIPS_FPU_SINGLE; | |
8259 | break; | |
8260 | default: | |
8261 | fpu_type = MIPS_FPU_DOUBLE; | |
8262 | break; | |
8263 | } | |
8264 | else if (arches != NULL) | |
8265 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
8266 | else | |
8267 | fpu_type = MIPS_FPU_DOUBLE; | |
8268 | if (gdbarch_debug) | |
8269 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8270 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8271 | |
29709017 DJ |
8272 | /* Check for blatant incompatibilities. */ |
8273 | ||
8274 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8275 | ABI. */ | |
8276 | if (info.target_desc | |
8277 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8278 | && mips_abi != MIPS_ABI_EABI32 | |
8279 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8280 | { |
8281 | if (tdesc_data != NULL) | |
8282 | tdesc_data_cleanup (tdesc_data); | |
8283 | return NULL; | |
8284 | } | |
29709017 | 8285 | |
025bb325 | 8286 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8287 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8288 | arches != NULL; | |
8289 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8290 | { | |
d54398a7 MR |
8291 | /* MIPS needs to be pedantic about which ABI and the compressed |
8292 | ISA variation the object is using. */ | |
9103eae0 | 8293 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8294 | continue; |
9103eae0 | 8295 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8296 | continue; |
d54398a7 MR |
8297 | if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) |
8298 | continue; | |
719ec221 AC |
8299 | /* Need to be pedantic about which register virtual size is |
8300 | used. */ | |
8301 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8302 | != mips64_transfers_32bit_regs_p) | |
8303 | continue; | |
8d5838b5 AC |
8304 | /* Be pedantic about which FPU is selected. */ |
8305 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
8306 | continue; | |
f8b73d13 DJ |
8307 | |
8308 | if (tdesc_data != NULL) | |
8309 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8310 | return arches->gdbarch; |
c2d11a7d JM |
8311 | } |
8312 | ||
102182a9 | 8313 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
8314 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
8315 | gdbarch = gdbarch_alloc (&info, tdep); | |
8316 | tdep->elf_flags = elf_flags; | |
719ec221 | 8317 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8318 | tdep->found_abi = found_abi; |
8319 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8320 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8321 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8322 | tdep->register_size_valid_p = 0; |
8323 | tdep->register_size = 0; | |
8324 | ||
8325 | if (info.target_desc) | |
8326 | { | |
8327 | /* Some useful properties can be inferred from the target. */ | |
8328 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8329 | { | |
8330 | tdep->register_size_valid_p = 1; | |
8331 | tdep->register_size = 4; | |
8332 | } | |
8333 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8334 | { | |
8335 | tdep->register_size_valid_p = 1; | |
8336 | tdep->register_size = 8; | |
8337 | } | |
8338 | } | |
c2d11a7d | 8339 | |
102182a9 | 8340 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8341 | set_gdbarch_short_bit (gdbarch, 16); |
8342 | set_gdbarch_int_bit (gdbarch, 32); | |
8343 | set_gdbarch_float_bit (gdbarch, 32); | |
8344 | set_gdbarch_double_bit (gdbarch, 64); | |
8345 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8346 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8347 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8348 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8349 | |
175ff332 HZ |
8350 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8351 | mips_ax_pseudo_register_collect); | |
8352 | set_gdbarch_ax_pseudo_register_push_stack | |
8353 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8354 | ||
6d82d43b | 8355 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
8356 | mips_elf_make_msymbol_special); |
8357 | ||
1faeff08 MR |
8358 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8359 | *regnum = mips_regnum; | |
1faeff08 MR |
8360 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8361 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8362 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8363 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8364 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8365 | tdep->mips_processor_reg_names = reg_names; | |
8366 | tdep->regnum = regnum; | |
fe29b929 | 8367 | |
0dadbba0 | 8368 | switch (mips_abi) |
c2d11a7d | 8369 | { |
0dadbba0 | 8370 | case MIPS_ABI_O32: |
25ab4790 | 8371 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8372 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8373 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8374 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8375 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8376 | set_gdbarch_long_bit (gdbarch, 32); |
8377 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8378 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8379 | break; | |
0dadbba0 | 8380 | case MIPS_ABI_O64: |
25ab4790 | 8381 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8382 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8383 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8384 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8385 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8386 | set_gdbarch_long_bit (gdbarch, 32); |
8387 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8388 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8389 | break; | |
0dadbba0 | 8390 | case MIPS_ABI_EABI32: |
25ab4790 | 8391 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8392 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8393 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8394 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8395 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8396 | set_gdbarch_long_bit (gdbarch, 32); |
8397 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8398 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8399 | break; | |
0dadbba0 | 8400 | case MIPS_ABI_EABI64: |
25ab4790 | 8401 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8402 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8403 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8404 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8405 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8406 | set_gdbarch_long_bit (gdbarch, 64); |
8407 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8408 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8409 | break; | |
0dadbba0 | 8410 | case MIPS_ABI_N32: |
25ab4790 | 8411 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8412 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8413 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8414 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8415 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8416 | set_gdbarch_long_bit (gdbarch, 32); |
8417 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8418 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8419 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8420 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8421 | break; |
8422 | case MIPS_ABI_N64: | |
25ab4790 | 8423 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8424 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8425 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8426 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8427 | tdep->default_mask_address_p = 0; |
8428 | set_gdbarch_long_bit (gdbarch, 64); | |
8429 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8430 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8431 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8432 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8433 | break; |
c2d11a7d | 8434 | default: |
e2e0b3e5 | 8435 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8436 | } |
8437 | ||
22e47e37 FF |
8438 | /* GCC creates a pseudo-section whose name specifies the size of |
8439 | longs, since -mlong32 or -mlong64 may be used independent of | |
8440 | other options. How those options affect pointer sizes is ABI and | |
8441 | architecture dependent, so use them to override the default sizes | |
8442 | set by the ABI. This table shows the relationship between ABI, | |
8443 | -mlongXX, and size of pointers: | |
8444 | ||
8445 | ABI -mlongXX ptr bits | |
8446 | --- -------- -------- | |
8447 | o32 32 32 | |
8448 | o32 64 32 | |
8449 | n32 32 32 | |
8450 | n32 64 64 | |
8451 | o64 32 32 | |
8452 | o64 64 64 | |
8453 | n64 32 32 | |
8454 | n64 64 64 | |
8455 | eabi32 32 32 | |
8456 | eabi32 64 32 | |
8457 | eabi64 32 32 | |
8458 | eabi64 64 64 | |
8459 | ||
8460 | Note that for o32 and eabi32, pointers are always 32 bits | |
8461 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8462 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8463 | |
8464 | if (info.abfd != NULL) | |
8465 | { | |
8466 | int long_bit = 0; | |
8467 | ||
8468 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8469 | if (long_bit) | |
8470 | { | |
8471 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8472 | switch (mips_abi) | |
8473 | { | |
8474 | case MIPS_ABI_O32: | |
8475 | case MIPS_ABI_EABI32: | |
8476 | break; | |
8477 | case MIPS_ABI_N32: | |
8478 | case MIPS_ABI_O64: | |
8479 | case MIPS_ABI_N64: | |
8480 | case MIPS_ABI_EABI64: | |
8481 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8482 | break; | |
8483 | default: | |
8484 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8485 | } | |
8486 | } | |
8487 | } | |
8488 | ||
a5ea2558 AC |
8489 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8490 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8491 | comment: | |
8492 | ||
8493 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8494 | flag in object files because to do so would make it impossible to | |
102182a9 | 8495 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8496 | unnecessarily restrictive. |
361d1df0 | 8497 | |
a5ea2558 AC |
8498 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8499 | but to set this flag before gcc is built with such multilibs will | |
8500 | break too many systems.'' | |
8501 | ||
8502 | But even more unhelpfully, the default linker output target for | |
8503 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8504 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8505 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8506 | this flag to detect 32-bit mode would do the wrong thing given |
8507 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8508 | as 32-bit programs by default. */ |
a5ea2558 | 8509 | |
6c997a34 | 8510 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8511 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8512 | |
102182a9 MS |
8513 | /* Add/remove bits from an address. The MIPS needs be careful to |
8514 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8515 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8516 | ||
58dfe9ff AC |
8517 | /* Unwind the frame. */ |
8518 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8519 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8520 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8521 | |
102182a9 | 8522 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8523 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8524 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8525 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8526 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8527 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8528 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8529 | |
025bb325 | 8530 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8531 | |
2c76a0c7 JB |
8532 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8533 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8534 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8535 | |
87783b8b AC |
8536 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8537 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8538 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8539 | ||
f7b9e9fc AC |
8540 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
8541 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4cc0665f MR |
8542 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
8543 | mips_remote_breakpoint_from_pc); | |
c8cef75f MR |
8544 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8545 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8546 | |
8547 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8548 | |
97ab0fdd MR |
8549 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
8550 | ||
fc0c74b1 AC |
8551 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8552 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8553 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8554 | |
a4b8ebc8 | 8555 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8556 | |
e11c53d2 | 8557 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8558 | |
9dae60cc UW |
8559 | if (mips_abi == MIPS_ABI_N32) |
8560 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8561 | else if (mips_abi == MIPS_ABI_N64) | |
8562 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8563 | else | |
8564 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8565 | |
d92524f1 PM |
8566 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8567 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8568 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8569 | being used as guards for target_stopped_by_watchpoint, why not have |
8570 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8571 | is sitting on? */ |
8572 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8573 | ||
e7d6a6d2 | 8574 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8575 | |
14132e89 MR |
8576 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8577 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8578 | if we have an OS ABI that actually supports shared libraries, since | |
8579 | shared library support is more important. If we have an OS someday | |
8580 | that supports both shared libraries and MIPS16, we'll have to find | |
8581 | a better place for these. | |
8582 | macro/2012-04-25: But that applies to return trampolines only and | |
8583 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8584 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8585 | ||
025bb325 MS |
8586 | set_gdbarch_single_step_through_delay (gdbarch, |
8587 | mips_single_step_through_delay); | |
3352ef37 | 8588 | |
0d5de010 DJ |
8589 | /* Virtual tables. */ |
8590 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8591 | ||
29709017 DJ |
8592 | mips_register_g_packet_guesses (gdbarch); |
8593 | ||
6de918a6 | 8594 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 8595 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 8596 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8597 | |
9aac7884 MR |
8598 | /* The hook may have adjusted num_regs, fetch the final value and |
8599 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8600 | num_regs = gdbarch_num_regs (gdbarch); |
8601 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8602 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8603 | ||
5792a79b | 8604 | /* Unwind the frame. */ |
b8a22b94 DJ |
8605 | dwarf2_append_unwinders (gdbarch); |
8606 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8607 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8608 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8609 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8610 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8611 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8612 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8613 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8614 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8615 | |
f8b73d13 DJ |
8616 | if (tdesc_data) |
8617 | { | |
8618 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8619 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8620 | |
8621 | /* Override the normal target description methods to handle our | |
8622 | dual real and pseudo registers. */ | |
8623 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8624 | set_gdbarch_register_reggroup_p (gdbarch, |
8625 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8626 | |
8627 | num_regs = gdbarch_num_regs (gdbarch); | |
8628 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8629 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8630 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8631 | } | |
8632 | ||
8633 | /* Add ABI-specific aliases for the registers. */ | |
8634 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8635 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8636 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8637 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8638 | else | |
8639 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8640 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8641 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8642 | ||
8643 | /* Add some other standard aliases. */ | |
8644 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8645 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8646 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8647 | ||
865093a3 AR |
8648 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8649 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8650 | value_of_mips_user_reg, | |
8651 | &mips_numeric_register_aliases[i].regnum); | |
8652 | ||
4b9b3959 AC |
8653 | return gdbarch; |
8654 | } | |
8655 | ||
2e4ebe70 | 8656 | static void |
6d82d43b | 8657 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
8658 | { |
8659 | struct gdbarch_info info; | |
8660 | ||
8661 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8662 | mips_gdbarch_init will take care of the rest. */ | |
8663 | gdbarch_info_init (&info); | |
8664 | gdbarch_update_p (info); | |
8665 | } | |
8666 | ||
ad188201 KB |
8667 | /* Print out which MIPS ABI is in use. */ |
8668 | ||
8669 | static void | |
1f8ca57c JB |
8670 | show_mips_abi (struct ui_file *file, |
8671 | int from_tty, | |
8672 | struct cmd_list_element *ignored_cmd, | |
8673 | const char *ignored_value) | |
ad188201 | 8674 | { |
f5656ead | 8675 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1f8ca57c JB |
8676 | fprintf_filtered |
8677 | (file, | |
8678 | "The MIPS ABI is unknown because the current architecture " | |
8679 | "is not MIPS.\n"); | |
ad188201 KB |
8680 | else |
8681 | { | |
8682 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8683 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8684 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8685 | ||
8686 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8687 | fprintf_filtered |
8688 | (file, | |
8689 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8690 | actual_abi_str); |
ad188201 | 8691 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8692 | fprintf_filtered |
8693 | (file, | |
8694 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8695 | actual_abi_str); |
ad188201 KB |
8696 | else |
8697 | { | |
8698 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8699 | fprintf_filtered (file, |
8700 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8701 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8702 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8703 | } |
8704 | } | |
8705 | } | |
8706 | ||
4cc0665f MR |
8707 | /* Print out which MIPS compressed ISA encoding is used. */ |
8708 | ||
8709 | static void | |
8710 | show_mips_compression (struct ui_file *file, int from_tty, | |
8711 | struct cmd_list_element *c, const char *value) | |
8712 | { | |
8713 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8714 | value); | |
8715 | } | |
8716 | ||
4b9b3959 | 8717 | static void |
72a155b4 | 8718 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8719 | { |
72a155b4 | 8720 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8721 | if (tdep != NULL) |
c2d11a7d | 8722 | { |
acdb74a0 AC |
8723 | int ef_mips_arch; |
8724 | int ef_mips_32bitmode; | |
f49e4e6d | 8725 | /* Determine the ISA. */ |
acdb74a0 AC |
8726 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8727 | { | |
8728 | case E_MIPS_ARCH_1: | |
8729 | ef_mips_arch = 1; | |
8730 | break; | |
8731 | case E_MIPS_ARCH_2: | |
8732 | ef_mips_arch = 2; | |
8733 | break; | |
8734 | case E_MIPS_ARCH_3: | |
8735 | ef_mips_arch = 3; | |
8736 | break; | |
8737 | case E_MIPS_ARCH_4: | |
93d56215 | 8738 | ef_mips_arch = 4; |
acdb74a0 AC |
8739 | break; |
8740 | default: | |
93d56215 | 8741 | ef_mips_arch = 0; |
acdb74a0 AC |
8742 | break; |
8743 | } | |
f49e4e6d | 8744 | /* Determine the size of a pointer. */ |
acdb74a0 | 8745 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8746 | fprintf_unfiltered (file, |
8747 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8748 | tdep->elf_flags); |
4b9b3959 | 8749 | fprintf_unfiltered (file, |
acdb74a0 AC |
8750 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8751 | ef_mips_32bitmode); | |
8752 | fprintf_unfiltered (file, | |
8753 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8754 | ef_mips_arch); | |
8755 | fprintf_unfiltered (file, | |
8756 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8757 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8758 | fprintf_unfiltered (file, |
025bb325 MS |
8759 | "mips_dump_tdep: " |
8760 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8761 | mips_mask_address_p (tdep), |
4014092b | 8762 | tdep->default_mask_address_p); |
c2d11a7d | 8763 | } |
4b9b3959 AC |
8764 | fprintf_unfiltered (file, |
8765 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8766 | MIPS_DEFAULT_FPU_TYPE, | |
8767 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
8768 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
8769 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
8770 | : "???")); | |
74ed0bb4 MD |
8771 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8772 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8773 | fprintf_unfiltered (file, |
8774 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
8775 | MIPS_FPU_TYPE (gdbarch), |
8776 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
8777 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
8778 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 8779 | : "???")); |
c2d11a7d JM |
8780 | } |
8781 | ||
025bb325 | 8782 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 8783 | |
c906108c | 8784 | void |
acdb74a0 | 8785 | _initialize_mips_tdep (void) |
c906108c SS |
8786 | { |
8787 | static struct cmd_list_element *mipsfpulist = NULL; | |
8788 | struct cmd_list_element *c; | |
8789 | ||
6d82d43b | 8790 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8791 | if (MIPS_ABI_LAST + 1 |
8792 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8793 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8794 | |
4b9b3959 | 8795 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8796 | |
8d5f9dcb DJ |
8797 | mips_pdr_data = register_objfile_data (); |
8798 | ||
4eb0ad19 DJ |
8799 | /* Create feature sets with the appropriate properties. The values |
8800 | are not important. */ | |
8801 | mips_tdesc_gp32 = allocate_target_description (); | |
8802 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8803 | ||
8804 | mips_tdesc_gp64 = allocate_target_description (); | |
8805 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8806 | ||
025bb325 | 8807 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8808 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8809 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8810 | &setmipscmdlist, "set mips ", 0, &setlist); |
8811 | ||
8812 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8813 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8814 | &showmipscmdlist, "show mips ", 0, &showlist); |
8815 | ||
025bb325 | 8816 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8817 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8818 | &mips_abi_string, _("\ | |
8819 | Set the MIPS ABI used by this program."), _("\ | |
8820 | Show the MIPS ABI used by this program."), _("\ | |
8821 | This option can be set to one of:\n\ | |
8822 | auto - the default ABI associated with the current binary\n\ | |
8823 | o32\n\ | |
8824 | o64\n\ | |
8825 | n32\n\ | |
8826 | n64\n\ | |
8827 | eabi32\n\ | |
8828 | eabi64"), | |
8829 | mips_abi_update, | |
8830 | show_mips_abi, | |
8831 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 8832 | |
4cc0665f MR |
8833 | /* Allow the user to set the ISA to assume for compressed code if ELF |
8834 | file flags don't tell or there is no program file selected. This | |
8835 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
8836 | and carried over to subsequent sessions. */ | |
8837 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
8838 | &mips_compression_string, _("\ | |
8839 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
8840 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
8841 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
8842 | information available. The encoding can be set to either of:\n\ | |
8843 | mips16\n\ | |
8844 | micromips\n\ | |
8845 | and is updated automatically from ELF file flags if available."), | |
8846 | mips_abi_update, | |
8847 | show_mips_compression, | |
8848 | &setmipscmdlist, &showmipscmdlist); | |
8849 | ||
c906108c SS |
8850 | /* Let the user turn off floating point and set the fence post for |
8851 | heuristic_proc_start. */ | |
8852 | ||
8853 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 8854 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
8855 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
8856 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 8857 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
8858 | &mipsfpulist); |
8859 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 8860 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
8861 | &mipsfpulist); |
8862 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
8863 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
8864 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
8865 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 8866 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
8867 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
8868 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
8869 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
8870 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 8871 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
8872 | &mipsfpulist); |
8873 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 8874 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
8875 | &showlist); |
8876 | ||
c906108c SS |
8877 | /* We really would like to have both "0" and "unlimited" work, but |
8878 | command.c doesn't deal with that. So make it a var_zinteger | |
8879 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 8880 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
8881 | &heuristic_fence_post, _("\ |
8882 | Set the distance searched for the start of a function."), _("\ | |
8883 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
8884 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
8885 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 8886 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 8887 | reinit_frame_cache_sfunc, |
025bb325 MS |
8888 | NULL, /* FIXME: i18n: The distance searched for |
8889 | the start of a function is %s. */ | |
6bcadd06 | 8890 | &setlist, &showlist); |
c906108c SS |
8891 | |
8892 | /* Allow the user to control whether the upper bits of 64-bit | |
8893 | addresses should be zeroed. */ | |
7915a72c AC |
8894 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
8895 | &mask_address_var, _("\ | |
8896 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
8897 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 8898 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 8899 | allow GDB to determine the correct value."), |
08546159 AC |
8900 | NULL, show_mask_address, |
8901 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
8902 | |
8903 | /* Allow the user to control the size of 32 bit registers within the | |
8904 | raw remote packet. */ | |
b3f42336 | 8905 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
8906 | &mips64_transfers_32bit_regs_p, _("\ |
8907 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8908 | _("\ | |
8909 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8910 | _("\ | |
719ec221 AC |
8911 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
8912 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 8913 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 8914 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
8915 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
8916 | MIPS target that transfers 32-bit | |
8917 | quantities is %s. */ | |
7915a72c | 8918 | &setlist, &showlist); |
9ace0497 | 8919 | |
025bb325 | 8920 | /* Debug this files internals. */ |
ccce17b0 YQ |
8921 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
8922 | &mips_debug, _("\ | |
7915a72c AC |
8923 | Set mips debugging."), _("\ |
8924 | Show mips debugging."), _("\ | |
8925 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
8926 | NULL, |
8927 | NULL, /* FIXME: i18n: Mips debugging is | |
8928 | currently %s. */ | |
8929 | &setdebuglist, &showdebuglist); | |
c906108c | 8930 | } |