Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
4cc0665f MR |
65 | static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR); |
66 | static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
67 | int); | |
68 | static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
69 | int); | |
70 | ||
24e05951 | 71 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
72 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
73 | #define ST0_FR (1 << 26) | |
74 | ||
b0069a17 AC |
75 | /* The sizes of floating point registers. */ |
76 | ||
77 | enum | |
78 | { | |
79 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
80 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
81 | }; | |
82 | ||
1a69e1e4 DJ |
83 | enum |
84 | { | |
85 | MIPS32_REGSIZE = 4, | |
86 | MIPS64_REGSIZE = 8 | |
87 | }; | |
0dadbba0 | 88 | |
2e4ebe70 DJ |
89 | static const char *mips_abi_string; |
90 | ||
40478521 | 91 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
92 | "auto", |
93 | "n32", | |
94 | "o32", | |
28d169de | 95 | "n64", |
2e4ebe70 DJ |
96 | "o64", |
97 | "eabi32", | |
98 | "eabi64", | |
99 | NULL | |
100 | }; | |
101 | ||
4cc0665f MR |
102 | /* For backwards compatibility we default to MIPS16. This flag is |
103 | overridden as soon as unambiguous ELF file flags tell us the | |
104 | compressed ISA encoding used. */ | |
105 | static const char mips_compression_mips16[] = "mips16"; | |
106 | static const char mips_compression_micromips[] = "micromips"; | |
107 | static const char *const mips_compression_strings[] = | |
108 | { | |
109 | mips_compression_mips16, | |
110 | mips_compression_micromips, | |
111 | NULL | |
112 | }; | |
113 | ||
114 | static const char *mips_compression_string = mips_compression_mips16; | |
115 | ||
f8b73d13 DJ |
116 | /* The standard register names, and all the valid aliases for them. */ |
117 | struct register_alias | |
118 | { | |
119 | const char *name; | |
120 | int regnum; | |
121 | }; | |
122 | ||
123 | /* Aliases for o32 and most other ABIs. */ | |
124 | const struct register_alias mips_o32_aliases[] = { | |
125 | { "ta0", 12 }, | |
126 | { "ta1", 13 }, | |
127 | { "ta2", 14 }, | |
128 | { "ta3", 15 } | |
129 | }; | |
130 | ||
131 | /* Aliases for n32 and n64. */ | |
132 | const struct register_alias mips_n32_n64_aliases[] = { | |
133 | { "ta0", 8 }, | |
134 | { "ta1", 9 }, | |
135 | { "ta2", 10 }, | |
136 | { "ta3", 11 } | |
137 | }; | |
138 | ||
139 | /* Aliases for ABI-independent registers. */ | |
140 | const struct register_alias mips_register_aliases[] = { | |
141 | /* The architecture manuals specify these ABI-independent names for | |
142 | the GPRs. */ | |
143 | #define R(n) { "r" #n, n } | |
144 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
145 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
146 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
147 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
148 | #undef R | |
149 | ||
150 | /* k0 and k1 are sometimes called these instead (for "kernel | |
151 | temp"). */ | |
152 | { "kt0", 26 }, | |
153 | { "kt1", 27 }, | |
154 | ||
155 | /* This is the traditional GDB name for the CP0 status register. */ | |
156 | { "sr", MIPS_PS_REGNUM }, | |
157 | ||
158 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
159 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
160 | ||
161 | /* This is the traditional GDB name for the FCSR. */ | |
162 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
163 | }; | |
164 | ||
865093a3 AR |
165 | const struct register_alias mips_numeric_register_aliases[] = { |
166 | #define R(n) { #n, n } | |
167 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
168 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
169 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
170 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
171 | #undef R | |
172 | }; | |
173 | ||
c906108c SS |
174 | #ifndef MIPS_DEFAULT_FPU_TYPE |
175 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
176 | #endif | |
177 | static int mips_fpu_type_auto = 1; | |
178 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 179 | |
9ace0497 | 180 | static int mips_debug = 0; |
7a292a7a | 181 | |
29709017 DJ |
182 | /* Properties (for struct target_desc) describing the g/G packet |
183 | layout. */ | |
184 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
185 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
186 | ||
4eb0ad19 DJ |
187 | struct target_desc *mips_tdesc_gp32; |
188 | struct target_desc *mips_tdesc_gp64; | |
189 | ||
56cea623 AC |
190 | const struct mips_regnum * |
191 | mips_regnum (struct gdbarch *gdbarch) | |
192 | { | |
193 | return gdbarch_tdep (gdbarch)->regnum; | |
194 | } | |
195 | ||
196 | static int | |
197 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
198 | { | |
199 | return mips_regnum (gdbarch)->fp0 + 12; | |
200 | } | |
201 | ||
004159a2 MR |
202 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
203 | or cooked. Otherwise return 0. */ | |
204 | ||
205 | static int | |
206 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
207 | { | |
208 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
209 | ||
210 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
211 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
212 | } | |
213 | ||
74ed0bb4 MD |
214 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
215 | == MIPS_ABI_EABI32 \ | |
216 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 217 | |
025bb325 MS |
218 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
219 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 220 | |
025bb325 MS |
221 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
222 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 223 | |
74ed0bb4 | 224 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 225 | |
d1973055 KB |
226 | /* Return the MIPS ABI associated with GDBARCH. */ |
227 | enum mips_abi | |
228 | mips_abi (struct gdbarch *gdbarch) | |
229 | { | |
230 | return gdbarch_tdep (gdbarch)->mips_abi; | |
231 | } | |
232 | ||
4246e332 | 233 | int |
1b13c4f6 | 234 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 235 | { |
29709017 DJ |
236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
237 | ||
238 | /* If we know how big the registers are, use that size. */ | |
239 | if (tdep->register_size_valid_p) | |
240 | return tdep->register_size; | |
241 | ||
242 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
243 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
244 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
245 | } | |
246 | ||
025bb325 | 247 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 248 | |
e6bc2e8a | 249 | unsigned int |
13326b4e | 250 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 251 | { |
1a69e1e4 DJ |
252 | switch (mips_abi (gdbarch)) |
253 | { | |
254 | case MIPS_ABI_EABI32: | |
255 | case MIPS_ABI_O32: | |
256 | return 4; | |
257 | case MIPS_ABI_N32: | |
258 | case MIPS_ABI_N64: | |
259 | case MIPS_ABI_O64: | |
260 | case MIPS_ABI_EABI64: | |
261 | return 8; | |
262 | case MIPS_ABI_UNKNOWN: | |
263 | case MIPS_ABI_LAST: | |
264 | default: | |
265 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
266 | } | |
d929b26f AC |
267 | } |
268 | ||
4cc0665f MR |
269 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
270 | are some functions to handle addresses associated with compressed | |
271 | code including but not limited to testing, setting, or clearing | |
272 | bit 0 of such addresses. */ | |
742c84f6 | 273 | |
4cc0665f MR |
274 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
275 | ||
276 | static int | |
277 | is_mips16_isa (struct gdbarch *gdbarch) | |
278 | { | |
279 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
280 | } | |
281 | ||
282 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
283 | ||
284 | static int | |
285 | is_micromips_isa (struct gdbarch *gdbarch) | |
286 | { | |
287 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
288 | } | |
289 | ||
290 | /* Return one iff ADDR denotes compressed code. */ | |
291 | ||
292 | static int | |
293 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
294 | { |
295 | return ((addr) & 1); | |
296 | } | |
297 | ||
4cc0665f MR |
298 | /* Return one iff ADDR denotes standard ISA code. */ |
299 | ||
300 | static int | |
301 | is_mips_addr (CORE_ADDR addr) | |
302 | { | |
303 | return !is_compact_addr (addr); | |
304 | } | |
305 | ||
306 | /* Return one iff ADDR denotes MIPS16 code. */ | |
307 | ||
308 | static int | |
309 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
310 | { | |
311 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
312 | } | |
313 | ||
314 | /* Return one iff ADDR denotes microMIPS code. */ | |
315 | ||
316 | static int | |
317 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
318 | { | |
319 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
320 | } | |
321 | ||
322 | /* Strip the ISA (compression) bit off from ADDR. */ | |
323 | ||
742c84f6 | 324 | static CORE_ADDR |
4cc0665f | 325 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
326 | { |
327 | return ((addr) & ~(CORE_ADDR) 1); | |
328 | } | |
329 | ||
4cc0665f MR |
330 | /* Add the ISA (compression) bit to ADDR. */ |
331 | ||
742c84f6 | 332 | static CORE_ADDR |
4cc0665f | 333 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
334 | { |
335 | return ((addr) | (CORE_ADDR) 1); | |
336 | } | |
337 | ||
71b8ef93 | 338 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
339 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
340 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 341 | |
4cc0665f MR |
342 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
343 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
344 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
345 | The test checks an ELF-private flag that is valid for true function | |
346 | symbols only; in particular synthetic symbols such as for PLT stubs | |
347 | have no ELF-private part at all. | |
5a89d8aa | 348 | |
4cc0665f MR |
349 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
350 | in a minimal symbol. */ | |
5a89d8aa | 351 | |
5a89d8aa | 352 | static void |
6d82d43b AC |
353 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
354 | { | |
4cc0665f MR |
355 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
356 | ||
357 | if ((sym->flags & BSF_SYNTHETIC) != 0) | |
358 | return; | |
359 | ||
360 | if (ELF_ST_IS_MICROMIPS (elfsym->internal_elf_sym.st_other)) | |
361 | MSYMBOL_TARGET_FLAG_2 (msym) = 1; | |
362 | else if (ELF_ST_IS_MIPS16 (elfsym->internal_elf_sym.st_other)) | |
363 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; | |
364 | } | |
365 | ||
366 | /* Return one iff MSYM refers to standard ISA code. */ | |
367 | ||
368 | static int | |
369 | msymbol_is_mips (struct minimal_symbol *msym) | |
370 | { | |
371 | return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym)); | |
5a89d8aa MS |
372 | } |
373 | ||
4cc0665f MR |
374 | /* Return one iff MSYM refers to MIPS16 code. */ |
375 | ||
71b8ef93 | 376 | static int |
4cc0665f | 377 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 378 | { |
b887350f | 379 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
380 | } |
381 | ||
4cc0665f MR |
382 | /* Return one iff MSYM refers to microMIPS code. */ |
383 | ||
384 | static int | |
385 | msymbol_is_micromips (struct minimal_symbol *msym) | |
386 | { | |
387 | return MSYMBOL_TARGET_FLAG_2 (msym); | |
388 | } | |
389 | ||
88658117 AC |
390 | /* XFER a value from the big/little/left end of the register. |
391 | Depending on the size of the value it might occupy the entire | |
392 | register or just part of it. Make an allowance for this, aligning | |
393 | things accordingly. */ | |
394 | ||
395 | static void | |
ba32f989 DJ |
396 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
397 | int reg_num, int length, | |
870cd05e MK |
398 | enum bfd_endian endian, gdb_byte *in, |
399 | const gdb_byte *out, int buf_offset) | |
88658117 | 400 | { |
88658117 | 401 | int reg_offset = 0; |
72a155b4 UW |
402 | |
403 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
404 | /* Need to transfer the left or right part of the register, based on |
405 | the targets byte order. */ | |
88658117 AC |
406 | switch (endian) |
407 | { | |
408 | case BFD_ENDIAN_BIG: | |
72a155b4 | 409 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
410 | break; |
411 | case BFD_ENDIAN_LITTLE: | |
412 | reg_offset = 0; | |
413 | break; | |
6d82d43b | 414 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
415 | reg_offset = 0; |
416 | break; | |
417 | default: | |
e2e0b3e5 | 418 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
419 | } |
420 | if (mips_debug) | |
cb1d2653 AC |
421 | fprintf_unfiltered (gdb_stderr, |
422 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
423 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
424 | if (mips_debug && out != NULL) |
425 | { | |
426 | int i; | |
cb1d2653 | 427 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 428 | for (i = 0; i < length; i++) |
cb1d2653 | 429 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
430 | } |
431 | if (in != NULL) | |
6d82d43b AC |
432 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
433 | in + buf_offset); | |
88658117 | 434 | if (out != NULL) |
6d82d43b AC |
435 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
436 | out + buf_offset); | |
88658117 AC |
437 | if (mips_debug && in != NULL) |
438 | { | |
439 | int i; | |
cb1d2653 | 440 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 441 | for (i = 0; i < length; i++) |
cb1d2653 | 442 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
443 | } |
444 | if (mips_debug) | |
445 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
446 | } | |
447 | ||
dd824b04 DJ |
448 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
449 | compatiblity mode. A return value of 1 means that we have | |
450 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
451 | ||
452 | static int | |
9c9acae0 | 453 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 454 | { |
72a155b4 | 455 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
456 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
457 | meaningful. */ | |
72a155b4 | 458 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
459 | return 0; |
460 | ||
461 | #if 0 | |
462 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
463 | in all the places we deal with FP registers. PR gdb/413. */ | |
464 | /* Otherwise check the FR bit in the status register - it controls | |
465 | the FP compatiblity mode. If it is clear we are in compatibility | |
466 | mode. */ | |
9c9acae0 | 467 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
468 | return 1; |
469 | #endif | |
361d1df0 | 470 | |
dd824b04 DJ |
471 | return 0; |
472 | } | |
473 | ||
7a292a7a | 474 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 475 | |
74ed0bb4 | 476 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 477 | |
a14ed312 | 478 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 479 | |
025bb325 | 480 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
481 | |
482 | static struct cmd_list_element *setmipscmdlist = NULL; | |
483 | static struct cmd_list_element *showmipscmdlist = NULL; | |
484 | ||
5e2e9765 KB |
485 | /* Integer registers 0 thru 31 are handled explicitly by |
486 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 487 | are listed in the following tables. */ |
691c0433 | 488 | |
6d82d43b AC |
489 | enum |
490 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
491 | |
492 | /* Generic MIPS. */ | |
493 | ||
494 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
495 | "sr", "lo", "hi", "bad", "cause", "pc", |
496 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
497 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
498 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
499 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 500 | "fsr", "fir", |
691c0433 AC |
501 | }; |
502 | ||
503 | /* Names of IDT R3041 registers. */ | |
504 | ||
505 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
506 | "sr", "lo", "hi", "bad", "cause", "pc", |
507 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
508 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
509 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
510 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
511 | "fsr", "fir", "", /*"fp" */ "", | |
512 | "", "", "bus", "ccfg", "", "", "", "", | |
513 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
514 | }; |
515 | ||
516 | /* Names of tx39 registers. */ | |
517 | ||
518 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
519 | "sr", "lo", "hi", "bad", "cause", "pc", |
520 | "", "", "", "", "", "", "", "", | |
521 | "", "", "", "", "", "", "", "", | |
522 | "", "", "", "", "", "", "", "", | |
523 | "", "", "", "", "", "", "", "", | |
524 | "", "", "", "", | |
525 | "", "", "", "", "", "", "", "", | |
1faeff08 | 526 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
527 | }; |
528 | ||
529 | /* Names of IRIX registers. */ | |
530 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
531 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
532 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
533 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
534 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
535 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
536 | }; |
537 | ||
44099a67 | 538 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
539 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
540 | "sr", "lo", "hi", "bad", "cause", "pc", | |
541 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
542 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
543 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
544 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
545 | "fsr", "fir" | |
546 | }; | |
547 | ||
cce74817 | 548 | |
5e2e9765 | 549 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 550 | static const char * |
d93859e2 | 551 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 552 | { |
d93859e2 | 553 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
554 | /* GPR names for all ABIs other than n32/n64. */ |
555 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
556 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
557 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
558 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
559 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
560 | }; |
561 | ||
562 | /* GPR names for n32 and n64 ABIs. */ | |
563 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
564 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
565 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
566 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
567 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
568 | }; |
569 | ||
d93859e2 | 570 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 571 | |
f57d151a | 572 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
573 | but then don't make the raw register names visible. This (upper) |
574 | range of user visible register numbers are the pseudo-registers. | |
575 | ||
576 | This approach was adopted accommodate the following scenario: | |
577 | It is possible to debug a 64-bit device using a 32-bit | |
578 | programming model. In such instances, the raw registers are | |
579 | configured to be 64-bits wide, while the pseudo registers are | |
580 | configured to be 32-bits wide. The registers that the user | |
581 | sees - the pseudo registers - match the users expectations | |
582 | given the programming model being used. */ | |
d93859e2 UW |
583 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
584 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
585 | return ""; |
586 | ||
5e2e9765 KB |
587 | /* The MIPS integer registers are always mapped from 0 to 31. The |
588 | names of the registers (which reflects the conventions regarding | |
589 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 590 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
591 | { |
592 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 593 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 594 | else |
a4b8ebc8 | 595 | return mips_gpr_names[rawnum]; |
5e2e9765 | 596 | } |
d93859e2 UW |
597 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
598 | return tdesc_register_name (gdbarch, rawnum); | |
599 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
600 | { |
601 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
602 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
603 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
604 | return ""; | |
691c0433 | 605 | } |
5e2e9765 KB |
606 | else |
607 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 608 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 609 | } |
5e2e9765 | 610 | |
a4b8ebc8 | 611 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 612 | |
a4b8ebc8 AC |
613 | static int |
614 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
615 | struct reggroup *reggroup) | |
616 | { | |
617 | int vector_p; | |
618 | int float_p; | |
619 | int raw_p; | |
72a155b4 UW |
620 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
621 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
622 | if (reggroup == all_reggroup) |
623 | return pseudo; | |
624 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
625 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
626 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
627 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
628 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
629 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
630 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
631 | return 0; |
632 | if (reggroup == float_reggroup) | |
633 | return float_p && pseudo; | |
634 | if (reggroup == vector_reggroup) | |
635 | return vector_p && pseudo; | |
636 | if (reggroup == general_reggroup) | |
637 | return (!vector_p && !float_p) && pseudo; | |
638 | /* Save the pseudo registers. Need to make certain that any code | |
639 | extracting register values from a saved register cache also uses | |
640 | pseudo registers. */ | |
641 | if (reggroup == save_reggroup) | |
642 | return raw_p && pseudo; | |
643 | /* Restore the same pseudo register. */ | |
644 | if (reggroup == restore_reggroup) | |
645 | return raw_p && pseudo; | |
6d82d43b | 646 | return 0; |
a4b8ebc8 AC |
647 | } |
648 | ||
f8b73d13 DJ |
649 | /* Return the groups that a MIPS register can be categorised into. |
650 | This version is only used if we have a target description which | |
651 | describes real registers (and their groups). */ | |
652 | ||
653 | static int | |
654 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
655 | struct reggroup *reggroup) | |
656 | { | |
657 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
658 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
659 | int ret; | |
660 | ||
661 | /* Only save, restore, and display the pseudo registers. Need to | |
662 | make certain that any code extracting register values from a | |
663 | saved register cache also uses pseudo registers. | |
664 | ||
665 | Note: saving and restoring the pseudo registers is slightly | |
666 | strange; if we have 64 bits, we should save and restore all | |
667 | 64 bits. But this is hard and has little benefit. */ | |
668 | if (!pseudo) | |
669 | return 0; | |
670 | ||
671 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
672 | if (ret != -1) | |
673 | return ret; | |
674 | ||
675 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
676 | } | |
677 | ||
a4b8ebc8 | 678 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 679 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 680 | registers. Take care of alignment and size problems. */ |
c5aa993b | 681 | |
05d1431c | 682 | static enum register_status |
a4b8ebc8 | 683 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 684 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 685 | { |
72a155b4 UW |
686 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
687 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
688 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 689 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 690 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
691 | else if (register_size (gdbarch, rawnum) > |
692 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 693 | { |
8bdf35dc | 694 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 695 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 696 | else |
8bdf35dc KB |
697 | { |
698 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
699 | LONGEST regval; | |
05d1431c PA |
700 | enum register_status status; |
701 | ||
702 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
703 | if (status == REG_VALID) | |
704 | store_signed_integer (buf, 4, byte_order, regval); | |
705 | return status; | |
8bdf35dc | 706 | } |
47ebcfbe AC |
707 | } |
708 | else | |
e2e0b3e5 | 709 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
710 | } |
711 | ||
712 | static void | |
6d82d43b AC |
713 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
714 | struct regcache *regcache, int cookednum, | |
47a35522 | 715 | const gdb_byte *buf) |
a4b8ebc8 | 716 | { |
72a155b4 UW |
717 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
718 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
719 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 720 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 721 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
722 | else if (register_size (gdbarch, rawnum) > |
723 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 724 | { |
8bdf35dc | 725 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
726 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
727 | else | |
8bdf35dc KB |
728 | { |
729 | /* Sign extend the shortened version of the register prior | |
730 | to placing it in the raw register. This is required for | |
731 | some mips64 parts in order to avoid unpredictable behavior. */ | |
732 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
733 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
734 | regcache_raw_write_signed (regcache, rawnum, regval); | |
735 | } | |
47ebcfbe AC |
736 | } |
737 | else | |
e2e0b3e5 | 738 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 739 | } |
c5aa993b | 740 | |
175ff332 HZ |
741 | static int |
742 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
743 | struct agent_expr *ax, int reg) | |
744 | { | |
745 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
746 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
747 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
748 | ||
749 | ax_reg_mask (ax, rawnum); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | static int | |
755 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
756 | struct agent_expr *ax, int reg) | |
757 | { | |
758 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
759 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
760 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
761 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
762 | { | |
763 | ax_reg (ax, rawnum); | |
764 | ||
765 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
766 | { | |
767 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
768 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
769 | { | |
770 | ax_const_l (ax, 32); | |
771 | ax_simple (ax, aop_lsh); | |
772 | } | |
773 | ax_const_l (ax, 32); | |
774 | ax_simple (ax, aop_rsh_signed); | |
775 | } | |
776 | } | |
777 | else | |
778 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
4cc0665f | 783 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 784 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
785 | |
786 | /* Heuristic_proc_start may hunt through the text section for a long | |
787 | time across a 2400 baud serial line. Allows the user to limit this | |
788 | search. */ | |
789 | ||
790 | static unsigned int heuristic_fence_post = 0; | |
791 | ||
46cd78fb | 792 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
793 | register N. NOTE: This defines the pseudo register type so need to |
794 | rebuild the architecture vector. */ | |
43e526b9 JM |
795 | |
796 | static int mips64_transfers_32bit_regs_p = 0; | |
797 | ||
719ec221 AC |
798 | static void |
799 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
800 | struct cmd_list_element *c) | |
43e526b9 | 801 | { |
719ec221 AC |
802 | struct gdbarch_info info; |
803 | gdbarch_info_init (&info); | |
804 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
805 | instead of relying on globals. Doing that would let generic code | |
806 | handle the search for this specific architecture. */ | |
807 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 808 | { |
719ec221 | 809 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 810 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 811 | } |
a4b8ebc8 AC |
812 | } |
813 | ||
47ebcfbe | 814 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 815 | |
ee51a8c7 KB |
816 | /* This predicate tests for the case of an 8 byte floating point |
817 | value that is being transferred to or from a pair of floating point | |
818 | registers each of which are (or are considered to be) only 4 bytes | |
819 | wide. */ | |
ff2e87ac | 820 | static int |
ee51a8c7 KB |
821 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
822 | struct type *type) | |
ff2e87ac | 823 | { |
0abe36f5 MD |
824 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
825 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 826 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 827 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
828 | } |
829 | ||
ee51a8c7 KB |
830 | /* This predicate tests for the case of a value of less than 8 |
831 | bytes in width that is being transfered to or from an 8 byte | |
832 | general purpose register. */ | |
833 | static int | |
834 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
835 | struct type *type) | |
836 | { | |
837 | int num_regs = gdbarch_num_regs (gdbarch); | |
838 | ||
839 | return (register_size (gdbarch, regnum) == 8 | |
840 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
841 | && TYPE_LENGTH (type) < 8); | |
842 | } | |
843 | ||
844 | static int | |
025bb325 MS |
845 | mips_convert_register_p (struct gdbarch *gdbarch, |
846 | int regnum, struct type *type) | |
ee51a8c7 KB |
847 | { |
848 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
849 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
850 | } | |
851 | ||
8dccd430 | 852 | static int |
ff2e87ac | 853 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
854 | struct type *type, gdb_byte *to, |
855 | int *optimizedp, int *unavailablep) | |
102182a9 | 856 | { |
ee51a8c7 KB |
857 | struct gdbarch *gdbarch = get_frame_arch (frame); |
858 | ||
859 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
860 | { | |
861 | get_frame_register (frame, regnum + 0, to + 4); | |
862 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
863 | |
864 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
865 | optimizedp, unavailablep)) | |
866 | return 0; | |
867 | ||
868 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
869 | optimizedp, unavailablep)) | |
870 | return 0; | |
871 | *optimizedp = *unavailablep = 0; | |
872 | return 1; | |
ee51a8c7 KB |
873 | } |
874 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
875 | { | |
876 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
877 | CORE_ADDR offset; |
878 | ||
879 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
880 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
881 | optimizedp, unavailablep)) | |
882 | return 0; | |
883 | ||
884 | *optimizedp = *unavailablep = 0; | |
885 | return 1; | |
ee51a8c7 KB |
886 | } |
887 | else | |
888 | { | |
889 | internal_error (__FILE__, __LINE__, | |
890 | _("mips_register_to_value: unrecognized case")); | |
891 | } | |
102182a9 MS |
892 | } |
893 | ||
42c466d7 | 894 | static void |
ff2e87ac | 895 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 896 | struct type *type, const gdb_byte *from) |
102182a9 | 897 | { |
ee51a8c7 KB |
898 | struct gdbarch *gdbarch = get_frame_arch (frame); |
899 | ||
900 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
901 | { | |
902 | put_frame_register (frame, regnum + 0, from + 4); | |
903 | put_frame_register (frame, regnum + 1, from + 0); | |
904 | } | |
905 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
906 | { | |
907 | gdb_byte fill[8]; | |
908 | int len = TYPE_LENGTH (type); | |
909 | ||
910 | /* Sign extend values, irrespective of type, that are stored to | |
911 | a 64-bit general purpose register. (32-bit unsigned values | |
912 | are stored as signed quantities within a 64-bit register. | |
913 | When performing an operation, in compiled code, that combines | |
914 | a 32-bit unsigned value with a signed 64-bit value, a type | |
915 | conversion is first performed that zeroes out the high 32 bits.) */ | |
916 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
917 | { | |
918 | if (from[0] & 0x80) | |
919 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
920 | else | |
921 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
922 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
923 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
924 | } | |
925 | else | |
926 | { | |
927 | if (from[len-1] & 0x80) | |
928 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
929 | else | |
930 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
931 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
932 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
933 | } | |
934 | } | |
935 | else | |
936 | { | |
937 | internal_error (__FILE__, __LINE__, | |
938 | _("mips_value_to_register: unrecognized case")); | |
939 | } | |
102182a9 MS |
940 | } |
941 | ||
a4b8ebc8 AC |
942 | /* Return the GDB type object for the "standard" data type of data in |
943 | register REG. */ | |
78fde5f8 KB |
944 | |
945 | static struct type * | |
a4b8ebc8 AC |
946 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
947 | { | |
72a155b4 | 948 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 949 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 950 | { |
5ef80fb0 | 951 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 952 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 953 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 954 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 955 | else |
27067745 | 956 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 957 | } |
72a155b4 | 958 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
959 | { |
960 | /* The raw or ISA registers. These are all sized according to | |
961 | the ISA regsize. */ | |
962 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 963 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 964 | else |
df4df182 | 965 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 966 | } |
78fde5f8 | 967 | else |
d5ac5a39 | 968 | { |
1faeff08 MR |
969 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
970 | ||
d5ac5a39 AC |
971 | /* The cooked or ABI registers. These are sized according to |
972 | the ABI (with a few complications). */ | |
1faeff08 MR |
973 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
974 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
975 | return builtin_type (gdbarch)->builtin_int32; | |
976 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
977 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
978 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
979 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
980 | /* The pseudo/cooked view of the embedded registers is always |
981 | 32-bit. The raw view is handled below. */ | |
df4df182 | 982 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
983 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
984 | /* The target, while possibly using a 64-bit register buffer, | |
985 | is only transfering 32-bits of each integer register. | |
986 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 987 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
988 | else if (mips_abi_regsize (gdbarch) == 4) |
989 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
990 | 32- or 64-bit). */ | |
df4df182 | 991 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
992 | else |
993 | /* 64-bit ABI. */ | |
df4df182 | 994 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 995 | } |
78fde5f8 KB |
996 | } |
997 | ||
f8b73d13 DJ |
998 | /* Return the GDB type for the pseudo register REGNUM, which is the |
999 | ABI-level view. This function is only called if there is a target | |
1000 | description which includes registers, so we know precisely the | |
1001 | types of hardware registers. */ | |
1002 | ||
1003 | static struct type * | |
1004 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1005 | { | |
1006 | const int num_regs = gdbarch_num_regs (gdbarch); | |
1007 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1008 | int rawnum = regnum % num_regs; | |
1009 | struct type *rawtype; | |
1010 | ||
1011 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1012 | ||
1013 | /* Absent registers are still absent. */ | |
1014 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1015 | if (TYPE_LENGTH (rawtype) == 0) | |
1016 | return rawtype; | |
1017 | ||
1faeff08 MR |
1018 | if (rawnum >= mips_regnum (gdbarch)->fp0 |
1019 | && rawnum < mips_regnum (gdbarch)->fp0 + 32) | |
f8b73d13 DJ |
1020 | /* Present the floating point registers however the hardware did; |
1021 | do not try to convert between FPU layouts. */ | |
1022 | return rawtype; | |
1023 | ||
f8b73d13 DJ |
1024 | /* Use pointer types for registers if we can. For n32 we can not, |
1025 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1026 | if (mips_abi_regsize (gdbarch) |
1027 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1028 | { |
1faeff08 MR |
1029 | if (rawnum == MIPS_SP_REGNUM |
1030 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1031 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1032 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1033 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1034 | } |
1035 | ||
1036 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1037 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1038 | || rawnum == mips_regnum (gdbarch)->lo | |
1039 | || rawnum == mips_regnum (gdbarch)->hi | |
1040 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1041 | || rawnum == mips_regnum (gdbarch)->cause | |
1042 | || rawnum == mips_regnum (gdbarch)->pc | |
1043 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1044 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1045 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1046 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1047 | |
1faeff08 MR |
1048 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
1049 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
1050 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
1051 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
1052 | { | |
1053 | /* The pseudo/cooked view of embedded registers is always | |
1054 | 32-bit, even if the target transfers 64-bit values for them. | |
1055 | New targets relying on XML descriptions should only transfer | |
1056 | the necessary 32 bits, but older versions of GDB expected 64, | |
1057 | so allow the target to provide 64 bits without interfering | |
1058 | with the displayed type. */ | |
1059 | return builtin_type (gdbarch)->builtin_int32; | |
1060 | } | |
1061 | ||
f8b73d13 DJ |
1062 | /* For all other registers, pass through the hardware type. */ |
1063 | return rawtype; | |
1064 | } | |
bcb0cc15 | 1065 | |
025bb325 | 1066 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1067 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1068 | |
1069 | static int | |
480d3dd2 | 1070 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1071 | { |
1072 | switch (mask_address_var) | |
1073 | { | |
7f19b9a2 | 1074 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1075 | return 1; |
7f19b9a2 | 1076 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1077 | return 0; |
1078 | break; | |
7f19b9a2 | 1079 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1080 | return tdep->default_mask_address_p; |
4014092b | 1081 | default: |
025bb325 MS |
1082 | internal_error (__FILE__, __LINE__, |
1083 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1084 | return -1; |
361d1df0 | 1085 | } |
4014092b AC |
1086 | } |
1087 | ||
1088 | static void | |
08546159 AC |
1089 | show_mask_address (struct ui_file *file, int from_tty, |
1090 | struct cmd_list_element *c, const char *value) | |
4014092b | 1091 | { |
1cf3db46 | 1092 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
1093 | |
1094 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1095 | switch (mask_address_var) |
1096 | { | |
7f19b9a2 | 1097 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1098 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1099 | break; | |
7f19b9a2 | 1100 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1101 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1102 | break; | |
7f19b9a2 | 1103 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1104 | printf_filtered |
1105 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1106 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1107 | break; |
1108 | default: | |
e2e0b3e5 | 1109 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1110 | break; |
361d1df0 | 1111 | } |
4014092b | 1112 | } |
c906108c | 1113 | |
4cc0665f MR |
1114 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1115 | function. */ | |
1116 | ||
1117 | int | |
1118 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1119 | { | |
1120 | struct minimal_symbol *sym; | |
1121 | ||
1122 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1123 | stored by elfread.c in the high bit of the info field. Use this | |
1124 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1125 | of the address is clear, then this is a standard MIPS function. */ | |
1126 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1127 | if (sym) | |
1128 | return msymbol_is_mips (sym); | |
1129 | else | |
1130 | return is_mips_addr (memaddr); | |
1131 | } | |
1132 | ||
c906108c SS |
1133 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1134 | ||
0fe7e7c8 | 1135 | int |
4cc0665f | 1136 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c SS |
1137 | { |
1138 | struct minimal_symbol *sym; | |
1139 | ||
91912e4d MR |
1140 | /* A flag indicating that this is a MIPS16 function is stored by |
1141 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1142 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1143 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
1144 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1145 | if (sym) | |
1146 | return msymbol_is_mips16 (sym); | |
1147 | else | |
1148 | return is_mips16_addr (gdbarch, memaddr); | |
1149 | } | |
1150 | ||
1151 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1152 | ||
1153 | int | |
1154 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1155 | { | |
1156 | struct minimal_symbol *sym; | |
1157 | ||
1158 | /* A flag indicating that this is a microMIPS function is stored by | |
1159 | elfread.c in the high bit of the info field. Use this to decide | |
1160 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1161 | is set, then ELF file flags will tell if this is a microMIPS | |
1162 | function. */ | |
1163 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1164 | if (sym) | |
1165 | return msymbol_is_micromips (sym); | |
1166 | else | |
1167 | return is_micromips_addr (gdbarch, memaddr); | |
1168 | } | |
1169 | ||
1170 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1171 | is in. */ | |
1172 | ||
1173 | static enum mips_isa | |
1174 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1175 | { | |
1176 | struct minimal_symbol *sym; | |
1177 | ||
1178 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1179 | is stored by elfread.c in the high bit of the info field. Use | |
1180 | this to decide if the function is MIPS16 or microMIPS or normal | |
1181 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1182 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
c906108c SS |
1183 | sym = lookup_minimal_symbol_by_pc (memaddr); |
1184 | if (sym) | |
4cc0665f MR |
1185 | { |
1186 | if (msymbol_is_micromips (sym)) | |
1187 | return ISA_MICROMIPS; | |
1188 | else if (msymbol_is_mips16 (sym)) | |
1189 | return ISA_MIPS16; | |
1190 | else | |
1191 | return ISA_MIPS; | |
1192 | } | |
c906108c | 1193 | else |
4cc0665f MR |
1194 | { |
1195 | if (is_mips_addr (memaddr)) | |
1196 | return ISA_MIPS; | |
1197 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1198 | return ISA_MICROMIPS; | |
1199 | else | |
1200 | return ISA_MIPS16; | |
1201 | } | |
c906108c SS |
1202 | } |
1203 | ||
14132e89 MR |
1204 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1205 | ||
1206 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1207 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1208 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1209 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1210 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1211 | ||
1212 | /* This is used as a PIC thunk prefix. */ | |
1213 | ||
1214 | static const char mips_str_pic[] = ".pic."; | |
1215 | ||
1216 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1217 | trampoline) that should be treated as a temporary frame. */ | |
1218 | ||
1219 | static int | |
1220 | mips_in_frame_stub (CORE_ADDR pc) | |
1221 | { | |
1222 | CORE_ADDR start_addr; | |
1223 | const char *name; | |
1224 | ||
1225 | /* Find the starting address of the function containing the PC. */ | |
1226 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1227 | return 0; | |
1228 | ||
1229 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
1230 | if (strncmp (name, mips_str_mips16_call_stub, | |
1231 | strlen (mips_str_mips16_call_stub)) == 0) | |
1232 | return 1; | |
1233 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
1234 | if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
1235 | return 1; | |
1236 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
1237 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) | |
1238 | return 1; | |
1239 | ||
1240 | return 0; /* Not a stub. */ | |
1241 | } | |
1242 | ||
b2fa5097 | 1243 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1244 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1245 | |
1246 | static CORE_ADDR | |
61a1198a | 1247 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1248 | { |
8376de04 | 1249 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
61a1198a | 1250 | ULONGEST pc; |
8376de04 | 1251 | |
61a1198a | 1252 | regcache_cooked_read_signed (regcache, regnum, &pc); |
4cc0665f MR |
1253 | if (is_compact_addr (pc)) |
1254 | pc = unmake_compact_addr (pc); | |
61a1198a | 1255 | return pc; |
b6cb9035 AC |
1256 | } |
1257 | ||
58dfe9ff AC |
1258 | static CORE_ADDR |
1259 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1260 | { | |
14132e89 | 1261 | CORE_ADDR pc; |
930bd0e0 | 1262 | |
8376de04 | 1263 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
4cc0665f MR |
1264 | if (is_compact_addr (pc)) |
1265 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1266 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1267 | intermediate frames. In this case we can get the caller's address | |
1268 | from $ra, or if $ra contains an address within a thunk as well, then | |
1269 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1270 | and thus the caller's address is in $s2. */ | |
1271 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1272 | { | |
1273 | pc = frame_unwind_register_signed | |
1274 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
4cc0665f MR |
1275 | if (is_compact_addr (pc)) |
1276 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1277 | if (mips_in_frame_stub (pc)) |
1278 | { | |
1279 | pc = frame_unwind_register_signed | |
1280 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
4cc0665f MR |
1281 | if (is_compact_addr (pc)) |
1282 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1283 | } |
1284 | } | |
930bd0e0 | 1285 | return pc; |
edfae063 AC |
1286 | } |
1287 | ||
30244cd8 UW |
1288 | static CORE_ADDR |
1289 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1290 | { | |
72a155b4 UW |
1291 | return frame_unwind_register_signed |
1292 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1293 | } |
1294 | ||
b8a22b94 | 1295 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1296 | dummy frame. The frame ID's base needs to match the TOS value |
1297 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1298 | breakpoint. */ | |
1299 | ||
1300 | static struct frame_id | |
b8a22b94 | 1301 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1302 | { |
f57d151a | 1303 | return frame_id_build |
b8a22b94 DJ |
1304 | (get_frame_register_signed (this_frame, |
1305 | gdbarch_num_regs (gdbarch) | |
1306 | + MIPS_SP_REGNUM), | |
1307 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1308 | } |
1309 | ||
5a439849 MR |
1310 | /* Implement the "write_pc" gdbarch method. */ |
1311 | ||
1312 | void | |
61a1198a | 1313 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1314 | { |
8376de04 MR |
1315 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1316 | ||
4cc0665f | 1317 | if (mips_pc_is_mips (pc)) |
930bd0e0 | 1318 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
4cc0665f MR |
1319 | else |
1320 | regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc)); | |
6c997a34 | 1321 | } |
c906108c | 1322 | |
4cc0665f MR |
1323 | /* Fetch and return instruction from the specified location. Handle |
1324 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1325 | |
d37cca3d | 1326 | static ULONGEST |
4cc0665f MR |
1327 | mips_fetch_instruction (struct gdbarch *gdbarch, |
1328 | enum mips_isa isa, CORE_ADDR addr, int *statusp) | |
c906108c | 1329 | { |
e17a4113 | 1330 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1331 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1332 | int instlen; |
1333 | int status; | |
1334 | ||
4cc0665f | 1335 | switch (isa) |
c906108c | 1336 | { |
4cc0665f MR |
1337 | case ISA_MICROMIPS: |
1338 | case ISA_MIPS16: | |
95ac2dcf | 1339 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1340 | addr = unmake_compact_addr (addr); |
1341 | break; | |
1342 | case ISA_MIPS: | |
1343 | instlen = MIPS_INSN32_SIZE; | |
1344 | break; | |
1345 | default: | |
1346 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1347 | break; | |
c906108c | 1348 | } |
8defab1a | 1349 | status = target_read_memory (addr, buf, instlen); |
4cc0665f MR |
1350 | if (statusp != NULL) |
1351 | *statusp = status; | |
c906108c | 1352 | if (status) |
4cc0665f MR |
1353 | { |
1354 | if (statusp == NULL) | |
1355 | memory_error (status, addr); | |
1356 | return 0; | |
1357 | } | |
e17a4113 | 1358 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1359 | } |
1360 | ||
025bb325 | 1361 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1362 | #define mips32_op(x) (x >> 26) |
1363 | #define itype_op(x) (x >> 26) | |
1364 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1365 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1366 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1367 | |
e135b889 DJ |
1368 | #define jtype_op(x) (x >> 26) |
1369 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1370 | |
e135b889 DJ |
1371 | #define rtype_op(x) (x >> 26) |
1372 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1373 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1374 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1375 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1376 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1377 | |
4cc0665f MR |
1378 | /* MicroMIPS instruction fields. */ |
1379 | #define micromips_op(x) ((x) >> 10) | |
1380 | ||
1381 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1382 | bit and the size respectively of the field extracted. */ | |
1383 | #define b0s4_imm(x) ((x) & 0xf) | |
1384 | #define b0s5_imm(x) ((x) & 0x1f) | |
1385 | #define b0s5_reg(x) ((x) & 0x1f) | |
1386 | #define b0s7_imm(x) ((x) & 0x7f) | |
1387 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1388 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1389 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1390 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1391 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1392 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1393 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1394 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1395 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1396 | ||
1397 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1398 | respectively of the field extracted. */ | |
1399 | #define b0s6_op(x) ((x) & 0x3f) | |
1400 | #define b0s11_op(x) ((x) & 0x7ff) | |
1401 | #define b0s12_imm(x) ((x) & 0xfff) | |
1402 | #define b0s16_imm(x) ((x) & 0xffff) | |
1403 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1404 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1405 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1406 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1407 | ||
1408 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1409 | instruction set. */ | |
1410 | ||
1411 | static int | |
1412 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1413 | { | |
1414 | switch (isa) | |
1415 | { | |
1416 | case ISA_MICROMIPS: | |
1417 | if (micromips_op (insn) == 0x1f) | |
1418 | return 3 * MIPS_INSN16_SIZE; | |
1419 | else if (((micromips_op (insn) & 0x4) == 0x4) | |
1420 | || ((micromips_op (insn) & 0x7) == 0x0)) | |
1421 | return 2 * MIPS_INSN16_SIZE; | |
1422 | else | |
1423 | return MIPS_INSN16_SIZE; | |
1424 | case ISA_MIPS16: | |
1425 | if ((insn & 0xf800) == 0xf000) | |
1426 | return 2 * MIPS_INSN16_SIZE; | |
1427 | else | |
1428 | return MIPS_INSN16_SIZE; | |
1429 | case ISA_MIPS: | |
1430 | return MIPS_INSN32_SIZE; | |
1431 | } | |
1432 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1433 | } | |
1434 | ||
06987e64 MK |
1435 | static LONGEST |
1436 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1437 | { |
06987e64 | 1438 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1439 | } |
1440 | ||
a385295e MR |
1441 | /* Determine the address of the next instruction executed after the INST |
1442 | floating condition branch instruction at PC. COUNT specifies the | |
1443 | number of the floating condition bits tested by the branch. */ | |
1444 | ||
1445 | static CORE_ADDR | |
1446 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1447 | ULONGEST inst, CORE_ADDR pc, int count) | |
1448 | { | |
1449 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1450 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1451 | int tf = itype_rt (inst) & 1; | |
1452 | int mask = (1 << count) - 1; | |
1453 | ULONGEST fcs; | |
1454 | int cond; | |
1455 | ||
1456 | if (fcsr == -1) | |
1457 | /* No way to handle; it'll most likely trap anyway. */ | |
1458 | return pc; | |
1459 | ||
1460 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1461 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1462 | ||
1463 | if (((cond >> cnum) & mask) != mask * !tf) | |
1464 | pc += mips32_relative_offset (inst); | |
1465 | else | |
1466 | pc += 4; | |
1467 | ||
1468 | return pc; | |
1469 | } | |
1470 | ||
f49e4e6d MS |
1471 | /* Determine where to set a single step breakpoint while considering |
1472 | branch prediction. */ | |
5a89d8aa | 1473 | static CORE_ADDR |
0b1b3e42 | 1474 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1475 | { |
e17a4113 | 1476 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1477 | unsigned long inst; |
1478 | int op; | |
4cc0665f | 1479 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
025bb325 MS |
1480 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1481 | instruction. */ | |
c5aa993b | 1482 | { |
e135b889 | 1483 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1484 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1485 | { |
e135b889 | 1486 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1487 | switch (op) |
1488 | { | |
e135b889 DJ |
1489 | case 0: /* BEQL */ |
1490 | goto equal_branch; | |
1491 | case 1: /* BNEL */ | |
1492 | goto neq_branch; | |
1493 | case 2: /* BLEZL */ | |
1494 | goto less_branch; | |
313628cc | 1495 | case 3: /* BGTZL */ |
e135b889 | 1496 | goto greater_branch; |
c5aa993b JM |
1497 | default: |
1498 | pc += 4; | |
c906108c SS |
1499 | } |
1500 | } | |
e135b889 | 1501 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1502 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
1503 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
1504 | else if (itype_op (inst) == 17 && itype_rs (inst) == 9 | |
1505 | && (itype_rt (inst) & 2) == 0) | |
1506 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1507 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
1508 | else if (itype_op (inst) == 17 && itype_rs (inst) == 10 | |
1509 | && (itype_rt (inst) & 2) == 0) | |
1510 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1511 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
9e8da49c MR |
1512 | else if (itype_op (inst) == 29) |
1513 | /* JALX: 011101 */ | |
1514 | /* The new PC will be alternate mode. */ | |
1515 | { | |
1516 | unsigned long reg; | |
1517 | ||
1518 | reg = jtype_target (inst) << 2; | |
1519 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1520 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1521 | } | |
c5aa993b | 1522 | else |
025bb325 | 1523 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1524 | } |
1525 | else | |
025bb325 | 1526 | { /* This gets way messy. */ |
c5aa993b | 1527 | |
025bb325 MS |
1528 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1529 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1530 | { |
c5aa993b JM |
1531 | case 0: /* SPECIAL */ |
1532 | op = rtype_funct (inst); | |
1533 | switch (op) | |
1534 | { | |
1535 | case 8: /* JR */ | |
1536 | case 9: /* JALR */ | |
025bb325 | 1537 | /* Set PC to that address. */ |
0b1b3e42 | 1538 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1539 | break; |
e38d4e1a DJ |
1540 | case 12: /* SYSCALL */ |
1541 | { | |
1542 | struct gdbarch_tdep *tdep; | |
1543 | ||
1544 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1545 | if (tdep->syscall_next_pc != NULL) | |
1546 | pc = tdep->syscall_next_pc (frame); | |
1547 | else | |
1548 | pc += 4; | |
1549 | } | |
1550 | break; | |
c5aa993b JM |
1551 | default: |
1552 | pc += 4; | |
1553 | } | |
1554 | ||
6d82d43b | 1555 | break; /* end SPECIAL */ |
025bb325 | 1556 | case 1: /* REGIMM */ |
c906108c | 1557 | { |
e135b889 DJ |
1558 | op = itype_rt (inst); /* branch condition */ |
1559 | switch (op) | |
c906108c | 1560 | { |
c5aa993b | 1561 | case 0: /* BLTZ */ |
e135b889 DJ |
1562 | case 2: /* BLTZL */ |
1563 | case 16: /* BLTZAL */ | |
c5aa993b | 1564 | case 18: /* BLTZALL */ |
c906108c | 1565 | less_branch: |
0b1b3e42 | 1566 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1567 | pc += mips32_relative_offset (inst) + 4; |
1568 | else | |
1569 | pc += 8; /* after the delay slot */ | |
1570 | break; | |
e135b889 | 1571 | case 1: /* BGEZ */ |
c5aa993b JM |
1572 | case 3: /* BGEZL */ |
1573 | case 17: /* BGEZAL */ | |
1574 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1575 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1576 | pc += mips32_relative_offset (inst) + 4; |
1577 | else | |
1578 | pc += 8; /* after the delay slot */ | |
1579 | break; | |
a385295e MR |
1580 | case 0x1c: /* BPOSGE32 */ |
1581 | case 0x1e: /* BPOSGE64 */ | |
1582 | pc += 4; | |
1583 | if (itype_rs (inst) == 0) | |
1584 | { | |
1585 | unsigned int pos = (op & 2) ? 64 : 32; | |
1586 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1587 | ||
1588 | if (dspctl == -1) | |
1589 | /* No way to handle; it'll most likely trap anyway. */ | |
1590 | break; | |
1591 | ||
1592 | if ((get_frame_register_unsigned (frame, | |
1593 | dspctl) & 0x7f) >= pos) | |
1594 | pc += mips32_relative_offset (inst); | |
1595 | else | |
1596 | pc += 4; | |
1597 | } | |
1598 | break; | |
e135b889 | 1599 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1600 | default: |
1601 | pc += 4; | |
c906108c SS |
1602 | } |
1603 | } | |
6d82d43b | 1604 | break; /* end REGIMM */ |
c5aa993b JM |
1605 | case 2: /* J */ |
1606 | case 3: /* JAL */ | |
1607 | { | |
1608 | unsigned long reg; | |
1609 | reg = jtype_target (inst) << 2; | |
025bb325 | 1610 | /* Upper four bits get never changed... */ |
5b652102 | 1611 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1612 | } |
c5aa993b | 1613 | break; |
e135b889 | 1614 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1615 | equal_branch: |
0b1b3e42 UW |
1616 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1617 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1618 | pc += mips32_relative_offset (inst) + 4; |
1619 | else | |
1620 | pc += 8; | |
1621 | break; | |
e135b889 | 1622 | case 5: /* BNE, BNEL */ |
c5aa993b | 1623 | neq_branch: |
0b1b3e42 UW |
1624 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1625 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1626 | pc += mips32_relative_offset (inst) + 4; |
1627 | else | |
1628 | pc += 8; | |
1629 | break; | |
e135b889 | 1630 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1631 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1632 | pc += mips32_relative_offset (inst) + 4; |
1633 | else | |
1634 | pc += 8; | |
1635 | break; | |
1636 | case 7: | |
e135b889 DJ |
1637 | default: |
1638 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1639 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1640 | pc += mips32_relative_offset (inst) + 4; |
1641 | else | |
1642 | pc += 8; | |
1643 | break; | |
c5aa993b JM |
1644 | } /* switch */ |
1645 | } /* else */ | |
1646 | return pc; | |
1647 | } /* mips32_next_pc */ | |
c906108c | 1648 | |
4cc0665f MR |
1649 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1650 | INSN. */ | |
1651 | ||
1652 | static LONGEST | |
1653 | micromips_relative_offset7 (ULONGEST insn) | |
1654 | { | |
1655 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1656 | } | |
1657 | ||
1658 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1659 | INSN. */ | |
1660 | ||
1661 | static LONGEST | |
1662 | micromips_relative_offset10 (ULONGEST insn) | |
1663 | { | |
1664 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1665 | } | |
1666 | ||
1667 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1668 | INSN. */ | |
1669 | ||
1670 | static LONGEST | |
1671 | micromips_relative_offset16 (ULONGEST insn) | |
1672 | { | |
1673 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1674 | } | |
1675 | ||
1676 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1677 | ||
1678 | static int | |
1679 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1680 | { | |
1681 | ULONGEST insn; | |
1682 | ||
1683 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1684 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1685 | } | |
1686 | ||
1687 | /* Calculate the address of the next microMIPS instruction to execute | |
1688 | after the INSN coprocessor 1 conditional branch instruction at the | |
1689 | address PC. COUNT denotes the number of coprocessor condition bits | |
1690 | examined by the branch. */ | |
1691 | ||
1692 | static CORE_ADDR | |
1693 | micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1694 | ULONGEST insn, CORE_ADDR pc, int count) | |
1695 | { | |
1696 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1697 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1698 | int tf = b5s5_op (insn >> 16) & 1; | |
1699 | int mask = (1 << count) - 1; | |
1700 | ULONGEST fcs; | |
1701 | int cond; | |
1702 | ||
1703 | if (fcsr == -1) | |
1704 | /* No way to handle; it'll most likely trap anyway. */ | |
1705 | return pc; | |
1706 | ||
1707 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1708 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1709 | ||
1710 | if (((cond >> cnum) & mask) != mask * !tf) | |
1711 | pc += micromips_relative_offset16 (insn); | |
1712 | else | |
1713 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1714 | ||
1715 | return pc; | |
1716 | } | |
1717 | ||
1718 | /* Calculate the address of the next microMIPS instruction to execute | |
1719 | after the instruction at the address PC. */ | |
1720 | ||
1721 | static CORE_ADDR | |
1722 | micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
1723 | { | |
1724 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1725 | ULONGEST insn; | |
1726 | ||
1727 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1728 | pc += MIPS_INSN16_SIZE; | |
1729 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1730 | { | |
1731 | /* 48-bit instructions. */ | |
1732 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
1733 | /* No branch or jump instructions in this category. */ | |
1734 | pc += 2 * MIPS_INSN16_SIZE; | |
1735 | break; | |
1736 | ||
1737 | /* 32-bit instructions. */ | |
1738 | case 2 * MIPS_INSN16_SIZE: | |
1739 | insn <<= 16; | |
1740 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1741 | pc += MIPS_INSN16_SIZE; | |
1742 | switch (micromips_op (insn >> 16)) | |
1743 | { | |
1744 | case 0x00: /* POOL32A: bits 000000 */ | |
1745 | if (b0s6_op (insn) == 0x3c | |
1746 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1747 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1748 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1749 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
1750 | pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); | |
1751 | break; | |
1752 | ||
1753 | case 0x10: /* POOL32I: bits 010000 */ | |
1754 | switch (b5s5_op (insn >> 16)) | |
1755 | { | |
1756 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1757 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1758 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
1759 | if (get_frame_register_signed (frame, | |
1760 | b0s5_reg (insn >> 16)) < 0) | |
1761 | pc += micromips_relative_offset16 (insn); | |
1762 | else | |
1763 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1764 | break; | |
1765 | ||
1766 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1767 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1768 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
1769 | if (get_frame_register_signed (frame, | |
1770 | b0s5_reg (insn >> 16)) >= 0) | |
1771 | pc += micromips_relative_offset16 (insn); | |
1772 | else | |
1773 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1774 | break; | |
1775 | ||
1776 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
1777 | if (get_frame_register_signed (frame, | |
1778 | b0s5_reg (insn >> 16)) <= 0) | |
1779 | pc += micromips_relative_offset16 (insn); | |
1780 | else | |
1781 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1782 | break; | |
1783 | ||
1784 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
1785 | if (get_frame_register_signed (frame, | |
1786 | b0s5_reg (insn >> 16)) != 0) | |
1787 | pc += micromips_relative_offset16 (insn); | |
1788 | break; | |
1789 | ||
1790 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
1791 | if (get_frame_register_signed (frame, | |
1792 | b0s5_reg (insn >> 16)) > 0) | |
1793 | pc += micromips_relative_offset16 (insn); | |
1794 | else | |
1795 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1796 | break; | |
1797 | ||
1798 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
1799 | if (get_frame_register_signed (frame, | |
1800 | b0s5_reg (insn >> 16)) == 0) | |
1801 | pc += micromips_relative_offset16 (insn); | |
1802 | break; | |
1803 | ||
1804 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1805 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1806 | if (((insn >> 16) & 0x3) == 0x0) | |
1807 | /* BC2F, BC2T: don't know how to handle these. */ | |
1808 | break; | |
1809 | break; | |
1810 | ||
1811 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1812 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1813 | { | |
1814 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1815 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1816 | ||
1817 | if (dspctl == -1) | |
1818 | /* No way to handle; it'll most likely trap anyway. */ | |
1819 | break; | |
1820 | ||
1821 | if ((get_frame_register_unsigned (frame, | |
1822 | dspctl) & 0x7f) >= pos) | |
1823 | pc += micromips_relative_offset16 (insn); | |
1824 | else | |
1825 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1826 | } | |
1827 | break; | |
1828 | ||
1829 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1830 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1831 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1832 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1833 | if (((insn >> 16) & 0x2) == 0x0) | |
1834 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, | |
1835 | ((insn >> 16) & 0x1) + 1); | |
1836 | break; | |
1837 | ||
1838 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1839 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1840 | if (((insn >> 16) & 0x3) == 0x1) | |
1841 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); | |
1842 | break; | |
1843 | } | |
1844 | break; | |
1845 | ||
1846 | case 0x1d: /* JALS: bits 011101 */ | |
1847 | case 0x35: /* J: bits 110101 */ | |
1848 | case 0x3d: /* JAL: bits 111101 */ | |
1849 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1850 | break; | |
1851 | ||
1852 | case 0x25: /* BEQ: bits 100101 */ | |
1853 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1854 | == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1855 | pc += micromips_relative_offset16 (insn); | |
1856 | else | |
1857 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1858 | break; | |
1859 | ||
1860 | case 0x2d: /* BNE: bits 101101 */ | |
1861 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1862 | != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1863 | pc += micromips_relative_offset16 (insn); | |
1864 | else | |
1865 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1866 | break; | |
1867 | ||
1868 | case 0x3c: /* JALX: bits 111100 */ | |
1869 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
1870 | break; | |
1871 | } | |
1872 | break; | |
1873 | ||
1874 | /* 16-bit instructions. */ | |
1875 | case MIPS_INSN16_SIZE: | |
1876 | switch (micromips_op (insn)) | |
1877 | { | |
1878 | case 0x11: /* POOL16C: bits 010001 */ | |
1879 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
1880 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
1881 | pc = get_frame_register_signed (frame, b0s5_reg (insn)); | |
1882 | else if (b5s5_op (insn) == 0x18) | |
1883 | /* JRADDIUSP: bits 010001 11000 */ | |
1884 | pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); | |
1885 | break; | |
1886 | ||
1887 | case 0x23: /* BEQZ16: bits 100011 */ | |
1888 | { | |
1889 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1890 | ||
1891 | if (get_frame_register_signed (frame, rs) == 0) | |
1892 | pc += micromips_relative_offset7 (insn); | |
1893 | else | |
1894 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1895 | } | |
1896 | break; | |
1897 | ||
1898 | case 0x2b: /* BNEZ16: bits 101011 */ | |
1899 | { | |
1900 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1901 | ||
1902 | if (get_frame_register_signed (frame, rs) != 0) | |
1903 | pc += micromips_relative_offset7 (insn); | |
1904 | else | |
1905 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1906 | } | |
1907 | break; | |
1908 | ||
1909 | case 0x33: /* B16: bits 110011 */ | |
1910 | pc += micromips_relative_offset10 (insn); | |
1911 | break; | |
1912 | } | |
1913 | break; | |
1914 | } | |
1915 | ||
1916 | return pc; | |
1917 | } | |
1918 | ||
c906108c | 1919 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
1920 | mips 16 variant, but fortunately, there fewer instructions. We have |
1921 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1922 | 32 bit instructions. We dont want to set a single step instruction | |
1923 | on the extend instruction either. */ | |
c906108c SS |
1924 | |
1925 | /* Lots of mips16 instruction formats */ | |
1926 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1927 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1928 | enum mips16_inst_fmts |
1929 | { | |
c5aa993b JM |
1930 | itype, /* 0 immediate 5,10 */ |
1931 | ritype, /* 1 5,3,8 */ | |
1932 | rrtype, /* 2 5,3,3,5 */ | |
1933 | rritype, /* 3 5,3,3,5 */ | |
1934 | rrrtype, /* 4 5,3,3,3,2 */ | |
1935 | rriatype, /* 5 5,3,3,1,4 */ | |
1936 | shifttype, /* 6 5,3,3,3,2 */ | |
1937 | i8type, /* 7 5,3,8 */ | |
1938 | i8movtype, /* 8 5,3,3,5 */ | |
1939 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1940 | i64type, /* 10 5,3,8 */ | |
1941 | ri64type, /* 11 5,3,3,5 */ | |
1942 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1943 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1944 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1945 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1946 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1947 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1948 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1949 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1950 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1951 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1952 | }; | |
12f02c2a | 1953 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1954 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1955 | struct upk_mips16 |
6d82d43b AC |
1956 | { |
1957 | CORE_ADDR offset; | |
025bb325 | 1958 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1959 | unsigned int regy; |
1960 | }; | |
c906108c SS |
1961 | |
1962 | ||
12f02c2a | 1963 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1964 | for the bits which make up the immediate extension. */ |
c906108c | 1965 | |
12f02c2a AC |
1966 | static CORE_ADDR |
1967 | extended_offset (unsigned int extension) | |
c906108c | 1968 | { |
12f02c2a | 1969 | CORE_ADDR value; |
130854df | 1970 | |
4c2051c6 | 1971 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1972 | value = value << 6; |
4c2051c6 | 1973 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1974 | value = value << 5; |
130854df MR |
1975 | value |= extension & 0x1f; /* Extract 4:0. */ |
1976 | ||
c5aa993b | 1977 | return value; |
c906108c SS |
1978 | } |
1979 | ||
1980 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1981 | instruction. It won't malfunction, but why make excess remote memory |
1982 | references? If the immediate operands get sign extended or something, | |
1983 | do it after the extension is performed. */ | |
c906108c | 1984 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1985 | when the offset is to be used in relative addressing. */ |
c906108c | 1986 | |
12f02c2a | 1987 | static unsigned int |
e17a4113 | 1988 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1989 | { |
e17a4113 | 1990 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1991 | gdb_byte buf[8]; |
025bb325 | 1992 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1993 | target_read_memory (pc, buf, 2); |
e17a4113 | 1994 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1995 | } |
1996 | ||
1997 | static void | |
e17a4113 | 1998 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1999 | unsigned int extension, |
2000 | unsigned int inst, | |
6d82d43b | 2001 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2002 | { |
12f02c2a AC |
2003 | CORE_ADDR offset; |
2004 | int regx; | |
2005 | int regy; | |
2006 | switch (insn_format) | |
c906108c | 2007 | { |
c5aa993b | 2008 | case itype: |
c906108c | 2009 | { |
12f02c2a AC |
2010 | CORE_ADDR value; |
2011 | if (extension) | |
c5aa993b | 2012 | { |
4c2051c6 MR |
2013 | value = extended_offset ((extension << 16) | inst); |
2014 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2015 | } |
2016 | else | |
c5aa993b | 2017 | { |
12f02c2a | 2018 | value = inst & 0x7ff; |
4c2051c6 | 2019 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2020 | } |
12f02c2a AC |
2021 | offset = value; |
2022 | regx = -1; | |
2023 | regy = -1; | |
c906108c | 2024 | } |
c5aa993b JM |
2025 | break; |
2026 | case ritype: | |
2027 | case i8type: | |
025bb325 | 2028 | { /* A register identifier and an offset. */ |
c906108c | 2029 | /* Most of the fields are the same as I type but the |
025bb325 | 2030 | immediate value is of a different length. */ |
12f02c2a AC |
2031 | CORE_ADDR value; |
2032 | if (extension) | |
c906108c | 2033 | { |
4c2051c6 MR |
2034 | value = extended_offset ((extension << 16) | inst); |
2035 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2036 | } |
c5aa993b JM |
2037 | else |
2038 | { | |
4c2051c6 MR |
2039 | value = inst & 0xff; /* 8 bits */ |
2040 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2041 | } |
12f02c2a | 2042 | offset = value; |
4c2051c6 | 2043 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2044 | regy = -1; |
c5aa993b | 2045 | break; |
c906108c | 2046 | } |
c5aa993b | 2047 | case jalxtype: |
c906108c | 2048 | { |
c5aa993b | 2049 | unsigned long value; |
12f02c2a AC |
2050 | unsigned int nexthalf; |
2051 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2052 | value = value << 16; |
4cc0665f MR |
2053 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2054 | /* Low bit still set. */ | |
c5aa993b | 2055 | value |= nexthalf; |
12f02c2a AC |
2056 | offset = value; |
2057 | regx = -1; | |
2058 | regy = -1; | |
c5aa993b | 2059 | break; |
c906108c SS |
2060 | } |
2061 | default: | |
e2e0b3e5 | 2062 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2063 | } |
12f02c2a AC |
2064 | upk->offset = offset; |
2065 | upk->regx = regx; | |
2066 | upk->regy = regy; | |
c906108c SS |
2067 | } |
2068 | ||
2069 | ||
c5aa993b JM |
2070 | static CORE_ADDR |
2071 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2072 | { |
5b652102 | 2073 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
2074 | } |
2075 | ||
12f02c2a | 2076 | static CORE_ADDR |
0b1b3e42 | 2077 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 2078 | unsigned int extension, unsigned int insn) |
c906108c | 2079 | { |
e17a4113 | 2080 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
2081 | int op = (insn >> 11); |
2082 | switch (op) | |
c906108c | 2083 | { |
6d82d43b | 2084 | case 2: /* Branch */ |
12f02c2a | 2085 | { |
12f02c2a | 2086 | struct upk_mips16 upk; |
e17a4113 | 2087 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 2088 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
2089 | break; |
2090 | } | |
025bb325 MS |
2091 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2092 | instructions. */ | |
12f02c2a AC |
2093 | { |
2094 | struct upk_mips16 upk; | |
e17a4113 | 2095 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
2096 | pc = add_offset_16 (pc, upk.offset); |
2097 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 2098 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2099 | else |
2100 | pc |= 0x01; | |
2101 | break; | |
2102 | } | |
6d82d43b | 2103 | case 4: /* beqz */ |
12f02c2a AC |
2104 | { |
2105 | struct upk_mips16 upk; | |
2106 | int reg; | |
e17a4113 | 2107 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2108 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2109 | if (reg == 0) |
2110 | pc += (upk.offset << 1) + 2; | |
2111 | else | |
2112 | pc += 2; | |
2113 | break; | |
2114 | } | |
6d82d43b | 2115 | case 5: /* bnez */ |
12f02c2a AC |
2116 | { |
2117 | struct upk_mips16 upk; | |
2118 | int reg; | |
e17a4113 | 2119 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2120 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2121 | if (reg != 0) |
2122 | pc += (upk.offset << 1) + 2; | |
2123 | else | |
2124 | pc += 2; | |
2125 | break; | |
2126 | } | |
6d82d43b | 2127 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2128 | { |
2129 | struct upk_mips16 upk; | |
2130 | int reg; | |
e17a4113 | 2131 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2132 | /* upk.regx contains the opcode */ |
0b1b3e42 | 2133 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
2134 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2135 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
2136 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
2137 | pc += (upk.offset << 1) + 2; | |
2138 | else | |
2139 | pc += 2; | |
2140 | break; | |
2141 | } | |
6d82d43b | 2142 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2143 | { |
2144 | struct upk_mips16 upk; | |
2145 | /* upk.fmt = rrtype; */ | |
2146 | op = insn & 0x1f; | |
2147 | if (op == 0) | |
c5aa993b | 2148 | { |
12f02c2a AC |
2149 | int reg; |
2150 | upk.regx = (insn >> 8) & 0x07; | |
2151 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2152 | if ((upk.regy & 1) == 0) |
4cc0665f | 2153 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2154 | else |
2155 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 2156 | pc = get_frame_register_signed (frame, reg); |
c906108c | 2157 | } |
12f02c2a | 2158 | else |
c5aa993b | 2159 | pc += 2; |
12f02c2a AC |
2160 | break; |
2161 | } | |
2162 | case 30: | |
2163 | /* This is an instruction extension. Fetch the real instruction | |
2164 | (which follows the extension) and decode things based on | |
025bb325 | 2165 | that. */ |
12f02c2a AC |
2166 | { |
2167 | pc += 2; | |
e17a4113 UW |
2168 | pc = extended_mips16_next_pc (frame, pc, insn, |
2169 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
2170 | break; |
2171 | } | |
2172 | default: | |
2173 | { | |
2174 | pc += 2; | |
2175 | break; | |
2176 | } | |
c906108c | 2177 | } |
c5aa993b | 2178 | return pc; |
12f02c2a | 2179 | } |
c906108c | 2180 | |
5a89d8aa | 2181 | static CORE_ADDR |
0b1b3e42 | 2182 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 2183 | { |
e17a4113 UW |
2184 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2185 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 2186 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
2187 | } |
2188 | ||
2189 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2190 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2191 | It works by decoding the current instruction and predicting where a |
025bb325 | 2192 | branch will go. This isnt hard because all the data is available. |
4cc0665f | 2193 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2194 | static CORE_ADDR |
0b1b3e42 | 2195 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2196 | { |
4cc0665f MR |
2197 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2198 | ||
2199 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
0b1b3e42 | 2200 | return mips16_next_pc (frame, pc); |
4cc0665f MR |
2201 | else if (mips_pc_is_micromips (gdbarch, pc)) |
2202 | return micromips_next_pc (frame, pc); | |
c5aa993b | 2203 | else |
0b1b3e42 | 2204 | return mips32_next_pc (frame, pc); |
12f02c2a | 2205 | } |
c906108c | 2206 | |
edfae063 AC |
2207 | struct mips_frame_cache |
2208 | { | |
2209 | CORE_ADDR base; | |
2210 | struct trad_frame_saved_reg *saved_regs; | |
2211 | }; | |
2212 | ||
29639122 JB |
2213 | /* Set a register's saved stack address in temp_saved_regs. If an |
2214 | address has already been set for this register, do nothing; this | |
2215 | way we will only recognize the first save of a given register in a | |
2216 | function prologue. | |
eec63939 | 2217 | |
f57d151a UW |
2218 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2219 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2220 | Strictly speaking, only the second range is used as it is only second | |
2221 | range (the ABI instead of ISA registers) that comes into play when finding | |
2222 | saved registers in a frame. */ | |
eec63939 AC |
2223 | |
2224 | static void | |
74ed0bb4 MD |
2225 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2226 | int regnum, CORE_ADDR offset) | |
eec63939 | 2227 | { |
29639122 JB |
2228 | if (this_cache != NULL |
2229 | && this_cache->saved_regs[regnum].addr == -1) | |
2230 | { | |
74ed0bb4 MD |
2231 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2232 | = offset; | |
2233 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2234 | = offset; | |
29639122 | 2235 | } |
eec63939 AC |
2236 | } |
2237 | ||
eec63939 | 2238 | |
29639122 JB |
2239 | /* Fetch the immediate value from a MIPS16 instruction. |
2240 | If the previous instruction was an EXTEND, use it to extend | |
2241 | the upper bits of the immediate value. This is a helper function | |
2242 | for mips16_scan_prologue. */ | |
eec63939 | 2243 | |
29639122 JB |
2244 | static int |
2245 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2246 | unsigned short inst, /* current instruction */ | |
2247 | int nbits, /* number of bits in imm field */ | |
2248 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2249 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2250 | { |
29639122 | 2251 | int offset; |
eec63939 | 2252 | |
29639122 JB |
2253 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2254 | { | |
2255 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2256 | if (offset & 0x8000) /* check for negative extend */ | |
2257 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2258 | return offset | (inst & 0x1f); | |
2259 | } | |
eec63939 | 2260 | else |
29639122 JB |
2261 | { |
2262 | int max_imm = 1 << nbits; | |
2263 | int mask = max_imm - 1; | |
2264 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2265 | |
29639122 JB |
2266 | offset = inst & mask; |
2267 | if (is_signed && (offset & sign_bit)) | |
2268 | offset = 0 - (max_imm - offset); | |
2269 | return offset * scale; | |
2270 | } | |
2271 | } | |
eec63939 | 2272 | |
65596487 | 2273 | |
29639122 JB |
2274 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2275 | the associated FRAME_CACHE if not null. | |
2276 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2277 | |
29639122 | 2278 | static CORE_ADDR |
e17a4113 UW |
2279 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2280 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2281 | struct frame_info *this_frame, |
29639122 JB |
2282 | struct mips_frame_cache *this_cache) |
2283 | { | |
2284 | CORE_ADDR cur_pc; | |
025bb325 | 2285 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2286 | CORE_ADDR sp; |
2287 | long frame_offset = 0; /* Size of stack frame. */ | |
2288 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2289 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2290 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2291 | unsigned inst = 0; /* current instruction */ |
2292 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2293 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 2294 | int reg, offset; |
a343eb3c | 2295 | |
29639122 JB |
2296 | int extend_bytes = 0; |
2297 | int prev_extend_bytes; | |
2298 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 2299 | |
29639122 | 2300 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2301 | THIS_FRAME. */ |
2302 | if (this_frame != NULL) | |
2303 | sp = get_frame_register_signed (this_frame, | |
2304 | gdbarch_num_regs (gdbarch) | |
2305 | + MIPS_SP_REGNUM); | |
29639122 JB |
2306 | else |
2307 | sp = 0; | |
eec63939 | 2308 | |
29639122 JB |
2309 | if (limit_pc > start_pc + 200) |
2310 | limit_pc = start_pc + 200; | |
eec63939 | 2311 | |
95ac2dcf | 2312 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
2313 | { |
2314 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2315 | the immediate offset extension from it in mips16_get_imm. */ | |
2316 | prev_inst = inst; | |
eec63939 | 2317 | |
025bb325 | 2318 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2319 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2320 | cur_pc, NULL); | |
eec63939 | 2321 | |
29639122 JB |
2322 | /* Normally we ignore extend instructions. However, if it is |
2323 | not followed by a valid prologue instruction, then this | |
2324 | instruction is not part of the prologue either. We must | |
2325 | remember in this case to adjust the end_prologue_addr back | |
2326 | over the extend. */ | |
2327 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2328 | { | |
95ac2dcf | 2329 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2330 | continue; |
2331 | } | |
eec63939 | 2332 | |
29639122 JB |
2333 | prev_extend_bytes = extend_bytes; |
2334 | extend_bytes = 0; | |
eec63939 | 2335 | |
29639122 JB |
2336 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2337 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2338 | { | |
2339 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2340 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2341 | frame_offset -= offset; |
2342 | else | |
2343 | /* Exit loop if a positive stack adjustment is found, which | |
2344 | usually means that the stack cleanup code in the function | |
2345 | epilogue is reached. */ | |
2346 | break; | |
2347 | } | |
2348 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2349 | { | |
2350 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2351 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2352 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2353 | } |
2354 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2355 | { | |
2356 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2357 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2358 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2359 | } |
2360 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2361 | { | |
2362 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2363 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2364 | } |
2365 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2366 | { | |
2367 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2368 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2369 | } |
2370 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2371 | { | |
2372 | frame_addr = sp; | |
2373 | frame_reg = 17; | |
2374 | } | |
2375 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2376 | { | |
2377 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2378 | frame_addr = sp + offset; | |
2379 | frame_reg = 17; | |
2380 | frame_adjust = offset; | |
2381 | } | |
2382 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2383 | { | |
2384 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2385 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2386 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2387 | } |
2388 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2389 | { | |
2390 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2391 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2392 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2393 | } |
2394 | else if ((inst & 0xf81f) == 0xe809 | |
2395 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2396 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2397 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2398 | { | |
025bb325 | 2399 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2400 | if (prev_extend_bytes) /* extend */ |
2401 | save_inst |= prev_inst << 16; | |
2402 | } | |
29639122 | 2403 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 2404 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
2405 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2406 | { | |
2407 | /* This instruction is part of the prologue, but we don't | |
2408 | need to do anything special to handle it. */ | |
2409 | } | |
2410 | else | |
2411 | { | |
2412 | /* This instruction is not an instruction typically found | |
2413 | in a prologue, so we must have reached the end of the | |
2414 | prologue. */ | |
2415 | if (end_prologue_addr == 0) | |
2416 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
2417 | } | |
2418 | } | |
eec63939 | 2419 | |
29639122 JB |
2420 | /* The entry instruction is typically the first instruction in a function, |
2421 | and it stores registers at offsets relative to the value of the old SP | |
2422 | (before the prologue). But the value of the sp parameter to this | |
2423 | function is the new SP (after the prologue has been executed). So we | |
2424 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2425 | and can calculate what the old SP must have been. */ |
29639122 JB |
2426 | if (entry_inst != 0) |
2427 | { | |
2428 | int areg_count = (entry_inst >> 8) & 7; | |
2429 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2430 | |
29639122 JB |
2431 | /* The entry instruction always subtracts 32 from the SP. */ |
2432 | frame_offset += 32; | |
2433 | ||
2434 | /* Now we can calculate what the SP must have been at the | |
2435 | start of the function prologue. */ | |
2436 | sp += frame_offset; | |
2437 | ||
2438 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2439 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2440 | { | |
74ed0bb4 | 2441 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2442 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2443 | } |
2444 | ||
2445 | /* Check if the ra register was pushed on the stack. */ | |
2446 | offset = -4; | |
2447 | if (entry_inst & 0x20) | |
2448 | { | |
74ed0bb4 | 2449 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2450 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2451 | } |
2452 | ||
2453 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2454 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2455 | { | |
74ed0bb4 | 2456 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2457 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2458 | } |
2459 | } | |
2460 | ||
2207132d MR |
2461 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2462 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2463 | size of the frame is specified as an immediate field of instruction | |
2464 | and an extended variation exists which lets additional registers and | |
2465 | frame space to be specified. The instruction always treats registers | |
2466 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2467 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2468 | { | |
2469 | static int args_table[16] = { | |
2470 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2471 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2472 | }; | |
2473 | static int astatic_table[16] = { | |
2474 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2475 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2476 | }; | |
2477 | int aregs = (save_inst >> 16) & 0xf; | |
2478 | int xsregs = (save_inst >> 24) & 0x7; | |
2479 | int args = args_table[aregs]; | |
2480 | int astatic = astatic_table[aregs]; | |
2481 | long frame_size; | |
2482 | ||
2483 | if (args < 0) | |
2484 | { | |
2485 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2486 | args = 0; | |
2487 | } | |
2488 | if (astatic < 0) | |
2489 | { | |
2490 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2491 | astatic = 0; | |
2492 | } | |
2493 | ||
2494 | /* For standard SAVE the frame size of 0 means 128. */ | |
2495 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2496 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2497 | frame_size = 16; | |
2498 | frame_size *= 8; | |
2499 | frame_offset += frame_size; | |
2500 | ||
2501 | /* Now we can calculate what the SP must have been at the | |
2502 | start of the function prologue. */ | |
2503 | sp += frame_offset; | |
2504 | ||
2505 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2506 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2507 | { | |
74ed0bb4 | 2508 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2509 | offset += mips_abi_regsize (gdbarch); |
2510 | } | |
2511 | ||
2512 | offset = -4; | |
2513 | ||
2514 | /* Check if the RA register was pushed on the stack. */ | |
2515 | if (save_inst & 0x40) | |
2516 | { | |
74ed0bb4 | 2517 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2518 | offset -= mips_abi_regsize (gdbarch); |
2519 | } | |
2520 | ||
2521 | /* Check if the S8 register was pushed on the stack. */ | |
2522 | if (xsregs > 6) | |
2523 | { | |
74ed0bb4 | 2524 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2525 | offset -= mips_abi_regsize (gdbarch); |
2526 | xsregs--; | |
2527 | } | |
2528 | /* Check if S2-S7 were pushed on the stack. */ | |
2529 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2530 | { | |
74ed0bb4 | 2531 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2532 | offset -= mips_abi_regsize (gdbarch); |
2533 | } | |
2534 | ||
2535 | /* Check if the S1 register was pushed on the stack. */ | |
2536 | if (save_inst & 0x10) | |
2537 | { | |
74ed0bb4 | 2538 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2539 | offset -= mips_abi_regsize (gdbarch); |
2540 | } | |
2541 | /* Check if the S0 register was pushed on the stack. */ | |
2542 | if (save_inst & 0x20) | |
2543 | { | |
74ed0bb4 | 2544 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2545 | offset -= mips_abi_regsize (gdbarch); |
2546 | } | |
2547 | ||
4cc0665f MR |
2548 | /* Check if A0-A3 were pushed on the stack. */ |
2549 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2550 | { | |
2551 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2552 | offset -= mips_abi_regsize (gdbarch); | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | if (this_cache != NULL) | |
2557 | { | |
2558 | this_cache->base = | |
2559 | (get_frame_register_signed (this_frame, | |
2560 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2561 | + frame_offset - frame_adjust); | |
2562 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2563 | be able to get rid of the assignment below, evetually. But it's | |
2564 | still needed for now. */ | |
2565 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2566 | + mips_regnum (gdbarch)->pc] | |
2567 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2568 | } | |
2569 | ||
2570 | /* If we didn't reach the end of the prologue when scanning the function | |
2571 | instructions, then set end_prologue_addr to the address of the | |
2572 | instruction immediately after the last one we scanned. */ | |
2573 | if (end_prologue_addr == 0) | |
2574 | end_prologue_addr = cur_pc; | |
2575 | ||
2576 | return end_prologue_addr; | |
2577 | } | |
2578 | ||
2579 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2580 | Procedures that use the 32-bit instruction set are handled by the | |
2581 | mips_insn32 unwinder. */ | |
2582 | ||
2583 | static struct mips_frame_cache * | |
2584 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2585 | { | |
2586 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2587 | struct mips_frame_cache *cache; | |
2588 | ||
2589 | if ((*this_cache) != NULL) | |
2590 | return (*this_cache); | |
2591 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2592 | (*this_cache) = cache; | |
2593 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2594 | ||
2595 | /* Analyze the function prologue. */ | |
2596 | { | |
2597 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2598 | CORE_ADDR start_addr; | |
2599 | ||
2600 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2601 | if (start_addr == 0) | |
2602 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2603 | /* We can't analyze the prologue if we couldn't find the begining | |
2604 | of the function. */ | |
2605 | if (start_addr == 0) | |
2606 | return cache; | |
2607 | ||
2608 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); | |
2609 | } | |
2610 | ||
2611 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2612 | trad_frame_set_value (cache->saved_regs, | |
2613 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2614 | cache->base); | |
2615 | ||
2616 | return (*this_cache); | |
2617 | } | |
2618 | ||
2619 | static void | |
2620 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2621 | struct frame_id *this_id) | |
2622 | { | |
2623 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2624 | this_cache); | |
2625 | /* This marks the outermost frame. */ | |
2626 | if (info->base == 0) | |
2627 | return; | |
2628 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2629 | } | |
2630 | ||
2631 | static struct value * | |
2632 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2633 | void **this_cache, int regnum) | |
2634 | { | |
2635 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2636 | this_cache); | |
2637 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2638 | } | |
2639 | ||
2640 | static int | |
2641 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2642 | struct frame_info *this_frame, void **this_cache) | |
2643 | { | |
2644 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2645 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2646 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2647 | return 1; | |
2648 | return 0; | |
2649 | } | |
2650 | ||
2651 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2652 | { | |
2653 | NORMAL_FRAME, | |
2654 | default_frame_unwind_stop_reason, | |
2655 | mips_insn16_frame_this_id, | |
2656 | mips_insn16_frame_prev_register, | |
2657 | NULL, | |
2658 | mips_insn16_frame_sniffer | |
2659 | }; | |
2660 | ||
2661 | static CORE_ADDR | |
2662 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2663 | void **this_cache) | |
2664 | { | |
2665 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2666 | this_cache); | |
2667 | return info->base; | |
2668 | } | |
2669 | ||
2670 | static const struct frame_base mips_insn16_frame_base = | |
2671 | { | |
2672 | &mips_insn16_frame_unwind, | |
2673 | mips_insn16_frame_base_address, | |
2674 | mips_insn16_frame_base_address, | |
2675 | mips_insn16_frame_base_address | |
2676 | }; | |
2677 | ||
2678 | static const struct frame_base * | |
2679 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2680 | { | |
2681 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2682 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2683 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2684 | return &mips_insn16_frame_base; | |
2685 | else | |
2686 | return NULL; | |
2687 | } | |
2688 | ||
2689 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2690 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2691 | interpreted directly, and then multiplied by 4. */ | |
2692 | ||
2693 | static int | |
2694 | micromips_decode_imm9 (int imm) | |
2695 | { | |
2696 | imm = (imm ^ 0x100) - 0x100; | |
2697 | if (imm > -3 && imm < 2) | |
2698 | imm ^= 0x100; | |
2699 | return imm << 2; | |
2700 | } | |
2701 | ||
2702 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2703 | the address of the first instruction past the prologue. */ | |
2704 | ||
2705 | static CORE_ADDR | |
2706 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2707 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2708 | struct frame_info *this_frame, | |
2709 | struct mips_frame_cache *this_cache) | |
2710 | { | |
2711 | CORE_ADDR end_prologue_addr = 0; | |
2712 | int prev_non_prologue_insn = 0; | |
2713 | int frame_reg = MIPS_SP_REGNUM; | |
2714 | int this_non_prologue_insn; | |
2715 | int non_prologue_insns = 0; | |
2716 | long frame_offset = 0; /* Size of stack frame. */ | |
2717 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2718 | CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ | |
2719 | CORE_ADDR prev_pc; | |
2720 | CORE_ADDR cur_pc; | |
2721 | ULONGEST insn; /* current instruction */ | |
2722 | CORE_ADDR sp; | |
2723 | long offset; | |
2724 | long sp_adj; | |
2725 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2726 | int reglist; | |
2727 | int breg; | |
2728 | int dreg; | |
2729 | int sreg; | |
2730 | int treg; | |
2731 | int loc; | |
2732 | int op; | |
2733 | int s; | |
2734 | int i; | |
2735 | ||
2736 | /* Can be called when there's no process, and hence when there's no | |
2737 | THIS_FRAME. */ | |
2738 | if (this_frame != NULL) | |
2739 | sp = get_frame_register_signed (this_frame, | |
2740 | gdbarch_num_regs (gdbarch) | |
2741 | + MIPS_SP_REGNUM); | |
2742 | else | |
2743 | sp = 0; | |
2744 | ||
2745 | if (limit_pc > start_pc + 200) | |
2746 | limit_pc = start_pc + 200; | |
2747 | prev_pc = start_pc; | |
2748 | ||
2749 | /* Permit at most one non-prologue non-control-transfer instruction | |
2750 | in the middle which may have been reordered by the compiler for | |
2751 | optimisation. */ | |
2752 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2753 | { | |
2754 | this_non_prologue_insn = 0; | |
2755 | sp_adj = 0; | |
2756 | loc = 0; | |
2757 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2758 | loc += MIPS_INSN16_SIZE; | |
2759 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2760 | { | |
2761 | /* 48-bit instructions. */ | |
2762 | case 3 * MIPS_INSN16_SIZE: | |
2763 | /* No prologue instructions in this category. */ | |
2764 | this_non_prologue_insn = 1; | |
2765 | loc += 2 * MIPS_INSN16_SIZE; | |
2766 | break; | |
2767 | ||
2768 | /* 32-bit instructions. */ | |
2769 | case 2 * MIPS_INSN16_SIZE: | |
2770 | insn <<= 16; | |
2771 | insn |= mips_fetch_instruction (gdbarch, | |
2772 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2773 | loc += MIPS_INSN16_SIZE; | |
2774 | switch (micromips_op (insn >> 16)) | |
2775 | { | |
2776 | /* Record $sp/$fp adjustment. */ | |
2777 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2778 | case 0x0: /* POOL32A: bits 000000 */ | |
2779 | case 0x16: /* POOL32S: bits 010110 */ | |
2780 | op = b0s11_op (insn); | |
2781 | sreg = b0s5_reg (insn >> 16); | |
2782 | treg = b5s5_reg (insn >> 16); | |
2783 | dreg = b11s5_reg (insn); | |
2784 | if (op == 0x1d0 | |
2785 | /* SUBU: bits 000000 00111010000 */ | |
2786 | /* DSUBU: bits 010110 00111010000 */ | |
2787 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
2788 | && treg == 3) | |
2789 | /* (D)SUBU $sp, $v1 */ | |
2790 | sp_adj = v1_off; | |
2791 | else if (op != 0x150 | |
2792 | /* ADDU: bits 000000 00101010000 */ | |
2793 | /* DADDU: bits 010110 00101010000 */ | |
2794 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
2795 | this_non_prologue_insn = 1; | |
2796 | break; | |
2797 | ||
2798 | case 0x8: /* POOL32B: bits 001000 */ | |
2799 | op = b12s4_op (insn); | |
2800 | breg = b0s5_reg (insn >> 16); | |
2801 | reglist = sreg = b5s5_reg (insn >> 16); | |
2802 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
2803 | if ((op == 0x9 || op == 0xc) | |
2804 | /* SWP: bits 001000 1001 */ | |
2805 | /* SDP: bits 001000 1100 */ | |
2806 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
2807 | /* S[DW]P reg,offset($sp) */ | |
2808 | { | |
2809 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
2810 | set_reg_offset (gdbarch, this_cache, | |
2811 | sreg, sp + offset); | |
2812 | set_reg_offset (gdbarch, this_cache, | |
2813 | sreg + 1, sp + offset + s); | |
2814 | } | |
2815 | else if ((op == 0xd || op == 0xf) | |
2816 | /* SWM: bits 001000 1101 */ | |
2817 | /* SDM: bits 001000 1111 */ | |
2818 | && breg == MIPS_SP_REGNUM | |
2819 | /* SWM reglist,offset($sp) */ | |
2820 | && ((reglist >= 1 && reglist <= 9) | |
2821 | || (reglist >= 16 && reglist <= 25))) | |
2822 | { | |
2823 | int sreglist = min(reglist & 0xf, 8); | |
2824 | ||
2825 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
2826 | for (i = 0; i < sreglist; i++) | |
2827 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
2828 | if ((reglist & 0xf) > 8) | |
2829 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
2830 | if ((reglist & 0x10) == 0x10) | |
2831 | set_reg_offset (gdbarch, this_cache, | |
2832 | MIPS_RA_REGNUM, sp + s * i++); | |
2833 | } | |
2834 | else | |
2835 | this_non_prologue_insn = 1; | |
2836 | break; | |
2837 | ||
2838 | /* Record $sp/$fp adjustment. */ | |
2839 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
2840 | case 0xc: /* ADDIU: bits 001100 */ | |
2841 | case 0x17: /* DADDIU: bits 010111 */ | |
2842 | sreg = b0s5_reg (insn >> 16); | |
2843 | dreg = b5s5_reg (insn >> 16); | |
2844 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2845 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
2846 | /* (D)ADDIU $sp, imm */ | |
2847 | sp_adj = offset; | |
2848 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2849 | /* (D)ADDIU $fp, $sp, imm */ | |
2850 | { | |
2851 | frame_addr = sp + offset; | |
2852 | frame_adjust = offset; | |
2853 | frame_reg = 30; | |
2854 | } | |
2855 | else if (sreg != 28 || dreg != 28) | |
2856 | /* (D)ADDIU $gp, imm */ | |
2857 | this_non_prologue_insn = 1; | |
2858 | break; | |
2859 | ||
2860 | /* LUI $v1 is used for larger $sp adjustments. */ | |
2861 | /* Discard LUI $gp is used for PIC code. */ | |
2862 | case 0x10: /* POOL32I: bits 010000 */ | |
2863 | if (b5s5_op (insn >> 16) == 0xd | |
2864 | /* LUI: bits 010000 001101 */ | |
2865 | && b0s5_reg (insn >> 16) == 3) | |
2866 | /* LUI $v1, imm */ | |
2867 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
2868 | else if (b5s5_op (insn >> 16) != 0xd | |
2869 | /* LUI: bits 010000 001101 */ | |
2870 | || b0s5_reg (insn >> 16) != 28) | |
2871 | /* LUI $gp, imm */ | |
2872 | this_non_prologue_insn = 1; | |
2873 | break; | |
2874 | ||
2875 | /* ORI $v1 is used for larger $sp adjustments. */ | |
2876 | case 0x14: /* ORI: bits 010100 */ | |
2877 | sreg = b0s5_reg (insn >> 16); | |
2878 | dreg = b5s5_reg (insn >> 16); | |
2879 | if (sreg == 3 && dreg == 3) | |
2880 | /* ORI $v1, imm */ | |
2881 | v1_off |= b0s16_imm (insn); | |
2882 | else | |
2883 | this_non_prologue_insn = 1; | |
2884 | break; | |
2885 | ||
2886 | case 0x26: /* SWC1: bits 100110 */ | |
2887 | case 0x2e: /* SDC1: bits 101110 */ | |
2888 | breg = b0s5_reg (insn >> 16); | |
2889 | if (breg != MIPS_SP_REGNUM) | |
2890 | /* S[DW]C1 reg,offset($sp) */ | |
2891 | this_non_prologue_insn = 1; | |
2892 | break; | |
2893 | ||
2894 | case 0x36: /* SD: bits 110110 */ | |
2895 | case 0x3e: /* SW: bits 111110 */ | |
2896 | breg = b0s5_reg (insn >> 16); | |
2897 | sreg = b5s5_reg (insn >> 16); | |
2898 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2899 | if (breg == MIPS_SP_REGNUM) | |
2900 | /* S[DW] reg,offset($sp) */ | |
2901 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2902 | else | |
2903 | this_non_prologue_insn = 1; | |
2904 | break; | |
2905 | ||
2906 | default: | |
2907 | this_non_prologue_insn = 1; | |
2908 | break; | |
2909 | } | |
2910 | break; | |
2911 | ||
2912 | /* 16-bit instructions. */ | |
2913 | case MIPS_INSN16_SIZE: | |
2914 | switch (micromips_op (insn)) | |
2915 | { | |
2916 | case 0x3: /* MOVE: bits 000011 */ | |
2917 | sreg = b0s5_reg (insn); | |
2918 | dreg = b5s5_reg (insn); | |
2919 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2920 | /* MOVE $fp, $sp */ | |
2921 | { | |
2922 | frame_addr = sp; | |
2923 | frame_reg = 30; | |
2924 | } | |
2925 | else if ((sreg & 0x1c) != 0x4) | |
2926 | /* MOVE reg, $a0-$a3 */ | |
2927 | this_non_prologue_insn = 1; | |
2928 | break; | |
2929 | ||
2930 | case 0x11: /* POOL16C: bits 010001 */ | |
2931 | if (b6s4_op (insn) == 0x5) | |
2932 | /* SWM: bits 010001 0101 */ | |
2933 | { | |
2934 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
2935 | reglist = b4s2_regl (insn); | |
2936 | for (i = 0; i <= reglist; i++) | |
2937 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
2938 | set_reg_offset (gdbarch, this_cache, | |
2939 | MIPS_RA_REGNUM, sp + 4 * i++); | |
2940 | } | |
2941 | else | |
2942 | this_non_prologue_insn = 1; | |
2943 | break; | |
2944 | ||
2945 | case 0x13: /* POOL16D: bits 010011 */ | |
2946 | if ((insn & 0x1) == 0x1) | |
2947 | /* ADDIUSP: bits 010011 1 */ | |
2948 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
2949 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
2950 | /* ADDIUS5: bits 010011 0 */ | |
2951 | /* ADDIUS5 $sp, imm */ | |
2952 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
2953 | else | |
2954 | this_non_prologue_insn = 1; | |
2955 | break; | |
2956 | ||
2957 | case 0x32: /* SWSP: bits 110010 */ | |
2958 | offset = b0s5_imm (insn) << 2; | |
2959 | sreg = b5s5_reg (insn); | |
2960 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2961 | break; | |
2962 | ||
2963 | default: | |
2964 | this_non_prologue_insn = 1; | |
2965 | break; | |
2966 | } | |
2967 | break; | |
2968 | } | |
2969 | if (sp_adj < 0) | |
2970 | frame_offset -= sp_adj; | |
2971 | ||
2972 | non_prologue_insns += this_non_prologue_insn; | |
2973 | /* Enough non-prologue insns seen or positive stack adjustment? */ | |
2974 | if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0)) | |
2207132d | 2975 | { |
4cc0665f MR |
2976 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
2977 | break; | |
2207132d | 2978 | } |
4cc0665f MR |
2979 | prev_non_prologue_insn = this_non_prologue_insn; |
2980 | prev_pc = cur_pc; | |
2207132d MR |
2981 | } |
2982 | ||
29639122 JB |
2983 | if (this_cache != NULL) |
2984 | { | |
2985 | this_cache->base = | |
4cc0665f | 2986 | (get_frame_register_signed (this_frame, |
b8a22b94 | 2987 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 2988 | + frame_offset - frame_adjust); |
29639122 | 2989 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
2990 | be able to get rid of the assignment below, evetually. But it's |
2991 | still needed for now. */ | |
72a155b4 UW |
2992 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2993 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 2994 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
2995 | } |
2996 | ||
2997 | /* If we didn't reach the end of the prologue when scanning the function | |
2998 | instructions, then set end_prologue_addr to the address of the | |
4cc0665f MR |
2999 | instruction immediately after the last one we scanned. Unless the |
3000 | last one looked like a non-prologue instruction (and we looked ahead), | |
3001 | in which case use its address instead. */ | |
29639122 | 3002 | if (end_prologue_addr == 0) |
4cc0665f | 3003 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
29639122 JB |
3004 | |
3005 | return end_prologue_addr; | |
eec63939 AC |
3006 | } |
3007 | ||
4cc0665f | 3008 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3009 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3010 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3011 | |
3012 | static struct mips_frame_cache * | |
4cc0665f | 3013 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3014 | { |
e17a4113 | 3015 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3016 | struct mips_frame_cache *cache; |
eec63939 AC |
3017 | |
3018 | if ((*this_cache) != NULL) | |
3019 | return (*this_cache); | |
4cc0665f | 3020 | |
29639122 JB |
3021 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3022 | (*this_cache) = cache; | |
b8a22b94 | 3023 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3024 | |
29639122 JB |
3025 | /* Analyze the function prologue. */ |
3026 | { | |
b8a22b94 | 3027 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3028 | CORE_ADDR start_addr; |
eec63939 | 3029 | |
29639122 JB |
3030 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3031 | if (start_addr == 0) | |
4cc0665f | 3032 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3033 | /* We can't analyze the prologue if we couldn't find the begining |
3034 | of the function. */ | |
3035 | if (start_addr == 0) | |
3036 | return cache; | |
eec63939 | 3037 | |
4cc0665f | 3038 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 | 3039 | } |
4cc0665f | 3040 | |
3e8c568d | 3041 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3042 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3043 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3044 | cache->base); |
eec63939 | 3045 | |
29639122 | 3046 | return (*this_cache); |
eec63939 AC |
3047 | } |
3048 | ||
3049 | static void | |
4cc0665f MR |
3050 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3051 | struct frame_id *this_id) | |
eec63939 | 3052 | { |
4cc0665f MR |
3053 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3054 | this_cache); | |
21327321 DJ |
3055 | /* This marks the outermost frame. */ |
3056 | if (info->base == 0) | |
3057 | return; | |
b8a22b94 | 3058 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3059 | } |
3060 | ||
b8a22b94 | 3061 | static struct value * |
4cc0665f MR |
3062 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3063 | void **this_cache, int regnum) | |
eec63939 | 3064 | { |
4cc0665f MR |
3065 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3066 | this_cache); | |
b8a22b94 DJ |
3067 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3068 | } | |
3069 | ||
3070 | static int | |
4cc0665f MR |
3071 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3072 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3073 | { |
4cc0665f | 3074 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3075 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3076 | |
3077 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3078 | return 1; |
3079 | return 0; | |
eec63939 AC |
3080 | } |
3081 | ||
4cc0665f | 3082 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3083 | { |
3084 | NORMAL_FRAME, | |
8fbca658 | 3085 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3086 | mips_micro_frame_this_id, |
3087 | mips_micro_frame_prev_register, | |
b8a22b94 | 3088 | NULL, |
4cc0665f | 3089 | mips_micro_frame_sniffer |
eec63939 AC |
3090 | }; |
3091 | ||
eec63939 | 3092 | static CORE_ADDR |
4cc0665f MR |
3093 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3094 | void **this_cache) | |
eec63939 | 3095 | { |
4cc0665f MR |
3096 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3097 | this_cache); | |
29639122 | 3098 | return info->base; |
eec63939 AC |
3099 | } |
3100 | ||
4cc0665f | 3101 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3102 | { |
4cc0665f MR |
3103 | &mips_micro_frame_unwind, |
3104 | mips_micro_frame_base_address, | |
3105 | mips_micro_frame_base_address, | |
3106 | mips_micro_frame_base_address | |
eec63939 AC |
3107 | }; |
3108 | ||
3109 | static const struct frame_base * | |
4cc0665f | 3110 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3111 | { |
4cc0665f | 3112 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3113 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3114 | |
3115 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3116 | return &mips_micro_frame_base; | |
eec63939 AC |
3117 | else |
3118 | return NULL; | |
edfae063 AC |
3119 | } |
3120 | ||
29639122 JB |
3121 | /* Mark all the registers as unset in the saved_regs array |
3122 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3123 | ||
74ed0bb4 MD |
3124 | static void |
3125 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3126 | { |
29639122 JB |
3127 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3128 | return; | |
3129 | ||
3130 | { | |
74ed0bb4 | 3131 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3132 | int i; |
64159455 | 3133 | |
29639122 JB |
3134 | for (i = 0; i < num_regs; i++) |
3135 | { | |
3136 | this_cache->saved_regs[i].addr = -1; | |
3137 | } | |
3138 | } | |
c906108c SS |
3139 | } |
3140 | ||
025bb325 | 3141 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3142 | the associated FRAME_CACHE if not null. |
3143 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3144 | |
875e1767 | 3145 | static CORE_ADDR |
e17a4113 UW |
3146 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3147 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3148 | struct frame_info *this_frame, |
29639122 | 3149 | struct mips_frame_cache *this_cache) |
c906108c | 3150 | { |
29639122 | 3151 | CORE_ADDR cur_pc; |
025bb325 MS |
3152 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3153 | frame-pointer. */ | |
29639122 JB |
3154 | CORE_ADDR sp; |
3155 | long frame_offset; | |
3156 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3157 | |
29639122 JB |
3158 | CORE_ADDR end_prologue_addr = 0; |
3159 | int seen_sp_adjust = 0; | |
3160 | int load_immediate_bytes = 0; | |
db5f024e | 3161 | int in_delay_slot = 0; |
7d1e6fb8 | 3162 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3163 | |
29639122 | 3164 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3165 | THIS_FRAME. */ |
3166 | if (this_frame != NULL) | |
3167 | sp = get_frame_register_signed (this_frame, | |
3168 | gdbarch_num_regs (gdbarch) | |
3169 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3170 | else |
29639122 | 3171 | sp = 0; |
9022177c | 3172 | |
29639122 JB |
3173 | if (limit_pc > start_pc + 200) |
3174 | limit_pc = start_pc + 200; | |
9022177c | 3175 | |
29639122 | 3176 | restart: |
9022177c | 3177 | |
29639122 | 3178 | frame_offset = 0; |
95ac2dcf | 3179 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3180 | { |
29639122 JB |
3181 | unsigned long inst, high_word, low_word; |
3182 | int reg; | |
9022177c | 3183 | |
025bb325 | 3184 | /* Fetch the instruction. */ |
4cc0665f MR |
3185 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3186 | cur_pc, NULL); | |
9022177c | 3187 | |
29639122 JB |
3188 | /* Save some code by pre-extracting some useful fields. */ |
3189 | high_word = (inst >> 16) & 0xffff; | |
3190 | low_word = inst & 0xffff; | |
3191 | reg = high_word & 0x1f; | |
fe29b929 | 3192 | |
025bb325 | 3193 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3194 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3195 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3196 | { | |
025bb325 | 3197 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
3198 | frame_offset += 0x10000 - low_word; |
3199 | else | |
3200 | /* Exit loop if a positive stack adjustment is found, which | |
3201 | usually means that the stack cleanup code in the function | |
3202 | epilogue is reached. */ | |
3203 | break; | |
3204 | seen_sp_adjust = 1; | |
3205 | } | |
7d1e6fb8 KB |
3206 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3207 | && !regsize_is_64_bits) | |
29639122 | 3208 | { |
74ed0bb4 | 3209 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 3210 | } |
7d1e6fb8 KB |
3211 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3212 | && regsize_is_64_bits) | |
29639122 JB |
3213 | { |
3214 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 3215 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
3216 | } |
3217 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3218 | { | |
3219 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
3220 | if ((long) low_word != frame_offset) | |
3221 | frame_addr = sp + low_word; | |
b8a22b94 | 3222 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3223 | { |
3224 | unsigned alloca_adjust; | |
a4b8ebc8 | 3225 | |
29639122 | 3226 | frame_reg = 30; |
b8a22b94 DJ |
3227 | frame_addr = get_frame_register_signed |
3228 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3229 | |
29639122 JB |
3230 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
3231 | if (alloca_adjust > 0) | |
3232 | { | |
025bb325 | 3233 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3234 | an alloca or somethings similar. Fix sp to |
3235 | "pre-alloca" value, and try again. */ | |
3236 | sp += alloca_adjust; | |
3237 | /* Need to reset the status of all registers. Otherwise, | |
3238 | we will hit a guard that prevents the new address | |
3239 | for each register to be recomputed during the second | |
3240 | pass. */ | |
74ed0bb4 | 3241 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3242 | goto restart; |
3243 | } | |
3244 | } | |
3245 | } | |
3246 | /* move $30,$sp. With different versions of gas this will be either | |
3247 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3248 | Accept any one of these. */ | |
3249 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3250 | { | |
3251 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3252 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3253 | { |
3254 | unsigned alloca_adjust; | |
c906108c | 3255 | |
29639122 | 3256 | frame_reg = 30; |
b8a22b94 DJ |
3257 | frame_addr = get_frame_register_signed |
3258 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3259 | |
29639122 JB |
3260 | alloca_adjust = (unsigned) (frame_addr - sp); |
3261 | if (alloca_adjust > 0) | |
3262 | { | |
025bb325 | 3263 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3264 | an alloca or somethings similar. Fix sp to |
3265 | "pre-alloca" value, and try again. */ | |
3266 | sp = frame_addr; | |
3267 | /* Need to reset the status of all registers. Otherwise, | |
3268 | we will hit a guard that prevents the new address | |
3269 | for each register to be recomputed during the second | |
3270 | pass. */ | |
74ed0bb4 | 3271 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3272 | goto restart; |
3273 | } | |
3274 | } | |
3275 | } | |
7d1e6fb8 KB |
3276 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3277 | && !regsize_is_64_bits) | |
29639122 | 3278 | { |
74ed0bb4 | 3279 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
3280 | } |
3281 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3282 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3283 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3284 | || high_word == 0x3c1c /* lui $gp,n */ | |
3285 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3286 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3287 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3288 | ) | |
19080931 MR |
3289 | { |
3290 | /* These instructions are part of the prologue, but we don't | |
3291 | need to do anything special to handle them. */ | |
3292 | } | |
29639122 JB |
3293 | /* The instructions below load $at or $t0 with an immediate |
3294 | value in preparation for a stack adjustment via | |
025bb325 | 3295 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3296 | initialize a local variable, so we accept them only before |
3297 | a stack adjustment instruction was seen. */ | |
3298 | else if (!seen_sp_adjust | |
19080931 MR |
3299 | && (high_word == 0x3c01 /* lui $at,n */ |
3300 | || high_word == 0x3c08 /* lui $t0,n */ | |
3301 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3302 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3303 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3304 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3305 | )) | |
3306 | { | |
3307 | if (end_prologue_addr == 0) | |
3308 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
3309 | } | |
29639122 | 3310 | else |
19080931 MR |
3311 | { |
3312 | /* This instruction is not an instruction typically found | |
3313 | in a prologue, so we must have reached the end of the | |
3314 | prologue. */ | |
3315 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
3316 | loop now? Why would we need to continue scanning the function | |
3317 | instructions? */ | |
3318 | if (end_prologue_addr == 0) | |
3319 | end_prologue_addr = cur_pc; | |
3320 | ||
3321 | /* Check for branches and jumps. For now, only jump to | |
3322 | register are caught (i.e. returns). */ | |
3323 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
3324 | in_delay_slot = 1; | |
3325 | } | |
db5f024e DJ |
3326 | |
3327 | /* If the previous instruction was a jump, we must have reached | |
3328 | the end of the prologue by now. Stop scanning so that we do | |
3329 | not go past the function return. */ | |
3330 | if (in_delay_slot) | |
3331 | break; | |
a4b8ebc8 | 3332 | } |
c906108c | 3333 | |
29639122 JB |
3334 | if (this_cache != NULL) |
3335 | { | |
3336 | this_cache->base = | |
b8a22b94 DJ |
3337 | (get_frame_register_signed (this_frame, |
3338 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3339 | + frame_offset); |
3340 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3341 | this assignment below, eventually. But it's still needed | |
3342 | for now. */ | |
72a155b4 UW |
3343 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3344 | + mips_regnum (gdbarch)->pc] | |
3345 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3346 | + MIPS_RA_REGNUM]; |
29639122 | 3347 | } |
c906108c | 3348 | |
29639122 JB |
3349 | /* If we didn't reach the end of the prologue when scanning the function |
3350 | instructions, then set end_prologue_addr to the address of the | |
3351 | instruction immediately after the last one we scanned. */ | |
3352 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
3353 | we may as well be careful and do our best if we have a null | |
3354 | end_prologue_addr. */ | |
3355 | if (end_prologue_addr == 0) | |
3356 | end_prologue_addr = cur_pc; | |
3357 | ||
3358 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3359 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3360 | if the load immediate was not followed by a stack adjustment. */ |
3361 | if (load_immediate_bytes && !seen_sp_adjust) | |
3362 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3363 | |
29639122 | 3364 | return end_prologue_addr; |
c906108c SS |
3365 | } |
3366 | ||
29639122 JB |
3367 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3368 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3369 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3370 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3371 | |
29639122 | 3372 | static struct mips_frame_cache * |
b8a22b94 | 3373 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3374 | { |
e17a4113 | 3375 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3376 | struct mips_frame_cache *cache; |
c906108c | 3377 | |
29639122 JB |
3378 | if ((*this_cache) != NULL) |
3379 | return (*this_cache); | |
c5aa993b | 3380 | |
29639122 JB |
3381 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3382 | (*this_cache) = cache; | |
b8a22b94 | 3383 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3384 | |
29639122 JB |
3385 | /* Analyze the function prologue. */ |
3386 | { | |
b8a22b94 | 3387 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3388 | CORE_ADDR start_addr; |
c906108c | 3389 | |
29639122 JB |
3390 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3391 | if (start_addr == 0) | |
e17a4113 | 3392 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3393 | /* We can't analyze the prologue if we couldn't find the begining |
3394 | of the function. */ | |
3395 | if (start_addr == 0) | |
3396 | return cache; | |
c5aa993b | 3397 | |
e17a4113 | 3398 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
3399 | } |
3400 | ||
3e8c568d | 3401 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3402 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3403 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3404 | cache->base); |
c5aa993b | 3405 | |
29639122 | 3406 | return (*this_cache); |
c906108c SS |
3407 | } |
3408 | ||
29639122 | 3409 | static void |
b8a22b94 | 3410 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3411 | struct frame_id *this_id) |
c906108c | 3412 | { |
b8a22b94 | 3413 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3414 | this_cache); |
21327321 DJ |
3415 | /* This marks the outermost frame. */ |
3416 | if (info->base == 0) | |
3417 | return; | |
b8a22b94 | 3418 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3419 | } |
c906108c | 3420 | |
b8a22b94 DJ |
3421 | static struct value * |
3422 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3423 | void **this_cache, int regnum) | |
29639122 | 3424 | { |
b8a22b94 | 3425 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3426 | this_cache); |
b8a22b94 DJ |
3427 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3428 | } | |
3429 | ||
3430 | static int | |
3431 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3432 | struct frame_info *this_frame, void **this_cache) | |
3433 | { | |
3434 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3435 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3436 | return 1; |
3437 | return 0; | |
c906108c SS |
3438 | } |
3439 | ||
29639122 JB |
3440 | static const struct frame_unwind mips_insn32_frame_unwind = |
3441 | { | |
3442 | NORMAL_FRAME, | |
8fbca658 | 3443 | default_frame_unwind_stop_reason, |
29639122 | 3444 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3445 | mips_insn32_frame_prev_register, |
3446 | NULL, | |
3447 | mips_insn32_frame_sniffer | |
29639122 | 3448 | }; |
c906108c | 3449 | |
1c645fec | 3450 | static CORE_ADDR |
b8a22b94 | 3451 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3452 | void **this_cache) |
c906108c | 3453 | { |
b8a22b94 | 3454 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3455 | this_cache); |
3456 | return info->base; | |
3457 | } | |
c906108c | 3458 | |
29639122 JB |
3459 | static const struct frame_base mips_insn32_frame_base = |
3460 | { | |
3461 | &mips_insn32_frame_unwind, | |
3462 | mips_insn32_frame_base_address, | |
3463 | mips_insn32_frame_base_address, | |
3464 | mips_insn32_frame_base_address | |
3465 | }; | |
1c645fec | 3466 | |
29639122 | 3467 | static const struct frame_base * |
b8a22b94 | 3468 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3469 | { |
b8a22b94 | 3470 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3471 | if (mips_pc_is_mips (pc)) |
29639122 | 3472 | return &mips_insn32_frame_base; |
a65bbe44 | 3473 | else |
29639122 JB |
3474 | return NULL; |
3475 | } | |
a65bbe44 | 3476 | |
29639122 | 3477 | static struct trad_frame_cache * |
b8a22b94 | 3478 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3479 | { |
3480 | CORE_ADDR pc; | |
3481 | CORE_ADDR start_addr; | |
3482 | CORE_ADDR stack_addr; | |
3483 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3484 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3485 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3486 | |
29639122 JB |
3487 | if ((*this_cache) != NULL) |
3488 | return (*this_cache); | |
b8a22b94 | 3489 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3490 | (*this_cache) = this_trad_cache; |
1c645fec | 3491 | |
29639122 | 3492 | /* The return address is in the link register. */ |
3e8c568d | 3493 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3494 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3495 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3496 | |
29639122 JB |
3497 | /* Frame ID, since it's a frameless / stackless function, no stack |
3498 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3499 | pc = get_frame_pc (this_frame); |
29639122 | 3500 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3501 | stack_addr = get_frame_register_signed (this_frame, |
3502 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3503 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3504 | |
29639122 JB |
3505 | /* Assume that the frame's base is the same as the |
3506 | stack-pointer. */ | |
3507 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3508 | |
29639122 JB |
3509 | return this_trad_cache; |
3510 | } | |
c906108c | 3511 | |
29639122 | 3512 | static void |
b8a22b94 | 3513 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3514 | struct frame_id *this_id) |
3515 | { | |
3516 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3517 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3518 | trad_frame_get_id (this_trad_cache, this_id); |
3519 | } | |
c906108c | 3520 | |
b8a22b94 DJ |
3521 | static struct value * |
3522 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3523 | void **this_cache, int regnum) | |
29639122 JB |
3524 | { |
3525 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3526 | = mips_stub_frame_cache (this_frame, this_cache); |
3527 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3528 | } |
c906108c | 3529 | |
b8a22b94 DJ |
3530 | static int |
3531 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3532 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3533 | { |
aa6c981f | 3534 | gdb_byte dummy[4]; |
979b38e0 | 3535 | struct obj_section *s; |
b8a22b94 | 3536 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 3537 | struct minimal_symbol *msym; |
979b38e0 | 3538 | |
aa6c981f | 3539 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3540 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3541 | return 1; | |
aa6c981f | 3542 | |
29639122 | 3543 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 3544 | return 1; |
979b38e0 DJ |
3545 | |
3546 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
3547 | s = find_pc_section (pc); | |
3548 | ||
3549 | if (s != NULL | |
3550 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
3551 | ".MIPS.stubs") == 0) | |
b8a22b94 | 3552 | return 1; |
979b38e0 | 3553 | |
db5f024e DJ |
3554 | /* Calling a PIC function from a non-PIC function passes through a |
3555 | stub. The stub for foo is named ".pic.foo". */ | |
3556 | msym = lookup_minimal_symbol_by_pc (pc); | |
3557 | if (msym != NULL | |
3558 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
3559 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
3560 | return 1; | |
3561 | ||
b8a22b94 | 3562 | return 0; |
29639122 | 3563 | } |
c906108c | 3564 | |
b8a22b94 DJ |
3565 | static const struct frame_unwind mips_stub_frame_unwind = |
3566 | { | |
3567 | NORMAL_FRAME, | |
8fbca658 | 3568 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3569 | mips_stub_frame_this_id, |
3570 | mips_stub_frame_prev_register, | |
3571 | NULL, | |
3572 | mips_stub_frame_sniffer | |
3573 | }; | |
3574 | ||
29639122 | 3575 | static CORE_ADDR |
b8a22b94 | 3576 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3577 | void **this_cache) |
3578 | { | |
3579 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3580 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3581 | return trad_frame_get_this_base (this_trad_cache); |
3582 | } | |
0fce0821 | 3583 | |
29639122 JB |
3584 | static const struct frame_base mips_stub_frame_base = |
3585 | { | |
3586 | &mips_stub_frame_unwind, | |
3587 | mips_stub_frame_base_address, | |
3588 | mips_stub_frame_base_address, | |
3589 | mips_stub_frame_base_address | |
3590 | }; | |
3591 | ||
3592 | static const struct frame_base * | |
b8a22b94 | 3593 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3594 | { |
b8a22b94 | 3595 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3596 | return &mips_stub_frame_base; |
3597 | else | |
3598 | return NULL; | |
3599 | } | |
3600 | ||
29639122 | 3601 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3602 | |
29639122 | 3603 | static CORE_ADDR |
24568a2c | 3604 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3605 | { |
24568a2c | 3606 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3607 | |
4cc0665f MR |
3608 | if (is_compact_addr (addr)) |
3609 | addr = unmake_compact_addr (addr); | |
930bd0e0 | 3610 | |
29639122 JB |
3611 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3612 | /* This hack is a work-around for existing boards using PMON, the | |
3613 | simulator, and any other 64-bit targets that doesn't have true | |
3614 | 64-bit addressing. On these targets, the upper 32 bits of | |
3615 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3616 | likely to have been sign extended to all 1s by instruction | |
3617 | sequences that load 32-bit addresses. For example, a typical | |
3618 | piece of code that loads an address is this: | |
65596487 | 3619 | |
29639122 JB |
3620 | lui $r2, <upper 16 bits> |
3621 | ori $r2, <lower 16 bits> | |
65596487 | 3622 | |
29639122 JB |
3623 | But the lui sign-extends the value such that the upper 32 bits |
3624 | may be all 1s. The workaround is simply to mask off these | |
3625 | bits. In the future, gcc may be changed to support true 64-bit | |
3626 | addressing, and this masking will have to be disabled. */ | |
3627 | return addr &= 0xffffffffUL; | |
3628 | else | |
3629 | return addr; | |
65596487 JB |
3630 | } |
3631 | ||
3d5f6d12 DJ |
3632 | |
3633 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3634 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3635 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3636 | the sequence. */ | |
3637 | ||
4cc0665f MR |
3638 | /* Instructions used during single-stepping of atomic sequences, standard |
3639 | ISA version. */ | |
3640 | #define LL_OPCODE 0x30 | |
3641 | #define LLD_OPCODE 0x34 | |
3642 | #define SC_OPCODE 0x38 | |
3643 | #define SCD_OPCODE 0x3c | |
3644 | ||
3d5f6d12 | 3645 | static int |
4cc0665f MR |
3646 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
3647 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
3648 | { |
3649 | CORE_ADDR breaks[2] = {-1, -1}; | |
3650 | CORE_ADDR loc = pc; | |
3651 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3652 | ULONGEST insn; |
3d5f6d12 DJ |
3653 | int insn_count; |
3654 | int index; | |
3655 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3656 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3657 | ||
4cc0665f | 3658 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3659 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3660 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
3661 | return 0; | |
3662 | ||
3663 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3664 | instructions. */ | |
3665 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3666 | { | |
3667 | int is_branch = 0; | |
3668 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3669 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3670 | |
3671 | /* Assume that there is at most one branch in the atomic | |
3672 | sequence. If a branch is found, put a breakpoint in its | |
3673 | destination address. */ | |
3674 | switch (itype_op (insn)) | |
3675 | { | |
3676 | case 0: /* SPECIAL */ | |
3677 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 3678 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3679 | break; |
3680 | case 1: /* REGIMM */ | |
a385295e MR |
3681 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3682 | || ((itype_rt (insn) & 0x1e) == 0 | |
3683 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3684 | break; |
3685 | case 2: /* J */ | |
3686 | case 3: /* JAL */ | |
025bb325 | 3687 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3688 | case 4: /* BEQ */ |
3689 | case 5: /* BNE */ | |
3690 | case 6: /* BLEZ */ | |
3691 | case 7: /* BGTZ */ | |
3692 | case 20: /* BEQL */ | |
3693 | case 21: /* BNEL */ | |
3694 | case 22: /* BLEZL */ | |
3695 | case 23: /* BGTTL */ | |
3696 | is_branch = 1; | |
3697 | break; | |
3698 | case 17: /* COP1 */ | |
a385295e MR |
3699 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3700 | && (itype_rt (insn) & 0x2) == 0); | |
3701 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3702 | break; | |
3703 | /* Fall through. */ | |
3d5f6d12 DJ |
3704 | case 18: /* COP2 */ |
3705 | case 19: /* COP3 */ | |
3706 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3707 | break; | |
3708 | } | |
3709 | if (is_branch) | |
3710 | { | |
3711 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3712 | if (last_breakpoint >= 1) | |
3713 | return 0; /* More than one branch found, fallback to the | |
3714 | standard single-step code. */ | |
3715 | breaks[1] = branch_bp; | |
3716 | last_breakpoint++; | |
3717 | } | |
3718 | ||
3719 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3720 | break; | |
3721 | } | |
3722 | ||
3723 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3724 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
3725 | return 0; | |
3726 | ||
3727 | loc += MIPS_INSN32_SIZE; | |
3728 | ||
3729 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3730 | breaks[0] = loc; | |
3731 | ||
3732 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3733 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3734 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3735 | last_breakpoint = 0; | |
3736 | ||
3737 | /* Effectively inserts the breakpoints. */ | |
3738 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 3739 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
3740 | |
3741 | return 1; | |
3742 | } | |
3743 | ||
4cc0665f MR |
3744 | static int |
3745 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3746 | struct address_space *aspace, | |
3747 | CORE_ADDR pc) | |
3748 | { | |
3749 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3750 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3751 | CORE_ADDR breaks[2] = {-1, -1}; | |
3752 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
3753 | CORE_ADDR loc = pc; | |
3754 | int sc_found = 0; | |
3755 | ULONGEST insn; | |
3756 | int insn_count; | |
3757 | int index; | |
3758 | ||
3759 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3760 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3761 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
3762 | return 0; | |
3763 | loc += MIPS_INSN16_SIZE; | |
3764 | insn <<= 16; | |
3765 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3766 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
3767 | return 0; | |
3768 | loc += MIPS_INSN16_SIZE; | |
3769 | ||
3770 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
3771 | that no atomic sequence is longer than "atomic_sequence_length" | |
3772 | instructions. */ | |
3773 | for (insn_count = 0; | |
3774 | !sc_found && insn_count < atomic_sequence_length; | |
3775 | ++insn_count) | |
3776 | { | |
3777 | int is_branch = 0; | |
3778 | ||
3779 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3780 | loc += MIPS_INSN16_SIZE; | |
3781 | ||
3782 | /* Assume that there is at most one conditional branch in the | |
3783 | atomic sequence. If a branch is found, put a breakpoint in | |
3784 | its destination address. */ | |
3785 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3786 | { | |
3787 | /* 48-bit instructions. */ | |
3788 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
3789 | loc += 2 * MIPS_INSN16_SIZE; | |
3790 | break; | |
3791 | ||
3792 | /* 32-bit instructions. */ | |
3793 | case 2 * MIPS_INSN16_SIZE: | |
3794 | switch (micromips_op (insn)) | |
3795 | { | |
3796 | case 0x10: /* POOL32I: bits 010000 */ | |
3797 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
3798 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
3799 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
3800 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
3801 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
3802 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
3803 | || (insn & 0x3) != 0x0) | |
3804 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
3805 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
3806 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
3807 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
3808 | || (insn & 0x3) != 0x0) | |
3809 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
3810 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
3811 | || (insn & 0x3) != 0x1)) | |
3812 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
3813 | break; | |
3814 | /* Fall through. */ | |
3815 | ||
3816 | case 0x25: /* BEQ: bits 100101 */ | |
3817 | case 0x2d: /* BNE: bits 101101 */ | |
3818 | insn <<= 16; | |
3819 | insn |= mips_fetch_instruction (gdbarch, | |
3820 | ISA_MICROMIPS, loc, NULL); | |
3821 | branch_bp = (loc + MIPS_INSN16_SIZE | |
3822 | + micromips_relative_offset16 (insn)); | |
3823 | is_branch = 1; | |
3824 | break; | |
3825 | ||
3826 | case 0x00: /* POOL32A: bits 000000 */ | |
3827 | insn <<= 16; | |
3828 | insn |= mips_fetch_instruction (gdbarch, | |
3829 | ISA_MICROMIPS, loc, NULL); | |
3830 | if (b0s6_op (insn) != 0x3c | |
3831 | /* POOL32Axf: bits 000000 ... 111100 */ | |
3832 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
3833 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
3834 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
3835 | break; | |
3836 | /* Fall through. */ | |
3837 | ||
3838 | case 0x1d: /* JALS: bits 011101 */ | |
3839 | case 0x35: /* J: bits 110101 */ | |
3840 | case 0x3d: /* JAL: bits 111101 */ | |
3841 | case 0x3c: /* JALX: bits 111100 */ | |
3842 | return 0; /* Fall back to the standard single-step code. */ | |
3843 | ||
3844 | case 0x18: /* POOL32C: bits 011000 */ | |
3845 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
3846 | /* SC, SCD: bits 011000 1x11 */ | |
3847 | sc_found = 1; | |
3848 | break; | |
3849 | } | |
3850 | loc += MIPS_INSN16_SIZE; | |
3851 | break; | |
3852 | ||
3853 | /* 16-bit instructions. */ | |
3854 | case MIPS_INSN16_SIZE: | |
3855 | switch (micromips_op (insn)) | |
3856 | { | |
3857 | case 0x23: /* BEQZ16: bits 100011 */ | |
3858 | case 0x2b: /* BNEZ16: bits 101011 */ | |
3859 | branch_bp = loc + micromips_relative_offset7 (insn); | |
3860 | is_branch = 1; | |
3861 | break; | |
3862 | ||
3863 | case 0x11: /* POOL16C: bits 010001 */ | |
3864 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
3865 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
3866 | && b5s5_op (insn) != 0x18) | |
3867 | /* JRADDIUSP: bits 010001 11000 */ | |
3868 | break; | |
3869 | return 0; /* Fall back to the standard single-step code. */ | |
3870 | ||
3871 | case 0x33: /* B16: bits 110011 */ | |
3872 | return 0; /* Fall back to the standard single-step code. */ | |
3873 | } | |
3874 | break; | |
3875 | } | |
3876 | if (is_branch) | |
3877 | { | |
3878 | if (last_breakpoint >= 1) | |
3879 | return 0; /* More than one branch found, fallback to the | |
3880 | standard single-step code. */ | |
3881 | breaks[1] = branch_bp; | |
3882 | last_breakpoint++; | |
3883 | } | |
3884 | } | |
3885 | if (!sc_found) | |
3886 | return 0; | |
3887 | ||
3888 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3889 | breaks[0] = loc; | |
3890 | ||
3891 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
3892 | placed (branch instruction's destination) in the atomic sequence */ | |
3893 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
3894 | last_breakpoint = 0; | |
3895 | ||
3896 | /* Effectively inserts the breakpoints. */ | |
3897 | for (index = 0; index <= last_breakpoint; index++) | |
3898 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | |
3899 | ||
3900 | return 1; | |
3901 | } | |
3902 | ||
3903 | static int | |
3904 | deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3905 | struct address_space *aspace, CORE_ADDR pc) | |
3906 | { | |
3907 | if (mips_pc_is_mips (pc)) | |
3908 | return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3909 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
3910 | return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3911 | else | |
3912 | return 0; | |
3913 | } | |
3914 | ||
29639122 JB |
3915 | /* mips_software_single_step() is called just before we want to resume |
3916 | the inferior, if we want to single-step it but there is no hardware | |
3917 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 3918 | the target of the coming instruction and breakpoint it. */ |
29639122 | 3919 | |
e6590a1b | 3920 | int |
0b1b3e42 | 3921 | mips_software_single_step (struct frame_info *frame) |
c906108c | 3922 | { |
a6d9a66e | 3923 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 3924 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 3925 | CORE_ADDR pc, next_pc; |
65596487 | 3926 | |
0b1b3e42 | 3927 | pc = get_frame_pc (frame); |
6c95b8df | 3928 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
3929 | return 1; |
3930 | ||
0b1b3e42 | 3931 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 3932 | |
6c95b8df | 3933 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 3934 | return 1; |
29639122 | 3935 | } |
a65bbe44 | 3936 | |
29639122 | 3937 | /* Test whether the PC points to the return instruction at the |
025bb325 | 3938 | end of a function. */ |
65596487 | 3939 | |
29639122 | 3940 | static int |
e17a4113 | 3941 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 3942 | { |
6321c22a MR |
3943 | ULONGEST insn; |
3944 | ULONGEST hint; | |
3945 | ||
3946 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
3947 | called for MIPS16 functions. And likewise microMIPS ones. */ |
3948 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 3949 | |
4cc0665f | 3950 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
3951 | hint = 0x7c0; |
3952 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 3953 | } |
c906108c | 3954 | |
c906108c | 3955 | |
29639122 JB |
3956 | /* This fencepost looks highly suspicious to me. Removing it also |
3957 | seems suspicious as it could affect remote debugging across serial | |
3958 | lines. */ | |
c906108c | 3959 | |
29639122 | 3960 | static CORE_ADDR |
74ed0bb4 | 3961 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
3962 | { |
3963 | CORE_ADDR start_pc; | |
3964 | CORE_ADDR fence; | |
3965 | int instlen; | |
3966 | int seen_adjsp = 0; | |
d6b48e9c | 3967 | struct inferior *inf; |
65596487 | 3968 | |
74ed0bb4 | 3969 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
3970 | start_pc = pc; |
3971 | fence = start_pc - heuristic_fence_post; | |
3972 | if (start_pc == 0) | |
3973 | return 0; | |
65596487 | 3974 | |
29639122 JB |
3975 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
3976 | fence = VM_MIN_ADDRESS; | |
65596487 | 3977 | |
4cc0665f | 3978 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 3979 | |
d6b48e9c PA |
3980 | inf = current_inferior (); |
3981 | ||
025bb325 | 3982 | /* Search back for previous return. */ |
29639122 JB |
3983 | for (start_pc -= instlen;; start_pc -= instlen) |
3984 | if (start_pc < fence) | |
3985 | { | |
3986 | /* It's not clear to me why we reach this point when | |
3987 | stop_soon, but with this test, at least we | |
3988 | don't print out warnings for every child forked (eg, on | |
3989 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 3990 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
3991 | { |
3992 | static int blurb_printed = 0; | |
98b4dd94 | 3993 | |
5af949e3 UW |
3994 | warning (_("GDB can't find the start of the function at %s."), |
3995 | paddress (gdbarch, pc)); | |
29639122 JB |
3996 | |
3997 | if (!blurb_printed) | |
3998 | { | |
3999 | /* This actually happens frequently in embedded | |
4000 | development, when you first connect to a board | |
4001 | and your stack pointer and pc are nowhere in | |
4002 | particular. This message needs to give people | |
4003 | in that situation enough information to | |
4004 | determine that it's no big deal. */ | |
4005 | printf_filtered ("\n\ | |
5af949e3 | 4006 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4007 | and thus can't determine the size of that function's stack frame.\n\ |
4008 | This means that GDB may be unable to access that stack frame, or\n\ | |
4009 | the frames below it.\n\ | |
4010 | This problem is most likely caused by an invalid program counter or\n\ | |
4011 | stack pointer.\n\ | |
4012 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4013 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4014 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4015 | heuristic-fence-post' command.\n", |
4016 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4017 | blurb_printed = 1; |
4018 | } | |
4019 | } | |
4020 | ||
4021 | return 0; | |
4022 | } | |
4cc0665f | 4023 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4024 | { |
4025 | unsigned short inst; | |
4026 | ||
4027 | /* On MIPS16, any one of the following is likely to be the | |
4028 | start of a function: | |
193774b3 MR |
4029 | extend save |
4030 | save | |
29639122 JB |
4031 | entry |
4032 | addiu sp,-n | |
4033 | daddiu sp,-n | |
025bb325 | 4034 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4035 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4036 | if ((inst & 0xff80) == 0x6480) /* save */ |
4037 | { | |
4038 | if (start_pc - instlen >= fence) | |
4039 | { | |
4cc0665f MR |
4040 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4041 | start_pc - instlen, NULL); | |
193774b3 MR |
4042 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4043 | start_pc -= instlen; | |
4044 | } | |
4045 | break; | |
4046 | } | |
4047 | else if (((inst & 0xf81f) == 0xe809 | |
4048 | && (inst & 0x700) != 0x700) /* entry */ | |
4049 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4050 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4051 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4052 | break; |
4053 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4054 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4055 | seen_adjsp = 1; | |
4056 | else | |
4057 | seen_adjsp = 0; | |
4058 | } | |
4cc0665f MR |
4059 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4060 | { | |
4061 | ULONGEST insn; | |
4062 | int stop = 0; | |
4063 | long offset; | |
4064 | int dreg; | |
4065 | int sreg; | |
4066 | ||
4067 | /* On microMIPS, any one of the following is likely to be the | |
4068 | start of a function: | |
4069 | ADDIUSP -imm | |
4070 | (D)ADDIU $sp, -imm | |
4071 | LUI $gp, imm */ | |
4072 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4073 | switch (micromips_op (insn)) | |
4074 | { | |
4075 | case 0xc: /* ADDIU: bits 001100 */ | |
4076 | case 0x17: /* DADDIU: bits 010111 */ | |
4077 | sreg = b0s5_reg (insn); | |
4078 | dreg = b5s5_reg (insn); | |
4079 | insn <<= 16; | |
4080 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4081 | pc + MIPS_INSN16_SIZE, NULL); | |
4082 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4083 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4084 | /* (D)ADDIU $sp, imm */ | |
4085 | && offset < 0) | |
4086 | stop = 1; | |
4087 | break; | |
4088 | ||
4089 | case 0x10: /* POOL32I: bits 010000 */ | |
4090 | if (b5s5_op (insn) == 0xd | |
4091 | /* LUI: bits 010000 001101 */ | |
4092 | && b0s5_reg (insn >> 16) == 28) | |
4093 | /* LUI $gp, imm */ | |
4094 | stop = 1; | |
4095 | break; | |
4096 | ||
4097 | case 0x13: /* POOL16D: bits 010011 */ | |
4098 | if ((insn & 0x1) == 0x1) | |
4099 | /* ADDIUSP: bits 010011 1 */ | |
4100 | { | |
4101 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4102 | if (offset < 0) | |
4103 | /* ADDIUSP -imm */ | |
4104 | stop = 1; | |
4105 | } | |
4106 | else | |
4107 | /* ADDIUS5: bits 010011 0 */ | |
4108 | { | |
4109 | dreg = b5s5_reg (insn); | |
4110 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4111 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4112 | /* ADDIUS5 $sp, -imm */ | |
4113 | stop = 1; | |
4114 | } | |
4115 | break; | |
4116 | } | |
4117 | if (stop) | |
4118 | break; | |
4119 | } | |
e17a4113 | 4120 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4121 | { |
4c7d22cb | 4122 | /* Skip return and its delay slot. */ |
95ac2dcf | 4123 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4124 | break; |
4125 | } | |
4126 | ||
4127 | return start_pc; | |
c906108c SS |
4128 | } |
4129 | ||
6c0d6680 DJ |
4130 | struct mips_objfile_private |
4131 | { | |
4132 | bfd_size_type size; | |
4133 | char *contents; | |
4134 | }; | |
4135 | ||
f09ded24 AC |
4136 | /* According to the current ABI, should the type be passed in a |
4137 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4138 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4139 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4140 | arguments into integer registers. */ |
f09ded24 AC |
4141 | |
4142 | static int | |
74ed0bb4 MD |
4143 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4144 | struct type *arg_type) | |
f09ded24 AC |
4145 | { |
4146 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4147 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4148 | && (typecode == TYPE_CODE_STRUCT |
4149 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4150 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4151 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4152 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4153 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4154 | } |
4155 | ||
49e790b0 | 4156 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4157 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4158 | |
4159 | static int | |
4160 | mips_type_needs_double_align (struct type *type) | |
4161 | { | |
4162 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4163 | |
49e790b0 DJ |
4164 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4165 | return 1; | |
4166 | else if (typecode == TYPE_CODE_STRUCT) | |
4167 | { | |
4168 | if (TYPE_NFIELDS (type) < 1) | |
4169 | return 0; | |
4170 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4171 | } | |
4172 | else if (typecode == TYPE_CODE_UNION) | |
4173 | { | |
361d1df0 | 4174 | int i, n; |
49e790b0 DJ |
4175 | |
4176 | n = TYPE_NFIELDS (type); | |
4177 | for (i = 0; i < n; i++) | |
4178 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4179 | return 1; | |
4180 | return 0; | |
4181 | } | |
4182 | return 0; | |
4183 | } | |
4184 | ||
dc604539 AC |
4185 | /* Adjust the address downward (direction of stack growth) so that it |
4186 | is correctly aligned for a new stack frame. */ | |
4187 | static CORE_ADDR | |
4188 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4189 | { | |
5b03f266 | 4190 | return align_down (addr, 16); |
dc604539 AC |
4191 | } |
4192 | ||
8ae38c14 | 4193 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4194 | |
4195 | static CORE_ADDR | |
4196 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4197 | CORE_ADDR funaddr, struct value **args, | |
4198 | int nargs, struct type *value_type, | |
4199 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4200 | struct regcache *regcache) | |
4201 | { | |
4202 | CORE_ADDR nop_addr; | |
4203 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; | |
4204 | ||
4205 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
4206 | *bp_addr = sp - sizeof (nop_insn); | |
4207 | ||
4208 | /* The breakpoint layer automatically adjusts the address of | |
4209 | breakpoints inserted in a branch delay slot. With enough | |
4210 | bad luck, the 4 bytes located just before our breakpoint | |
4211 | instruction could look like a branch instruction, and thus | |
4212 | trigger the adjustement, and break the function call entirely. | |
4213 | So, we reserve those 4 bytes and write a nop instruction | |
4214 | to prevent that from happening. */ | |
4215 | nop_addr = *bp_addr - sizeof (nop_insn); | |
4216 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); | |
4217 | sp = mips_frame_align (gdbarch, nop_addr); | |
4218 | ||
4219 | /* Inferior resumes at the function entry point. */ | |
4220 | *real_pc = funaddr; | |
4221 | ||
4222 | return sp; | |
4223 | } | |
4224 | ||
f7ab6ec6 | 4225 | static CORE_ADDR |
7d9b040b | 4226 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4227 | struct regcache *regcache, CORE_ADDR bp_addr, |
4228 | int nargs, struct value **args, CORE_ADDR sp, | |
4229 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4230 | { |
4231 | int argreg; | |
4232 | int float_argreg; | |
4233 | int argnum; | |
4234 | int len = 0; | |
4235 | int stack_offset = 0; | |
480d3dd2 | 4236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4237 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4238 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 4239 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 4240 | |
25ab4790 AC |
4241 | /* For shared libraries, "t9" needs to point at the function |
4242 | address. */ | |
4c7d22cb | 4243 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4244 | |
4245 | /* Set the return address register to point to the entry point of | |
4246 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4247 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4248 | |
c906108c | 4249 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4250 | are properly aligned. The stack has to be at least 64-bit |
4251 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4252 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4253 | aligned, so we round to this widest known alignment. */ | |
4254 | ||
5b03f266 AC |
4255 | sp = align_down (sp, 16); |
4256 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4257 | |
46e0f506 | 4258 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4259 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4260 | passed in registers, but that's OK. */ |
c906108c | 4261 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 4262 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 4263 | sp -= align_up (len, 16); |
c906108c | 4264 | |
9ace0497 | 4265 | if (mips_debug) |
6d82d43b | 4266 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4267 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4268 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4269 | |
c906108c | 4270 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4271 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4272 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4273 | |
46e0f506 | 4274 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4275 | if (struct_return) |
9ace0497 AC |
4276 | { |
4277 | if (mips_debug) | |
4278 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4279 | "mips_eabi_push_dummy_call: " |
4280 | "struct_return reg=%d %s\n", | |
5af949e3 | 4281 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4282 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4283 | } |
c906108c SS |
4284 | |
4285 | /* Now load as many as possible of the first arguments into | |
4286 | registers, and push the rest onto the stack. Loop thru args | |
4287 | from first to last. */ | |
4288 | for (argnum = 0; argnum < nargs; argnum++) | |
4289 | { | |
47a35522 MK |
4290 | const gdb_byte *val; |
4291 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 4292 | struct value *arg = args[argnum]; |
4991999e | 4293 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4294 | int len = TYPE_LENGTH (arg_type); |
4295 | enum type_code typecode = TYPE_CODE (arg_type); | |
4296 | ||
9ace0497 AC |
4297 | if (mips_debug) |
4298 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4299 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4300 | argnum + 1, len, (int) typecode); |
9ace0497 | 4301 | |
930bd0e0 KB |
4302 | /* Function pointer arguments to mips16 code need to be made into |
4303 | mips16 pointers. */ | |
4304 | if (typecode == TYPE_CODE_PTR | |
4305 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4306 | { | |
4307 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4308 | len, byte_order); | |
4cc0665f MR |
4309 | if (mips_pc_is_mips (addr)) |
4310 | val = value_contents (arg); | |
4311 | else | |
930bd0e0 KB |
4312 | { |
4313 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 4314 | make_compact_addr (addr)); |
930bd0e0 KB |
4315 | val = valbuf; |
4316 | } | |
930bd0e0 | 4317 | } |
c906108c | 4318 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4319 | reference. */ |
930bd0e0 | 4320 | else if (len > regsize |
9ace0497 | 4321 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4322 | { |
e17a4113 UW |
4323 | store_unsigned_integer (valbuf, regsize, byte_order, |
4324 | value_address (arg)); | |
c906108c | 4325 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 4326 | len = regsize; |
c906108c | 4327 | val = valbuf; |
9ace0497 AC |
4328 | if (mips_debug) |
4329 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4330 | } |
4331 | else | |
47a35522 | 4332 | val = value_contents (arg); |
c906108c SS |
4333 | |
4334 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4335 | even-numbered floating point register. Round the FP register |
4336 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4337 | left. Non MIPS_EABI targets also pass the FP in the integer |
4338 | registers so also round up normal registers. */ | |
74ed0bb4 | 4339 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4340 | { |
4341 | if ((float_argreg & 1)) | |
4342 | float_argreg++; | |
4343 | } | |
c906108c SS |
4344 | |
4345 | /* Floating point arguments passed in registers have to be | |
4346 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4347 | are passed in register pairs; the even register gets |
4348 | the low word, and the odd register gets the high word. | |
4349 | On non-EABI processors, the first two floating point arguments are | |
4350 | also copied to general registers, because MIPS16 functions | |
4351 | don't use float registers for arguments. This duplication of | |
4352 | arguments in general registers can't hurt non-MIPS16 functions | |
4353 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4354 | /* MIPS_EABI squeezes a struct that contains a single floating |
4355 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4356 | stack. */ |
74ed0bb4 MD |
4357 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4358 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4359 | { |
6da397e0 KB |
4360 | /* EABI32 will pass doubles in consecutive registers, even on |
4361 | 64-bit cores. At one time, we used to check the size of | |
4362 | `float_argreg' to determine whether or not to pass doubles | |
4363 | in consecutive registers, but this is not sufficient for | |
4364 | making the ABI determination. */ | |
4365 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4366 | { |
72a155b4 | 4367 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4368 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4369 | long regval; |
c906108c SS |
4370 | |
4371 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4372 | regval = extract_signed_integer (val + low_offset, |
4373 | 4, byte_order); | |
9ace0497 | 4374 | if (mips_debug) |
acdb74a0 | 4375 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4376 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4377 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4378 | |
4379 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4380 | regval = extract_signed_integer (val + 4 - low_offset, |
4381 | 4, byte_order); | |
9ace0497 | 4382 | if (mips_debug) |
acdb74a0 | 4383 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4384 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4385 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4386 | } |
4387 | else | |
4388 | { | |
4389 | /* This is a floating point value that fits entirely | |
4390 | in a single register. */ | |
53a5351d | 4391 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4392 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4393 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4394 | if (mips_debug) |
acdb74a0 | 4395 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4396 | float_argreg, phex (regval, len)); |
a8852dc5 | 4397 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4398 | } |
4399 | } | |
4400 | else | |
4401 | { | |
4402 | /* Copy the argument to general registers or the stack in | |
4403 | register-sized pieces. Large arguments are split between | |
4404 | registers and stack. */ | |
1a69e1e4 DJ |
4405 | /* Note: structs whose size is not a multiple of regsize |
4406 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4407 | them in registers where gcc sometimes puts them on the |
4408 | stack. For maximum compatibility, we will put them in | |
4409 | both places. */ | |
1a69e1e4 | 4410 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 4411 | |
f09ded24 | 4412 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4413 | register are only written to memory. */ |
c906108c SS |
4414 | while (len > 0) |
4415 | { | |
ebafbe83 | 4416 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4417 | int stack_used_p = 0; |
1a69e1e4 | 4418 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 4419 | |
acdb74a0 AC |
4420 | if (mips_debug) |
4421 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4422 | partial_len); | |
4423 | ||
566f0f7a | 4424 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4425 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4426 | || odd_sized_struct |
74ed0bb4 | 4427 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4428 | { |
c906108c | 4429 | /* Should shorter than int integer values be |
025bb325 | 4430 | promoted to int before being stored? */ |
c906108c | 4431 | int longword_offset = 0; |
9ace0497 | 4432 | CORE_ADDR addr; |
566f0f7a | 4433 | stack_used_p = 1; |
72a155b4 | 4434 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4435 | { |
1a69e1e4 | 4436 | if (regsize == 8 |
480d3dd2 AC |
4437 | && (typecode == TYPE_CODE_INT |
4438 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4439 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 4440 | longword_offset = regsize - len; |
480d3dd2 AC |
4441 | else if ((typecode == TYPE_CODE_STRUCT |
4442 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
4443 | && TYPE_LENGTH (arg_type) < regsize) |
4444 | longword_offset = regsize - len; | |
7a292a7a | 4445 | } |
c5aa993b | 4446 | |
9ace0497 AC |
4447 | if (mips_debug) |
4448 | { | |
5af949e3 UW |
4449 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4450 | paddress (gdbarch, stack_offset)); | |
4451 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4452 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4453 | } |
361d1df0 | 4454 | |
9ace0497 AC |
4455 | addr = sp + stack_offset + longword_offset; |
4456 | ||
4457 | if (mips_debug) | |
4458 | { | |
4459 | int i; | |
5af949e3 UW |
4460 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4461 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4462 | for (i = 0; i < partial_len; i++) |
4463 | { | |
6d82d43b | 4464 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4465 | val[i] & 0xff); |
9ace0497 AC |
4466 | } |
4467 | } | |
4468 | write_memory (addr, val, partial_len); | |
c906108c SS |
4469 | } |
4470 | ||
f09ded24 AC |
4471 | /* Note!!! This is NOT an else clause. Odd sized |
4472 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4473 | arguments will not. */ |
566f0f7a | 4474 | /* Write this portion of the argument to a general |
6d82d43b | 4475 | purpose register. */ |
74ed0bb4 MD |
4476 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4477 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4478 | { |
6d82d43b | 4479 | LONGEST regval = |
a8852dc5 | 4480 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4481 | |
9ace0497 | 4482 | if (mips_debug) |
acdb74a0 | 4483 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4484 | argreg, |
1a69e1e4 | 4485 | phex (regval, regsize)); |
a8852dc5 | 4486 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4487 | argreg++; |
c906108c | 4488 | } |
c5aa993b | 4489 | |
c906108c SS |
4490 | len -= partial_len; |
4491 | val += partial_len; | |
4492 | ||
b021a221 MS |
4493 | /* Compute the offset into the stack at which we will |
4494 | copy the next parameter. | |
566f0f7a | 4495 | |
566f0f7a | 4496 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4497 | only needs to be adjusted when it has been used. */ |
c906108c | 4498 | |
46e0f506 | 4499 | if (stack_used_p) |
1a69e1e4 | 4500 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
4501 | } |
4502 | } | |
9ace0497 AC |
4503 | if (mips_debug) |
4504 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4505 | } |
4506 | ||
f10683bb | 4507 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4508 | |
0f71a2f6 JM |
4509 | /* Return adjusted stack pointer. */ |
4510 | return sp; | |
4511 | } | |
4512 | ||
a1f5b845 | 4513 | /* Determine the return value convention being used. */ |
6d82d43b | 4514 | |
9c8fdbfa | 4515 | static enum return_value_convention |
6a3a010b | 4516 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4517 | struct type *type, struct regcache *regcache, |
47a35522 | 4518 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4519 | { |
609ba780 JM |
4520 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4521 | int fp_return_type = 0; | |
4522 | int offset, regnum, xfer; | |
4523 | ||
9c8fdbfa AC |
4524 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4525 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4526 | |
4527 | /* Floating point type? */ | |
4528 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4529 | { | |
4530 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4531 | fp_return_type = 1; | |
4532 | /* Structs with a single field of float type | |
4533 | are returned in a floating point register. */ | |
4534 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4535 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4536 | && TYPE_NFIELDS (type) == 1) | |
4537 | { | |
4538 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4539 | ||
4540 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4541 | fp_return_type = 1; | |
4542 | } | |
4543 | } | |
4544 | ||
4545 | if (fp_return_type) | |
4546 | { | |
4547 | /* A floating-point value belongs in the least significant part | |
4548 | of FP0/FP1. */ | |
4549 | if (mips_debug) | |
4550 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4551 | regnum = mips_regnum (gdbarch)->fp0; | |
4552 | } | |
4553 | else | |
4554 | { | |
4555 | /* An integer value goes in V0/V1. */ | |
4556 | if (mips_debug) | |
4557 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4558 | regnum = MIPS_V0_REGNUM; | |
4559 | } | |
4560 | for (offset = 0; | |
4561 | offset < TYPE_LENGTH (type); | |
4562 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4563 | { | |
4564 | xfer = mips_abi_regsize (gdbarch); | |
4565 | if (offset + xfer > TYPE_LENGTH (type)) | |
4566 | xfer = TYPE_LENGTH (type) - offset; | |
4567 | mips_xfer_register (gdbarch, regcache, | |
4568 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4569 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4570 | offset); | |
4571 | } | |
4572 | ||
9c8fdbfa | 4573 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4574 | } |
4575 | ||
6d82d43b AC |
4576 | |
4577 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4578 | |
8d26208a DJ |
4579 | /* Search for a naturally aligned double at OFFSET inside a struct |
4580 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4581 | registers. */ | |
4582 | ||
4583 | static int | |
74ed0bb4 MD |
4584 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4585 | int offset) | |
8d26208a DJ |
4586 | { |
4587 | int i; | |
4588 | ||
4589 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4590 | return 0; | |
4591 | ||
74ed0bb4 | 4592 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4593 | return 0; |
4594 | ||
4595 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4596 | return 0; | |
4597 | ||
4598 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4599 | { | |
4600 | int pos; | |
4601 | struct type *field_type; | |
4602 | ||
4603 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4604 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4605 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4606 | continue; | |
4607 | ||
4608 | /* If we have gone past the offset, there is no double to pass. */ | |
4609 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4610 | if (pos > offset) | |
4611 | return 0; | |
4612 | ||
4613 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4614 | ||
4615 | /* If this field is entirely before the requested offset, go | |
4616 | on to the next one. */ | |
4617 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4618 | continue; | |
4619 | ||
4620 | /* If this is our special aligned double, we can stop. */ | |
4621 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4622 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4623 | return 1; | |
4624 | ||
4625 | /* This field starts at or before the requested offset, and | |
4626 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4627 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4628 | } |
4629 | ||
4630 | return 0; | |
4631 | } | |
4632 | ||
f7ab6ec6 | 4633 | static CORE_ADDR |
7d9b040b | 4634 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4635 | struct regcache *regcache, CORE_ADDR bp_addr, |
4636 | int nargs, struct value **args, CORE_ADDR sp, | |
4637 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4638 | { |
4639 | int argreg; | |
4640 | int float_argreg; | |
4641 | int argnum; | |
4642 | int len = 0; | |
4643 | int stack_offset = 0; | |
480d3dd2 | 4644 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4645 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4646 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4647 | |
25ab4790 AC |
4648 | /* For shared libraries, "t9" needs to point at the function |
4649 | address. */ | |
4c7d22cb | 4650 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4651 | |
4652 | /* Set the return address register to point to the entry point of | |
4653 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4654 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4655 | |
cb3d25d1 MS |
4656 | /* First ensure that the stack and structure return address (if any) |
4657 | are properly aligned. The stack has to be at least 64-bit | |
4658 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4659 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4660 | aligned, so we round to this widest known alignment. */ | |
4661 | ||
5b03f266 AC |
4662 | sp = align_down (sp, 16); |
4663 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4664 | |
4665 | /* Now make space on the stack for the args. */ | |
4666 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4667 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4668 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4669 | |
4670 | if (mips_debug) | |
6d82d43b | 4671 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4672 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4673 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4674 | |
4675 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4676 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4677 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4678 | |
46e0f506 | 4679 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4680 | if (struct_return) |
4681 | { | |
4682 | if (mips_debug) | |
4683 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4684 | "mips_n32n64_push_dummy_call: " |
4685 | "struct_return reg=%d %s\n", | |
5af949e3 | 4686 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4687 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4688 | } |
4689 | ||
4690 | /* Now load as many as possible of the first arguments into | |
4691 | registers, and push the rest onto the stack. Loop thru args | |
4692 | from first to last. */ | |
4693 | for (argnum = 0; argnum < nargs; argnum++) | |
4694 | { | |
47a35522 | 4695 | const gdb_byte *val; |
cb3d25d1 | 4696 | struct value *arg = args[argnum]; |
4991999e | 4697 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4698 | int len = TYPE_LENGTH (arg_type); |
4699 | enum type_code typecode = TYPE_CODE (arg_type); | |
4700 | ||
4701 | if (mips_debug) | |
4702 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4703 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4704 | argnum + 1, len, (int) typecode); |
4705 | ||
47a35522 | 4706 | val = value_contents (arg); |
cb3d25d1 | 4707 | |
5b68030f JM |
4708 | /* A 128-bit long double value requires an even-odd pair of |
4709 | floating-point registers. */ | |
4710 | if (len == 16 | |
4711 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4712 | && (float_argreg & 1)) | |
4713 | { | |
4714 | float_argreg++; | |
4715 | argreg++; | |
4716 | } | |
4717 | ||
74ed0bb4 MD |
4718 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4719 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4720 | { |
4721 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4722 | in a single register or a pair of registers. */ |
4723 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4724 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4725 | if (mips_debug) |
4726 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4727 | float_argreg, phex (regval, reglen)); |
8d26208a | 4728 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4729 | |
4730 | if (mips_debug) | |
4731 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4732 | argreg, phex (regval, reglen)); |
9c9acae0 | 4733 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4734 | float_argreg++; |
4735 | argreg++; | |
5b68030f JM |
4736 | if (len == 16) |
4737 | { | |
e17a4113 UW |
4738 | regval = extract_unsigned_integer (val + reglen, |
4739 | reglen, byte_order); | |
5b68030f JM |
4740 | if (mips_debug) |
4741 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4742 | float_argreg, phex (regval, reglen)); | |
4743 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4744 | ||
4745 | if (mips_debug) | |
4746 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4747 | argreg, phex (regval, reglen)); | |
4748 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4749 | float_argreg++; | |
4750 | argreg++; | |
4751 | } | |
cb3d25d1 MS |
4752 | } |
4753 | else | |
4754 | { | |
4755 | /* Copy the argument to general registers or the stack in | |
4756 | register-sized pieces. Large arguments are split between | |
4757 | registers and stack. */ | |
ab2e1992 MR |
4758 | /* For N32/N64, structs, unions, or other composite types are |
4759 | treated as a sequence of doublewords, and are passed in integer | |
4760 | or floating point registers as though they were simple scalar | |
4761 | parameters to the extent that they fit, with any excess on the | |
4762 | stack packed according to the normal memory layout of the | |
4763 | object. | |
4764 | The caller does not reserve space for the register arguments; | |
4765 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4766 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4767 | register are only written to memory. */ |
cb3d25d1 MS |
4768 | while (len > 0) |
4769 | { | |
ad018eee | 4770 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4771 | int stack_used_p = 0; |
1a69e1e4 | 4772 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4773 | |
4774 | if (mips_debug) | |
4775 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4776 | partial_len); | |
4777 | ||
74ed0bb4 MD |
4778 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
4779 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 4780 | |
cb3d25d1 | 4781 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4782 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
4783 | { |
4784 | /* Should shorter than int integer values be | |
025bb325 | 4785 | promoted to int before being stored? */ |
cb3d25d1 MS |
4786 | int longword_offset = 0; |
4787 | CORE_ADDR addr; | |
4788 | stack_used_p = 1; | |
72a155b4 | 4789 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 4790 | { |
1a69e1e4 | 4791 | if ((typecode == TYPE_CODE_INT |
5b68030f | 4792 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
4793 | && len <= 4) |
4794 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
4795 | } |
4796 | ||
4797 | if (mips_debug) | |
4798 | { | |
5af949e3 UW |
4799 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4800 | paddress (gdbarch, stack_offset)); | |
4801 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4802 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
4803 | } |
4804 | ||
4805 | addr = sp + stack_offset + longword_offset; | |
4806 | ||
4807 | if (mips_debug) | |
4808 | { | |
4809 | int i; | |
5af949e3 UW |
4810 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4811 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
4812 | for (i = 0; i < partial_len; i++) |
4813 | { | |
6d82d43b | 4814 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
4815 | val[i] & 0xff); |
4816 | } | |
4817 | } | |
4818 | write_memory (addr, val, partial_len); | |
4819 | } | |
4820 | ||
4821 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 4822 | structs may go thru BOTH paths. */ |
cb3d25d1 | 4823 | /* Write this portion of the argument to a general |
6d82d43b | 4824 | purpose register. */ |
74ed0bb4 | 4825 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 4826 | { |
5863b5d5 MR |
4827 | LONGEST regval; |
4828 | ||
4829 | /* Sign extend pointers, 32-bit integers and signed | |
4830 | 16-bit and 8-bit integers; everything else is taken | |
4831 | as is. */ | |
4832 | ||
4833 | if ((partial_len == 4 | |
4834 | && (typecode == TYPE_CODE_PTR | |
4835 | || typecode == TYPE_CODE_INT)) | |
4836 | || (partial_len < 4 | |
4837 | && typecode == TYPE_CODE_INT | |
4838 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
4839 | regval = extract_signed_integer (val, partial_len, |
4840 | byte_order); | |
5863b5d5 | 4841 | else |
e17a4113 UW |
4842 | regval = extract_unsigned_integer (val, partial_len, |
4843 | byte_order); | |
cb3d25d1 MS |
4844 | |
4845 | /* A non-floating-point argument being passed in a | |
4846 | general register. If a struct or union, and if | |
4847 | the remaining length is smaller than the register | |
4848 | size, we have to adjust the register value on | |
4849 | big endian targets. | |
4850 | ||
4851 | It does not seem to be necessary to do the | |
1a69e1e4 | 4852 | same for integral types. */ |
cb3d25d1 | 4853 | |
72a155b4 | 4854 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4855 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4856 | && (typecode == TYPE_CODE_STRUCT |
4857 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4858 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4859 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
4860 | |
4861 | if (mips_debug) | |
4862 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4863 | argreg, | |
1a69e1e4 | 4864 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4865 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 4866 | |
74ed0bb4 | 4867 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
4868 | TYPE_LENGTH (arg_type) - len)) |
4869 | { | |
4870 | if (mips_debug) | |
4871 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
4872 | float_argreg, | |
4873 | phex (regval, MIPS64_REGSIZE)); | |
4874 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
4875 | regval); | |
4876 | } | |
4877 | ||
4878 | float_argreg++; | |
cb3d25d1 MS |
4879 | argreg++; |
4880 | } | |
4881 | ||
4882 | len -= partial_len; | |
4883 | val += partial_len; | |
4884 | ||
b021a221 MS |
4885 | /* Compute the offset into the stack at which we will |
4886 | copy the next parameter. | |
cb3d25d1 MS |
4887 | |
4888 | In N32 (N64?), the stack_offset only needs to be | |
4889 | adjusted when it has been used. */ | |
4890 | ||
4891 | if (stack_used_p) | |
1a69e1e4 | 4892 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
4893 | } |
4894 | } | |
4895 | if (mips_debug) | |
4896 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4897 | } | |
4898 | ||
f10683bb | 4899 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4900 | |
cb3d25d1 MS |
4901 | /* Return adjusted stack pointer. */ |
4902 | return sp; | |
4903 | } | |
4904 | ||
6d82d43b | 4905 | static enum return_value_convention |
6a3a010b | 4906 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 4907 | struct type *type, struct regcache *regcache, |
47a35522 | 4908 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 4909 | { |
72a155b4 | 4910 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
4911 | |
4912 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
4913 | ||
4914 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
4915 | if needed), as appropriate for the type. Composite results (struct, | |
4916 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
4917 | following rules: | |
4918 | ||
4919 | * A struct with only one or two floating point fields is returned in $f0 | |
4920 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
4921 | case. | |
4922 | ||
f08877ba | 4923 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
4924 | $2 (first 64 bits) and $3 (remainder, if necessary). |
4925 | ||
4926 | * Larger composite results are handled by converting the function to a | |
4927 | procedure with an implicit first parameter, which is a pointer to an area | |
4928 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
4929 | that all composite results be handled by conversion to implicit first | |
4930 | parameters. The MIPS/SGI Fortran implementation has always made a | |
4931 | specific exception to return COMPLEX results in the floating point | |
4932 | registers.] */ | |
4933 | ||
f08877ba | 4934 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 4935 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
4936 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4937 | && TYPE_LENGTH (type) == 16 | |
4938 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4939 | { | |
4940 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
4941 | two registers are used in the same as memory order, so the | |
4942 | eight bytes with the lower memory address are in $f0. */ | |
4943 | if (mips_debug) | |
4944 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 4945 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4946 | (gdbarch_num_regs (gdbarch) |
4947 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 4948 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4949 | readbuf, writebuf, 0); |
ba32f989 | 4950 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4951 | (gdbarch_num_regs (gdbarch) |
4952 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 4953 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4954 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
4955 | writebuf ? writebuf + 8 : writebuf, 0); |
4956 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4957 | } | |
6d82d43b AC |
4958 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4959 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4960 | { | |
59aa1faa | 4961 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
4962 | if (mips_debug) |
4963 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4964 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4965 | (gdbarch_num_regs (gdbarch) |
4966 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 4967 | TYPE_LENGTH (type), |
72a155b4 | 4968 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4969 | readbuf, writebuf, 0); |
6d82d43b AC |
4970 | return RETURN_VALUE_REGISTER_CONVENTION; |
4971 | } | |
4972 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4973 | && TYPE_NFIELDS (type) <= 2 | |
4974 | && TYPE_NFIELDS (type) >= 1 | |
4975 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 4976 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
4977 | == TYPE_CODE_FLT)) |
4978 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 4979 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 4980 | == TYPE_CODE_FLT) |
b18bb924 | 4981 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 4982 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
4983 | { |
4984 | /* A struct that contains one or two floats. Each value is part | |
4985 | in the least significant part of their floating point | |
5b68030f | 4986 | register (or GPR, for soft float). */ |
6d82d43b AC |
4987 | int regnum; |
4988 | int field; | |
5b68030f JM |
4989 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
4990 | ? mips_regnum (gdbarch)->fp0 | |
4991 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
4992 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4993 | { | |
4994 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4995 | / TARGET_CHAR_BIT); | |
4996 | if (mips_debug) | |
4997 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4998 | offset); | |
5b68030f JM |
4999 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
5000 | { | |
5001 | /* A 16-byte long double field goes in two consecutive | |
5002 | registers. */ | |
5003 | mips_xfer_register (gdbarch, regcache, | |
5004 | gdbarch_num_regs (gdbarch) + regnum, | |
5005 | 8, | |
5006 | gdbarch_byte_order (gdbarch), | |
5007 | readbuf, writebuf, offset); | |
5008 | mips_xfer_register (gdbarch, regcache, | |
5009 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5010 | 8, | |
5011 | gdbarch_byte_order (gdbarch), | |
5012 | readbuf, writebuf, offset + 8); | |
5013 | } | |
5014 | else | |
5015 | mips_xfer_register (gdbarch, regcache, | |
5016 | gdbarch_num_regs (gdbarch) + regnum, | |
5017 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5018 | gdbarch_byte_order (gdbarch), | |
5019 | readbuf, writebuf, offset); | |
6d82d43b AC |
5020 | } |
5021 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5022 | } | |
5023 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5024 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5025 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5026 | { |
f08877ba | 5027 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5028 | regardless of the byte order. I.e. DO NOT USE |
5029 | mips_xfer_lower. */ | |
5030 | int offset; | |
5031 | int regnum; | |
4c7d22cb | 5032 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5033 | offset < TYPE_LENGTH (type); |
72a155b4 | 5034 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5035 | { |
72a155b4 | 5036 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5037 | if (offset + xfer > TYPE_LENGTH (type)) |
5038 | xfer = TYPE_LENGTH (type) - offset; | |
5039 | if (mips_debug) | |
5040 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5041 | offset, xfer, regnum); | |
ba32f989 DJ |
5042 | mips_xfer_register (gdbarch, regcache, |
5043 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5044 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5045 | offset); | |
6d82d43b AC |
5046 | } |
5047 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5048 | } | |
5049 | else | |
5050 | { | |
5051 | /* A scalar extract each part but least-significant-byte | |
5052 | justified. */ | |
5053 | int offset; | |
5054 | int regnum; | |
4c7d22cb | 5055 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5056 | offset < TYPE_LENGTH (type); |
72a155b4 | 5057 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5058 | { |
72a155b4 | 5059 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5060 | if (offset + xfer > TYPE_LENGTH (type)) |
5061 | xfer = TYPE_LENGTH (type) - offset; | |
5062 | if (mips_debug) | |
5063 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5064 | offset, xfer, regnum); | |
ba32f989 DJ |
5065 | mips_xfer_register (gdbarch, regcache, |
5066 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5067 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5068 | readbuf, writebuf, offset); |
6d82d43b AC |
5069 | } |
5070 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5071 | } | |
5072 | } | |
5073 | ||
6a3a010b MR |
5074 | /* Which registers to use for passing floating-point values between |
5075 | function calls, one of floating-point, general and both kinds of | |
5076 | registers. O32 and O64 use different register kinds for standard | |
5077 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5078 | not know what kind of code is being used (e.g. no debug information) | |
5079 | easier we sometimes use both kinds. */ | |
5080 | ||
5081 | enum mips_fval_reg | |
5082 | { | |
5083 | mips_fval_fpr, | |
5084 | mips_fval_gpr, | |
5085 | mips_fval_both | |
5086 | }; | |
5087 | ||
6d82d43b AC |
5088 | /* O32 ABI stuff. */ |
5089 | ||
5090 | static CORE_ADDR | |
7d9b040b | 5091 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5092 | struct regcache *regcache, CORE_ADDR bp_addr, |
5093 | int nargs, struct value **args, CORE_ADDR sp, | |
5094 | int struct_return, CORE_ADDR struct_addr) | |
5095 | { | |
5096 | int argreg; | |
5097 | int float_argreg; | |
5098 | int argnum; | |
5099 | int len = 0; | |
5100 | int stack_offset = 0; | |
5101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 5102 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5103 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5104 | |
5105 | /* For shared libraries, "t9" needs to point at the function | |
5106 | address. */ | |
4c7d22cb | 5107 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5108 | |
5109 | /* Set the return address register to point to the entry point of | |
5110 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5111 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5112 | |
5113 | /* First ensure that the stack and structure return address (if any) | |
5114 | are properly aligned. The stack has to be at least 64-bit | |
5115 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5116 | aligned. For n32 and n64, stack frames need to be 128-bit |
5117 | aligned, so we round to this widest known alignment. */ | |
5118 | ||
5b03f266 AC |
5119 | sp = align_down (sp, 16); |
5120 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5121 | |
5122 | /* Now make space on the stack for the args. */ | |
5123 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5124 | { |
5125 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
5126 | int arglen = TYPE_LENGTH (arg_type); | |
5127 | ||
5128 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5129 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5130 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5131 | /* Allocate space on the stack. */ |
1a69e1e4 | 5132 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 5133 | } |
5b03f266 | 5134 | sp -= align_up (len, 16); |
ebafbe83 MS |
5135 | |
5136 | if (mips_debug) | |
6d82d43b | 5137 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5138 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5139 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5140 | |
5141 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5142 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5143 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5144 | |
bcb0cc15 | 5145 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5146 | if (struct_return) |
5147 | { | |
5148 | if (mips_debug) | |
5149 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5150 | "mips_o32_push_dummy_call: " |
5151 | "struct_return reg=%d %s\n", | |
5af949e3 | 5152 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5153 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5154 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5155 | } |
5156 | ||
5157 | /* Now load as many as possible of the first arguments into | |
5158 | registers, and push the rest onto the stack. Loop thru args | |
5159 | from first to last. */ | |
5160 | for (argnum = 0; argnum < nargs; argnum++) | |
5161 | { | |
47a35522 | 5162 | const gdb_byte *val; |
ebafbe83 | 5163 | struct value *arg = args[argnum]; |
4991999e | 5164 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5165 | int len = TYPE_LENGTH (arg_type); |
5166 | enum type_code typecode = TYPE_CODE (arg_type); | |
5167 | ||
5168 | if (mips_debug) | |
5169 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5170 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5171 | argnum + 1, len, (int) typecode); |
5172 | ||
47a35522 | 5173 | val = value_contents (arg); |
46cac009 AC |
5174 | |
5175 | /* 32-bit ABIs always start floating point arguments in an | |
5176 | even-numbered floating point register. Round the FP register | |
5177 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5178 | left. O32 targets also pass the FP in the integer registers |
5179 | so also round up normal registers. */ | |
74ed0bb4 | 5180 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5181 | { |
5182 | if ((float_argreg & 1)) | |
5183 | float_argreg++; | |
5184 | } | |
5185 | ||
5186 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5187 | treated specially. On 32-bit architectures, doubles are |
5188 | passed in register pairs; the even FP register gets the | |
5189 | low word, and the odd FP register gets the high word. | |
5190 | On O32, the first two floating point arguments are also | |
5191 | copied to general registers, following their memory order, | |
5192 | because MIPS16 functions don't use float registers for | |
5193 | arguments. This duplication of arguments in general | |
5194 | registers can't hurt non-MIPS16 functions, because those | |
5195 | registers are normally skipped. */ | |
46cac009 | 5196 | |
74ed0bb4 MD |
5197 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5198 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5199 | { |
8b07f6d8 | 5200 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5201 | { |
6a3a010b MR |
5202 | int freg_offset = gdbarch_byte_order (gdbarch) |
5203 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5204 | unsigned long regval; |
5205 | ||
6a3a010b MR |
5206 | /* First word. */ |
5207 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5208 | if (mips_debug) |
5209 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5210 | float_argreg + freg_offset, |
5211 | phex (regval, 4)); | |
025bb325 | 5212 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5213 | float_argreg++ + freg_offset, |
5214 | regval); | |
46cac009 AC |
5215 | if (mips_debug) |
5216 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5217 | argreg, phex (regval, 4)); | |
9c9acae0 | 5218 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5219 | |
6a3a010b MR |
5220 | /* Second word. */ |
5221 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5222 | if (mips_debug) |
5223 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5224 | float_argreg - freg_offset, |
5225 | phex (regval, 4)); | |
025bb325 | 5226 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5227 | float_argreg++ - freg_offset, |
5228 | regval); | |
46cac009 AC |
5229 | if (mips_debug) |
5230 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5231 | argreg, phex (regval, 4)); | |
9c9acae0 | 5232 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5233 | } |
5234 | else | |
5235 | { | |
5236 | /* This is a floating point value that fits entirely | |
5237 | in a single register. */ | |
5238 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5239 | above to ensure that it is even register aligned. */ |
e17a4113 | 5240 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5241 | if (mips_debug) |
5242 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5243 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5244 | regcache_cooked_write_unsigned (regcache, |
5245 | float_argreg++, regval); | |
5b68030f JM |
5246 | /* Although two FP registers are reserved for each |
5247 | argument, only one corresponding integer register is | |
5248 | reserved. */ | |
46cac009 AC |
5249 | if (mips_debug) |
5250 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5251 | argreg, phex (regval, len)); | |
5b68030f | 5252 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5253 | } |
5254 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5255 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5256 | } |
5257 | else | |
5258 | { | |
5259 | /* Copy the argument to general registers or the stack in | |
5260 | register-sized pieces. Large arguments are split between | |
5261 | registers and stack. */ | |
1a69e1e4 DJ |
5262 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5263 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5264 | them in registers where gcc sometimes puts them on the |
5265 | stack. For maximum compatibility, we will put them in | |
5266 | both places. */ | |
1a69e1e4 DJ |
5267 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5268 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5269 | /* Structures should be aligned to eight bytes (even arg registers) |
5270 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5271 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5272 | { |
5273 | if ((argreg & 1)) | |
968b5391 MR |
5274 | { |
5275 | argreg++; | |
1a69e1e4 | 5276 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5277 | } |
46cac009 | 5278 | } |
46cac009 AC |
5279 | while (len > 0) |
5280 | { | |
5281 | /* Remember if the argument was written to the stack. */ | |
5282 | int stack_used_p = 0; | |
1a69e1e4 | 5283 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5284 | |
5285 | if (mips_debug) | |
5286 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5287 | partial_len); | |
5288 | ||
5289 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5290 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5291 | || odd_sized_struct) |
46cac009 AC |
5292 | { |
5293 | /* Should shorter than int integer values be | |
025bb325 | 5294 | promoted to int before being stored? */ |
46cac009 AC |
5295 | int longword_offset = 0; |
5296 | CORE_ADDR addr; | |
5297 | stack_used_p = 1; | |
46cac009 AC |
5298 | |
5299 | if (mips_debug) | |
5300 | { | |
5af949e3 UW |
5301 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5302 | paddress (gdbarch, stack_offset)); | |
5303 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5304 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5305 | } |
5306 | ||
5307 | addr = sp + stack_offset + longword_offset; | |
5308 | ||
5309 | if (mips_debug) | |
5310 | { | |
5311 | int i; | |
5af949e3 UW |
5312 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5313 | paddress (gdbarch, addr)); | |
46cac009 AC |
5314 | for (i = 0; i < partial_len; i++) |
5315 | { | |
6d82d43b | 5316 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5317 | val[i] & 0xff); |
5318 | } | |
5319 | } | |
5320 | write_memory (addr, val, partial_len); | |
5321 | } | |
5322 | ||
5323 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5324 | structs may go thru BOTH paths. */ |
46cac009 | 5325 | /* Write this portion of the argument to a general |
6d82d43b | 5326 | purpose register. */ |
74ed0bb4 | 5327 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5328 | { |
e17a4113 UW |
5329 | LONGEST regval = extract_signed_integer (val, partial_len, |
5330 | byte_order); | |
4246e332 | 5331 | /* Value may need to be sign extended, because |
1b13c4f6 | 5332 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5333 | |
5334 | /* A non-floating-point argument being passed in a | |
5335 | general register. If a struct or union, and if | |
5336 | the remaining length is smaller than the register | |
5337 | size, we have to adjust the register value on | |
5338 | big endian targets. | |
5339 | ||
5340 | It does not seem to be necessary to do the | |
5341 | same for integral types. | |
5342 | ||
5343 | Also don't do this adjustment on O64 binaries. | |
5344 | ||
5345 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5346 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5347 | mips_abi_regsize(), generates a left shift |
5348 | as part of storing the argument in a register | |
5349 | (the left shift isn't generated when | |
1b13c4f6 | 5350 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5351 | it is quite possible that this is GCC |
5352 | contradicting the LE/O32 ABI, GDB has not been | |
5353 | adjusted to accommodate this. Either someone | |
5354 | needs to demonstrate that the LE/O32 ABI | |
5355 | specifies such a left shift OR this new ABI gets | |
5356 | identified as such and GDB gets tweaked | |
5357 | accordingly. */ | |
5358 | ||
72a155b4 | 5359 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5360 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5361 | && (typecode == TYPE_CODE_STRUCT |
5362 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5363 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5364 | * TARGET_CHAR_BIT); |
46cac009 AC |
5365 | |
5366 | if (mips_debug) | |
5367 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5368 | argreg, | |
1a69e1e4 | 5369 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5370 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5371 | argreg++; |
5372 | ||
5373 | /* Prevent subsequent floating point arguments from | |
5374 | being passed in floating point registers. */ | |
74ed0bb4 | 5375 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5376 | } |
5377 | ||
5378 | len -= partial_len; | |
5379 | val += partial_len; | |
5380 | ||
b021a221 MS |
5381 | /* Compute the offset into the stack at which we will |
5382 | copy the next parameter. | |
46cac009 | 5383 | |
6d82d43b AC |
5384 | In older ABIs, the caller reserved space for |
5385 | registers that contained arguments. This was loosely | |
5386 | refered to as their "home". Consequently, space is | |
5387 | always allocated. */ | |
46cac009 | 5388 | |
1a69e1e4 | 5389 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5390 | } |
5391 | } | |
5392 | if (mips_debug) | |
5393 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5394 | } | |
5395 | ||
f10683bb | 5396 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5397 | |
46cac009 AC |
5398 | /* Return adjusted stack pointer. */ |
5399 | return sp; | |
5400 | } | |
5401 | ||
6d82d43b | 5402 | static enum return_value_convention |
6a3a010b | 5403 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5404 | struct type *type, struct regcache *regcache, |
47a35522 | 5405 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5406 | { |
6a3a010b | 5407 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5408 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5409 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5410 | enum mips_fval_reg fval_reg; |
6d82d43b | 5411 | |
6a3a010b | 5412 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5413 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5414 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5415 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5416 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5417 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5418 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5419 | { | |
6a3a010b MR |
5420 | /* A single-precision floating-point value. If reading in or copying, |
5421 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5422 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5423 | and GPR2. We do not support reading in with no function known, if | |
5424 | this safety check ever triggers, then we'll have to try harder. */ | |
5425 | gdb_assert (function || !readbuf); | |
6d82d43b | 5426 | if (mips_debug) |
6a3a010b MR |
5427 | switch (fval_reg) |
5428 | { | |
5429 | case mips_fval_fpr: | |
5430 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5431 | break; | |
5432 | case mips_fval_gpr: | |
5433 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5434 | break; | |
5435 | case mips_fval_both: | |
5436 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5437 | break; | |
5438 | } | |
5439 | if (fval_reg != mips_fval_gpr) | |
5440 | mips_xfer_register (gdbarch, regcache, | |
5441 | (gdbarch_num_regs (gdbarch) | |
5442 | + mips_regnum (gdbarch)->fp0), | |
5443 | TYPE_LENGTH (type), | |
5444 | gdbarch_byte_order (gdbarch), | |
5445 | readbuf, writebuf, 0); | |
5446 | if (fval_reg != mips_fval_fpr) | |
5447 | mips_xfer_register (gdbarch, regcache, | |
5448 | gdbarch_num_regs (gdbarch) + 2, | |
5449 | TYPE_LENGTH (type), | |
5450 | gdbarch_byte_order (gdbarch), | |
5451 | readbuf, writebuf, 0); | |
6d82d43b AC |
5452 | return RETURN_VALUE_REGISTER_CONVENTION; |
5453 | } | |
5454 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5455 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5456 | { | |
6a3a010b MR |
5457 | /* A double-precision floating-point value. If reading in or copying, |
5458 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5459 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5460 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5461 | no function known, if this safety check ever triggers, then we'll | |
5462 | have to try harder. */ | |
5463 | gdb_assert (function || !readbuf); | |
6d82d43b | 5464 | if (mips_debug) |
6a3a010b MR |
5465 | switch (fval_reg) |
5466 | { | |
5467 | case mips_fval_fpr: | |
5468 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5469 | break; | |
5470 | case mips_fval_gpr: | |
5471 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5472 | break; | |
5473 | case mips_fval_both: | |
5474 | fprintf_unfiltered (gdb_stderr, | |
5475 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5476 | break; | |
5477 | } | |
5478 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5479 | { |
6a3a010b MR |
5480 | /* The most significant part goes in FP1, and the least significant |
5481 | in FP0. */ | |
5482 | switch (gdbarch_byte_order (gdbarch)) | |
5483 | { | |
5484 | case BFD_ENDIAN_LITTLE: | |
5485 | mips_xfer_register (gdbarch, regcache, | |
5486 | (gdbarch_num_regs (gdbarch) | |
5487 | + mips_regnum (gdbarch)->fp0 + 0), | |
5488 | 4, gdbarch_byte_order (gdbarch), | |
5489 | readbuf, writebuf, 0); | |
5490 | mips_xfer_register (gdbarch, regcache, | |
5491 | (gdbarch_num_regs (gdbarch) | |
5492 | + mips_regnum (gdbarch)->fp0 + 1), | |
5493 | 4, gdbarch_byte_order (gdbarch), | |
5494 | readbuf, writebuf, 4); | |
5495 | break; | |
5496 | case BFD_ENDIAN_BIG: | |
5497 | mips_xfer_register (gdbarch, regcache, | |
5498 | (gdbarch_num_regs (gdbarch) | |
5499 | + mips_regnum (gdbarch)->fp0 + 1), | |
5500 | 4, gdbarch_byte_order (gdbarch), | |
5501 | readbuf, writebuf, 0); | |
5502 | mips_xfer_register (gdbarch, regcache, | |
5503 | (gdbarch_num_regs (gdbarch) | |
5504 | + mips_regnum (gdbarch)->fp0 + 0), | |
5505 | 4, gdbarch_byte_order (gdbarch), | |
5506 | readbuf, writebuf, 4); | |
5507 | break; | |
5508 | default: | |
5509 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5510 | } | |
5511 | } | |
5512 | if (fval_reg != mips_fval_fpr) | |
5513 | { | |
5514 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5515 | following these registers' memory order. */ | |
ba32f989 | 5516 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5517 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5518 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5519 | readbuf, writebuf, 0); |
ba32f989 | 5520 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5521 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5522 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5523 | readbuf, writebuf, 4); |
6d82d43b AC |
5524 | } |
5525 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5526 | } | |
5527 | #if 0 | |
5528 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5529 | && TYPE_NFIELDS (type) <= 2 | |
5530 | && TYPE_NFIELDS (type) >= 1 | |
5531 | && ((TYPE_NFIELDS (type) == 1 | |
5532 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5533 | == TYPE_CODE_FLT)) | |
5534 | || (TYPE_NFIELDS (type) == 2 | |
5535 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5536 | == TYPE_CODE_FLT) | |
5537 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5538 | == TYPE_CODE_FLT))) | |
5539 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5540 | { | |
5541 | /* A struct that contains one or two floats. Each value is part | |
5542 | in the least significant part of their floating point | |
5543 | register.. */ | |
870cd05e | 5544 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
5545 | int regnum; |
5546 | int field; | |
72a155b4 | 5547 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5548 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5549 | { | |
5550 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5551 | / TARGET_CHAR_BIT); | |
5552 | if (mips_debug) | |
5553 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5554 | offset); | |
ba32f989 DJ |
5555 | mips_xfer_register (gdbarch, regcache, |
5556 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5557 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5558 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5559 | readbuf, writebuf, offset); |
6d82d43b AC |
5560 | } |
5561 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5562 | } | |
5563 | #endif | |
5564 | #if 0 | |
5565 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5566 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5567 | { | |
5568 | /* A structure or union. Extract the left justified value, | |
5569 | regardless of the byte order. I.e. DO NOT USE | |
5570 | mips_xfer_lower. */ | |
5571 | int offset; | |
5572 | int regnum; | |
4c7d22cb | 5573 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5574 | offset < TYPE_LENGTH (type); |
72a155b4 | 5575 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5576 | { |
72a155b4 | 5577 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5578 | if (offset + xfer > TYPE_LENGTH (type)) |
5579 | xfer = TYPE_LENGTH (type) - offset; | |
5580 | if (mips_debug) | |
5581 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5582 | offset, xfer, regnum); | |
ba32f989 DJ |
5583 | mips_xfer_register (gdbarch, regcache, |
5584 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5585 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5586 | } | |
5587 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5588 | } | |
5589 | #endif | |
5590 | else | |
5591 | { | |
5592 | /* A scalar extract each part but least-significant-byte | |
5593 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5594 | the ISA. */ |
6d82d43b AC |
5595 | int offset; |
5596 | int regnum; | |
4c7d22cb | 5597 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5598 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5599 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5600 | { |
1a69e1e4 | 5601 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5602 | if (offset + xfer > TYPE_LENGTH (type)) |
5603 | xfer = TYPE_LENGTH (type) - offset; | |
5604 | if (mips_debug) | |
5605 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5606 | offset, xfer, regnum); | |
ba32f989 DJ |
5607 | mips_xfer_register (gdbarch, regcache, |
5608 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5609 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5610 | readbuf, writebuf, offset); |
6d82d43b AC |
5611 | } |
5612 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5613 | } | |
5614 | } | |
5615 | ||
5616 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5617 | ABI. */ | |
46cac009 AC |
5618 | |
5619 | static CORE_ADDR | |
7d9b040b | 5620 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5621 | struct regcache *regcache, CORE_ADDR bp_addr, |
5622 | int nargs, | |
5623 | struct value **args, CORE_ADDR sp, | |
5624 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5625 | { |
5626 | int argreg; | |
5627 | int float_argreg; | |
5628 | int argnum; | |
5629 | int len = 0; | |
5630 | int stack_offset = 0; | |
480d3dd2 | 5631 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 5632 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5633 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5634 | |
25ab4790 AC |
5635 | /* For shared libraries, "t9" needs to point at the function |
5636 | address. */ | |
4c7d22cb | 5637 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5638 | |
5639 | /* Set the return address register to point to the entry point of | |
5640 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5641 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5642 | |
46cac009 AC |
5643 | /* First ensure that the stack and structure return address (if any) |
5644 | are properly aligned. The stack has to be at least 64-bit | |
5645 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5646 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5647 | aligned, so we round to this widest known alignment. */ | |
5648 | ||
5b03f266 AC |
5649 | sp = align_down (sp, 16); |
5650 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5651 | |
5652 | /* Now make space on the stack for the args. */ | |
5653 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5654 | { |
5655 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
5656 | int arglen = TYPE_LENGTH (arg_type); | |
5657 | ||
968b5391 | 5658 | /* Allocate space on the stack. */ |
1a69e1e4 | 5659 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 5660 | } |
5b03f266 | 5661 | sp -= align_up (len, 16); |
46cac009 AC |
5662 | |
5663 | if (mips_debug) | |
6d82d43b | 5664 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5665 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5666 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5667 | |
5668 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5669 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5670 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5671 | |
5672 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5673 | if (struct_return) | |
5674 | { | |
5675 | if (mips_debug) | |
5676 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5677 | "mips_o64_push_dummy_call: " |
5678 | "struct_return reg=%d %s\n", | |
5af949e3 | 5679 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5680 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5681 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5682 | } |
5683 | ||
5684 | /* Now load as many as possible of the first arguments into | |
5685 | registers, and push the rest onto the stack. Loop thru args | |
5686 | from first to last. */ | |
5687 | for (argnum = 0; argnum < nargs; argnum++) | |
5688 | { | |
47a35522 | 5689 | const gdb_byte *val; |
930bd0e0 | 5690 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 5691 | struct value *arg = args[argnum]; |
4991999e | 5692 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5693 | int len = TYPE_LENGTH (arg_type); |
5694 | enum type_code typecode = TYPE_CODE (arg_type); | |
5695 | ||
5696 | if (mips_debug) | |
5697 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5698 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5699 | argnum + 1, len, (int) typecode); |
5700 | ||
47a35522 | 5701 | val = value_contents (arg); |
ebafbe83 | 5702 | |
930bd0e0 KB |
5703 | /* Function pointer arguments to mips16 code need to be made into |
5704 | mips16 pointers. */ | |
5705 | if (typecode == TYPE_CODE_PTR | |
5706 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
5707 | { | |
5708 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
5709 | len, byte_order); | |
4cc0665f | 5710 | if (!mips_pc_is_mips (addr)) |
930bd0e0 KB |
5711 | { |
5712 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 5713 | make_compact_addr (addr)); |
930bd0e0 KB |
5714 | val = valbuf; |
5715 | } | |
5716 | } | |
5717 | ||
ebafbe83 | 5718 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5719 | treated specially. On 32-bit architectures, doubles are |
5720 | passed in register pairs; the even FP register gets the | |
5721 | low word, and the odd FP register gets the high word. | |
5722 | On O64, the first two floating point arguments are also | |
5723 | copied to general registers, because MIPS16 functions | |
5724 | don't use float registers for arguments. This duplication | |
5725 | of arguments in general registers can't hurt non-MIPS16 | |
5726 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5727 | |
74ed0bb4 MD |
5728 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5729 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5730 | { |
e17a4113 | 5731 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5732 | if (mips_debug) |
5733 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5734 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5735 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5736 | if (mips_debug) |
5737 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5738 | argreg, phex (regval, len)); | |
9c9acae0 | 5739 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5740 | argreg++; |
ebafbe83 | 5741 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5742 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5743 | } |
5744 | else | |
5745 | { | |
5746 | /* Copy the argument to general registers or the stack in | |
5747 | register-sized pieces. Large arguments are split between | |
5748 | registers and stack. */ | |
1a69e1e4 | 5749 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5750 | are treated specially: Irix cc passes them in registers |
5751 | where gcc sometimes puts them on the stack. For maximum | |
5752 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5753 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5754 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5755 | while (len > 0) |
5756 | { | |
5757 | /* Remember if the argument was written to the stack. */ | |
5758 | int stack_used_p = 0; | |
1a69e1e4 | 5759 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5760 | |
5761 | if (mips_debug) | |
5762 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5763 | partial_len); | |
5764 | ||
5765 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5766 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5767 | || odd_sized_struct) |
ebafbe83 MS |
5768 | { |
5769 | /* Should shorter than int integer values be | |
025bb325 | 5770 | promoted to int before being stored? */ |
ebafbe83 MS |
5771 | int longword_offset = 0; |
5772 | CORE_ADDR addr; | |
5773 | stack_used_p = 1; | |
72a155b4 | 5774 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5775 | { |
1a69e1e4 DJ |
5776 | if ((typecode == TYPE_CODE_INT |
5777 | || typecode == TYPE_CODE_PTR | |
5778 | || typecode == TYPE_CODE_FLT) | |
5779 | && len <= 4) | |
5780 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5781 | } |
5782 | ||
5783 | if (mips_debug) | |
5784 | { | |
5af949e3 UW |
5785 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5786 | paddress (gdbarch, stack_offset)); | |
5787 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5788 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5789 | } |
5790 | ||
5791 | addr = sp + stack_offset + longword_offset; | |
5792 | ||
5793 | if (mips_debug) | |
5794 | { | |
5795 | int i; | |
5af949e3 UW |
5796 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5797 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5798 | for (i = 0; i < partial_len; i++) |
5799 | { | |
6d82d43b | 5800 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
5801 | val[i] & 0xff); |
5802 | } | |
5803 | } | |
5804 | write_memory (addr, val, partial_len); | |
5805 | } | |
5806 | ||
5807 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5808 | structs may go thru BOTH paths. */ |
ebafbe83 | 5809 | /* Write this portion of the argument to a general |
6d82d43b | 5810 | purpose register. */ |
74ed0bb4 | 5811 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 5812 | { |
e17a4113 UW |
5813 | LONGEST regval = extract_signed_integer (val, partial_len, |
5814 | byte_order); | |
4246e332 | 5815 | /* Value may need to be sign extended, because |
1b13c4f6 | 5816 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
5817 | |
5818 | /* A non-floating-point argument being passed in a | |
5819 | general register. If a struct or union, and if | |
5820 | the remaining length is smaller than the register | |
5821 | size, we have to adjust the register value on | |
5822 | big endian targets. | |
5823 | ||
5824 | It does not seem to be necessary to do the | |
025bb325 | 5825 | same for integral types. */ |
480d3dd2 | 5826 | |
72a155b4 | 5827 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5828 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5829 | && (typecode == TYPE_CODE_STRUCT |
5830 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5831 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5832 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
5833 | |
5834 | if (mips_debug) | |
5835 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5836 | argreg, | |
1a69e1e4 | 5837 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5838 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
5839 | argreg++; |
5840 | ||
5841 | /* Prevent subsequent floating point arguments from | |
5842 | being passed in floating point registers. */ | |
74ed0bb4 | 5843 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
5844 | } |
5845 | ||
5846 | len -= partial_len; | |
5847 | val += partial_len; | |
5848 | ||
b021a221 MS |
5849 | /* Compute the offset into the stack at which we will |
5850 | copy the next parameter. | |
ebafbe83 | 5851 | |
6d82d43b AC |
5852 | In older ABIs, the caller reserved space for |
5853 | registers that contained arguments. This was loosely | |
5854 | refered to as their "home". Consequently, space is | |
5855 | always allocated. */ | |
ebafbe83 | 5856 | |
1a69e1e4 | 5857 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
5858 | } |
5859 | } | |
5860 | if (mips_debug) | |
5861 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5862 | } | |
5863 | ||
f10683bb | 5864 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5865 | |
ebafbe83 MS |
5866 | /* Return adjusted stack pointer. */ |
5867 | return sp; | |
5868 | } | |
5869 | ||
9c8fdbfa | 5870 | static enum return_value_convention |
6a3a010b | 5871 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 5872 | struct type *type, struct regcache *regcache, |
47a35522 | 5873 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5874 | { |
6a3a010b | 5875 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5876 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5877 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5878 | enum mips_fval_reg fval_reg; |
7a076fd2 | 5879 | |
6a3a010b | 5880 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
5881 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5882 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5883 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5884 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 5885 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 5886 | { |
6a3a010b MR |
5887 | /* A floating-point value. If reading in or copying, then we get it |
5888 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
5889 | If writing out only, then we put it to both FP0 and GPR2. We do | |
5890 | not support reading in with no function known, if this safety | |
5891 | check ever triggers, then we'll have to try harder. */ | |
5892 | gdb_assert (function || !readbuf); | |
7a076fd2 | 5893 | if (mips_debug) |
6a3a010b MR |
5894 | switch (fval_reg) |
5895 | { | |
5896 | case mips_fval_fpr: | |
5897 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5898 | break; | |
5899 | case mips_fval_gpr: | |
5900 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5901 | break; | |
5902 | case mips_fval_both: | |
5903 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5904 | break; | |
5905 | } | |
5906 | if (fval_reg != mips_fval_gpr) | |
5907 | mips_xfer_register (gdbarch, regcache, | |
5908 | (gdbarch_num_regs (gdbarch) | |
5909 | + mips_regnum (gdbarch)->fp0), | |
5910 | TYPE_LENGTH (type), | |
5911 | gdbarch_byte_order (gdbarch), | |
5912 | readbuf, writebuf, 0); | |
5913 | if (fval_reg != mips_fval_fpr) | |
5914 | mips_xfer_register (gdbarch, regcache, | |
5915 | gdbarch_num_regs (gdbarch) + 2, | |
5916 | TYPE_LENGTH (type), | |
5917 | gdbarch_byte_order (gdbarch), | |
5918 | readbuf, writebuf, 0); | |
7a076fd2 FF |
5919 | return RETURN_VALUE_REGISTER_CONVENTION; |
5920 | } | |
5921 | else | |
5922 | { | |
5923 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 5924 | justified. */ |
7a076fd2 FF |
5925 | int offset; |
5926 | int regnum; | |
5927 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
5928 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 5929 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 5930 | { |
1a69e1e4 | 5931 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
5932 | if (offset + xfer > TYPE_LENGTH (type)) |
5933 | xfer = TYPE_LENGTH (type) - offset; | |
5934 | if (mips_debug) | |
5935 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5936 | offset, xfer, regnum); | |
ba32f989 DJ |
5937 | mips_xfer_register (gdbarch, regcache, |
5938 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5939 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5940 | readbuf, writebuf, offset); |
7a076fd2 FF |
5941 | } |
5942 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5943 | } | |
6d82d43b AC |
5944 | } |
5945 | ||
dd824b04 DJ |
5946 | /* Floating point register management. |
5947 | ||
5948 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
5949 | 64bit operations, these early MIPS cpus treat fp register pairs | |
5950 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
5951 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
5952 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
5953 | double precision floats into two 32-bit chunks and store them in | |
5954 | consecutive fp regs. To display 64-bit floats stored in this | |
5955 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
5956 | Throw in user-configurable endianness and you have a real mess. | |
5957 | ||
5958 | The way this works is: | |
5959 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
5960 | double-precision value will be split across two logical registers. | |
5961 | The lower-numbered logical register will hold the low-order bits, | |
5962 | regardless of the processor's endianness. | |
5963 | - If we are on a 64-bit processor, and we are looking for a | |
5964 | single-precision value, it will be in the low ordered bits | |
5965 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
5966 | save slot in memory. | |
5967 | - If we are in 64-bit mode, everything is straightforward. | |
5968 | ||
5969 | Note that this code only deals with "live" registers at the top of the | |
5970 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 5971 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
5972 | interface that can deal with dynamic saved register sizes -- fp |
5973 | regs could be 32 bits wide in one frame and 64 on the frame above | |
5974 | and below). */ | |
5975 | ||
5976 | /* Copy a 32-bit single-precision value from the current frame | |
5977 | into rare_buffer. */ | |
5978 | ||
5979 | static void | |
e11c53d2 | 5980 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 5981 | gdb_byte *rare_buffer) |
dd824b04 | 5982 | { |
72a155b4 UW |
5983 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5984 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 5985 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 5986 | |
e11c53d2 | 5987 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 5988 | error (_("can't read register %d (%s)"), |
72a155b4 | 5989 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
5990 | if (raw_size == 8) |
5991 | { | |
5992 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 5993 | 32 bits. */ |
dd824b04 DJ |
5994 | int offset; |
5995 | ||
72a155b4 | 5996 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
5997 | offset = 4; |
5998 | else | |
5999 | offset = 0; | |
6000 | ||
6001 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6002 | } | |
6003 | else | |
6004 | { | |
6005 | memcpy (rare_buffer, raw_buffer, 4); | |
6006 | } | |
6007 | } | |
6008 | ||
6009 | /* Copy a 64-bit double-precision value from the current frame into | |
6010 | rare_buffer. This may include getting half of it from the next | |
6011 | register. */ | |
6012 | ||
6013 | static void | |
e11c53d2 | 6014 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6015 | gdb_byte *rare_buffer) |
dd824b04 | 6016 | { |
72a155b4 UW |
6017 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6018 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6019 | |
9c9acae0 | 6020 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6021 | { |
6022 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6023 | all 64 bits. */ |
e11c53d2 | 6024 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6025 | error (_("can't read register %d (%s)"), |
72a155b4 | 6026 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6027 | } |
6028 | else | |
6029 | { | |
72a155b4 | 6030 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6031 | |
72a155b4 | 6032 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6033 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6034 | _("mips_read_fp_register_double: bad access to " |
6035 | "odd-numbered FP register")); | |
dd824b04 DJ |
6036 | |
6037 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6038 | each register. */ |
72a155b4 | 6039 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6040 | { |
e11c53d2 AC |
6041 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6042 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6043 | } |
361d1df0 | 6044 | else |
dd824b04 | 6045 | { |
e11c53d2 AC |
6046 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6047 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6048 | } |
6049 | } | |
6050 | } | |
6051 | ||
c906108c | 6052 | static void |
e11c53d2 AC |
6053 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6054 | int regnum) | |
025bb325 | 6055 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6056 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6057 | gdb_byte *raw_buffer; |
025bb325 | 6058 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 6059 | int inv1, inv2; |
c5aa993b | 6060 | |
025bb325 MS |
6061 | raw_buffer = alloca (2 * register_size (gdbarch, |
6062 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 6063 | |
72a155b4 | 6064 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6065 | fprintf_filtered (file, "%*s", |
72a155b4 | 6066 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6067 | ""); |
f0ef6b29 | 6068 | |
72a155b4 | 6069 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6070 | { |
79a45b7d TT |
6071 | struct value_print_options opts; |
6072 | ||
f0ef6b29 KB |
6073 | /* 4-byte registers: Print hex and floating. Also print even |
6074 | numbered registers as doubles. */ | |
e11c53d2 | 6075 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
6076 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6077 | raw_buffer, &inv1); | |
c5aa993b | 6078 | |
79a45b7d | 6079 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6080 | print_scalar_formatted (raw_buffer, |
6081 | builtin_type (gdbarch)->builtin_uint32, | |
6082 | &opts, 'w', file); | |
dd824b04 | 6083 | |
e11c53d2 | 6084 | fprintf_filtered (file, " flt: "); |
1adad886 | 6085 | if (inv1) |
e11c53d2 | 6086 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 6087 | else |
e11c53d2 | 6088 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6089 | |
72a155b4 | 6090 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6091 | { |
e11c53d2 | 6092 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6093 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6094 | raw_buffer, &inv2); | |
1adad886 | 6095 | |
e11c53d2 | 6096 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6097 | if (inv2) |
e11c53d2 | 6098 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 6099 | else |
e11c53d2 | 6100 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 6101 | } |
c906108c SS |
6102 | } |
6103 | else | |
dd824b04 | 6104 | { |
79a45b7d TT |
6105 | struct value_print_options opts; |
6106 | ||
f0ef6b29 | 6107 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6108 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
6109 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6110 | raw_buffer, &inv1); | |
c906108c | 6111 | |
e11c53d2 | 6112 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6113 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6114 | raw_buffer, &inv2); | |
f0ef6b29 | 6115 | |
79a45b7d | 6116 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6117 | print_scalar_formatted (raw_buffer, |
6118 | builtin_type (gdbarch)->builtin_uint64, | |
6119 | &opts, 'g', file); | |
f0ef6b29 | 6120 | |
e11c53d2 | 6121 | fprintf_filtered (file, " flt: "); |
1adad886 | 6122 | if (inv1) |
e11c53d2 | 6123 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 6124 | else |
e11c53d2 | 6125 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6126 | |
e11c53d2 | 6127 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6128 | if (inv2) |
e11c53d2 | 6129 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 6130 | else |
e11c53d2 | 6131 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
6132 | } |
6133 | } | |
6134 | ||
6135 | static void | |
e11c53d2 | 6136 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6137 | int regnum) |
f0ef6b29 | 6138 | { |
a4b8ebc8 | 6139 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6140 | struct value_print_options opts; |
de15c4ab | 6141 | struct value *val; |
1adad886 | 6142 | |
004159a2 | 6143 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6144 | { |
e11c53d2 | 6145 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6146 | return; |
6147 | } | |
6148 | ||
de15c4ab PA |
6149 | val = get_frame_register_value (frame, regnum); |
6150 | if (value_optimized_out (val)) | |
f0ef6b29 | 6151 | { |
c9f4d572 | 6152 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 6153 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 6154 | return; |
c906108c | 6155 | } |
f0ef6b29 | 6156 | |
72a155b4 | 6157 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6158 | |
6159 | /* The problem with printing numeric register names (r26, etc.) is that | |
6160 | the user can't use them on input. Probably the best solution is to | |
6161 | fix it so that either the numeric or the funky (a2, etc.) names | |
6162 | are accepted on input. */ | |
6163 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6164 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6165 | else |
e11c53d2 | 6166 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6167 | |
79a45b7d | 6168 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
6169 | val_print_scalar_formatted (value_type (val), |
6170 | value_contents_for_printing (val), | |
6171 | value_embedded_offset (val), | |
6172 | val, | |
6173 | &opts, 0, file); | |
c906108c SS |
6174 | } |
6175 | ||
f0ef6b29 KB |
6176 | /* Replacement for generic do_registers_info. |
6177 | Print regs in pretty columns. */ | |
6178 | ||
6179 | static int | |
e11c53d2 AC |
6180 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6181 | int regnum) | |
f0ef6b29 | 6182 | { |
e11c53d2 AC |
6183 | fprintf_filtered (file, " "); |
6184 | mips_print_fp_register (file, frame, regnum); | |
6185 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6186 | return regnum + 1; |
6187 | } | |
6188 | ||
6189 | ||
025bb325 | 6190 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6191 | |
6192 | static int | |
e11c53d2 | 6193 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6194 | int start_regnum) |
c906108c | 6195 | { |
a4b8ebc8 | 6196 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6197 | /* Do values for GP (int) regs. */ |
47a35522 | 6198 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
6199 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6200 | per row. */ | |
c906108c | 6201 | int col, byte; |
a4b8ebc8 | 6202 | int regnum; |
c906108c | 6203 | |
025bb325 | 6204 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6205 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6206 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6207 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6208 | regnum++) |
c906108c | 6209 | { |
72a155b4 | 6210 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6211 | continue; /* unused register */ |
004159a2 | 6212 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6213 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6214 | /* Large registers are handled separately. */ |
72a155b4 | 6215 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6216 | { |
6217 | if (col > 0) | |
6218 | break; /* End the row before this register. */ | |
6219 | ||
6220 | /* Print this register on a row by itself. */ | |
6221 | mips_print_register (file, frame, regnum); | |
6222 | fprintf_filtered (file, "\n"); | |
6223 | return regnum + 1; | |
6224 | } | |
d05f6826 DJ |
6225 | if (col == 0) |
6226 | fprintf_filtered (file, " "); | |
6d82d43b | 6227 | fprintf_filtered (file, |
72a155b4 UW |
6228 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6229 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6230 | col++; |
6231 | } | |
d05f6826 DJ |
6232 | |
6233 | if (col == 0) | |
6234 | return regnum; | |
6235 | ||
025bb325 | 6236 | /* Print the R0 to R31 names. */ |
72a155b4 | 6237 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6238 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6239 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6240 | else |
6241 | fprintf_filtered (file, "\n "); | |
c906108c | 6242 | |
025bb325 | 6243 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6244 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6245 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6246 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6247 | regnum++) |
c906108c | 6248 | { |
72a155b4 | 6249 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6250 | continue; /* unused register */ |
004159a2 | 6251 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6252 | break; /* End row: reached FP register. */ |
72a155b4 | 6253 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6254 | break; /* End row: large register. */ |
6255 | ||
c906108c | 6256 | /* OK: get the data in raw format. */ |
e11c53d2 | 6257 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 6258 | error (_("can't read register %d (%s)"), |
72a155b4 | 6259 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 6260 | /* pad small registers */ |
4246e332 | 6261 | for (byte = 0; |
72a155b4 UW |
6262 | byte < (mips_abi_regsize (gdbarch) |
6263 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 6264 | printf_filtered (" "); |
025bb325 | 6265 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6266 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6267 | for (byte = |
72a155b4 UW |
6268 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6269 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6270 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6271 | else |
72a155b4 | 6272 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6273 | byte >= 0; byte--) |
47a35522 | 6274 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6275 | fprintf_filtered (file, " "); |
c906108c SS |
6276 | col++; |
6277 | } | |
025bb325 | 6278 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6279 | fprintf_filtered (file, "\n"); |
c906108c SS |
6280 | |
6281 | return regnum; | |
6282 | } | |
6283 | ||
025bb325 | 6284 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6285 | |
bf1f5b4c | 6286 | static void |
e11c53d2 AC |
6287 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6288 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6289 | { |
025bb325 | 6290 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6291 | { |
72a155b4 UW |
6292 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6293 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6294 | error (_("Not a valid register for the current processor type")); |
c906108c | 6295 | |
0cc93a06 | 6296 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6297 | fprintf_filtered (file, "\n"); |
c906108c | 6298 | } |
c5aa993b | 6299 | else |
025bb325 | 6300 | /* Do all (or most) registers. */ |
c906108c | 6301 | { |
72a155b4 UW |
6302 | regnum = gdbarch_num_regs (gdbarch); |
6303 | while (regnum < gdbarch_num_regs (gdbarch) | |
6304 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6305 | { |
004159a2 | 6306 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6307 | { |
025bb325 | 6308 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6309 | regnum = print_fp_register_row (file, frame, regnum); |
6310 | else | |
025bb325 | 6311 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6312 | } |
c906108c | 6313 | else |
e11c53d2 | 6314 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6315 | } |
6316 | } | |
6317 | } | |
6318 | ||
63807e1d | 6319 | static int |
3352ef37 AC |
6320 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6321 | struct frame_info *frame) | |
c906108c | 6322 | { |
e17a4113 | 6323 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 6324 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6325 | struct address_space *aspace; |
6326 | enum mips_isa isa; | |
6327 | ULONGEST insn; | |
6328 | int status; | |
6329 | int size; | |
6330 | ||
6331 | if ((mips_pc_is_mips (pc) | |
6332 | && !mips32_instruction_has_delay_slot (gdbarch, pc)) | |
6333 | || (mips_pc_is_micromips (gdbarch, pc) | |
6334 | && !micromips_instruction_has_delay_slot (gdbarch, pc, 0)) | |
6335 | || (mips_pc_is_mips16 (gdbarch, pc) | |
6336 | && !mips16_instruction_has_delay_slot (gdbarch, pc, 0))) | |
06648491 MK |
6337 | return 0; |
6338 | ||
4cc0665f MR |
6339 | isa = mips_pc_isa (gdbarch, pc); |
6340 | /* _has_delay_slot above will have validated the read. */ | |
6341 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6342 | size = mips_insn_size (isa, insn); | |
6343 | aspace = get_frame_address_space (frame); | |
6344 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; | |
c906108c SS |
6345 | } |
6346 | ||
6d82d43b AC |
6347 | /* To skip prologues, I use this predicate. Returns either PC itself |
6348 | if the code at PC does not look like a function prologue; otherwise | |
6349 | returns an address that (if we're lucky) follows the prologue. If | |
6350 | LENIENT, then we must skip everything which is involved in setting | |
6351 | up the frame (it's OK to skip more, just so long as we don't skip | |
6352 | anything which might clobber the registers which are being saved. | |
6353 | We must skip more in the case where part of the prologue is in the | |
6354 | delay slot of a non-prologue instruction). */ | |
6355 | ||
6356 | static CORE_ADDR | |
6093d2eb | 6357 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6358 | { |
8b622e6a AC |
6359 | CORE_ADDR limit_pc; |
6360 | CORE_ADDR func_addr; | |
6361 | ||
6d82d43b AC |
6362 | /* See if we can determine the end of the prologue via the symbol table. |
6363 | If so, then return either PC, or the PC after the prologue, whichever | |
6364 | is greater. */ | |
8b622e6a AC |
6365 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6366 | { | |
d80b854b UW |
6367 | CORE_ADDR post_prologue_pc |
6368 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
6369 | if (post_prologue_pc != 0) |
6370 | return max (pc, post_prologue_pc); | |
6371 | } | |
6d82d43b AC |
6372 | |
6373 | /* Can't determine prologue from the symbol table, need to examine | |
6374 | instructions. */ | |
6375 | ||
98b4dd94 JB |
6376 | /* Find an upper limit on the function prologue using the debug |
6377 | information. If the debug information could not be used to provide | |
6378 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6379 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6380 | if (limit_pc == 0) |
6381 | limit_pc = pc + 100; /* Magic. */ | |
6382 | ||
4cc0665f | 6383 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6384 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6385 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6386 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6387 | else |
e17a4113 | 6388 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6389 | } |
6390 | ||
97ab0fdd MR |
6391 | /* Check whether the PC is in a function epilogue (32-bit version). |
6392 | This is a helper function for mips_in_function_epilogue_p. */ | |
6393 | static int | |
e17a4113 | 6394 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6395 | { |
6396 | CORE_ADDR func_addr = 0, func_end = 0; | |
6397 | ||
6398 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6399 | { | |
6400 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6401 | CORE_ADDR addr = func_end - 12; | |
6402 | ||
6403 | if (addr < func_addr + 4) | |
6404 | addr = func_addr + 4; | |
6405 | if (pc < addr) | |
6406 | return 0; | |
6407 | ||
6408 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6409 | { | |
6410 | unsigned long high_word; | |
6411 | unsigned long inst; | |
6412 | ||
4cc0665f | 6413 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6414 | high_word = (inst >> 16) & 0xffff; |
6415 | ||
6416 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6417 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6418 | && inst != 0x03e00008 /* jr $ra */ | |
6419 | && inst != 0x00000000) /* nop */ | |
6420 | return 0; | |
6421 | } | |
6422 | ||
6423 | return 1; | |
6424 | } | |
6425 | ||
6426 | return 0; | |
6427 | } | |
6428 | ||
4cc0665f MR |
6429 | /* Check whether the PC is in a function epilogue (microMIPS version). |
6430 | This is a helper function for mips_in_function_epilogue_p. */ | |
6431 | ||
6432 | static int | |
6433 | micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6434 | { | |
6435 | CORE_ADDR func_addr = 0; | |
6436 | CORE_ADDR func_end = 0; | |
6437 | CORE_ADDR addr; | |
6438 | ULONGEST insn; | |
6439 | long offset; | |
6440 | int dreg; | |
6441 | int sreg; | |
6442 | int loc; | |
6443 | ||
6444 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6445 | return 0; | |
6446 | ||
6447 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6448 | addr = func_end - 12; | |
6449 | ||
6450 | if (addr < func_addr + 2) | |
6451 | addr = func_addr + 2; | |
6452 | if (pc < addr) | |
6453 | return 0; | |
6454 | ||
6455 | for (; pc < func_end; pc += loc) | |
6456 | { | |
6457 | loc = 0; | |
6458 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6459 | loc += MIPS_INSN16_SIZE; | |
6460 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6461 | { | |
6462 | /* 48-bit instructions. */ | |
6463 | case 3 * MIPS_INSN16_SIZE: | |
6464 | /* No epilogue instructions in this category. */ | |
6465 | return 0; | |
6466 | ||
6467 | /* 32-bit instructions. */ | |
6468 | case 2 * MIPS_INSN16_SIZE: | |
6469 | insn <<= 16; | |
6470 | insn |= mips_fetch_instruction (gdbarch, | |
6471 | ISA_MICROMIPS, pc + loc, NULL); | |
6472 | loc += MIPS_INSN16_SIZE; | |
6473 | switch (micromips_op (insn >> 16)) | |
6474 | { | |
6475 | case 0xc: /* ADDIU: bits 001100 */ | |
6476 | case 0x17: /* DADDIU: bits 010111 */ | |
6477 | sreg = b0s5_reg (insn >> 16); | |
6478 | dreg = b5s5_reg (insn >> 16); | |
6479 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6480 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6481 | /* (D)ADDIU $sp, imm */ | |
6482 | && offset >= 0) | |
6483 | break; | |
6484 | return 0; | |
6485 | ||
6486 | default: | |
6487 | return 0; | |
6488 | } | |
6489 | break; | |
6490 | ||
6491 | /* 16-bit instructions. */ | |
6492 | case MIPS_INSN16_SIZE: | |
6493 | switch (micromips_op (insn)) | |
6494 | { | |
6495 | case 0x3: /* MOVE: bits 000011 */ | |
6496 | sreg = b0s5_reg (insn); | |
6497 | dreg = b5s5_reg (insn); | |
6498 | if (sreg == 0 && dreg == 0) | |
6499 | /* MOVE $zero, $zero aka NOP */ | |
6500 | break; | |
6501 | return 0; | |
6502 | ||
6503 | case 0x11: /* POOL16C: bits 010001 */ | |
6504 | if (b5s5_op (insn) == 0x18 | |
6505 | /* JRADDIUSP: bits 010011 11000 */ | |
6506 | || (b5s5_op (insn) == 0xd | |
6507 | /* JRC: bits 010011 01101 */ | |
6508 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6509 | /* JRC $ra */ | |
6510 | break; | |
6511 | return 0; | |
6512 | ||
6513 | case 0x13: /* POOL16D: bits 010011 */ | |
6514 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6515 | if ((insn & 0x1) == 0x1 | |
6516 | /* ADDIUSP: bits 010011 1 */ | |
6517 | && offset > 0) | |
6518 | break; | |
6519 | return 0; | |
6520 | ||
6521 | default: | |
6522 | return 0; | |
6523 | } | |
6524 | } | |
6525 | } | |
6526 | ||
6527 | return 1; | |
6528 | } | |
6529 | ||
97ab0fdd MR |
6530 | /* Check whether the PC is in a function epilogue (16-bit version). |
6531 | This is a helper function for mips_in_function_epilogue_p. */ | |
6532 | static int | |
e17a4113 | 6533 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6534 | { |
6535 | CORE_ADDR func_addr = 0, func_end = 0; | |
6536 | ||
6537 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6538 | { | |
6539 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6540 | CORE_ADDR addr = func_end - 12; | |
6541 | ||
6542 | if (addr < func_addr + 4) | |
6543 | addr = func_addr + 4; | |
6544 | if (pc < addr) | |
6545 | return 0; | |
6546 | ||
6547 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6548 | { | |
6549 | unsigned short inst; | |
6550 | ||
4cc0665f | 6551 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6552 | |
6553 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6554 | continue; | |
6555 | ||
6556 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6557 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6558 | && inst != 0xe820 /* jr $ra */ | |
6559 | && inst != 0xe8a0 /* jrc $ra */ | |
6560 | && inst != 0x6500) /* nop */ | |
6561 | return 0; | |
6562 | } | |
6563 | ||
6564 | return 1; | |
6565 | } | |
6566 | ||
6567 | return 0; | |
6568 | } | |
6569 | ||
6570 | /* The epilogue is defined here as the area at the end of a function, | |
6571 | after an instruction which destroys the function's stack frame. */ | |
6572 | static int | |
6573 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6574 | { | |
4cc0665f | 6575 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6576 | return mips16_in_function_epilogue_p (gdbarch, pc); |
4cc0665f MR |
6577 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6578 | return micromips_in_function_epilogue_p (gdbarch, pc); | |
97ab0fdd | 6579 | else |
e17a4113 | 6580 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
6581 | } |
6582 | ||
025bb325 | 6583 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6584 | used for all MIPS-specific commands. */ |
6585 | ||
a5ea2558 | 6586 | static void |
acdb74a0 | 6587 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
6588 | { |
6589 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6590 | } | |
6591 | ||
a5ea2558 | 6592 | static void |
acdb74a0 | 6593 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 6594 | { |
6d82d43b AC |
6595 | printf_unfiltered |
6596 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6597 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6598 | } | |
6599 | ||
c906108c SS |
6600 | /* Commands to show/set the MIPS FPU type. */ |
6601 | ||
c906108c | 6602 | static void |
acdb74a0 | 6603 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 6604 | { |
c906108c | 6605 | char *fpu; |
6ca0852e | 6606 | |
1cf3db46 | 6607 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
6608 | { |
6609 | printf_unfiltered | |
6610 | ("The MIPS floating-point coprocessor is unknown " | |
6611 | "because the current architecture is not MIPS.\n"); | |
6612 | return; | |
6613 | } | |
6614 | ||
1cf3db46 | 6615 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
6616 | { |
6617 | case MIPS_FPU_SINGLE: | |
6618 | fpu = "single-precision"; | |
6619 | break; | |
6620 | case MIPS_FPU_DOUBLE: | |
6621 | fpu = "double-precision"; | |
6622 | break; | |
6623 | case MIPS_FPU_NONE: | |
6624 | fpu = "absent (none)"; | |
6625 | break; | |
93d56215 | 6626 | default: |
e2e0b3e5 | 6627 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6628 | } |
6629 | if (mips_fpu_type_auto) | |
025bb325 MS |
6630 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6631 | "is set automatically (currently %s)\n", | |
6632 | fpu); | |
c906108c | 6633 | else |
6d82d43b AC |
6634 | printf_unfiltered |
6635 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6636 | } |
6637 | ||
6638 | ||
c906108c | 6639 | static void |
acdb74a0 | 6640 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 6641 | { |
025bb325 MS |
6642 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6643 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6644 | show_mipsfpu_command (args, from_tty); |
6645 | } | |
6646 | ||
c906108c | 6647 | static void |
acdb74a0 | 6648 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 6649 | { |
8d5838b5 AC |
6650 | struct gdbarch_info info; |
6651 | gdbarch_info_init (&info); | |
c906108c SS |
6652 | mips_fpu_type = MIPS_FPU_SINGLE; |
6653 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6654 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6655 | instead of relying on globals. Doing that would let generic code | |
6656 | handle the search for this specific architecture. */ | |
6657 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6658 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6659 | } |
6660 | ||
c906108c | 6661 | static void |
acdb74a0 | 6662 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 6663 | { |
8d5838b5 AC |
6664 | struct gdbarch_info info; |
6665 | gdbarch_info_init (&info); | |
c906108c SS |
6666 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6667 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6668 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6669 | instead of relying on globals. Doing that would let generic code | |
6670 | handle the search for this specific architecture. */ | |
6671 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6672 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6673 | } |
6674 | ||
c906108c | 6675 | static void |
acdb74a0 | 6676 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 6677 | { |
8d5838b5 AC |
6678 | struct gdbarch_info info; |
6679 | gdbarch_info_init (&info); | |
c906108c SS |
6680 | mips_fpu_type = MIPS_FPU_NONE; |
6681 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6682 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6683 | instead of relying on globals. Doing that would let generic code | |
6684 | handle the search for this specific architecture. */ | |
6685 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6686 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6687 | } |
6688 | ||
c906108c | 6689 | static void |
acdb74a0 | 6690 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
6691 | { |
6692 | mips_fpu_type_auto = 1; | |
6693 | } | |
6694 | ||
c906108c | 6695 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
6696 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
6697 | the relevant processor still exists (it dates back to '94) and | |
6698 | secondly this is not the way to do this. The processor type should | |
6699 | be set by forcing an architecture change. */ | |
c906108c | 6700 | |
691c0433 AC |
6701 | void |
6702 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 6703 | { |
bb486190 UW |
6704 | struct regcache *regcache = get_current_regcache (); |
6705 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
6706 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 6707 | ULONGEST prid; |
c906108c | 6708 | |
bb486190 | 6709 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 6710 | if ((prid & ~0xf) == 0x700) |
691c0433 | 6711 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
6712 | } |
6713 | ||
6714 | /* Just like reinit_frame_cache, but with the right arguments to be | |
6715 | callable as an sfunc. */ | |
6716 | ||
6717 | static void | |
acdb74a0 AC |
6718 | reinit_frame_cache_sfunc (char *args, int from_tty, |
6719 | struct cmd_list_element *c) | |
c906108c SS |
6720 | { |
6721 | reinit_frame_cache (); | |
6722 | } | |
6723 | ||
a89aa300 AC |
6724 | static int |
6725 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6726 | { |
4cc0665f MR |
6727 | struct gdbarch *gdbarch = info->application_data; |
6728 | ||
d31431ed AC |
6729 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6730 | disassembler needs to be able to locally determine the ISA, and | |
6731 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6732 | work. */ | |
4cc0665f | 6733 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6734 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6735 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6736 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6737 | |
6738 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6739 | memaddr &= (info->mach == bfd_mach_mips16 |
6740 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6741 | |
e5ab0dce | 6742 | /* Set the disassembler options. */ |
9dae60cc | 6743 | if (!info->disassembler_options) |
e5ab0dce AC |
6744 | /* This string is not recognized explicitly by the disassembler, |
6745 | but it tells the disassembler to not try to guess the ABI from | |
6746 | the bfd elf headers, such that, if the user overrides the ABI | |
6747 | of a program linked as NewABI, the disassembly will follow the | |
6748 | register naming conventions specified by the user. */ | |
6749 | info->disassembler_options = "gpr-names=32"; | |
6750 | ||
c906108c | 6751 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 6752 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
6753 | return print_insn_big_mips (memaddr, info); |
6754 | else | |
6755 | return print_insn_little_mips (memaddr, info); | |
6756 | } | |
6757 | ||
9dae60cc UW |
6758 | static int |
6759 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
6760 | { | |
6761 | /* Set up the disassembler info, so that we get the right | |
6762 | register names from libopcodes. */ | |
6763 | info->disassembler_options = "gpr-names=n32"; | |
6764 | info->flavour = bfd_target_elf_flavour; | |
6765 | ||
6766 | return gdb_print_insn_mips (memaddr, info); | |
6767 | } | |
6768 | ||
6769 | static int | |
6770 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
6771 | { | |
6772 | /* Set up the disassembler info, so that we get the right | |
6773 | register names from libopcodes. */ | |
6774 | info->disassembler_options = "gpr-names=64"; | |
6775 | info->flavour = bfd_target_elf_flavour; | |
6776 | ||
6777 | return gdb_print_insn_mips (memaddr, info); | |
6778 | } | |
6779 | ||
025bb325 MS |
6780 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
6781 | program counter value to determine whether a 16- or 32-bit breakpoint | |
6782 | should be used. It returns a pointer to a string of bytes that encode a | |
6783 | breakpoint instruction, stores the length of the string to *lenptr, and | |
6784 | adjusts pc (if necessary) to point to the actual memory location where | |
6785 | the breakpoint should be inserted. */ | |
c906108c | 6786 | |
47a35522 | 6787 | static const gdb_byte * |
025bb325 MS |
6788 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
6789 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 6790 | { |
4cc0665f MR |
6791 | CORE_ADDR pc = *pcptr; |
6792 | ||
67d57894 | 6793 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 6794 | { |
4cc0665f | 6795 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6796 | { |
47a35522 | 6797 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
4cc0665f | 6798 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6799 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
6800 | return mips16_big_breakpoint; |
6801 | } | |
4cc0665f MR |
6802 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6803 | { | |
6804 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
6805 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
6806 | ULONGEST insn; | |
6807 | int status; | |
6808 | int size; | |
6809 | ||
6810 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6811 | size = status ? 2 | |
6812 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6813 | *pcptr = unmake_compact_addr (pc); | |
6814 | *lenptr = size; | |
6815 | return (size == 2) ? micromips16_big_breakpoint | |
6816 | : micromips32_big_breakpoint; | |
6817 | } | |
c906108c SS |
6818 | else |
6819 | { | |
aaab4dba AC |
6820 | /* The IDT board uses an unusual breakpoint value, and |
6821 | sometimes gets confused when it sees the usual MIPS | |
6822 | breakpoint instruction. */ | |
47a35522 MK |
6823 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
6824 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
6825 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 6826 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 6827 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 6828 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 6829 | |
c5aa993b | 6830 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
6831 | |
6832 | if (strcmp (target_shortname, "mips") == 0) | |
6833 | return idt_big_breakpoint; | |
6834 | else if (strcmp (target_shortname, "ddb") == 0 | |
6835 | || strcmp (target_shortname, "pmon") == 0 | |
6836 | || strcmp (target_shortname, "lsi") == 0) | |
6837 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
6838 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
6839 | return irix_big_breakpoint; | |
c906108c SS |
6840 | else |
6841 | return big_breakpoint; | |
6842 | } | |
6843 | } | |
6844 | else | |
6845 | { | |
4cc0665f | 6846 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6847 | { |
47a35522 | 6848 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
4cc0665f | 6849 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6850 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
6851 | return mips16_little_breakpoint; |
6852 | } | |
4cc0665f MR |
6853 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6854 | { | |
6855 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
6856 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
6857 | ULONGEST insn; | |
6858 | int status; | |
6859 | int size; | |
6860 | ||
6861 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6862 | size = status ? 2 | |
6863 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6864 | *pcptr = unmake_compact_addr (pc); | |
6865 | *lenptr = size; | |
6866 | return (size == 2) ? micromips16_little_breakpoint | |
6867 | : micromips32_little_breakpoint; | |
6868 | } | |
c906108c SS |
6869 | else |
6870 | { | |
47a35522 MK |
6871 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
6872 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
6873 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 6874 | |
c5aa993b | 6875 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
6876 | |
6877 | if (strcmp (target_shortname, "mips") == 0) | |
6878 | return idt_little_breakpoint; | |
6879 | else if (strcmp (target_shortname, "ddb") == 0 | |
6880 | || strcmp (target_shortname, "pmon") == 0 | |
6881 | || strcmp (target_shortname, "lsi") == 0) | |
6882 | return pmon_little_breakpoint; | |
6883 | else | |
6884 | return little_breakpoint; | |
6885 | } | |
6886 | } | |
6887 | } | |
6888 | ||
4cc0665f MR |
6889 | /* Determine the remote breakpoint kind suitable for the PC. The following |
6890 | kinds are used: | |
6891 | ||
6892 | * 2 -- 16-bit MIPS16 mode breakpoint, | |
6893 | ||
6894 | * 3 -- 16-bit microMIPS mode breakpoint, | |
6895 | ||
6896 | * 4 -- 32-bit standard MIPS mode breakpoint, | |
6897 | ||
6898 | * 5 -- 32-bit microMIPS mode breakpoint. */ | |
6899 | ||
6900 | static void | |
6901 | mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
6902 | int *kindptr) | |
6903 | { | |
6904 | CORE_ADDR pc = *pcptr; | |
6905 | ||
6906 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
6907 | { | |
6908 | *pcptr = unmake_compact_addr (pc); | |
6909 | *kindptr = 2; | |
6910 | } | |
6911 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
6912 | { | |
6913 | ULONGEST insn; | |
6914 | int status; | |
6915 | int size; | |
6916 | ||
6917 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6918 | size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6919 | *pcptr = unmake_compact_addr (pc); | |
6920 | *kindptr = size | 1; | |
6921 | } | |
6922 | else | |
6923 | *kindptr = 4; | |
6924 | } | |
6925 | ||
c8cef75f MR |
6926 | /* Return non-zero if the ADDR instruction has a branch delay slot |
6927 | (i.e. it is a jump or branch instruction). This function is based | |
6928 | on mips32_next_pc. */ | |
6929 | ||
6930 | static int | |
6931 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
6932 | { | |
c8cef75f MR |
6933 | unsigned long inst; |
6934 | int status; | |
6935 | int op; | |
a385295e MR |
6936 | int rs; |
6937 | int rt; | |
c8cef75f | 6938 | |
4cc0665f | 6939 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
c8cef75f MR |
6940 | if (status) |
6941 | return 0; | |
6942 | ||
c8cef75f MR |
6943 | op = itype_op (inst); |
6944 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
6945 | { |
6946 | rs = itype_rs (inst); | |
6947 | rt = itype_rt (inst); | |
6948 | return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
6949 | || op == 29 /* JALX: bits 011101 */ | |
6950 | || (op == 17 | |
6951 | && (rs == 8 | |
c8cef75f | 6952 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
6953 | || (rs == 9 && (rt & 0x2) == 0) |
6954 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
6955 | || (rs == 10 && (rt & 0x2) == 0)))); | |
6956 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
6957 | } | |
c8cef75f MR |
6958 | else |
6959 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
6960 | { | |
6961 | case 0: /* SPECIAL */ | |
6962 | op = rtype_funct (inst); | |
6963 | return (op == 8 /* JR */ | |
6964 | || op == 9); /* JALR */ | |
6965 | break; /* end SPECIAL */ | |
6966 | case 1: /* REGIMM */ | |
a385295e MR |
6967 | rs = itype_rs (inst); |
6968 | rt = itype_rt (inst); /* branch condition */ | |
6969 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
6970 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
6971 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
6972 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
6973 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
6974 | break; /* end REGIMM */ |
6975 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
6976 | return 1; | |
6977 | break; | |
6978 | } | |
6979 | } | |
6980 | ||
6981 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
6982 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
6983 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
6984 | ||
4cc0665f MR |
6985 | static int |
6986 | micromips_instruction_has_delay_slot (struct gdbarch *gdbarch, | |
6987 | CORE_ADDR addr, int mustbe32) | |
6988 | { | |
6989 | ULONGEST insn; | |
6990 | int status; | |
6991 | ||
6992 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
6993 | if (status) | |
6994 | return 0; | |
6995 | ||
6996 | if (!mustbe32) /* 16-bit instructions. */ | |
6997 | return (micromips_op (insn) == 0x11 | |
6998 | /* POOL16C: bits 010001 */ | |
6999 | && (b5s5_op (insn) == 0xc | |
7000 | /* JR16: bits 010001 01100 */ | |
7001 | || (b5s5_op (insn) & 0x1e) == 0xe)) | |
7002 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7003 | || (micromips_op (insn) & 0x37) == 0x23 | |
7004 | /* BEQZ16, BNEZ16: bits 10x011 */ | |
7005 | || micromips_op (insn) == 0x33; | |
7006 | /* B16: bits 110011 */ | |
7007 | ||
7008 | /* 32-bit instructions. */ | |
7009 | if (micromips_op (insn) == 0x0) | |
7010 | /* POOL32A: bits 000000 */ | |
7011 | { | |
7012 | insn <<= 16; | |
7013 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7014 | if (status) | |
7015 | return 0; | |
7016 | return b0s6_op (insn) == 0x3c | |
7017 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7018 | && (b6s10_ext (insn) & 0x2bf) == 0x3c; | |
7019 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7020 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7021 | } | |
7022 | ||
7023 | return (micromips_op (insn) == 0x10 | |
7024 | /* POOL32I: bits 010000 */ | |
7025 | && ((b5s5_op (insn) & 0x1c) == 0x0 | |
7026 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
7027 | || (b5s5_op (insn) & 0x1d) == 0x4 | |
7028 | /* BLEZ, BGTZ: bits 010000 001x0 */ | |
7029 | || (b5s5_op (insn) & 0x1d) == 0x11 | |
7030 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
7031 | || ((b5s5_op (insn) & 0x1e) == 0x14 | |
7032 | && (insn & 0x3) == 0x0) | |
7033 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
7034 | || (b5s5_op (insn) & 0x1e) == 0x1a | |
7035 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
7036 | || ((b5s5_op (insn) & 0x1e) == 0x1c | |
7037 | && (insn & 0x3) == 0x0) | |
7038 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
7039 | || ((b5s5_op (insn) & 0x1c) == 0x1c | |
7040 | && (insn & 0x3) == 0x1))) | |
7041 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
7042 | || (micromips_op (insn) & 0x1f) == 0x1d | |
7043 | /* JALS, JAL: bits x11101 */ | |
7044 | || (micromips_op (insn) & 0x37) == 0x25 | |
7045 | /* BEQ, BNE: bits 10x101 */ | |
7046 | || micromips_op (insn) == 0x35 | |
7047 | /* J: bits 110101 */ | |
7048 | || micromips_op (insn) == 0x3c; | |
7049 | /* JALX: bits 111100 */ | |
7050 | } | |
7051 | ||
c8cef75f MR |
7052 | static int |
7053 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
7054 | int mustbe32) | |
7055 | { | |
c8cef75f MR |
7056 | unsigned short inst; |
7057 | int status; | |
7058 | ||
4cc0665f | 7059 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); |
c8cef75f MR |
7060 | if (status) |
7061 | return 0; | |
7062 | ||
c8cef75f MR |
7063 | if (!mustbe32) |
7064 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
7065 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
7066 | } | |
7067 | ||
7068 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
7069 | This assumes KSSEG exists. */ | |
7070 | ||
7071 | static CORE_ADDR | |
7072 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7073 | { | |
7074 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7075 | int segsize; | |
7076 | ||
7077 | if (sizeof (CORE_ADDR) == 8) | |
7078 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7079 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7080 | though in that case this is dead code). */ | |
7081 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7082 | { | |
7083 | case 3: | |
7084 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7085 | segsize = 29; /* 32-bit compatibility segment */ | |
7086 | else | |
7087 | segsize = 62; /* xkseg */ | |
7088 | break; | |
7089 | case 2: /* xkphys */ | |
7090 | segsize = 59; | |
7091 | break; | |
7092 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7093 | segsize = 62; | |
7094 | break; | |
7095 | } | |
7096 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7097 | segsize = 29; | |
7098 | else | |
7099 | segsize = 31; /* user segment */ | |
7100 | mask <<= segsize; | |
7101 | return bpaddr & mask; | |
7102 | } | |
7103 | ||
7104 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7105 | it backwards if necessary. Return the address of the new location. */ | |
7106 | ||
7107 | static CORE_ADDR | |
7108 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7109 | { | |
22e048c9 | 7110 | CORE_ADDR prev_addr; |
c8cef75f MR |
7111 | CORE_ADDR boundary; |
7112 | CORE_ADDR func_addr; | |
7113 | ||
7114 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7115 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7116 | the instruction in the branch delay slot, the PC will point to | |
7117 | the branch instruction. Since the PC doesn't match any known | |
7118 | breakpoints, GDB reports a trap exception. | |
7119 | ||
7120 | There are two possible fixes for this problem. | |
7121 | ||
7122 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7123 | Cause register (which indicates the last exception occurred in a | |
7124 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7125 | the instruction in the branch delay slot. | |
7126 | ||
7127 | 2) When the user sets the breakpoint, don't allow him to set the | |
7128 | breakpoint on the instruction in the branch delay slot. Instead | |
7129 | move the breakpoint to the branch instruction (which will have | |
7130 | the same result). | |
7131 | ||
7132 | The problem with the first solution is that if the user then | |
7133 | single-steps the processor, the branch instruction will get | |
7134 | skipped (since GDB thinks the PC is on the instruction in the | |
7135 | branch delay slot). | |
7136 | ||
7137 | So, we'll use the second solution. To do this we need to know if | |
7138 | the instruction we're trying to set the breakpoint on is in the | |
7139 | branch delay slot. */ | |
7140 | ||
7141 | boundary = mips_segment_boundary (bpaddr); | |
7142 | ||
7143 | /* Make sure we don't scan back before the beginning of the current | |
7144 | function, since we may fetch constant data or insns that look like | |
7145 | a jump. Of course we might do that anyway if the compiler has | |
7146 | moved constants inline. :-( */ | |
7147 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7148 | && func_addr > boundary && func_addr <= bpaddr) | |
7149 | boundary = func_addr; | |
7150 | ||
4cc0665f | 7151 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7152 | { |
7153 | if (bpaddr == boundary) | |
7154 | return bpaddr; | |
7155 | ||
7156 | /* If the previous instruction has a branch delay slot, we have | |
7157 | to move the breakpoint to the branch instruction. */ | |
7158 | prev_addr = bpaddr - 4; | |
7159 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
7160 | bpaddr = prev_addr; | |
7161 | } | |
7162 | else | |
7163 | { | |
4cc0665f | 7164 | int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7165 | CORE_ADDR addr, jmpaddr; |
7166 | int i; | |
7167 | ||
4cc0665f | 7168 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7169 | |
7170 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7171 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7172 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7173 | The microMIPS ASE has a whole range of jumps and branches |
7174 | with delay slots, some of which take 4 bytes and some take | |
7175 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7176 | FIXME: We have to assume that bpaddr is not the second half |
7177 | of an extended instruction. */ | |
4cc0665f MR |
7178 | instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7179 | ? micromips_instruction_has_delay_slot | |
7180 | : mips16_instruction_has_delay_slot); | |
c8cef75f MR |
7181 | |
7182 | jmpaddr = 0; | |
7183 | addr = bpaddr; | |
7184 | for (i = 1; i < 4; i++) | |
7185 | { | |
4cc0665f | 7186 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7187 | break; |
4cc0665f MR |
7188 | addr -= MIPS_INSN16_SIZE; |
7189 | if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0)) | |
c8cef75f MR |
7190 | /* Looks like a JR/JALR at [target-1], but it could be |
7191 | the second word of a previous JAL/JALX, so record it | |
7192 | and check back one more. */ | |
7193 | jmpaddr = addr; | |
4cc0665f | 7194 | else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7195 | { |
7196 | if (i == 2) | |
7197 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7198 | be the second word of a previous JAL/JALX, record it, | |
7199 | and check back one more. */ | |
7200 | jmpaddr = addr; | |
7201 | else | |
7202 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7203 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7204 | ||
7205 | >-3: JAL | |
7206 | -2: JAL-ext (can't be JAL/JALX) | |
7207 | -1: bdslot (can't be JR/JALR) | |
7208 | 0: target insn | |
7209 | ||
7210 | Of course it could be another JAL-ext which looks | |
7211 | like a JAL, but in that case we'd have broken out | |
7212 | of this loop at [target-2]: | |
7213 | ||
7214 | -4: JAL | |
7215 | >-3: JAL-ext | |
7216 | -2: bdslot (can't be jmp) | |
7217 | -1: JR/JALR | |
7218 | 0: target insn */ | |
7219 | jmpaddr = 0; | |
7220 | } | |
7221 | else | |
7222 | { | |
7223 | /* Not a jump instruction: if we're at [target-1] this | |
7224 | could be the second word of a JAL/JALX, so continue; | |
7225 | otherwise we're done. */ | |
7226 | if (i > 1) | |
7227 | break; | |
7228 | } | |
7229 | } | |
7230 | ||
7231 | if (jmpaddr) | |
7232 | bpaddr = jmpaddr; | |
7233 | } | |
7234 | ||
7235 | return bpaddr; | |
7236 | } | |
7237 | ||
14132e89 MR |
7238 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7239 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7240 | ||
7241 | static int | |
7242 | mips_is_stub_suffix (const char *suffix, int zero) | |
7243 | { | |
7244 | switch (suffix[0]) | |
7245 | { | |
7246 | case '0': | |
7247 | return zero && suffix[1] == '\0'; | |
7248 | case '1': | |
7249 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7250 | case '2': | |
7251 | case '5': | |
7252 | case '6': | |
7253 | case '9': | |
7254 | return suffix[1] == '\0'; | |
7255 | default: | |
7256 | return 0; | |
7257 | } | |
7258 | } | |
7259 | ||
7260 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7261 | call stubs, one of sf, df, sc, or dc. */ | |
7262 | ||
7263 | static int | |
7264 | mips_is_stub_mode (const char *mode) | |
7265 | { | |
7266 | return ((mode[0] == 's' || mode[0] == 'd') | |
7267 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7268 | } | |
7269 | ||
7270 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7271 | bar might have a name like __fn_stub_bar, and might look like this: | |
7272 | ||
7273 | mfc1 $4, $f13 | |
7274 | mfc1 $5, $f12 | |
7275 | mfc1 $6, $f15 | |
7276 | mfc1 $7, $f14 | |
7277 | ||
7278 | followed by (or interspersed with): | |
7279 | ||
7280 | j bar | |
7281 | ||
7282 | or: | |
7283 | ||
7284 | lui $25, %hi(bar) | |
7285 | addiu $25, $25, %lo(bar) | |
7286 | jr $25 | |
7287 | ||
7288 | ($1 may be used in old code; for robustness we accept any register) | |
7289 | or, in PIC code: | |
7290 | ||
7291 | lui $28, %hi(_gp_disp) | |
7292 | addiu $28, $28, %lo(_gp_disp) | |
7293 | addu $28, $28, $25 | |
7294 | lw $25, %got(bar) | |
7295 | addiu $25, $25, %lo(bar) | |
7296 | jr $25 | |
7297 | ||
7298 | In the case of a __call_stub_bar stub, the sequence to set up | |
7299 | arguments might look like this: | |
7300 | ||
7301 | mtc1 $4, $f13 | |
7302 | mtc1 $5, $f12 | |
7303 | mtc1 $6, $f15 | |
7304 | mtc1 $7, $f14 | |
7305 | ||
7306 | followed by (or interspersed with) one of the jump sequences above. | |
7307 | ||
7308 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7309 | of J or JR, respectively, followed by: | |
7310 | ||
7311 | mfc1 $2, $f0 | |
7312 | mfc1 $3, $f1 | |
7313 | jr $18 | |
7314 | ||
7315 | We are at the beginning of the stub here, and scan down and extract | |
7316 | the target address from the jump immediate instruction or, if a jump | |
7317 | register instruction is used, from the register referred. Return | |
7318 | the value of PC calculated or 0 if inconclusive. | |
7319 | ||
7320 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7321 | ||
7322 | static CORE_ADDR | |
7323 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7324 | { | |
7325 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7326 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7327 | int addrreg = MIPS_ZERO_REGNUM; | |
7328 | CORE_ADDR start_pc = pc; | |
7329 | CORE_ADDR target_pc = 0; | |
7330 | CORE_ADDR addr = 0; | |
7331 | CORE_ADDR gp = 0; | |
7332 | int status = 0; | |
7333 | int i; | |
7334 | ||
7335 | for (i = 0; | |
7336 | status == 0 && target_pc == 0 && i < 20; | |
7337 | i++, pc += MIPS_INSN32_SIZE) | |
7338 | { | |
4cc0665f | 7339 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7340 | CORE_ADDR imm; |
7341 | int rt; | |
7342 | int rs; | |
7343 | int rd; | |
7344 | ||
7345 | switch (itype_op (inst)) | |
7346 | { | |
7347 | case 0: /* SPECIAL */ | |
7348 | switch (rtype_funct (inst)) | |
7349 | { | |
7350 | case 8: /* JR */ | |
7351 | case 9: /* JALR */ | |
7352 | rs = rtype_rs (inst); | |
7353 | if (rs == MIPS_GP_REGNUM) | |
7354 | target_pc = gp; /* Hmm... */ | |
7355 | else if (rs == addrreg) | |
7356 | target_pc = addr; | |
7357 | break; | |
7358 | ||
7359 | case 0x21: /* ADDU */ | |
7360 | rt = rtype_rt (inst); | |
7361 | rs = rtype_rs (inst); | |
7362 | rd = rtype_rd (inst); | |
7363 | if (rd == MIPS_GP_REGNUM | |
7364 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7365 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7366 | gp += start_pc; | |
7367 | break; | |
7368 | } | |
7369 | break; | |
7370 | ||
7371 | case 2: /* J */ | |
7372 | case 3: /* JAL */ | |
7373 | target_pc = jtype_target (inst) << 2; | |
7374 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7375 | break; | |
7376 | ||
7377 | case 9: /* ADDIU */ | |
7378 | rt = itype_rt (inst); | |
7379 | rs = itype_rs (inst); | |
7380 | if (rt == rs) | |
7381 | { | |
7382 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7383 | if (rt == MIPS_GP_REGNUM) | |
7384 | gp += imm; | |
7385 | else if (rt == addrreg) | |
7386 | addr += imm; | |
7387 | } | |
7388 | break; | |
7389 | ||
7390 | case 0xf: /* LUI */ | |
7391 | rt = itype_rt (inst); | |
7392 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7393 | if (rt == MIPS_GP_REGNUM) | |
7394 | gp = imm; | |
7395 | else if (rt != MIPS_ZERO_REGNUM) | |
7396 | { | |
7397 | addrreg = rt; | |
7398 | addr = imm; | |
7399 | } | |
7400 | break; | |
7401 | ||
7402 | case 0x23: /* LW */ | |
7403 | rt = itype_rt (inst); | |
7404 | rs = itype_rs (inst); | |
7405 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7406 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7407 | { | |
7408 | gdb_byte buf[4]; | |
7409 | ||
7410 | memset (buf, 0, sizeof (buf)); | |
7411 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7412 | addrreg = rt; | |
7413 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7414 | } | |
7415 | break; | |
7416 | } | |
7417 | } | |
7418 | ||
7419 | return target_pc; | |
7420 | } | |
7421 | ||
7422 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7423 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7424 | cases which must be handled: |
7425 | ||
14132e89 MR |
7426 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7427 | and the target PC is in $31 ($ra). | |
c906108c | 7428 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7429 | and the target PC is in $2. |
7430 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7431 | i.e. before the JALR instruction, this is effectively a call stub | |
7432 | and the target PC is in $2. Otherwise this is effectively | |
7433 | a return stub and the target PC is in $18. | |
7434 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7435 | JAL or JALR instruction, this is effectively a call stub and the | |
7436 | target PC is buried in the instruction stream. Otherwise this | |
7437 | is effectively a return stub and the target PC is in $18. | |
7438 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7439 | stub and the target PC is buried in the instruction stream. | |
7440 | ||
7441 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7442 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7443 | gory details. */ |
c906108c | 7444 | |
757a7cc6 | 7445 | static CORE_ADDR |
db5f024e | 7446 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7447 | { |
e17a4113 | 7448 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7449 | CORE_ADDR start_addr; |
14132e89 MR |
7450 | const char *name; |
7451 | size_t prefixlen; | |
c906108c SS |
7452 | |
7453 | /* Find the starting address and name of the function containing the PC. */ | |
7454 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7455 | return 0; | |
7456 | ||
14132e89 MR |
7457 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7458 | and the target PC is in $31 ($ra). */ | |
7459 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7460 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7461 | && mips_is_stub_mode (name + prefixlen) | |
7462 | && name[prefixlen + 2] == '\0') | |
7463 | return get_frame_register_signed | |
7464 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7465 | ||
7466 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7467 | call/return stubs. */ | |
7468 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7469 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7470 | { |
7471 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7472 | and the target PC is in $2. */ | |
14132e89 MR |
7473 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7474 | return get_frame_register_signed | |
7475 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7476 | |
14132e89 MR |
7477 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7478 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7479 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7480 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7481 | else if (mips_is_stub_mode (name + prefixlen) |
7482 | && name[prefixlen + 2] == '_' | |
7483 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7484 | { |
7485 | if (pc == start_addr) | |
14132e89 MR |
7486 | /* This is the 'call' part of a call stub. The return |
7487 | address is in $2. */ | |
7488 | return get_frame_register_signed | |
7489 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7490 | else |
7491 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7492 | address is in $18. */ |
7493 | return get_frame_register_signed | |
7494 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7495 | } |
14132e89 MR |
7496 | else |
7497 | return 0; /* Not a stub. */ | |
7498 | } | |
7499 | ||
7500 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7501 | compiler-generated call or call/return stubs. */ | |
7502 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 | |
7503 | || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
7504 | { | |
7505 | if (pc == start_addr) | |
7506 | /* This is the 'call' part of a call stub. Call this helper | |
7507 | to scan through this code for interesting instructions | |
7508 | and determine the final PC. */ | |
7509 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7510 | else | |
7511 | /* This is the 'return' part of a call stub. The return address | |
7512 | is in $18. */ | |
7513 | return get_frame_register_signed | |
7514 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7515 | } |
14132e89 MR |
7516 | |
7517 | return 0; /* Not a stub. */ | |
7518 | } | |
7519 | ||
7520 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7521 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7522 | ||
7523 | static int | |
7524 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7525 | { | |
7526 | CORE_ADDR start_addr; | |
7527 | size_t prefixlen; | |
7528 | ||
7529 | /* Find the starting address of the function containing the PC. */ | |
7530 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7531 | return 0; | |
7532 | ||
7533 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7534 | the start, i.e. after the JALR instruction, this is effectively | |
7535 | a return stub. */ | |
7536 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7537 | if (pc != start_addr | |
7538 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7539 | && mips_is_stub_mode (name + prefixlen) | |
7540 | && name[prefixlen + 2] == '_' | |
7541 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7542 | return 1; | |
7543 | ||
7544 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7545 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7546 | prefixlen = strlen (mips_str_call_fp_stub); | |
7547 | if (pc != start_addr | |
7548 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7549 | return 1; | |
7550 | ||
7551 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7552 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7553 | or the call stub path will trigger in handle_inferior_event causing | |
7554 | it to go astray. */ | |
7555 | prefixlen = strlen (mips_str_pic); | |
7556 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7557 | name += prefixlen; | |
7558 | ||
7559 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7560 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7561 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7562 | && mips_is_stub_mode (name + prefixlen) | |
7563 | && name[prefixlen + 2] == '\0') | |
7564 | return 1; | |
7565 | ||
7566 | return 0; /* Not a stub. */ | |
c906108c SS |
7567 | } |
7568 | ||
db5f024e DJ |
7569 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7570 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7571 | so that $t9 has the correct value at function entry. */ | |
7572 | ||
7573 | static CORE_ADDR | |
7574 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7575 | { | |
e17a4113 UW |
7576 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7577 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
7578 | struct minimal_symbol *msym; |
7579 | int i; | |
7580 | gdb_byte stub_code[16]; | |
7581 | int32_t stub_words[4]; | |
7582 | ||
7583 | /* The stub for foo is named ".pic.foo", and is either two | |
7584 | instructions inserted before foo or a three instruction sequence | |
7585 | which jumps to foo. */ | |
7586 | msym = lookup_minimal_symbol_by_pc (pc); | |
7587 | if (msym == NULL | |
7588 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
7589 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
7590 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
7591 | return 0; | |
7592 | ||
7593 | /* A two-instruction header. */ | |
7594 | if (MSYMBOL_SIZE (msym) == 8) | |
7595 | return pc + 8; | |
7596 | ||
7597 | /* A three-instruction (plus delay slot) trampoline. */ | |
7598 | if (MSYMBOL_SIZE (msym) == 16) | |
7599 | { | |
7600 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7601 | return 0; | |
7602 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7603 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7604 | 4, byte_order); | |
db5f024e DJ |
7605 | |
7606 | /* A stub contains these instructions: | |
7607 | lui t9, %hi(target) | |
7608 | j target | |
7609 | addiu t9, t9, %lo(target) | |
7610 | nop | |
7611 | ||
7612 | This works even for N64, since stubs are only generated with | |
7613 | -msym32. */ | |
7614 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7615 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7616 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7617 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7618 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7619 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7620 | } |
7621 | ||
7622 | /* Not a recognized stub. */ | |
7623 | return 0; | |
7624 | } | |
7625 | ||
7626 | static CORE_ADDR | |
7627 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7628 | { | |
14132e89 | 7629 | CORE_ADDR requested_pc = pc; |
db5f024e | 7630 | CORE_ADDR target_pc; |
14132e89 MR |
7631 | CORE_ADDR new_pc; |
7632 | ||
7633 | do | |
7634 | { | |
7635 | target_pc = pc; | |
db5f024e | 7636 | |
14132e89 MR |
7637 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7638 | if (new_pc) | |
7639 | { | |
7640 | pc = new_pc; | |
4cc0665f MR |
7641 | if (is_compact_addr (pc)) |
7642 | pc = unmake_compact_addr (pc); | |
14132e89 | 7643 | } |
db5f024e | 7644 | |
14132e89 MR |
7645 | new_pc = find_solib_trampoline_target (frame, pc); |
7646 | if (new_pc) | |
7647 | { | |
7648 | pc = new_pc; | |
4cc0665f MR |
7649 | if (is_compact_addr (pc)) |
7650 | pc = unmake_compact_addr (pc); | |
14132e89 | 7651 | } |
db5f024e | 7652 | |
14132e89 MR |
7653 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7654 | if (new_pc) | |
7655 | { | |
7656 | pc = new_pc; | |
4cc0665f MR |
7657 | if (is_compact_addr (pc)) |
7658 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
7659 | } |
7660 | } | |
7661 | while (pc != target_pc); | |
db5f024e | 7662 | |
14132e89 | 7663 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7664 | } |
7665 | ||
a4b8ebc8 | 7666 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7667 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7668 | |
7669 | static int | |
d3f73121 | 7670 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7671 | { |
a4b8ebc8 | 7672 | int regnum; |
2f38ef89 | 7673 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7674 | regnum = num; |
2f38ef89 | 7675 | else if (num >= 38 && num < 70) |
d3f73121 | 7676 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7677 | else if (num == 70) |
d3f73121 | 7678 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7679 | else if (num == 71) |
d3f73121 | 7680 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7681 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7682 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7683 | else |
a4b8ebc8 AC |
7684 | /* This will hopefully (eventually) provoke a warning. Should |
7685 | we be calling complaint() here? */ | |
d3f73121 MD |
7686 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7687 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
7688 | } |
7689 | ||
2f38ef89 | 7690 | |
a4b8ebc8 | 7691 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7692 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7693 | |
7694 | static int | |
d3f73121 | 7695 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7696 | { |
a4b8ebc8 | 7697 | int regnum; |
2f38ef89 | 7698 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7699 | regnum = num; |
2f38ef89 | 7700 | else if (num >= 32 && num < 64) |
d3f73121 | 7701 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7702 | else if (num == 64) |
d3f73121 | 7703 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7704 | else if (num == 65) |
d3f73121 | 7705 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7706 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7707 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7708 | else |
a4b8ebc8 AC |
7709 | /* This will hopefully (eventually) provoke a warning. Should we |
7710 | be calling complaint() here? */ | |
d3f73121 MD |
7711 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7712 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
7713 | } |
7714 | ||
7715 | static int | |
e7faf938 | 7716 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7717 | { |
7718 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7719 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7720 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7721 | decide if it is valid. Should instead define a standard sim/gdb | |
7722 | register numbering scheme. */ | |
e7faf938 MD |
7723 | if (gdbarch_register_name (gdbarch, |
7724 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7725 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7726 | gdbarch_num_regs (gdbarch) |
7727 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7728 | return regnum; |
7729 | else | |
6d82d43b | 7730 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7731 | } |
7732 | ||
2f38ef89 | 7733 | |
4844f454 CV |
7734 | /* Convert an integer into an address. Extracting the value signed |
7735 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7736 | |
7737 | static CORE_ADDR | |
79dd2d24 | 7738 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7739 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7740 | { |
e17a4113 UW |
7741 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7742 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7743 | } |
7744 | ||
82e91389 DJ |
7745 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7746 | than most other architectures; we just need to be explicit about it, | |
7747 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7748 | an assertion failure. */ | |
7749 | ||
7750 | static void | |
a54fba4c MD |
7751 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7752 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7753 | { |
7754 | *reg = MIPS_SP_REGNUM; | |
7755 | *offset = 0; | |
7756 | } | |
7757 | ||
caaa3122 DJ |
7758 | static void |
7759 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7760 | { | |
7761 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7762 | const char *name = bfd_get_section_name (abfd, sect); | |
7763 | ||
7764 | if (*abip != MIPS_ABI_UNKNOWN) | |
7765 | return; | |
7766 | ||
7767 | if (strncmp (name, ".mdebug.", 8) != 0) | |
7768 | return; | |
7769 | ||
7770 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7771 | *abip = MIPS_ABI_O32; | |
7772 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7773 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7774 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7775 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7776 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7777 | *abip = MIPS_ABI_O64; | |
7778 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7779 | *abip = MIPS_ABI_EABI32; | |
7780 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7781 | *abip = MIPS_ABI_EABI64; | |
7782 | else | |
8a3fe4f8 | 7783 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7784 | } |
7785 | ||
22e47e37 FF |
7786 | static void |
7787 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
7788 | { | |
7789 | int *lbp = (int *) obj; | |
7790 | const char *name = bfd_get_section_name (abfd, sect); | |
7791 | ||
7792 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
7793 | *lbp = 32; | |
7794 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
7795 | *lbp = 64; | |
7796 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
7797 | warning (_("unrecognized .gcc_compiled_longXX")); | |
7798 | } | |
7799 | ||
2e4ebe70 DJ |
7800 | static enum mips_abi |
7801 | global_mips_abi (void) | |
7802 | { | |
7803 | int i; | |
7804 | ||
7805 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
7806 | if (mips_abi_strings[i] == mips_abi_string) | |
7807 | return (enum mips_abi) i; | |
7808 | ||
e2e0b3e5 | 7809 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
7810 | } |
7811 | ||
4cc0665f MR |
7812 | /* Return the default compressed instruction set, either of MIPS16 |
7813 | or microMIPS, selected when none could have been determined from | |
7814 | the ELF header of the binary being executed (or no binary has been | |
7815 | selected. */ | |
7816 | ||
7817 | static enum mips_isa | |
7818 | global_mips_compression (void) | |
7819 | { | |
7820 | int i; | |
7821 | ||
7822 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
7823 | if (mips_compression_strings[i] == mips_compression_string) | |
7824 | return (enum mips_isa) i; | |
7825 | ||
7826 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
7827 | } | |
7828 | ||
29709017 DJ |
7829 | static void |
7830 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
7831 | { | |
29709017 DJ |
7832 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
7833 | assume that's what we've got. */ | |
4eb0ad19 DJ |
7834 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
7835 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7836 | |
7837 | /* If the size matches the full set of registers GDB traditionally | |
7838 | knows about, including floating point, for either 32-bit or | |
7839 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
7840 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
7841 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7842 | |
7843 | /* Otherwise we don't have a useful guess. */ | |
7844 | } | |
7845 | ||
f8b73d13 DJ |
7846 | static struct value * |
7847 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
7848 | { | |
7849 | const int *reg_p = baton; | |
7850 | return value_of_register (*reg_p, frame); | |
7851 | } | |
7852 | ||
c2d11a7d | 7853 | static struct gdbarch * |
6d82d43b | 7854 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 7855 | { |
c2d11a7d JM |
7856 | struct gdbarch *gdbarch; |
7857 | struct gdbarch_tdep *tdep; | |
7858 | int elf_flags; | |
2e4ebe70 | 7859 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 7860 | int i, num_regs; |
8d5838b5 | 7861 | enum mips_fpu_type fpu_type; |
f8b73d13 | 7862 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 7863 | int elf_fpu_type = 0; |
1faeff08 MR |
7864 | const char **reg_names; |
7865 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 7866 | enum mips_isa mips_isa; |
1faeff08 MR |
7867 | int dspacc; |
7868 | int dspctl; | |
7869 | ||
7870 | /* Fill in the OS dependent register numbers and names. */ | |
7871 | if (info.osabi == GDB_OSABI_IRIX) | |
7872 | { | |
7873 | mips_regnum.fp0 = 32; | |
7874 | mips_regnum.pc = 64; | |
7875 | mips_regnum.cause = 65; | |
7876 | mips_regnum.badvaddr = 66; | |
7877 | mips_regnum.hi = 67; | |
7878 | mips_regnum.lo = 68; | |
7879 | mips_regnum.fp_control_status = 69; | |
7880 | mips_regnum.fp_implementation_revision = 70; | |
7881 | mips_regnum.dspacc = dspacc = -1; | |
7882 | mips_regnum.dspctl = dspctl = -1; | |
7883 | num_regs = 71; | |
7884 | reg_names = mips_irix_reg_names; | |
7885 | } | |
7886 | else if (info.osabi == GDB_OSABI_LINUX) | |
7887 | { | |
7888 | mips_regnum.fp0 = 38; | |
7889 | mips_regnum.pc = 37; | |
7890 | mips_regnum.cause = 36; | |
7891 | mips_regnum.badvaddr = 35; | |
7892 | mips_regnum.hi = 34; | |
7893 | mips_regnum.lo = 33; | |
7894 | mips_regnum.fp_control_status = 70; | |
7895 | mips_regnum.fp_implementation_revision = 71; | |
7896 | mips_regnum.dspacc = -1; | |
7897 | mips_regnum.dspctl = -1; | |
7898 | dspacc = 72; | |
7899 | dspctl = 78; | |
7900 | num_regs = 79; | |
7901 | reg_names = mips_linux_reg_names; | |
7902 | } | |
7903 | else | |
7904 | { | |
7905 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
7906 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
7907 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
7908 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
7909 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
7910 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
7911 | mips_regnum.fp_control_status = 70; | |
7912 | mips_regnum.fp_implementation_revision = 71; | |
7913 | mips_regnum.dspacc = dspacc = -1; | |
7914 | mips_regnum.dspctl = dspctl = -1; | |
7915 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
7916 | if (info.bfd_arch_info != NULL | |
7917 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
7918 | reg_names = mips_tx39_reg_names; | |
7919 | else | |
7920 | reg_names = mips_generic_reg_names; | |
7921 | } | |
f8b73d13 DJ |
7922 | |
7923 | /* Check any target description for validity. */ | |
7924 | if (tdesc_has_registers (info.target_desc)) | |
7925 | { | |
7926 | static const char *const mips_gprs[] = { | |
7927 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
7928 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
7929 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
7930 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
7931 | }; | |
7932 | static const char *const mips_fprs[] = { | |
7933 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
7934 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
7935 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
7936 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
7937 | }; | |
7938 | ||
7939 | const struct tdesc_feature *feature; | |
7940 | int valid_p; | |
7941 | ||
7942 | feature = tdesc_find_feature (info.target_desc, | |
7943 | "org.gnu.gdb.mips.cpu"); | |
7944 | if (feature == NULL) | |
7945 | return NULL; | |
7946 | ||
7947 | tdesc_data = tdesc_data_alloc (); | |
7948 | ||
7949 | valid_p = 1; | |
7950 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
7951 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
7952 | mips_gprs[i]); | |
7953 | ||
7954 | ||
7955 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7956 | mips_regnum.lo, "lo"); |
f8b73d13 | 7957 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 7958 | mips_regnum.hi, "hi"); |
f8b73d13 | 7959 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 7960 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
7961 | |
7962 | if (!valid_p) | |
7963 | { | |
7964 | tdesc_data_cleanup (tdesc_data); | |
7965 | return NULL; | |
7966 | } | |
7967 | ||
7968 | feature = tdesc_find_feature (info.target_desc, | |
7969 | "org.gnu.gdb.mips.cp0"); | |
7970 | if (feature == NULL) | |
7971 | { | |
7972 | tdesc_data_cleanup (tdesc_data); | |
7973 | return NULL; | |
7974 | } | |
7975 | ||
7976 | valid_p = 1; | |
7977 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7978 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
7979 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
7980 | MIPS_PS_REGNUM, "status"); | |
7981 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7982 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
7983 | |
7984 | if (!valid_p) | |
7985 | { | |
7986 | tdesc_data_cleanup (tdesc_data); | |
7987 | return NULL; | |
7988 | } | |
7989 | ||
7990 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
7991 | backend is not prepared for that, though. */ | |
7992 | feature = tdesc_find_feature (info.target_desc, | |
7993 | "org.gnu.gdb.mips.fpu"); | |
7994 | if (feature == NULL) | |
7995 | { | |
7996 | tdesc_data_cleanup (tdesc_data); | |
7997 | return NULL; | |
7998 | } | |
7999 | ||
8000 | valid_p = 1; | |
8001 | for (i = 0; i < 32; i++) | |
8002 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8003 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8004 | |
8005 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8006 | mips_regnum.fp_control_status, |
8007 | "fcsr"); | |
8008 | valid_p | |
8009 | &= tdesc_numbered_register (feature, tdesc_data, | |
8010 | mips_regnum.fp_implementation_revision, | |
8011 | "fir"); | |
f8b73d13 DJ |
8012 | |
8013 | if (!valid_p) | |
8014 | { | |
8015 | tdesc_data_cleanup (tdesc_data); | |
8016 | return NULL; | |
8017 | } | |
8018 | ||
1faeff08 MR |
8019 | if (dspacc >= 0) |
8020 | { | |
8021 | feature = tdesc_find_feature (info.target_desc, | |
8022 | "org.gnu.gdb.mips.dsp"); | |
8023 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8024 | if (feature != NULL) | |
8025 | { | |
8026 | i = 0; | |
8027 | valid_p = 1; | |
8028 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8029 | dspacc + i++, "hi1"); | |
8030 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8031 | dspacc + i++, "lo1"); | |
8032 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8033 | dspacc + i++, "hi2"); | |
8034 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8035 | dspacc + i++, "lo2"); | |
8036 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8037 | dspacc + i++, "hi3"); | |
8038 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8039 | dspacc + i++, "lo3"); | |
8040 | ||
8041 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8042 | dspctl, "dspctl"); | |
8043 | ||
8044 | if (!valid_p) | |
8045 | { | |
8046 | tdesc_data_cleanup (tdesc_data); | |
8047 | return NULL; | |
8048 | } | |
8049 | ||
8050 | mips_regnum.dspacc = dspacc; | |
8051 | mips_regnum.dspctl = dspctl; | |
8052 | } | |
8053 | } | |
8054 | ||
f8b73d13 DJ |
8055 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8056 | when only 32-bit registers are provided. */ | |
1faeff08 | 8057 | reg_names = NULL; |
f8b73d13 | 8058 | } |
c2d11a7d | 8059 | |
ec03c1ac AC |
8060 | /* First of all, extract the elf_flags, if available. */ |
8061 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8062 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8063 | else if (arches != NULL) |
8064 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8065 | else |
8066 | elf_flags = 0; | |
8067 | if (gdbarch_debug) | |
8068 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8069 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8070 | |
102182a9 | 8071 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8072 | switch ((elf_flags & EF_MIPS_ABI)) |
8073 | { | |
8074 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8075 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8076 | break; |
8077 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8078 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8079 | break; |
8080 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8081 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8082 | break; |
8083 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8084 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8085 | break; |
8086 | default: | |
acdb74a0 | 8087 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8088 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8089 | else |
ec03c1ac | 8090 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8091 | break; |
8092 | } | |
acdb74a0 | 8093 | |
caaa3122 | 8094 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8095 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8096 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8097 | |
dc305454 | 8098 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8099 | MIPS architecture (if there is one). */ |
8100 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8101 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8102 | |
32a6503c | 8103 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8104 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8105 | && info.bfd_arch_info != NULL |
8106 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8107 | { | |
8108 | switch (info.bfd_arch_info->mach) | |
8109 | { | |
8110 | case bfd_mach_mips3900: | |
ec03c1ac | 8111 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8112 | break; |
8113 | case bfd_mach_mips4100: | |
8114 | case bfd_mach_mips5000: | |
ec03c1ac | 8115 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8116 | break; |
1d06468c EZ |
8117 | case bfd_mach_mips8000: |
8118 | case bfd_mach_mips10000: | |
32a6503c KB |
8119 | /* On Irix, ELF64 executables use the N64 ABI. The |
8120 | pseudo-sections which describe the ABI aren't present | |
8121 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
8122 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
8123 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 8124 | found_abi = MIPS_ABI_N64; |
28d169de | 8125 | else |
ec03c1ac | 8126 | found_abi = MIPS_ABI_N32; |
1d06468c | 8127 | break; |
bf64bfd6 AC |
8128 | } |
8129 | } | |
2e4ebe70 | 8130 | |
26c53e50 DJ |
8131 | /* Default 64-bit objects to N64 instead of O32. */ |
8132 | if (found_abi == MIPS_ABI_UNKNOWN | |
8133 | && info.abfd != NULL | |
8134 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8135 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8136 | found_abi = MIPS_ABI_N64; | |
8137 | ||
ec03c1ac AC |
8138 | if (gdbarch_debug) |
8139 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8140 | found_abi); | |
8141 | ||
8142 | /* What has the user specified from the command line? */ | |
8143 | wanted_abi = global_mips_abi (); | |
8144 | if (gdbarch_debug) | |
8145 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8146 | wanted_abi); | |
2e4ebe70 DJ |
8147 | |
8148 | /* Now that we have found what the ABI for this binary would be, | |
8149 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8150 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8151 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8152 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8153 | mips_abi = found_abi; | |
8154 | else | |
8155 | mips_abi = MIPS_ABI_O32; | |
8156 | if (gdbarch_debug) | |
8157 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8158 | mips_abi); | |
2e4ebe70 | 8159 | |
4cc0665f MR |
8160 | /* Determine the default compressed ISA. */ |
8161 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8162 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8163 | mips_isa = ISA_MICROMIPS; | |
8164 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8165 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8166 | mips_isa = ISA_MIPS16; | |
8167 | else | |
8168 | mips_isa = global_mips_compression (); | |
8169 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8170 | ||
ec03c1ac | 8171 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8172 | if (gdbarch_debug) |
ec03c1ac | 8173 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8174 | "mips_gdbarch_init: " |
8175 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8176 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8177 | |
8d5838b5 | 8178 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8179 | #ifdef HAVE_ELF |
8180 | if (info.abfd | |
8181 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8182 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8183 | Tag_GNU_MIPS_ABI_FP); | |
8184 | #endif /* HAVE_ELF */ | |
8185 | ||
8d5838b5 AC |
8186 | if (!mips_fpu_type_auto) |
8187 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
8188 | else if (elf_fpu_type != 0) |
8189 | { | |
8190 | switch (elf_fpu_type) | |
8191 | { | |
8192 | case 1: | |
8193 | fpu_type = MIPS_FPU_DOUBLE; | |
8194 | break; | |
8195 | case 2: | |
8196 | fpu_type = MIPS_FPU_SINGLE; | |
8197 | break; | |
8198 | case 3: | |
8199 | default: | |
8200 | /* Soft float or unknown. */ | |
8201 | fpu_type = MIPS_FPU_NONE; | |
8202 | break; | |
8203 | } | |
8204 | } | |
8d5838b5 AC |
8205 | else if (info.bfd_arch_info != NULL |
8206 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8207 | switch (info.bfd_arch_info->mach) | |
8208 | { | |
8209 | case bfd_mach_mips3900: | |
8210 | case bfd_mach_mips4100: | |
8211 | case bfd_mach_mips4111: | |
a9d61c86 | 8212 | case bfd_mach_mips4120: |
8d5838b5 AC |
8213 | fpu_type = MIPS_FPU_NONE; |
8214 | break; | |
8215 | case bfd_mach_mips4650: | |
8216 | fpu_type = MIPS_FPU_SINGLE; | |
8217 | break; | |
8218 | default: | |
8219 | fpu_type = MIPS_FPU_DOUBLE; | |
8220 | break; | |
8221 | } | |
8222 | else if (arches != NULL) | |
8223 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
8224 | else | |
8225 | fpu_type = MIPS_FPU_DOUBLE; | |
8226 | if (gdbarch_debug) | |
8227 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8228 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8229 | |
29709017 DJ |
8230 | /* Check for blatant incompatibilities. */ |
8231 | ||
8232 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8233 | ABI. */ | |
8234 | if (info.target_desc | |
8235 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8236 | && mips_abi != MIPS_ABI_EABI32 | |
8237 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8238 | { |
8239 | if (tdesc_data != NULL) | |
8240 | tdesc_data_cleanup (tdesc_data); | |
8241 | return NULL; | |
8242 | } | |
29709017 | 8243 | |
025bb325 | 8244 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8245 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8246 | arches != NULL; | |
8247 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8248 | { | |
8249 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 8250 | using. */ |
9103eae0 | 8251 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8252 | continue; |
9103eae0 | 8253 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8254 | continue; |
719ec221 AC |
8255 | /* Need to be pedantic about which register virtual size is |
8256 | used. */ | |
8257 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8258 | != mips64_transfers_32bit_regs_p) | |
8259 | continue; | |
8d5838b5 AC |
8260 | /* Be pedantic about which FPU is selected. */ |
8261 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
8262 | continue; | |
f8b73d13 DJ |
8263 | |
8264 | if (tdesc_data != NULL) | |
8265 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8266 | return arches->gdbarch; |
c2d11a7d JM |
8267 | } |
8268 | ||
102182a9 | 8269 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
8270 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
8271 | gdbarch = gdbarch_alloc (&info, tdep); | |
8272 | tdep->elf_flags = elf_flags; | |
719ec221 | 8273 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8274 | tdep->found_abi = found_abi; |
8275 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8276 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8277 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8278 | tdep->register_size_valid_p = 0; |
8279 | tdep->register_size = 0; | |
50e8a0d5 HZ |
8280 | tdep->gregset = NULL; |
8281 | tdep->gregset64 = NULL; | |
8282 | tdep->fpregset = NULL; | |
8283 | tdep->fpregset64 = NULL; | |
29709017 DJ |
8284 | |
8285 | if (info.target_desc) | |
8286 | { | |
8287 | /* Some useful properties can be inferred from the target. */ | |
8288 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8289 | { | |
8290 | tdep->register_size_valid_p = 1; | |
8291 | tdep->register_size = 4; | |
8292 | } | |
8293 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8294 | { | |
8295 | tdep->register_size_valid_p = 1; | |
8296 | tdep->register_size = 8; | |
8297 | } | |
8298 | } | |
c2d11a7d | 8299 | |
102182a9 | 8300 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8301 | set_gdbarch_short_bit (gdbarch, 16); |
8302 | set_gdbarch_int_bit (gdbarch, 32); | |
8303 | set_gdbarch_float_bit (gdbarch, 32); | |
8304 | set_gdbarch_double_bit (gdbarch, 64); | |
8305 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8306 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8307 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8308 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8309 | |
175ff332 HZ |
8310 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8311 | mips_ax_pseudo_register_collect); | |
8312 | set_gdbarch_ax_pseudo_register_push_stack | |
8313 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8314 | ||
6d82d43b | 8315 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
8316 | mips_elf_make_msymbol_special); |
8317 | ||
1faeff08 MR |
8318 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8319 | *regnum = mips_regnum; | |
1faeff08 MR |
8320 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8321 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8322 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8323 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8324 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8325 | tdep->mips_processor_reg_names = reg_names; | |
8326 | tdep->regnum = regnum; | |
fe29b929 | 8327 | |
0dadbba0 | 8328 | switch (mips_abi) |
c2d11a7d | 8329 | { |
0dadbba0 | 8330 | case MIPS_ABI_O32: |
25ab4790 | 8331 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8332 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8333 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8334 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8335 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8336 | set_gdbarch_long_bit (gdbarch, 32); |
8337 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8338 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8339 | break; | |
0dadbba0 | 8340 | case MIPS_ABI_O64: |
25ab4790 | 8341 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8342 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8343 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8344 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8345 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8346 | set_gdbarch_long_bit (gdbarch, 32); |
8347 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8348 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8349 | break; | |
0dadbba0 | 8350 | case MIPS_ABI_EABI32: |
25ab4790 | 8351 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8352 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8353 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8354 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8355 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8356 | set_gdbarch_long_bit (gdbarch, 32); |
8357 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8358 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8359 | break; | |
0dadbba0 | 8360 | case MIPS_ABI_EABI64: |
25ab4790 | 8361 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8362 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8363 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8364 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8365 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8366 | set_gdbarch_long_bit (gdbarch, 64); |
8367 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8368 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8369 | break; | |
0dadbba0 | 8370 | case MIPS_ABI_N32: |
25ab4790 | 8371 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8372 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8373 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8374 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8375 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8376 | set_gdbarch_long_bit (gdbarch, 32); |
8377 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8378 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8379 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8380 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8381 | break; |
8382 | case MIPS_ABI_N64: | |
25ab4790 | 8383 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8384 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8385 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8386 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8387 | tdep->default_mask_address_p = 0; |
8388 | set_gdbarch_long_bit (gdbarch, 64); | |
8389 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8390 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8391 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8392 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8393 | break; |
c2d11a7d | 8394 | default: |
e2e0b3e5 | 8395 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8396 | } |
8397 | ||
22e47e37 FF |
8398 | /* GCC creates a pseudo-section whose name specifies the size of |
8399 | longs, since -mlong32 or -mlong64 may be used independent of | |
8400 | other options. How those options affect pointer sizes is ABI and | |
8401 | architecture dependent, so use them to override the default sizes | |
8402 | set by the ABI. This table shows the relationship between ABI, | |
8403 | -mlongXX, and size of pointers: | |
8404 | ||
8405 | ABI -mlongXX ptr bits | |
8406 | --- -------- -------- | |
8407 | o32 32 32 | |
8408 | o32 64 32 | |
8409 | n32 32 32 | |
8410 | n32 64 64 | |
8411 | o64 32 32 | |
8412 | o64 64 64 | |
8413 | n64 32 32 | |
8414 | n64 64 64 | |
8415 | eabi32 32 32 | |
8416 | eabi32 64 32 | |
8417 | eabi64 32 32 | |
8418 | eabi64 64 64 | |
8419 | ||
8420 | Note that for o32 and eabi32, pointers are always 32 bits | |
8421 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8422 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8423 | |
8424 | if (info.abfd != NULL) | |
8425 | { | |
8426 | int long_bit = 0; | |
8427 | ||
8428 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8429 | if (long_bit) | |
8430 | { | |
8431 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8432 | switch (mips_abi) | |
8433 | { | |
8434 | case MIPS_ABI_O32: | |
8435 | case MIPS_ABI_EABI32: | |
8436 | break; | |
8437 | case MIPS_ABI_N32: | |
8438 | case MIPS_ABI_O64: | |
8439 | case MIPS_ABI_N64: | |
8440 | case MIPS_ABI_EABI64: | |
8441 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8442 | break; | |
8443 | default: | |
8444 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8445 | } | |
8446 | } | |
8447 | } | |
8448 | ||
a5ea2558 AC |
8449 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8450 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8451 | comment: | |
8452 | ||
8453 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8454 | flag in object files because to do so would make it impossible to | |
102182a9 | 8455 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8456 | unnecessarily restrictive. |
361d1df0 | 8457 | |
a5ea2558 AC |
8458 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8459 | but to set this flag before gcc is built with such multilibs will | |
8460 | break too many systems.'' | |
8461 | ||
8462 | But even more unhelpfully, the default linker output target for | |
8463 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8464 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8465 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8466 | this flag to detect 32-bit mode would do the wrong thing given |
8467 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8468 | as 32-bit programs by default. */ |
a5ea2558 | 8469 | |
6c997a34 | 8470 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8471 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8472 | |
102182a9 MS |
8473 | /* Add/remove bits from an address. The MIPS needs be careful to |
8474 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8475 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8476 | ||
58dfe9ff AC |
8477 | /* Unwind the frame. */ |
8478 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8479 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8480 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8481 | |
102182a9 | 8482 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8483 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8484 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8485 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8486 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8487 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8488 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8489 | |
025bb325 | 8490 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8491 | |
2c76a0c7 JB |
8492 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8493 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8494 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8495 | |
87783b8b AC |
8496 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8497 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8498 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8499 | ||
f7b9e9fc AC |
8500 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
8501 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4cc0665f MR |
8502 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
8503 | mips_remote_breakpoint_from_pc); | |
c8cef75f MR |
8504 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8505 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8506 | |
8507 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8508 | |
97ab0fdd MR |
8509 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
8510 | ||
fc0c74b1 AC |
8511 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8512 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8513 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8514 | |
a4b8ebc8 | 8515 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8516 | |
e11c53d2 | 8517 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8518 | |
9dae60cc UW |
8519 | if (mips_abi == MIPS_ABI_N32) |
8520 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8521 | else if (mips_abi == MIPS_ABI_N64) | |
8522 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8523 | else | |
8524 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8525 | |
d92524f1 PM |
8526 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8527 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8528 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8529 | being used as guards for target_stopped_by_watchpoint, why not have |
8530 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8531 | is sitting on? */ |
8532 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8533 | ||
e7d6a6d2 | 8534 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8535 | |
14132e89 MR |
8536 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8537 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8538 | if we have an OS ABI that actually supports shared libraries, since | |
8539 | shared library support is more important. If we have an OS someday | |
8540 | that supports both shared libraries and MIPS16, we'll have to find | |
8541 | a better place for these. | |
8542 | macro/2012-04-25: But that applies to return trampolines only and | |
8543 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8544 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8545 | ||
025bb325 MS |
8546 | set_gdbarch_single_step_through_delay (gdbarch, |
8547 | mips_single_step_through_delay); | |
3352ef37 | 8548 | |
0d5de010 DJ |
8549 | /* Virtual tables. */ |
8550 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8551 | ||
29709017 DJ |
8552 | mips_register_g_packet_guesses (gdbarch); |
8553 | ||
6de918a6 | 8554 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 8555 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 8556 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8557 | |
9aac7884 MR |
8558 | /* The hook may have adjusted num_regs, fetch the final value and |
8559 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8560 | num_regs = gdbarch_num_regs (gdbarch); |
8561 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8562 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8563 | ||
5792a79b | 8564 | /* Unwind the frame. */ |
b8a22b94 DJ |
8565 | dwarf2_append_unwinders (gdbarch); |
8566 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8567 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8568 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8569 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8570 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8571 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8572 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8573 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8574 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8575 | |
f8b73d13 DJ |
8576 | if (tdesc_data) |
8577 | { | |
8578 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8579 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8580 | |
8581 | /* Override the normal target description methods to handle our | |
8582 | dual real and pseudo registers. */ | |
8583 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8584 | set_gdbarch_register_reggroup_p (gdbarch, |
8585 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8586 | |
8587 | num_regs = gdbarch_num_regs (gdbarch); | |
8588 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8589 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8590 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8591 | } | |
8592 | ||
8593 | /* Add ABI-specific aliases for the registers. */ | |
8594 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8595 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8596 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8597 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8598 | else | |
8599 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8600 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8601 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8602 | ||
8603 | /* Add some other standard aliases. */ | |
8604 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8605 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8606 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8607 | ||
865093a3 AR |
8608 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8609 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8610 | value_of_mips_user_reg, | |
8611 | &mips_numeric_register_aliases[i].regnum); | |
8612 | ||
4b9b3959 AC |
8613 | return gdbarch; |
8614 | } | |
8615 | ||
2e4ebe70 | 8616 | static void |
6d82d43b | 8617 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
8618 | { |
8619 | struct gdbarch_info info; | |
8620 | ||
8621 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8622 | mips_gdbarch_init will take care of the rest. */ | |
8623 | gdbarch_info_init (&info); | |
8624 | gdbarch_update_p (info); | |
8625 | } | |
8626 | ||
ad188201 KB |
8627 | /* Print out which MIPS ABI is in use. */ |
8628 | ||
8629 | static void | |
1f8ca57c JB |
8630 | show_mips_abi (struct ui_file *file, |
8631 | int from_tty, | |
8632 | struct cmd_list_element *ignored_cmd, | |
8633 | const char *ignored_value) | |
ad188201 | 8634 | { |
1cf3db46 | 8635 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
8636 | fprintf_filtered |
8637 | (file, | |
8638 | "The MIPS ABI is unknown because the current architecture " | |
8639 | "is not MIPS.\n"); | |
ad188201 KB |
8640 | else |
8641 | { | |
8642 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 8643 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
8644 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8645 | ||
8646 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8647 | fprintf_filtered |
8648 | (file, | |
8649 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8650 | actual_abi_str); |
ad188201 | 8651 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8652 | fprintf_filtered |
8653 | (file, | |
8654 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8655 | actual_abi_str); |
ad188201 KB |
8656 | else |
8657 | { | |
8658 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8659 | fprintf_filtered (file, |
8660 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8661 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8662 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8663 | } |
8664 | } | |
8665 | } | |
8666 | ||
4cc0665f MR |
8667 | /* Print out which MIPS compressed ISA encoding is used. */ |
8668 | ||
8669 | static void | |
8670 | show_mips_compression (struct ui_file *file, int from_tty, | |
8671 | struct cmd_list_element *c, const char *value) | |
8672 | { | |
8673 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8674 | value); | |
8675 | } | |
8676 | ||
4b9b3959 | 8677 | static void |
72a155b4 | 8678 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8679 | { |
72a155b4 | 8680 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8681 | if (tdep != NULL) |
c2d11a7d | 8682 | { |
acdb74a0 AC |
8683 | int ef_mips_arch; |
8684 | int ef_mips_32bitmode; | |
f49e4e6d | 8685 | /* Determine the ISA. */ |
acdb74a0 AC |
8686 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8687 | { | |
8688 | case E_MIPS_ARCH_1: | |
8689 | ef_mips_arch = 1; | |
8690 | break; | |
8691 | case E_MIPS_ARCH_2: | |
8692 | ef_mips_arch = 2; | |
8693 | break; | |
8694 | case E_MIPS_ARCH_3: | |
8695 | ef_mips_arch = 3; | |
8696 | break; | |
8697 | case E_MIPS_ARCH_4: | |
93d56215 | 8698 | ef_mips_arch = 4; |
acdb74a0 AC |
8699 | break; |
8700 | default: | |
93d56215 | 8701 | ef_mips_arch = 0; |
acdb74a0 AC |
8702 | break; |
8703 | } | |
f49e4e6d | 8704 | /* Determine the size of a pointer. */ |
acdb74a0 | 8705 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8706 | fprintf_unfiltered (file, |
8707 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8708 | tdep->elf_flags); |
4b9b3959 | 8709 | fprintf_unfiltered (file, |
acdb74a0 AC |
8710 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8711 | ef_mips_32bitmode); | |
8712 | fprintf_unfiltered (file, | |
8713 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8714 | ef_mips_arch); | |
8715 | fprintf_unfiltered (file, | |
8716 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8717 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8718 | fprintf_unfiltered (file, |
025bb325 MS |
8719 | "mips_dump_tdep: " |
8720 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8721 | mips_mask_address_p (tdep), |
4014092b | 8722 | tdep->default_mask_address_p); |
c2d11a7d | 8723 | } |
4b9b3959 AC |
8724 | fprintf_unfiltered (file, |
8725 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8726 | MIPS_DEFAULT_FPU_TYPE, | |
8727 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
8728 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
8729 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
8730 | : "???")); | |
74ed0bb4 MD |
8731 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8732 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8733 | fprintf_unfiltered (file, |
8734 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
8735 | MIPS_FPU_TYPE (gdbarch), |
8736 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
8737 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
8738 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 8739 | : "???")); |
c2d11a7d JM |
8740 | } |
8741 | ||
025bb325 | 8742 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 8743 | |
c906108c | 8744 | void |
acdb74a0 | 8745 | _initialize_mips_tdep (void) |
c906108c SS |
8746 | { |
8747 | static struct cmd_list_element *mipsfpulist = NULL; | |
8748 | struct cmd_list_element *c; | |
8749 | ||
6d82d43b | 8750 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8751 | if (MIPS_ABI_LAST + 1 |
8752 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8753 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8754 | |
4b9b3959 | 8755 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8756 | |
8d5f9dcb DJ |
8757 | mips_pdr_data = register_objfile_data (); |
8758 | ||
4eb0ad19 DJ |
8759 | /* Create feature sets with the appropriate properties. The values |
8760 | are not important. */ | |
8761 | mips_tdesc_gp32 = allocate_target_description (); | |
8762 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8763 | ||
8764 | mips_tdesc_gp64 = allocate_target_description (); | |
8765 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8766 | ||
025bb325 | 8767 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8768 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8769 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8770 | &setmipscmdlist, "set mips ", 0, &setlist); |
8771 | ||
8772 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8773 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8774 | &showmipscmdlist, "show mips ", 0, &showlist); |
8775 | ||
025bb325 | 8776 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8777 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8778 | &mips_abi_string, _("\ | |
8779 | Set the MIPS ABI used by this program."), _("\ | |
8780 | Show the MIPS ABI used by this program."), _("\ | |
8781 | This option can be set to one of:\n\ | |
8782 | auto - the default ABI associated with the current binary\n\ | |
8783 | o32\n\ | |
8784 | o64\n\ | |
8785 | n32\n\ | |
8786 | n64\n\ | |
8787 | eabi32\n\ | |
8788 | eabi64"), | |
8789 | mips_abi_update, | |
8790 | show_mips_abi, | |
8791 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 8792 | |
4cc0665f MR |
8793 | /* Allow the user to set the ISA to assume for compressed code if ELF |
8794 | file flags don't tell or there is no program file selected. This | |
8795 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
8796 | and carried over to subsequent sessions. */ | |
8797 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
8798 | &mips_compression_string, _("\ | |
8799 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
8800 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
8801 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
8802 | information available. The encoding can be set to either of:\n\ | |
8803 | mips16\n\ | |
8804 | micromips\n\ | |
8805 | and is updated automatically from ELF file flags if available."), | |
8806 | mips_abi_update, | |
8807 | show_mips_compression, | |
8808 | &setmipscmdlist, &showmipscmdlist); | |
8809 | ||
c906108c SS |
8810 | /* Let the user turn off floating point and set the fence post for |
8811 | heuristic_proc_start. */ | |
8812 | ||
8813 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 8814 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
8815 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
8816 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 8817 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
8818 | &mipsfpulist); |
8819 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 8820 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
8821 | &mipsfpulist); |
8822 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
8823 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
8824 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
8825 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 8826 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
8827 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
8828 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
8829 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
8830 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 8831 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
8832 | &mipsfpulist); |
8833 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 8834 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
8835 | &showlist); |
8836 | ||
c906108c SS |
8837 | /* We really would like to have both "0" and "unlimited" work, but |
8838 | command.c doesn't deal with that. So make it a var_zinteger | |
8839 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 8840 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
8841 | &heuristic_fence_post, _("\ |
8842 | Set the distance searched for the start of a function."), _("\ | |
8843 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
8844 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
8845 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 8846 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 8847 | reinit_frame_cache_sfunc, |
025bb325 MS |
8848 | NULL, /* FIXME: i18n: The distance searched for |
8849 | the start of a function is %s. */ | |
6bcadd06 | 8850 | &setlist, &showlist); |
c906108c SS |
8851 | |
8852 | /* Allow the user to control whether the upper bits of 64-bit | |
8853 | addresses should be zeroed. */ | |
7915a72c AC |
8854 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
8855 | &mask_address_var, _("\ | |
8856 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
8857 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 8858 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 8859 | allow GDB to determine the correct value."), |
08546159 AC |
8860 | NULL, show_mask_address, |
8861 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
8862 | |
8863 | /* Allow the user to control the size of 32 bit registers within the | |
8864 | raw remote packet. */ | |
b3f42336 | 8865 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
8866 | &mips64_transfers_32bit_regs_p, _("\ |
8867 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8868 | _("\ | |
8869 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8870 | _("\ | |
719ec221 AC |
8871 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
8872 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 8873 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 8874 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
8875 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
8876 | MIPS target that transfers 32-bit | |
8877 | quantities is %s. */ | |
7915a72c | 8878 | &setlist, &showlist); |
9ace0497 | 8879 | |
025bb325 | 8880 | /* Debug this files internals. */ |
6bcadd06 | 8881 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
8882 | &mips_debug, _("\ |
8883 | Set mips debugging."), _("\ | |
8884 | Show mips debugging."), _("\ | |
8885 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 8886 | NULL, |
025bb325 MS |
8887 | NULL, /* FIXME: i18n: Mips debugging is |
8888 | currently %s. */ | |
6bcadd06 | 8889 | &setdebuglist, &showdebuglist); |
c906108c | 8890 | } |