Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 AC |
2 | |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, | |
4fcf66da | 4 | 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
c906108c SS |
40 | |
41 | #include "opcode/mips.h" | |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
c906108c | 45 | |
b0069a17 AC |
46 | /* The sizes of floating point registers. */ |
47 | ||
48 | enum | |
49 | { | |
50 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
51 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
52 | }; | |
53 | ||
0dadbba0 AC |
54 | /* All the possible MIPS ABIs. */ |
55 | ||
56 | enum mips_abi | |
57 | { | |
58 | MIPS_ABI_UNKNOWN, | |
59 | MIPS_ABI_N32, | |
60 | MIPS_ABI_O32, | |
61 | MIPS_ABI_O64, | |
62 | MIPS_ABI_EABI32, | |
63 | MIPS_ABI_EABI64 | |
64 | }; | |
65 | ||
cce74817 | 66 | struct frame_extra_info |
c5aa993b JM |
67 | { |
68 | mips_extra_func_info_t proc_desc; | |
69 | int num_args; | |
70 | }; | |
cce74817 | 71 | |
d929b26f AC |
72 | /* Various MIPS ISA options (related to stack analysis) can be |
73 | overridden dynamically. Establish an enum/array for managing | |
74 | them. */ | |
75 | ||
53904c9e AC |
76 | static const char size_auto[] = "auto"; |
77 | static const char size_32[] = "32"; | |
78 | static const char size_64[] = "64"; | |
d929b26f | 79 | |
53904c9e | 80 | static const char *size_enums[] = { |
d929b26f AC |
81 | size_auto, |
82 | size_32, | |
83 | size_64, | |
a5ea2558 AC |
84 | 0 |
85 | }; | |
86 | ||
7a292a7a SS |
87 | /* Some MIPS boards don't support floating point while others only |
88 | support single-precision floating-point operations. See also | |
89 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
90 | |
91 | enum mips_fpu_type | |
c5aa993b JM |
92 | { |
93 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
94 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
95 | MIPS_FPU_NONE /* No floating point. */ | |
96 | }; | |
c906108c SS |
97 | |
98 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
99 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
100 | #endif | |
101 | static int mips_fpu_type_auto = 1; | |
102 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
103 | #define MIPS_FPU_TYPE mips_fpu_type | |
104 | ||
c906108c | 105 | /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */ |
7a292a7a | 106 | #ifndef FP_REGISTER_DOUBLE |
c906108c | 107 | #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8) |
7a292a7a SS |
108 | #endif |
109 | ||
9ace0497 | 110 | static int mips_debug = 0; |
7a292a7a | 111 | |
c2d11a7d JM |
112 | /* MIPS specific per-architecture information */ |
113 | struct gdbarch_tdep | |
114 | { | |
115 | /* from the elf header */ | |
116 | int elf_flags; | |
117 | /* mips options */ | |
0dadbba0 | 118 | enum mips_abi mips_abi; |
acdb74a0 | 119 | const char *mips_abi_string; |
c2d11a7d JM |
120 | enum mips_fpu_type mips_fpu_type; |
121 | int mips_last_arg_regnum; | |
122 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 123 | int mips_default_saved_regsize; |
c2d11a7d | 124 | int mips_fp_register_double; |
d929b26f AC |
125 | int mips_regs_have_home_p; |
126 | int mips_default_stack_argsize; | |
5213ab06 | 127 | int gdb_target_is_mips64; |
4014092b | 128 | int default_mask_address_p; |
c2d11a7d JM |
129 | }; |
130 | ||
131 | #if GDB_MULTI_ARCH | |
132 | #undef MIPS_EABI | |
0dadbba0 | 133 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 134 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d JM |
135 | #endif |
136 | ||
137 | #if GDB_MULTI_ARCH | |
138 | #undef MIPS_LAST_FP_ARG_REGNUM | |
139 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) | |
140 | #endif | |
141 | ||
142 | #if GDB_MULTI_ARCH | |
143 | #undef MIPS_LAST_ARG_REGNUM | |
144 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) | |
145 | #endif | |
146 | ||
147 | #if GDB_MULTI_ARCH | |
148 | #undef MIPS_FPU_TYPE | |
149 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) | |
150 | #endif | |
151 | ||
d929b26f AC |
152 | /* Return the currently configured (or set) saved register size. */ |
153 | ||
c2d11a7d | 154 | #if GDB_MULTI_ARCH |
a5ea2558 AC |
155 | #undef MIPS_DEFAULT_SAVED_REGSIZE |
156 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) | |
d929b26f AC |
157 | #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE) |
158 | #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE | |
c2d11a7d JM |
159 | #endif |
160 | ||
53904c9e | 161 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
162 | |
163 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
164 | ||
165 | static unsigned int | |
acdb74a0 | 166 | mips_saved_regsize (void) |
d929b26f AC |
167 | { |
168 | if (mips_saved_regsize_string == size_auto) | |
169 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
170 | else if (mips_saved_regsize_string == size_64) | |
171 | return 8; | |
172 | else /* if (mips_saved_regsize_string == size_32) */ | |
173 | return 4; | |
174 | } | |
175 | ||
c2d11a7d JM |
176 | /* Indicate that the ABI makes use of double-precision registers |
177 | provided by the FPU (rather than combining pairs of registers to | |
178 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
179 | determine if the ABI is using double-precision registers. See also | |
180 | MIPS_FPU_TYPE. */ | |
181 | #if GDB_MULTI_ARCH | |
182 | #undef FP_REGISTER_DOUBLE | |
183 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) | |
184 | #endif | |
185 | ||
d929b26f AC |
186 | /* Does the caller allocate a ``home'' for each register used in the |
187 | function call? The N32 ABI and MIPS_EABI do not, the others do. */ | |
188 | ||
189 | #if GDB_MULTI_ARCH | |
190 | #undef MIPS_REGS_HAVE_HOME_P | |
191 | #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p) | |
192 | #elif !defined (MIPS_REGS_HAVE_HOME_P) | |
193 | #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI) | |
194 | #endif | |
195 | ||
196 | /* The amount of space reserved on the stack for registers. This is | |
197 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
198 | data allocated after the registers have run out. */ | |
199 | ||
200 | #if GDB_MULTI_ARCH | |
201 | #undef MIPS_DEFAULT_STACK_ARGSIZE | |
0dadbba0 | 202 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
203 | #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE) |
204 | #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE) | |
205 | #endif | |
206 | ||
207 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
208 | ||
53904c9e | 209 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
210 | |
211 | static unsigned int | |
212 | mips_stack_argsize (void) | |
213 | { | |
214 | if (mips_stack_argsize_string == size_auto) | |
215 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
216 | else if (mips_stack_argsize_string == size_64) | |
217 | return 8; | |
218 | else /* if (mips_stack_argsize_string == size_32) */ | |
219 | return 4; | |
220 | } | |
221 | ||
5213ab06 AC |
222 | #if GDB_MULTI_ARCH |
223 | #undef GDB_TARGET_IS_MIPS64 | |
224 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) | |
225 | #endif | |
c2d11a7d | 226 | |
92e1c15c FF |
227 | #if GDB_MULTI_ARCH |
228 | #undef MIPS_DEFAULT_MASK_ADDRESS_P | |
229 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) | |
230 | #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P) | |
231 | #define MIPS_DEFAULT_MASK_ADDRESS_P (0) | |
232 | #endif | |
233 | ||
7a292a7a | 234 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 235 | |
a14ed312 | 236 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 237 | |
a14ed312 | 238 | static void mips_print_register (int, int); |
c906108c SS |
239 | |
240 | static mips_extra_func_info_t | |
a14ed312 | 241 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *); |
c906108c | 242 | |
a14ed312 | 243 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 244 | |
a14ed312 | 245 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 246 | |
a14ed312 | 247 | int mips_set_processor_type (char *); |
c906108c | 248 | |
a14ed312 | 249 | static void mips_show_processor_type_command (char *, int); |
c906108c | 250 | |
a14ed312 | 251 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
252 | |
253 | static mips_extra_func_info_t | |
a14ed312 | 254 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame); |
c906108c | 255 | |
a14ed312 KB |
256 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
257 | mips_extra_func_info_t proc_desc); | |
c906108c SS |
258 | |
259 | /* This value is the model of MIPS in use. It is derived from the value | |
260 | of the PrID register. */ | |
261 | ||
262 | char *mips_processor_type; | |
263 | ||
264 | char *tmp_mips_processor_type; | |
265 | ||
acdb74a0 AC |
266 | /* The list of available "set mips " and "show mips " commands */ |
267 | ||
268 | static struct cmd_list_element *setmipscmdlist = NULL; | |
269 | static struct cmd_list_element *showmipscmdlist = NULL; | |
270 | ||
c906108c SS |
271 | /* A set of original names, to be used when restoring back to generic |
272 | registers from a specific set. */ | |
273 | ||
cce74817 JM |
274 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
275 | char **mips_processor_reg_names = mips_generic_reg_names; | |
276 | ||
277 | char * | |
fba45db2 | 278 | mips_register_name (int i) |
cce74817 JM |
279 | { |
280 | return mips_processor_reg_names[i]; | |
281 | } | |
9846de1b | 282 | /* *INDENT-OFF* */ |
c906108c SS |
283 | /* Names of IDT R3041 registers. */ |
284 | ||
285 | char *mips_r3041_reg_names[] = { | |
286 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
287 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
288 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
289 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
290 | "sr", "lo", "hi", "bad", "cause","pc", | |
291 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
292 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
293 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
294 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
295 | "fsr", "fir", "fp", "", | |
296 | "", "", "bus", "ccfg", "", "", "", "", | |
297 | "", "", "port", "cmp", "", "", "epc", "prid", | |
298 | }; | |
299 | ||
300 | /* Names of IDT R3051 registers. */ | |
301 | ||
302 | char *mips_r3051_reg_names[] = { | |
303 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
304 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
305 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
306 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
307 | "sr", "lo", "hi", "bad", "cause","pc", | |
308 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
309 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
310 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
311 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
312 | "fsr", "fir", "fp", "", | |
313 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
314 | "", "", "ehi", "", "", "", "epc", "prid", | |
315 | }; | |
316 | ||
317 | /* Names of IDT R3081 registers. */ | |
318 | ||
319 | char *mips_r3081_reg_names[] = { | |
320 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
321 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
322 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
323 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
324 | "sr", "lo", "hi", "bad", "cause","pc", | |
325 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
326 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
327 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
328 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
329 | "fsr", "fir", "fp", "", | |
330 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
331 | "", "", "ehi", "", "", "", "epc", "prid", | |
332 | }; | |
333 | ||
334 | /* Names of LSI 33k registers. */ | |
335 | ||
336 | char *mips_lsi33k_reg_names[] = { | |
337 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
338 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
339 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
340 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
341 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
342 | "dcic", "bpc", "bda", "", "", "", "", "", | |
343 | "", "", "", "", "", "", "", "", | |
344 | "", "", "", "", "", "", "", "", | |
345 | "", "", "", "", "", "", "", "", | |
346 | "", "", "", "", | |
347 | "", "", "", "", "", "", "", "", | |
348 | "", "", "", "", "", "", "", "", | |
349 | }; | |
350 | ||
351 | struct { | |
352 | char *name; | |
353 | char **regnames; | |
354 | } mips_processor_type_table[] = { | |
355 | { "generic", mips_generic_reg_names }, | |
356 | { "r3041", mips_r3041_reg_names }, | |
357 | { "r3051", mips_r3051_reg_names }, | |
358 | { "r3071", mips_r3081_reg_names }, | |
359 | { "r3081", mips_r3081_reg_names }, | |
360 | { "lsi33k", mips_lsi33k_reg_names }, | |
361 | { NULL, NULL } | |
362 | }; | |
9846de1b | 363 | /* *INDENT-ON* */ |
c906108c | 364 | |
c5aa993b JM |
365 | |
366 | ||
367 | ||
c906108c | 368 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
369 | static int mips16_to_32_reg[8] = |
370 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
371 | |
372 | /* Heuristic_proc_start may hunt through the text section for a long | |
373 | time across a 2400 baud serial line. Allows the user to limit this | |
374 | search. */ | |
375 | ||
376 | static unsigned int heuristic_fence_post = 0; | |
377 | ||
c5aa993b JM |
378 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
379 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
380 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
381 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
382 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
383 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
384 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
385 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
386 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
387 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
388 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
389 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
390 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
391 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
392 | ||
393 | struct linked_proc_info | |
c5aa993b JM |
394 | { |
395 | struct mips_extra_func_info info; | |
396 | struct linked_proc_info *next; | |
397 | } | |
398 | *linked_proc_desc_table = NULL; | |
c906108c | 399 | |
cce74817 | 400 | void |
acdb74a0 | 401 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
402 | { |
403 | if (fi | |
404 | && fi->extra_info | |
405 | && fi->extra_info->proc_desc | |
406 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 407 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 408 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 409 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 410 | } |
c906108c | 411 | |
43e526b9 JM |
412 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
413 | defines the remote-gdb packet. */ | |
414 | ||
415 | static int mips64_transfers_32bit_regs_p = 0; | |
416 | ||
417 | int | |
acdb74a0 | 418 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
419 | { |
420 | if (mips64_transfers_32bit_regs_p) | |
421 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
422 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
423 | && FP_REGISTER_DOUBLE) | |
424 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
425 | registers. */ | |
426 | return 8; | |
43e526b9 JM |
427 | else |
428 | return MIPS_REGSIZE; | |
429 | } | |
430 | ||
431 | int | |
acdb74a0 | 432 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
433 | { |
434 | if (mips64_transfers_32bit_regs_p) | |
435 | return 0; | |
436 | else | |
437 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
438 | } | |
439 | ||
440 | void | |
acdb74a0 AC |
441 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
442 | char *raw_buf, char *virt_buf) | |
43e526b9 JM |
443 | { |
444 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
445 | memcpy (virt_buf, | |
446 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
447 | TYPE_LENGTH (virtual_type)); | |
448 | else | |
449 | memcpy (virt_buf, | |
450 | raw_buf, | |
451 | TYPE_LENGTH (virtual_type)); | |
452 | } | |
453 | ||
454 | void | |
acdb74a0 AC |
455 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
456 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
457 | { |
458 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
459 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
460 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
461 | virt_buf, | |
462 | TYPE_LENGTH (virtual_type)); | |
463 | else | |
464 | memcpy (raw_buf, | |
465 | virt_buf, | |
466 | TYPE_LENGTH (virtual_type)); | |
467 | } | |
468 | ||
c906108c | 469 | /* Should the upper word of 64-bit addresses be zeroed? */ |
4014092b AC |
470 | enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO; |
471 | ||
472 | static int | |
473 | mips_mask_address_p (void) | |
474 | { | |
475 | switch (mask_address_var) | |
476 | { | |
477 | case CMD_AUTO_BOOLEAN_TRUE: | |
478 | return 1; | |
479 | case CMD_AUTO_BOOLEAN_FALSE: | |
480 | return 0; | |
481 | break; | |
482 | case CMD_AUTO_BOOLEAN_AUTO: | |
92e1c15c | 483 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 484 | default: |
8e65ff28 AC |
485 | internal_error (__FILE__, __LINE__, |
486 | "mips_mask_address_p: bad switch"); | |
4014092b AC |
487 | return -1; |
488 | } | |
489 | } | |
490 | ||
491 | static void | |
492 | show_mask_address (char *cmd, int from_tty) | |
493 | { | |
494 | switch (mask_address_var) | |
495 | { | |
496 | case CMD_AUTO_BOOLEAN_TRUE: | |
497 | printf_filtered ("The 32 bit mips address mask is enabled\n"); | |
498 | break; | |
499 | case CMD_AUTO_BOOLEAN_FALSE: | |
500 | printf_filtered ("The 32 bit mips address mask is disabled\n"); | |
501 | break; | |
502 | case CMD_AUTO_BOOLEAN_AUTO: | |
503 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", | |
504 | mips_mask_address_p () ? "enabled" : "disabled"); | |
505 | break; | |
506 | default: | |
8e65ff28 AC |
507 | internal_error (__FILE__, __LINE__, |
508 | "show_mask_address: bad switch"); | |
4014092b AC |
509 | break; |
510 | } | |
511 | } | |
c906108c SS |
512 | |
513 | /* Should call_function allocate stack space for a struct return? */ | |
514 | int | |
fba45db2 | 515 | mips_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
516 | { |
517 | if (MIPS_EABI) | |
7a292a7a | 518 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
c906108c | 519 | else |
c5aa993b | 520 | return 1; /* Structures are returned by ref in extra arg0 */ |
c906108c SS |
521 | } |
522 | ||
523 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ | |
524 | ||
525 | static int | |
526 | pc_is_mips16 (bfd_vma memaddr) | |
527 | { | |
528 | struct minimal_symbol *sym; | |
529 | ||
530 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
531 | if (IS_MIPS16_ADDR (memaddr)) | |
532 | return 1; | |
533 | ||
534 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
535 | the high bit of the info field. Use this to decide if the function is | |
536 | MIPS16 or normal MIPS. */ | |
537 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
538 | if (sym) | |
539 | return MSYMBOL_IS_SPECIAL (sym); | |
540 | else | |
541 | return 0; | |
542 | } | |
543 | ||
6c997a34 AC |
544 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
545 | all registers should be sign extended for simplicity? */ | |
546 | ||
547 | static CORE_ADDR | |
548 | mips_read_pc (int pid) | |
549 | { | |
550 | return read_signed_register_pid (PC_REGNUM, pid); | |
551 | } | |
c906108c SS |
552 | |
553 | /* This returns the PC of the first inst after the prologue. If we can't | |
554 | find the prologue, then return 0. */ | |
555 | ||
556 | static CORE_ADDR | |
acdb74a0 AC |
557 | after_prologue (CORE_ADDR pc, |
558 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
559 | { |
560 | struct symtab_and_line sal; | |
561 | CORE_ADDR func_addr, func_end; | |
562 | ||
563 | if (!proc_desc) | |
564 | proc_desc = find_proc_desc (pc, NULL); | |
565 | ||
566 | if (proc_desc) | |
567 | { | |
568 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 569 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
570 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
571 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
572 | return 0; | |
573 | } | |
574 | ||
575 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
576 | return 0; /* Unknown */ | |
577 | ||
578 | sal = find_pc_line (func_addr, 0); | |
579 | ||
580 | if (sal.end < func_end) | |
581 | return sal.end; | |
582 | ||
583 | /* The line after the prologue is after the end of the function. In this | |
584 | case, tell the caller to find the prologue the hard way. */ | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
590 | set the appropriate bit in the general register mask or float register mask | |
591 | to indicate which register is saved. This is a helper function | |
592 | for mips_find_saved_regs. */ | |
593 | ||
594 | static void | |
acdb74a0 AC |
595 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
596 | unsigned long *float_mask) | |
c906108c SS |
597 | { |
598 | int reg; | |
599 | ||
600 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
601 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
602 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
603 | { | |
604 | /* It might be possible to use the instruction to | |
c5aa993b JM |
605 | find the offset, rather than the code below which |
606 | is based on things being in a certain order in the | |
607 | frame, but figuring out what the instruction's offset | |
608 | is relative to might be a little tricky. */ | |
c906108c SS |
609 | reg = (inst & 0x001f0000) >> 16; |
610 | *gen_mask |= (1 << reg); | |
611 | } | |
612 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
613 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
614 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
615 | |
616 | { | |
617 | reg = ((inst & 0x001f0000) >> 16); | |
618 | *float_mask |= (1 << reg); | |
619 | } | |
620 | } | |
621 | ||
622 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
623 | set the appropriate bit in the general register or float register mask | |
624 | to indicate which register is saved. This is a helper function | |
625 | for mips_find_saved_regs. */ | |
626 | ||
627 | static void | |
acdb74a0 | 628 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 629 | { |
c5aa993b | 630 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
631 | { |
632 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
633 | *gen_mask |= (1 << reg); | |
634 | } | |
c5aa993b | 635 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
636 | { |
637 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
638 | *gen_mask |= (1 << reg); | |
639 | } | |
c5aa993b | 640 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
641 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
642 | *gen_mask |= (1 << RA_REGNUM); | |
643 | } | |
644 | ||
645 | ||
646 | /* Fetch and return instruction from the specified location. If the PC | |
647 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
648 | ||
649 | static t_inst | |
acdb74a0 | 650 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
651 | { |
652 | char buf[MIPS_INSTLEN]; | |
653 | int instlen; | |
654 | int status; | |
655 | ||
656 | if (pc_is_mips16 (addr)) | |
657 | { | |
658 | instlen = MIPS16_INSTLEN; | |
659 | addr = UNMAKE_MIPS16_ADDR (addr); | |
660 | } | |
661 | else | |
c5aa993b | 662 | instlen = MIPS_INSTLEN; |
c906108c SS |
663 | status = read_memory_nobpt (addr, buf, instlen); |
664 | if (status) | |
665 | memory_error (status, addr); | |
666 | return extract_unsigned_integer (buf, instlen); | |
667 | } | |
668 | ||
669 | ||
670 | /* These the fields of 32 bit mips instructions */ | |
671 | #define mips32_op(x) (x >> 25) | |
672 | #define itype_op(x) (x >> 25) | |
673 | #define itype_rs(x) ((x >> 21)& 0x1f) | |
674 | #define itype_rt(x) ((x >> 16) & 0x1f) | |
675 | #define itype_immediate(x) ( x & 0xffff) | |
676 | ||
677 | #define jtype_op(x) (x >> 25) | |
678 | #define jtype_target(x) ( x & 0x03fffff) | |
679 | ||
680 | #define rtype_op(x) (x >>25) | |
681 | #define rtype_rs(x) ((x>>21) & 0x1f) | |
682 | #define rtype_rt(x) ((x>>16) & 0x1f) | |
c5aa993b | 683 | #define rtype_rd(x) ((x>>11) & 0x1f) |
c906108c SS |
684 | #define rtype_shamt(x) ((x>>6) & 0x1f) |
685 | #define rtype_funct(x) (x & 0x3f ) | |
686 | ||
687 | static CORE_ADDR | |
c5aa993b JM |
688 | mips32_relative_offset (unsigned long inst) |
689 | { | |
690 | long x; | |
691 | x = itype_immediate (inst); | |
692 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 693 | { |
c5aa993b | 694 | x |= 0xffff0000; /* sign extension */ |
c906108c | 695 | } |
c5aa993b JM |
696 | x = x << 2; |
697 | return x; | |
c906108c SS |
698 | } |
699 | ||
700 | /* Determine whate to set a single step breakpoint while considering | |
701 | branch prediction */ | |
702 | CORE_ADDR | |
c5aa993b JM |
703 | mips32_next_pc (CORE_ADDR pc) |
704 | { | |
705 | unsigned long inst; | |
706 | int op; | |
707 | inst = mips_fetch_instruction (pc); | |
708 | if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */ | |
709 | { | |
710 | if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */ | |
711 | { | |
712 | op = ((inst >> 25) & 0x03); | |
c906108c SS |
713 | switch (op) |
714 | { | |
c5aa993b JM |
715 | case 0: |
716 | goto equal_branch; /* BEQL */ | |
717 | case 1: | |
718 | goto neq_branch; /* BNEZ */ | |
719 | case 2: | |
720 | goto less_branch; /* BLEZ */ | |
721 | case 3: | |
722 | goto greater_branch; /* BGTZ */ | |
723 | default: | |
724 | pc += 4; | |
c906108c SS |
725 | } |
726 | } | |
c5aa993b JM |
727 | else |
728 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
729 | } |
730 | else | |
c5aa993b JM |
731 | { /* This gets way messy */ |
732 | ||
c906108c | 733 | /* Further subdivide into SPECIAL, REGIMM and other */ |
c5aa993b | 734 | switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */ |
c906108c | 735 | { |
c5aa993b JM |
736 | case 0: /* SPECIAL */ |
737 | op = rtype_funct (inst); | |
738 | switch (op) | |
739 | { | |
740 | case 8: /* JR */ | |
741 | case 9: /* JALR */ | |
6c997a34 AC |
742 | /* Set PC to that address */ |
743 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
744 | break; |
745 | default: | |
746 | pc += 4; | |
747 | } | |
748 | ||
749 | break; /* end special */ | |
750 | case 1: /* REGIMM */ | |
c906108c | 751 | { |
c5aa993b JM |
752 | op = jtype_op (inst); /* branch condition */ |
753 | switch (jtype_op (inst)) | |
c906108c | 754 | { |
c5aa993b JM |
755 | case 0: /* BLTZ */ |
756 | case 2: /* BLTXL */ | |
757 | case 16: /* BLTZALL */ | |
758 | case 18: /* BLTZALL */ | |
c906108c | 759 | less_branch: |
6c997a34 | 760 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
761 | pc += mips32_relative_offset (inst) + 4; |
762 | else | |
763 | pc += 8; /* after the delay slot */ | |
764 | break; | |
765 | case 1: /* GEZ */ | |
766 | case 3: /* BGEZL */ | |
767 | case 17: /* BGEZAL */ | |
768 | case 19: /* BGEZALL */ | |
c906108c | 769 | greater_equal_branch: |
6c997a34 | 770 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
771 | pc += mips32_relative_offset (inst) + 4; |
772 | else | |
773 | pc += 8; /* after the delay slot */ | |
774 | break; | |
775 | /* All of the other intructions in the REGIMM catagory */ | |
776 | default: | |
777 | pc += 4; | |
c906108c SS |
778 | } |
779 | } | |
c5aa993b JM |
780 | break; /* end REGIMM */ |
781 | case 2: /* J */ | |
782 | case 3: /* JAL */ | |
783 | { | |
784 | unsigned long reg; | |
785 | reg = jtype_target (inst) << 2; | |
786 | pc = reg + ((pc + 4) & 0xf0000000); | |
c906108c SS |
787 | /* Whats this mysterious 0xf000000 adjustment ??? */ |
788 | } | |
c5aa993b JM |
789 | break; |
790 | /* FIXME case JALX : */ | |
791 | { | |
792 | unsigned long reg; | |
793 | reg = jtype_target (inst) << 2; | |
794 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
795 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
796 | } | |
c5aa993b JM |
797 | break; /* The new PC will be alternate mode */ |
798 | case 4: /* BEQ , BEQL */ | |
799 | equal_branch: | |
6c997a34 AC |
800 | if (read_signed_register (itype_rs (inst)) == |
801 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
802 | pc += mips32_relative_offset (inst) + 4; |
803 | else | |
804 | pc += 8; | |
805 | break; | |
806 | case 5: /* BNE , BNEL */ | |
807 | neq_branch: | |
6c997a34 AC |
808 | if (read_signed_register (itype_rs (inst)) != |
809 | read_signed_register (itype_rs (inst))) | |
c5aa993b JM |
810 | pc += mips32_relative_offset (inst) + 4; |
811 | else | |
812 | pc += 8; | |
813 | break; | |
814 | case 6: /* BLEZ , BLEZL */ | |
c906108c | 815 | less_zero_branch: |
6c997a34 | 816 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
817 | pc += mips32_relative_offset (inst) + 4; |
818 | else | |
819 | pc += 8; | |
820 | break; | |
821 | case 7: | |
822 | greater_branch: /* BGTZ BGTZL */ | |
6c997a34 | 823 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
824 | pc += mips32_relative_offset (inst) + 4; |
825 | else | |
826 | pc += 8; | |
827 | break; | |
828 | default: | |
829 | pc += 8; | |
830 | } /* switch */ | |
831 | } /* else */ | |
832 | return pc; | |
833 | } /* mips32_next_pc */ | |
c906108c SS |
834 | |
835 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 836 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
837 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
838 | We dont want to set a single step instruction on the extend instruction | |
839 | either. | |
c5aa993b | 840 | */ |
c906108c SS |
841 | |
842 | /* Lots of mips16 instruction formats */ | |
843 | /* Predicting jumps requires itype,ritype,i8type | |
844 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 845 | */ |
c906108c SS |
846 | enum mips16_inst_fmts |
847 | { | |
c5aa993b JM |
848 | itype, /* 0 immediate 5,10 */ |
849 | ritype, /* 1 5,3,8 */ | |
850 | rrtype, /* 2 5,3,3,5 */ | |
851 | rritype, /* 3 5,3,3,5 */ | |
852 | rrrtype, /* 4 5,3,3,3,2 */ | |
853 | rriatype, /* 5 5,3,3,1,4 */ | |
854 | shifttype, /* 6 5,3,3,3,2 */ | |
855 | i8type, /* 7 5,3,8 */ | |
856 | i8movtype, /* 8 5,3,3,5 */ | |
857 | i8mov32rtype, /* 9 5,3,5,3 */ | |
858 | i64type, /* 10 5,3,8 */ | |
859 | ri64type, /* 11 5,3,3,5 */ | |
860 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
861 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
862 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
863 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
864 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
865 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
866 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
867 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
868 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
869 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
870 | }; | |
12f02c2a AC |
871 | /* I am heaping all the fields of the formats into one structure and |
872 | then, only the fields which are involved in instruction extension */ | |
c906108c | 873 | struct upk_mips16 |
c5aa993b | 874 | { |
12f02c2a | 875 | CORE_ADDR offset; |
c5aa993b JM |
876 | unsigned int regx; /* Function in i8 type */ |
877 | unsigned int regy; | |
878 | }; | |
c906108c SS |
879 | |
880 | ||
12f02c2a AC |
881 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
882 | for the bits which make up the immediatate extension. */ | |
c906108c | 883 | |
12f02c2a AC |
884 | static CORE_ADDR |
885 | extended_offset (unsigned int extension) | |
c906108c | 886 | { |
12f02c2a | 887 | CORE_ADDR value; |
c5aa993b JM |
888 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
889 | value = value << 6; | |
890 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
891 | value = value << 5; | |
892 | value |= extension & 0x01f; /* extract 4:0 */ | |
893 | return value; | |
c906108c SS |
894 | } |
895 | ||
896 | /* Only call this function if you know that this is an extendable | |
897 | instruction, It wont malfunction, but why make excess remote memory references? | |
898 | If the immediate operands get sign extended or somthing, do it after | |
899 | the extension is performed. | |
c5aa993b | 900 | */ |
c906108c SS |
901 | /* FIXME: Every one of these cases needs to worry about sign extension |
902 | when the offset is to be used in relative addressing */ | |
903 | ||
904 | ||
12f02c2a | 905 | static unsigned int |
c5aa993b | 906 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 907 | { |
c5aa993b JM |
908 | char buf[8]; |
909 | pc &= 0xfffffffe; /* clear the low order bit */ | |
910 | target_read_memory (pc, buf, 2); | |
911 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
912 | } |
913 | ||
914 | static void | |
c5aa993b | 915 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
916 | unsigned int extension, |
917 | unsigned int inst, | |
918 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 919 | struct upk_mips16 *upk) |
c906108c | 920 | { |
12f02c2a AC |
921 | CORE_ADDR offset; |
922 | int regx; | |
923 | int regy; | |
924 | switch (insn_format) | |
c906108c | 925 | { |
c5aa993b | 926 | case itype: |
c906108c | 927 | { |
12f02c2a AC |
928 | CORE_ADDR value; |
929 | if (extension) | |
c5aa993b JM |
930 | { |
931 | value = extended_offset (extension); | |
932 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 933 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
934 | } |
935 | else | |
c5aa993b | 936 | { |
12f02c2a | 937 | value = inst & 0x7ff; |
c5aa993b | 938 | /* FIXME : Consider sign extension */ |
c906108c | 939 | } |
12f02c2a AC |
940 | offset = value; |
941 | regx = -1; | |
942 | regy = -1; | |
c906108c | 943 | } |
c5aa993b JM |
944 | break; |
945 | case ritype: | |
946 | case i8type: | |
947 | { /* A register identifier and an offset */ | |
c906108c SS |
948 | /* Most of the fields are the same as I type but the |
949 | immediate value is of a different length */ | |
12f02c2a AC |
950 | CORE_ADDR value; |
951 | if (extension) | |
c906108c | 952 | { |
c5aa993b JM |
953 | value = extended_offset (extension); |
954 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
955 | value |= inst & 0xff; /* eleven bits from instruction */ |
956 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
957 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
958 | { | |
959 | value &= ~0x3fff; /* remove the sign bit */ | |
960 | value = -value; | |
c906108c SS |
961 | } |
962 | } | |
c5aa993b JM |
963 | else |
964 | { | |
12f02c2a AC |
965 | value = inst & 0xff; /* 8 bits */ |
966 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
967 | /* FIXME: Do sign extension , this format needs it */ |
968 | if (value & 0x80) /* THIS CONFUSES ME */ | |
969 | { | |
970 | value &= 0xef; /* remove the sign bit */ | |
971 | value = -value; | |
972 | } | |
c5aa993b | 973 | } |
12f02c2a AC |
974 | offset = value; |
975 | regy = -1; | |
c5aa993b | 976 | break; |
c906108c | 977 | } |
c5aa993b | 978 | case jalxtype: |
c906108c | 979 | { |
c5aa993b | 980 | unsigned long value; |
12f02c2a AC |
981 | unsigned int nexthalf; |
982 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
983 | value = value << 16; |
984 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
985 | value |= nexthalf; | |
12f02c2a AC |
986 | offset = value; |
987 | regx = -1; | |
988 | regy = -1; | |
c5aa993b | 989 | break; |
c906108c SS |
990 | } |
991 | default: | |
8e65ff28 AC |
992 | internal_error (__FILE__, __LINE__, |
993 | "bad switch"); | |
c906108c | 994 | } |
12f02c2a AC |
995 | upk->offset = offset; |
996 | upk->regx = regx; | |
997 | upk->regy = regy; | |
c906108c SS |
998 | } |
999 | ||
1000 | ||
c5aa993b JM |
1001 | static CORE_ADDR |
1002 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1003 | { |
c5aa993b JM |
1004 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
1005 | ||
c906108c SS |
1006 | } |
1007 | ||
12f02c2a AC |
1008 | static CORE_ADDR |
1009 | extended_mips16_next_pc (CORE_ADDR pc, | |
1010 | unsigned int extension, | |
1011 | unsigned int insn) | |
c906108c | 1012 | { |
12f02c2a AC |
1013 | int op = (insn >> 11); |
1014 | switch (op) | |
c906108c | 1015 | { |
12f02c2a AC |
1016 | case 2: /* Branch */ |
1017 | { | |
1018 | CORE_ADDR offset; | |
1019 | struct upk_mips16 upk; | |
1020 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1021 | offset = upk.offset; | |
1022 | if (offset & 0x800) | |
1023 | { | |
1024 | offset &= 0xeff; | |
1025 | offset = -offset; | |
1026 | } | |
1027 | pc += (offset << 1) + 2; | |
1028 | break; | |
1029 | } | |
1030 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1031 | { | |
1032 | struct upk_mips16 upk; | |
1033 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1034 | pc = add_offset_16 (pc, upk.offset); | |
1035 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1036 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1037 | else | |
1038 | pc |= 0x01; | |
1039 | break; | |
1040 | } | |
1041 | case 4: /* beqz */ | |
1042 | { | |
1043 | struct upk_mips16 upk; | |
1044 | int reg; | |
1045 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1046 | reg = read_signed_register (upk.regx); | |
1047 | if (reg == 0) | |
1048 | pc += (upk.offset << 1) + 2; | |
1049 | else | |
1050 | pc += 2; | |
1051 | break; | |
1052 | } | |
1053 | case 5: /* bnez */ | |
1054 | { | |
1055 | struct upk_mips16 upk; | |
1056 | int reg; | |
1057 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1058 | reg = read_signed_register (upk.regx); | |
1059 | if (reg != 0) | |
1060 | pc += (upk.offset << 1) + 2; | |
1061 | else | |
1062 | pc += 2; | |
1063 | break; | |
1064 | } | |
1065 | case 12: /* I8 Formats btez btnez */ | |
1066 | { | |
1067 | struct upk_mips16 upk; | |
1068 | int reg; | |
1069 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1070 | /* upk.regx contains the opcode */ | |
1071 | reg = read_signed_register (24); /* Test register is 24 */ | |
1072 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1073 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1074 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1075 | pc += (upk.offset << 1) + 2; | |
1076 | else | |
1077 | pc += 2; | |
1078 | break; | |
1079 | } | |
1080 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1081 | { | |
1082 | struct upk_mips16 upk; | |
1083 | /* upk.fmt = rrtype; */ | |
1084 | op = insn & 0x1f; | |
1085 | if (op == 0) | |
c5aa993b | 1086 | { |
12f02c2a AC |
1087 | int reg; |
1088 | upk.regx = (insn >> 8) & 0x07; | |
1089 | upk.regy = (insn >> 5) & 0x07; | |
1090 | switch (upk.regy) | |
c5aa993b | 1091 | { |
12f02c2a AC |
1092 | case 0: |
1093 | reg = upk.regx; | |
1094 | break; | |
1095 | case 1: | |
1096 | reg = 31; | |
1097 | break; /* Function return instruction */ | |
1098 | case 2: | |
1099 | reg = upk.regx; | |
1100 | break; | |
1101 | default: | |
1102 | reg = 31; | |
1103 | break; /* BOGUS Guess */ | |
c906108c | 1104 | } |
12f02c2a | 1105 | pc = read_signed_register (reg); |
c906108c | 1106 | } |
12f02c2a | 1107 | else |
c5aa993b | 1108 | pc += 2; |
12f02c2a AC |
1109 | break; |
1110 | } | |
1111 | case 30: | |
1112 | /* This is an instruction extension. Fetch the real instruction | |
1113 | (which follows the extension) and decode things based on | |
1114 | that. */ | |
1115 | { | |
1116 | pc += 2; | |
1117 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1118 | break; | |
1119 | } | |
1120 | default: | |
1121 | { | |
1122 | pc += 2; | |
1123 | break; | |
1124 | } | |
c906108c | 1125 | } |
c5aa993b | 1126 | return pc; |
12f02c2a | 1127 | } |
c906108c | 1128 | |
12f02c2a AC |
1129 | CORE_ADDR |
1130 | mips16_next_pc (CORE_ADDR pc) | |
1131 | { | |
1132 | unsigned int insn = fetch_mips_16 (pc); | |
1133 | return extended_mips16_next_pc (pc, 0, insn); | |
1134 | } | |
1135 | ||
1136 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1137 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1138 | It works by decoding the current instruction and predicting where a |
1139 | branch will go. This isnt hard because all the data is available. | |
1140 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1141 | CORE_ADDR |
1142 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1143 | { |
c5aa993b JM |
1144 | if (pc & 0x01) |
1145 | return mips16_next_pc (pc); | |
1146 | else | |
1147 | return mips32_next_pc (pc); | |
12f02c2a | 1148 | } |
c906108c SS |
1149 | |
1150 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
1151 | NULL). */ | |
1152 | ||
1153 | void | |
acdb74a0 | 1154 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1155 | { |
1156 | int ireg; | |
1157 | CORE_ADDR reg_position; | |
1158 | /* r0 bit means kernel trap */ | |
1159 | int kernel_trap; | |
1160 | /* What registers have been saved? Bitmasks. */ | |
1161 | unsigned long gen_mask, float_mask; | |
1162 | mips_extra_func_info_t proc_desc; | |
1163 | t_inst inst; | |
1164 | ||
1165 | frame_saved_regs_zalloc (fci); | |
1166 | ||
1167 | /* If it is the frame for sigtramp, the saved registers are located | |
1168 | in a sigcontext structure somewhere on the stack. | |
1169 | If the stack layout for sigtramp changes we might have to change these | |
1170 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1171 | #ifndef SIGFRAME_BASE | |
1172 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1173 | above the sigtramp frame. */ | |
1174 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1175 | /* FIXME! Are these correct?? */ | |
1176 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1177 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1178 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1179 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1180 | #endif | |
1181 | #ifndef SIGFRAME_REG_SIZE | |
1182 | /* FIXME! Is this correct?? */ | |
1183 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1184 | #endif | |
1185 | if (fci->signal_handler_caller) | |
1186 | { | |
1187 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1188 | { | |
c5aa993b JM |
1189 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1190 | + ireg * SIGFRAME_REG_SIZE; | |
1191 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1192 | } |
1193 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1194 | { | |
c5aa993b JM |
1195 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1196 | + ireg * SIGFRAME_REG_SIZE; | |
1197 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1198 | } |
1199 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1200 | return; | |
1201 | } | |
1202 | ||
cce74817 | 1203 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1204 | if (proc_desc == NULL) |
1205 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1206 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1207 | and set the saved_regs right away. */ | |
1208 | return; | |
1209 | ||
c5aa993b JM |
1210 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1211 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1212 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1213 | |
c5aa993b JM |
1214 | if ( /* In any frame other than the innermost or a frame interrupted by |
1215 | a signal, we assume that all registers have been saved. | |
1216 | This assumes that all register saves in a function happen before | |
1217 | the first function call. */ | |
1218 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1219 | |
c5aa993b JM |
1220 | /* In a dummy frame we know exactly where things are saved. */ |
1221 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1222 | |
c5aa993b JM |
1223 | /* Don't bother unless we are inside a function prologue. Outside the |
1224 | prologue, we know where everything is. */ | |
c906108c | 1225 | |
c5aa993b | 1226 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1227 | |
c5aa993b JM |
1228 | /* Not sure exactly what kernel_trap means, but if it means |
1229 | the kernel saves the registers without a prologue doing it, | |
1230 | we better not examine the prologue to see whether registers | |
1231 | have been saved yet. */ | |
1232 | && !kernel_trap) | |
c906108c SS |
1233 | { |
1234 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1235 | claims are saved have been saved yet. */ |
c906108c SS |
1236 | |
1237 | CORE_ADDR addr; | |
1238 | ||
1239 | /* Bitmasks; set if we have found a save for the register. */ | |
1240 | unsigned long gen_save_found = 0; | |
1241 | unsigned long float_save_found = 0; | |
1242 | int instlen; | |
1243 | ||
1244 | /* If the address is odd, assume this is MIPS16 code. */ | |
1245 | addr = PROC_LOW_ADDR (proc_desc); | |
1246 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1247 | ||
1248 | /* Scan through this function's instructions preceding the current | |
1249 | PC, and look for those that save registers. */ | |
1250 | while (addr < fci->pc) | |
1251 | { | |
1252 | inst = mips_fetch_instruction (addr); | |
1253 | if (pc_is_mips16 (addr)) | |
1254 | mips16_decode_reg_save (inst, &gen_save_found); | |
1255 | else | |
1256 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1257 | addr += instlen; | |
1258 | } | |
1259 | gen_mask = gen_save_found; | |
1260 | float_mask = float_save_found; | |
1261 | } | |
1262 | ||
1263 | /* Fill in the offsets for the registers which gen_mask says | |
1264 | were saved. */ | |
1265 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1266 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1267 | if (gen_mask & 0x80000000) |
1268 | { | |
1269 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1270 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1271 | } |
1272 | ||
1273 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1274 | of that normally used by gcc. Therefore, we have to fetch the first | |
1275 | instruction of the function, and if it's an entry instruction that | |
1276 | saves $s0 or $s1, correct their saved addresses. */ | |
1277 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1278 | { | |
1279 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1280 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1281 | { |
1282 | int reg; | |
1283 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1284 | |
c906108c SS |
1285 | /* Check if the ra register was pushed on the stack. */ |
1286 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1287 | if (inst & 0x20) | |
7a292a7a | 1288 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1289 | |
1290 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1291 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1292 | { |
1293 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1294 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1295 | } |
1296 | } | |
1297 | } | |
1298 | ||
1299 | /* Fill in the offsets for the registers which float_mask says | |
1300 | were saved. */ | |
1301 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1302 | ||
1303 | /* The freg_offset points to where the first *double* register | |
1304 | is saved. So skip to the high-order word. */ | |
c5aa993b | 1305 | if (!GDB_TARGET_IS_MIPS64) |
7a292a7a | 1306 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1307 | |
1308 | /* Fill in the offsets for the float registers which float_mask says | |
1309 | were saved. */ | |
c5aa993b | 1310 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1311 | if (float_mask & 0x80000000) |
1312 | { | |
c5aa993b | 1313 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1314 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1315 | } |
1316 | ||
1317 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1318 | } | |
1319 | ||
1320 | static CORE_ADDR | |
acdb74a0 | 1321 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c SS |
1322 | { |
1323 | for (; fi; fi = fi->next) | |
1324 | { | |
1325 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1326 | if it is a signal handler frame. */ |
c906108c SS |
1327 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1328 | return fi->frame; | |
1329 | else | |
1330 | { | |
1331 | if (fi->saved_regs == NULL) | |
1332 | mips_find_saved_regs (fi); | |
1333 | if (fi->saved_regs[regno]) | |
2acceee2 | 1334 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1335 | } |
1336 | } | |
6c997a34 | 1337 | return read_signed_register (regno); |
c906108c SS |
1338 | } |
1339 | ||
1340 | /* mips_addr_bits_remove - remove useless address bits */ | |
1341 | ||
1342 | CORE_ADDR | |
acdb74a0 | 1343 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1344 | { |
5213ab06 AC |
1345 | if (GDB_TARGET_IS_MIPS64) |
1346 | { | |
4014092b | 1347 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1348 | { |
1349 | /* This hack is a work-around for existing boards using | |
1350 | PMON, the simulator, and any other 64-bit targets that | |
1351 | doesn't have true 64-bit addressing. On these targets, | |
1352 | the upper 32 bits of addresses are ignored by the | |
1353 | hardware. Thus, the PC or SP are likely to have been | |
1354 | sign extended to all 1s by instruction sequences that | |
1355 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1356 | code that loads an address is this: |
1357 | lui $r2, <upper 16 bits> | |
1358 | ori $r2, <lower 16 bits> | |
1359 | But the lui sign-extends the value such that the upper 32 | |
1360 | bits may be all 1s. The workaround is simply to mask off | |
1361 | these bits. In the future, gcc may be changed to support | |
1362 | true 64-bit addressing, and this masking will have to be | |
1363 | disabled. */ | |
5213ab06 AC |
1364 | addr &= (CORE_ADDR) 0xffffffff; |
1365 | } | |
1366 | } | |
4014092b | 1367 | else if (mips_mask_address_p ()) |
5213ab06 | 1368 | { |
4014092b AC |
1369 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1370 | masking off bits, instead, the actual target should be asking | |
1371 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1372 | /* Even when GDB is configured for some 32-bit targets |
1373 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1374 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1375 | useless bits from addresses. */ | |
c5aa993b | 1376 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1377 | } |
c906108c SS |
1378 | return addr; |
1379 | } | |
1380 | ||
1381 | void | |
acdb74a0 | 1382 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1383 | { |
1384 | CORE_ADDR pc, tmp; | |
1385 | ||
1386 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1387 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
c906108c | 1388 | tmp = mips_skip_stub (pc); |
c5aa993b | 1389 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1390 | } |
1391 | ||
1392 | ||
1393 | CORE_ADDR | |
acdb74a0 | 1394 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1395 | { |
1396 | CORE_ADDR saved_pc; | |
cce74817 | 1397 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1398 | /* We have to get the saved pc from the sigcontext |
1399 | if it is a signal handler frame. */ | |
1400 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1401 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1402 | |
c5aa993b | 1403 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1404 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1405 | else |
7a292a7a | 1406 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1407 | |
1408 | return ADDR_BITS_REMOVE (saved_pc); | |
1409 | } | |
1410 | ||
1411 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1412 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1413 | |
1414 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1415 | has already been set for this register, do nothing; this way we will | |
1416 | only recognize the first save of a given register in a function prologue. | |
1417 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1418 | ||
1419 | static void | |
acdb74a0 | 1420 | set_reg_offset (int regno, CORE_ADDR offset) |
c906108c | 1421 | { |
cce74817 JM |
1422 | if (temp_saved_regs[regno] == 0) |
1423 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1424 | } |
1425 | ||
1426 | ||
1427 | /* Test whether the PC points to the return instruction at the | |
1428 | end of a function. */ | |
1429 | ||
c5aa993b | 1430 | static int |
acdb74a0 | 1431 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1432 | { |
1433 | if (pc_is_mips16 (pc)) | |
1434 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1435 | generates a "jr $ra"; other times it generates code to load | |
1436 | the return address from the stack to an accessible register (such | |
1437 | as $a3), then a "jr" using that register. This second case | |
1438 | is almost impossible to distinguish from an indirect jump | |
1439 | used for switch statements, so we don't even try. */ | |
1440 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1441 | else | |
1442 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1443 | } | |
1444 | ||
1445 | ||
1446 | /* This fencepost looks highly suspicious to me. Removing it also | |
1447 | seems suspicious as it could affect remote debugging across serial | |
1448 | lines. */ | |
1449 | ||
1450 | static CORE_ADDR | |
acdb74a0 | 1451 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1452 | { |
c5aa993b JM |
1453 | CORE_ADDR start_pc; |
1454 | CORE_ADDR fence; | |
1455 | int instlen; | |
1456 | int seen_adjsp = 0; | |
c906108c | 1457 | |
c5aa993b JM |
1458 | pc = ADDR_BITS_REMOVE (pc); |
1459 | start_pc = pc; | |
1460 | fence = start_pc - heuristic_fence_post; | |
1461 | if (start_pc == 0) | |
1462 | return 0; | |
c906108c | 1463 | |
c5aa993b JM |
1464 | if (heuristic_fence_post == UINT_MAX |
1465 | || fence < VM_MIN_ADDRESS) | |
1466 | fence = VM_MIN_ADDRESS; | |
c906108c | 1467 | |
c5aa993b | 1468 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1469 | |
c5aa993b JM |
1470 | /* search back for previous return */ |
1471 | for (start_pc -= instlen;; start_pc -= instlen) | |
1472 | if (start_pc < fence) | |
1473 | { | |
1474 | /* It's not clear to me why we reach this point when | |
1475 | stop_soon_quietly, but with this test, at least we | |
1476 | don't print out warnings for every child forked (eg, on | |
1477 | decstation). 22apr93 rich@cygnus.com. */ | |
1478 | if (!stop_soon_quietly) | |
c906108c | 1479 | { |
c5aa993b JM |
1480 | static int blurb_printed = 0; |
1481 | ||
1482 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1483 | paddr_nz (pc)); | |
1484 | ||
1485 | if (!blurb_printed) | |
c906108c | 1486 | { |
c5aa993b JM |
1487 | /* This actually happens frequently in embedded |
1488 | development, when you first connect to a board | |
1489 | and your stack pointer and pc are nowhere in | |
1490 | particular. This message needs to give people | |
1491 | in that situation enough information to | |
1492 | determine that it's no big deal. */ | |
1493 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1494 | GDB is unable to find the start of the function at 0x%s\n\ |
1495 | and thus can't determine the size of that function's stack frame.\n\ | |
1496 | This means that GDB may be unable to access that stack frame, or\n\ | |
1497 | the frames below it.\n\ | |
1498 | This problem is most likely caused by an invalid program counter or\n\ | |
1499 | stack pointer.\n\ | |
1500 | However, if you think GDB should simply search farther back\n\ | |
1501 | from 0x%s for code which looks like the beginning of a\n\ | |
1502 | function, you can increase the range of the search using the `set\n\ | |
1503 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1504 | paddr_nz (pc), paddr_nz (pc)); |
1505 | blurb_printed = 1; | |
c906108c | 1506 | } |
c906108c SS |
1507 | } |
1508 | ||
c5aa993b JM |
1509 | return 0; |
1510 | } | |
1511 | else if (pc_is_mips16 (start_pc)) | |
1512 | { | |
1513 | unsigned short inst; | |
1514 | ||
1515 | /* On MIPS16, any one of the following is likely to be the | |
1516 | start of a function: | |
1517 | entry | |
1518 | addiu sp,-n | |
1519 | daddiu sp,-n | |
1520 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1521 | inst = mips_fetch_instruction (start_pc); | |
1522 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1523 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1524 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1525 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1526 | break; | |
1527 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1528 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1529 | seen_adjsp = 1; | |
1530 | else | |
1531 | seen_adjsp = 0; | |
1532 | } | |
1533 | else if (mips_about_to_return (start_pc)) | |
1534 | { | |
1535 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1536 | break; | |
1537 | } | |
1538 | ||
c5aa993b | 1539 | return start_pc; |
c906108c SS |
1540 | } |
1541 | ||
1542 | /* Fetch the immediate value from a MIPS16 instruction. | |
1543 | If the previous instruction was an EXTEND, use it to extend | |
1544 | the upper bits of the immediate value. This is a helper function | |
1545 | for mips16_heuristic_proc_desc. */ | |
1546 | ||
1547 | static int | |
acdb74a0 AC |
1548 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1549 | unsigned short inst, /* current instruction */ | |
1550 | int nbits, /* number of bits in imm field */ | |
1551 | int scale, /* scale factor to be applied to imm */ | |
1552 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1553 | { |
1554 | int offset; | |
1555 | ||
1556 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1557 | { | |
1558 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1559 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1560 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1561 | return offset | (inst & 0x1f); | |
1562 | } | |
1563 | else | |
1564 | { | |
1565 | int max_imm = 1 << nbits; | |
1566 | int mask = max_imm - 1; | |
1567 | int sign_bit = max_imm >> 1; | |
1568 | ||
1569 | offset = inst & mask; | |
1570 | if (is_signed && (offset & sign_bit)) | |
1571 | offset = 0 - (max_imm - offset); | |
1572 | return offset * scale; | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | ||
1577 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1578 | stream from start_pc to limit_pc. */ | |
1579 | ||
1580 | static void | |
acdb74a0 AC |
1581 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1582 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1583 | { |
1584 | CORE_ADDR cur_pc; | |
1585 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1586 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1587 | unsigned inst = 0; /* current instruction */ | |
1588 | unsigned entry_inst = 0; /* the entry instruction */ | |
1589 | int reg, offset; | |
1590 | ||
c5aa993b JM |
1591 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1592 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1593 | |
1594 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1595 | { | |
1596 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1597 | the immediate offset extension from it in mips16_get_imm. */ | |
1598 | prev_inst = inst; | |
1599 | ||
1600 | /* Fetch and decode the instruction. */ | |
1601 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1602 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1603 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1604 | { | |
1605 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1606 | if (offset < 0) /* negative stack adjustment? */ |
1607 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1608 | else |
1609 | /* Exit loop if a positive stack adjustment is found, which | |
1610 | usually means that the stack cleanup code in the function | |
1611 | epilogue is reached. */ | |
1612 | break; | |
1613 | } | |
1614 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1615 | { | |
1616 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1617 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1618 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1619 | set_reg_offset (reg, sp + offset); |
1620 | } | |
1621 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1622 | { | |
1623 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1624 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1625 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1626 | set_reg_offset (reg, sp + offset); |
1627 | } | |
1628 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1629 | { | |
1630 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1631 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1632 | set_reg_offset (RA_REGNUM, sp + offset); |
1633 | } | |
1634 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1635 | { | |
1636 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1637 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1638 | set_reg_offset (RA_REGNUM, sp + offset); |
1639 | } | |
c5aa993b | 1640 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1641 | { |
1642 | frame_addr = sp; | |
1643 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1644 | } | |
1645 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1646 | { | |
1647 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1648 | frame_addr = sp + offset; | |
1649 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1650 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1651 | } | |
1652 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1653 | { | |
1654 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1655 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1656 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1657 | set_reg_offset (reg, frame_addr + offset); |
1658 | } | |
1659 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1660 | { | |
1661 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1662 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1663 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1664 | set_reg_offset (reg, frame_addr + offset); |
1665 | } | |
c5aa993b JM |
1666 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1667 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1668 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1669 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1670 | } |
1671 | ||
c5aa993b JM |
1672 | /* The entry instruction is typically the first instruction in a function, |
1673 | and it stores registers at offsets relative to the value of the old SP | |
1674 | (before the prologue). But the value of the sp parameter to this | |
1675 | function is the new SP (after the prologue has been executed). So we | |
1676 | can't calculate those offsets until we've seen the entire prologue, | |
1677 | and can calculate what the old SP must have been. */ | |
1678 | if (entry_inst != 0) | |
1679 | { | |
1680 | int areg_count = (entry_inst >> 8) & 7; | |
1681 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1682 | |
c5aa993b JM |
1683 | /* The entry instruction always subtracts 32 from the SP. */ |
1684 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1685 | |
c5aa993b JM |
1686 | /* Now we can calculate what the SP must have been at the |
1687 | start of the function prologue. */ | |
1688 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1689 | |
c5aa993b JM |
1690 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1691 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1692 | { | |
1693 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1694 | set_reg_offset (reg, sp + offset); | |
1695 | offset += MIPS_SAVED_REGSIZE; | |
1696 | } | |
c906108c | 1697 | |
c5aa993b JM |
1698 | /* Check if the ra register was pushed on the stack. */ |
1699 | offset = -4; | |
1700 | if (entry_inst & 0x20) | |
1701 | { | |
1702 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1703 | set_reg_offset (RA_REGNUM, sp + offset); | |
1704 | offset -= MIPS_SAVED_REGSIZE; | |
1705 | } | |
c906108c | 1706 | |
c5aa993b JM |
1707 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
1708 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1709 | { | |
1710 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1711 | set_reg_offset (reg, sp + offset); | |
1712 | offset -= MIPS_SAVED_REGSIZE; | |
1713 | } | |
1714 | } | |
c906108c SS |
1715 | } |
1716 | ||
1717 | static void | |
fba45db2 KB |
1718 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1719 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1720 | { |
1721 | CORE_ADDR cur_pc; | |
c5aa993b | 1722 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 1723 | restart: |
cce74817 | 1724 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 1725 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
1726 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
1727 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
1728 | { | |
1729 | unsigned long inst, high_word, low_word; | |
1730 | int reg; | |
1731 | ||
1732 | /* Fetch the instruction. */ | |
1733 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
1734 | ||
1735 | /* Save some code by pre-extracting some useful fields. */ | |
1736 | high_word = (inst >> 16) & 0xffff; | |
1737 | low_word = inst & 0xffff; | |
1738 | reg = high_word & 0x1f; | |
1739 | ||
c5aa993b | 1740 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
1741 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
1742 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1743 | { | |
1744 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 1745 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
1746 | else |
1747 | /* Exit loop if a positive stack adjustment is found, which | |
1748 | usually means that the stack cleanup code in the function | |
1749 | epilogue is reached. */ | |
1750 | break; | |
1751 | } | |
1752 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1753 | { | |
c5aa993b | 1754 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1755 | set_reg_offset (reg, sp + low_word); |
1756 | } | |
1757 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1758 | { | |
1759 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1760 | but the register size used is only 32 bits. Make the address | |
1761 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 1762 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1763 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
1764 | } | |
c5aa993b | 1765 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
1766 | { |
1767 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
1768 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
1769 | frame_addr = sp + low_word; | |
c906108c SS |
1770 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
1771 | { | |
1772 | unsigned alloca_adjust; | |
1773 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1774 | frame_addr = read_next_frame_reg (next_frame, 30); |
1775 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
1776 | if (alloca_adjust > 0) |
1777 | { | |
1778 | /* FP > SP + frame_size. This may be because | |
1779 | * of an alloca or somethings similar. | |
1780 | * Fix sp to "pre-alloca" value, and try again. | |
1781 | */ | |
1782 | sp += alloca_adjust; | |
1783 | goto restart; | |
1784 | } | |
1785 | } | |
1786 | } | |
c5aa993b JM |
1787 | /* move $30,$sp. With different versions of gas this will be either |
1788 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1789 | Accept any one of these. */ | |
c906108c SS |
1790 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
1791 | { | |
1792 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1793 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1794 | { | |
1795 | unsigned alloca_adjust; | |
1796 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1797 | frame_addr = read_next_frame_reg (next_frame, 30); |
1798 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
1799 | if (alloca_adjust > 0) |
1800 | { | |
1801 | /* FP > SP + frame_size. This may be because | |
1802 | * of an alloca or somethings similar. | |
1803 | * Fix sp to "pre-alloca" value, and try again. | |
1804 | */ | |
1805 | sp += alloca_adjust; | |
1806 | goto restart; | |
1807 | } | |
1808 | } | |
1809 | } | |
c5aa993b | 1810 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 1811 | { |
c5aa993b | 1812 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1813 | set_reg_offset (reg, frame_addr + low_word); |
1814 | } | |
1815 | } | |
1816 | } | |
1817 | ||
1818 | static mips_extra_func_info_t | |
acdb74a0 AC |
1819 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1820 | struct frame_info *next_frame) | |
c906108c SS |
1821 | { |
1822 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1823 | ||
c5aa993b JM |
1824 | if (start_pc == 0) |
1825 | return NULL; | |
1826 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 1827 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1828 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
1829 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
1830 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
1831 | ||
1832 | if (start_pc + 200 < limit_pc) | |
1833 | limit_pc = start_pc + 200; | |
1834 | if (pc_is_mips16 (start_pc)) | |
1835 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1836 | else | |
1837 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1838 | return &temp_proc_desc; | |
1839 | } | |
1840 | ||
1841 | static mips_extra_func_info_t | |
acdb74a0 | 1842 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
1843 | { |
1844 | CORE_ADDR startaddr; | |
1845 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 1846 | struct block *b = block_for_pc (pc); |
c906108c SS |
1847 | struct symbol *sym; |
1848 | ||
1849 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
1850 | if (addrptr) | |
1851 | *addrptr = startaddr; | |
1852 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) | |
1853 | sym = NULL; | |
1854 | else | |
1855 | { | |
1856 | if (startaddr > BLOCK_START (b)) | |
1857 | /* This is the "pathological" case referred to in a comment in | |
1858 | print_frame_info. It might be better to move this check into | |
1859 | symbol reading. */ | |
1860 | sym = NULL; | |
1861 | else | |
1862 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
1863 | } | |
1864 | ||
1865 | /* If we never found a PDR for this function in symbol reading, then | |
1866 | examine prologues to find the information. */ | |
1867 | if (sym) | |
1868 | { | |
1869 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
1870 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1871 | return NULL; | |
1872 | else | |
1873 | return proc_desc; | |
1874 | } | |
1875 | else | |
1876 | return NULL; | |
1877 | } | |
1878 | ||
1879 | ||
1880 | static mips_extra_func_info_t | |
acdb74a0 | 1881 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame) |
c906108c SS |
1882 | { |
1883 | mips_extra_func_info_t proc_desc; | |
1884 | CORE_ADDR startaddr; | |
1885 | ||
1886 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1887 | ||
1888 | if (proc_desc) | |
1889 | { | |
1890 | /* IF this is the topmost frame AND | |
1891 | * (this proc does not have debugging information OR | |
1892 | * the PC is in the procedure prologue) | |
1893 | * THEN create a "heuristic" proc_desc (by analyzing | |
1894 | * the actual code) to replace the "official" proc_desc. | |
1895 | */ | |
1896 | if (next_frame == NULL) | |
1897 | { | |
1898 | struct symtab_and_line val; | |
1899 | struct symbol *proc_symbol = | |
c5aa993b | 1900 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
1901 | |
1902 | if (proc_symbol) | |
1903 | { | |
1904 | val = find_pc_line (BLOCK_START | |
c5aa993b | 1905 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
1906 | 0); |
1907 | val.pc = val.end ? val.end : pc; | |
1908 | } | |
1909 | if (!proc_symbol || pc < val.pc) | |
1910 | { | |
1911 | mips_extra_func_info_t found_heuristic = | |
c5aa993b JM |
1912 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
1913 | pc, next_frame); | |
c906108c SS |
1914 | if (found_heuristic) |
1915 | proc_desc = found_heuristic; | |
1916 | } | |
1917 | } | |
1918 | } | |
1919 | else | |
1920 | { | |
1921 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
1922 | by procedure call dummys. However, the procedures being called ought |
1923 | to have their own proc_descs, and even if they don't, | |
1924 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
1925 | |
1926 | register struct linked_proc_info *link; | |
1927 | ||
1928 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
1929 | if (PROC_LOW_ADDR (&link->info) <= pc |
1930 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
1931 | return &link->info; |
1932 | ||
1933 | if (startaddr == 0) | |
1934 | startaddr = heuristic_proc_start (pc); | |
1935 | ||
1936 | proc_desc = | |
1937 | heuristic_proc_desc (startaddr, pc, next_frame); | |
1938 | } | |
1939 | return proc_desc; | |
1940 | } | |
1941 | ||
1942 | static CORE_ADDR | |
acdb74a0 AC |
1943 | get_frame_pointer (struct frame_info *frame, |
1944 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
1945 | { |
1946 | return ADDR_BITS_REMOVE ( | |
c5aa993b JM |
1947 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + |
1948 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
1949 | } |
1950 | ||
1951 | mips_extra_func_info_t cached_proc_desc; | |
1952 | ||
1953 | CORE_ADDR | |
acdb74a0 | 1954 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
1955 | { |
1956 | mips_extra_func_info_t proc_desc; | |
1957 | CORE_ADDR tmp; | |
c5aa993b | 1958 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
1959 | |
1960 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
1961 | return 0; | |
1962 | ||
1963 | /* Check if the PC is inside a call stub. If it is, fetch the | |
1964 | PC of the caller of that stub. */ | |
1965 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
1966 | saved_pc = tmp; | |
1967 | ||
1968 | /* Look up the procedure descriptor for this PC. */ | |
c5aa993b | 1969 | proc_desc = find_proc_desc (saved_pc, frame); |
c906108c SS |
1970 | if (!proc_desc) |
1971 | return 0; | |
1972 | ||
1973 | cached_proc_desc = proc_desc; | |
1974 | ||
1975 | /* If no frame pointer and frame size is zero, we must be at end | |
1976 | of stack (or otherwise hosed). If we don't check frame size, | |
1977 | we loop forever if we see a zero size frame. */ | |
1978 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
1979 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
c5aa993b JM |
1980 | /* The previous frame from a sigtramp frame might be frameless |
1981 | and have frame size zero. */ | |
c906108c SS |
1982 | && !frame->signal_handler_caller) |
1983 | return 0; | |
1984 | else | |
1985 | return get_frame_pointer (frame, proc_desc); | |
1986 | } | |
1987 | ||
1988 | void | |
acdb74a0 | 1989 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
1990 | { |
1991 | int regnum; | |
1992 | ||
1993 | /* Use proc_desc calculated in frame_chain */ | |
1994 | mips_extra_func_info_t proc_desc = | |
c5aa993b | 1995 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next); |
c906108c | 1996 | |
cce74817 JM |
1997 | fci->extra_info = (struct frame_extra_info *) |
1998 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1999 | ||
c906108c | 2000 | fci->saved_regs = NULL; |
cce74817 | 2001 | fci->extra_info->proc_desc = |
c906108c SS |
2002 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2003 | if (proc_desc) | |
2004 | { | |
2005 | /* Fixup frame-pointer - only needed for top frame */ | |
2006 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2007 | Get the value of the frame relative sp, procedure might have been |
2008 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2009 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2010 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2011 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2012 | else | |
2013 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2014 | ||
2015 | if (proc_desc == &temp_proc_desc) | |
2016 | { | |
2017 | char *name; | |
2018 | ||
2019 | /* Do not set the saved registers for a sigtramp frame, | |
2020 | mips_find_saved_registers will do that for us. | |
2021 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2022 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2023 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
2024 | if (!IN_SIGTRAMP (fci->pc, name)) |
2025 | { | |
c5aa993b | 2026 | frame_saved_regs_zalloc (fci); |
cce74817 | 2027 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2028 | fci->saved_regs[PC_REGNUM] |
2029 | = fci->saved_regs[RA_REGNUM]; | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2034 | /* assume we can't tell how many args for now */ |
2035 | fci->extra_info->num_args = -1; | |
c906108c SS |
2036 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2037 | { | |
c5aa993b | 2038 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2039 | { |
cce74817 | 2040 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2041 | break; |
2042 | } | |
c5aa993b | 2043 | } |
c906108c SS |
2044 | } |
2045 | } | |
2046 | ||
2047 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2048 | we basically have to look at symbol information for the function | |
2049 | that we stopped in, which tells us *which* register (if any) is | |
2050 | the base of the frame pointer, and what offset from that register | |
2051 | the frame itself is at. | |
2052 | ||
2053 | This presents a problem when trying to examine a stack in memory | |
2054 | (that isn't executing at the moment), using the "frame" command. We | |
2055 | don't have a PC, nor do we have any registers except SP. | |
2056 | ||
2057 | This routine takes two arguments, SP and PC, and tries to make the | |
2058 | cached frames look as if these two arguments defined a frame on the | |
2059 | cache. This allows the rest of info frame to extract the important | |
2060 | arguments without difficulty. */ | |
2061 | ||
2062 | struct frame_info * | |
acdb74a0 | 2063 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2064 | { |
2065 | if (argc != 2) | |
2066 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2067 | ||
2068 | return create_new_frame (argv[0], argv[1]); | |
2069 | } | |
2070 | ||
f09ded24 AC |
2071 | /* According to the current ABI, should the type be passed in a |
2072 | floating-point register (assuming that there is space)? When there | |
2073 | is no FPU, FP are not even considered as possibile candidates for | |
2074 | FP registers and, consequently this returns false - forces FP | |
2075 | arguments into integer registers. */ | |
2076 | ||
2077 | static int | |
2078 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2079 | { | |
2080 | return ((typecode == TYPE_CODE_FLT | |
2081 | || (MIPS_EABI | |
2082 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2083 | && TYPE_NFIELDS (arg_type) == 1 | |
2084 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
2085 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); | |
2086 | } | |
2087 | ||
c906108c | 2088 | CORE_ADDR |
acdb74a0 AC |
2089 | mips_push_arguments (int nargs, |
2090 | value_ptr *args, | |
2091 | CORE_ADDR sp, | |
2092 | int struct_return, | |
2093 | CORE_ADDR struct_addr) | |
c906108c SS |
2094 | { |
2095 | int argreg; | |
2096 | int float_argreg; | |
2097 | int argnum; | |
2098 | int len = 0; | |
2099 | int stack_offset = 0; | |
2100 | ||
2101 | /* Macros to round N up or down to the next A boundary; A must be | |
2102 | a power of two. */ | |
2103 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2104 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
c5aa993b | 2105 | |
c906108c SS |
2106 | /* First ensure that the stack and structure return address (if any) |
2107 | are properly aligned. The stack has to be at least 64-bit aligned | |
2108 | even on 32-bit machines, because doubles must be 64-bit aligned. | |
2109 | On at least one MIPS variant, stack frames need to be 128-bit | |
2110 | aligned, so we round to this widest known alignment. */ | |
2111 | sp = ROUND_DOWN (sp, 16); | |
cce41527 | 2112 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2113 | |
c906108c SS |
2114 | /* Now make space on the stack for the args. We allocate more |
2115 | than necessary for EABI, because the first few arguments are | |
2116 | passed in registers, but that's OK. */ | |
2117 | for (argnum = 0; argnum < nargs; argnum++) | |
cce41527 | 2118 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE); |
c906108c SS |
2119 | sp -= ROUND_UP (len, 16); |
2120 | ||
9ace0497 AC |
2121 | if (mips_debug) |
2122 | fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n", | |
2123 | (long) sp, ROUND_UP (len, 16)); | |
2124 | ||
c906108c SS |
2125 | /* Initialize the integer and float register pointers. */ |
2126 | argreg = A0_REGNUM; | |
2127 | float_argreg = FPA0_REGNUM; | |
2128 | ||
2129 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
2130 | if (struct_return) | |
9ace0497 AC |
2131 | { |
2132 | if (mips_debug) | |
2133 | fprintf_unfiltered (gdb_stdlog, | |
cce41527 | 2134 | "mips_push_arguments: struct_return reg=%d 0x%lx\n", |
9ace0497 AC |
2135 | argreg, (long) struct_addr); |
2136 | write_register (argreg++, struct_addr); | |
cce41527 AC |
2137 | if (MIPS_REGS_HAVE_HOME_P) |
2138 | stack_offset += MIPS_STACK_ARGSIZE; | |
9ace0497 | 2139 | } |
c906108c SS |
2140 | |
2141 | /* Now load as many as possible of the first arguments into | |
2142 | registers, and push the rest onto the stack. Loop thru args | |
2143 | from first to last. */ | |
2144 | for (argnum = 0; argnum < nargs; argnum++) | |
2145 | { | |
2146 | char *val; | |
2147 | char valbuf[MAX_REGISTER_RAW_SIZE]; | |
2148 | value_ptr arg = args[argnum]; | |
2149 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2150 | int len = TYPE_LENGTH (arg_type); | |
2151 | enum type_code typecode = TYPE_CODE (arg_type); | |
2152 | ||
9ace0497 AC |
2153 | if (mips_debug) |
2154 | fprintf_unfiltered (gdb_stdlog, | |
2155 | "mips_push_arguments: %d len=%d type=%d", | |
acdb74a0 | 2156 | argnum + 1, len, (int) typecode); |
9ace0497 | 2157 | |
c906108c | 2158 | /* The EABI passes structures that do not fit in a register by |
c5aa993b | 2159 | reference. In all other cases, pass the structure by value. */ |
9ace0497 AC |
2160 | if (MIPS_EABI |
2161 | && len > MIPS_SAVED_REGSIZE | |
2162 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
c906108c | 2163 | { |
7a292a7a | 2164 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2165 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2166 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2167 | val = valbuf; |
9ace0497 AC |
2168 | if (mips_debug) |
2169 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2170 | } |
2171 | else | |
c5aa993b | 2172 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2173 | |
2174 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2175 | even-numbered floating point register. Round the FP register |
2176 | up before the check to see if there are any FP registers | |
2177 | left. Non MIPS_EABI targets also pass the FP in the integer | |
2178 | registers so also round up normal registers. */ | |
2179 | if (!FP_REGISTER_DOUBLE | |
2180 | && fp_register_arg_p (typecode, arg_type)) | |
2181 | { | |
2182 | if ((float_argreg & 1)) | |
2183 | float_argreg++; | |
2184 | } | |
c906108c SS |
2185 | |
2186 | /* Floating point arguments passed in registers have to be | |
2187 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2188 | are passed in register pairs; the even register gets |
2189 | the low word, and the odd register gets the high word. | |
2190 | On non-EABI processors, the first two floating point arguments are | |
2191 | also copied to general registers, because MIPS16 functions | |
2192 | don't use float registers for arguments. This duplication of | |
2193 | arguments in general registers can't hurt non-MIPS16 functions | |
2194 | because those registers are normally skipped. */ | |
9a0149c6 AC |
2195 | /* MIPS_EABI squeeses a struct that contains a single floating |
2196 | point value into an FP register instead of pusing it onto the | |
2197 | stack. */ | |
f09ded24 AC |
2198 | if (fp_register_arg_p (typecode, arg_type) |
2199 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2200 | { |
2201 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2202 | { | |
2203 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
2204 | unsigned long regval; | |
2205 | ||
2206 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2207 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2208 | if (mips_debug) |
acdb74a0 | 2209 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2210 | float_argreg, phex (regval, 4)); |
c906108c SS |
2211 | write_register (float_argreg++, regval); |
2212 | if (!MIPS_EABI) | |
9ace0497 AC |
2213 | { |
2214 | if (mips_debug) | |
acdb74a0 | 2215 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2216 | argreg, phex (regval, 4)); |
2217 | write_register (argreg++, regval); | |
2218 | } | |
c906108c SS |
2219 | |
2220 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2221 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2222 | if (mips_debug) |
acdb74a0 | 2223 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2224 | float_argreg, phex (regval, 4)); |
c906108c SS |
2225 | write_register (float_argreg++, regval); |
2226 | if (!MIPS_EABI) | |
c5aa993b | 2227 | { |
9ace0497 | 2228 | if (mips_debug) |
acdb74a0 | 2229 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2230 | argreg, phex (regval, 4)); |
2231 | write_register (argreg++, regval); | |
c906108c SS |
2232 | } |
2233 | ||
2234 | } | |
2235 | else | |
2236 | { | |
2237 | /* This is a floating point value that fits entirely | |
2238 | in a single register. */ | |
53a5351d JM |
2239 | /* On 32 bit ABI's the float_argreg is further adjusted |
2240 | above to ensure that it is even register aligned. */ | |
9ace0497 AC |
2241 | LONGEST regval = extract_unsigned_integer (val, len); |
2242 | if (mips_debug) | |
acdb74a0 | 2243 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2244 | float_argreg, phex (regval, len)); |
c906108c SS |
2245 | write_register (float_argreg++, regval); |
2246 | if (!MIPS_EABI) | |
c5aa993b | 2247 | { |
53a5351d JM |
2248 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
2249 | registers for each argument. The below is (my | |
2250 | guess) to ensure that the corresponding integer | |
2251 | register has reserved the same space. */ | |
9ace0497 | 2252 | if (mips_debug) |
acdb74a0 | 2253 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2254 | argreg, phex (regval, len)); |
c906108c SS |
2255 | write_register (argreg, regval); |
2256 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
2257 | } | |
2258 | } | |
cce41527 AC |
2259 | /* Reserve space for the FP register. */ |
2260 | if (MIPS_REGS_HAVE_HOME_P) | |
2261 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
c906108c SS |
2262 | } |
2263 | else | |
2264 | { | |
2265 | /* Copy the argument to general registers or the stack in | |
2266 | register-sized pieces. Large arguments are split between | |
2267 | registers and stack. */ | |
2268 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2269 | are treated specially: Irix cc passes them in registers | |
2270 | where gcc sometimes puts them on the stack. For maximum | |
2271 | compatibility, we will put them in both places. */ | |
c5aa993b | 2272 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2273 | (len % MIPS_SAVED_REGSIZE != 0)); |
f09ded24 AC |
2274 | /* Note: Floating-point values that didn't fit into an FP |
2275 | register are only written to memory. */ | |
c906108c SS |
2276 | while (len > 0) |
2277 | { | |
566f0f7a AC |
2278 | /* Rememer if the argument was written to the stack. */ |
2279 | int stack_used_p = 0; | |
7a292a7a | 2280 | int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; |
c906108c | 2281 | |
acdb74a0 AC |
2282 | if (mips_debug) |
2283 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2284 | partial_len); | |
2285 | ||
566f0f7a | 2286 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2287 | if (argreg > MIPS_LAST_ARG_REGNUM |
2288 | || odd_sized_struct | |
2289 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2290 | { |
c906108c SS |
2291 | /* Should shorter than int integer values be |
2292 | promoted to int before being stored? */ | |
c906108c | 2293 | int longword_offset = 0; |
9ace0497 | 2294 | CORE_ADDR addr; |
566f0f7a | 2295 | stack_used_p = 1; |
c906108c | 2296 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
7a292a7a | 2297 | { |
d929b26f | 2298 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2299 | (typecode == TYPE_CODE_INT || |
2300 | typecode == TYPE_CODE_PTR || | |
2301 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2302 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2303 | else if ((typecode == TYPE_CODE_STRUCT || |
2304 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2305 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2306 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2307 | } |
c5aa993b | 2308 | |
9ace0497 AC |
2309 | if (mips_debug) |
2310 | { | |
acdb74a0 | 2311 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx", |
9ace0497 AC |
2312 | (long) stack_offset); |
2313 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx", | |
2314 | (long) longword_offset); | |
2315 | } | |
2316 | ||
2317 | addr = sp + stack_offset + longword_offset; | |
2318 | ||
2319 | if (mips_debug) | |
2320 | { | |
2321 | int i; | |
2322 | fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr); | |
2323 | for (i = 0; i < partial_len; i++) | |
2324 | { | |
2325 | fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff); | |
2326 | } | |
2327 | } | |
2328 | write_memory (addr, val, partial_len); | |
c906108c SS |
2329 | } |
2330 | ||
f09ded24 AC |
2331 | /* Note!!! This is NOT an else clause. Odd sized |
2332 | structs may go thru BOTH paths. Floating point | |
2333 | arguments will not. */ | |
566f0f7a AC |
2334 | /* Write this portion of the argument to a general |
2335 | purpose register. */ | |
f09ded24 AC |
2336 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2337 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2338 | { |
9ace0497 | 2339 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c SS |
2340 | |
2341 | /* A non-floating-point argument being passed in a | |
2342 | general register. If a struct or union, and if | |
2343 | the remaining length is smaller than the register | |
2344 | size, we have to adjust the register value on | |
2345 | big endian targets. | |
2346 | ||
2347 | It does not seem to be necessary to do the | |
2348 | same for integral types. | |
2349 | ||
2350 | Also don't do this adjustment on EABI and O64 | |
2351 | binaries. */ | |
2352 | ||
2353 | if (!MIPS_EABI | |
7a292a7a | 2354 | && MIPS_SAVED_REGSIZE < 8 |
c906108c | 2355 | && TARGET_BYTE_ORDER == BIG_ENDIAN |
7a292a7a | 2356 | && partial_len < MIPS_SAVED_REGSIZE |
c906108c SS |
2357 | && (typecode == TYPE_CODE_STRUCT || |
2358 | typecode == TYPE_CODE_UNION)) | |
c5aa993b | 2359 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * |
c906108c SS |
2360 | TARGET_CHAR_BIT); |
2361 | ||
9ace0497 | 2362 | if (mips_debug) |
acdb74a0 | 2363 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2364 | argreg, |
2365 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2366 | write_register (argreg, regval); |
2367 | argreg++; | |
c5aa993b | 2368 | |
c906108c SS |
2369 | /* If this is the old ABI, prevent subsequent floating |
2370 | point arguments from being passed in floating point | |
2371 | registers. */ | |
2372 | if (!MIPS_EABI) | |
2373 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
2374 | } | |
c5aa993b | 2375 | |
c906108c SS |
2376 | len -= partial_len; |
2377 | val += partial_len; | |
2378 | ||
566f0f7a AC |
2379 | /* Compute the the offset into the stack at which we |
2380 | will copy the next parameter. | |
2381 | ||
2382 | In older ABIs, the caller reserved space for | |
2383 | registers that contained arguments. This was loosely | |
2384 | refered to as their "home". Consequently, space is | |
2385 | always allocated. | |
c906108c | 2386 | |
566f0f7a AC |
2387 | In the new EABI (and the NABI32), the stack_offset |
2388 | only needs to be adjusted when it has been used.. */ | |
c906108c | 2389 | |
566f0f7a | 2390 | if (MIPS_REGS_HAVE_HOME_P || stack_used_p) |
d929b26f | 2391 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2392 | } |
2393 | } | |
9ace0497 AC |
2394 | if (mips_debug) |
2395 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2396 | } |
2397 | ||
0f71a2f6 JM |
2398 | /* Return adjusted stack pointer. */ |
2399 | return sp; | |
2400 | } | |
2401 | ||
2402 | CORE_ADDR | |
acdb74a0 | 2403 | mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
0f71a2f6 | 2404 | { |
c906108c SS |
2405 | /* Set the return address register to point to the entry |
2406 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 2407 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
2408 | return sp; |
2409 | } | |
2410 | ||
2411 | static void | |
c5aa993b | 2412 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c SS |
2413 | { |
2414 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
7a292a7a SS |
2415 | int regsize; |
2416 | int offset; | |
2417 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
2418 | { | |
2419 | regsize = MIPS_SAVED_REGSIZE; | |
2420 | offset = (TARGET_BYTE_ORDER == BIG_ENDIAN | |
2421 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE | |
2422 | : 0); | |
2423 | } | |
2424 | else | |
2425 | { | |
2426 | regsize = REGISTER_RAW_SIZE (regno); | |
2427 | offset = 0; | |
2428 | } | |
c906108c SS |
2429 | *sp -= regsize; |
2430 | read_register_gen (regno, buffer); | |
7a292a7a | 2431 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
2432 | } |
2433 | ||
2434 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
2435 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
2436 | ||
2437 | void | |
acdb74a0 | 2438 | mips_push_dummy_frame (void) |
c906108c SS |
2439 | { |
2440 | int ireg; | |
c5aa993b JM |
2441 | struct linked_proc_info *link = (struct linked_proc_info *) |
2442 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c | 2443 | mips_extra_func_info_t proc_desc = &link->info; |
6c997a34 | 2444 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); |
c906108c SS |
2445 | CORE_ADDR old_sp = sp; |
2446 | link->next = linked_proc_desc_table; | |
2447 | linked_proc_desc_table = link; | |
2448 | ||
2449 | /* FIXME! are these correct ? */ | |
c5aa993b | 2450 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
2451 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
2452 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
2453 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
2454 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
2455 | /* | |
2456 | * The registers we must save are all those not preserved across | |
2457 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
2458 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
2459 | * and FP Control/Status registers. | |
2460 | * | |
2461 | * | |
2462 | * Dummy frame layout: | |
2463 | * (high memory) | |
c5aa993b JM |
2464 | * Saved PC |
2465 | * Saved MMHI, MMLO, FPC_CSR | |
2466 | * Saved R31 | |
2467 | * Saved R28 | |
2468 | * ... | |
2469 | * Saved R1 | |
c906108c SS |
2470 | * Saved D18 (i.e. F19, F18) |
2471 | * ... | |
2472 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 2473 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
2474 | * (low memory) |
2475 | */ | |
2476 | ||
2477 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
2478 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
2479 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
2480 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
2481 | mips_push_register (&sp, PC_REGNUM); |
2482 | mips_push_register (&sp, HI_REGNUM); | |
2483 | mips_push_register (&sp, LO_REGNUM); | |
2484 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
2485 | ||
2486 | /* Save general CPU registers */ | |
c5aa993b | 2487 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 2488 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
2489 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
2490 | for (ireg = 32; --ireg >= 0;) | |
2491 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2492 | mips_push_register (&sp, ireg); |
2493 | ||
2494 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 2495 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
2496 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
2497 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
2498 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
2499 | from FP. */ | |
c5aa993b JM |
2500 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
2501 | for (ireg = 32; --ireg >= 0;) | |
2502 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2503 | mips_push_register (&sp, ireg + FP0_REGNUM); |
2504 | ||
2505 | /* Update the frame pointer for the call dummy and the stack pointer. | |
2506 | Set the procedure's starting and ending addresses to point to the | |
2507 | call dummy address at the entry point. */ | |
2508 | write_register (PUSH_FP_REGNUM, old_sp); | |
2509 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
2510 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
2511 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
2512 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
2513 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
2514 | } |
2515 | ||
2516 | void | |
acdb74a0 | 2517 | mips_pop_frame (void) |
c906108c SS |
2518 | { |
2519 | register int regnum; | |
2520 | struct frame_info *frame = get_current_frame (); | |
2521 | CORE_ADDR new_sp = FRAME_FP (frame); | |
2522 | ||
cce74817 | 2523 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 2524 | |
c5aa993b | 2525 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c SS |
2526 | if (frame->saved_regs == NULL) |
2527 | mips_find_saved_regs (frame); | |
2528 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
2529 | { | |
2530 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
2531 | && frame->saved_regs[regnum]) | |
2532 | write_register (regnum, | |
2533 | read_memory_integer (frame->saved_regs[regnum], | |
c5aa993b | 2534 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2535 | } |
2536 | write_register (SP_REGNUM, new_sp); | |
2537 | flush_cached_frames (); | |
2538 | ||
c5aa993b | 2539 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
2540 | { |
2541 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
2542 | ||
2543 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
2544 | pi_ptr != NULL; | |
2545 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
2546 | { | |
2547 | if (&pi_ptr->info == proc_desc) | |
2548 | break; | |
2549 | } | |
2550 | ||
2551 | if (pi_ptr == NULL) | |
2552 | error ("Can't locate dummy extra frame info\n"); | |
2553 | ||
2554 | if (prev_ptr != NULL) | |
2555 | prev_ptr->next = pi_ptr->next; | |
2556 | else | |
2557 | linked_proc_desc_table = pi_ptr->next; | |
2558 | ||
b8c9b27d | 2559 | xfree (pi_ptr); |
c906108c SS |
2560 | |
2561 | write_register (HI_REGNUM, | |
c5aa993b | 2562 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2563 | MIPS_SAVED_REGSIZE)); |
c906108c | 2564 | write_register (LO_REGNUM, |
c5aa993b | 2565 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2566 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2567 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
2568 | write_register (FCRCS_REGNUM, | |
c5aa993b | 2569 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2570 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2571 | } |
2572 | } | |
2573 | ||
2574 | static void | |
acdb74a0 | 2575 | mips_print_register (int regnum, int all) |
c906108c SS |
2576 | { |
2577 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2578 | ||
2579 | /* Get the data in raw format. */ | |
2580 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2581 | { | |
2582 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
2583 | return; | |
2584 | } | |
2585 | ||
2586 | /* If an even floating point register, also print as double. */ | |
2587 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT | |
c5aa993b JM |
2588 | && !((regnum - FP0_REGNUM) & 1)) |
2589 | if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */ | |
c906108c | 2590 | { |
c5aa993b | 2591 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; |
c906108c SS |
2592 | |
2593 | read_relative_register_raw_bytes (regnum, dbuffer); | |
c5aa993b | 2594 | read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE); |
c906108c SS |
2595 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); |
2596 | ||
c5aa993b | 2597 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
c906108c SS |
2598 | val_print (builtin_type_double, dbuffer, 0, 0, |
2599 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2600 | printf_filtered ("); "); | |
2601 | } | |
2602 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
2603 | ||
2604 | /* The problem with printing numeric register names (r26, etc.) is that | |
2605 | the user can't use them on input. Probably the best solution is to | |
2606 | fix it so that either the numeric or the funky (a2, etc.) names | |
2607 | are accepted on input. */ | |
2608 | if (regnum < MIPS_NUMREGS) | |
2609 | printf_filtered ("(r%d): ", regnum); | |
2610 | else | |
2611 | printf_filtered (": "); | |
2612 | ||
2613 | /* If virtual format is floating, print it that way. */ | |
2614 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2615 | if (FP_REGISTER_DOUBLE) | |
c5aa993b | 2616 | { /* show 8-byte floats as float AND double: */ |
c906108c SS |
2617 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2618 | ||
2619 | printf_filtered (" (float) "); | |
2620 | val_print (builtin_type_float, raw_buffer + offset, 0, 0, | |
2621 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2622 | printf_filtered (", (double) "); | |
2623 | val_print (builtin_type_double, raw_buffer, 0, 0, | |
2624 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2625 | } | |
2626 | else | |
2627 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
2628 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2629 | /* Else print as integer in hex. */ | |
2630 | else | |
ed9a39eb JM |
2631 | { |
2632 | int offset; | |
2633 | ||
2634 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2635 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); | |
2636 | else | |
2637 | offset = 0; | |
2638 | ||
2639 | print_scalar_formatted (raw_buffer + offset, | |
2640 | REGISTER_VIRTUAL_TYPE (regnum), | |
2641 | 'x', 0, gdb_stdout); | |
2642 | } | |
c906108c SS |
2643 | } |
2644 | ||
2645 | /* Replacement for generic do_registers_info. | |
2646 | Print regs in pretty columns. */ | |
2647 | ||
2648 | static int | |
acdb74a0 | 2649 | do_fp_register_row (int regnum) |
c5aa993b | 2650 | { /* do values for FP (float) regs */ |
c906108c SS |
2651 | char *raw_buffer[2]; |
2652 | char *dbl_buffer; | |
2653 | /* use HI and LO to control the order of combining two flt regs */ | |
2654 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2655 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); | |
2656 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ | |
2657 | int inv1, inv2, inv3; | |
c5aa993b | 2658 | |
c906108c SS |
2659 | raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
2660 | raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2661 | dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2662 | ||
2663 | /* Get the data in raw format. */ | |
2664 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) | |
2665 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
c5aa993b | 2666 | if (REGISTER_RAW_SIZE (regnum) == 4) |
c906108c SS |
2667 | { |
2668 | /* 4-byte registers: we can fit two registers per row. */ | |
2669 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
2670 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) | |
c5aa993b | 2671 | error ("can't read register %d (%s)", |
c906108c SS |
2672 | regnum + 1, REGISTER_NAME (regnum + 1)); |
2673 | ||
2674 | /* copy the two floats into one double, and unpack both */ | |
65edb64b | 2675 | memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b JM |
2676 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); |
2677 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); | |
2678 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
2679 | ||
1adad886 AC |
2680 | printf_filtered (" %-5s", REGISTER_NAME (regnum)); |
2681 | if (inv1) | |
2682 | printf_filtered (": <invalid float>"); | |
2683 | else | |
2684 | printf_filtered ("%-17.9g", flt1); | |
2685 | ||
2686 | printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); | |
2687 | if (inv2) | |
2688 | printf_filtered (": <invalid float>"); | |
2689 | else | |
2690 | printf_filtered ("%-17.9g", flt2); | |
2691 | ||
2692 | printf_filtered (" dbl: "); | |
2693 | if (inv3) | |
2694 | printf_filtered ("<invalid double>"); | |
2695 | else | |
2696 | printf_filtered ("%-24.17g", doub); | |
2697 | printf_filtered ("\n"); | |
2698 | ||
c906108c | 2699 | /* may want to do hex display here (future enhancement) */ |
c5aa993b | 2700 | regnum += 2; |
c906108c SS |
2701 | } |
2702 | else | |
c5aa993b | 2703 | { /* eight byte registers: print each one as float AND as double. */ |
c906108c SS |
2704 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2705 | ||
65edb64b | 2706 | memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b | 2707 | flt1 = unpack_double (builtin_type_float, |
c906108c | 2708 | &raw_buffer[HI][offset], &inv1); |
c5aa993b | 2709 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); |
c906108c | 2710 | |
1adad886 AC |
2711 | printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); |
2712 | if (inv1) | |
2713 | printf_filtered ("<invalid float>"); | |
2714 | else | |
2715 | printf_filtered ("flt: %-17.9g", flt1); | |
2716 | ||
2717 | printf_filtered (" dbl: "); | |
2718 | if (inv3) | |
2719 | printf_filtered ("<invalid double>"); | |
2720 | else | |
2721 | printf_filtered ("%-24.17g", doub); | |
2722 | ||
2723 | printf_filtered ("\n"); | |
c906108c SS |
2724 | /* may want to do hex display here (future enhancement) */ |
2725 | regnum++; | |
2726 | } | |
2727 | return regnum; | |
2728 | } | |
2729 | ||
2730 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
2731 | ||
2732 | static int | |
acdb74a0 | 2733 | do_gp_register_row (int regnum) |
c906108c SS |
2734 | { |
2735 | /* do values for GP (int) regs */ | |
2736 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2737 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ | |
2738 | int col, byte; | |
2739 | int start_regnum = regnum; | |
2740 | int numregs = NUM_REGS; | |
2741 | ||
2742 | ||
2743 | /* For GP registers, we print a separate row of names above the vals */ | |
2744 | printf_filtered (" "); | |
2745 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2746 | { | |
2747 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2748 | continue; /* unused register */ |
c906108c | 2749 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
2750 | break; /* end the row: reached FP register */ |
2751 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
2752 | REGISTER_NAME (regnum)); |
2753 | col++; | |
2754 | } | |
c5aa993b | 2755 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
2756 | start_regnum); /* print the R0 to R31 names */ |
2757 | ||
2758 | regnum = start_regnum; /* go back to start of row */ | |
2759 | /* now print the values in hex, 4 or 8 to the row */ | |
2760 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2761 | { | |
2762 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2763 | continue; /* unused register */ |
c906108c | 2764 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 2765 | break; /* end row: reached FP register */ |
c906108c SS |
2766 | /* OK: get the data in raw format. */ |
2767 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2768 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
2769 | /* pad small registers */ | |
43e526b9 | 2770 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
2771 | printf_filtered (" "); |
2772 | /* Now print the register value in hex, endian order. */ | |
2773 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
43e526b9 JM |
2774 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
2775 | byte < REGISTER_RAW_SIZE (regnum); | |
2776 | byte++) | |
c906108c SS |
2777 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2778 | else | |
43e526b9 JM |
2779 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
2780 | byte >= 0; | |
2781 | byte--) | |
c906108c SS |
2782 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2783 | printf_filtered (" "); | |
2784 | col++; | |
2785 | } | |
c5aa993b | 2786 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
2787 | printf_filtered ("\n"); |
2788 | ||
2789 | return regnum; | |
2790 | } | |
2791 | ||
2792 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
2793 | ||
2794 | void | |
acdb74a0 | 2795 | mips_do_registers_info (int regnum, int fpregs) |
c906108c | 2796 | { |
c5aa993b | 2797 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
2798 | { |
2799 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2800 | error ("Not a valid register for the current processor type"); | |
2801 | ||
2802 | mips_print_register (regnum, 0); | |
2803 | printf_filtered ("\n"); | |
2804 | } | |
c5aa993b JM |
2805 | else |
2806 | /* do all (or most) registers */ | |
c906108c SS |
2807 | { |
2808 | regnum = 0; | |
2809 | while (regnum < NUM_REGS) | |
2810 | { | |
c5aa993b JM |
2811 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
2812 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
2813 | regnum = do_fp_register_row (regnum); /* FP regs */ |
2814 | else | |
2815 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
2816 | else | |
2817 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
2818 | } | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | /* Return number of args passed to a frame. described by FIP. | |
2823 | Can return -1, meaning no way to tell. */ | |
2824 | ||
2825 | int | |
acdb74a0 | 2826 | mips_frame_num_args (struct frame_info *frame) |
c906108c | 2827 | { |
c906108c SS |
2828 | return -1; |
2829 | } | |
2830 | ||
2831 | /* Is this a branch with a delay slot? */ | |
2832 | ||
a14ed312 | 2833 | static int is_delayed (unsigned long); |
c906108c SS |
2834 | |
2835 | static int | |
acdb74a0 | 2836 | is_delayed (unsigned long insn) |
c906108c SS |
2837 | { |
2838 | int i; | |
2839 | for (i = 0; i < NUMOPCODES; ++i) | |
2840 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
2841 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
2842 | break; | |
2843 | return (i < NUMOPCODES | |
2844 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2845 | | INSN_COND_BRANCH_DELAY | |
2846 | | INSN_COND_BRANCH_LIKELY))); | |
2847 | } | |
2848 | ||
2849 | int | |
acdb74a0 | 2850 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
2851 | { |
2852 | char buf[MIPS_INSTLEN]; | |
2853 | ||
2854 | /* There is no branch delay slot on MIPS16. */ | |
2855 | if (pc_is_mips16 (pc)) | |
2856 | return 0; | |
2857 | ||
2858 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
2859 | /* If error reading memory, guess that it is not a delayed branch. */ | |
2860 | return 0; | |
c5aa993b | 2861 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
2862 | } |
2863 | ||
2864 | ||
2865 | /* Skip the PC past function prologue instructions (32-bit version). | |
2866 | This is a helper function for mips_skip_prologue. */ | |
2867 | ||
2868 | static CORE_ADDR | |
f7b9e9fc | 2869 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 2870 | { |
c5aa993b JM |
2871 | t_inst inst; |
2872 | CORE_ADDR end_pc; | |
2873 | int seen_sp_adjust = 0; | |
2874 | int load_immediate_bytes = 0; | |
2875 | ||
2876 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2877 | instruction and the instructions that save registers on the stack | |
2878 | or in the gcc frame. */ | |
2879 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
2880 | { | |
2881 | unsigned long high_word; | |
c906108c | 2882 | |
c5aa993b JM |
2883 | inst = mips_fetch_instruction (pc); |
2884 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 2885 | |
c5aa993b JM |
2886 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
2887 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
2888 | seen_sp_adjust = 1; | |
2889 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
2890 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
2891 | seen_sp_adjust = 1; | |
2892 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
2893 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
2894 | && (inst & 0x001F0000)) /* reg != $zero */ | |
2895 | continue; | |
2896 | ||
2897 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
2898 | continue; | |
2899 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
2900 | /* sx reg,n($s8) */ | |
2901 | continue; /* reg != $zero */ | |
2902 | ||
2903 | /* move $s8,$sp. With different versions of gas this will be either | |
2904 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
2905 | Accept any one of these. */ | |
2906 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2907 | continue; | |
2908 | ||
2909 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
2910 | continue; | |
2911 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
2912 | continue; | |
2913 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
2914 | continue; | |
2915 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2916 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
2917 | continue; | |
2918 | /* The following instructions load $at or $t0 with an immediate | |
2919 | value in preparation for a stack adjustment via | |
2920 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
2921 | a local variable, so we accept them only before a stack adjustment | |
2922 | instruction was seen. */ | |
2923 | else if (!seen_sp_adjust) | |
2924 | { | |
2925 | if (high_word == 0x3c01 || /* lui $at,n */ | |
2926 | high_word == 0x3c08) /* lui $t0,n */ | |
2927 | { | |
2928 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
2929 | continue; | |
2930 | } | |
2931 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
2932 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
2933 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
2934 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
2935 | { | |
2936 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
2937 | continue; | |
2938 | } | |
2939 | else | |
2940 | break; | |
2941 | } | |
2942 | else | |
2943 | break; | |
c906108c SS |
2944 | } |
2945 | ||
c5aa993b JM |
2946 | /* In a frameless function, we might have incorrectly |
2947 | skipped some load immediate instructions. Undo the skipping | |
2948 | if the load immediate was not followed by a stack adjustment. */ | |
2949 | if (load_immediate_bytes && !seen_sp_adjust) | |
2950 | pc -= load_immediate_bytes; | |
2951 | return pc; | |
c906108c SS |
2952 | } |
2953 | ||
2954 | /* Skip the PC past function prologue instructions (16-bit version). | |
2955 | This is a helper function for mips_skip_prologue. */ | |
2956 | ||
2957 | static CORE_ADDR | |
f7b9e9fc | 2958 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 2959 | { |
c5aa993b JM |
2960 | CORE_ADDR end_pc; |
2961 | int extend_bytes = 0; | |
2962 | int prev_extend_bytes; | |
c906108c | 2963 | |
c5aa993b JM |
2964 | /* Table of instructions likely to be found in a function prologue. */ |
2965 | static struct | |
c906108c SS |
2966 | { |
2967 | unsigned short inst; | |
2968 | unsigned short mask; | |
c5aa993b JM |
2969 | } |
2970 | table[] = | |
2971 | { | |
c906108c | 2972 | { |
c5aa993b JM |
2973 | 0x6300, 0xff00 |
2974 | } | |
2975 | , /* addiu $sp,offset */ | |
2976 | { | |
2977 | 0xfb00, 0xff00 | |
2978 | } | |
2979 | , /* daddiu $sp,offset */ | |
2980 | { | |
2981 | 0xd000, 0xf800 | |
2982 | } | |
2983 | , /* sw reg,n($sp) */ | |
2984 | { | |
2985 | 0xf900, 0xff00 | |
2986 | } | |
2987 | , /* sd reg,n($sp) */ | |
2988 | { | |
2989 | 0x6200, 0xff00 | |
2990 | } | |
2991 | , /* sw $ra,n($sp) */ | |
2992 | { | |
2993 | 0xfa00, 0xff00 | |
2994 | } | |
2995 | , /* sd $ra,n($sp) */ | |
2996 | { | |
2997 | 0x673d, 0xffff | |
2998 | } | |
2999 | , /* move $s1,sp */ | |
3000 | { | |
3001 | 0xd980, 0xff80 | |
3002 | } | |
3003 | , /* sw $a0-$a3,n($s1) */ | |
3004 | { | |
3005 | 0x6704, 0xff1c | |
3006 | } | |
3007 | , /* move reg,$a0-$a3 */ | |
3008 | { | |
3009 | 0xe809, 0xf81f | |
3010 | } | |
3011 | , /* entry pseudo-op */ | |
3012 | { | |
3013 | 0x0100, 0xff00 | |
3014 | } | |
3015 | , /* addiu $s1,$sp,n */ | |
3016 | { | |
3017 | 0, 0 | |
3018 | } /* end of table marker */ | |
3019 | }; | |
3020 | ||
3021 | /* Skip the typical prologue instructions. These are the stack adjustment | |
3022 | instruction and the instructions that save registers on the stack | |
3023 | or in the gcc frame. */ | |
3024 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
3025 | { | |
3026 | unsigned short inst; | |
3027 | int i; | |
c906108c | 3028 | |
c5aa993b | 3029 | inst = mips_fetch_instruction (pc); |
c906108c | 3030 | |
c5aa993b JM |
3031 | /* Normally we ignore an extend instruction. However, if it is |
3032 | not followed by a valid prologue instruction, we must adjust | |
3033 | the pc back over the extend so that it won't be considered | |
3034 | part of the prologue. */ | |
3035 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
3036 | { | |
3037 | extend_bytes = MIPS16_INSTLEN; | |
3038 | continue; | |
3039 | } | |
3040 | prev_extend_bytes = extend_bytes; | |
3041 | extend_bytes = 0; | |
c906108c | 3042 | |
c5aa993b JM |
3043 | /* Check for other valid prologue instructions besides extend. */ |
3044 | for (i = 0; table[i].mask != 0; i++) | |
3045 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
3046 | break; | |
3047 | if (table[i].mask != 0) /* it was in table? */ | |
3048 | continue; /* ignore it */ | |
3049 | else | |
3050 | /* non-prologue */ | |
3051 | { | |
3052 | /* Return the current pc, adjusted backwards by 2 if | |
3053 | the previous instruction was an extend. */ | |
3054 | return pc - prev_extend_bytes; | |
3055 | } | |
c906108c SS |
3056 | } |
3057 | return pc; | |
3058 | } | |
3059 | ||
3060 | /* To skip prologues, I use this predicate. Returns either PC itself | |
3061 | if the code at PC does not look like a function prologue; otherwise | |
3062 | returns an address that (if we're lucky) follows the prologue. If | |
3063 | LENIENT, then we must skip everything which is involved in setting | |
3064 | up the frame (it's OK to skip more, just so long as we don't skip | |
3065 | anything which might clobber the registers which are being saved. | |
3066 | We must skip more in the case where part of the prologue is in the | |
3067 | delay slot of a non-prologue instruction). */ | |
3068 | ||
3069 | CORE_ADDR | |
f7b9e9fc | 3070 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
3071 | { |
3072 | /* See if we can determine the end of the prologue via the symbol table. | |
3073 | If so, then return either PC, or the PC after the prologue, whichever | |
3074 | is greater. */ | |
3075 | ||
3076 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
3077 | ||
3078 | if (post_prologue_pc != 0) | |
3079 | return max (pc, post_prologue_pc); | |
3080 | ||
3081 | /* Can't determine prologue from the symbol table, need to examine | |
3082 | instructions. */ | |
3083 | ||
3084 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 3085 | return mips16_skip_prologue (pc); |
c906108c | 3086 | else |
f7b9e9fc | 3087 | return mips32_skip_prologue (pc); |
c906108c | 3088 | } |
c906108c | 3089 | |
7a292a7a SS |
3090 | /* Determine how a return value is stored within the MIPS register |
3091 | file, given the return type `valtype'. */ | |
3092 | ||
3093 | struct return_value_word | |
3094 | { | |
3095 | int len; | |
3096 | int reg; | |
3097 | int reg_offset; | |
3098 | int buf_offset; | |
3099 | }; | |
3100 | ||
7a292a7a | 3101 | static void |
acdb74a0 AC |
3102 | return_value_location (struct type *valtype, |
3103 | struct return_value_word *hi, | |
3104 | struct return_value_word *lo) | |
7a292a7a SS |
3105 | { |
3106 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3107 | |
7a292a7a SS |
3108 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
3109 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3110 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3111 | { | |
3112 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3113 | { | |
3114 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 3115 | spread them across a floating-point register pair. */ |
7a292a7a SS |
3116 | lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; |
3117 | hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4; | |
3118 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN | |
3119 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) | |
3120 | ? 4 : 0); | |
3121 | hi->reg_offset = lo->reg_offset; | |
3122 | lo->reg = FP0_REGNUM + 0; | |
3123 | hi->reg = FP0_REGNUM + 1; | |
3124 | lo->len = 4; | |
3125 | hi->len = 4; | |
3126 | } | |
3127 | else | |
3128 | { | |
3129 | /* The floating point value fits in a single floating-point | |
c5aa993b | 3130 | register. */ |
7a292a7a SS |
3131 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN |
3132 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 | |
3133 | && len == 4) | |
3134 | ? 4 : 0); | |
3135 | lo->reg = FP0_REGNUM; | |
3136 | lo->len = len; | |
3137 | lo->buf_offset = 0; | |
3138 | hi->len = 0; | |
3139 | hi->reg_offset = 0; | |
3140 | hi->buf_offset = 0; | |
3141 | hi->reg = 0; | |
3142 | } | |
3143 | } | |
3144 | else | |
3145 | { | |
3146 | /* Locate a result possibly spread across two registers. */ | |
3147 | int regnum = 2; | |
3148 | lo->reg = regnum + 0; | |
3149 | hi->reg = regnum + 1; | |
3150 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3151 | && len < MIPS_SAVED_REGSIZE) | |
3152 | { | |
3153 | /* "un-left-justify" the value in the low register */ | |
3154 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
3155 | lo->len = len; | |
3156 | hi->reg_offset = 0; | |
3157 | hi->len = 0; | |
3158 | } | |
3159 | else if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3160 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ | |
3161 | && len < MIPS_SAVED_REGSIZE * 2 | |
3162 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3163 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3164 | { | |
3165 | /* "un-left-justify" the value spread across two registers. */ | |
3166 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
3167 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
3168 | hi->reg_offset = 0; | |
3169 | hi->len = len - lo->len; | |
3170 | } | |
3171 | else | |
3172 | { | |
3173 | /* Only perform a partial copy of the second register. */ | |
3174 | lo->reg_offset = 0; | |
3175 | hi->reg_offset = 0; | |
3176 | if (len > MIPS_SAVED_REGSIZE) | |
3177 | { | |
3178 | lo->len = MIPS_SAVED_REGSIZE; | |
3179 | hi->len = len - MIPS_SAVED_REGSIZE; | |
3180 | } | |
3181 | else | |
3182 | { | |
3183 | lo->len = len; | |
3184 | hi->len = 0; | |
3185 | } | |
3186 | } | |
3187 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3188 | && REGISTER_RAW_SIZE (regnum) == 8 | |
3189 | && MIPS_SAVED_REGSIZE == 4) | |
3190 | { | |
3191 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 3192 | of the register is being used */ |
7a292a7a SS |
3193 | lo->reg_offset += 4; |
3194 | hi->reg_offset += 4; | |
3195 | } | |
3196 | lo->buf_offset = 0; | |
3197 | hi->buf_offset = lo->len; | |
3198 | } | |
3199 | } | |
3200 | ||
3201 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
3202 | copy its value into `valbuf'. */ | |
3203 | ||
c906108c | 3204 | void |
acdb74a0 AC |
3205 | mips_extract_return_value (struct type *valtype, |
3206 | char regbuf[REGISTER_BYTES], | |
3207 | char *valbuf) | |
c906108c | 3208 | { |
7a292a7a SS |
3209 | struct return_value_word lo; |
3210 | struct return_value_word hi; | |
3211 | return_value_location (valtype, &lo, &hi); | |
3212 | ||
3213 | memcpy (valbuf + lo.buf_offset, | |
3214 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
3215 | lo.len); | |
3216 | ||
3217 | if (hi.len > 0) | |
3218 | memcpy (valbuf + hi.buf_offset, | |
3219 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
3220 | hi.len); | |
c906108c SS |
3221 | } |
3222 | ||
7a292a7a SS |
3223 | /* Given a return value in `valbuf' with a type `valtype', write it's |
3224 | value into the appropriate register. */ | |
3225 | ||
c906108c | 3226 | void |
acdb74a0 | 3227 | mips_store_return_value (struct type *valtype, char *valbuf) |
c906108c | 3228 | { |
7a292a7a SS |
3229 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
3230 | struct return_value_word lo; | |
3231 | struct return_value_word hi; | |
3232 | return_value_location (valtype, &lo, &hi); | |
3233 | ||
3234 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3235 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3236 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
3237 | raw_buffer, | |
3238 | REGISTER_RAW_SIZE (lo.reg)); | |
c5aa993b | 3239 | |
7a292a7a SS |
3240 | if (hi.len > 0) |
3241 | { | |
3242 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3243 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3244 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
3245 | raw_buffer, | |
3246 | REGISTER_RAW_SIZE (hi.reg)); | |
3247 | } | |
c906108c SS |
3248 | } |
3249 | ||
3250 | /* Exported procedure: Is PC in the signal trampoline code */ | |
3251 | ||
3252 | int | |
acdb74a0 | 3253 | in_sigtramp (CORE_ADDR pc, char *ignore) |
c906108c SS |
3254 | { |
3255 | if (sigtramp_address == 0) | |
3256 | fixup_sigtramp (); | |
3257 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
3258 | } | |
3259 | ||
a5ea2558 AC |
3260 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
3261 | used for all MIPS-specific commands. */ | |
3262 | ||
a5ea2558 | 3263 | static void |
acdb74a0 | 3264 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
3265 | { |
3266 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
3267 | } | |
3268 | ||
a5ea2558 | 3269 | static void |
acdb74a0 | 3270 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
3271 | { |
3272 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
3273 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
3274 | } | |
3275 | ||
c906108c SS |
3276 | /* Commands to show/set the MIPS FPU type. */ |
3277 | ||
c906108c | 3278 | static void |
acdb74a0 | 3279 | show_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
3280 | { |
3281 | char *msg; | |
3282 | char *fpu; | |
3283 | switch (MIPS_FPU_TYPE) | |
3284 | { | |
3285 | case MIPS_FPU_SINGLE: | |
3286 | fpu = "single-precision"; | |
3287 | break; | |
3288 | case MIPS_FPU_DOUBLE: | |
3289 | fpu = "double-precision"; | |
3290 | break; | |
3291 | case MIPS_FPU_NONE: | |
3292 | fpu = "absent (none)"; | |
3293 | break; | |
3294 | } | |
3295 | if (mips_fpu_type_auto) | |
3296 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
3297 | fpu); | |
3298 | else | |
3299 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
3300 | fpu); | |
3301 | } | |
3302 | ||
3303 | ||
c906108c | 3304 | static void |
acdb74a0 | 3305 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
3306 | { |
3307 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
3308 | show_mipsfpu_command (args, from_tty); | |
3309 | } | |
3310 | ||
c906108c | 3311 | static void |
acdb74a0 | 3312 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
3313 | { |
3314 | mips_fpu_type = MIPS_FPU_SINGLE; | |
3315 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3316 | if (GDB_MULTI_ARCH) |
3317 | { | |
3318 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; | |
3319 | } | |
c906108c SS |
3320 | } |
3321 | ||
c906108c | 3322 | static void |
acdb74a0 | 3323 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
3324 | { |
3325 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
3326 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3327 | if (GDB_MULTI_ARCH) |
3328 | { | |
3329 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; | |
3330 | } | |
c906108c SS |
3331 | } |
3332 | ||
c906108c | 3333 | static void |
acdb74a0 | 3334 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
3335 | { |
3336 | mips_fpu_type = MIPS_FPU_NONE; | |
3337 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3338 | if (GDB_MULTI_ARCH) |
3339 | { | |
3340 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; | |
3341 | } | |
c906108c SS |
3342 | } |
3343 | ||
c906108c | 3344 | static void |
acdb74a0 | 3345 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
3346 | { |
3347 | mips_fpu_type_auto = 1; | |
3348 | } | |
3349 | ||
3350 | /* Command to set the processor type. */ | |
3351 | ||
3352 | void | |
acdb74a0 | 3353 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
3354 | { |
3355 | int i; | |
3356 | ||
3357 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
3358 | { | |
3359 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
3360 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3361 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
3362 | ||
3363 | /* Restore the value. */ | |
4fcf66da | 3364 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
3365 | |
3366 | return; | |
3367 | } | |
c5aa993b | 3368 | |
c906108c SS |
3369 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
3370 | { | |
3371 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
3372 | /* Restore its value. */ | |
4fcf66da | 3373 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
3374 | } |
3375 | } | |
3376 | ||
3377 | static void | |
acdb74a0 | 3378 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
3379 | { |
3380 | } | |
3381 | ||
3382 | /* Modify the actual processor type. */ | |
3383 | ||
3384 | int | |
acdb74a0 | 3385 | mips_set_processor_type (char *str) |
c906108c SS |
3386 | { |
3387 | int i, j; | |
3388 | ||
3389 | if (str == NULL) | |
3390 | return 0; | |
3391 | ||
3392 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3393 | { | |
3394 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
3395 | { | |
3396 | mips_processor_type = str; | |
cce74817 | 3397 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 3398 | return 1; |
c906108c SS |
3399 | /* FIXME tweak fpu flag too */ |
3400 | } | |
3401 | } | |
3402 | ||
3403 | return 0; | |
3404 | } | |
3405 | ||
3406 | /* Attempt to identify the particular processor model by reading the | |
3407 | processor id. */ | |
3408 | ||
3409 | char * | |
acdb74a0 | 3410 | mips_read_processor_type (void) |
c906108c SS |
3411 | { |
3412 | CORE_ADDR prid; | |
3413 | ||
3414 | prid = read_register (PRID_REGNUM); | |
3415 | ||
3416 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 3417 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
3418 | |
3419 | return NULL; | |
3420 | } | |
3421 | ||
3422 | /* Just like reinit_frame_cache, but with the right arguments to be | |
3423 | callable as an sfunc. */ | |
3424 | ||
3425 | static void | |
acdb74a0 AC |
3426 | reinit_frame_cache_sfunc (char *args, int from_tty, |
3427 | struct cmd_list_element *c) | |
c906108c SS |
3428 | { |
3429 | reinit_frame_cache (); | |
3430 | } | |
3431 | ||
3432 | int | |
acdb74a0 | 3433 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
3434 | { |
3435 | mips_extra_func_info_t proc_desc; | |
3436 | ||
3437 | /* Search for the function containing this address. Set the low bit | |
3438 | of the address when searching, in case we were given an even address | |
3439 | that is the start of a 16-bit function. If we didn't do this, | |
3440 | the search would fail because the symbol table says the function | |
3441 | starts at an odd address, i.e. 1 byte past the given address. */ | |
3442 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
3443 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
3444 | ||
3445 | /* Make an attempt to determine if this is a 16-bit function. If | |
3446 | the procedure descriptor exists and the address therein is odd, | |
3447 | it's definitely a 16-bit function. Otherwise, we have to just | |
3448 | guess that if the address passed in is odd, it's 16-bits. */ | |
3449 | if (proc_desc) | |
65c11066 MS |
3450 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
3451 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; | |
c906108c | 3452 | else |
65c11066 MS |
3453 | info->mach = pc_is_mips16 (memaddr) ? |
3454 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; | |
c906108c SS |
3455 | |
3456 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 3457 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 3458 | |
c906108c SS |
3459 | /* Call the appropriate disassembler based on the target endian-ness. */ |
3460 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3461 | return print_insn_big_mips (memaddr, info); | |
3462 | else | |
3463 | return print_insn_little_mips (memaddr, info); | |
3464 | } | |
3465 | ||
3466 | /* Old-style breakpoint macros. | |
3467 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
3468 | confused when it sees the usual MIPS breakpoint instruction. */ | |
3469 | ||
3470 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
3471 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
3472 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
3473 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
3474 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
3475 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
3476 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
3477 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
3478 | ||
3479 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
3480 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
3481 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
3482 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
3483 | (if necessary) to point to the actual memory location where the | |
3484 | breakpoint should be inserted. */ | |
3485 | ||
c5aa993b | 3486 | unsigned char * |
acdb74a0 | 3487 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c SS |
3488 | { |
3489 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3490 | { | |
3491 | if (pc_is_mips16 (*pcptr)) | |
3492 | { | |
3493 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
3494 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); | |
c5aa993b | 3495 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
3496 | return mips16_big_breakpoint; |
3497 | } | |
3498 | else | |
3499 | { | |
3500 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
3501 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
3502 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
3503 | ||
c5aa993b | 3504 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
3505 | |
3506 | if (strcmp (target_shortname, "mips") == 0) | |
3507 | return idt_big_breakpoint; | |
3508 | else if (strcmp (target_shortname, "ddb") == 0 | |
3509 | || strcmp (target_shortname, "pmon") == 0 | |
3510 | || strcmp (target_shortname, "lsi") == 0) | |
3511 | return pmon_big_breakpoint; | |
3512 | else | |
3513 | return big_breakpoint; | |
3514 | } | |
3515 | } | |
3516 | else | |
3517 | { | |
3518 | if (pc_is_mips16 (*pcptr)) | |
3519 | { | |
3520 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
3521 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); | |
c5aa993b | 3522 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
3523 | return mips16_little_breakpoint; |
3524 | } | |
3525 | else | |
3526 | { | |
3527 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
3528 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; | |
3529 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; | |
3530 | ||
c5aa993b | 3531 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
3532 | |
3533 | if (strcmp (target_shortname, "mips") == 0) | |
3534 | return idt_little_breakpoint; | |
3535 | else if (strcmp (target_shortname, "ddb") == 0 | |
3536 | || strcmp (target_shortname, "pmon") == 0 | |
3537 | || strcmp (target_shortname, "lsi") == 0) | |
3538 | return pmon_little_breakpoint; | |
3539 | else | |
3540 | return little_breakpoint; | |
3541 | } | |
3542 | } | |
3543 | } | |
3544 | ||
3545 | /* If PC is in a mips16 call or return stub, return the address of the target | |
3546 | PC, which is either the callee or the caller. There are several | |
3547 | cases which must be handled: | |
3548 | ||
3549 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 3550 | target PC is in $31 ($ra). |
c906108c | 3551 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 3552 | and the target PC is in $2. |
c906108c | 3553 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
3554 | before the jal instruction, this is effectively a call stub |
3555 | and the the target PC is in $2. Otherwise this is effectively | |
3556 | a return stub and the target PC is in $18. | |
c906108c SS |
3557 | |
3558 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
3559 | gory details. | |
3560 | ||
3561 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 3562 | */ |
c906108c SS |
3563 | |
3564 | CORE_ADDR | |
acdb74a0 | 3565 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
3566 | { |
3567 | char *name; | |
3568 | CORE_ADDR start_addr; | |
3569 | ||
3570 | /* Find the starting address and name of the function containing the PC. */ | |
3571 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3572 | return 0; | |
3573 | ||
3574 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3575 | target PC is in $31 ($ra). */ | |
3576 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3577 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 3578 | return read_signed_register (RA_REGNUM); |
c906108c SS |
3579 | |
3580 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3581 | { | |
3582 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3583 | and the target PC is in $2. */ | |
3584 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 3585 | return read_signed_register (2); |
c906108c SS |
3586 | |
3587 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
3588 | before the jal instruction, this is effectively a call stub |
3589 | and the the target PC is in $2. Otherwise this is effectively | |
3590 | a return stub and the target PC is in $18. */ | |
c906108c SS |
3591 | else if (name[19] == 's' || name[19] == 'd') |
3592 | { | |
3593 | if (pc == start_addr) | |
3594 | { | |
3595 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
3596 | stub. Such a stub for a function bar might have a name |
3597 | like __fn_stub_bar, and might look like this: | |
3598 | mfc1 $4,$f13 | |
3599 | mfc1 $5,$f12 | |
3600 | mfc1 $6,$f15 | |
3601 | mfc1 $7,$f14 | |
3602 | la $1,bar (becomes a lui/addiu pair) | |
3603 | jr $1 | |
3604 | So scan down to the lui/addi and extract the target | |
3605 | address from those two instructions. */ | |
c906108c | 3606 | |
6c997a34 | 3607 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
3608 | t_inst inst; |
3609 | int i; | |
3610 | ||
3611 | /* See if the name of the target function is __fn_stub_*. */ | |
3612 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
3613 | return target_pc; | |
3614 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
3615 | && strcmp (name, "etext") != 0 | |
3616 | && strcmp (name, "_etext") != 0) | |
3617 | return target_pc; | |
3618 | ||
3619 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
3620 | The limit on the search is arbitrarily set to 20 |
3621 | instructions. FIXME. */ | |
c906108c SS |
3622 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
3623 | { | |
c5aa993b JM |
3624 | inst = mips_fetch_instruction (target_pc); |
3625 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
3626 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
3627 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
3628 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
3629 | } |
3630 | ||
3631 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
3632 | return target_pc; | |
3633 | } | |
3634 | else | |
3635 | /* This is the 'return' part of a call stub. The return | |
3636 | address is in $r18. */ | |
6c997a34 | 3637 | return read_signed_register (18); |
c906108c SS |
3638 | } |
3639 | } | |
c5aa993b | 3640 | return 0; /* not a stub */ |
c906108c SS |
3641 | } |
3642 | ||
3643 | ||
3644 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
3645 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
3646 | ||
3647 | int | |
acdb74a0 | 3648 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
3649 | { |
3650 | CORE_ADDR start_addr; | |
3651 | ||
3652 | /* Find the starting address of the function containing the PC. If the | |
3653 | caller didn't give us a name, look it up at the same time. */ | |
3654 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
3655 | return 0; | |
3656 | ||
3657 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3658 | { | |
3659 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
3660 | if (name[19] >= '0' && name[19] <= '9') | |
3661 | return 1; | |
3662 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 3663 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
3664 | else if (name[19] == 's' || name[19] == 'd') |
3665 | return pc == start_addr; | |
3666 | } | |
3667 | ||
c5aa993b | 3668 | return 0; /* not a stub */ |
c906108c SS |
3669 | } |
3670 | ||
3671 | ||
3672 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
3673 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
3674 | ||
3675 | int | |
acdb74a0 | 3676 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
3677 | { |
3678 | CORE_ADDR start_addr; | |
3679 | ||
3680 | /* Find the starting address of the function containing the PC. */ | |
3681 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
3682 | return 0; | |
3683 | ||
3684 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
3685 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3686 | || strcmp (name, "__mips16_ret_df") == 0) | |
3687 | return 1; | |
3688 | ||
3689 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 3690 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
3691 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
3692 | && (name[19] == 's' || name[19] == 'd') | |
3693 | && pc != start_addr) | |
3694 | return 1; | |
3695 | ||
c5aa993b | 3696 | return 0; /* not a stub */ |
c906108c SS |
3697 | } |
3698 | ||
3699 | ||
3700 | /* Return non-zero if the PC is in a library helper function that should | |
3701 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
3702 | ||
3703 | int | |
acdb74a0 | 3704 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
3705 | { |
3706 | char *name; | |
3707 | ||
3708 | /* Find the starting address and name of the function containing the PC. */ | |
3709 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
3710 | return 0; | |
3711 | ||
3712 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
3713 | that we want to ignore. */ | |
3714 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
3715 | || strcmp (name, "__mips16_ret_df") == 0); | |
3716 | } | |
3717 | ||
3718 | ||
3719 | /* Return a location where we can set a breakpoint that will be hit | |
3720 | when an inferior function call returns. This is normally the | |
3721 | program's entry point. Executables that don't have an entry | |
3722 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
3723 | whose address is the location where the breakpoint should be placed. */ | |
3724 | ||
3725 | CORE_ADDR | |
acdb74a0 | 3726 | mips_call_dummy_address (void) |
c906108c SS |
3727 | { |
3728 | struct minimal_symbol *sym; | |
3729 | ||
3730 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
3731 | if (sym) | |
3732 | return SYMBOL_VALUE_ADDRESS (sym); | |
3733 | else | |
3734 | return entry_point_address (); | |
3735 | } | |
3736 | ||
3737 | ||
9dcb560c | 3738 | /* If the current gcc for this target does not produce correct debugging |
b9a8e3bf JB |
3739 | information for float parameters, both prototyped and unprototyped, then |
3740 | define this macro. This forces gdb to always assume that floats are | |
3741 | passed as doubles and then converted in the callee. | |
3742 | ||
3743 | For the mips chip, it appears that the debug info marks the parameters as | |
3744 | floats regardless of whether the function is prototyped, but the actual | |
3745 | values are passed as doubles for the non-prototyped case and floats for | |
3746 | the prototyped case. Thus we choose to make the non-prototyped case work | |
3747 | for C and break the prototyped case, since the non-prototyped case is | |
3748 | probably much more common. (FIXME). */ | |
3749 | ||
3750 | static int | |
3751 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
3752 | { | |
3753 | return current_language->la_language == language_c; | |
3754 | } | |
3755 | ||
47a8d4ba AC |
3756 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
3757 | the register stored on the stack (32) is different to its real raw | |
3758 | size (64). The below ensures that registers are fetched from the | |
3759 | stack using their ABI size and then stored into the RAW_BUFFER | |
3760 | using their raw size. | |
3761 | ||
3762 | The alternative to adding this function would be to add an ABI | |
3763 | macro - REGISTER_STACK_SIZE(). */ | |
3764 | ||
3765 | static void | |
acdb74a0 AC |
3766 | mips_get_saved_register (char *raw_buffer, |
3767 | int *optimized, | |
3768 | CORE_ADDR *addrp, | |
3769 | struct frame_info *frame, | |
3770 | int regnum, | |
3771 | enum lval_type *lval) | |
47a8d4ba AC |
3772 | { |
3773 | CORE_ADDR addr; | |
3774 | ||
3775 | if (!target_has_registers) | |
3776 | error ("No registers."); | |
3777 | ||
3778 | /* Normal systems don't optimize out things with register numbers. */ | |
3779 | if (optimized != NULL) | |
3780 | *optimized = 0; | |
3781 | addr = find_saved_register (frame, regnum); | |
3782 | if (addr != 0) | |
3783 | { | |
3784 | if (lval != NULL) | |
3785 | *lval = lval_memory; | |
3786 | if (regnum == SP_REGNUM) | |
3787 | { | |
3788 | if (raw_buffer != NULL) | |
3789 | { | |
3790 | /* Put it back in target format. */ | |
3791 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
3792 | (LONGEST) addr); | |
3793 | } | |
3794 | if (addrp != NULL) | |
3795 | *addrp = 0; | |
3796 | return; | |
3797 | } | |
3798 | if (raw_buffer != NULL) | |
3799 | { | |
3800 | LONGEST val; | |
3801 | if (regnum < 32) | |
3802 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
3803 | saved. */ | |
3804 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
3805 | else | |
3806 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
3807 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
3808 | } | |
3809 | } | |
3810 | else | |
3811 | { | |
3812 | if (lval != NULL) | |
3813 | *lval = lval_register; | |
3814 | addr = REGISTER_BYTE (regnum); | |
3815 | if (raw_buffer != NULL) | |
3816 | read_register_gen (regnum, raw_buffer); | |
3817 | } | |
3818 | if (addrp != NULL) | |
3819 | *addrp = addr; | |
3820 | } | |
2acceee2 | 3821 | |
f7b9e9fc AC |
3822 | /* Immediately after a function call, return the saved pc. |
3823 | Can't always go through the frames for this because on some machines | |
3824 | the new frame is not set up until the new function executes | |
3825 | some instructions. */ | |
3826 | ||
3827 | static CORE_ADDR | |
3828 | mips_saved_pc_after_call (struct frame_info *frame) | |
3829 | { | |
6c997a34 | 3830 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
3831 | } |
3832 | ||
3833 | ||
88c72b7d AC |
3834 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
3835 | REGNUM */ | |
3836 | ||
3837 | static int | |
3838 | mips_stab_reg_to_regnum (int num) | |
3839 | { | |
3840 | if (num < 32) | |
3841 | return num; | |
3842 | else | |
3843 | return num + FP0_REGNUM - 38; | |
3844 | } | |
3845 | ||
3846 | /* Convert a ecoff register number to a gdb REGNUM */ | |
3847 | ||
3848 | static int | |
3849 | mips_ecoff_reg_to_regnum (int num) | |
3850 | { | |
3851 | if (num < 32) | |
3852 | return num; | |
3853 | else | |
3854 | return num + FP0_REGNUM - 32; | |
3855 | } | |
3856 | ||
c2d11a7d | 3857 | static struct gdbarch * |
acdb74a0 AC |
3858 | mips_gdbarch_init (struct gdbarch_info info, |
3859 | struct gdbarch_list *arches) | |
c2d11a7d JM |
3860 | { |
3861 | static LONGEST mips_call_dummy_words[] = | |
3862 | {0}; | |
3863 | struct gdbarch *gdbarch; | |
3864 | struct gdbarch_tdep *tdep; | |
3865 | int elf_flags; | |
0dadbba0 | 3866 | enum mips_abi mips_abi; |
c2d11a7d JM |
3867 | |
3868 | /* Extract the elf_flags if available */ | |
3869 | if (info.abfd != NULL | |
3870 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3871 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
3872 | else | |
3873 | elf_flags = 0; | |
3874 | ||
0dadbba0 AC |
3875 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
3876 | switch ((elf_flags & EF_MIPS_ABI)) | |
3877 | { | |
3878 | case E_MIPS_ABI_O32: | |
3879 | mips_abi = MIPS_ABI_O32; | |
3880 | break; | |
3881 | case E_MIPS_ABI_O64: | |
3882 | mips_abi = MIPS_ABI_O64; | |
3883 | break; | |
3884 | case E_MIPS_ABI_EABI32: | |
3885 | mips_abi = MIPS_ABI_EABI32; | |
3886 | break; | |
3887 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 3888 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
3889 | break; |
3890 | default: | |
acdb74a0 AC |
3891 | if ((elf_flags & EF_MIPS_ABI2)) |
3892 | mips_abi = MIPS_ABI_N32; | |
3893 | else | |
3894 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
3895 | break; |
3896 | } | |
acdb74a0 | 3897 | |
bf64bfd6 AC |
3898 | /* Try the architecture for any hint of the corect ABI */ |
3899 | if (mips_abi == MIPS_ABI_UNKNOWN | |
3900 | && info.bfd_arch_info != NULL | |
3901 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
3902 | { | |
3903 | switch (info.bfd_arch_info->mach) | |
3904 | { | |
3905 | case bfd_mach_mips3900: | |
3906 | mips_abi = MIPS_ABI_EABI32; | |
3907 | break; | |
3908 | case bfd_mach_mips4100: | |
3909 | case bfd_mach_mips5000: | |
3910 | mips_abi = MIPS_ABI_EABI64; | |
3911 | break; | |
3912 | } | |
3913 | } | |
0dadbba0 AC |
3914 | #ifdef MIPS_DEFAULT_ABI |
3915 | if (mips_abi == MIPS_ABI_UNKNOWN) | |
3916 | mips_abi = MIPS_DEFAULT_ABI; | |
3917 | #endif | |
4b9b3959 AC |
3918 | |
3919 | if (gdbarch_debug) | |
3920 | { | |
3921 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 3922 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 3923 | elf_flags); |
4b9b3959 AC |
3924 | fprintf_unfiltered (gdb_stdlog, |
3925 | "mips_gdbarch_init: mips_abi = %d\n", | |
3926 | mips_abi); | |
3927 | } | |
0dadbba0 | 3928 | |
c2d11a7d JM |
3929 | /* try to find a pre-existing architecture */ |
3930 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3931 | arches != NULL; | |
3932 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3933 | { | |
3934 | /* MIPS needs to be pedantic about which ABI the object is | |
3935 | using. */ | |
9103eae0 | 3936 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 3937 | continue; |
9103eae0 | 3938 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 3939 | continue; |
c2d11a7d JM |
3940 | return arches->gdbarch; |
3941 | } | |
3942 | ||
3943 | /* Need a new architecture. Fill in a target specific vector. */ | |
3944 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3945 | gdbarch = gdbarch_alloc (&info, tdep); | |
3946 | tdep->elf_flags = elf_flags; | |
3947 | ||
3948 | /* Initially set everything according to the ABI. */ | |
3949 | set_gdbarch_short_bit (gdbarch, 16); | |
3950 | set_gdbarch_int_bit (gdbarch, 32); | |
3951 | set_gdbarch_float_bit (gdbarch, 32); | |
3952 | set_gdbarch_double_bit (gdbarch, 64); | |
3953 | set_gdbarch_long_double_bit (gdbarch, 64); | |
0dadbba0 AC |
3954 | tdep->mips_abi = mips_abi; |
3955 | switch (mips_abi) | |
c2d11a7d | 3956 | { |
0dadbba0 | 3957 | case MIPS_ABI_O32: |
acdb74a0 | 3958 | tdep->mips_abi_string = "o32"; |
a5ea2558 | 3959 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 3960 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 3961 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
3962 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
3963 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
0dadbba0 | 3964 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 3965 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 3966 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
3967 | set_gdbarch_long_bit (gdbarch, 32); |
3968 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3969 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3970 | break; | |
0dadbba0 | 3971 | case MIPS_ABI_O64: |
acdb74a0 | 3972 | tdep->mips_abi_string = "o64"; |
a5ea2558 | 3973 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 3974 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 3975 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
3976 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
3977 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
0dadbba0 | 3978 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 3979 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 3980 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
3981 | set_gdbarch_long_bit (gdbarch, 32); |
3982 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3983 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3984 | break; | |
0dadbba0 | 3985 | case MIPS_ABI_EABI32: |
acdb74a0 | 3986 | tdep->mips_abi_string = "eabi32"; |
a5ea2558 | 3987 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 3988 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 3989 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
3990 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
3991 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 3992 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 3993 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 3994 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
3995 | set_gdbarch_long_bit (gdbarch, 32); |
3996 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3997 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3998 | break; | |
0dadbba0 | 3999 | case MIPS_ABI_EABI64: |
acdb74a0 | 4000 | tdep->mips_abi_string = "eabi64"; |
a5ea2558 | 4001 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 4002 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 4003 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
4004 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4005 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4006 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4007 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 4008 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4009 | set_gdbarch_long_bit (gdbarch, 64); |
4010 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4011 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4012 | break; | |
0dadbba0 | 4013 | case MIPS_ABI_N32: |
acdb74a0 | 4014 | tdep->mips_abi_string = "n32"; |
0dadbba0 AC |
4015 | tdep->mips_default_saved_regsize = 4; |
4016 | tdep->mips_default_stack_argsize = 8; | |
4017 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
4018 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4019 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4020 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4021 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4022 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
4023 | set_gdbarch_long_bit (gdbarch, 32); |
4024 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4025 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4026 | break; | |
c2d11a7d | 4027 | default: |
acdb74a0 | 4028 | tdep->mips_abi_string = "default"; |
a5ea2558 | 4029 | tdep->mips_default_saved_regsize = MIPS_REGSIZE; |
0dadbba0 | 4030 | tdep->mips_default_stack_argsize = MIPS_REGSIZE; |
c2d11a7d | 4031 | tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8); |
acdb74a0 AC |
4032 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4033 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4034 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 4035 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4036 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4037 | set_gdbarch_long_bit (gdbarch, 32); |
4038 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4039 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4040 | break; | |
4041 | } | |
4042 | ||
a5ea2558 AC |
4043 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
4044 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
4045 | comment: | |
4046 | ||
4047 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
4048 | flag in object files because to do so would make it impossible to | |
4049 | link with libraries compiled without "-gp32". This is | |
4050 | unnecessarily restrictive. | |
4051 | ||
4052 | We could solve this problem by adding "-gp32" multilibs to gcc, | |
4053 | but to set this flag before gcc is built with such multilibs will | |
4054 | break too many systems.'' | |
4055 | ||
4056 | But even more unhelpfully, the default linker output target for | |
4057 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
4058 | for 64-bit programs - you need to change the ABI to change this, | |
4059 | and not all gcc targets support that currently. Therefore using | |
4060 | this flag to detect 32-bit mode would do the wrong thing given | |
4061 | the current gcc - it would make GDB treat these 64-bit programs | |
4062 | as 32-bit programs by default. */ | |
4063 | ||
c2d11a7d JM |
4064 | /* enable/disable the MIPS FPU */ |
4065 | if (!mips_fpu_type_auto) | |
4066 | tdep->mips_fpu_type = mips_fpu_type; | |
4067 | else if (info.bfd_arch_info != NULL | |
4068 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4069 | switch (info.bfd_arch_info->mach) | |
4070 | { | |
b0069a17 | 4071 | case bfd_mach_mips3900: |
c2d11a7d | 4072 | case bfd_mach_mips4100: |
ed9a39eb | 4073 | case bfd_mach_mips4111: |
c2d11a7d JM |
4074 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
4075 | break; | |
bf64bfd6 AC |
4076 | case bfd_mach_mips4650: |
4077 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
4078 | break; | |
c2d11a7d JM |
4079 | default: |
4080 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4081 | break; | |
4082 | } | |
4083 | else | |
4084 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4085 | ||
4086 | /* MIPS version of register names. NOTE: At present the MIPS | |
4087 | register name management is part way between the old - | |
4088 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
4089 | Further work on it is required. */ | |
4090 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6c997a34 | 4091 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d JM |
4092 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
4093 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
4094 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); | |
4095 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); | |
4096 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4097 | ||
88c72b7d AC |
4098 | /* Map debug register numbers onto internal register numbers. */ |
4099 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); | |
4100 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); | |
4101 | ||
c2d11a7d JM |
4102 | /* Initialize a frame */ |
4103 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
4104 | ||
4105 | /* MIPS version of CALL_DUMMY */ | |
4106 | ||
4107 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4108 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
4109 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
4110 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
4111 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
4112 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
4113 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
4114 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4115 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
4116 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
4117 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
4118 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
4119 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
4120 | set_gdbarch_push_arguments (gdbarch, mips_push_arguments); | |
4121 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
b9a8e3bf | 4122 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 4123 | |
c4093a6a | 4124 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
47a8d4ba | 4125 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 4126 | |
f7b9e9fc AC |
4127 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
4128 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4129 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
4130 | set_gdbarch_ieee_float (gdbarch, 1); | |
4131 | ||
4132 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
4133 | set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); | |
4134 | ||
4b9b3959 AC |
4135 | return gdbarch; |
4136 | } | |
4137 | ||
4138 | static void | |
4139 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4140 | { | |
4141 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4142 | if (tdep != NULL) | |
c2d11a7d | 4143 | { |
acdb74a0 AC |
4144 | int ef_mips_arch; |
4145 | int ef_mips_32bitmode; | |
4146 | /* determine the ISA */ | |
4147 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
4148 | { | |
4149 | case E_MIPS_ARCH_1: | |
4150 | ef_mips_arch = 1; | |
4151 | break; | |
4152 | case E_MIPS_ARCH_2: | |
4153 | ef_mips_arch = 2; | |
4154 | break; | |
4155 | case E_MIPS_ARCH_3: | |
4156 | ef_mips_arch = 3; | |
4157 | break; | |
4158 | case E_MIPS_ARCH_4: | |
4159 | ef_mips_arch = 0; | |
4160 | break; | |
4161 | default: | |
4162 | break; | |
4163 | } | |
4164 | /* determine the size of a pointer */ | |
4165 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
4166 | fprintf_unfiltered (file, |
4167 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 4168 | tdep->elf_flags); |
4b9b3959 | 4169 | fprintf_unfiltered (file, |
acdb74a0 AC |
4170 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
4171 | ef_mips_32bitmode); | |
4172 | fprintf_unfiltered (file, | |
4173 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
4174 | ef_mips_arch); | |
4175 | fprintf_unfiltered (file, | |
4176 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
4177 | tdep->mips_abi, | |
4178 | tdep->mips_abi_string); | |
4014092b AC |
4179 | fprintf_unfiltered (file, |
4180 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
4181 | mips_mask_address_p (), | |
4182 | tdep->default_mask_address_p); | |
c2d11a7d | 4183 | } |
4b9b3959 AC |
4184 | fprintf_unfiltered (file, |
4185 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4186 | FP_REGISTER_DOUBLE); | |
4187 | fprintf_unfiltered (file, | |
4188 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
4189 | MIPS_DEFAULT_FPU_TYPE, | |
4190 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4191 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4192 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4193 | : "???")); | |
4194 | fprintf_unfiltered (file, | |
4195 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
4196 | MIPS_EABI); | |
4197 | fprintf_unfiltered (file, | |
acdb74a0 AC |
4198 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
4199 | MIPS_LAST_FP_ARG_REGNUM, | |
4200 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
4201 | fprintf_unfiltered (file, |
4202 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
4203 | MIPS_FPU_TYPE, | |
4204 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4205 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4206 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4207 | : "???")); | |
4208 | fprintf_unfiltered (file, | |
4209 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
4210 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
4211 | fprintf_unfiltered (file, |
4212 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4213 | FP_REGISTER_DOUBLE); | |
4214 | fprintf_unfiltered (file, | |
4215 | "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n", | |
4216 | MIPS_REGS_HAVE_HOME_P); | |
4217 | fprintf_unfiltered (file, | |
4218 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
4219 | MIPS_DEFAULT_STACK_ARGSIZE); | |
4220 | fprintf_unfiltered (file, | |
4221 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
4222 | MIPS_STACK_ARGSIZE); | |
4223 | fprintf_unfiltered (file, | |
4224 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
4225 | MIPS_REGSIZE); | |
2475bac3 AC |
4226 | fprintf_unfiltered (file, |
4227 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
4228 | A0_REGNUM); | |
4229 | fprintf_unfiltered (file, | |
4230 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
4231 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
4232 | fprintf_unfiltered (file, | |
4233 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
4234 | XSTRING (ATTACH_DETACH)); | |
4235 | fprintf_unfiltered (file, | |
4236 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
4237 | BADVADDR_REGNUM); | |
4238 | fprintf_unfiltered (file, | |
4239 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
4240 | fprintf_unfiltered (file, | |
4241 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
4242 | CAUSE_REGNUM); | |
4243 | fprintf_unfiltered (file, | |
4244 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
4245 | CPLUS_MARKER); | |
4246 | fprintf_unfiltered (file, | |
4247 | "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n", | |
4248 | DEFAULT_MIPS_TYPE); | |
4249 | fprintf_unfiltered (file, | |
4250 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
4251 | XSTRING (DO_REGISTERS_INFO)); | |
4252 | fprintf_unfiltered (file, | |
4253 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
4254 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
4255 | fprintf_unfiltered (file, | |
4256 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
4257 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
4258 | fprintf_unfiltered (file, | |
4259 | "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n", | |
4260 | XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM))); | |
4261 | fprintf_unfiltered (file, | |
4262 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
4263 | FCRCS_REGNUM); | |
4264 | fprintf_unfiltered (file, | |
4265 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
4266 | FCRIR_REGNUM); | |
4267 | fprintf_unfiltered (file, | |
4268 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
4269 | FIRST_EMBED_REGNUM); | |
4270 | fprintf_unfiltered (file, | |
4271 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
4272 | FPA0_REGNUM); | |
4273 | fprintf_unfiltered (file, | |
4274 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
4275 | GDB_TARGET_IS_MIPS64); | |
4276 | fprintf_unfiltered (file, | |
4277 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
4278 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
4279 | fprintf_unfiltered (file, | |
4280 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
4281 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
4282 | fprintf_unfiltered (file, | |
4283 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
4284 | GEN_REG_SAVE_MASK); | |
4285 | fprintf_unfiltered (file, | |
4286 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
4287 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
4288 | fprintf_unfiltered (file, | |
4289 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
4290 | HI_REGNUM); | |
4291 | fprintf_unfiltered (file, | |
4292 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
4293 | fprintf_unfiltered (file, | |
4294 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
4295 | fprintf_unfiltered (file, | |
4296 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
4297 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
4298 | fprintf_unfiltered (file, | |
4299 | "mips_dump_tdep: INIT_FRAME_PC # %s\n", | |
4300 | XSTRING (INIT_FRAME_PC (FROMLEAF, PREV))); | |
4301 | fprintf_unfiltered (file, | |
4302 | "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n", | |
4303 | XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF, PREV))); | |
4304 | fprintf_unfiltered (file, | |
4305 | "mips_dump_tdep: IN_SIGTRAMP # %s\n", | |
4306 | XSTRING (IN_SIGTRAMP (PC, NAME))); | |
4307 | fprintf_unfiltered (file, | |
4308 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
4309 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
4310 | fprintf_unfiltered (file, | |
4311 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
4312 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
4313 | fprintf_unfiltered (file, | |
4314 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
4315 | fprintf_unfiltered (file, | |
4316 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
4317 | LAST_EMBED_REGNUM); | |
4318 | fprintf_unfiltered (file, | |
4319 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
4320 | fprintf_unfiltered (file, | |
4321 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
4322 | LO_REGNUM); | |
4323 | #ifdef MACHINE_CPROC_FP_OFFSET | |
4324 | fprintf_unfiltered (file, | |
4325 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
4326 | MACHINE_CPROC_FP_OFFSET); | |
4327 | #endif | |
4328 | #ifdef MACHINE_CPROC_PC_OFFSET | |
4329 | fprintf_unfiltered (file, | |
4330 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
4331 | MACHINE_CPROC_PC_OFFSET); | |
4332 | #endif | |
4333 | #ifdef MACHINE_CPROC_SP_OFFSET | |
4334 | fprintf_unfiltered (file, | |
4335 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
4336 | MACHINE_CPROC_SP_OFFSET); | |
4337 | #endif | |
4338 | fprintf_unfiltered (file, | |
4339 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
4340 | fprintf_unfiltered (file, | |
4341 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
4342 | fprintf_unfiltered (file, | |
4343 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
4344 | MIPS16_INSTLEN); | |
4345 | fprintf_unfiltered (file, | |
4346 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
4347 | fprintf_unfiltered (file, | |
4348 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
4349 | fprintf_unfiltered (file, | |
4350 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
4351 | fprintf_unfiltered (file, | |
4352 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
4353 | MIPS_INSTLEN); | |
4354 | fprintf_unfiltered (file, | |
acdb74a0 AC |
4355 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
4356 | MIPS_LAST_ARG_REGNUM, | |
4357 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
4358 | fprintf_unfiltered (file, |
4359 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
4360 | MIPS_NUMREGS); | |
4361 | fprintf_unfiltered (file, | |
4362 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
4363 | fprintf_unfiltered (file, | |
4364 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
4365 | MIPS_SAVED_REGSIZE); | |
4366 | fprintf_unfiltered (file, | |
4367 | "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n"); | |
4368 | fprintf_unfiltered (file, | |
4369 | "mips_dump_tdep: MSYMBOL_SIZE # %s\n", | |
4370 | XSTRING (MSYMBOL_SIZE (MSYM))); | |
4371 | fprintf_unfiltered (file, | |
4372 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
4373 | fprintf_unfiltered (file, | |
4374 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
4375 | fprintf_unfiltered (file, | |
4376 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
4377 | fprintf_unfiltered (file, | |
4378 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
4379 | fprintf_unfiltered (file, | |
4380 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
4381 | PRID_REGNUM); | |
4382 | fprintf_unfiltered (file, | |
4383 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
4384 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
4385 | fprintf_unfiltered (file, | |
4386 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
4387 | fprintf_unfiltered (file, | |
4388 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
4389 | fprintf_unfiltered (file, | |
4390 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
4391 | fprintf_unfiltered (file, | |
4392 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
4393 | fprintf_unfiltered (file, | |
4394 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
4395 | fprintf_unfiltered (file, | |
4396 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
4397 | fprintf_unfiltered (file, | |
4398 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
4399 | fprintf_unfiltered (file, | |
4400 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
4401 | fprintf_unfiltered (file, | |
4402 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
4403 | fprintf_unfiltered (file, | |
4404 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
4405 | fprintf_unfiltered (file, | |
4406 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
4407 | fprintf_unfiltered (file, | |
4408 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
4409 | fprintf_unfiltered (file, | |
4410 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
4411 | PS_REGNUM); | |
4412 | fprintf_unfiltered (file, | |
4413 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
4414 | PUSH_FP_REGNUM); | |
4415 | fprintf_unfiltered (file, | |
4416 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
4417 | RA_REGNUM); | |
4418 | fprintf_unfiltered (file, | |
4419 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
4420 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4421 | fprintf_unfiltered (file, | |
4422 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
4423 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4424 | fprintf_unfiltered (file, | |
4425 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
4426 | fprintf_unfiltered (file, | |
4427 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
4428 | fprintf_unfiltered (file, | |
4429 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
4430 | #ifdef SAVED_BYTES | |
4431 | fprintf_unfiltered (file, | |
4432 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
4433 | SAVED_BYTES); | |
4434 | #endif | |
4435 | #ifdef SAVED_FP | |
4436 | fprintf_unfiltered (file, | |
4437 | "mips_dump_tdep: SAVED_FP = %d\n", | |
4438 | SAVED_FP); | |
4439 | #endif | |
4440 | #ifdef SAVED_PC | |
4441 | fprintf_unfiltered (file, | |
4442 | "mips_dump_tdep: SAVED_PC = %d\n", | |
4443 | SAVED_PC); | |
4444 | #endif | |
4445 | fprintf_unfiltered (file, | |
4446 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
4447 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
4448 | fprintf_unfiltered (file, | |
4449 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
4450 | fprintf_unfiltered (file, | |
4451 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
4452 | SIGFRAME_BASE); | |
4453 | fprintf_unfiltered (file, | |
4454 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
4455 | SIGFRAME_FPREGSAVE_OFF); | |
4456 | fprintf_unfiltered (file, | |
4457 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
4458 | SIGFRAME_PC_OFF); | |
4459 | fprintf_unfiltered (file, | |
4460 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
4461 | SIGFRAME_REGSAVE_OFF); | |
4462 | fprintf_unfiltered (file, | |
4463 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
4464 | SIGFRAME_REG_SIZE); | |
4465 | fprintf_unfiltered (file, | |
4466 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
4467 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
4468 | fprintf_unfiltered (file, | |
4469 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
4470 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
4471 | fprintf_unfiltered (file, | |
4472 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n", | |
4473 | SOFTWARE_SINGLE_STEP_P); | |
4474 | fprintf_unfiltered (file, | |
4475 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n", | |
4476 | SOFTWARE_SINGLE_STEP_P); | |
4477 | fprintf_unfiltered (file, | |
4478 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
4479 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
4480 | #ifdef STACK_END_ADDR | |
4481 | fprintf_unfiltered (file, | |
4482 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
4483 | STACK_END_ADDR); | |
4484 | #endif | |
4485 | fprintf_unfiltered (file, | |
4486 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
4487 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
4488 | fprintf_unfiltered (file, | |
4489 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
4490 | STEP_SKIPS_DELAY_P); | |
4491 | fprintf_unfiltered (file, | |
4492 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
4493 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
4494 | fprintf_unfiltered (file, | |
4495 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
4496 | T9_REGNUM); | |
4497 | fprintf_unfiltered (file, | |
4498 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
4499 | fprintf_unfiltered (file, | |
4500 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
4501 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
4502 | fprintf_unfiltered (file, | |
4503 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
4504 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
4505 | fprintf_unfiltered (file, | |
4506 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
4507 | fprintf_unfiltered (file, | |
4508 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
4509 | XSTRING (TM_PRINT_INSN_MACH)); | |
4510 | #ifdef TRACE_CLEAR | |
4511 | fprintf_unfiltered (file, | |
4512 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
4513 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
4514 | #endif | |
4515 | #ifdef TRACE_FLAVOR | |
4516 | fprintf_unfiltered (file, | |
4517 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
4518 | TRACE_FLAVOR); | |
4519 | #endif | |
4520 | #ifdef TRACE_FLAVOR_SIZE | |
4521 | fprintf_unfiltered (file, | |
4522 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
4523 | TRACE_FLAVOR_SIZE); | |
4524 | #endif | |
4525 | #ifdef TRACE_SET | |
4526 | fprintf_unfiltered (file, | |
4527 | "mips_dump_tdep: TRACE_SET # %s\n", | |
4528 | XSTRING (TRACE_SET (X,STATE))); | |
4529 | #endif | |
4530 | fprintf_unfiltered (file, | |
4531 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
4532 | #ifdef UNUSED_REGNUM | |
4533 | fprintf_unfiltered (file, | |
4534 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
4535 | UNUSED_REGNUM); | |
4536 | #endif | |
4537 | fprintf_unfiltered (file, | |
4538 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
4539 | V0_REGNUM); | |
4540 | fprintf_unfiltered (file, | |
4541 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
4542 | (long) VM_MIN_ADDRESS); | |
4543 | #ifdef VX_NUM_REGS | |
4544 | fprintf_unfiltered (file, | |
4545 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
4546 | VX_NUM_REGS); | |
4547 | #endif | |
4548 | fprintf_unfiltered (file, | |
4549 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
4550 | ZERO_REGNUM); | |
4551 | fprintf_unfiltered (file, | |
4552 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
4553 | _PROC_MAGIC_); | |
c2d11a7d JM |
4554 | } |
4555 | ||
c906108c | 4556 | void |
acdb74a0 | 4557 | _initialize_mips_tdep (void) |
c906108c SS |
4558 | { |
4559 | static struct cmd_list_element *mipsfpulist = NULL; | |
4560 | struct cmd_list_element *c; | |
4561 | ||
4b9b3959 | 4562 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 4563 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
4564 | tm_print_insn = gdb_print_insn_mips; |
4565 | ||
a5ea2558 AC |
4566 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
4567 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
4568 | "Various MIPS specific commands.", | |
4569 | &setmipscmdlist, "set mips ", 0, &setlist); | |
4570 | ||
4571 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
4572 | "Various MIPS specific commands.", | |
4573 | &showmipscmdlist, "show mips ", 0, &showlist); | |
4574 | ||
4575 | /* Allow the user to override the saved register size. */ | |
4576 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
4577 | class_obscure, |
4578 | size_enums, | |
4579 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
4580 | Set size of general purpose registers saved on the stack.\n\ |
4581 | This option can be set to one of:\n\ | |
4582 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
4583 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
4584 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
4585 | saved GP register size from information contained in the executable.\n\ | |
4586 | (default: auto)", | |
1ed2a135 | 4587 | &setmipscmdlist), |
a5ea2558 AC |
4588 | &showmipscmdlist); |
4589 | ||
d929b26f AC |
4590 | /* Allow the user to override the argument stack size. */ |
4591 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
4592 | class_obscure, | |
4593 | size_enums, | |
1ed2a135 | 4594 | &mips_stack_argsize_string, "\ |
d929b26f AC |
4595 | Set the amount of stack space reserved for each argument.\n\ |
4596 | This option can be set to one of:\n\ | |
4597 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
4598 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
4599 | auto - Allow GDB to determine the correct setting from the current\n\ | |
4600 | target and executable (default)", | |
4601 | &setmipscmdlist), | |
4602 | &showmipscmdlist); | |
4603 | ||
c906108c SS |
4604 | /* Let the user turn off floating point and set the fence post for |
4605 | heuristic_proc_start. */ | |
4606 | ||
4607 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
4608 | "Set use of MIPS floating-point coprocessor.", | |
4609 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
4610 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
4611 | "Select single-precision MIPS floating-point coprocessor.", | |
4612 | &mipsfpulist); | |
4613 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 4614 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
4615 | &mipsfpulist); |
4616 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
4617 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
4618 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
4619 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
4620 | "Select no MIPS floating-point coprocessor.", | |
4621 | &mipsfpulist); | |
4622 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
4623 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
4624 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
4625 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
4626 | "Select MIPS floating-point coprocessor automatically.", | |
4627 | &mipsfpulist); | |
4628 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
4629 | "Show current use of MIPS floating-point coprocessor target.", | |
4630 | &showlist); | |
4631 | ||
c2d11a7d | 4632 | #if !GDB_MULTI_ARCH |
c906108c SS |
4633 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
4634 | (char *) &tmp_mips_processor_type, | |
4635 | "Set the type of MIPS processor in use.\n\ | |
4636 | Set this to be able to access processor-type-specific registers.\n\ | |
4637 | ", | |
4638 | &setlist); | |
4639 | c->function.cfunc = mips_set_processor_type_command; | |
4640 | c = add_show_from_set (c, &showlist); | |
4641 | c->function.cfunc = mips_show_processor_type_command; | |
4642 | ||
4fcf66da AC |
4643 | tmp_mips_processor_type = xstrdup (DEFAULT_MIPS_TYPE); |
4644 | mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE), 0); | |
c2d11a7d | 4645 | #endif |
c906108c SS |
4646 | |
4647 | /* We really would like to have both "0" and "unlimited" work, but | |
4648 | command.c doesn't deal with that. So make it a var_zinteger | |
4649 | because the user can always use "999999" or some such for unlimited. */ | |
4650 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
4651 | (char *) &heuristic_fence_post, | |
4652 | "\ | |
4653 | Set the distance searched for the start of a function.\n\ | |
4654 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
4655 | program for the start of a function. This command sets the distance of the\n\ | |
4656 | search. The only need to set it is when debugging a stripped executable.", | |
4657 | &setlist); | |
4658 | /* We need to throw away the frame cache when we set this, since it | |
4659 | might change our ability to get backtraces. */ | |
4660 | c->function.sfunc = reinit_frame_cache_sfunc; | |
4661 | add_show_from_set (c, &showlist); | |
4662 | ||
4663 | /* Allow the user to control whether the upper bits of 64-bit | |
4664 | addresses should be zeroed. */ | |
4014092b AC |
4665 | c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, |
4666 | "Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
4667 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\ | |
4668 | the correct value.\n", | |
4669 | &setmipscmdlist); | |
4670 | add_cmd ("mask-address", no_class, show_mask_address, | |
4671 | "Show current mask-address value", &showmipscmdlist); | |
43e526b9 JM |
4672 | |
4673 | /* Allow the user to control the size of 32 bit registers within the | |
4674 | raw remote packet. */ | |
4675 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
4676 | class_obscure, | |
4677 | var_boolean, | |
4678 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
4679 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
4680 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
4681 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
4682 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
4683 | &setlist), | |
4684 | &showlist); | |
9ace0497 AC |
4685 | |
4686 | /* Debug this files internals. */ | |
4687 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
4688 | &mips_debug, "Set mips debugging.\n\ | |
4689 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
4690 | &showdebuglist); | |
c906108c | 4691 | } |
9ace0497 | 4692 |