Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a AC |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
4 | 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. | |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
c906108c SS |
42 | |
43 | #include "opcode/mips.h" | |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
c906108c | 47 | |
dd824b04 DJ |
48 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
49 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
50 | #define ST0_FR (1 << 26) | |
51 | ||
b0069a17 AC |
52 | /* The sizes of floating point registers. */ |
53 | ||
54 | enum | |
55 | { | |
56 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
57 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
58 | }; | |
59 | ||
0dadbba0 AC |
60 | /* All the possible MIPS ABIs. */ |
61 | ||
62 | enum mips_abi | |
63 | { | |
2e4ebe70 | 64 | MIPS_ABI_UNKNOWN = 0, |
0dadbba0 AC |
65 | MIPS_ABI_N32, |
66 | MIPS_ABI_O32, | |
28d169de | 67 | MIPS_ABI_N64, |
0dadbba0 AC |
68 | MIPS_ABI_O64, |
69 | MIPS_ABI_EABI32, | |
2e4ebe70 DJ |
70 | MIPS_ABI_EABI64, |
71 | MIPS_ABI_LAST | |
0dadbba0 AC |
72 | }; |
73 | ||
2e4ebe70 DJ |
74 | static const char *mips_abi_string; |
75 | ||
76 | static const char *mips_abi_strings[] = { | |
77 | "auto", | |
78 | "n32", | |
79 | "o32", | |
28d169de | 80 | "n64", |
2e4ebe70 DJ |
81 | "o64", |
82 | "eabi32", | |
83 | "eabi64", | |
84 | NULL | |
85 | }; | |
86 | ||
cce74817 | 87 | struct frame_extra_info |
c5aa993b JM |
88 | { |
89 | mips_extra_func_info_t proc_desc; | |
90 | int num_args; | |
91 | }; | |
cce74817 | 92 | |
d929b26f AC |
93 | /* Various MIPS ISA options (related to stack analysis) can be |
94 | overridden dynamically. Establish an enum/array for managing | |
95 | them. */ | |
96 | ||
53904c9e AC |
97 | static const char size_auto[] = "auto"; |
98 | static const char size_32[] = "32"; | |
99 | static const char size_64[] = "64"; | |
d929b26f | 100 | |
53904c9e | 101 | static const char *size_enums[] = { |
d929b26f AC |
102 | size_auto, |
103 | size_32, | |
104 | size_64, | |
a5ea2558 AC |
105 | 0 |
106 | }; | |
107 | ||
7a292a7a SS |
108 | /* Some MIPS boards don't support floating point while others only |
109 | support single-precision floating-point operations. See also | |
110 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
111 | |
112 | enum mips_fpu_type | |
c5aa993b JM |
113 | { |
114 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
115 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
116 | MIPS_FPU_NONE /* No floating point. */ | |
117 | }; | |
c906108c SS |
118 | |
119 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
120 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
121 | #endif | |
122 | static int mips_fpu_type_auto = 1; | |
123 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 124 | |
9ace0497 | 125 | static int mips_debug = 0; |
7a292a7a | 126 | |
c2d11a7d JM |
127 | /* MIPS specific per-architecture information */ |
128 | struct gdbarch_tdep | |
129 | { | |
130 | /* from the elf header */ | |
131 | int elf_flags; | |
70f80edf | 132 | |
c2d11a7d | 133 | /* mips options */ |
0dadbba0 | 134 | enum mips_abi mips_abi; |
2e4ebe70 | 135 | enum mips_abi found_abi; |
c2d11a7d JM |
136 | enum mips_fpu_type mips_fpu_type; |
137 | int mips_last_arg_regnum; | |
138 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 139 | int mips_default_saved_regsize; |
c2d11a7d | 140 | int mips_fp_register_double; |
d929b26f | 141 | int mips_default_stack_argsize; |
5213ab06 | 142 | int gdb_target_is_mips64; |
4014092b | 143 | int default_mask_address_p; |
70f80edf JT |
144 | |
145 | enum gdb_osabi osabi; | |
c2d11a7d JM |
146 | }; |
147 | ||
0dadbba0 | 148 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 149 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 150 | |
c2d11a7d | 151 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 152 | |
c2d11a7d | 153 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 154 | |
c2d11a7d | 155 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 156 | |
d929b26f AC |
157 | /* Return the currently configured (or set) saved register size. */ |
158 | ||
a5ea2558 | 159 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 160 | |
53904c9e | 161 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
162 | |
163 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
164 | ||
165 | static unsigned int | |
acdb74a0 | 166 | mips_saved_regsize (void) |
d929b26f AC |
167 | { |
168 | if (mips_saved_regsize_string == size_auto) | |
169 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
170 | else if (mips_saved_regsize_string == size_64) | |
171 | return 8; | |
172 | else /* if (mips_saved_regsize_string == size_32) */ | |
173 | return 4; | |
174 | } | |
175 | ||
71b8ef93 | 176 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa MS |
177 | marks it as 16-bit function. The MSB of the minimal symbol's |
178 | "info" field is used for this purpose. This field is already | |
179 | being used to store the symbol size, so the assumption is | |
180 | that the symbol size cannot exceed 2^31. | |
181 | ||
182 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
183 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
184 | minimal symbol to mark it as a 16-bit function | |
185 | ||
186 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
187 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
188 | the "info" field with the "special" bit masked out */ | |
189 | ||
5a89d8aa MS |
190 | static void |
191 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
192 | { | |
193 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
194 | { | |
195 | MSYMBOL_INFO (msym) = (char *) | |
196 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
197 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
198 | } | |
199 | } | |
200 | ||
71b8ef93 MS |
201 | static int |
202 | msymbol_is_special (struct minimal_symbol *msym) | |
203 | { | |
204 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
205 | } | |
206 | ||
207 | static long | |
208 | msymbol_size (struct minimal_symbol *msym) | |
209 | { | |
210 | return ((long) MSYMBOL_INFO (msym) & 0x7fffffff); | |
211 | } | |
212 | ||
88658117 AC |
213 | /* XFER a value from the big/little/left end of the register. |
214 | Depending on the size of the value it might occupy the entire | |
215 | register or just part of it. Make an allowance for this, aligning | |
216 | things accordingly. */ | |
217 | ||
218 | static void | |
219 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
220 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
221 | int buf_offset) | |
222 | { | |
223 | bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); | |
224 | int reg_offset = 0; | |
cb1d2653 AC |
225 | /* Need to transfer the left or right part of the register, based on |
226 | the targets byte order. */ | |
88658117 AC |
227 | switch (endian) |
228 | { | |
229 | case BFD_ENDIAN_BIG: | |
230 | reg_offset = REGISTER_RAW_SIZE (reg_num) - length; | |
231 | break; | |
232 | case BFD_ENDIAN_LITTLE: | |
233 | reg_offset = 0; | |
234 | break; | |
235 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
236 | reg_offset = 0; | |
237 | break; | |
238 | default: | |
239 | internal_error (__FILE__, __LINE__, "bad switch"); | |
240 | } | |
241 | if (mips_debug) | |
cb1d2653 AC |
242 | fprintf_unfiltered (gdb_stderr, |
243 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
244 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
245 | if (mips_debug && out != NULL) |
246 | { | |
247 | int i; | |
cb1d2653 | 248 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 249 | for (i = 0; i < length; i++) |
cb1d2653 | 250 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
251 | } |
252 | if (in != NULL) | |
253 | regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); | |
254 | if (out != NULL) | |
255 | regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); | |
256 | if (mips_debug && in != NULL) | |
257 | { | |
258 | int i; | |
cb1d2653 | 259 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 260 | for (i = 0; i < length; i++) |
cb1d2653 | 261 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
262 | } |
263 | if (mips_debug) | |
264 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
265 | } | |
266 | ||
dd824b04 DJ |
267 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
268 | compatiblity mode. A return value of 1 means that we have | |
269 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
270 | ||
271 | static int | |
272 | mips2_fp_compat (void) | |
273 | { | |
274 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
275 | meaningful. */ | |
276 | if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4) | |
277 | return 0; | |
278 | ||
279 | #if 0 | |
280 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
281 | in all the places we deal with FP registers. PR gdb/413. */ | |
282 | /* Otherwise check the FR bit in the status register - it controls | |
283 | the FP compatiblity mode. If it is clear we are in compatibility | |
284 | mode. */ | |
285 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
286 | return 1; | |
287 | #endif | |
361d1df0 | 288 | |
dd824b04 DJ |
289 | return 0; |
290 | } | |
291 | ||
c2d11a7d JM |
292 | /* Indicate that the ABI makes use of double-precision registers |
293 | provided by the FPU (rather than combining pairs of registers to | |
294 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
295 | determine if the ABI is using double-precision registers. See also | |
296 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 297 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 298 | |
d929b26f AC |
299 | /* The amount of space reserved on the stack for registers. This is |
300 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
301 | data allocated after the registers have run out. */ | |
302 | ||
0dadbba0 | 303 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
304 | |
305 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
306 | ||
53904c9e | 307 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
308 | |
309 | static unsigned int | |
310 | mips_stack_argsize (void) | |
311 | { | |
312 | if (mips_stack_argsize_string == size_auto) | |
313 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
314 | else if (mips_stack_argsize_string == size_64) | |
315 | return 8; | |
316 | else /* if (mips_stack_argsize_string == size_32) */ | |
317 | return 4; | |
318 | } | |
319 | ||
5213ab06 | 320 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 321 | |
92e1c15c | 322 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 323 | |
7a292a7a | 324 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 325 | |
a14ed312 | 326 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 327 | |
a14ed312 | 328 | static void mips_print_register (int, int); |
c906108c SS |
329 | |
330 | static mips_extra_func_info_t | |
479412cd | 331 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int); |
c906108c | 332 | |
a14ed312 | 333 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 334 | |
a14ed312 | 335 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 336 | |
5a89d8aa | 337 | static int mips_set_processor_type (char *); |
c906108c | 338 | |
a14ed312 | 339 | static void mips_show_processor_type_command (char *, int); |
c906108c | 340 | |
a14ed312 | 341 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
342 | |
343 | static mips_extra_func_info_t | |
479412cd | 344 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame); |
c906108c | 345 | |
a14ed312 KB |
346 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
347 | mips_extra_func_info_t proc_desc); | |
c906108c | 348 | |
dd824b04 DJ |
349 | static void mips_read_fp_register_single (int regno, char *rare_buffer); |
350 | static void mips_read_fp_register_double (int regno, char *rare_buffer); | |
351 | ||
67b2c998 DJ |
352 | static struct type *mips_float_register_type (void); |
353 | static struct type *mips_double_register_type (void); | |
354 | ||
c906108c SS |
355 | /* This value is the model of MIPS in use. It is derived from the value |
356 | of the PrID register. */ | |
357 | ||
358 | char *mips_processor_type; | |
359 | ||
360 | char *tmp_mips_processor_type; | |
361 | ||
acdb74a0 AC |
362 | /* The list of available "set mips " and "show mips " commands */ |
363 | ||
364 | static struct cmd_list_element *setmipscmdlist = NULL; | |
365 | static struct cmd_list_element *showmipscmdlist = NULL; | |
366 | ||
c906108c SS |
367 | /* A set of original names, to be used when restoring back to generic |
368 | registers from a specific set. */ | |
369 | ||
cce74817 JM |
370 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
371 | char **mips_processor_reg_names = mips_generic_reg_names; | |
372 | ||
5a89d8aa | 373 | static const char * |
fba45db2 | 374 | mips_register_name (int i) |
cce74817 JM |
375 | { |
376 | return mips_processor_reg_names[i]; | |
377 | } | |
9846de1b | 378 | /* *INDENT-OFF* */ |
c906108c SS |
379 | /* Names of IDT R3041 registers. */ |
380 | ||
381 | char *mips_r3041_reg_names[] = { | |
382 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
383 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
384 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
385 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
386 | "sr", "lo", "hi", "bad", "cause","pc", | |
387 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
388 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
389 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
390 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 391 | "fsr", "fir", "",/*"fp"*/ "", |
c906108c SS |
392 | "", "", "bus", "ccfg", "", "", "", "", |
393 | "", "", "port", "cmp", "", "", "epc", "prid", | |
394 | }; | |
395 | ||
396 | /* Names of IDT R3051 registers. */ | |
397 | ||
398 | char *mips_r3051_reg_names[] = { | |
399 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
400 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
401 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
402 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
403 | "sr", "lo", "hi", "bad", "cause","pc", | |
404 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
405 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
406 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
407 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 408 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
409 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
410 | "", "", "ehi", "", "", "", "epc", "prid", | |
411 | }; | |
412 | ||
413 | /* Names of IDT R3081 registers. */ | |
414 | ||
415 | char *mips_r3081_reg_names[] = { | |
416 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
417 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
418 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
419 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
420 | "sr", "lo", "hi", "bad", "cause","pc", | |
421 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
422 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
423 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
424 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 425 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
426 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
427 | "", "", "ehi", "", "", "", "epc", "prid", | |
428 | }; | |
429 | ||
430 | /* Names of LSI 33k registers. */ | |
431 | ||
432 | char *mips_lsi33k_reg_names[] = { | |
433 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
434 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
435 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
436 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
437 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
438 | "dcic", "bpc", "bda", "", "", "", "", "", | |
439 | "", "", "", "", "", "", "", "", | |
440 | "", "", "", "", "", "", "", "", | |
441 | "", "", "", "", "", "", "", "", | |
442 | "", "", "", "", | |
443 | "", "", "", "", "", "", "", "", | |
444 | "", "", "", "", "", "", "", "", | |
445 | }; | |
446 | ||
447 | struct { | |
448 | char *name; | |
449 | char **regnames; | |
450 | } mips_processor_type_table[] = { | |
451 | { "generic", mips_generic_reg_names }, | |
452 | { "r3041", mips_r3041_reg_names }, | |
453 | { "r3051", mips_r3051_reg_names }, | |
454 | { "r3071", mips_r3081_reg_names }, | |
455 | { "r3081", mips_r3081_reg_names }, | |
456 | { "lsi33k", mips_lsi33k_reg_names }, | |
457 | { NULL, NULL } | |
458 | }; | |
9846de1b | 459 | /* *INDENT-ON* */ |
c906108c | 460 | |
c5aa993b JM |
461 | |
462 | ||
463 | ||
c906108c | 464 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
465 | static int mips16_to_32_reg[8] = |
466 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
467 | |
468 | /* Heuristic_proc_start may hunt through the text section for a long | |
469 | time across a 2400 baud serial line. Allows the user to limit this | |
470 | search. */ | |
471 | ||
472 | static unsigned int heuristic_fence_post = 0; | |
473 | ||
c5aa993b JM |
474 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
475 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
476 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
477 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
478 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
479 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
480 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
481 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
482 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
483 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
484 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
485 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
486 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
487 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
488 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
489 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
490 | ||
491 | struct linked_proc_info | |
c5aa993b JM |
492 | { |
493 | struct mips_extra_func_info info; | |
494 | struct linked_proc_info *next; | |
495 | } | |
496 | *linked_proc_desc_table = NULL; | |
c906108c | 497 | |
cce74817 | 498 | void |
acdb74a0 | 499 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
500 | { |
501 | if (fi | |
502 | && fi->extra_info | |
503 | && fi->extra_info->proc_desc | |
504 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 505 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 506 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 507 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 508 | } |
c906108c | 509 | |
46cd78fb AC |
510 | /* Number of bytes of storage in the actual machine representation for |
511 | register N. NOTE: This indirectly defines the register size | |
512 | transfered by the GDB protocol. */ | |
43e526b9 JM |
513 | |
514 | static int mips64_transfers_32bit_regs_p = 0; | |
515 | ||
f7ab6ec6 | 516 | static int |
acdb74a0 | 517 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
518 | { |
519 | if (mips64_transfers_32bit_regs_p) | |
520 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
521 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
522 | && FP_REGISTER_DOUBLE) | |
523 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
524 | registers. */ | |
525 | return 8; | |
43e526b9 JM |
526 | else |
527 | return MIPS_REGSIZE; | |
528 | } | |
529 | ||
46cd78fb AC |
530 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
531 | defines the remote-gdb packet. */ | |
532 | ||
d05285fa | 533 | static int |
acdb74a0 | 534 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
535 | { |
536 | if (mips64_transfers_32bit_regs_p) | |
537 | return 0; | |
538 | else | |
539 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
540 | } | |
541 | ||
d05285fa | 542 | static void |
acdb74a0 AC |
543 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
544 | char *raw_buf, char *virt_buf) | |
43e526b9 | 545 | { |
d7449b42 | 546 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
547 | memcpy (virt_buf, |
548 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
549 | TYPE_LENGTH (virtual_type)); | |
550 | else | |
551 | memcpy (virt_buf, | |
552 | raw_buf, | |
553 | TYPE_LENGTH (virtual_type)); | |
554 | } | |
555 | ||
d05285fa | 556 | static void |
acdb74a0 AC |
557 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
558 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
559 | { |
560 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
d7449b42 | 561 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
562 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
563 | virt_buf, | |
564 | TYPE_LENGTH (virtual_type)); | |
565 | else | |
566 | memcpy (raw_buf, | |
567 | virt_buf, | |
568 | TYPE_LENGTH (virtual_type)); | |
569 | } | |
570 | ||
102182a9 MS |
571 | void |
572 | mips_register_convert_to_type (int regnum, struct type *type, char *buffer) | |
573 | { | |
574 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
575 | && REGISTER_RAW_SIZE (regnum) == 4 | |
576 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
577 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
578 | && TYPE_LENGTH(type) == 8) | |
579 | { | |
580 | char temp[4]; | |
581 | memcpy (temp, ((char *)(buffer))+4, 4); | |
582 | memcpy (((char *)(buffer))+4, (buffer), 4); | |
583 | memcpy (((char *)(buffer)), temp, 4); | |
584 | } | |
585 | } | |
586 | ||
587 | void | |
588 | mips_register_convert_from_type (int regnum, struct type *type, char *buffer) | |
589 | { | |
590 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
591 | && REGISTER_RAW_SIZE (regnum) == 4 | |
592 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
593 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
594 | && TYPE_LENGTH(type) == 8) | |
595 | { | |
596 | char temp[4]; | |
597 | memcpy (temp, ((char *)(buffer))+4, 4); | |
598 | memcpy (((char *)(buffer))+4, (buffer), 4); | |
599 | memcpy (((char *)(buffer)), temp, 4); | |
600 | } | |
601 | } | |
602 | ||
78fde5f8 KB |
603 | /* Return the GDB type object for the "standard" data type |
604 | of data in register REG. | |
605 | ||
606 | Note: kevinb/2002-08-01: The definition below should faithfully | |
607 | reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE | |
608 | definitions found in config/mips/tm-*.h. I'm concerned about | |
609 | the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause | |
610 | though. In some cases FP_REGNUM is in this range, and I doubt | |
611 | that this code is correct for the 64-bit case. */ | |
612 | ||
613 | static struct type * | |
614 | mips_register_virtual_type (int reg) | |
615 | { | |
616 | if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32) | |
a6425924 KB |
617 | { |
618 | /* Floating point registers... */ | |
619 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
620 | return builtin_type_ieee_double_big; | |
621 | else | |
622 | return builtin_type_ieee_double_little; | |
623 | } | |
78fde5f8 KB |
624 | else if (reg == PS_REGNUM /* CR */) |
625 | return builtin_type_uint32; | |
626 | else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM) | |
627 | return builtin_type_uint32; | |
628 | else | |
629 | { | |
a6425924 KB |
630 | /* Everything else... |
631 | Return type appropriate for width of register. */ | |
632 | if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64)) | |
633 | return builtin_type_uint64; | |
78fde5f8 | 634 | else |
a6425924 | 635 | return builtin_type_uint32; |
78fde5f8 KB |
636 | } |
637 | } | |
638 | ||
bcb0cc15 MS |
639 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
640 | ||
641 | static CORE_ADDR | |
642 | mips_read_sp (void) | |
643 | { | |
644 | return ADDR_BITS_REMOVE (read_register (SP_REGNUM)); | |
645 | } | |
646 | ||
c906108c | 647 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 648 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
649 | |
650 | static int | |
651 | mips_mask_address_p (void) | |
652 | { | |
653 | switch (mask_address_var) | |
654 | { | |
7f19b9a2 | 655 | case AUTO_BOOLEAN_TRUE: |
4014092b | 656 | return 1; |
7f19b9a2 | 657 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
658 | return 0; |
659 | break; | |
7f19b9a2 | 660 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 661 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 662 | default: |
8e65ff28 AC |
663 | internal_error (__FILE__, __LINE__, |
664 | "mips_mask_address_p: bad switch"); | |
4014092b | 665 | return -1; |
361d1df0 | 666 | } |
4014092b AC |
667 | } |
668 | ||
669 | static void | |
e9e68a56 | 670 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
671 | { |
672 | switch (mask_address_var) | |
673 | { | |
7f19b9a2 | 674 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
675 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
676 | break; | |
7f19b9a2 | 677 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
678 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
679 | break; | |
7f19b9a2 | 680 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
681 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
682 | mips_mask_address_p () ? "enabled" : "disabled"); | |
683 | break; | |
684 | default: | |
8e65ff28 AC |
685 | internal_error (__FILE__, __LINE__, |
686 | "show_mask_address: bad switch"); | |
4014092b | 687 | break; |
361d1df0 | 688 | } |
4014092b | 689 | } |
c906108c SS |
690 | |
691 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 692 | |
f7ab6ec6 | 693 | static int |
cb811fe7 | 694 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 695 | { |
cb811fe7 MS |
696 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
697 | } | |
698 | ||
f7ab6ec6 | 699 | static int |
cb811fe7 MS |
700 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) |
701 | { | |
b78bcb18 | 702 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
703 | } |
704 | ||
f7ab6ec6 | 705 | static int |
cb811fe7 MS |
706 | mips_o32_use_struct_convention (int gcc_p, struct type *type) |
707 | { | |
708 | return 1; /* Structures are returned by ref in extra arg0. */ | |
c906108c SS |
709 | } |
710 | ||
8b389c40 MS |
711 | /* Should call_function pass struct by reference? |
712 | For each architecture, structs are passed either by | |
713 | value or by reference, depending on their size. */ | |
714 | ||
715 | static int | |
716 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
717 | { | |
718 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
719 | int len = TYPE_LENGTH (check_typedef (type)); | |
720 | ||
721 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
722 | return (len > MIPS_SAVED_REGSIZE); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static int | |
728 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
729 | { | |
730 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
731 | } | |
732 | ||
f7ab6ec6 | 733 | static int |
8b389c40 MS |
734 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
735 | { | |
736 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
737 | } | |
738 | ||
c906108c SS |
739 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
740 | ||
741 | static int | |
742 | pc_is_mips16 (bfd_vma memaddr) | |
743 | { | |
744 | struct minimal_symbol *sym; | |
745 | ||
746 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
747 | if (IS_MIPS16_ADDR (memaddr)) | |
748 | return 1; | |
749 | ||
750 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
751 | the high bit of the info field. Use this to decide if the function is | |
752 | MIPS16 or normal MIPS. */ | |
753 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
754 | if (sym) | |
71b8ef93 | 755 | return msymbol_is_special (sym); |
c906108c SS |
756 | else |
757 | return 0; | |
758 | } | |
759 | ||
6c997a34 AC |
760 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
761 | all registers should be sign extended for simplicity? */ | |
762 | ||
763 | static CORE_ADDR | |
39f77062 | 764 | mips_read_pc (ptid_t ptid) |
6c997a34 | 765 | { |
39f77062 | 766 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 767 | } |
c906108c SS |
768 | |
769 | /* This returns the PC of the first inst after the prologue. If we can't | |
770 | find the prologue, then return 0. */ | |
771 | ||
772 | static CORE_ADDR | |
acdb74a0 AC |
773 | after_prologue (CORE_ADDR pc, |
774 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
775 | { |
776 | struct symtab_and_line sal; | |
777 | CORE_ADDR func_addr, func_end; | |
778 | ||
479412cd DJ |
779 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
780 | to read the stack pointer from the current machine state, because | |
781 | the current machine state has nothing to do with the information | |
782 | we need from the proc_desc; and the process may or may not exist | |
783 | right now. */ | |
c906108c | 784 | if (!proc_desc) |
479412cd | 785 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
786 | |
787 | if (proc_desc) | |
788 | { | |
789 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 790 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
791 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
792 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
793 | return 0; | |
794 | } | |
795 | ||
796 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
797 | return 0; /* Unknown */ | |
798 | ||
799 | sal = find_pc_line (func_addr, 0); | |
800 | ||
801 | if (sal.end < func_end) | |
802 | return sal.end; | |
803 | ||
804 | /* The line after the prologue is after the end of the function. In this | |
805 | case, tell the caller to find the prologue the hard way. */ | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
811 | set the appropriate bit in the general register mask or float register mask | |
812 | to indicate which register is saved. This is a helper function | |
813 | for mips_find_saved_regs. */ | |
814 | ||
815 | static void | |
acdb74a0 AC |
816 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
817 | unsigned long *float_mask) | |
c906108c SS |
818 | { |
819 | int reg; | |
820 | ||
821 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
822 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
823 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
824 | { | |
825 | /* It might be possible to use the instruction to | |
c5aa993b JM |
826 | find the offset, rather than the code below which |
827 | is based on things being in a certain order in the | |
828 | frame, but figuring out what the instruction's offset | |
829 | is relative to might be a little tricky. */ | |
c906108c SS |
830 | reg = (inst & 0x001f0000) >> 16; |
831 | *gen_mask |= (1 << reg); | |
832 | } | |
833 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
834 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
835 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
836 | |
837 | { | |
838 | reg = ((inst & 0x001f0000) >> 16); | |
839 | *float_mask |= (1 << reg); | |
840 | } | |
841 | } | |
842 | ||
843 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
844 | set the appropriate bit in the general register or float register mask | |
845 | to indicate which register is saved. This is a helper function | |
846 | for mips_find_saved_regs. */ | |
847 | ||
848 | static void | |
acdb74a0 | 849 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 850 | { |
c5aa993b | 851 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
852 | { |
853 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
854 | *gen_mask |= (1 << reg); | |
855 | } | |
c5aa993b | 856 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
857 | { |
858 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
859 | *gen_mask |= (1 << reg); | |
860 | } | |
c5aa993b | 861 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
862 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
863 | *gen_mask |= (1 << RA_REGNUM); | |
864 | } | |
865 | ||
866 | ||
867 | /* Fetch and return instruction from the specified location. If the PC | |
868 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
869 | ||
870 | static t_inst | |
acdb74a0 | 871 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
872 | { |
873 | char buf[MIPS_INSTLEN]; | |
874 | int instlen; | |
875 | int status; | |
876 | ||
877 | if (pc_is_mips16 (addr)) | |
878 | { | |
879 | instlen = MIPS16_INSTLEN; | |
880 | addr = UNMAKE_MIPS16_ADDR (addr); | |
881 | } | |
882 | else | |
c5aa993b | 883 | instlen = MIPS_INSTLEN; |
c906108c SS |
884 | status = read_memory_nobpt (addr, buf, instlen); |
885 | if (status) | |
886 | memory_error (status, addr); | |
887 | return extract_unsigned_integer (buf, instlen); | |
888 | } | |
889 | ||
890 | ||
891 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
892 | #define mips32_op(x) (x >> 26) |
893 | #define itype_op(x) (x >> 26) | |
894 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 895 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 896 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 897 | |
e135b889 DJ |
898 | #define jtype_op(x) (x >> 26) |
899 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 900 | |
e135b889 DJ |
901 | #define rtype_op(x) (x >> 26) |
902 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
903 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
904 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
905 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
906 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
907 | |
908 | static CORE_ADDR | |
c5aa993b JM |
909 | mips32_relative_offset (unsigned long inst) |
910 | { | |
911 | long x; | |
912 | x = itype_immediate (inst); | |
913 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 914 | { |
c5aa993b | 915 | x |= 0xffff0000; /* sign extension */ |
c906108c | 916 | } |
c5aa993b JM |
917 | x = x << 2; |
918 | return x; | |
c906108c SS |
919 | } |
920 | ||
921 | /* Determine whate to set a single step breakpoint while considering | |
922 | branch prediction */ | |
5a89d8aa | 923 | static CORE_ADDR |
c5aa993b JM |
924 | mips32_next_pc (CORE_ADDR pc) |
925 | { | |
926 | unsigned long inst; | |
927 | int op; | |
928 | inst = mips_fetch_instruction (pc); | |
e135b889 | 929 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 930 | { |
e135b889 DJ |
931 | if (itype_op (inst) >> 2 == 5) |
932 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 933 | { |
e135b889 | 934 | op = (itype_op (inst) & 0x03); |
c906108c SS |
935 | switch (op) |
936 | { | |
e135b889 DJ |
937 | case 0: /* BEQL */ |
938 | goto equal_branch; | |
939 | case 1: /* BNEL */ | |
940 | goto neq_branch; | |
941 | case 2: /* BLEZL */ | |
942 | goto less_branch; | |
943 | case 3: /* BGTZ */ | |
944 | goto greater_branch; | |
c5aa993b JM |
945 | default: |
946 | pc += 4; | |
c906108c SS |
947 | } |
948 | } | |
e135b889 DJ |
949 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
950 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
951 | { | |
952 | int tf = itype_rt (inst) & 0x01; | |
953 | int cnum = itype_rt (inst) >> 2; | |
954 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
955 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
956 | ||
957 | if (((cond >> cnum) & 0x01) == tf) | |
958 | pc += mips32_relative_offset (inst) + 4; | |
959 | else | |
960 | pc += 8; | |
961 | } | |
c5aa993b JM |
962 | else |
963 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
964 | } |
965 | else | |
c5aa993b JM |
966 | { /* This gets way messy */ |
967 | ||
c906108c | 968 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 969 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 970 | { |
c5aa993b JM |
971 | case 0: /* SPECIAL */ |
972 | op = rtype_funct (inst); | |
973 | switch (op) | |
974 | { | |
975 | case 8: /* JR */ | |
976 | case 9: /* JALR */ | |
6c997a34 AC |
977 | /* Set PC to that address */ |
978 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
979 | break; |
980 | default: | |
981 | pc += 4; | |
982 | } | |
983 | ||
e135b889 | 984 | break; /* end SPECIAL */ |
c5aa993b | 985 | case 1: /* REGIMM */ |
c906108c | 986 | { |
e135b889 DJ |
987 | op = itype_rt (inst); /* branch condition */ |
988 | switch (op) | |
c906108c | 989 | { |
c5aa993b | 990 | case 0: /* BLTZ */ |
e135b889 DJ |
991 | case 2: /* BLTZL */ |
992 | case 16: /* BLTZAL */ | |
c5aa993b | 993 | case 18: /* BLTZALL */ |
c906108c | 994 | less_branch: |
6c997a34 | 995 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
996 | pc += mips32_relative_offset (inst) + 4; |
997 | else | |
998 | pc += 8; /* after the delay slot */ | |
999 | break; | |
e135b889 | 1000 | case 1: /* BGEZ */ |
c5aa993b JM |
1001 | case 3: /* BGEZL */ |
1002 | case 17: /* BGEZAL */ | |
1003 | case 19: /* BGEZALL */ | |
c906108c | 1004 | greater_equal_branch: |
6c997a34 | 1005 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1006 | pc += mips32_relative_offset (inst) + 4; |
1007 | else | |
1008 | pc += 8; /* after the delay slot */ | |
1009 | break; | |
e135b889 | 1010 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1011 | default: |
1012 | pc += 4; | |
c906108c SS |
1013 | } |
1014 | } | |
e135b889 | 1015 | break; /* end REGIMM */ |
c5aa993b JM |
1016 | case 2: /* J */ |
1017 | case 3: /* JAL */ | |
1018 | { | |
1019 | unsigned long reg; | |
1020 | reg = jtype_target (inst) << 2; | |
e135b889 | 1021 | /* Upper four bits get never changed... */ |
c5aa993b | 1022 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1023 | } |
c5aa993b JM |
1024 | break; |
1025 | /* FIXME case JALX : */ | |
1026 | { | |
1027 | unsigned long reg; | |
1028 | reg = jtype_target (inst) << 2; | |
1029 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1030 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1031 | } | |
c5aa993b | 1032 | break; /* The new PC will be alternate mode */ |
e135b889 | 1033 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1034 | equal_branch: |
6c997a34 AC |
1035 | if (read_signed_register (itype_rs (inst)) == |
1036 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1037 | pc += mips32_relative_offset (inst) + 4; |
1038 | else | |
1039 | pc += 8; | |
1040 | break; | |
e135b889 | 1041 | case 5: /* BNE, BNEL */ |
c5aa993b | 1042 | neq_branch: |
6c997a34 | 1043 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1044 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1045 | pc += mips32_relative_offset (inst) + 4; |
1046 | else | |
1047 | pc += 8; | |
1048 | break; | |
e135b889 | 1049 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1050 | less_zero_branch: |
6c997a34 | 1051 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1052 | pc += mips32_relative_offset (inst) + 4; |
1053 | else | |
1054 | pc += 8; | |
1055 | break; | |
1056 | case 7: | |
e135b889 DJ |
1057 | default: |
1058 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1059 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1060 | pc += mips32_relative_offset (inst) + 4; |
1061 | else | |
1062 | pc += 8; | |
1063 | break; | |
c5aa993b JM |
1064 | } /* switch */ |
1065 | } /* else */ | |
1066 | return pc; | |
1067 | } /* mips32_next_pc */ | |
c906108c SS |
1068 | |
1069 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1070 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1071 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1072 | We dont want to set a single step instruction on the extend instruction | |
1073 | either. | |
c5aa993b | 1074 | */ |
c906108c SS |
1075 | |
1076 | /* Lots of mips16 instruction formats */ | |
1077 | /* Predicting jumps requires itype,ritype,i8type | |
1078 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1079 | */ |
c906108c SS |
1080 | enum mips16_inst_fmts |
1081 | { | |
c5aa993b JM |
1082 | itype, /* 0 immediate 5,10 */ |
1083 | ritype, /* 1 5,3,8 */ | |
1084 | rrtype, /* 2 5,3,3,5 */ | |
1085 | rritype, /* 3 5,3,3,5 */ | |
1086 | rrrtype, /* 4 5,3,3,3,2 */ | |
1087 | rriatype, /* 5 5,3,3,1,4 */ | |
1088 | shifttype, /* 6 5,3,3,3,2 */ | |
1089 | i8type, /* 7 5,3,8 */ | |
1090 | i8movtype, /* 8 5,3,3,5 */ | |
1091 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1092 | i64type, /* 10 5,3,8 */ | |
1093 | ri64type, /* 11 5,3,3,5 */ | |
1094 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1095 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1096 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1097 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1098 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1099 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1100 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1101 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1102 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1103 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1104 | }; | |
12f02c2a AC |
1105 | /* I am heaping all the fields of the formats into one structure and |
1106 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1107 | struct upk_mips16 |
c5aa993b | 1108 | { |
12f02c2a | 1109 | CORE_ADDR offset; |
c5aa993b JM |
1110 | unsigned int regx; /* Function in i8 type */ |
1111 | unsigned int regy; | |
1112 | }; | |
c906108c SS |
1113 | |
1114 | ||
12f02c2a AC |
1115 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1116 | for the bits which make up the immediatate extension. */ | |
c906108c | 1117 | |
12f02c2a AC |
1118 | static CORE_ADDR |
1119 | extended_offset (unsigned int extension) | |
c906108c | 1120 | { |
12f02c2a | 1121 | CORE_ADDR value; |
c5aa993b JM |
1122 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1123 | value = value << 6; | |
1124 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1125 | value = value << 5; | |
1126 | value |= extension & 0x01f; /* extract 4:0 */ | |
1127 | return value; | |
c906108c SS |
1128 | } |
1129 | ||
1130 | /* Only call this function if you know that this is an extendable | |
1131 | instruction, It wont malfunction, but why make excess remote memory references? | |
1132 | If the immediate operands get sign extended or somthing, do it after | |
1133 | the extension is performed. | |
c5aa993b | 1134 | */ |
c906108c SS |
1135 | /* FIXME: Every one of these cases needs to worry about sign extension |
1136 | when the offset is to be used in relative addressing */ | |
1137 | ||
1138 | ||
12f02c2a | 1139 | static unsigned int |
c5aa993b | 1140 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1141 | { |
c5aa993b JM |
1142 | char buf[8]; |
1143 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1144 | target_read_memory (pc, buf, 2); | |
1145 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1146 | } |
1147 | ||
1148 | static void | |
c5aa993b | 1149 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1150 | unsigned int extension, |
1151 | unsigned int inst, | |
1152 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1153 | struct upk_mips16 *upk) |
c906108c | 1154 | { |
12f02c2a AC |
1155 | CORE_ADDR offset; |
1156 | int regx; | |
1157 | int regy; | |
1158 | switch (insn_format) | |
c906108c | 1159 | { |
c5aa993b | 1160 | case itype: |
c906108c | 1161 | { |
12f02c2a AC |
1162 | CORE_ADDR value; |
1163 | if (extension) | |
c5aa993b JM |
1164 | { |
1165 | value = extended_offset (extension); | |
1166 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1167 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1168 | } |
1169 | else | |
c5aa993b | 1170 | { |
12f02c2a | 1171 | value = inst & 0x7ff; |
c5aa993b | 1172 | /* FIXME : Consider sign extension */ |
c906108c | 1173 | } |
12f02c2a AC |
1174 | offset = value; |
1175 | regx = -1; | |
1176 | regy = -1; | |
c906108c | 1177 | } |
c5aa993b JM |
1178 | break; |
1179 | case ritype: | |
1180 | case i8type: | |
1181 | { /* A register identifier and an offset */ | |
c906108c SS |
1182 | /* Most of the fields are the same as I type but the |
1183 | immediate value is of a different length */ | |
12f02c2a AC |
1184 | CORE_ADDR value; |
1185 | if (extension) | |
c906108c | 1186 | { |
c5aa993b JM |
1187 | value = extended_offset (extension); |
1188 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1189 | value |= inst & 0xff; /* eleven bits from instruction */ |
1190 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1191 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1192 | { | |
1193 | value &= ~0x3fff; /* remove the sign bit */ | |
1194 | value = -value; | |
c906108c SS |
1195 | } |
1196 | } | |
c5aa993b JM |
1197 | else |
1198 | { | |
12f02c2a AC |
1199 | value = inst & 0xff; /* 8 bits */ |
1200 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1201 | /* FIXME: Do sign extension , this format needs it */ |
1202 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1203 | { | |
1204 | value &= 0xef; /* remove the sign bit */ | |
1205 | value = -value; | |
1206 | } | |
c5aa993b | 1207 | } |
12f02c2a AC |
1208 | offset = value; |
1209 | regy = -1; | |
c5aa993b | 1210 | break; |
c906108c | 1211 | } |
c5aa993b | 1212 | case jalxtype: |
c906108c | 1213 | { |
c5aa993b | 1214 | unsigned long value; |
12f02c2a AC |
1215 | unsigned int nexthalf; |
1216 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1217 | value = value << 16; |
1218 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1219 | value |= nexthalf; | |
12f02c2a AC |
1220 | offset = value; |
1221 | regx = -1; | |
1222 | regy = -1; | |
c5aa993b | 1223 | break; |
c906108c SS |
1224 | } |
1225 | default: | |
8e65ff28 AC |
1226 | internal_error (__FILE__, __LINE__, |
1227 | "bad switch"); | |
c906108c | 1228 | } |
12f02c2a AC |
1229 | upk->offset = offset; |
1230 | upk->regx = regx; | |
1231 | upk->regy = regy; | |
c906108c SS |
1232 | } |
1233 | ||
1234 | ||
c5aa993b JM |
1235 | static CORE_ADDR |
1236 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1237 | { |
c5aa993b | 1238 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1239 | } |
1240 | ||
12f02c2a AC |
1241 | static CORE_ADDR |
1242 | extended_mips16_next_pc (CORE_ADDR pc, | |
1243 | unsigned int extension, | |
1244 | unsigned int insn) | |
c906108c | 1245 | { |
12f02c2a AC |
1246 | int op = (insn >> 11); |
1247 | switch (op) | |
c906108c | 1248 | { |
12f02c2a AC |
1249 | case 2: /* Branch */ |
1250 | { | |
1251 | CORE_ADDR offset; | |
1252 | struct upk_mips16 upk; | |
1253 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1254 | offset = upk.offset; | |
1255 | if (offset & 0x800) | |
1256 | { | |
1257 | offset &= 0xeff; | |
1258 | offset = -offset; | |
1259 | } | |
1260 | pc += (offset << 1) + 2; | |
1261 | break; | |
1262 | } | |
1263 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1264 | { | |
1265 | struct upk_mips16 upk; | |
1266 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1267 | pc = add_offset_16 (pc, upk.offset); | |
1268 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1269 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1270 | else | |
1271 | pc |= 0x01; | |
1272 | break; | |
1273 | } | |
1274 | case 4: /* beqz */ | |
1275 | { | |
1276 | struct upk_mips16 upk; | |
1277 | int reg; | |
1278 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1279 | reg = read_signed_register (upk.regx); | |
1280 | if (reg == 0) | |
1281 | pc += (upk.offset << 1) + 2; | |
1282 | else | |
1283 | pc += 2; | |
1284 | break; | |
1285 | } | |
1286 | case 5: /* bnez */ | |
1287 | { | |
1288 | struct upk_mips16 upk; | |
1289 | int reg; | |
1290 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1291 | reg = read_signed_register (upk.regx); | |
1292 | if (reg != 0) | |
1293 | pc += (upk.offset << 1) + 2; | |
1294 | else | |
1295 | pc += 2; | |
1296 | break; | |
1297 | } | |
1298 | case 12: /* I8 Formats btez btnez */ | |
1299 | { | |
1300 | struct upk_mips16 upk; | |
1301 | int reg; | |
1302 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1303 | /* upk.regx contains the opcode */ | |
1304 | reg = read_signed_register (24); /* Test register is 24 */ | |
1305 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1306 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1307 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1308 | pc += (upk.offset << 1) + 2; | |
1309 | else | |
1310 | pc += 2; | |
1311 | break; | |
1312 | } | |
1313 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1314 | { | |
1315 | struct upk_mips16 upk; | |
1316 | /* upk.fmt = rrtype; */ | |
1317 | op = insn & 0x1f; | |
1318 | if (op == 0) | |
c5aa993b | 1319 | { |
12f02c2a AC |
1320 | int reg; |
1321 | upk.regx = (insn >> 8) & 0x07; | |
1322 | upk.regy = (insn >> 5) & 0x07; | |
1323 | switch (upk.regy) | |
c5aa993b | 1324 | { |
12f02c2a AC |
1325 | case 0: |
1326 | reg = upk.regx; | |
1327 | break; | |
1328 | case 1: | |
1329 | reg = 31; | |
1330 | break; /* Function return instruction */ | |
1331 | case 2: | |
1332 | reg = upk.regx; | |
1333 | break; | |
1334 | default: | |
1335 | reg = 31; | |
1336 | break; /* BOGUS Guess */ | |
c906108c | 1337 | } |
12f02c2a | 1338 | pc = read_signed_register (reg); |
c906108c | 1339 | } |
12f02c2a | 1340 | else |
c5aa993b | 1341 | pc += 2; |
12f02c2a AC |
1342 | break; |
1343 | } | |
1344 | case 30: | |
1345 | /* This is an instruction extension. Fetch the real instruction | |
1346 | (which follows the extension) and decode things based on | |
1347 | that. */ | |
1348 | { | |
1349 | pc += 2; | |
1350 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1351 | break; | |
1352 | } | |
1353 | default: | |
1354 | { | |
1355 | pc += 2; | |
1356 | break; | |
1357 | } | |
c906108c | 1358 | } |
c5aa993b | 1359 | return pc; |
12f02c2a | 1360 | } |
c906108c | 1361 | |
5a89d8aa | 1362 | static CORE_ADDR |
12f02c2a AC |
1363 | mips16_next_pc (CORE_ADDR pc) |
1364 | { | |
1365 | unsigned int insn = fetch_mips_16 (pc); | |
1366 | return extended_mips16_next_pc (pc, 0, insn); | |
1367 | } | |
1368 | ||
1369 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1370 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1371 | It works by decoding the current instruction and predicting where a |
1372 | branch will go. This isnt hard because all the data is available. | |
1373 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1374 | CORE_ADDR |
1375 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1376 | { |
c5aa993b JM |
1377 | if (pc & 0x01) |
1378 | return mips16_next_pc (pc); | |
1379 | else | |
1380 | return mips32_next_pc (pc); | |
12f02c2a | 1381 | } |
c906108c SS |
1382 | |
1383 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
ffabd70d KB |
1384 | NULL). |
1385 | ||
1386 | Note: kevinb/2002-08-09: The only caller of this function is (and | |
1387 | should remain) mips_frame_init_saved_regs(). In fact, | |
1388 | aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs() | |
1389 | does nothing more than set frame->saved_regs[SP_REGNUM]. These two | |
1390 | functions should really be combined and now that there is only one | |
1391 | caller, it should be straightforward. (Watch out for multiple returns | |
c4ac3e63 | 1392 | though.) */ |
c906108c | 1393 | |
d28e01f4 | 1394 | static void |
acdb74a0 | 1395 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1396 | { |
1397 | int ireg; | |
1398 | CORE_ADDR reg_position; | |
1399 | /* r0 bit means kernel trap */ | |
1400 | int kernel_trap; | |
1401 | /* What registers have been saved? Bitmasks. */ | |
1402 | unsigned long gen_mask, float_mask; | |
1403 | mips_extra_func_info_t proc_desc; | |
1404 | t_inst inst; | |
1405 | ||
1406 | frame_saved_regs_zalloc (fci); | |
1407 | ||
1408 | /* If it is the frame for sigtramp, the saved registers are located | |
1409 | in a sigcontext structure somewhere on the stack. | |
1410 | If the stack layout for sigtramp changes we might have to change these | |
1411 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1412 | #ifndef SIGFRAME_BASE | |
1413 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1414 | above the sigtramp frame. */ | |
1415 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1416 | /* FIXME! Are these correct?? */ | |
1417 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1418 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1419 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1420 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1421 | #endif | |
1422 | #ifndef SIGFRAME_REG_SIZE | |
1423 | /* FIXME! Is this correct?? */ | |
1424 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1425 | #endif | |
1426 | if (fci->signal_handler_caller) | |
1427 | { | |
1428 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1429 | { | |
c5aa993b JM |
1430 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1431 | + ireg * SIGFRAME_REG_SIZE; | |
1432 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1433 | } |
1434 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1435 | { | |
c5aa993b JM |
1436 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1437 | + ireg * SIGFRAME_REG_SIZE; | |
1438 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1439 | } |
1440 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1441 | return; | |
1442 | } | |
1443 | ||
cce74817 | 1444 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1445 | if (proc_desc == NULL) |
1446 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1447 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1448 | and set the saved_regs right away. */ | |
1449 | return; | |
1450 | ||
c5aa993b JM |
1451 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1452 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1453 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1454 | |
c5aa993b JM |
1455 | if ( /* In any frame other than the innermost or a frame interrupted by |
1456 | a signal, we assume that all registers have been saved. | |
1457 | This assumes that all register saves in a function happen before | |
1458 | the first function call. */ | |
1459 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1460 | |
c5aa993b JM |
1461 | /* In a dummy frame we know exactly where things are saved. */ |
1462 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1463 | |
c5aa993b JM |
1464 | /* Don't bother unless we are inside a function prologue. Outside the |
1465 | prologue, we know where everything is. */ | |
c906108c | 1466 | |
c5aa993b | 1467 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1468 | |
c5aa993b JM |
1469 | /* Not sure exactly what kernel_trap means, but if it means |
1470 | the kernel saves the registers without a prologue doing it, | |
1471 | we better not examine the prologue to see whether registers | |
1472 | have been saved yet. */ | |
1473 | && !kernel_trap) | |
c906108c SS |
1474 | { |
1475 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1476 | claims are saved have been saved yet. */ |
c906108c SS |
1477 | |
1478 | CORE_ADDR addr; | |
1479 | ||
1480 | /* Bitmasks; set if we have found a save for the register. */ | |
1481 | unsigned long gen_save_found = 0; | |
1482 | unsigned long float_save_found = 0; | |
1483 | int instlen; | |
1484 | ||
1485 | /* If the address is odd, assume this is MIPS16 code. */ | |
1486 | addr = PROC_LOW_ADDR (proc_desc); | |
1487 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1488 | ||
1489 | /* Scan through this function's instructions preceding the current | |
1490 | PC, and look for those that save registers. */ | |
1491 | while (addr < fci->pc) | |
1492 | { | |
1493 | inst = mips_fetch_instruction (addr); | |
1494 | if (pc_is_mips16 (addr)) | |
1495 | mips16_decode_reg_save (inst, &gen_save_found); | |
1496 | else | |
1497 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1498 | addr += instlen; | |
1499 | } | |
1500 | gen_mask = gen_save_found; | |
1501 | float_mask = float_save_found; | |
1502 | } | |
1503 | ||
1504 | /* Fill in the offsets for the registers which gen_mask says | |
1505 | were saved. */ | |
1506 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1507 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1508 | if (gen_mask & 0x80000000) |
1509 | { | |
1510 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1511 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1512 | } |
1513 | ||
1514 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1515 | of that normally used by gcc. Therefore, we have to fetch the first | |
1516 | instruction of the function, and if it's an entry instruction that | |
1517 | saves $s0 or $s1, correct their saved addresses. */ | |
1518 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1519 | { | |
1520 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1521 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1522 | { |
1523 | int reg; | |
1524 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1525 | |
c906108c SS |
1526 | /* Check if the ra register was pushed on the stack. */ |
1527 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1528 | if (inst & 0x20) | |
7a292a7a | 1529 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1530 | |
1531 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1532 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1533 | { |
1534 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1535 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1536 | } |
1537 | } | |
1538 | } | |
1539 | ||
1540 | /* Fill in the offsets for the registers which float_mask says | |
1541 | were saved. */ | |
1542 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1543 | ||
6acdf5c7 MS |
1544 | /* Apparently, the freg_offset gives the offset to the first 64 bit |
1545 | saved. | |
1546 | ||
1547 | When the ABI specifies 64 bit saved registers, the FREG_OFFSET | |
1548 | designates the first saved 64 bit register. | |
1549 | ||
1550 | When the ABI specifies 32 bit saved registers, the ``64 bit saved | |
1551 | DOUBLE'' consists of two adjacent 32 bit registers, Hence | |
1552 | FREG_OFFSET, designates the address of the lower register of the | |
1553 | register pair. Adjust the offset so that it designates the upper | |
1554 | register of the pair -- i.e., the address of the first saved 32 | |
1555 | bit register. */ | |
1556 | ||
1557 | if (MIPS_SAVED_REGSIZE == 4) | |
7a292a7a | 1558 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1559 | |
1560 | /* Fill in the offsets for the float registers which float_mask says | |
1561 | were saved. */ | |
c5aa993b | 1562 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1563 | if (float_mask & 0x80000000) |
1564 | { | |
c5aa993b | 1565 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1566 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1567 | } |
1568 | ||
1569 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1570 | } | |
1571 | ||
d28e01f4 KB |
1572 | /* Set up the 'saved_regs' array. This is a data structure containing |
1573 | the addresses on the stack where each register has been saved, for | |
1574 | each stack frame. Registers that have not been saved will have | |
1575 | zero here. The stack pointer register is special: rather than the | |
1576 | address where the stack register has been saved, saved_regs[SP_REGNUM] | |
1577 | will have the actual value of the previous frame's stack register. */ | |
1578 | ||
1579 | static void | |
1580 | mips_frame_init_saved_regs (struct frame_info *frame) | |
1581 | { | |
1582 | if (frame->saved_regs == NULL) | |
1583 | { | |
1584 | mips_find_saved_regs (frame); | |
1585 | } | |
1586 | frame->saved_regs[SP_REGNUM] = frame->frame; | |
1587 | } | |
1588 | ||
c906108c | 1589 | static CORE_ADDR |
acdb74a0 | 1590 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1591 | { |
64159455 AC |
1592 | int optimized; |
1593 | CORE_ADDR addr; | |
1594 | int realnum; | |
1595 | enum lval_type lval; | |
1596 | void *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); | |
1597 | frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum, | |
1598 | raw_buffer); | |
1599 | /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS | |
1600 | should have a pseudo register range that correspons to the ABI's, | |
1601 | rather than the ISA's, view of registers. These registers would | |
1602 | then implicitly describe their size and hence could be used | |
1603 | without the below munging. */ | |
1604 | if (lval == lval_memory) | |
c906108c | 1605 | { |
64159455 | 1606 | if (regno < 32) |
c906108c | 1607 | { |
64159455 AC |
1608 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are |
1609 | saved. */ | |
1610 | return read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
c906108c SS |
1611 | } |
1612 | } | |
64159455 AC |
1613 | |
1614 | return extract_signed_integer (raw_buffer, REGISTER_VIRTUAL_SIZE (regno)); | |
c906108c SS |
1615 | } |
1616 | ||
1617 | /* mips_addr_bits_remove - remove useless address bits */ | |
1618 | ||
875e1767 | 1619 | static CORE_ADDR |
acdb74a0 | 1620 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1621 | { |
5213ab06 AC |
1622 | if (GDB_TARGET_IS_MIPS64) |
1623 | { | |
4014092b | 1624 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1625 | { |
1626 | /* This hack is a work-around for existing boards using | |
1627 | PMON, the simulator, and any other 64-bit targets that | |
1628 | doesn't have true 64-bit addressing. On these targets, | |
1629 | the upper 32 bits of addresses are ignored by the | |
1630 | hardware. Thus, the PC or SP are likely to have been | |
1631 | sign extended to all 1s by instruction sequences that | |
1632 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1633 | code that loads an address is this: |
1634 | lui $r2, <upper 16 bits> | |
1635 | ori $r2, <lower 16 bits> | |
1636 | But the lui sign-extends the value such that the upper 32 | |
1637 | bits may be all 1s. The workaround is simply to mask off | |
1638 | these bits. In the future, gcc may be changed to support | |
1639 | true 64-bit addressing, and this masking will have to be | |
1640 | disabled. */ | |
5213ab06 AC |
1641 | addr &= (CORE_ADDR) 0xffffffff; |
1642 | } | |
1643 | } | |
4014092b | 1644 | else if (mips_mask_address_p ()) |
5213ab06 | 1645 | { |
4014092b AC |
1646 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1647 | masking off bits, instead, the actual target should be asking | |
1648 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1649 | /* Even when GDB is configured for some 32-bit targets |
1650 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1651 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1652 | useless bits from addresses. */ | |
c5aa993b | 1653 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1654 | } |
c906108c SS |
1655 | return addr; |
1656 | } | |
1657 | ||
9022177c DJ |
1658 | /* mips_software_single_step() is called just before we want to resume |
1659 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1660 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1661 | the target of the coming instruction and breakpoint it. |
1662 | ||
1663 | single_step is also called just after the inferior stops. If we had | |
1664 | set up a simulated single-step, we undo our damage. */ | |
1665 | ||
1666 | void | |
1667 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1668 | { | |
1669 | static CORE_ADDR next_pc; | |
1670 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1671 | static binsn_quantum break_mem; | |
1672 | CORE_ADDR pc; | |
1673 | ||
1674 | if (insert_breakpoints_p) | |
1675 | { | |
1676 | pc = read_register (PC_REGNUM); | |
1677 | next_pc = mips_next_pc (pc); | |
1678 | ||
1679 | target_insert_breakpoint (next_pc, break_mem); | |
1680 | } | |
1681 | else | |
1682 | target_remove_breakpoint (next_pc, break_mem); | |
1683 | } | |
1684 | ||
10312cc4 | 1685 | static void |
acdb74a0 | 1686 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1687 | { |
1688 | CORE_ADDR pc, tmp; | |
1689 | ||
1690 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1691 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
5a89d8aa | 1692 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
c5aa993b | 1693 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1694 | } |
1695 | ||
1696 | ||
f7ab6ec6 | 1697 | static CORE_ADDR |
acdb74a0 | 1698 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1699 | { |
1700 | CORE_ADDR saved_pc; | |
cce74817 | 1701 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1702 | /* We have to get the saved pc from the sigcontext |
1703 | if it is a signal handler frame. */ | |
1704 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1705 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1706 | |
c5aa993b | 1707 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1708 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1709 | else |
7a292a7a | 1710 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1711 | |
1712 | return ADDR_BITS_REMOVE (saved_pc); | |
1713 | } | |
1714 | ||
1715 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1716 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1717 | |
1718 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1719 | has already been set for this register, do nothing; this way we will | |
1720 | only recognize the first save of a given register in a function prologue. | |
1721 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1722 | ||
1723 | static void | |
acdb74a0 | 1724 | set_reg_offset (int regno, CORE_ADDR offset) |
c906108c | 1725 | { |
cce74817 JM |
1726 | if (temp_saved_regs[regno] == 0) |
1727 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1728 | } |
1729 | ||
1730 | ||
1731 | /* Test whether the PC points to the return instruction at the | |
1732 | end of a function. */ | |
1733 | ||
c5aa993b | 1734 | static int |
acdb74a0 | 1735 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1736 | { |
1737 | if (pc_is_mips16 (pc)) | |
1738 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1739 | generates a "jr $ra"; other times it generates code to load | |
1740 | the return address from the stack to an accessible register (such | |
1741 | as $a3), then a "jr" using that register. This second case | |
1742 | is almost impossible to distinguish from an indirect jump | |
1743 | used for switch statements, so we don't even try. */ | |
1744 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1745 | else | |
1746 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1747 | } | |
1748 | ||
1749 | ||
1750 | /* This fencepost looks highly suspicious to me. Removing it also | |
1751 | seems suspicious as it could affect remote debugging across serial | |
1752 | lines. */ | |
1753 | ||
1754 | static CORE_ADDR | |
acdb74a0 | 1755 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1756 | { |
c5aa993b JM |
1757 | CORE_ADDR start_pc; |
1758 | CORE_ADDR fence; | |
1759 | int instlen; | |
1760 | int seen_adjsp = 0; | |
c906108c | 1761 | |
c5aa993b JM |
1762 | pc = ADDR_BITS_REMOVE (pc); |
1763 | start_pc = pc; | |
1764 | fence = start_pc - heuristic_fence_post; | |
1765 | if (start_pc == 0) | |
1766 | return 0; | |
c906108c | 1767 | |
c5aa993b JM |
1768 | if (heuristic_fence_post == UINT_MAX |
1769 | || fence < VM_MIN_ADDRESS) | |
1770 | fence = VM_MIN_ADDRESS; | |
c906108c | 1771 | |
c5aa993b | 1772 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1773 | |
c5aa993b JM |
1774 | /* search back for previous return */ |
1775 | for (start_pc -= instlen;; start_pc -= instlen) | |
1776 | if (start_pc < fence) | |
1777 | { | |
1778 | /* It's not clear to me why we reach this point when | |
1779 | stop_soon_quietly, but with this test, at least we | |
1780 | don't print out warnings for every child forked (eg, on | |
1781 | decstation). 22apr93 rich@cygnus.com. */ | |
1782 | if (!stop_soon_quietly) | |
c906108c | 1783 | { |
c5aa993b JM |
1784 | static int blurb_printed = 0; |
1785 | ||
1786 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1787 | paddr_nz (pc)); | |
1788 | ||
1789 | if (!blurb_printed) | |
c906108c | 1790 | { |
c5aa993b JM |
1791 | /* This actually happens frequently in embedded |
1792 | development, when you first connect to a board | |
1793 | and your stack pointer and pc are nowhere in | |
1794 | particular. This message needs to give people | |
1795 | in that situation enough information to | |
1796 | determine that it's no big deal. */ | |
1797 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1798 | GDB is unable to find the start of the function at 0x%s\n\ |
1799 | and thus can't determine the size of that function's stack frame.\n\ | |
1800 | This means that GDB may be unable to access that stack frame, or\n\ | |
1801 | the frames below it.\n\ | |
1802 | This problem is most likely caused by an invalid program counter or\n\ | |
1803 | stack pointer.\n\ | |
1804 | However, if you think GDB should simply search farther back\n\ | |
1805 | from 0x%s for code which looks like the beginning of a\n\ | |
1806 | function, you can increase the range of the search using the `set\n\ | |
1807 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1808 | paddr_nz (pc), paddr_nz (pc)); |
1809 | blurb_printed = 1; | |
c906108c | 1810 | } |
c906108c SS |
1811 | } |
1812 | ||
c5aa993b JM |
1813 | return 0; |
1814 | } | |
1815 | else if (pc_is_mips16 (start_pc)) | |
1816 | { | |
1817 | unsigned short inst; | |
1818 | ||
1819 | /* On MIPS16, any one of the following is likely to be the | |
1820 | start of a function: | |
1821 | entry | |
1822 | addiu sp,-n | |
1823 | daddiu sp,-n | |
1824 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1825 | inst = mips_fetch_instruction (start_pc); | |
1826 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1827 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1828 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1829 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1830 | break; | |
1831 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1832 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1833 | seen_adjsp = 1; | |
1834 | else | |
1835 | seen_adjsp = 0; | |
1836 | } | |
1837 | else if (mips_about_to_return (start_pc)) | |
1838 | { | |
1839 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1840 | break; | |
1841 | } | |
1842 | ||
c5aa993b | 1843 | return start_pc; |
c906108c SS |
1844 | } |
1845 | ||
1846 | /* Fetch the immediate value from a MIPS16 instruction. | |
1847 | If the previous instruction was an EXTEND, use it to extend | |
1848 | the upper bits of the immediate value. This is a helper function | |
1849 | for mips16_heuristic_proc_desc. */ | |
1850 | ||
1851 | static int | |
acdb74a0 AC |
1852 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1853 | unsigned short inst, /* current instruction */ | |
1854 | int nbits, /* number of bits in imm field */ | |
1855 | int scale, /* scale factor to be applied to imm */ | |
1856 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1857 | { |
1858 | int offset; | |
1859 | ||
1860 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1861 | { | |
1862 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1863 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1864 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1865 | return offset | (inst & 0x1f); | |
1866 | } | |
1867 | else | |
1868 | { | |
1869 | int max_imm = 1 << nbits; | |
1870 | int mask = max_imm - 1; | |
1871 | int sign_bit = max_imm >> 1; | |
1872 | ||
1873 | offset = inst & mask; | |
1874 | if (is_signed && (offset & sign_bit)) | |
1875 | offset = 0 - (max_imm - offset); | |
1876 | return offset * scale; | |
1877 | } | |
1878 | } | |
1879 | ||
1880 | ||
1881 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1882 | stream from start_pc to limit_pc. */ | |
1883 | ||
1884 | static void | |
acdb74a0 AC |
1885 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1886 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1887 | { |
1888 | CORE_ADDR cur_pc; | |
1889 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1890 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1891 | unsigned inst = 0; /* current instruction */ | |
1892 | unsigned entry_inst = 0; /* the entry instruction */ | |
1893 | int reg, offset; | |
1894 | ||
c5aa993b JM |
1895 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1896 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1897 | |
1898 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1899 | { | |
1900 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1901 | the immediate offset extension from it in mips16_get_imm. */ | |
1902 | prev_inst = inst; | |
1903 | ||
1904 | /* Fetch and decode the instruction. */ | |
1905 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1906 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1907 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1908 | { | |
1909 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1910 | if (offset < 0) /* negative stack adjustment? */ |
1911 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1912 | else |
1913 | /* Exit loop if a positive stack adjustment is found, which | |
1914 | usually means that the stack cleanup code in the function | |
1915 | epilogue is reached. */ | |
1916 | break; | |
1917 | } | |
1918 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1919 | { | |
1920 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1921 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1922 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1923 | set_reg_offset (reg, sp + offset); |
1924 | } | |
1925 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1926 | { | |
1927 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1928 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1929 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1930 | set_reg_offset (reg, sp + offset); |
1931 | } | |
1932 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1933 | { | |
1934 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1935 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1936 | set_reg_offset (RA_REGNUM, sp + offset); |
1937 | } | |
1938 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1939 | { | |
1940 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1941 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1942 | set_reg_offset (RA_REGNUM, sp + offset); |
1943 | } | |
c5aa993b | 1944 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1945 | { |
1946 | frame_addr = sp; | |
1947 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1948 | } | |
1949 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1950 | { | |
1951 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1952 | frame_addr = sp + offset; | |
1953 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1954 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1955 | } | |
1956 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1957 | { | |
1958 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1959 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1960 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1961 | set_reg_offset (reg, frame_addr + offset); |
1962 | } | |
1963 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1964 | { | |
1965 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1966 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1967 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1968 | set_reg_offset (reg, frame_addr + offset); |
1969 | } | |
c5aa993b JM |
1970 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1971 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1972 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1973 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1974 | } |
1975 | ||
c5aa993b JM |
1976 | /* The entry instruction is typically the first instruction in a function, |
1977 | and it stores registers at offsets relative to the value of the old SP | |
1978 | (before the prologue). But the value of the sp parameter to this | |
1979 | function is the new SP (after the prologue has been executed). So we | |
1980 | can't calculate those offsets until we've seen the entire prologue, | |
1981 | and can calculate what the old SP must have been. */ | |
1982 | if (entry_inst != 0) | |
1983 | { | |
1984 | int areg_count = (entry_inst >> 8) & 7; | |
1985 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1986 | |
c5aa993b JM |
1987 | /* The entry instruction always subtracts 32 from the SP. */ |
1988 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1989 | |
c5aa993b JM |
1990 | /* Now we can calculate what the SP must have been at the |
1991 | start of the function prologue. */ | |
1992 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1993 | |
c5aa993b JM |
1994 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1995 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1996 | { | |
1997 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1998 | set_reg_offset (reg, sp + offset); | |
1999 | offset += MIPS_SAVED_REGSIZE; | |
2000 | } | |
c906108c | 2001 | |
c5aa993b JM |
2002 | /* Check if the ra register was pushed on the stack. */ |
2003 | offset = -4; | |
2004 | if (entry_inst & 0x20) | |
2005 | { | |
2006 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
2007 | set_reg_offset (RA_REGNUM, sp + offset); | |
2008 | offset -= MIPS_SAVED_REGSIZE; | |
2009 | } | |
c906108c | 2010 | |
c5aa993b JM |
2011 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2012 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2013 | { | |
2014 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
2015 | set_reg_offset (reg, sp + offset); | |
2016 | offset -= MIPS_SAVED_REGSIZE; | |
2017 | } | |
2018 | } | |
c906108c SS |
2019 | } |
2020 | ||
2021 | static void | |
fba45db2 KB |
2022 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2023 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2024 | { |
2025 | CORE_ADDR cur_pc; | |
c5aa993b | 2026 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2027 | restart: |
cce74817 | 2028 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2029 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2030 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2031 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2032 | { | |
2033 | unsigned long inst, high_word, low_word; | |
2034 | int reg; | |
2035 | ||
2036 | /* Fetch the instruction. */ | |
2037 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2038 | ||
2039 | /* Save some code by pre-extracting some useful fields. */ | |
2040 | high_word = (inst >> 16) & 0xffff; | |
2041 | low_word = inst & 0xffff; | |
2042 | reg = high_word & 0x1f; | |
2043 | ||
c5aa993b | 2044 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2045 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2046 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2047 | { | |
2048 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2049 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2050 | else |
2051 | /* Exit loop if a positive stack adjustment is found, which | |
2052 | usually means that the stack cleanup code in the function | |
2053 | epilogue is reached. */ | |
2054 | break; | |
2055 | } | |
2056 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2057 | { | |
c5aa993b | 2058 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
2059 | set_reg_offset (reg, sp + low_word); |
2060 | } | |
2061 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2062 | { | |
2063 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2064 | but the register size used is only 32 bits. Make the address | |
2065 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2066 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
2067 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
2068 | } | |
c5aa993b | 2069 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2070 | { |
2071 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2072 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2073 | frame_addr = sp + low_word; | |
c906108c SS |
2074 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2075 | { | |
2076 | unsigned alloca_adjust; | |
2077 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2078 | frame_addr = read_next_frame_reg (next_frame, 30); |
2079 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
2080 | if (alloca_adjust > 0) |
2081 | { | |
2082 | /* FP > SP + frame_size. This may be because | |
2083 | * of an alloca or somethings similar. | |
2084 | * Fix sp to "pre-alloca" value, and try again. | |
2085 | */ | |
2086 | sp += alloca_adjust; | |
2087 | goto restart; | |
2088 | } | |
2089 | } | |
2090 | } | |
c5aa993b JM |
2091 | /* move $30,$sp. With different versions of gas this will be either |
2092 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2093 | Accept any one of these. */ | |
c906108c SS |
2094 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2095 | { | |
2096 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2097 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2098 | { | |
2099 | unsigned alloca_adjust; | |
2100 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2101 | frame_addr = read_next_frame_reg (next_frame, 30); |
2102 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
2103 | if (alloca_adjust > 0) |
2104 | { | |
2105 | /* FP > SP + frame_size. This may be because | |
2106 | * of an alloca or somethings similar. | |
2107 | * Fix sp to "pre-alloca" value, and try again. | |
2108 | */ | |
2109 | sp += alloca_adjust; | |
2110 | goto restart; | |
2111 | } | |
2112 | } | |
2113 | } | |
c5aa993b | 2114 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2115 | { |
c5aa993b | 2116 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
2117 | set_reg_offset (reg, frame_addr + low_word); |
2118 | } | |
2119 | } | |
2120 | } | |
2121 | ||
2122 | static mips_extra_func_info_t | |
acdb74a0 | 2123 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2124 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2125 | { |
479412cd DJ |
2126 | CORE_ADDR sp; |
2127 | ||
2128 | if (cur_frame) | |
2129 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
2130 | else | |
2131 | sp = 0; | |
c906108c | 2132 | |
c5aa993b JM |
2133 | if (start_pc == 0) |
2134 | return NULL; | |
2135 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 2136 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2137 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2138 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2139 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2140 | ||
2141 | if (start_pc + 200 < limit_pc) | |
2142 | limit_pc = start_pc + 200; | |
2143 | if (pc_is_mips16 (start_pc)) | |
2144 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2145 | else | |
2146 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2147 | return &temp_proc_desc; | |
2148 | } | |
2149 | ||
6c0d6680 DJ |
2150 | struct mips_objfile_private |
2151 | { | |
2152 | bfd_size_type size; | |
2153 | char *contents; | |
2154 | }; | |
2155 | ||
2156 | /* Global used to communicate between non_heuristic_proc_desc and | |
2157 | compare_pdr_entries within qsort (). */ | |
2158 | static bfd *the_bfd; | |
2159 | ||
2160 | static int | |
2161 | compare_pdr_entries (const void *a, const void *b) | |
2162 | { | |
2163 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2164 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2165 | ||
2166 | if (lhs < rhs) | |
2167 | return -1; | |
2168 | else if (lhs == rhs) | |
2169 | return 0; | |
2170 | else | |
2171 | return 1; | |
2172 | } | |
2173 | ||
c906108c | 2174 | static mips_extra_func_info_t |
acdb74a0 | 2175 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2176 | { |
2177 | CORE_ADDR startaddr; | |
2178 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2179 | struct block *b = block_for_pc (pc); |
c906108c | 2180 | struct symbol *sym; |
6c0d6680 DJ |
2181 | struct obj_section *sec; |
2182 | struct mips_objfile_private *priv; | |
2183 | ||
2184 | if (PC_IN_CALL_DUMMY (pc, 0, 0)) | |
2185 | return NULL; | |
c906108c SS |
2186 | |
2187 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2188 | if (addrptr) | |
2189 | *addrptr = startaddr; | |
6c0d6680 DJ |
2190 | |
2191 | priv = NULL; | |
2192 | ||
2193 | sec = find_pc_section (pc); | |
2194 | if (sec != NULL) | |
c906108c | 2195 | { |
6c0d6680 DJ |
2196 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2197 | ||
2198 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2199 | the information normally found in ECOFF PDRs. */ | |
2200 | ||
2201 | the_bfd = sec->objfile->obfd; | |
2202 | if (priv == NULL | |
2203 | && (the_bfd->format == bfd_object | |
2204 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2205 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2206 | { | |
2207 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2208 | This means that we should not bother with this method on 64-bit | |
2209 | targets (until that is fixed). */ | |
2210 | ||
2211 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2212 | sizeof (struct mips_objfile_private)); | |
2213 | priv->size = 0; | |
2214 | sec->objfile->obj_private = priv; | |
2215 | } | |
2216 | else if (priv == NULL) | |
2217 | { | |
2218 | asection *bfdsec; | |
2219 | ||
2220 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2221 | sizeof (struct mips_objfile_private)); | |
2222 | ||
2223 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2224 | if (bfdsec != NULL) | |
2225 | { | |
2226 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2227 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2228 | priv->size); | |
2229 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2230 | priv->contents, 0, priv->size); | |
2231 | ||
2232 | /* In general, the .pdr section is sorted. However, in the | |
2233 | presence of multiple code sections (and other corner cases) | |
2234 | it can become unsorted. Sort it so that we can use a faster | |
2235 | binary search. */ | |
2236 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2237 | } | |
2238 | else | |
2239 | priv->size = 0; | |
2240 | ||
2241 | sec->objfile->obj_private = priv; | |
2242 | } | |
2243 | the_bfd = NULL; | |
2244 | ||
2245 | if (priv->size != 0) | |
2246 | { | |
2247 | int low, mid, high; | |
2248 | char *ptr; | |
2249 | ||
2250 | low = 0; | |
2251 | high = priv->size / 32; | |
2252 | ||
2253 | do | |
2254 | { | |
2255 | CORE_ADDR pdr_pc; | |
2256 | ||
2257 | mid = (low + high) / 2; | |
2258 | ||
2259 | ptr = priv->contents + mid * 32; | |
2260 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2261 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2262 | SECT_OFF_TEXT (sec->objfile)); | |
2263 | if (pdr_pc == startaddr) | |
2264 | break; | |
2265 | if (pdr_pc > startaddr) | |
2266 | high = mid; | |
2267 | else | |
2268 | low = mid + 1; | |
2269 | } | |
2270 | while (low != high); | |
2271 | ||
2272 | if (low != high) | |
2273 | { | |
2274 | struct symbol *sym = find_pc_function (pc); | |
2275 | ||
2276 | /* Fill in what we need of the proc_desc. */ | |
2277 | proc_desc = (mips_extra_func_info_t) | |
2278 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2279 | sizeof (struct mips_extra_func_info)); | |
2280 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2281 | ||
2282 | /* Only used for dummy frames. */ | |
2283 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2284 | ||
2285 | PROC_FRAME_OFFSET (proc_desc) | |
2286 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2287 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2288 | ptr + 24); | |
2289 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2290 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2291 | ptr + 4); | |
2292 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2293 | ptr + 12); | |
2294 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2295 | ptr + 8); | |
2296 | PROC_FREG_OFFSET (proc_desc) | |
2297 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2298 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2299 | ptr + 28); | |
2300 | proc_desc->pdr.isym = (long) sym; | |
2301 | ||
2302 | return proc_desc; | |
2303 | } | |
2304 | } | |
c906108c SS |
2305 | } |
2306 | ||
6c0d6680 DJ |
2307 | if (b == NULL) |
2308 | return NULL; | |
2309 | ||
2310 | if (startaddr > BLOCK_START (b)) | |
2311 | { | |
2312 | /* This is the "pathological" case referred to in a comment in | |
2313 | print_frame_info. It might be better to move this check into | |
2314 | symbol reading. */ | |
2315 | return NULL; | |
2316 | } | |
2317 | ||
2318 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
2319 | ||
c906108c SS |
2320 | /* If we never found a PDR for this function in symbol reading, then |
2321 | examine prologues to find the information. */ | |
2322 | if (sym) | |
2323 | { | |
2324 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2325 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2326 | return NULL; | |
2327 | else | |
2328 | return proc_desc; | |
2329 | } | |
2330 | else | |
2331 | return NULL; | |
2332 | } | |
2333 | ||
2334 | ||
2335 | static mips_extra_func_info_t | |
479412cd | 2336 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2337 | { |
2338 | mips_extra_func_info_t proc_desc; | |
2339 | CORE_ADDR startaddr; | |
2340 | ||
2341 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2342 | ||
2343 | if (proc_desc) | |
2344 | { | |
2345 | /* IF this is the topmost frame AND | |
2346 | * (this proc does not have debugging information OR | |
2347 | * the PC is in the procedure prologue) | |
2348 | * THEN create a "heuristic" proc_desc (by analyzing | |
2349 | * the actual code) to replace the "official" proc_desc. | |
2350 | */ | |
2351 | if (next_frame == NULL) | |
2352 | { | |
2353 | struct symtab_and_line val; | |
2354 | struct symbol *proc_symbol = | |
c86b5b38 | 2355 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2356 | |
2357 | if (proc_symbol) | |
2358 | { | |
2359 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2360 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2361 | 0); |
2362 | val.pc = val.end ? val.end : pc; | |
2363 | } | |
2364 | if (!proc_symbol || pc < val.pc) | |
2365 | { | |
2366 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2367 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2368 | pc, next_frame, cur_frame); | |
c906108c SS |
2369 | if (found_heuristic) |
2370 | proc_desc = found_heuristic; | |
2371 | } | |
2372 | } | |
2373 | } | |
2374 | else | |
2375 | { | |
2376 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2377 | by procedure call dummys. However, the procedures being called ought |
2378 | to have their own proc_descs, and even if they don't, | |
2379 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
2380 | |
2381 | register struct linked_proc_info *link; | |
2382 | ||
2383 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2384 | if (PROC_LOW_ADDR (&link->info) <= pc |
2385 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2386 | return &link->info; |
2387 | ||
2388 | if (startaddr == 0) | |
2389 | startaddr = heuristic_proc_start (pc); | |
2390 | ||
2391 | proc_desc = | |
479412cd | 2392 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2393 | } |
2394 | return proc_desc; | |
2395 | } | |
2396 | ||
2397 | static CORE_ADDR | |
acdb74a0 AC |
2398 | get_frame_pointer (struct frame_info *frame, |
2399 | mips_extra_func_info_t proc_desc) | |
c906108c | 2400 | { |
c86b5b38 MS |
2401 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, |
2402 | PROC_FRAME_REG (proc_desc)) + | |
2403 | PROC_FRAME_OFFSET (proc_desc) - | |
2404 | PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2405 | } |
2406 | ||
5a89d8aa | 2407 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2408 | |
f7ab6ec6 | 2409 | static CORE_ADDR |
acdb74a0 | 2410 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2411 | { |
2412 | mips_extra_func_info_t proc_desc; | |
2413 | CORE_ADDR tmp; | |
c5aa993b | 2414 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
2415 | |
2416 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2417 | return 0; | |
2418 | ||
2419 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2420 | PC of the caller of that stub. */ | |
5a89d8aa | 2421 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2422 | saved_pc = tmp; |
2423 | ||
2424 | /* Look up the procedure descriptor for this PC. */ | |
479412cd | 2425 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2426 | if (!proc_desc) |
2427 | return 0; | |
2428 | ||
2429 | cached_proc_desc = proc_desc; | |
2430 | ||
2431 | /* If no frame pointer and frame size is zero, we must be at end | |
2432 | of stack (or otherwise hosed). If we don't check frame size, | |
2433 | we loop forever if we see a zero size frame. */ | |
2434 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2435 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2436 | /* The previous frame from a sigtramp frame might be frameless |
2437 | and have frame size zero. */ | |
2438 | && !frame->signal_handler_caller | |
2439 | /* Check if this is a call dummy frame. */ | |
f7ab6ec6 | 2440 | && frame->pc != CALL_DUMMY_ADDRESS ()) |
c906108c SS |
2441 | return 0; |
2442 | else | |
2443 | return get_frame_pointer (frame, proc_desc); | |
2444 | } | |
2445 | ||
f7ab6ec6 | 2446 | static void |
acdb74a0 | 2447 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2448 | { |
2449 | int regnum; | |
2450 | ||
2451 | /* Use proc_desc calculated in frame_chain */ | |
2452 | mips_extra_func_info_t proc_desc = | |
c86b5b38 | 2453 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1); |
c906108c | 2454 | |
cce74817 JM |
2455 | fci->extra_info = (struct frame_extra_info *) |
2456 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
2457 | ||
c906108c | 2458 | fci->saved_regs = NULL; |
cce74817 | 2459 | fci->extra_info->proc_desc = |
c906108c SS |
2460 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2461 | if (proc_desc) | |
2462 | { | |
2463 | /* Fixup frame-pointer - only needed for top frame */ | |
2464 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2465 | Get the value of the frame relative sp, procedure might have been |
2466 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2467 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2468 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2469 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2470 | else | |
2471 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2472 | ||
2473 | if (proc_desc == &temp_proc_desc) | |
2474 | { | |
2475 | char *name; | |
2476 | ||
2477 | /* Do not set the saved registers for a sigtramp frame, | |
2478 | mips_find_saved_registers will do that for us. | |
2479 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2480 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2481 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
d7bd68ca | 2482 | if (!PC_IN_SIGTRAMP (fci->pc, name)) |
c906108c | 2483 | { |
c5aa993b | 2484 | frame_saved_regs_zalloc (fci); |
cce74817 | 2485 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2486 | fci->saved_regs[PC_REGNUM] |
2487 | = fci->saved_regs[RA_REGNUM]; | |
ffabd70d KB |
2488 | /* Set value of previous frame's stack pointer. Remember that |
2489 | saved_regs[SP_REGNUM] is special in that it contains the | |
2490 | value of the stack pointer register. The other saved_regs | |
2491 | values are addresses (in the inferior) at which a given | |
2492 | register's value may be found. */ | |
2493 | fci->saved_regs[SP_REGNUM] = fci->frame; | |
c906108c SS |
2494 | } |
2495 | } | |
2496 | ||
2497 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2498 | /* assume we can't tell how many args for now */ |
2499 | fci->extra_info->num_args = -1; | |
c906108c SS |
2500 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2501 | { | |
c5aa993b | 2502 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2503 | { |
cce74817 | 2504 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2505 | break; |
2506 | } | |
c5aa993b | 2507 | } |
c906108c SS |
2508 | } |
2509 | } | |
2510 | ||
2511 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2512 | we basically have to look at symbol information for the function | |
2513 | that we stopped in, which tells us *which* register (if any) is | |
2514 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2515 | the frame itself is at. |
c906108c SS |
2516 | |
2517 | This presents a problem when trying to examine a stack in memory | |
2518 | (that isn't executing at the moment), using the "frame" command. We | |
2519 | don't have a PC, nor do we have any registers except SP. | |
2520 | ||
2521 | This routine takes two arguments, SP and PC, and tries to make the | |
2522 | cached frames look as if these two arguments defined a frame on the | |
2523 | cache. This allows the rest of info frame to extract the important | |
2524 | arguments without difficulty. */ | |
2525 | ||
2526 | struct frame_info * | |
acdb74a0 | 2527 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2528 | { |
2529 | if (argc != 2) | |
2530 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2531 | ||
2532 | return create_new_frame (argv[0], argv[1]); | |
2533 | } | |
2534 | ||
f09ded24 AC |
2535 | /* According to the current ABI, should the type be passed in a |
2536 | floating-point register (assuming that there is space)? When there | |
2537 | is no FPU, FP are not even considered as possibile candidates for | |
2538 | FP registers and, consequently this returns false - forces FP | |
2539 | arguments into integer registers. */ | |
2540 | ||
2541 | static int | |
2542 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2543 | { | |
2544 | return ((typecode == TYPE_CODE_FLT | |
2545 | || (MIPS_EABI | |
2546 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2547 | && TYPE_NFIELDS (arg_type) == 1 | |
2548 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2549 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2550 | } |
2551 | ||
49e790b0 DJ |
2552 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2553 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2554 | ||
2555 | static int | |
2556 | mips_type_needs_double_align (struct type *type) | |
2557 | { | |
2558 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2559 | |
49e790b0 DJ |
2560 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2561 | return 1; | |
2562 | else if (typecode == TYPE_CODE_STRUCT) | |
2563 | { | |
2564 | if (TYPE_NFIELDS (type) < 1) | |
2565 | return 0; | |
2566 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2567 | } | |
2568 | else if (typecode == TYPE_CODE_UNION) | |
2569 | { | |
361d1df0 | 2570 | int i, n; |
49e790b0 DJ |
2571 | |
2572 | n = TYPE_NFIELDS (type); | |
2573 | for (i = 0; i < n; i++) | |
2574 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2575 | return 1; | |
2576 | return 0; | |
2577 | } | |
2578 | return 0; | |
2579 | } | |
2580 | ||
cb3d25d1 MS |
2581 | /* Macros to round N up or down to the next A boundary; |
2582 | A must be a power of two. */ | |
2583 | ||
2584 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2585 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
2586 | ||
f7ab6ec6 | 2587 | static CORE_ADDR |
46e0f506 MS |
2588 | mips_eabi_push_arguments (int nargs, |
2589 | struct value **args, | |
2590 | CORE_ADDR sp, | |
2591 | int struct_return, | |
2592 | CORE_ADDR struct_addr) | |
c906108c SS |
2593 | { |
2594 | int argreg; | |
2595 | int float_argreg; | |
2596 | int argnum; | |
2597 | int len = 0; | |
2598 | int stack_offset = 0; | |
2599 | ||
c906108c | 2600 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2601 | are properly aligned. The stack has to be at least 64-bit |
2602 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2603 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2604 | aligned, so we round to this widest known alignment. */ | |
2605 | ||
c906108c | 2606 | sp = ROUND_DOWN (sp, 16); |
cce41527 | 2607 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2608 | |
46e0f506 | 2609 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2610 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2611 | passed in registers, but that's OK. */ |
c906108c | 2612 | for (argnum = 0; argnum < nargs; argnum++) |
46e0f506 MS |
2613 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
2614 | MIPS_STACK_ARGSIZE); | |
c906108c SS |
2615 | sp -= ROUND_UP (len, 16); |
2616 | ||
9ace0497 | 2617 | if (mips_debug) |
46e0f506 MS |
2618 | fprintf_unfiltered (gdb_stdlog, |
2619 | "mips_eabi_push_arguments: sp=0x%s allocated %d\n", | |
cb3d25d1 | 2620 | paddr_nz (sp), ROUND_UP (len, 16)); |
9ace0497 | 2621 | |
c906108c SS |
2622 | /* Initialize the integer and float register pointers. */ |
2623 | argreg = A0_REGNUM; | |
2624 | float_argreg = FPA0_REGNUM; | |
2625 | ||
46e0f506 | 2626 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2627 | if (struct_return) |
9ace0497 AC |
2628 | { |
2629 | if (mips_debug) | |
2630 | fprintf_unfiltered (gdb_stdlog, | |
46e0f506 | 2631 | "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2632 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2633 | write_register (argreg++, struct_addr); |
2634 | } | |
c906108c SS |
2635 | |
2636 | /* Now load as many as possible of the first arguments into | |
2637 | registers, and push the rest onto the stack. Loop thru args | |
2638 | from first to last. */ | |
2639 | for (argnum = 0; argnum < nargs; argnum++) | |
2640 | { | |
2641 | char *val; | |
cb3d25d1 | 2642 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); |
ea7c478f | 2643 | struct value *arg = args[argnum]; |
c906108c SS |
2644 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2645 | int len = TYPE_LENGTH (arg_type); | |
2646 | enum type_code typecode = TYPE_CODE (arg_type); | |
2647 | ||
9ace0497 AC |
2648 | if (mips_debug) |
2649 | fprintf_unfiltered (gdb_stdlog, | |
46e0f506 | 2650 | "mips_eabi_push_arguments: %d len=%d type=%d", |
acdb74a0 | 2651 | argnum + 1, len, (int) typecode); |
9ace0497 | 2652 | |
c906108c | 2653 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2654 | reference. */ |
2655 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2656 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2657 | { |
7a292a7a | 2658 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2659 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2660 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2661 | val = valbuf; |
9ace0497 AC |
2662 | if (mips_debug) |
2663 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2664 | } |
2665 | else | |
c5aa993b | 2666 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2667 | |
2668 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2669 | even-numbered floating point register. Round the FP register |
2670 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2671 | left. Non MIPS_EABI targets also pass the FP in the integer |
2672 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2673 | if (!FP_REGISTER_DOUBLE |
2674 | && fp_register_arg_p (typecode, arg_type)) | |
2675 | { | |
2676 | if ((float_argreg & 1)) | |
2677 | float_argreg++; | |
2678 | } | |
c906108c SS |
2679 | |
2680 | /* Floating point arguments passed in registers have to be | |
2681 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2682 | are passed in register pairs; the even register gets |
2683 | the low word, and the odd register gets the high word. | |
2684 | On non-EABI processors, the first two floating point arguments are | |
2685 | also copied to general registers, because MIPS16 functions | |
2686 | don't use float registers for arguments. This duplication of | |
2687 | arguments in general registers can't hurt non-MIPS16 functions | |
2688 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2689 | /* MIPS_EABI squeezes a struct that contains a single floating |
2690 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2691 | stack. */ |
f09ded24 AC |
2692 | if (fp_register_arg_p (typecode, arg_type) |
2693 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2694 | { |
2695 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2696 | { | |
d7449b42 | 2697 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2698 | unsigned long regval; |
2699 | ||
2700 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2701 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2702 | if (mips_debug) |
acdb74a0 | 2703 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2704 | float_argreg, phex (regval, 4)); |
c906108c | 2705 | write_register (float_argreg++, regval); |
c906108c SS |
2706 | |
2707 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2708 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2709 | if (mips_debug) |
acdb74a0 | 2710 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2711 | float_argreg, phex (regval, 4)); |
c906108c | 2712 | write_register (float_argreg++, regval); |
c906108c SS |
2713 | } |
2714 | else | |
2715 | { | |
2716 | /* This is a floating point value that fits entirely | |
2717 | in a single register. */ | |
53a5351d | 2718 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2719 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2720 | LONGEST regval = extract_unsigned_integer (val, len); |
2721 | if (mips_debug) | |
acdb74a0 | 2722 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2723 | float_argreg, phex (regval, len)); |
c906108c | 2724 | write_register (float_argreg++, regval); |
c906108c SS |
2725 | } |
2726 | } | |
2727 | else | |
2728 | { | |
2729 | /* Copy the argument to general registers or the stack in | |
2730 | register-sized pieces. Large arguments are split between | |
2731 | registers and stack. */ | |
2732 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2733 | are treated specially: Irix cc passes them in registers | |
2734 | where gcc sometimes puts them on the stack. For maximum | |
2735 | compatibility, we will put them in both places. */ | |
c5aa993b | 2736 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2737 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2738 | |
f09ded24 | 2739 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2740 | register are only written to memory. */ |
c906108c SS |
2741 | while (len > 0) |
2742 | { | |
ebafbe83 | 2743 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2744 | int stack_used_p = 0; |
46e0f506 MS |
2745 | int partial_len = |
2746 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2747 | |
acdb74a0 AC |
2748 | if (mips_debug) |
2749 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2750 | partial_len); | |
2751 | ||
566f0f7a | 2752 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2753 | if (argreg > MIPS_LAST_ARG_REGNUM |
2754 | || odd_sized_struct | |
2755 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2756 | { |
c906108c SS |
2757 | /* Should shorter than int integer values be |
2758 | promoted to int before being stored? */ | |
c906108c | 2759 | int longword_offset = 0; |
9ace0497 | 2760 | CORE_ADDR addr; |
566f0f7a | 2761 | stack_used_p = 1; |
d7449b42 | 2762 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2763 | { |
d929b26f | 2764 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2765 | (typecode == TYPE_CODE_INT || |
2766 | typecode == TYPE_CODE_PTR || | |
2767 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2768 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2769 | else if ((typecode == TYPE_CODE_STRUCT || |
2770 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2771 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2772 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2773 | } |
c5aa993b | 2774 | |
9ace0497 AC |
2775 | if (mips_debug) |
2776 | { | |
cb3d25d1 MS |
2777 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2778 | paddr_nz (stack_offset)); | |
2779 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2780 | paddr_nz (longword_offset)); | |
9ace0497 | 2781 | } |
361d1df0 | 2782 | |
9ace0497 AC |
2783 | addr = sp + stack_offset + longword_offset; |
2784 | ||
2785 | if (mips_debug) | |
2786 | { | |
2787 | int i; | |
cb3d25d1 MS |
2788 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2789 | paddr_nz (addr)); | |
9ace0497 AC |
2790 | for (i = 0; i < partial_len; i++) |
2791 | { | |
cb3d25d1 MS |
2792 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2793 | val[i] & 0xff); | |
9ace0497 AC |
2794 | } |
2795 | } | |
2796 | write_memory (addr, val, partial_len); | |
c906108c SS |
2797 | } |
2798 | ||
f09ded24 AC |
2799 | /* Note!!! This is NOT an else clause. Odd sized |
2800 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2801 | arguments will not. */ |
566f0f7a | 2802 | /* Write this portion of the argument to a general |
46e0f506 | 2803 | purpose register. */ |
f09ded24 AC |
2804 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2805 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2806 | { |
9ace0497 | 2807 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2808 | |
9ace0497 | 2809 | if (mips_debug) |
acdb74a0 | 2810 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2811 | argreg, |
2812 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2813 | write_register (argreg, regval); |
2814 | argreg++; | |
c906108c | 2815 | } |
c5aa993b | 2816 | |
c906108c SS |
2817 | len -= partial_len; |
2818 | val += partial_len; | |
2819 | ||
566f0f7a AC |
2820 | /* Compute the the offset into the stack at which we |
2821 | will copy the next parameter. | |
2822 | ||
566f0f7a | 2823 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2824 | only needs to be adjusted when it has been used. */ |
c906108c | 2825 | |
46e0f506 | 2826 | if (stack_used_p) |
d929b26f | 2827 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2828 | } |
2829 | } | |
9ace0497 AC |
2830 | if (mips_debug) |
2831 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2832 | } |
2833 | ||
0f71a2f6 JM |
2834 | /* Return adjusted stack pointer. */ |
2835 | return sp; | |
2836 | } | |
2837 | ||
ebafbe83 MS |
2838 | /* N32/N64 version of push_arguments. */ |
2839 | ||
f7ab6ec6 | 2840 | static CORE_ADDR |
cb3d25d1 MS |
2841 | mips_n32n64_push_arguments (int nargs, |
2842 | struct value **args, | |
2843 | CORE_ADDR sp, | |
2844 | int struct_return, | |
2845 | CORE_ADDR struct_addr) | |
2846 | { | |
2847 | int argreg; | |
2848 | int float_argreg; | |
2849 | int argnum; | |
2850 | int len = 0; | |
2851 | int stack_offset = 0; | |
2852 | ||
2853 | /* First ensure that the stack and structure return address (if any) | |
2854 | are properly aligned. The stack has to be at least 64-bit | |
2855 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2856 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2857 | aligned, so we round to this widest known alignment. */ | |
2858 | ||
2859 | sp = ROUND_DOWN (sp, 16); | |
2860 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
2861 | ||
2862 | /* Now make space on the stack for the args. */ | |
2863 | for (argnum = 0; argnum < nargs; argnum++) | |
2864 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
2865 | MIPS_STACK_ARGSIZE); | |
2866 | sp -= ROUND_UP (len, 16); | |
2867 | ||
2868 | if (mips_debug) | |
2869 | fprintf_unfiltered (gdb_stdlog, | |
2870 | "mips_n32n64_push_arguments: sp=0x%s allocated %d\n", | |
2871 | paddr_nz (sp), ROUND_UP (len, 16)); | |
2872 | ||
2873 | /* Initialize the integer and float register pointers. */ | |
2874 | argreg = A0_REGNUM; | |
2875 | float_argreg = FPA0_REGNUM; | |
2876 | ||
46e0f506 | 2877 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2878 | if (struct_return) |
2879 | { | |
2880 | if (mips_debug) | |
2881 | fprintf_unfiltered (gdb_stdlog, | |
2882 | "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n", | |
2883 | argreg, paddr_nz (struct_addr)); | |
2884 | write_register (argreg++, struct_addr); | |
2885 | } | |
2886 | ||
2887 | /* Now load as many as possible of the first arguments into | |
2888 | registers, and push the rest onto the stack. Loop thru args | |
2889 | from first to last. */ | |
2890 | for (argnum = 0; argnum < nargs; argnum++) | |
2891 | { | |
2892 | char *val; | |
2893 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
2894 | struct value *arg = args[argnum]; | |
2895 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2896 | int len = TYPE_LENGTH (arg_type); | |
2897 | enum type_code typecode = TYPE_CODE (arg_type); | |
2898 | ||
2899 | if (mips_debug) | |
2900 | fprintf_unfiltered (gdb_stdlog, | |
2901 | "mips_n32n64_push_arguments: %d len=%d type=%d", | |
2902 | argnum + 1, len, (int) typecode); | |
2903 | ||
2904 | val = (char *) VALUE_CONTENTS (arg); | |
2905 | ||
2906 | if (fp_register_arg_p (typecode, arg_type) | |
2907 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2908 | { | |
2909 | /* This is a floating point value that fits entirely | |
2910 | in a single register. */ | |
2911 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2912 | above to ensure that it is even register aligned. */ | |
2913 | LONGEST regval = extract_unsigned_integer (val, len); | |
2914 | if (mips_debug) | |
2915 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2916 | float_argreg, phex (regval, len)); | |
2917 | write_register (float_argreg++, regval); | |
2918 | ||
2919 | if (mips_debug) | |
2920 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2921 | argreg, phex (regval, len)); | |
2922 | write_register (argreg, regval); | |
2923 | argreg += 1; | |
2924 | } | |
2925 | else | |
2926 | { | |
2927 | /* Copy the argument to general registers or the stack in | |
2928 | register-sized pieces. Large arguments are split between | |
2929 | registers and stack. */ | |
2930 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2931 | are treated specially: Irix cc passes them in registers | |
2932 | where gcc sometimes puts them on the stack. For maximum | |
2933 | compatibility, we will put them in both places. */ | |
2934 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
2935 | (len % MIPS_SAVED_REGSIZE != 0)); | |
2936 | /* Note: Floating-point values that didn't fit into an FP | |
2937 | register are only written to memory. */ | |
2938 | while (len > 0) | |
2939 | { | |
2940 | /* Rememer if the argument was written to the stack. */ | |
2941 | int stack_used_p = 0; | |
2942 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
2943 | len : MIPS_SAVED_REGSIZE; | |
2944 | ||
2945 | if (mips_debug) | |
2946 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2947 | partial_len); | |
2948 | ||
2949 | /* Write this portion of the argument to the stack. */ | |
2950 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2951 | || odd_sized_struct | |
2952 | || fp_register_arg_p (typecode, arg_type)) | |
2953 | { | |
2954 | /* Should shorter than int integer values be | |
2955 | promoted to int before being stored? */ | |
2956 | int longword_offset = 0; | |
2957 | CORE_ADDR addr; | |
2958 | stack_used_p = 1; | |
2959 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2960 | { | |
2961 | if (MIPS_STACK_ARGSIZE == 8 && | |
2962 | (typecode == TYPE_CODE_INT || | |
2963 | typecode == TYPE_CODE_PTR || | |
2964 | typecode == TYPE_CODE_FLT) && len <= 4) | |
2965 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
2966 | } |
2967 | ||
2968 | if (mips_debug) | |
2969 | { | |
2970 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2971 | paddr_nz (stack_offset)); | |
2972 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2973 | paddr_nz (longword_offset)); | |
2974 | } | |
2975 | ||
2976 | addr = sp + stack_offset + longword_offset; | |
2977 | ||
2978 | if (mips_debug) | |
2979 | { | |
2980 | int i; | |
2981 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
2982 | paddr_nz (addr)); | |
2983 | for (i = 0; i < partial_len; i++) | |
2984 | { | |
2985 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
2986 | val[i] & 0xff); | |
2987 | } | |
2988 | } | |
2989 | write_memory (addr, val, partial_len); | |
2990 | } | |
2991 | ||
2992 | /* Note!!! This is NOT an else clause. Odd sized | |
2993 | structs may go thru BOTH paths. Floating point | |
2994 | arguments will not. */ | |
2995 | /* Write this portion of the argument to a general | |
2996 | purpose register. */ | |
2997 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
2998 | && !fp_register_arg_p (typecode, arg_type)) | |
2999 | { | |
3000 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3001 | ||
3002 | /* A non-floating-point argument being passed in a | |
3003 | general register. If a struct or union, and if | |
3004 | the remaining length is smaller than the register | |
3005 | size, we have to adjust the register value on | |
3006 | big endian targets. | |
3007 | ||
3008 | It does not seem to be necessary to do the | |
3009 | same for integral types. | |
3010 | ||
3011 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3012 | outputting LE O32 with sizeof (struct) < | |
3013 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3014 | part of storing the argument in a register a | |
3015 | register (the left shift isn't generated when | |
3016 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3017 | is quite possible that this is GCC contradicting | |
3018 | the LE/O32 ABI, GDB has not been adjusted to | |
3019 | accommodate this. Either someone needs to | |
3020 | demonstrate that the LE/O32 ABI specifies such a | |
3021 | left shift OR this new ABI gets identified as | |
3022 | such and GDB gets tweaked accordingly. */ | |
3023 | ||
3024 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3025 | && partial_len < MIPS_SAVED_REGSIZE | |
3026 | && (typecode == TYPE_CODE_STRUCT || | |
3027 | typecode == TYPE_CODE_UNION)) | |
3028 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3029 | TARGET_CHAR_BIT); | |
3030 | ||
3031 | if (mips_debug) | |
3032 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3033 | argreg, | |
3034 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3035 | write_register (argreg, regval); | |
3036 | argreg++; | |
3037 | } | |
3038 | ||
3039 | len -= partial_len; | |
3040 | val += partial_len; | |
3041 | ||
3042 | /* Compute the the offset into the stack at which we | |
3043 | will copy the next parameter. | |
3044 | ||
3045 | In N32 (N64?), the stack_offset only needs to be | |
3046 | adjusted when it has been used. */ | |
3047 | ||
3048 | if (stack_used_p) | |
3049 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3050 | } | |
3051 | } | |
3052 | if (mips_debug) | |
3053 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3054 | } | |
3055 | ||
3056 | /* Return adjusted stack pointer. */ | |
3057 | return sp; | |
3058 | } | |
3059 | ||
46cac009 | 3060 | /* O32 version of push_arguments. */ |
ebafbe83 | 3061 | |
46cac009 AC |
3062 | static CORE_ADDR |
3063 | mips_o32_push_arguments (int nargs, | |
3064 | struct value **args, | |
3065 | CORE_ADDR sp, | |
3066 | int struct_return, | |
3067 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3068 | { |
3069 | int argreg; | |
3070 | int float_argreg; | |
3071 | int argnum; | |
3072 | int len = 0; | |
3073 | int stack_offset = 0; | |
ebafbe83 MS |
3074 | |
3075 | /* First ensure that the stack and structure return address (if any) | |
3076 | are properly aligned. The stack has to be at least 64-bit | |
3077 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3078 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3079 | aligned, so we round to this widest known alignment. */ | |
3080 | ||
3081 | sp = ROUND_DOWN (sp, 16); | |
3082 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3083 | ||
3084 | /* Now make space on the stack for the args. */ | |
3085 | for (argnum = 0; argnum < nargs; argnum++) | |
3086 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3087 | MIPS_STACK_ARGSIZE); | |
3088 | sp -= ROUND_UP (len, 16); | |
3089 | ||
3090 | if (mips_debug) | |
3091 | fprintf_unfiltered (gdb_stdlog, | |
46cac009 | 3092 | "mips_o32_push_arguments: sp=0x%s allocated %d\n", |
ebafbe83 MS |
3093 | paddr_nz (sp), ROUND_UP (len, 16)); |
3094 | ||
3095 | /* Initialize the integer and float register pointers. */ | |
3096 | argreg = A0_REGNUM; | |
3097 | float_argreg = FPA0_REGNUM; | |
3098 | ||
bcb0cc15 | 3099 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3100 | if (struct_return) |
3101 | { | |
3102 | if (mips_debug) | |
3103 | fprintf_unfiltered (gdb_stdlog, | |
46cac009 | 3104 | "mips_o32_push_arguments: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3105 | argreg, paddr_nz (struct_addr)); |
3106 | write_register (argreg++, struct_addr); | |
3107 | stack_offset += MIPS_STACK_ARGSIZE; | |
3108 | } | |
3109 | ||
3110 | /* Now load as many as possible of the first arguments into | |
3111 | registers, and push the rest onto the stack. Loop thru args | |
3112 | from first to last. */ | |
3113 | for (argnum = 0; argnum < nargs; argnum++) | |
3114 | { | |
3115 | char *val; | |
3116 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
3117 | struct value *arg = args[argnum]; | |
3118 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3119 | int len = TYPE_LENGTH (arg_type); | |
3120 | enum type_code typecode = TYPE_CODE (arg_type); | |
3121 | ||
3122 | if (mips_debug) | |
3123 | fprintf_unfiltered (gdb_stdlog, | |
46cac009 AC |
3124 | "mips_o32_push_arguments: %d len=%d type=%d", |
3125 | argnum + 1, len, (int) typecode); | |
3126 | ||
3127 | val = (char *) VALUE_CONTENTS (arg); | |
3128 | ||
3129 | /* 32-bit ABIs always start floating point arguments in an | |
3130 | even-numbered floating point register. Round the FP register | |
3131 | up before the check to see if there are any FP registers | |
3132 | left. O32/O64 targets also pass the FP in the integer | |
3133 | registers so also round up normal registers. */ | |
3134 | if (!FP_REGISTER_DOUBLE | |
3135 | && fp_register_arg_p (typecode, arg_type)) | |
3136 | { | |
3137 | if ((float_argreg & 1)) | |
3138 | float_argreg++; | |
3139 | } | |
3140 | ||
3141 | /* Floating point arguments passed in registers have to be | |
3142 | treated specially. On 32-bit architectures, doubles | |
3143 | are passed in register pairs; the even register gets | |
3144 | the low word, and the odd register gets the high word. | |
3145 | On O32/O64, the first two floating point arguments are | |
3146 | also copied to general registers, because MIPS16 functions | |
3147 | don't use float registers for arguments. This duplication of | |
3148 | arguments in general registers can't hurt non-MIPS16 functions | |
3149 | because those registers are normally skipped. */ | |
3150 | ||
3151 | if (fp_register_arg_p (typecode, arg_type) | |
3152 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3153 | { | |
3154 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3155 | { | |
3156 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3157 | unsigned long regval; | |
3158 | ||
3159 | /* Write the low word of the double to the even register(s). */ | |
3160 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3161 | if (mips_debug) | |
3162 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3163 | float_argreg, phex (regval, 4)); | |
3164 | write_register (float_argreg++, regval); | |
3165 | if (mips_debug) | |
3166 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3167 | argreg, phex (regval, 4)); | |
3168 | write_register (argreg++, regval); | |
3169 | ||
3170 | /* Write the high word of the double to the odd register(s). */ | |
3171 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3172 | if (mips_debug) | |
3173 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3174 | float_argreg, phex (regval, 4)); | |
3175 | write_register (float_argreg++, regval); | |
3176 | ||
3177 | if (mips_debug) | |
3178 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3179 | argreg, phex (regval, 4)); | |
3180 | write_register (argreg++, regval); | |
3181 | } | |
3182 | else | |
3183 | { | |
3184 | /* This is a floating point value that fits entirely | |
3185 | in a single register. */ | |
3186 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3187 | above to ensure that it is even register aligned. */ | |
3188 | LONGEST regval = extract_unsigned_integer (val, len); | |
3189 | if (mips_debug) | |
3190 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3191 | float_argreg, phex (regval, len)); | |
3192 | write_register (float_argreg++, regval); | |
3193 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3194 | registers for each argument. The below is (my | |
3195 | guess) to ensure that the corresponding integer | |
3196 | register has reserved the same space. */ | |
3197 | if (mips_debug) | |
3198 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3199 | argreg, phex (regval, len)); | |
3200 | write_register (argreg, regval); | |
3201 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3202 | } | |
3203 | /* Reserve space for the FP register. */ | |
3204 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3205 | } | |
3206 | else | |
3207 | { | |
3208 | /* Copy the argument to general registers or the stack in | |
3209 | register-sized pieces. Large arguments are split between | |
3210 | registers and stack. */ | |
3211 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3212 | are treated specially: Irix cc passes them in registers | |
3213 | where gcc sometimes puts them on the stack. For maximum | |
3214 | compatibility, we will put them in both places. */ | |
3215 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3216 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3217 | /* Structures should be aligned to eight bytes (even arg registers) | |
3218 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3219 | if (MIPS_SAVED_REGSIZE < 8 | |
3220 | && mips_type_needs_double_align (arg_type)) | |
3221 | { | |
3222 | if ((argreg & 1)) | |
3223 | argreg++; | |
3224 | } | |
3225 | /* Note: Floating-point values that didn't fit into an FP | |
3226 | register are only written to memory. */ | |
3227 | while (len > 0) | |
3228 | { | |
3229 | /* Remember if the argument was written to the stack. */ | |
3230 | int stack_used_p = 0; | |
3231 | int partial_len = | |
3232 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3233 | ||
3234 | if (mips_debug) | |
3235 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3236 | partial_len); | |
3237 | ||
3238 | /* Write this portion of the argument to the stack. */ | |
3239 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3240 | || odd_sized_struct | |
3241 | || fp_register_arg_p (typecode, arg_type)) | |
3242 | { | |
3243 | /* Should shorter than int integer values be | |
3244 | promoted to int before being stored? */ | |
3245 | int longword_offset = 0; | |
3246 | CORE_ADDR addr; | |
3247 | stack_used_p = 1; | |
3248 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3249 | { | |
3250 | if (MIPS_STACK_ARGSIZE == 8 && | |
3251 | (typecode == TYPE_CODE_INT || | |
3252 | typecode == TYPE_CODE_PTR || | |
3253 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3254 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3255 | } | |
3256 | ||
3257 | if (mips_debug) | |
3258 | { | |
3259 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3260 | paddr_nz (stack_offset)); | |
3261 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3262 | paddr_nz (longword_offset)); | |
3263 | } | |
3264 | ||
3265 | addr = sp + stack_offset + longword_offset; | |
3266 | ||
3267 | if (mips_debug) | |
3268 | { | |
3269 | int i; | |
3270 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3271 | paddr_nz (addr)); | |
3272 | for (i = 0; i < partial_len; i++) | |
3273 | { | |
3274 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3275 | val[i] & 0xff); | |
3276 | } | |
3277 | } | |
3278 | write_memory (addr, val, partial_len); | |
3279 | } | |
3280 | ||
3281 | /* Note!!! This is NOT an else clause. Odd sized | |
3282 | structs may go thru BOTH paths. Floating point | |
3283 | arguments will not. */ | |
3284 | /* Write this portion of the argument to a general | |
3285 | purpose register. */ | |
3286 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3287 | && !fp_register_arg_p (typecode, arg_type)) | |
3288 | { | |
3289 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3290 | /* Value may need to be sign extended, because | |
3291 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3292 | ||
3293 | /* A non-floating-point argument being passed in a | |
3294 | general register. If a struct or union, and if | |
3295 | the remaining length is smaller than the register | |
3296 | size, we have to adjust the register value on | |
3297 | big endian targets. | |
3298 | ||
3299 | It does not seem to be necessary to do the | |
3300 | same for integral types. | |
3301 | ||
3302 | Also don't do this adjustment on O64 binaries. | |
3303 | ||
3304 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3305 | outputting LE O32 with sizeof (struct) < | |
3306 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3307 | part of storing the argument in a register a | |
3308 | register (the left shift isn't generated when | |
3309 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3310 | is quite possible that this is GCC contradicting | |
3311 | the LE/O32 ABI, GDB has not been adjusted to | |
3312 | accommodate this. Either someone needs to | |
3313 | demonstrate that the LE/O32 ABI specifies such a | |
3314 | left shift OR this new ABI gets identified as | |
3315 | such and GDB gets tweaked accordingly. */ | |
3316 | ||
3317 | if (MIPS_SAVED_REGSIZE < 8 | |
3318 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3319 | && partial_len < MIPS_SAVED_REGSIZE | |
3320 | && (typecode == TYPE_CODE_STRUCT || | |
3321 | typecode == TYPE_CODE_UNION)) | |
3322 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3323 | TARGET_CHAR_BIT); | |
3324 | ||
3325 | if (mips_debug) | |
3326 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3327 | argreg, | |
3328 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3329 | write_register (argreg, regval); | |
3330 | argreg++; | |
3331 | ||
3332 | /* Prevent subsequent floating point arguments from | |
3333 | being passed in floating point registers. */ | |
3334 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3335 | } | |
3336 | ||
3337 | len -= partial_len; | |
3338 | val += partial_len; | |
3339 | ||
3340 | /* Compute the the offset into the stack at which we | |
3341 | will copy the next parameter. | |
3342 | ||
3343 | In older ABIs, the caller reserved space for | |
3344 | registers that contained arguments. This was loosely | |
3345 | refered to as their "home". Consequently, space is | |
3346 | always allocated. */ | |
3347 | ||
3348 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3349 | } | |
3350 | } | |
3351 | if (mips_debug) | |
3352 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3353 | } | |
3354 | ||
3355 | /* Return adjusted stack pointer. */ | |
3356 | return sp; | |
3357 | } | |
3358 | ||
3359 | /* O64 version of push_arguments. */ | |
3360 | ||
3361 | static CORE_ADDR | |
3362 | mips_o64_push_arguments (int nargs, | |
3363 | struct value **args, | |
3364 | CORE_ADDR sp, | |
3365 | int struct_return, | |
3366 | CORE_ADDR struct_addr) | |
3367 | { | |
3368 | int argreg; | |
3369 | int float_argreg; | |
3370 | int argnum; | |
3371 | int len = 0; | |
3372 | int stack_offset = 0; | |
3373 | ||
3374 | /* First ensure that the stack and structure return address (if any) | |
3375 | are properly aligned. The stack has to be at least 64-bit | |
3376 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3377 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3378 | aligned, so we round to this widest known alignment. */ | |
3379 | ||
3380 | sp = ROUND_DOWN (sp, 16); | |
3381 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3382 | ||
3383 | /* Now make space on the stack for the args. */ | |
3384 | for (argnum = 0; argnum < nargs; argnum++) | |
3385 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3386 | MIPS_STACK_ARGSIZE); | |
3387 | sp -= ROUND_UP (len, 16); | |
3388 | ||
3389 | if (mips_debug) | |
3390 | fprintf_unfiltered (gdb_stdlog, | |
3391 | "mips_o64_push_arguments: sp=0x%s allocated %d\n", | |
3392 | paddr_nz (sp), ROUND_UP (len, 16)); | |
3393 | ||
3394 | /* Initialize the integer and float register pointers. */ | |
3395 | argreg = A0_REGNUM; | |
3396 | float_argreg = FPA0_REGNUM; | |
3397 | ||
3398 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3399 | if (struct_return) | |
3400 | { | |
3401 | if (mips_debug) | |
3402 | fprintf_unfiltered (gdb_stdlog, | |
3403 | "mips_o64_push_arguments: struct_return reg=%d 0x%s\n", | |
3404 | argreg, paddr_nz (struct_addr)); | |
3405 | write_register (argreg++, struct_addr); | |
3406 | stack_offset += MIPS_STACK_ARGSIZE; | |
3407 | } | |
3408 | ||
3409 | /* Now load as many as possible of the first arguments into | |
3410 | registers, and push the rest onto the stack. Loop thru args | |
3411 | from first to last. */ | |
3412 | for (argnum = 0; argnum < nargs; argnum++) | |
3413 | { | |
3414 | char *val; | |
3415 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
3416 | struct value *arg = args[argnum]; | |
3417 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3418 | int len = TYPE_LENGTH (arg_type); | |
3419 | enum type_code typecode = TYPE_CODE (arg_type); | |
3420 | ||
3421 | if (mips_debug) | |
3422 | fprintf_unfiltered (gdb_stdlog, | |
3423 | "mips_o64_push_arguments: %d len=%d type=%d", | |
ebafbe83 MS |
3424 | argnum + 1, len, (int) typecode); |
3425 | ||
3426 | val = (char *) VALUE_CONTENTS (arg); | |
3427 | ||
3428 | /* 32-bit ABIs always start floating point arguments in an | |
3429 | even-numbered floating point register. Round the FP register | |
3430 | up before the check to see if there are any FP registers | |
3431 | left. O32/O64 targets also pass the FP in the integer | |
3432 | registers so also round up normal registers. */ | |
3433 | if (!FP_REGISTER_DOUBLE | |
3434 | && fp_register_arg_p (typecode, arg_type)) | |
3435 | { | |
3436 | if ((float_argreg & 1)) | |
3437 | float_argreg++; | |
3438 | } | |
3439 | ||
3440 | /* Floating point arguments passed in registers have to be | |
3441 | treated specially. On 32-bit architectures, doubles | |
3442 | are passed in register pairs; the even register gets | |
3443 | the low word, and the odd register gets the high word. | |
3444 | On O32/O64, the first two floating point arguments are | |
3445 | also copied to general registers, because MIPS16 functions | |
3446 | don't use float registers for arguments. This duplication of | |
3447 | arguments in general registers can't hurt non-MIPS16 functions | |
3448 | because those registers are normally skipped. */ | |
3449 | ||
3450 | if (fp_register_arg_p (typecode, arg_type) | |
3451 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3452 | { | |
3453 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3454 | { | |
3455 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3456 | unsigned long regval; | |
3457 | ||
3458 | /* Write the low word of the double to the even register(s). */ | |
3459 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3460 | if (mips_debug) | |
3461 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3462 | float_argreg, phex (regval, 4)); | |
3463 | write_register (float_argreg++, regval); | |
3464 | if (mips_debug) | |
3465 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3466 | argreg, phex (regval, 4)); | |
3467 | write_register (argreg++, regval); | |
3468 | ||
3469 | /* Write the high word of the double to the odd register(s). */ | |
3470 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3471 | if (mips_debug) | |
3472 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3473 | float_argreg, phex (regval, 4)); | |
3474 | write_register (float_argreg++, regval); | |
3475 | ||
3476 | if (mips_debug) | |
3477 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3478 | argreg, phex (regval, 4)); | |
3479 | write_register (argreg++, regval); | |
3480 | } | |
3481 | else | |
3482 | { | |
3483 | /* This is a floating point value that fits entirely | |
3484 | in a single register. */ | |
3485 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3486 | above to ensure that it is even register aligned. */ | |
3487 | LONGEST regval = extract_unsigned_integer (val, len); | |
3488 | if (mips_debug) | |
3489 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3490 | float_argreg, phex (regval, len)); | |
3491 | write_register (float_argreg++, regval); | |
3492 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3493 | registers for each argument. The below is (my | |
3494 | guess) to ensure that the corresponding integer | |
3495 | register has reserved the same space. */ | |
3496 | if (mips_debug) | |
3497 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3498 | argreg, phex (regval, len)); | |
3499 | write_register (argreg, regval); | |
3500 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3501 | } | |
3502 | /* Reserve space for the FP register. */ | |
3503 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3504 | } | |
3505 | else | |
3506 | { | |
3507 | /* Copy the argument to general registers or the stack in | |
3508 | register-sized pieces. Large arguments are split between | |
3509 | registers and stack. */ | |
3510 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3511 | are treated specially: Irix cc passes them in registers | |
3512 | where gcc sometimes puts them on the stack. For maximum | |
3513 | compatibility, we will put them in both places. */ | |
3514 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3515 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3516 | /* Structures should be aligned to eight bytes (even arg registers) | |
3517 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3518 | if (MIPS_SAVED_REGSIZE < 8 | |
3519 | && mips_type_needs_double_align (arg_type)) | |
3520 | { | |
3521 | if ((argreg & 1)) | |
3522 | argreg++; | |
3523 | } | |
3524 | /* Note: Floating-point values that didn't fit into an FP | |
3525 | register are only written to memory. */ | |
3526 | while (len > 0) | |
3527 | { | |
3528 | /* Remember if the argument was written to the stack. */ | |
3529 | int stack_used_p = 0; | |
3530 | int partial_len = | |
3531 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3532 | ||
3533 | if (mips_debug) | |
3534 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3535 | partial_len); | |
3536 | ||
3537 | /* Write this portion of the argument to the stack. */ | |
3538 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3539 | || odd_sized_struct | |
3540 | || fp_register_arg_p (typecode, arg_type)) | |
3541 | { | |
3542 | /* Should shorter than int integer values be | |
3543 | promoted to int before being stored? */ | |
3544 | int longword_offset = 0; | |
3545 | CORE_ADDR addr; | |
3546 | stack_used_p = 1; | |
3547 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3548 | { | |
3549 | if (MIPS_STACK_ARGSIZE == 8 && | |
3550 | (typecode == TYPE_CODE_INT || | |
3551 | typecode == TYPE_CODE_PTR || | |
3552 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3553 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3554 | } | |
3555 | ||
3556 | if (mips_debug) | |
3557 | { | |
3558 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3559 | paddr_nz (stack_offset)); | |
3560 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3561 | paddr_nz (longword_offset)); | |
3562 | } | |
3563 | ||
3564 | addr = sp + stack_offset + longword_offset; | |
3565 | ||
3566 | if (mips_debug) | |
3567 | { | |
3568 | int i; | |
3569 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3570 | paddr_nz (addr)); | |
3571 | for (i = 0; i < partial_len; i++) | |
3572 | { | |
3573 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3574 | val[i] & 0xff); | |
3575 | } | |
3576 | } | |
3577 | write_memory (addr, val, partial_len); | |
3578 | } | |
3579 | ||
3580 | /* Note!!! This is NOT an else clause. Odd sized | |
3581 | structs may go thru BOTH paths. Floating point | |
3582 | arguments will not. */ | |
3583 | /* Write this portion of the argument to a general | |
3584 | purpose register. */ | |
3585 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3586 | && !fp_register_arg_p (typecode, arg_type)) | |
3587 | { | |
3588 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3589 | /* Value may need to be sign extended, because | |
3590 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3591 | ||
3592 | /* A non-floating-point argument being passed in a | |
3593 | general register. If a struct or union, and if | |
3594 | the remaining length is smaller than the register | |
3595 | size, we have to adjust the register value on | |
3596 | big endian targets. | |
3597 | ||
3598 | It does not seem to be necessary to do the | |
3599 | same for integral types. | |
3600 | ||
3601 | Also don't do this adjustment on O64 binaries. | |
3602 | ||
3603 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3604 | outputting LE O32 with sizeof (struct) < | |
3605 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3606 | part of storing the argument in a register a | |
3607 | register (the left shift isn't generated when | |
3608 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3609 | is quite possible that this is GCC contradicting | |
3610 | the LE/O32 ABI, GDB has not been adjusted to | |
3611 | accommodate this. Either someone needs to | |
3612 | demonstrate that the LE/O32 ABI specifies such a | |
3613 | left shift OR this new ABI gets identified as | |
3614 | such and GDB gets tweaked accordingly. */ | |
3615 | ||
3616 | if (MIPS_SAVED_REGSIZE < 8 | |
3617 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3618 | && partial_len < MIPS_SAVED_REGSIZE | |
3619 | && (typecode == TYPE_CODE_STRUCT || | |
3620 | typecode == TYPE_CODE_UNION)) | |
3621 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3622 | TARGET_CHAR_BIT); | |
3623 | ||
3624 | if (mips_debug) | |
3625 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3626 | argreg, | |
3627 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3628 | write_register (argreg, regval); | |
3629 | argreg++; | |
3630 | ||
3631 | /* Prevent subsequent floating point arguments from | |
3632 | being passed in floating point registers. */ | |
3633 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3634 | } | |
3635 | ||
3636 | len -= partial_len; | |
3637 | val += partial_len; | |
3638 | ||
3639 | /* Compute the the offset into the stack at which we | |
3640 | will copy the next parameter. | |
3641 | ||
3642 | In older ABIs, the caller reserved space for | |
3643 | registers that contained arguments. This was loosely | |
3644 | refered to as their "home". Consequently, space is | |
3645 | always allocated. */ | |
3646 | ||
3647 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3648 | } | |
3649 | } | |
3650 | if (mips_debug) | |
3651 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3652 | } | |
3653 | ||
3654 | /* Return adjusted stack pointer. */ | |
3655 | return sp; | |
3656 | } | |
3657 | ||
f7ab6ec6 | 3658 | static CORE_ADDR |
acdb74a0 | 3659 | mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
0f71a2f6 | 3660 | { |
c906108c SS |
3661 | /* Set the return address register to point to the entry |
3662 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 3663 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
3664 | return sp; |
3665 | } | |
3666 | ||
3667 | static void | |
c5aa993b | 3668 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c | 3669 | { |
cb3d25d1 | 3670 | char *buffer = alloca (MAX_REGISTER_RAW_SIZE); |
7a292a7a SS |
3671 | int regsize; |
3672 | int offset; | |
3673 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
3674 | { | |
3675 | regsize = MIPS_SAVED_REGSIZE; | |
d7449b42 | 3676 | offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3677 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE |
3678 | : 0); | |
3679 | } | |
3680 | else | |
3681 | { | |
3682 | regsize = REGISTER_RAW_SIZE (regno); | |
3683 | offset = 0; | |
3684 | } | |
c906108c SS |
3685 | *sp -= regsize; |
3686 | read_register_gen (regno, buffer); | |
7a292a7a | 3687 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
3688 | } |
3689 | ||
3690 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
3691 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
3692 | ||
f7ab6ec6 | 3693 | static void |
acdb74a0 | 3694 | mips_push_dummy_frame (void) |
c906108c SS |
3695 | { |
3696 | int ireg; | |
c5aa993b JM |
3697 | struct linked_proc_info *link = (struct linked_proc_info *) |
3698 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c | 3699 | mips_extra_func_info_t proc_desc = &link->info; |
6c997a34 | 3700 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); |
c906108c SS |
3701 | CORE_ADDR old_sp = sp; |
3702 | link->next = linked_proc_desc_table; | |
3703 | linked_proc_desc_table = link; | |
3704 | ||
3705 | /* FIXME! are these correct ? */ | |
c5aa993b | 3706 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
3707 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
3708 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
3709 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
3710 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
3711 | /* | |
3712 | * The registers we must save are all those not preserved across | |
3713 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
3714 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
3715 | * and FP Control/Status registers. | |
361d1df0 | 3716 | * |
c906108c SS |
3717 | * |
3718 | * Dummy frame layout: | |
3719 | * (high memory) | |
c5aa993b JM |
3720 | * Saved PC |
3721 | * Saved MMHI, MMLO, FPC_CSR | |
3722 | * Saved R31 | |
3723 | * Saved R28 | |
3724 | * ... | |
3725 | * Saved R1 | |
c906108c SS |
3726 | * Saved D18 (i.e. F19, F18) |
3727 | * ... | |
3728 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 3729 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
3730 | * (low memory) |
3731 | */ | |
3732 | ||
3733 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
3734 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
3735 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
3736 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
3737 | mips_push_register (&sp, PC_REGNUM); |
3738 | mips_push_register (&sp, HI_REGNUM); | |
3739 | mips_push_register (&sp, LO_REGNUM); | |
3740 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
3741 | ||
3742 | /* Save general CPU registers */ | |
c5aa993b | 3743 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 3744 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
3745 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
3746 | for (ireg = 32; --ireg >= 0;) | |
3747 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
3748 | mips_push_register (&sp, ireg); |
3749 | ||
3750 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 3751 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
3752 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
3753 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
3754 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
3755 | from FP. */ | |
c5aa993b JM |
3756 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
3757 | for (ireg = 32; --ireg >= 0;) | |
3758 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
3759 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3760 | ||
3761 | /* Update the frame pointer for the call dummy and the stack pointer. | |
3762 | Set the procedure's starting and ending addresses to point to the | |
3763 | call dummy address at the entry point. */ | |
3764 | write_register (PUSH_FP_REGNUM, old_sp); | |
3765 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
3766 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
3767 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
3768 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
3769 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
3770 | } |
3771 | ||
f7ab6ec6 | 3772 | static void |
acdb74a0 | 3773 | mips_pop_frame (void) |
c906108c SS |
3774 | { |
3775 | register int regnum; | |
3776 | struct frame_info *frame = get_current_frame (); | |
3777 | CORE_ADDR new_sp = FRAME_FP (frame); | |
3778 | ||
cce74817 | 3779 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 3780 | |
c5aa993b | 3781 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c | 3782 | if (frame->saved_regs == NULL) |
ffabd70d | 3783 | FRAME_INIT_SAVED_REGS (frame); |
c906108c | 3784 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 MS |
3785 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
3786 | && frame->saved_regs[regnum]) | |
3787 | { | |
3788 | /* Floating point registers must not be sign extended, | |
3789 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3790 | ||
3791 | if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32) | |
3792 | write_register (regnum, | |
3793 | read_memory_unsigned_integer (frame->saved_regs[regnum], | |
3794 | MIPS_SAVED_REGSIZE)); | |
3795 | else | |
3796 | write_register (regnum, | |
3797 | read_memory_integer (frame->saved_regs[regnum], | |
3798 | MIPS_SAVED_REGSIZE)); | |
3799 | } | |
757a7cc6 | 3800 | |
c906108c SS |
3801 | write_register (SP_REGNUM, new_sp); |
3802 | flush_cached_frames (); | |
3803 | ||
c5aa993b | 3804 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3805 | { |
3806 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3807 | ||
3808 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3809 | pi_ptr != NULL; | |
3810 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3811 | { | |
3812 | if (&pi_ptr->info == proc_desc) | |
3813 | break; | |
3814 | } | |
3815 | ||
3816 | if (pi_ptr == NULL) | |
3817 | error ("Can't locate dummy extra frame info\n"); | |
3818 | ||
3819 | if (prev_ptr != NULL) | |
3820 | prev_ptr->next = pi_ptr->next; | |
3821 | else | |
3822 | linked_proc_desc_table = pi_ptr->next; | |
3823 | ||
b8c9b27d | 3824 | xfree (pi_ptr); |
c906108c SS |
3825 | |
3826 | write_register (HI_REGNUM, | |
c5aa993b | 3827 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3828 | MIPS_SAVED_REGSIZE)); |
c906108c | 3829 | write_register (LO_REGNUM, |
c5aa993b | 3830 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3831 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3832 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
3833 | write_register (FCRCS_REGNUM, | |
c5aa993b | 3834 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3835 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3836 | } |
3837 | } | |
3838 | ||
f7ab6ec6 MS |
3839 | static void |
3840 | mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, | |
3841 | struct value **args, struct type *type, int gcc_p) | |
3842 | { | |
3843 | write_register(T9_REGNUM, fun); | |
3844 | } | |
3845 | ||
dd824b04 DJ |
3846 | /* Floating point register management. |
3847 | ||
3848 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3849 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3850 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3851 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3852 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3853 | double precision floats into two 32-bit chunks and store them in | |
3854 | consecutive fp regs. To display 64-bit floats stored in this | |
3855 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3856 | Throw in user-configurable endianness and you have a real mess. | |
3857 | ||
3858 | The way this works is: | |
3859 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3860 | double-precision value will be split across two logical registers. | |
3861 | The lower-numbered logical register will hold the low-order bits, | |
3862 | regardless of the processor's endianness. | |
3863 | - If we are on a 64-bit processor, and we are looking for a | |
3864 | single-precision value, it will be in the low ordered bits | |
3865 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3866 | save slot in memory. | |
3867 | - If we are in 64-bit mode, everything is straightforward. | |
3868 | ||
3869 | Note that this code only deals with "live" registers at the top of the | |
3870 | stack. We will attempt to deal with saved registers later, when | |
3871 | the raw/cooked register interface is in place. (We need a general | |
3872 | interface that can deal with dynamic saved register sizes -- fp | |
3873 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3874 | and below). */ | |
3875 | ||
67b2c998 DJ |
3876 | static struct type * |
3877 | mips_float_register_type (void) | |
3878 | { | |
361d1df0 | 3879 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3880 | return builtin_type_ieee_single_big; |
3881 | else | |
3882 | return builtin_type_ieee_single_little; | |
3883 | } | |
3884 | ||
3885 | static struct type * | |
3886 | mips_double_register_type (void) | |
3887 | { | |
361d1df0 | 3888 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3889 | return builtin_type_ieee_double_big; |
3890 | else | |
3891 | return builtin_type_ieee_double_little; | |
3892 | } | |
3893 | ||
dd824b04 DJ |
3894 | /* Copy a 32-bit single-precision value from the current frame |
3895 | into rare_buffer. */ | |
3896 | ||
3897 | static void | |
3898 | mips_read_fp_register_single (int regno, char *rare_buffer) | |
3899 | { | |
3900 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3901 | char *raw_buffer = alloca (raw_size); | |
3902 | ||
cda5a58a | 3903 | if (!frame_register_read (selected_frame, regno, raw_buffer)) |
dd824b04 DJ |
3904 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3905 | if (raw_size == 8) | |
3906 | { | |
3907 | /* We have a 64-bit value for this register. Find the low-order | |
3908 | 32 bits. */ | |
3909 | int offset; | |
3910 | ||
3911 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3912 | offset = 4; | |
3913 | else | |
3914 | offset = 0; | |
3915 | ||
3916 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3917 | } | |
3918 | else | |
3919 | { | |
3920 | memcpy (rare_buffer, raw_buffer, 4); | |
3921 | } | |
3922 | } | |
3923 | ||
3924 | /* Copy a 64-bit double-precision value from the current frame into | |
3925 | rare_buffer. This may include getting half of it from the next | |
3926 | register. */ | |
3927 | ||
3928 | static void | |
3929 | mips_read_fp_register_double (int regno, char *rare_buffer) | |
3930 | { | |
3931 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3932 | ||
3933 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3934 | { | |
3935 | /* We have a 64-bit value for this register, and we should use | |
3936 | all 64 bits. */ | |
cda5a58a | 3937 | if (!frame_register_read (selected_frame, regno, rare_buffer)) |
dd824b04 DJ |
3938 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3939 | } | |
3940 | else | |
3941 | { | |
3942 | if ((regno - FP0_REGNUM) & 1) | |
3943 | internal_error (__FILE__, __LINE__, | |
3944 | "mips_read_fp_register_double: bad access to " | |
3945 | "odd-numbered FP register"); | |
3946 | ||
3947 | /* mips_read_fp_register_single will find the correct 32 bits from | |
3948 | each register. */ | |
3949 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3950 | { | |
3951 | mips_read_fp_register_single (regno, rare_buffer + 4); | |
3952 | mips_read_fp_register_single (regno + 1, rare_buffer); | |
3953 | } | |
361d1df0 | 3954 | else |
dd824b04 DJ |
3955 | { |
3956 | mips_read_fp_register_single (regno, rare_buffer); | |
3957 | mips_read_fp_register_single (regno + 1, rare_buffer + 4); | |
3958 | } | |
3959 | } | |
3960 | } | |
3961 | ||
c906108c | 3962 | static void |
acdb74a0 | 3963 | mips_print_register (int regnum, int all) |
c906108c | 3964 | { |
119d55d8 | 3965 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
c906108c SS |
3966 | |
3967 | /* Get the data in raw format. */ | |
cda5a58a | 3968 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
3969 | { |
3970 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
3971 | return; | |
3972 | } | |
3973 | ||
dd824b04 DJ |
3974 | /* If we have a actual 32-bit floating point register (or we are in |
3975 | 32-bit compatibility mode), and the register is even-numbered, | |
3976 | also print it as a double (spanning two registers). */ | |
c906108c | 3977 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
dd824b04 DJ |
3978 | && (REGISTER_RAW_SIZE (regnum) == 4 |
3979 | || mips2_fp_compat ()) | |
c5aa993b | 3980 | && !((regnum - FP0_REGNUM) & 1)) |
dd824b04 | 3981 | { |
cb3d25d1 | 3982 | char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE); |
c906108c | 3983 | |
dd824b04 | 3984 | mips_read_fp_register_double (regnum, dbuffer); |
c906108c | 3985 | |
dd824b04 | 3986 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
67b2c998 | 3987 | val_print (mips_double_register_type (), dbuffer, 0, 0, |
dd824b04 DJ |
3988 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3989 | printf_filtered ("); "); | |
3990 | } | |
c906108c SS |
3991 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); |
3992 | ||
3993 | /* The problem with printing numeric register names (r26, etc.) is that | |
3994 | the user can't use them on input. Probably the best solution is to | |
3995 | fix it so that either the numeric or the funky (a2, etc.) names | |
3996 | are accepted on input. */ | |
3997 | if (regnum < MIPS_NUMREGS) | |
3998 | printf_filtered ("(r%d): ", regnum); | |
3999 | else | |
4000 | printf_filtered (": "); | |
4001 | ||
4002 | /* If virtual format is floating, print it that way. */ | |
4003 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
dd824b04 DJ |
4004 | if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ()) |
4005 | { | |
4006 | /* We have a meaningful 64-bit value in this register. Show | |
4007 | it as a 32-bit float and a 64-bit double. */ | |
d7449b42 | 4008 | int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG); |
c906108c SS |
4009 | |
4010 | printf_filtered (" (float) "); | |
67b2c998 | 4011 | val_print (mips_float_register_type (), raw_buffer + offset, 0, 0, |
c906108c SS |
4012 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
4013 | printf_filtered (", (double) "); | |
67b2c998 | 4014 | val_print (mips_double_register_type (), raw_buffer, 0, 0, |
c906108c SS |
4015 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
4016 | } | |
4017 | else | |
4018 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
4019 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
4020 | /* Else print as integer in hex. */ | |
4021 | else | |
ed9a39eb JM |
4022 | { |
4023 | int offset; | |
4024 | ||
d7449b42 | 4025 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
ed9a39eb JM |
4026 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
4027 | else | |
4028 | offset = 0; | |
361d1df0 | 4029 | |
ed9a39eb JM |
4030 | print_scalar_formatted (raw_buffer + offset, |
4031 | REGISTER_VIRTUAL_TYPE (regnum), | |
4032 | 'x', 0, gdb_stdout); | |
4033 | } | |
c906108c SS |
4034 | } |
4035 | ||
361d1df0 | 4036 | /* Replacement for generic do_registers_info. |
c906108c SS |
4037 | Print regs in pretty columns. */ |
4038 | ||
4039 | static int | |
acdb74a0 | 4040 | do_fp_register_row (int regnum) |
c5aa993b | 4041 | { /* do values for FP (float) regs */ |
dd824b04 | 4042 | char *raw_buffer; |
c906108c SS |
4043 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
4044 | int inv1, inv2, inv3; | |
c5aa993b | 4045 | |
dd824b04 | 4046 | raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 4047 | |
dd824b04 | 4048 | if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4049 | { |
dd824b04 DJ |
4050 | /* 4-byte registers: we can fit two registers per row. */ |
4051 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
4052 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 4053 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4054 | |
dd824b04 | 4055 | mips_read_fp_register_single (regnum + 1, raw_buffer); |
67b2c998 | 4056 | flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2); |
dd824b04 DJ |
4057 | |
4058 | mips_read_fp_register_double (regnum, raw_buffer); | |
67b2c998 | 4059 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 4060 | |
1adad886 AC |
4061 | printf_filtered (" %-5s", REGISTER_NAME (regnum)); |
4062 | if (inv1) | |
4063 | printf_filtered (": <invalid float>"); | |
4064 | else | |
4065 | printf_filtered ("%-17.9g", flt1); | |
4066 | ||
4067 | printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); | |
4068 | if (inv2) | |
4069 | printf_filtered (": <invalid float>"); | |
4070 | else | |
4071 | printf_filtered ("%-17.9g", flt2); | |
4072 | ||
4073 | printf_filtered (" dbl: "); | |
4074 | if (inv3) | |
4075 | printf_filtered ("<invalid double>"); | |
4076 | else | |
4077 | printf_filtered ("%-24.17g", doub); | |
4078 | printf_filtered ("\n"); | |
4079 | ||
c906108c | 4080 | /* may want to do hex display here (future enhancement) */ |
c5aa993b | 4081 | regnum += 2; |
c906108c SS |
4082 | } |
4083 | else | |
dd824b04 DJ |
4084 | { |
4085 | /* Eight byte registers: print each one as float AND as double. */ | |
4086 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 4087 | flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1); |
c906108c | 4088 | |
dd824b04 | 4089 | mips_read_fp_register_double (regnum, raw_buffer); |
67b2c998 | 4090 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 4091 | |
1adad886 AC |
4092 | printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); |
4093 | if (inv1) | |
4094 | printf_filtered ("<invalid float>"); | |
4095 | else | |
4096 | printf_filtered ("flt: %-17.9g", flt1); | |
4097 | ||
4098 | printf_filtered (" dbl: "); | |
4099 | if (inv3) | |
4100 | printf_filtered ("<invalid double>"); | |
4101 | else | |
4102 | printf_filtered ("%-24.17g", doub); | |
4103 | ||
4104 | printf_filtered ("\n"); | |
c906108c SS |
4105 | /* may want to do hex display here (future enhancement) */ |
4106 | regnum++; | |
4107 | } | |
4108 | return regnum; | |
4109 | } | |
4110 | ||
4111 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
4112 | ||
4113 | static int | |
acdb74a0 | 4114 | do_gp_register_row (int regnum) |
c906108c SS |
4115 | { |
4116 | /* do values for GP (int) regs */ | |
cb3d25d1 | 4117 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
c906108c SS |
4118 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
4119 | int col, byte; | |
4120 | int start_regnum = regnum; | |
4121 | int numregs = NUM_REGS; | |
4122 | ||
4123 | ||
4124 | /* For GP registers, we print a separate row of names above the vals */ | |
4125 | printf_filtered (" "); | |
4126 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
4127 | { | |
4128 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4129 | continue; /* unused register */ |
c906108c | 4130 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
4131 | break; /* end the row: reached FP register */ |
4132 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
4133 | REGISTER_NAME (regnum)); |
4134 | col++; | |
4135 | } | |
c5aa993b | 4136 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
4137 | start_regnum); /* print the R0 to R31 names */ |
4138 | ||
4139 | regnum = start_regnum; /* go back to start of row */ | |
4140 | /* now print the values in hex, 4 or 8 to the row */ | |
4141 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
4142 | { | |
4143 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4144 | continue; /* unused register */ |
c906108c | 4145 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4146 | break; /* end row: reached FP register */ |
c906108c | 4147 | /* OK: get the data in raw format. */ |
cda5a58a | 4148 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
4149 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4150 | /* pad small registers */ | |
43e526b9 | 4151 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
4152 | printf_filtered (" "); |
4153 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4154 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
4155 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
4156 | byte < REGISTER_RAW_SIZE (regnum); | |
4157 | byte++) | |
c906108c SS |
4158 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
4159 | else | |
43e526b9 JM |
4160 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
4161 | byte >= 0; | |
4162 | byte--) | |
c906108c SS |
4163 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
4164 | printf_filtered (" "); | |
4165 | col++; | |
4166 | } | |
c5aa993b | 4167 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
4168 | printf_filtered ("\n"); |
4169 | ||
4170 | return regnum; | |
4171 | } | |
4172 | ||
4173 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4174 | ||
bf1f5b4c | 4175 | static void |
acdb74a0 | 4176 | mips_do_registers_info (int regnum, int fpregs) |
c906108c | 4177 | { |
c5aa993b | 4178 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
4179 | { |
4180 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4181 | error ("Not a valid register for the current processor type"); | |
4182 | ||
4183 | mips_print_register (regnum, 0); | |
4184 | printf_filtered ("\n"); | |
4185 | } | |
c5aa993b JM |
4186 | else |
4187 | /* do all (or most) registers */ | |
c906108c SS |
4188 | { |
4189 | regnum = 0; | |
4190 | while (regnum < NUM_REGS) | |
4191 | { | |
c5aa993b JM |
4192 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
4193 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
4194 | regnum = do_fp_register_row (regnum); /* FP regs */ |
4195 | else | |
4196 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4197 | else | |
4198 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
4199 | } | |
4200 | } | |
4201 | } | |
4202 | ||
c906108c SS |
4203 | /* Is this a branch with a delay slot? */ |
4204 | ||
a14ed312 | 4205 | static int is_delayed (unsigned long); |
c906108c SS |
4206 | |
4207 | static int | |
acdb74a0 | 4208 | is_delayed (unsigned long insn) |
c906108c SS |
4209 | { |
4210 | int i; | |
4211 | for (i = 0; i < NUMOPCODES; ++i) | |
4212 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4213 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4214 | break; | |
4215 | return (i < NUMOPCODES | |
4216 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4217 | | INSN_COND_BRANCH_DELAY | |
4218 | | INSN_COND_BRANCH_LIKELY))); | |
4219 | } | |
4220 | ||
4221 | int | |
acdb74a0 | 4222 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4223 | { |
4224 | char buf[MIPS_INSTLEN]; | |
4225 | ||
4226 | /* There is no branch delay slot on MIPS16. */ | |
4227 | if (pc_is_mips16 (pc)) | |
4228 | return 0; | |
4229 | ||
4230 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4231 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4232 | return 0; | |
c5aa993b | 4233 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4234 | } |
4235 | ||
4236 | ||
4237 | /* Skip the PC past function prologue instructions (32-bit version). | |
4238 | This is a helper function for mips_skip_prologue. */ | |
4239 | ||
4240 | static CORE_ADDR | |
f7b9e9fc | 4241 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4242 | { |
c5aa993b JM |
4243 | t_inst inst; |
4244 | CORE_ADDR end_pc; | |
4245 | int seen_sp_adjust = 0; | |
4246 | int load_immediate_bytes = 0; | |
4247 | ||
4248 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4249 | instruction and the instructions that save registers on the stack | |
4250 | or in the gcc frame. */ | |
4251 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
4252 | { | |
4253 | unsigned long high_word; | |
c906108c | 4254 | |
c5aa993b JM |
4255 | inst = mips_fetch_instruction (pc); |
4256 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4257 | |
c5aa993b JM |
4258 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4259 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4260 | seen_sp_adjust = 1; | |
4261 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4262 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4263 | seen_sp_adjust = 1; | |
4264 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4265 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4266 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4267 | continue; | |
4268 | ||
4269 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4270 | continue; | |
4271 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4272 | /* sx reg,n($s8) */ | |
4273 | continue; /* reg != $zero */ | |
4274 | ||
4275 | /* move $s8,$sp. With different versions of gas this will be either | |
4276 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4277 | Accept any one of these. */ | |
4278 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4279 | continue; | |
4280 | ||
4281 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4282 | continue; | |
4283 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4284 | continue; | |
4285 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4286 | continue; | |
4287 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4288 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4289 | continue; | |
4290 | /* The following instructions load $at or $t0 with an immediate | |
4291 | value in preparation for a stack adjustment via | |
4292 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4293 | a local variable, so we accept them only before a stack adjustment | |
4294 | instruction was seen. */ | |
4295 | else if (!seen_sp_adjust) | |
4296 | { | |
4297 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4298 | high_word == 0x3c08) /* lui $t0,n */ | |
4299 | { | |
4300 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4301 | continue; | |
4302 | } | |
4303 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4304 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4305 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4306 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4307 | { | |
4308 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4309 | continue; | |
4310 | } | |
4311 | else | |
4312 | break; | |
4313 | } | |
4314 | else | |
4315 | break; | |
c906108c SS |
4316 | } |
4317 | ||
c5aa993b JM |
4318 | /* In a frameless function, we might have incorrectly |
4319 | skipped some load immediate instructions. Undo the skipping | |
4320 | if the load immediate was not followed by a stack adjustment. */ | |
4321 | if (load_immediate_bytes && !seen_sp_adjust) | |
4322 | pc -= load_immediate_bytes; | |
4323 | return pc; | |
c906108c SS |
4324 | } |
4325 | ||
4326 | /* Skip the PC past function prologue instructions (16-bit version). | |
4327 | This is a helper function for mips_skip_prologue. */ | |
4328 | ||
4329 | static CORE_ADDR | |
f7b9e9fc | 4330 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4331 | { |
c5aa993b JM |
4332 | CORE_ADDR end_pc; |
4333 | int extend_bytes = 0; | |
4334 | int prev_extend_bytes; | |
c906108c | 4335 | |
c5aa993b JM |
4336 | /* Table of instructions likely to be found in a function prologue. */ |
4337 | static struct | |
c906108c SS |
4338 | { |
4339 | unsigned short inst; | |
4340 | unsigned short mask; | |
c5aa993b JM |
4341 | } |
4342 | table[] = | |
4343 | { | |
c906108c | 4344 | { |
c5aa993b JM |
4345 | 0x6300, 0xff00 |
4346 | } | |
4347 | , /* addiu $sp,offset */ | |
4348 | { | |
4349 | 0xfb00, 0xff00 | |
4350 | } | |
4351 | , /* daddiu $sp,offset */ | |
4352 | { | |
4353 | 0xd000, 0xf800 | |
4354 | } | |
4355 | , /* sw reg,n($sp) */ | |
4356 | { | |
4357 | 0xf900, 0xff00 | |
4358 | } | |
4359 | , /* sd reg,n($sp) */ | |
4360 | { | |
4361 | 0x6200, 0xff00 | |
4362 | } | |
4363 | , /* sw $ra,n($sp) */ | |
4364 | { | |
4365 | 0xfa00, 0xff00 | |
4366 | } | |
4367 | , /* sd $ra,n($sp) */ | |
4368 | { | |
4369 | 0x673d, 0xffff | |
4370 | } | |
4371 | , /* move $s1,sp */ | |
4372 | { | |
4373 | 0xd980, 0xff80 | |
4374 | } | |
4375 | , /* sw $a0-$a3,n($s1) */ | |
4376 | { | |
4377 | 0x6704, 0xff1c | |
4378 | } | |
4379 | , /* move reg,$a0-$a3 */ | |
4380 | { | |
4381 | 0xe809, 0xf81f | |
4382 | } | |
4383 | , /* entry pseudo-op */ | |
4384 | { | |
4385 | 0x0100, 0xff00 | |
4386 | } | |
4387 | , /* addiu $s1,$sp,n */ | |
4388 | { | |
4389 | 0, 0 | |
4390 | } /* end of table marker */ | |
4391 | }; | |
4392 | ||
4393 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4394 | instruction and the instructions that save registers on the stack | |
4395 | or in the gcc frame. */ | |
4396 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
4397 | { | |
4398 | unsigned short inst; | |
4399 | int i; | |
c906108c | 4400 | |
c5aa993b | 4401 | inst = mips_fetch_instruction (pc); |
c906108c | 4402 | |
c5aa993b JM |
4403 | /* Normally we ignore an extend instruction. However, if it is |
4404 | not followed by a valid prologue instruction, we must adjust | |
4405 | the pc back over the extend so that it won't be considered | |
4406 | part of the prologue. */ | |
4407 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4408 | { | |
4409 | extend_bytes = MIPS16_INSTLEN; | |
4410 | continue; | |
4411 | } | |
4412 | prev_extend_bytes = extend_bytes; | |
4413 | extend_bytes = 0; | |
c906108c | 4414 | |
c5aa993b JM |
4415 | /* Check for other valid prologue instructions besides extend. */ |
4416 | for (i = 0; table[i].mask != 0; i++) | |
4417 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4418 | break; | |
4419 | if (table[i].mask != 0) /* it was in table? */ | |
4420 | continue; /* ignore it */ | |
4421 | else | |
4422 | /* non-prologue */ | |
4423 | { | |
4424 | /* Return the current pc, adjusted backwards by 2 if | |
4425 | the previous instruction was an extend. */ | |
4426 | return pc - prev_extend_bytes; | |
4427 | } | |
c906108c SS |
4428 | } |
4429 | return pc; | |
4430 | } | |
4431 | ||
4432 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4433 | if the code at PC does not look like a function prologue; otherwise | |
4434 | returns an address that (if we're lucky) follows the prologue. If | |
4435 | LENIENT, then we must skip everything which is involved in setting | |
4436 | up the frame (it's OK to skip more, just so long as we don't skip | |
4437 | anything which might clobber the registers which are being saved. | |
4438 | We must skip more in the case where part of the prologue is in the | |
4439 | delay slot of a non-prologue instruction). */ | |
4440 | ||
f7ab6ec6 | 4441 | static CORE_ADDR |
f7b9e9fc | 4442 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4443 | { |
4444 | /* See if we can determine the end of the prologue via the symbol table. | |
4445 | If so, then return either PC, or the PC after the prologue, whichever | |
4446 | is greater. */ | |
4447 | ||
4448 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4449 | ||
4450 | if (post_prologue_pc != 0) | |
4451 | return max (pc, post_prologue_pc); | |
4452 | ||
4453 | /* Can't determine prologue from the symbol table, need to examine | |
4454 | instructions. */ | |
4455 | ||
4456 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4457 | return mips16_skip_prologue (pc); |
c906108c | 4458 | else |
f7b9e9fc | 4459 | return mips32_skip_prologue (pc); |
c906108c | 4460 | } |
c906108c | 4461 | |
7a292a7a SS |
4462 | /* Determine how a return value is stored within the MIPS register |
4463 | file, given the return type `valtype'. */ | |
4464 | ||
4465 | struct return_value_word | |
4466 | { | |
4467 | int len; | |
4468 | int reg; | |
4469 | int reg_offset; | |
4470 | int buf_offset; | |
4471 | }; | |
4472 | ||
7a292a7a | 4473 | static void |
acdb74a0 AC |
4474 | return_value_location (struct type *valtype, |
4475 | struct return_value_word *hi, | |
4476 | struct return_value_word *lo) | |
7a292a7a SS |
4477 | { |
4478 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4479 | |
7a292a7a SS |
4480 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4481 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4482 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4483 | { | |
4484 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4485 | { | |
4486 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4487 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4488 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4489 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4490 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
7a292a7a SS |
4491 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
4492 | ? 4 : 0); | |
4493 | hi->reg_offset = lo->reg_offset; | |
4494 | lo->reg = FP0_REGNUM + 0; | |
4495 | hi->reg = FP0_REGNUM + 1; | |
4496 | lo->len = 4; | |
4497 | hi->len = 4; | |
4498 | } | |
4499 | else | |
4500 | { | |
4501 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4502 | register. */ |
d7449b42 | 4503 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4504 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
4505 | && len == 4) | |
4506 | ? 4 : 0); | |
4507 | lo->reg = FP0_REGNUM; | |
4508 | lo->len = len; | |
4509 | lo->buf_offset = 0; | |
4510 | hi->len = 0; | |
4511 | hi->reg_offset = 0; | |
4512 | hi->buf_offset = 0; | |
4513 | hi->reg = 0; | |
4514 | } | |
4515 | } | |
4516 | else | |
4517 | { | |
4518 | /* Locate a result possibly spread across two registers. */ | |
4519 | int regnum = 2; | |
4520 | lo->reg = regnum + 0; | |
4521 | hi->reg = regnum + 1; | |
d7449b42 | 4522 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4523 | && len < MIPS_SAVED_REGSIZE) |
4524 | { | |
bf1f5b4c MS |
4525 | /* "un-left-justify" the value in the low register */ |
4526 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4527 | lo->len = len; |
bf1f5b4c | 4528 | hi->reg_offset = 0; |
7a292a7a SS |
4529 | hi->len = 0; |
4530 | } | |
d7449b42 | 4531 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4532 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4533 | && len < MIPS_SAVED_REGSIZE * 2 | |
4534 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4535 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4536 | { | |
4537 | /* "un-left-justify" the value spread across two registers. */ | |
4538 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4539 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4540 | hi->reg_offset = 0; | |
4541 | hi->len = len - lo->len; | |
4542 | } | |
4543 | else | |
4544 | { | |
4545 | /* Only perform a partial copy of the second register. */ | |
4546 | lo->reg_offset = 0; | |
4547 | hi->reg_offset = 0; | |
4548 | if (len > MIPS_SAVED_REGSIZE) | |
4549 | { | |
4550 | lo->len = MIPS_SAVED_REGSIZE; | |
4551 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4552 | } | |
4553 | else | |
4554 | { | |
4555 | lo->len = len; | |
4556 | hi->len = 0; | |
4557 | } | |
4558 | } | |
d7449b42 | 4559 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4560 | && REGISTER_RAW_SIZE (regnum) == 8 |
4561 | && MIPS_SAVED_REGSIZE == 4) | |
4562 | { | |
4563 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4564 | of the register is being used */ |
7a292a7a SS |
4565 | lo->reg_offset += 4; |
4566 | hi->reg_offset += 4; | |
4567 | } | |
4568 | lo->buf_offset = 0; | |
4569 | hi->buf_offset = lo->len; | |
4570 | } | |
4571 | } | |
4572 | ||
4573 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4574 | copy its value into `valbuf'. */ | |
4575 | ||
46cac009 AC |
4576 | static void |
4577 | mips_eabi_extract_return_value (struct type *valtype, | |
4578 | char regbuf[REGISTER_BYTES], | |
4579 | char *valbuf) | |
4580 | { | |
4581 | struct return_value_word lo; | |
4582 | struct return_value_word hi; | |
4583 | return_value_location (valtype, &hi, &lo); | |
4584 | ||
4585 | memcpy (valbuf + lo.buf_offset, | |
4586 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4587 | lo.len); | |
4588 | ||
4589 | if (hi.len > 0) | |
4590 | memcpy (valbuf + hi.buf_offset, | |
4591 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4592 | hi.len); | |
4593 | } | |
4594 | ||
46cac009 AC |
4595 | static void |
4596 | mips_o64_extract_return_value (struct type *valtype, | |
4597 | char regbuf[REGISTER_BYTES], | |
4598 | char *valbuf) | |
4599 | { | |
4600 | struct return_value_word lo; | |
4601 | struct return_value_word hi; | |
4602 | return_value_location (valtype, &hi, &lo); | |
4603 | ||
4604 | memcpy (valbuf + lo.buf_offset, | |
4605 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4606 | lo.len); | |
4607 | ||
4608 | if (hi.len > 0) | |
4609 | memcpy (valbuf + hi.buf_offset, | |
4610 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4611 | hi.len); | |
4612 | } | |
4613 | ||
7a292a7a SS |
4614 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4615 | value into the appropriate register. */ | |
4616 | ||
46cac009 AC |
4617 | static void |
4618 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4619 | { | |
4620 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); | |
4621 | struct return_value_word lo; | |
4622 | struct return_value_word hi; | |
4623 | return_value_location (valtype, &hi, &lo); | |
4624 | ||
4625 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4626 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4627 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
4628 | raw_buffer, | |
4629 | REGISTER_RAW_SIZE (lo.reg)); | |
4630 | ||
4631 | if (hi.len > 0) | |
4632 | { | |
4633 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4634 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4635 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
4636 | raw_buffer, | |
4637 | REGISTER_RAW_SIZE (hi.reg)); | |
4638 | } | |
4639 | } | |
4640 | ||
4641 | static void | |
cb1d2653 | 4642 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 AC |
4643 | { |
4644 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); | |
4645 | struct return_value_word lo; | |
4646 | struct return_value_word hi; | |
4647 | return_value_location (valtype, &hi, &lo); | |
4648 | ||
4649 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4650 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4651 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
4652 | raw_buffer, | |
4653 | REGISTER_RAW_SIZE (lo.reg)); | |
4654 | ||
4655 | if (hi.len > 0) | |
4656 | { | |
4657 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4658 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4659 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
4660 | raw_buffer, | |
4661 | REGISTER_RAW_SIZE (hi.reg)); | |
4662 | } | |
4663 | } | |
4664 | ||
cb1d2653 AC |
4665 | /* O32 ABI stuff. */ |
4666 | ||
46cac009 | 4667 | static void |
cb1d2653 AC |
4668 | mips_o32_xfer_return_value (struct type *type, |
4669 | struct regcache *regcache, | |
4670 | bfd_byte *in, const bfd_byte *out) | |
46cac009 | 4671 | { |
cb1d2653 AC |
4672 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4673 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4674 | && TYPE_LENGTH (type) == 4 | |
4675 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4676 | { |
cb1d2653 AC |
4677 | /* A single-precision floating-point value. It fits in the |
4678 | least significant part of FP0. */ | |
4679 | if (mips_debug) | |
4680 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4681 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4682 | TARGET_BYTE_ORDER, in, out, 0); | |
4683 | } | |
4684 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4685 | && TYPE_LENGTH (type) == 8 | |
4686 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4687 | { | |
4688 | /* A double-precision floating-point value. It fits in the | |
4689 | least significant part of FP0/FP1 but with byte ordering | |
4690 | based on the target (???). */ | |
4691 | if (mips_debug) | |
4692 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n"); | |
4693 | switch (TARGET_BYTE_ORDER) | |
4694 | { | |
4695 | case BFD_ENDIAN_LITTLE: | |
4696 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4697 | TARGET_BYTE_ORDER, in, out, 0); | |
4698 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4699 | TARGET_BYTE_ORDER, in, out, 4); | |
4700 | break; | |
4701 | case BFD_ENDIAN_BIG: | |
4702 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4703 | TARGET_BYTE_ORDER, in, out, 0); | |
4704 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4705 | TARGET_BYTE_ORDER, in, out, 4); | |
4706 | break; | |
4707 | default: | |
4708 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4709 | } | |
4710 | } | |
4711 | #if 0 | |
4712 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4713 | && TYPE_NFIELDS (type) <= 2 | |
4714 | && TYPE_NFIELDS (type) >= 1 | |
4715 | && ((TYPE_NFIELDS (type) == 1 | |
4716 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4717 | == TYPE_CODE_FLT)) | |
4718 | || (TYPE_NFIELDS (type) == 2 | |
4719 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4720 | == TYPE_CODE_FLT) | |
4721 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4722 | == TYPE_CODE_FLT))) | |
4723 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4724 | { | |
4725 | /* A struct that contains one or two floats. Each value is part | |
4726 | in the least significant part of their floating point | |
4727 | register.. */ | |
4728 | bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); | |
4729 | int regnum; | |
4730 | int field; | |
4731 | for (field = 0, regnum = FP0_REGNUM; | |
4732 | field < TYPE_NFIELDS (type); | |
4733 | field++, regnum += 2) | |
4734 | { | |
4735 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4736 | / TARGET_CHAR_BIT); | |
4737 | if (mips_debug) | |
4738 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4739 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4740 | TARGET_BYTE_ORDER, in, out, offset); | |
4741 | } | |
4742 | } | |
4743 | #endif | |
4744 | #if 0 | |
4745 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4746 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4747 | { | |
4748 | /* A structure or union. Extract the left justified value, | |
4749 | regardless of the byte order. I.e. DO NOT USE | |
4750 | mips_xfer_lower. */ | |
4751 | int offset; | |
4752 | int regnum; | |
4753 | for (offset = 0, regnum = V0_REGNUM; | |
4754 | offset < TYPE_LENGTH (type); | |
4755 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4756 | { | |
4757 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4758 | if (offset + xfer > TYPE_LENGTH (type)) | |
4759 | xfer = TYPE_LENGTH (type) - offset; | |
4760 | if (mips_debug) | |
4761 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4762 | offset, xfer, regnum); | |
4763 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4764 | in, out, offset); | |
4765 | } | |
4766 | } | |
4767 | #endif | |
4768 | else | |
4769 | { | |
4770 | /* A scalar extract each part but least-significant-byte | |
4771 | justified. o32 thinks registers are 4 byte, regardless of | |
4772 | the ISA. mips_stack_argsize controls this. */ | |
4773 | int offset; | |
4774 | int regnum; | |
4775 | for (offset = 0, regnum = V0_REGNUM; | |
4776 | offset < TYPE_LENGTH (type); | |
4777 | offset += mips_stack_argsize (), regnum++) | |
4778 | { | |
4779 | int xfer = mips_stack_argsize (); | |
4780 | int pos = 0; | |
4781 | if (offset + xfer > TYPE_LENGTH (type)) | |
4782 | xfer = TYPE_LENGTH (type) - offset; | |
4783 | if (mips_debug) | |
4784 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4785 | offset, xfer, regnum); | |
4786 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4787 | in, out, offset); | |
4788 | } | |
46cac009 AC |
4789 | } |
4790 | } | |
4791 | ||
cb1d2653 AC |
4792 | static void |
4793 | mips_o32_extract_return_value (struct type *type, | |
4794 | struct regcache *regcache, | |
ebba8386 | 4795 | void *valbuf) |
cb1d2653 AC |
4796 | { |
4797 | mips_o32_xfer_return_value (type, regcache, valbuf, NULL); | |
4798 | } | |
4799 | ||
4800 | static void | |
4801 | mips_o32_store_return_value (struct type *type, char *valbuf) | |
4802 | { | |
4803 | mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf); | |
4804 | } | |
4805 | ||
4806 | /* N32/N44 ABI stuff. */ | |
4807 | ||
46cac009 | 4808 | static void |
88658117 AC |
4809 | mips_n32n64_xfer_return_value (struct type *type, |
4810 | struct regcache *regcache, | |
4811 | bfd_byte *in, const bfd_byte *out) | |
c906108c | 4812 | { |
88658117 AC |
4813 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4814 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4815 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4816 | { |
88658117 AC |
4817 | /* A floating-point value belongs in the least significant part |
4818 | of FP0. */ | |
4819 | if (mips_debug) | |
4820 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4821 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4822 | TARGET_BYTE_ORDER, in, out, 0); | |
4823 | } | |
4824 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4825 | && TYPE_NFIELDS (type) <= 2 | |
4826 | && TYPE_NFIELDS (type) >= 1 | |
4827 | && ((TYPE_NFIELDS (type) == 1 | |
4828 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4829 | == TYPE_CODE_FLT)) | |
4830 | || (TYPE_NFIELDS (type) == 2 | |
4831 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4832 | == TYPE_CODE_FLT) | |
4833 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4834 | == TYPE_CODE_FLT))) | |
4835 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4836 | { | |
4837 | /* A struct that contains one or two floats. Each value is part | |
4838 | in the least significant part of their floating point | |
4839 | register.. */ | |
4840 | bfd_byte *reg = alloca (MAX_REGISTER_RAW_SIZE); | |
4841 | int regnum; | |
4842 | int field; | |
4843 | for (field = 0, regnum = FP0_REGNUM; | |
4844 | field < TYPE_NFIELDS (type); | |
4845 | field++, regnum += 2) | |
4846 | { | |
4847 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4848 | / TARGET_CHAR_BIT); | |
4849 | if (mips_debug) | |
4850 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4851 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4852 | TARGET_BYTE_ORDER, in, out, offset); | |
4853 | } | |
7a292a7a | 4854 | } |
88658117 AC |
4855 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4856 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4857 | { | |
4858 | /* A structure or union. Extract the left justified value, | |
4859 | regardless of the byte order. I.e. DO NOT USE | |
4860 | mips_xfer_lower. */ | |
4861 | int offset; | |
4862 | int regnum; | |
4863 | for (offset = 0, regnum = V0_REGNUM; | |
4864 | offset < TYPE_LENGTH (type); | |
4865 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4866 | { | |
4867 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4868 | if (offset + xfer > TYPE_LENGTH (type)) | |
4869 | xfer = TYPE_LENGTH (type) - offset; | |
4870 | if (mips_debug) | |
4871 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4872 | offset, xfer, regnum); | |
4873 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4874 | in, out, offset); | |
4875 | } | |
4876 | } | |
4877 | else | |
4878 | { | |
4879 | /* A scalar extract each part but least-significant-byte | |
4880 | justified. */ | |
4881 | int offset; | |
4882 | int regnum; | |
4883 | for (offset = 0, regnum = V0_REGNUM; | |
4884 | offset < TYPE_LENGTH (type); | |
4885 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4886 | { | |
4887 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4888 | int pos = 0; | |
4889 | if (offset + xfer > TYPE_LENGTH (type)) | |
4890 | xfer = TYPE_LENGTH (type) - offset; | |
4891 | if (mips_debug) | |
4892 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4893 | offset, xfer, regnum); | |
4894 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4895 | in, out, offset); | |
4896 | } | |
4897 | } | |
4898 | } | |
4899 | ||
4900 | static void | |
4901 | mips_n32n64_extract_return_value (struct type *type, | |
4902 | struct regcache *regcache, | |
ebba8386 | 4903 | void *valbuf) |
88658117 AC |
4904 | { |
4905 | mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); | |
4906 | } | |
4907 | ||
4908 | static void | |
4909 | mips_n32n64_store_return_value (struct type *type, char *valbuf) | |
4910 | { | |
4911 | mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); | |
c906108c SS |
4912 | } |
4913 | ||
2f1488ce MS |
4914 | static void |
4915 | mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
4916 | { | |
4917 | /* Nothing to do -- push_arguments does all the work. */ | |
4918 | } | |
4919 | ||
4920 | static CORE_ADDR | |
6672060b | 4921 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
4922 | { |
4923 | /* FIXME: This will only work at random. The caller passes the | |
4924 | struct_return address in V0, but it is not preserved. It may | |
4925 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
4926 | LONGEST val; |
4927 | ||
4928 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 4929 | return val; |
2f1488ce MS |
4930 | } |
4931 | ||
c906108c SS |
4932 | /* Exported procedure: Is PC in the signal trampoline code */ |
4933 | ||
102182a9 MS |
4934 | static int |
4935 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
4936 | { |
4937 | if (sigtramp_address == 0) | |
4938 | fixup_sigtramp (); | |
4939 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
4940 | } | |
4941 | ||
a5ea2558 AC |
4942 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4943 | used for all MIPS-specific commands. */ | |
4944 | ||
a5ea2558 | 4945 | static void |
acdb74a0 | 4946 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4947 | { |
4948 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4949 | } | |
4950 | ||
a5ea2558 | 4951 | static void |
acdb74a0 | 4952 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4953 | { |
4954 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
4955 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
4956 | } | |
4957 | ||
c906108c SS |
4958 | /* Commands to show/set the MIPS FPU type. */ |
4959 | ||
c906108c | 4960 | static void |
acdb74a0 | 4961 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4962 | { |
c906108c SS |
4963 | char *fpu; |
4964 | switch (MIPS_FPU_TYPE) | |
4965 | { | |
4966 | case MIPS_FPU_SINGLE: | |
4967 | fpu = "single-precision"; | |
4968 | break; | |
4969 | case MIPS_FPU_DOUBLE: | |
4970 | fpu = "double-precision"; | |
4971 | break; | |
4972 | case MIPS_FPU_NONE: | |
4973 | fpu = "absent (none)"; | |
4974 | break; | |
93d56215 AC |
4975 | default: |
4976 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4977 | } |
4978 | if (mips_fpu_type_auto) | |
4979 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4980 | fpu); | |
4981 | else | |
4982 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
4983 | fpu); | |
4984 | } | |
4985 | ||
4986 | ||
c906108c | 4987 | static void |
acdb74a0 | 4988 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
4989 | { |
4990 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
4991 | show_mipsfpu_command (args, from_tty); | |
4992 | } | |
4993 | ||
c906108c | 4994 | static void |
acdb74a0 | 4995 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
4996 | { |
4997 | mips_fpu_type = MIPS_FPU_SINGLE; | |
4998 | mips_fpu_type_auto = 0; | |
9e364162 | 4999 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5000 | } |
5001 | ||
c906108c | 5002 | static void |
acdb74a0 | 5003 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5004 | { |
5005 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5006 | mips_fpu_type_auto = 0; | |
9e364162 | 5007 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5008 | } |
5009 | ||
c906108c | 5010 | static void |
acdb74a0 | 5011 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5012 | { |
5013 | mips_fpu_type = MIPS_FPU_NONE; | |
5014 | mips_fpu_type_auto = 0; | |
9e364162 | 5015 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5016 | } |
5017 | ||
c906108c | 5018 | static void |
acdb74a0 | 5019 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5020 | { |
5021 | mips_fpu_type_auto = 1; | |
5022 | } | |
5023 | ||
5024 | /* Command to set the processor type. */ | |
5025 | ||
5026 | void | |
acdb74a0 | 5027 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
5028 | { |
5029 | int i; | |
5030 | ||
5031 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
5032 | { | |
5033 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
5034 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5035 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
5036 | ||
5037 | /* Restore the value. */ | |
4fcf66da | 5038 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5039 | |
5040 | return; | |
5041 | } | |
c5aa993b | 5042 | |
c906108c SS |
5043 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
5044 | { | |
5045 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
5046 | /* Restore its value. */ | |
4fcf66da | 5047 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5048 | } |
5049 | } | |
5050 | ||
5051 | static void | |
acdb74a0 | 5052 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
5053 | { |
5054 | } | |
5055 | ||
5056 | /* Modify the actual processor type. */ | |
5057 | ||
5a89d8aa | 5058 | static int |
acdb74a0 | 5059 | mips_set_processor_type (char *str) |
c906108c | 5060 | { |
1012bd0e | 5061 | int i; |
c906108c SS |
5062 | |
5063 | if (str == NULL) | |
5064 | return 0; | |
5065 | ||
5066 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5067 | { | |
5068 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
5069 | { | |
5070 | mips_processor_type = str; | |
cce74817 | 5071 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 5072 | return 1; |
c906108c SS |
5073 | /* FIXME tweak fpu flag too */ |
5074 | } | |
5075 | } | |
5076 | ||
5077 | return 0; | |
5078 | } | |
5079 | ||
5080 | /* Attempt to identify the particular processor model by reading the | |
5081 | processor id. */ | |
5082 | ||
5083 | char * | |
acdb74a0 | 5084 | mips_read_processor_type (void) |
c906108c SS |
5085 | { |
5086 | CORE_ADDR prid; | |
5087 | ||
5088 | prid = read_register (PRID_REGNUM); | |
5089 | ||
5090 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 5091 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
5092 | |
5093 | return NULL; | |
5094 | } | |
5095 | ||
5096 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5097 | callable as an sfunc. */ | |
5098 | ||
5099 | static void | |
acdb74a0 AC |
5100 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5101 | struct cmd_list_element *c) | |
c906108c SS |
5102 | { |
5103 | reinit_frame_cache (); | |
5104 | } | |
5105 | ||
5106 | int | |
acdb74a0 | 5107 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
5108 | { |
5109 | mips_extra_func_info_t proc_desc; | |
5110 | ||
5111 | /* Search for the function containing this address. Set the low bit | |
5112 | of the address when searching, in case we were given an even address | |
5113 | that is the start of a 16-bit function. If we didn't do this, | |
5114 | the search would fail because the symbol table says the function | |
5115 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5116 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
5117 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
5118 | ||
5119 | /* Make an attempt to determine if this is a 16-bit function. If | |
5120 | the procedure descriptor exists and the address therein is odd, | |
5121 | it's definitely a 16-bit function. Otherwise, we have to just | |
5122 | guess that if the address passed in is odd, it's 16-bits. */ | |
5123 | if (proc_desc) | |
361d1df0 | 5124 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
65c11066 | 5125 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c | 5126 | else |
361d1df0 | 5127 | info->mach = pc_is_mips16 (memaddr) ? |
65c11066 | 5128 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c SS |
5129 | |
5130 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5131 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5132 | |
c906108c | 5133 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5134 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5135 | return print_insn_big_mips (memaddr, info); |
5136 | else | |
5137 | return print_insn_little_mips (memaddr, info); | |
5138 | } | |
5139 | ||
5140 | /* Old-style breakpoint macros. | |
5141 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
5142 | confused when it sees the usual MIPS breakpoint instruction. */ | |
5143 | ||
5144 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
5145 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
5146 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
5147 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
5148 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
5149 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
5150 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
5151 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
5152 | ||
5153 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
5154 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5155 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5156 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5157 | (if necessary) to point to the actual memory location where the | |
5158 | breakpoint should be inserted. */ | |
5159 | ||
f7ab6ec6 | 5160 | static const unsigned char * |
acdb74a0 | 5161 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5162 | { |
d7449b42 | 5163 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5164 | { |
5165 | if (pc_is_mips16 (*pcptr)) | |
5166 | { | |
1012bd0e EZ |
5167 | static unsigned char mips16_big_breakpoint[] = |
5168 | MIPS16_BIG_BREAKPOINT; | |
c906108c | 5169 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 5170 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5171 | return mips16_big_breakpoint; |
5172 | } | |
5173 | else | |
5174 | { | |
1012bd0e EZ |
5175 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
5176 | static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
5177 | static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
c906108c | 5178 | |
c5aa993b | 5179 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5180 | |
5181 | if (strcmp (target_shortname, "mips") == 0) | |
5182 | return idt_big_breakpoint; | |
5183 | else if (strcmp (target_shortname, "ddb") == 0 | |
5184 | || strcmp (target_shortname, "pmon") == 0 | |
5185 | || strcmp (target_shortname, "lsi") == 0) | |
5186 | return pmon_big_breakpoint; | |
5187 | else | |
5188 | return big_breakpoint; | |
5189 | } | |
5190 | } | |
5191 | else | |
5192 | { | |
5193 | if (pc_is_mips16 (*pcptr)) | |
5194 | { | |
1012bd0e EZ |
5195 | static unsigned char mips16_little_breakpoint[] = |
5196 | MIPS16_LITTLE_BREAKPOINT; | |
c906108c | 5197 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 5198 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5199 | return mips16_little_breakpoint; |
5200 | } | |
5201 | else | |
5202 | { | |
1012bd0e EZ |
5203 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; |
5204 | static unsigned char pmon_little_breakpoint[] = | |
5205 | PMON_LITTLE_BREAKPOINT; | |
5206 | static unsigned char idt_little_breakpoint[] = | |
5207 | IDT_LITTLE_BREAKPOINT; | |
c906108c | 5208 | |
c5aa993b | 5209 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5210 | |
5211 | if (strcmp (target_shortname, "mips") == 0) | |
5212 | return idt_little_breakpoint; | |
5213 | else if (strcmp (target_shortname, "ddb") == 0 | |
5214 | || strcmp (target_shortname, "pmon") == 0 | |
5215 | || strcmp (target_shortname, "lsi") == 0) | |
5216 | return pmon_little_breakpoint; | |
5217 | else | |
5218 | return little_breakpoint; | |
5219 | } | |
5220 | } | |
5221 | } | |
5222 | ||
5223 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5224 | PC, which is either the callee or the caller. There are several | |
5225 | cases which must be handled: | |
5226 | ||
5227 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5228 | target PC is in $31 ($ra). |
c906108c | 5229 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5230 | and the target PC is in $2. |
c906108c | 5231 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5232 | before the jal instruction, this is effectively a call stub |
5233 | and the the target PC is in $2. Otherwise this is effectively | |
5234 | a return stub and the target PC is in $18. | |
c906108c SS |
5235 | |
5236 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5237 | gory details. | |
5238 | ||
5239 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5240 | */ |
c906108c | 5241 | |
757a7cc6 | 5242 | static CORE_ADDR |
acdb74a0 | 5243 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5244 | { |
5245 | char *name; | |
5246 | CORE_ADDR start_addr; | |
5247 | ||
5248 | /* Find the starting address and name of the function containing the PC. */ | |
5249 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5250 | return 0; | |
5251 | ||
5252 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5253 | target PC is in $31 ($ra). */ | |
5254 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5255 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5256 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5257 | |
5258 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5259 | { | |
5260 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5261 | and the target PC is in $2. */ | |
5262 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5263 | return read_signed_register (2); |
c906108c SS |
5264 | |
5265 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5266 | before the jal instruction, this is effectively a call stub |
5267 | and the the target PC is in $2. Otherwise this is effectively | |
5268 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5269 | else if (name[19] == 's' || name[19] == 'd') |
5270 | { | |
5271 | if (pc == start_addr) | |
5272 | { | |
5273 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5274 | stub. Such a stub for a function bar might have a name |
5275 | like __fn_stub_bar, and might look like this: | |
5276 | mfc1 $4,$f13 | |
5277 | mfc1 $5,$f12 | |
5278 | mfc1 $6,$f15 | |
5279 | mfc1 $7,$f14 | |
5280 | la $1,bar (becomes a lui/addiu pair) | |
5281 | jr $1 | |
5282 | So scan down to the lui/addi and extract the target | |
5283 | address from those two instructions. */ | |
c906108c | 5284 | |
6c997a34 | 5285 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5286 | t_inst inst; |
5287 | int i; | |
5288 | ||
5289 | /* See if the name of the target function is __fn_stub_*. */ | |
5290 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5291 | return target_pc; | |
5292 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5293 | && strcmp (name, "etext") != 0 | |
5294 | && strcmp (name, "_etext") != 0) | |
5295 | return target_pc; | |
5296 | ||
5297 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5298 | The limit on the search is arbitrarily set to 20 |
5299 | instructions. FIXME. */ | |
c906108c SS |
5300 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5301 | { | |
c5aa993b JM |
5302 | inst = mips_fetch_instruction (target_pc); |
5303 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5304 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5305 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5306 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5307 | } |
5308 | ||
5309 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5310 | return target_pc; | |
5311 | } | |
5312 | else | |
5313 | /* This is the 'return' part of a call stub. The return | |
5314 | address is in $r18. */ | |
6c997a34 | 5315 | return read_signed_register (18); |
c906108c SS |
5316 | } |
5317 | } | |
c5aa993b | 5318 | return 0; /* not a stub */ |
c906108c SS |
5319 | } |
5320 | ||
5321 | ||
5322 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5323 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5324 | ||
757a7cc6 | 5325 | static int |
acdb74a0 | 5326 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5327 | { |
5328 | CORE_ADDR start_addr; | |
5329 | ||
5330 | /* Find the starting address of the function containing the PC. If the | |
5331 | caller didn't give us a name, look it up at the same time. */ | |
5332 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5333 | return 0; | |
5334 | ||
5335 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5336 | { | |
5337 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5338 | if (name[19] >= '0' && name[19] <= '9') | |
5339 | return 1; | |
5340 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5341 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5342 | else if (name[19] == 's' || name[19] == 'd') |
5343 | return pc == start_addr; | |
5344 | } | |
5345 | ||
c5aa993b | 5346 | return 0; /* not a stub */ |
c906108c SS |
5347 | } |
5348 | ||
5349 | ||
5350 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5351 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5352 | ||
e41b17f0 | 5353 | static int |
acdb74a0 | 5354 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5355 | { |
5356 | CORE_ADDR start_addr; | |
5357 | ||
5358 | /* Find the starting address of the function containing the PC. */ | |
5359 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5360 | return 0; | |
5361 | ||
5362 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5363 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5364 | || strcmp (name, "__mips16_ret_df") == 0) | |
5365 | return 1; | |
5366 | ||
5367 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5368 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5369 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5370 | && (name[19] == 's' || name[19] == 'd') | |
5371 | && pc != start_addr) | |
5372 | return 1; | |
5373 | ||
c5aa993b | 5374 | return 0; /* not a stub */ |
c906108c SS |
5375 | } |
5376 | ||
5377 | ||
5378 | /* Return non-zero if the PC is in a library helper function that should | |
5379 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5380 | ||
5381 | int | |
acdb74a0 | 5382 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5383 | { |
5384 | char *name; | |
5385 | ||
5386 | /* Find the starting address and name of the function containing the PC. */ | |
5387 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5388 | return 0; | |
5389 | ||
5390 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5391 | that we want to ignore. */ | |
5392 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5393 | || strcmp (name, "__mips16_ret_df") == 0); | |
5394 | } | |
5395 | ||
5396 | ||
5397 | /* Return a location where we can set a breakpoint that will be hit | |
5398 | when an inferior function call returns. This is normally the | |
5399 | program's entry point. Executables that don't have an entry | |
5400 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
5401 | whose address is the location where the breakpoint should be placed. */ | |
5402 | ||
f7ab6ec6 | 5403 | static CORE_ADDR |
acdb74a0 | 5404 | mips_call_dummy_address (void) |
c906108c SS |
5405 | { |
5406 | struct minimal_symbol *sym; | |
5407 | ||
5408 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
5409 | if (sym) | |
5410 | return SYMBOL_VALUE_ADDRESS (sym); | |
5411 | else | |
5412 | return entry_point_address (); | |
5413 | } | |
5414 | ||
5415 | ||
9dcb560c | 5416 | /* If the current gcc for this target does not produce correct debugging |
b9a8e3bf JB |
5417 | information for float parameters, both prototyped and unprototyped, then |
5418 | define this macro. This forces gdb to always assume that floats are | |
5419 | passed as doubles and then converted in the callee. | |
5420 | ||
5421 | For the mips chip, it appears that the debug info marks the parameters as | |
5422 | floats regardless of whether the function is prototyped, but the actual | |
5423 | values are passed as doubles for the non-prototyped case and floats for | |
5424 | the prototyped case. Thus we choose to make the non-prototyped case work | |
5425 | for C and break the prototyped case, since the non-prototyped case is | |
5426 | probably much more common. (FIXME). */ | |
5427 | ||
5428 | static int | |
5429 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
5430 | { | |
5431 | return current_language->la_language == language_c; | |
5432 | } | |
5433 | ||
47a8d4ba AC |
5434 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5435 | the register stored on the stack (32) is different to its real raw | |
5436 | size (64). The below ensures that registers are fetched from the | |
5437 | stack using their ABI size and then stored into the RAW_BUFFER | |
5438 | using their raw size. | |
5439 | ||
5440 | The alternative to adding this function would be to add an ABI | |
5441 | macro - REGISTER_STACK_SIZE(). */ | |
5442 | ||
5443 | static void | |
acdb74a0 | 5444 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5445 | int *optimizedp, |
acdb74a0 AC |
5446 | CORE_ADDR *addrp, |
5447 | struct frame_info *frame, | |
5448 | int regnum, | |
795e1e11 | 5449 | enum lval_type *lvalp) |
47a8d4ba | 5450 | { |
795e1e11 AC |
5451 | CORE_ADDR addrx; |
5452 | enum lval_type lvalx; | |
5453 | int optimizedx; | |
5454 | int realnum; | |
47a8d4ba AC |
5455 | |
5456 | if (!target_has_registers) | |
5457 | error ("No registers."); | |
5458 | ||
795e1e11 AC |
5459 | /* Make certain that all needed parameters are present. */ |
5460 | if (addrp == NULL) | |
5461 | addrp = &addrx; | |
5462 | if (lvalp == NULL) | |
5463 | lvalp = &lvalx; | |
5464 | if (optimizedp == NULL) | |
5465 | optimizedp = &optimizedx; | |
5466 | frame_register_unwind (get_next_frame (frame), regnum, optimizedp, lvalp, | |
5467 | addrp, &realnum, raw_buffer); | |
5468 | /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should | |
5469 | have a pseudo register range that correspons to the ABI's, rather | |
5470 | than the ISA's, view of registers. These registers would then | |
5471 | implicitly describe their size and hence could be used without | |
5472 | the below munging. */ | |
5473 | if ((*lvalp) == lval_memory) | |
47a8d4ba | 5474 | { |
47a8d4ba AC |
5475 | if (raw_buffer != NULL) |
5476 | { | |
47a8d4ba | 5477 | if (regnum < 32) |
795e1e11 AC |
5478 | { |
5479 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
5480 | saved. */ | |
5481 | LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE); | |
5482 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
5483 | } | |
47a8d4ba AC |
5484 | } |
5485 | } | |
47a8d4ba | 5486 | } |
2acceee2 | 5487 | |
f7b9e9fc AC |
5488 | /* Immediately after a function call, return the saved pc. |
5489 | Can't always go through the frames for this because on some machines | |
5490 | the new frame is not set up until the new function executes | |
5491 | some instructions. */ | |
5492 | ||
5493 | static CORE_ADDR | |
5494 | mips_saved_pc_after_call (struct frame_info *frame) | |
5495 | { | |
6c997a34 | 5496 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5497 | } |
5498 | ||
5499 | ||
88c72b7d AC |
5500 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
5501 | REGNUM */ | |
5502 | ||
5503 | static int | |
5504 | mips_stab_reg_to_regnum (int num) | |
5505 | { | |
5506 | if (num < 32) | |
5507 | return num; | |
361d1df0 | 5508 | else |
88c72b7d AC |
5509 | return num + FP0_REGNUM - 38; |
5510 | } | |
5511 | ||
5512 | /* Convert a ecoff register number to a gdb REGNUM */ | |
5513 | ||
5514 | static int | |
5515 | mips_ecoff_reg_to_regnum (int num) | |
5516 | { | |
5517 | if (num < 32) | |
5518 | return num; | |
5519 | else | |
5520 | return num + FP0_REGNUM - 32; | |
5521 | } | |
5522 | ||
fc0c74b1 AC |
5523 | /* Convert an integer into an address. By first converting the value |
5524 | into a pointer and then extracting it signed, the address is | |
5525 | guarenteed to be correctly sign extended. */ | |
5526 | ||
5527 | static CORE_ADDR | |
5528 | mips_integer_to_address (struct type *type, void *buf) | |
5529 | { | |
5530 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5531 | LONGEST val = unpack_long (type, buf); | |
5532 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5533 | return extract_signed_integer (tmp, | |
5534 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5535 | } | |
5536 | ||
caaa3122 DJ |
5537 | static void |
5538 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5539 | { | |
5540 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5541 | const char *name = bfd_get_section_name (abfd, sect); | |
5542 | ||
5543 | if (*abip != MIPS_ABI_UNKNOWN) | |
5544 | return; | |
5545 | ||
5546 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5547 | return; | |
5548 | ||
5549 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5550 | *abip = MIPS_ABI_O32; | |
5551 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5552 | *abip = MIPS_ABI_N32; | |
e3bddbfa KB |
5553 | else if (strcmp (name, ".mdebug.abiN64") == 0) |
5554 | *abip = MIPS_ABI_N64; | |
caaa3122 DJ |
5555 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5556 | *abip = MIPS_ABI_O64; | |
5557 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5558 | *abip = MIPS_ABI_EABI32; | |
5559 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5560 | *abip = MIPS_ABI_EABI64; | |
5561 | else | |
5562 | warning ("unsupported ABI %s.", name + 8); | |
5563 | } | |
5564 | ||
2e4ebe70 DJ |
5565 | static enum mips_abi |
5566 | global_mips_abi (void) | |
5567 | { | |
5568 | int i; | |
5569 | ||
5570 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5571 | if (mips_abi_strings[i] == mips_abi_string) | |
5572 | return (enum mips_abi) i; | |
5573 | ||
5574 | internal_error (__FILE__, __LINE__, | |
5575 | "unknown ABI string"); | |
5576 | } | |
5577 | ||
c2d11a7d | 5578 | static struct gdbarch * |
acdb74a0 AC |
5579 | mips_gdbarch_init (struct gdbarch_info info, |
5580 | struct gdbarch_list *arches) | |
c2d11a7d JM |
5581 | { |
5582 | static LONGEST mips_call_dummy_words[] = | |
5583 | {0}; | |
5584 | struct gdbarch *gdbarch; | |
5585 | struct gdbarch_tdep *tdep; | |
5586 | int elf_flags; | |
2e4ebe70 | 5587 | enum mips_abi mips_abi, found_abi, wanted_abi; |
70f80edf | 5588 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
c2d11a7d | 5589 | |
1d06468c EZ |
5590 | /* Reset the disassembly info, in case it was set to something |
5591 | non-default. */ | |
5592 | tm_print_insn_info.flavour = bfd_target_unknown_flavour; | |
5593 | tm_print_insn_info.arch = bfd_arch_unknown; | |
5594 | tm_print_insn_info.mach = 0; | |
5595 | ||
70f80edf JT |
5596 | elf_flags = 0; |
5597 | ||
5598 | if (info.abfd) | |
5599 | { | |
5600 | /* First of all, extract the elf_flags, if available. */ | |
5601 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5602 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
5603 | ||
5604 | /* Try to determine the OS ABI of the object we are loading. If | |
5605 | we end up with `unknown', just leave it that way. */ | |
5606 | osabi = gdbarch_lookup_osabi (info.abfd); | |
5607 | } | |
c2d11a7d | 5608 | |
102182a9 | 5609 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5610 | switch ((elf_flags & EF_MIPS_ABI)) |
5611 | { | |
5612 | case E_MIPS_ABI_O32: | |
5613 | mips_abi = MIPS_ABI_O32; | |
5614 | break; | |
5615 | case E_MIPS_ABI_O64: | |
5616 | mips_abi = MIPS_ABI_O64; | |
5617 | break; | |
5618 | case E_MIPS_ABI_EABI32: | |
5619 | mips_abi = MIPS_ABI_EABI32; | |
5620 | break; | |
5621 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5622 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5623 | break; |
5624 | default: | |
acdb74a0 AC |
5625 | if ((elf_flags & EF_MIPS_ABI2)) |
5626 | mips_abi = MIPS_ABI_N32; | |
5627 | else | |
5628 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5629 | break; |
5630 | } | |
acdb74a0 | 5631 | |
caaa3122 DJ |
5632 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5633 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5634 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5635 | ||
2e4ebe70 DJ |
5636 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5637 | Use the ABI from the last architecture if there is one. */ | |
5638 | if (info.abfd == NULL && arches != NULL) | |
5639 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5640 | ||
32a6503c | 5641 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5642 | if (mips_abi == MIPS_ABI_UNKNOWN |
5643 | && info.bfd_arch_info != NULL | |
5644 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5645 | { | |
5646 | switch (info.bfd_arch_info->mach) | |
5647 | { | |
5648 | case bfd_mach_mips3900: | |
5649 | mips_abi = MIPS_ABI_EABI32; | |
5650 | break; | |
5651 | case bfd_mach_mips4100: | |
5652 | case bfd_mach_mips5000: | |
5653 | mips_abi = MIPS_ABI_EABI64; | |
5654 | break; | |
1d06468c EZ |
5655 | case bfd_mach_mips8000: |
5656 | case bfd_mach_mips10000: | |
32a6503c KB |
5657 | /* On Irix, ELF64 executables use the N64 ABI. The |
5658 | pseudo-sections which describe the ABI aren't present | |
5659 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5660 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5661 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5662 | mips_abi = MIPS_ABI_N64; | |
5663 | else | |
5664 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5665 | break; |
bf64bfd6 AC |
5666 | } |
5667 | } | |
2e4ebe70 | 5668 | |
2e4ebe70 DJ |
5669 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5670 | mips_abi = MIPS_ABI_O32; | |
5671 | ||
5672 | /* Now that we have found what the ABI for this binary would be, | |
5673 | check whether the user is overriding it. */ | |
5674 | found_abi = mips_abi; | |
5675 | wanted_abi = global_mips_abi (); | |
5676 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5677 | mips_abi = wanted_abi; | |
5678 | ||
4b9b3959 AC |
5679 | if (gdbarch_debug) |
5680 | { | |
5681 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5682 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5683 | elf_flags); |
4b9b3959 AC |
5684 | fprintf_unfiltered (gdb_stdlog, |
5685 | "mips_gdbarch_init: mips_abi = %d\n", | |
5686 | mips_abi); | |
2e4ebe70 DJ |
5687 | fprintf_unfiltered (gdb_stdlog, |
5688 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5689 | found_abi); | |
4b9b3959 | 5690 | } |
0dadbba0 | 5691 | |
c2d11a7d JM |
5692 | /* try to find a pre-existing architecture */ |
5693 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5694 | arches != NULL; | |
5695 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5696 | { | |
5697 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5698 | using. */ |
9103eae0 | 5699 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5700 | continue; |
9103eae0 | 5701 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5702 | continue; |
70f80edf JT |
5703 | if (gdbarch_tdep (arches->gdbarch)->osabi == osabi) |
5704 | return arches->gdbarch; | |
c2d11a7d JM |
5705 | } |
5706 | ||
102182a9 | 5707 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5708 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5709 | gdbarch = gdbarch_alloc (&info, tdep); | |
5710 | tdep->elf_flags = elf_flags; | |
70f80edf | 5711 | tdep->osabi = osabi; |
c2d11a7d | 5712 | |
102182a9 | 5713 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5714 | set_gdbarch_short_bit (gdbarch, 16); |
5715 | set_gdbarch_int_bit (gdbarch, 32); | |
5716 | set_gdbarch_float_bit (gdbarch, 32); | |
5717 | set_gdbarch_double_bit (gdbarch, 64); | |
5718 | set_gdbarch_long_double_bit (gdbarch, 64); | |
46cd78fb | 5719 | set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); |
d05285fa MS |
5720 | set_gdbarch_max_register_raw_size (gdbarch, 8); |
5721 | set_gdbarch_max_register_virtual_size (gdbarch, 8); | |
2e4ebe70 | 5722 | tdep->found_abi = found_abi; |
0dadbba0 | 5723 | tdep->mips_abi = mips_abi; |
1d06468c | 5724 | |
f7ab6ec6 MS |
5725 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5726 | mips_elf_make_msymbol_special); | |
5727 | ||
0dadbba0 | 5728 | switch (mips_abi) |
c2d11a7d | 5729 | { |
0dadbba0 | 5730 | case MIPS_ABI_O32: |
46cac009 | 5731 | set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments); |
ebba8386 | 5732 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); |
cb1d2653 | 5733 | set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); |
a5ea2558 | 5734 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5735 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5736 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5737 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5738 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5739 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5740 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5741 | set_gdbarch_long_bit (gdbarch, 32); |
5742 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5743 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5744 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5745 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5746 | set_gdbarch_use_struct_convention (gdbarch, |
5747 | mips_o32_use_struct_convention); | |
c2d11a7d | 5748 | break; |
0dadbba0 | 5749 | case MIPS_ABI_O64: |
46cac009 | 5750 | set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments); |
ebba8386 | 5751 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5752 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5753 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5754 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5755 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5756 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5757 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5758 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 5759 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5760 | set_gdbarch_long_bit (gdbarch, 32); |
5761 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5762 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5763 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5764 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5765 | set_gdbarch_use_struct_convention (gdbarch, |
5766 | mips_o32_use_struct_convention); | |
c2d11a7d | 5767 | break; |
0dadbba0 | 5768 | case MIPS_ABI_EABI32: |
46e0f506 | 5769 | set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); |
ebba8386 | 5770 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5771 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5772 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5773 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5774 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5775 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5776 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5777 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5778 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5779 | set_gdbarch_long_bit (gdbarch, 32); |
5780 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5781 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5782 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5783 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5784 | set_gdbarch_use_struct_convention (gdbarch, |
5785 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5786 | break; |
0dadbba0 | 5787 | case MIPS_ABI_EABI64: |
46e0f506 | 5788 | set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); |
ebba8386 | 5789 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5790 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5791 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5792 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5793 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5794 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5795 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5796 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5797 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5798 | set_gdbarch_long_bit (gdbarch, 64); |
5799 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5800 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5801 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5802 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5803 | set_gdbarch_use_struct_convention (gdbarch, |
5804 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5805 | break; |
0dadbba0 | 5806 | case MIPS_ABI_N32: |
cb3d25d1 | 5807 | set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); |
ebba8386 | 5808 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5809 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
63db5580 | 5810 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5811 | tdep->mips_default_stack_argsize = 8; |
5812 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
5813 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5814 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
6acdf5c7 | 5815 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5816 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5817 | set_gdbarch_long_bit (gdbarch, 32); |
5818 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5819 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1d06468c EZ |
5820 | |
5821 | /* Set up the disassembler info, so that we get the right | |
28d169de KB |
5822 | register names from libopcodes. */ |
5823 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5824 | tm_print_insn_info.arch = bfd_arch_mips; | |
5825 | if (info.bfd_arch_info != NULL | |
5826 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5827 | && info.bfd_arch_info->mach) | |
5828 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
5829 | else | |
5830 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
cb811fe7 MS |
5831 | |
5832 | set_gdbarch_use_struct_convention (gdbarch, | |
5833 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5834 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5835 | mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5836 | break; |
5837 | case MIPS_ABI_N64: | |
cb3d25d1 | 5838 | set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); |
ebba8386 | 5839 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5840 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
28d169de KB |
5841 | tdep->mips_default_saved_regsize = 8; |
5842 | tdep->mips_default_stack_argsize = 8; | |
5843 | tdep->mips_fp_register_double = 1; | |
5844 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
5845 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
28d169de KB |
5846 | tdep->gdb_target_is_mips64 = 1; |
5847 | tdep->default_mask_address_p = 0; | |
5848 | set_gdbarch_long_bit (gdbarch, 64); | |
5849 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5850 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5851 | ||
5852 | /* Set up the disassembler info, so that we get the right | |
1d06468c EZ |
5853 | register names from libopcodes. */ |
5854 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5855 | tm_print_insn_info.arch = bfd_arch_mips; | |
5856 | if (info.bfd_arch_info != NULL | |
5857 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5858 | && info.bfd_arch_info->mach) | |
5859 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
5860 | else | |
5861 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
cb811fe7 MS |
5862 | |
5863 | set_gdbarch_use_struct_convention (gdbarch, | |
5864 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5865 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5866 | mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5867 | break; |
c2d11a7d | 5868 | default: |
2e4ebe70 DJ |
5869 | internal_error (__FILE__, __LINE__, |
5870 | "unknown ABI in switch"); | |
c2d11a7d JM |
5871 | } |
5872 | ||
a5ea2558 AC |
5873 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5874 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5875 | comment: | |
5876 | ||
5877 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5878 | flag in object files because to do so would make it impossible to | |
102182a9 | 5879 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5880 | unnecessarily restrictive. |
361d1df0 | 5881 | |
a5ea2558 AC |
5882 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5883 | but to set this flag before gcc is built with such multilibs will | |
5884 | break too many systems.'' | |
5885 | ||
5886 | But even more unhelpfully, the default linker output target for | |
5887 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5888 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5889 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5890 | this flag to detect 32-bit mode would do the wrong thing given |
5891 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5892 | as 32-bit programs by default. */ |
a5ea2558 | 5893 | |
c2d11a7d JM |
5894 | /* enable/disable the MIPS FPU */ |
5895 | if (!mips_fpu_type_auto) | |
5896 | tdep->mips_fpu_type = mips_fpu_type; | |
5897 | else if (info.bfd_arch_info != NULL | |
5898 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5899 | switch (info.bfd_arch_info->mach) | |
5900 | { | |
b0069a17 | 5901 | case bfd_mach_mips3900: |
c2d11a7d | 5902 | case bfd_mach_mips4100: |
ed9a39eb | 5903 | case bfd_mach_mips4111: |
c2d11a7d JM |
5904 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5905 | break; | |
bf64bfd6 AC |
5906 | case bfd_mach_mips4650: |
5907 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5908 | break; | |
c2d11a7d JM |
5909 | default: |
5910 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5911 | break; | |
5912 | } | |
5913 | else | |
5914 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5915 | ||
5916 | /* MIPS version of register names. NOTE: At present the MIPS | |
5917 | register name management is part way between the old - | |
5918 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
102182a9 | 5919 | Further work on it is required. */ |
18f81521 MS |
5920 | /* NOTE: many targets (esp. embedded) do not go thru the |
5921 | gdbarch_register_name vector at all, instead bypassing it | |
5922 | by defining REGISTER_NAMES. */ | |
c2d11a7d | 5923 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6c997a34 | 5924 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 5925 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
a094c6fb | 5926 | set_gdbarch_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 5927 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d JM |
5928 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); |
5929 | ||
102182a9 MS |
5930 | /* Add/remove bits from an address. The MIPS needs be careful to |
5931 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5932 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5933 | ||
10312cc4 AC |
5934 | /* There's a mess in stack frame creation. See comments in |
5935 | blockframe.c near reference to INIT_FRAME_PC_FIRST. */ | |
5936 | set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
7824d2f2 | 5937 | set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 5938 | |
102182a9 | 5939 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d AC |
5940 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
5941 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); | |
5942 | ||
c2d11a7d JM |
5943 | /* Initialize a frame */ |
5944 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
d28e01f4 | 5945 | set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs); |
c2d11a7d JM |
5946 | |
5947 | /* MIPS version of CALL_DUMMY */ | |
5948 | ||
5949 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
5950 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
5951 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
5952 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
5953 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
f7ab6ec6 MS |
5954 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); |
5955 | set_gdbarch_push_dummy_frame (gdbarch, mips_push_dummy_frame); | |
5956 | set_gdbarch_pop_frame (gdbarch, mips_pop_frame); | |
c2d11a7d JM |
5957 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
5958 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
5959 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
5960 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
f7ab6ec6 | 5961 | set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy); |
c2d11a7d JM |
5962 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
5963 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
5964 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
5965 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
bf1f5b4c | 5966 | set_gdbarch_register_convertible (gdbarch, mips_register_convertible); |
d05285fa MS |
5967 | set_gdbarch_register_convert_to_virtual (gdbarch, |
5968 | mips_register_convert_to_virtual); | |
5969 | set_gdbarch_register_convert_to_raw (gdbarch, | |
5970 | mips_register_convert_to_raw); | |
5971 | ||
b9a8e3bf | 5972 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 5973 | |
b5d1566e | 5974 | set_gdbarch_frame_chain (gdbarch, mips_frame_chain); |
c4093a6a | 5975 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
b5d1566e MS |
5976 | set_gdbarch_frameless_function_invocation (gdbarch, |
5977 | generic_frameless_function_invocation_not); | |
5978 | set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc); | |
5979 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); | |
5980 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
5981 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
5982 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
5983 | ||
47a8d4ba | 5984 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 5985 | |
f7b9e9fc AC |
5986 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5987 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
5988 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
5989 | |
5990 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
5991 | set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); | |
5992 | ||
fc0c74b1 AC |
5993 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5994 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5995 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5996 | |
102182a9 MS |
5997 | set_gdbarch_function_start_offset (gdbarch, 0); |
5998 | ||
32a6503c KB |
5999 | /* There are MIPS targets which do not yet use this since they still |
6000 | define REGISTER_VIRTUAL_TYPE. */ | |
78fde5f8 | 6001 | set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type); |
102182a9 | 6002 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
78fde5f8 | 6003 | |
bf1f5b4c | 6004 | set_gdbarch_do_registers_info (gdbarch, mips_do_registers_info); |
102182a9 | 6005 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6006 | |
70f80edf JT |
6007 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
6008 | gdbarch_init_osabi (info, gdbarch, osabi); | |
6009 | ||
2f1488ce MS |
6010 | set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return); |
6011 | set_gdbarch_extract_struct_value_address (gdbarch, | |
6012 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6013 | |
6014 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6015 | ||
6016 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6017 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6018 | |
4b9b3959 AC |
6019 | return gdbarch; |
6020 | } | |
6021 | ||
2e4ebe70 DJ |
6022 | static void |
6023 | mips_abi_update (char *ignore_args, int from_tty, | |
6024 | struct cmd_list_element *c) | |
6025 | { | |
6026 | struct gdbarch_info info; | |
6027 | ||
6028 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6029 | mips_gdbarch_init will take care of the rest. */ | |
6030 | gdbarch_info_init (&info); | |
6031 | gdbarch_update_p (info); | |
6032 | } | |
6033 | ||
4b9b3959 AC |
6034 | static void |
6035 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6036 | { | |
6037 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6038 | if (tdep != NULL) | |
c2d11a7d | 6039 | { |
acdb74a0 AC |
6040 | int ef_mips_arch; |
6041 | int ef_mips_32bitmode; | |
6042 | /* determine the ISA */ | |
6043 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6044 | { | |
6045 | case E_MIPS_ARCH_1: | |
6046 | ef_mips_arch = 1; | |
6047 | break; | |
6048 | case E_MIPS_ARCH_2: | |
6049 | ef_mips_arch = 2; | |
6050 | break; | |
6051 | case E_MIPS_ARCH_3: | |
6052 | ef_mips_arch = 3; | |
6053 | break; | |
6054 | case E_MIPS_ARCH_4: | |
93d56215 | 6055 | ef_mips_arch = 4; |
acdb74a0 AC |
6056 | break; |
6057 | default: | |
93d56215 | 6058 | ef_mips_arch = 0; |
acdb74a0 AC |
6059 | break; |
6060 | } | |
6061 | /* determine the size of a pointer */ | |
6062 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6063 | fprintf_unfiltered (file, |
6064 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6065 | tdep->elf_flags); |
4b9b3959 | 6066 | fprintf_unfiltered (file, |
acdb74a0 AC |
6067 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6068 | ef_mips_32bitmode); | |
6069 | fprintf_unfiltered (file, | |
6070 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6071 | ef_mips_arch); | |
6072 | fprintf_unfiltered (file, | |
6073 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6074 | tdep->mips_abi, | |
2e4ebe70 | 6075 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6076 | fprintf_unfiltered (file, |
6077 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6078 | mips_mask_address_p (), | |
6079 | tdep->default_mask_address_p); | |
c2d11a7d | 6080 | } |
4b9b3959 AC |
6081 | fprintf_unfiltered (file, |
6082 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6083 | FP_REGISTER_DOUBLE); | |
6084 | fprintf_unfiltered (file, | |
6085 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6086 | MIPS_DEFAULT_FPU_TYPE, | |
6087 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6088 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6089 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6090 | : "???")); | |
6091 | fprintf_unfiltered (file, | |
6092 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6093 | MIPS_EABI); | |
6094 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6095 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
6096 | MIPS_LAST_FP_ARG_REGNUM, | |
6097 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
6098 | fprintf_unfiltered (file, |
6099 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6100 | MIPS_FPU_TYPE, | |
6101 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6102 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6103 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6104 | : "???")); | |
6105 | fprintf_unfiltered (file, | |
6106 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6107 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6108 | fprintf_unfiltered (file, |
6109 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6110 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6111 | fprintf_unfiltered (file, |
6112 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6113 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6114 | fprintf_unfiltered (file, | |
6115 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6116 | MIPS_STACK_ARGSIZE); | |
6117 | fprintf_unfiltered (file, | |
6118 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
6119 | MIPS_REGSIZE); | |
2475bac3 AC |
6120 | fprintf_unfiltered (file, |
6121 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6122 | A0_REGNUM); | |
6123 | fprintf_unfiltered (file, | |
6124 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6125 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6126 | fprintf_unfiltered (file, | |
6127 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6128 | XSTRING (ATTACH_DETACH)); | |
6129 | fprintf_unfiltered (file, | |
6130 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
6131 | BADVADDR_REGNUM); | |
6132 | fprintf_unfiltered (file, | |
6133 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
6134 | fprintf_unfiltered (file, | |
6135 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
6136 | CAUSE_REGNUM); | |
6137 | fprintf_unfiltered (file, | |
6138 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
6139 | CPLUS_MARKER); | |
2475bac3 AC |
6140 | fprintf_unfiltered (file, |
6141 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
6142 | XSTRING (DO_REGISTERS_INFO)); | |
6143 | fprintf_unfiltered (file, | |
6144 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6145 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6146 | fprintf_unfiltered (file, | |
6147 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6148 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6149 | fprintf_unfiltered (file, |
6150 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
6151 | FCRCS_REGNUM); | |
6152 | fprintf_unfiltered (file, | |
6153 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
6154 | FCRIR_REGNUM); | |
6155 | fprintf_unfiltered (file, | |
6156 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6157 | FIRST_EMBED_REGNUM); | |
6158 | fprintf_unfiltered (file, | |
6159 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
6160 | FPA0_REGNUM); | |
6161 | fprintf_unfiltered (file, | |
6162 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
6163 | GDB_TARGET_IS_MIPS64); | |
6164 | fprintf_unfiltered (file, | |
6165 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
6166 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
6167 | fprintf_unfiltered (file, | |
6168 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
6169 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
6170 | fprintf_unfiltered (file, | |
6171 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
6172 | GEN_REG_SAVE_MASK); | |
6173 | fprintf_unfiltered (file, | |
6174 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
6175 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
6176 | fprintf_unfiltered (file, | |
6177 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
6178 | HI_REGNUM); | |
6179 | fprintf_unfiltered (file, | |
6180 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
6181 | fprintf_unfiltered (file, | |
6182 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
6183 | fprintf_unfiltered (file, | |
6184 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6185 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6186 | fprintf_unfiltered (file, |
6187 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6188 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6189 | fprintf_unfiltered (file, | |
6190 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6191 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
6192 | fprintf_unfiltered (file, | |
6193 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
6194 | fprintf_unfiltered (file, | |
6195 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6196 | LAST_EMBED_REGNUM); | |
6197 | fprintf_unfiltered (file, | |
6198 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
6199 | fprintf_unfiltered (file, | |
6200 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
6201 | LO_REGNUM); | |
6202 | #ifdef MACHINE_CPROC_FP_OFFSET | |
6203 | fprintf_unfiltered (file, | |
6204 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6205 | MACHINE_CPROC_FP_OFFSET); | |
6206 | #endif | |
6207 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6208 | fprintf_unfiltered (file, | |
6209 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6210 | MACHINE_CPROC_PC_OFFSET); | |
6211 | #endif | |
6212 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6213 | fprintf_unfiltered (file, | |
6214 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6215 | MACHINE_CPROC_SP_OFFSET); | |
6216 | #endif | |
6217 | fprintf_unfiltered (file, | |
6218 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
6219 | fprintf_unfiltered (file, | |
6220 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
6221 | fprintf_unfiltered (file, | |
6222 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6223 | MIPS16_INSTLEN); | |
6224 | fprintf_unfiltered (file, | |
6225 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
6226 | fprintf_unfiltered (file, | |
6227 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6228 | fprintf_unfiltered (file, | |
6229 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6230 | fprintf_unfiltered (file, | |
6231 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6232 | MIPS_INSTLEN); | |
6233 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6234 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6235 | MIPS_LAST_ARG_REGNUM, | |
6236 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6237 | fprintf_unfiltered (file, |
6238 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6239 | MIPS_NUMREGS); | |
6240 | fprintf_unfiltered (file, | |
6241 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
6242 | fprintf_unfiltered (file, | |
6243 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6244 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6245 | fprintf_unfiltered (file, |
6246 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
6247 | fprintf_unfiltered (file, | |
6248 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
6249 | fprintf_unfiltered (file, | |
6250 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
6251 | fprintf_unfiltered (file, | |
6252 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
6253 | fprintf_unfiltered (file, | |
6254 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6255 | PRID_REGNUM); | |
6256 | fprintf_unfiltered (file, | |
6257 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
6258 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
6259 | fprintf_unfiltered (file, | |
6260 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6261 | fprintf_unfiltered (file, | |
6262 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6263 | fprintf_unfiltered (file, | |
6264 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6265 | fprintf_unfiltered (file, | |
6266 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6267 | fprintf_unfiltered (file, | |
6268 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6269 | fprintf_unfiltered (file, | |
6270 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6271 | fprintf_unfiltered (file, | |
6272 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6273 | fprintf_unfiltered (file, | |
6274 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6275 | fprintf_unfiltered (file, | |
6276 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6277 | fprintf_unfiltered (file, | |
6278 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6279 | fprintf_unfiltered (file, | |
6280 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6281 | fprintf_unfiltered (file, | |
6282 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6283 | fprintf_unfiltered (file, | |
6284 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6285 | PS_REGNUM); | |
6286 | fprintf_unfiltered (file, | |
6287 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
6288 | PUSH_FP_REGNUM); | |
6289 | fprintf_unfiltered (file, | |
6290 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6291 | RA_REGNUM); | |
6292 | fprintf_unfiltered (file, | |
6293 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
6294 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6295 | fprintf_unfiltered (file, | |
6296 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
6297 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6298 | fprintf_unfiltered (file, | |
6299 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
6300 | fprintf_unfiltered (file, | |
6301 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
6302 | fprintf_unfiltered (file, | |
6303 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
6304 | #ifdef SAVED_BYTES | |
6305 | fprintf_unfiltered (file, | |
6306 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6307 | SAVED_BYTES); | |
6308 | #endif | |
6309 | #ifdef SAVED_FP | |
6310 | fprintf_unfiltered (file, | |
6311 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6312 | SAVED_FP); | |
6313 | #endif | |
6314 | #ifdef SAVED_PC | |
6315 | fprintf_unfiltered (file, | |
6316 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6317 | SAVED_PC); | |
6318 | #endif | |
6319 | fprintf_unfiltered (file, | |
6320 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6321 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6322 | fprintf_unfiltered (file, | |
6323 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6324 | fprintf_unfiltered (file, | |
6325 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6326 | SIGFRAME_BASE); | |
6327 | fprintf_unfiltered (file, | |
6328 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6329 | SIGFRAME_FPREGSAVE_OFF); | |
6330 | fprintf_unfiltered (file, | |
6331 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6332 | SIGFRAME_PC_OFF); | |
6333 | fprintf_unfiltered (file, | |
6334 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6335 | SIGFRAME_REGSAVE_OFF); | |
6336 | fprintf_unfiltered (file, | |
6337 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
6338 | SIGFRAME_REG_SIZE); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6341 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6342 | fprintf_unfiltered (file, | |
6343 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6344 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6345 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6346 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6347 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6348 | fprintf_unfiltered (file, |
6349 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6350 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6351 | #ifdef STACK_END_ADDR | |
6352 | fprintf_unfiltered (file, | |
6353 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6354 | STACK_END_ADDR); | |
6355 | #endif | |
6356 | fprintf_unfiltered (file, | |
6357 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6358 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6359 | fprintf_unfiltered (file, | |
6360 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6361 | STEP_SKIPS_DELAY_P); | |
6362 | fprintf_unfiltered (file, | |
6363 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6364 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6365 | fprintf_unfiltered (file, | |
6366 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6367 | T9_REGNUM); | |
6368 | fprintf_unfiltered (file, | |
6369 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6370 | fprintf_unfiltered (file, | |
6371 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6372 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6373 | fprintf_unfiltered (file, | |
6374 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6375 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
6376 | fprintf_unfiltered (file, | |
6377 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
6378 | fprintf_unfiltered (file, | |
6379 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
6380 | XSTRING (TM_PRINT_INSN_MACH)); | |
6381 | #ifdef TRACE_CLEAR | |
6382 | fprintf_unfiltered (file, | |
6383 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6384 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6385 | #endif | |
6386 | #ifdef TRACE_FLAVOR | |
6387 | fprintf_unfiltered (file, | |
6388 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6389 | TRACE_FLAVOR); | |
6390 | #endif | |
6391 | #ifdef TRACE_FLAVOR_SIZE | |
6392 | fprintf_unfiltered (file, | |
6393 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6394 | TRACE_FLAVOR_SIZE); | |
6395 | #endif | |
6396 | #ifdef TRACE_SET | |
6397 | fprintf_unfiltered (file, | |
6398 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6399 | XSTRING (TRACE_SET (X,STATE))); | |
6400 | #endif | |
6401 | fprintf_unfiltered (file, | |
6402 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
6403 | #ifdef UNUSED_REGNUM | |
6404 | fprintf_unfiltered (file, | |
6405 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6406 | UNUSED_REGNUM); | |
6407 | #endif | |
6408 | fprintf_unfiltered (file, | |
6409 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6410 | V0_REGNUM); | |
6411 | fprintf_unfiltered (file, | |
6412 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6413 | (long) VM_MIN_ADDRESS); | |
6414 | #ifdef VX_NUM_REGS | |
6415 | fprintf_unfiltered (file, | |
6416 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
6417 | VX_NUM_REGS); | |
6418 | #endif | |
6419 | fprintf_unfiltered (file, | |
6420 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6421 | ZERO_REGNUM); | |
6422 | fprintf_unfiltered (file, | |
6423 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6424 | _PROC_MAGIC_); | |
70f80edf JT |
6425 | |
6426 | fprintf_unfiltered (file, | |
6427 | "mips_dump_tdep: OS ABI = %s\n", | |
6428 | gdbarch_osabi_name (tdep->osabi)); | |
c2d11a7d JM |
6429 | } |
6430 | ||
c906108c | 6431 | void |
acdb74a0 | 6432 | _initialize_mips_tdep (void) |
c906108c SS |
6433 | { |
6434 | static struct cmd_list_element *mipsfpulist = NULL; | |
6435 | struct cmd_list_element *c; | |
6436 | ||
2e4ebe70 DJ |
6437 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6438 | if (MIPS_ABI_LAST + 1 | |
6439 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6440 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6441 | ||
4b9b3959 | 6442 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 6443 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
6444 | tm_print_insn = gdb_print_insn_mips; |
6445 | ||
a5ea2558 AC |
6446 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6447 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6448 | "Various MIPS specific commands.", | |
6449 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6450 | ||
6451 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6452 | "Various MIPS specific commands.", | |
6453 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6454 | ||
6455 | /* Allow the user to override the saved register size. */ | |
6456 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6457 | class_obscure, |
6458 | size_enums, | |
6459 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6460 | Set size of general purpose registers saved on the stack.\n\ |
6461 | This option can be set to one of:\n\ | |
6462 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6463 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6464 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6465 | saved GP register size from information contained in the executable.\n\ | |
6466 | (default: auto)", | |
1ed2a135 | 6467 | &setmipscmdlist), |
a5ea2558 AC |
6468 | &showmipscmdlist); |
6469 | ||
d929b26f AC |
6470 | /* Allow the user to override the argument stack size. */ |
6471 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6472 | class_obscure, | |
6473 | size_enums, | |
1ed2a135 | 6474 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6475 | Set the amount of stack space reserved for each argument.\n\ |
6476 | This option can be set to one of:\n\ | |
6477 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6478 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6479 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6480 | target and executable (default)", | |
6481 | &setmipscmdlist), | |
6482 | &showmipscmdlist); | |
6483 | ||
2e4ebe70 DJ |
6484 | /* Allow the user to override the ABI. */ |
6485 | c = add_set_enum_cmd | |
6486 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6487 | "Set the ABI used by this program.\n" | |
6488 | "This option can be set to one of:\n" | |
6489 | " auto - the default ABI associated with the current binary\n" | |
6490 | " o32\n" | |
6491 | " o64\n" | |
6492 | " n32\n" | |
f3a7b3a5 | 6493 | " n64\n" |
2e4ebe70 DJ |
6494 | " eabi32\n" |
6495 | " eabi64", | |
6496 | &setmipscmdlist); | |
6497 | add_show_from_set (c, &showmipscmdlist); | |
6498 | set_cmd_sfunc (c, mips_abi_update); | |
6499 | ||
c906108c SS |
6500 | /* Let the user turn off floating point and set the fence post for |
6501 | heuristic_proc_start. */ | |
6502 | ||
6503 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6504 | "Set use of MIPS floating-point coprocessor.", | |
6505 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6506 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6507 | "Select single-precision MIPS floating-point coprocessor.", | |
6508 | &mipsfpulist); | |
6509 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6510 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6511 | &mipsfpulist); |
6512 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6513 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6514 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6515 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6516 | "Select no MIPS floating-point coprocessor.", | |
6517 | &mipsfpulist); | |
6518 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6519 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6520 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6521 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6522 | "Select MIPS floating-point coprocessor automatically.", | |
6523 | &mipsfpulist); | |
6524 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6525 | "Show current use of MIPS floating-point coprocessor target.", | |
6526 | &showlist); | |
6527 | ||
c906108c SS |
6528 | /* We really would like to have both "0" and "unlimited" work, but |
6529 | command.c doesn't deal with that. So make it a var_zinteger | |
6530 | because the user can always use "999999" or some such for unlimited. */ | |
6531 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6532 | (char *) &heuristic_fence_post, | |
6533 | "\ | |
6534 | Set the distance searched for the start of a function.\n\ | |
6535 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6536 | program for the start of a function. This command sets the distance of the\n\ | |
6537 | search. The only need to set it is when debugging a stripped executable.", | |
6538 | &setlist); | |
6539 | /* We need to throw away the frame cache when we set this, since it | |
6540 | might change our ability to get backtraces. */ | |
9f60d481 | 6541 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6542 | add_show_from_set (c, &showlist); |
6543 | ||
6544 | /* Allow the user to control whether the upper bits of 64-bit | |
6545 | addresses should be zeroed. */ | |
e9e68a56 AC |
6546 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6547 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6548 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6549 | allow GDB to determine the correct value.\n", "\ | |
6550 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6551 | NULL, show_mask_address, | |
6552 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6553 | |
6554 | /* Allow the user to control the size of 32 bit registers within the | |
6555 | raw remote packet. */ | |
6556 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
6557 | class_obscure, | |
6558 | var_boolean, | |
6559 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
6560 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
6561 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6562 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6563 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
6564 | &setlist), | |
6565 | &showlist); | |
9ace0497 AC |
6566 | |
6567 | /* Debug this files internals. */ | |
6568 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6569 | &mips_debug, "Set mips debugging.\n\ | |
6570 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6571 | &showdebuglist); | |
c906108c | 6572 | } |