Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
b6ba6518 KB |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001 Free Software Foundation, Inc. | |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
c906108c SS |
41 | |
42 | #include "opcode/mips.h" | |
c2d11a7d JM |
43 | #include "elf/mips.h" |
44 | #include "elf-bfd.h" | |
2475bac3 | 45 | #include "symcat.h" |
c906108c | 46 | |
b0069a17 AC |
47 | /* The sizes of floating point registers. */ |
48 | ||
49 | enum | |
50 | { | |
51 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
52 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
53 | }; | |
54 | ||
0dadbba0 AC |
55 | /* All the possible MIPS ABIs. */ |
56 | ||
57 | enum mips_abi | |
58 | { | |
59 | MIPS_ABI_UNKNOWN, | |
60 | MIPS_ABI_N32, | |
61 | MIPS_ABI_O32, | |
62 | MIPS_ABI_O64, | |
63 | MIPS_ABI_EABI32, | |
64 | MIPS_ABI_EABI64 | |
65 | }; | |
66 | ||
cce74817 | 67 | struct frame_extra_info |
c5aa993b JM |
68 | { |
69 | mips_extra_func_info_t proc_desc; | |
70 | int num_args; | |
71 | }; | |
cce74817 | 72 | |
d929b26f AC |
73 | /* Various MIPS ISA options (related to stack analysis) can be |
74 | overridden dynamically. Establish an enum/array for managing | |
75 | them. */ | |
76 | ||
53904c9e AC |
77 | static const char size_auto[] = "auto"; |
78 | static const char size_32[] = "32"; | |
79 | static const char size_64[] = "64"; | |
d929b26f | 80 | |
53904c9e | 81 | static const char *size_enums[] = { |
d929b26f AC |
82 | size_auto, |
83 | size_32, | |
84 | size_64, | |
a5ea2558 AC |
85 | 0 |
86 | }; | |
87 | ||
7a292a7a SS |
88 | /* Some MIPS boards don't support floating point while others only |
89 | support single-precision floating-point operations. See also | |
90 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
91 | |
92 | enum mips_fpu_type | |
c5aa993b JM |
93 | { |
94 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
95 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
96 | MIPS_FPU_NONE /* No floating point. */ | |
97 | }; | |
c906108c SS |
98 | |
99 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
100 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
101 | #endif | |
102 | static int mips_fpu_type_auto = 1; | |
103 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
104 | #define MIPS_FPU_TYPE mips_fpu_type | |
105 | ||
c906108c | 106 | /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */ |
7a292a7a | 107 | #ifndef FP_REGISTER_DOUBLE |
c906108c | 108 | #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8) |
7a292a7a SS |
109 | #endif |
110 | ||
9ace0497 | 111 | static int mips_debug = 0; |
7a292a7a | 112 | |
c2d11a7d JM |
113 | /* MIPS specific per-architecture information */ |
114 | struct gdbarch_tdep | |
115 | { | |
116 | /* from the elf header */ | |
117 | int elf_flags; | |
118 | /* mips options */ | |
0dadbba0 | 119 | enum mips_abi mips_abi; |
acdb74a0 | 120 | const char *mips_abi_string; |
c2d11a7d JM |
121 | enum mips_fpu_type mips_fpu_type; |
122 | int mips_last_arg_regnum; | |
123 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 124 | int mips_default_saved_regsize; |
c2d11a7d | 125 | int mips_fp_register_double; |
d929b26f AC |
126 | int mips_regs_have_home_p; |
127 | int mips_default_stack_argsize; | |
5213ab06 | 128 | int gdb_target_is_mips64; |
4014092b | 129 | int default_mask_address_p; |
c2d11a7d JM |
130 | }; |
131 | ||
132 | #if GDB_MULTI_ARCH | |
133 | #undef MIPS_EABI | |
0dadbba0 | 134 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 135 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d JM |
136 | #endif |
137 | ||
138 | #if GDB_MULTI_ARCH | |
139 | #undef MIPS_LAST_FP_ARG_REGNUM | |
140 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) | |
141 | #endif | |
142 | ||
143 | #if GDB_MULTI_ARCH | |
144 | #undef MIPS_LAST_ARG_REGNUM | |
145 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) | |
146 | #endif | |
147 | ||
148 | #if GDB_MULTI_ARCH | |
149 | #undef MIPS_FPU_TYPE | |
150 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) | |
151 | #endif | |
152 | ||
d929b26f AC |
153 | /* Return the currently configured (or set) saved register size. */ |
154 | ||
c2d11a7d | 155 | #if GDB_MULTI_ARCH |
a5ea2558 AC |
156 | #undef MIPS_DEFAULT_SAVED_REGSIZE |
157 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) | |
d929b26f AC |
158 | #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE) |
159 | #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE | |
c2d11a7d JM |
160 | #endif |
161 | ||
53904c9e | 162 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
163 | |
164 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
165 | ||
166 | static unsigned int | |
acdb74a0 | 167 | mips_saved_regsize (void) |
d929b26f AC |
168 | { |
169 | if (mips_saved_regsize_string == size_auto) | |
170 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
171 | else if (mips_saved_regsize_string == size_64) | |
172 | return 8; | |
173 | else /* if (mips_saved_regsize_string == size_32) */ | |
174 | return 4; | |
175 | } | |
176 | ||
c2d11a7d JM |
177 | /* Indicate that the ABI makes use of double-precision registers |
178 | provided by the FPU (rather than combining pairs of registers to | |
179 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
180 | determine if the ABI is using double-precision registers. See also | |
181 | MIPS_FPU_TYPE. */ | |
182 | #if GDB_MULTI_ARCH | |
183 | #undef FP_REGISTER_DOUBLE | |
184 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) | |
185 | #endif | |
186 | ||
d929b26f AC |
187 | /* Does the caller allocate a ``home'' for each register used in the |
188 | function call? The N32 ABI and MIPS_EABI do not, the others do. */ | |
189 | ||
190 | #if GDB_MULTI_ARCH | |
191 | #undef MIPS_REGS_HAVE_HOME_P | |
192 | #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p) | |
193 | #elif !defined (MIPS_REGS_HAVE_HOME_P) | |
194 | #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI) | |
195 | #endif | |
196 | ||
197 | /* The amount of space reserved on the stack for registers. This is | |
198 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
199 | data allocated after the registers have run out. */ | |
200 | ||
201 | #if GDB_MULTI_ARCH | |
202 | #undef MIPS_DEFAULT_STACK_ARGSIZE | |
0dadbba0 | 203 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
204 | #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE) |
205 | #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE) | |
206 | #endif | |
207 | ||
208 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
209 | ||
53904c9e | 210 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
211 | |
212 | static unsigned int | |
213 | mips_stack_argsize (void) | |
214 | { | |
215 | if (mips_stack_argsize_string == size_auto) | |
216 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
217 | else if (mips_stack_argsize_string == size_64) | |
218 | return 8; | |
219 | else /* if (mips_stack_argsize_string == size_32) */ | |
220 | return 4; | |
221 | } | |
222 | ||
5213ab06 AC |
223 | #if GDB_MULTI_ARCH |
224 | #undef GDB_TARGET_IS_MIPS64 | |
225 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) | |
226 | #endif | |
c2d11a7d | 227 | |
92e1c15c FF |
228 | #if GDB_MULTI_ARCH |
229 | #undef MIPS_DEFAULT_MASK_ADDRESS_P | |
230 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) | |
231 | #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P) | |
232 | #define MIPS_DEFAULT_MASK_ADDRESS_P (0) | |
233 | #endif | |
234 | ||
7a292a7a | 235 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 236 | |
a14ed312 | 237 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 238 | |
a14ed312 | 239 | static void mips_print_register (int, int); |
c906108c SS |
240 | |
241 | static mips_extra_func_info_t | |
479412cd | 242 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int); |
c906108c | 243 | |
a14ed312 | 244 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 245 | |
a14ed312 | 246 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 247 | |
a14ed312 | 248 | int mips_set_processor_type (char *); |
c906108c | 249 | |
a14ed312 | 250 | static void mips_show_processor_type_command (char *, int); |
c906108c | 251 | |
a14ed312 | 252 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
253 | |
254 | static mips_extra_func_info_t | |
479412cd | 255 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame); |
c906108c | 256 | |
a14ed312 KB |
257 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
258 | mips_extra_func_info_t proc_desc); | |
c906108c SS |
259 | |
260 | /* This value is the model of MIPS in use. It is derived from the value | |
261 | of the PrID register. */ | |
262 | ||
263 | char *mips_processor_type; | |
264 | ||
265 | char *tmp_mips_processor_type; | |
266 | ||
acdb74a0 AC |
267 | /* The list of available "set mips " and "show mips " commands */ |
268 | ||
269 | static struct cmd_list_element *setmipscmdlist = NULL; | |
270 | static struct cmd_list_element *showmipscmdlist = NULL; | |
271 | ||
c906108c SS |
272 | /* A set of original names, to be used when restoring back to generic |
273 | registers from a specific set. */ | |
274 | ||
cce74817 JM |
275 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
276 | char **mips_processor_reg_names = mips_generic_reg_names; | |
277 | ||
278 | char * | |
fba45db2 | 279 | mips_register_name (int i) |
cce74817 JM |
280 | { |
281 | return mips_processor_reg_names[i]; | |
282 | } | |
9846de1b | 283 | /* *INDENT-OFF* */ |
c906108c SS |
284 | /* Names of IDT R3041 registers. */ |
285 | ||
286 | char *mips_r3041_reg_names[] = { | |
287 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
288 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
289 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
290 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
291 | "sr", "lo", "hi", "bad", "cause","pc", | |
292 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
293 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
294 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
295 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
296 | "fsr", "fir", "fp", "", | |
297 | "", "", "bus", "ccfg", "", "", "", "", | |
298 | "", "", "port", "cmp", "", "", "epc", "prid", | |
299 | }; | |
300 | ||
301 | /* Names of IDT R3051 registers. */ | |
302 | ||
303 | char *mips_r3051_reg_names[] = { | |
304 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
305 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
306 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
307 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
308 | "sr", "lo", "hi", "bad", "cause","pc", | |
309 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
310 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
311 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
312 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
313 | "fsr", "fir", "fp", "", | |
314 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
315 | "", "", "ehi", "", "", "", "epc", "prid", | |
316 | }; | |
317 | ||
318 | /* Names of IDT R3081 registers. */ | |
319 | ||
320 | char *mips_r3081_reg_names[] = { | |
321 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
322 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
323 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
324 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
325 | "sr", "lo", "hi", "bad", "cause","pc", | |
326 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
327 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
328 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
329 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
330 | "fsr", "fir", "fp", "", | |
331 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
332 | "", "", "ehi", "", "", "", "epc", "prid", | |
333 | }; | |
334 | ||
335 | /* Names of LSI 33k registers. */ | |
336 | ||
337 | char *mips_lsi33k_reg_names[] = { | |
338 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
339 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
340 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
341 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
342 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
343 | "dcic", "bpc", "bda", "", "", "", "", "", | |
344 | "", "", "", "", "", "", "", "", | |
345 | "", "", "", "", "", "", "", "", | |
346 | "", "", "", "", "", "", "", "", | |
347 | "", "", "", "", | |
348 | "", "", "", "", "", "", "", "", | |
349 | "", "", "", "", "", "", "", "", | |
350 | }; | |
351 | ||
352 | struct { | |
353 | char *name; | |
354 | char **regnames; | |
355 | } mips_processor_type_table[] = { | |
356 | { "generic", mips_generic_reg_names }, | |
357 | { "r3041", mips_r3041_reg_names }, | |
358 | { "r3051", mips_r3051_reg_names }, | |
359 | { "r3071", mips_r3081_reg_names }, | |
360 | { "r3081", mips_r3081_reg_names }, | |
361 | { "lsi33k", mips_lsi33k_reg_names }, | |
362 | { NULL, NULL } | |
363 | }; | |
9846de1b | 364 | /* *INDENT-ON* */ |
c906108c | 365 | |
c5aa993b JM |
366 | |
367 | ||
368 | ||
c906108c | 369 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
370 | static int mips16_to_32_reg[8] = |
371 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
372 | |
373 | /* Heuristic_proc_start may hunt through the text section for a long | |
374 | time across a 2400 baud serial line. Allows the user to limit this | |
375 | search. */ | |
376 | ||
377 | static unsigned int heuristic_fence_post = 0; | |
378 | ||
c5aa993b JM |
379 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
380 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
381 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
382 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
383 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
384 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
385 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
386 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
387 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
388 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
389 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
390 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
391 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
392 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
393 | ||
394 | struct linked_proc_info | |
c5aa993b JM |
395 | { |
396 | struct mips_extra_func_info info; | |
397 | struct linked_proc_info *next; | |
398 | } | |
399 | *linked_proc_desc_table = NULL; | |
c906108c | 400 | |
cce74817 | 401 | void |
acdb74a0 | 402 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
403 | { |
404 | if (fi | |
405 | && fi->extra_info | |
406 | && fi->extra_info->proc_desc | |
407 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 408 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 409 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 410 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 411 | } |
c906108c | 412 | |
43e526b9 JM |
413 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
414 | defines the remote-gdb packet. */ | |
415 | ||
416 | static int mips64_transfers_32bit_regs_p = 0; | |
417 | ||
418 | int | |
acdb74a0 | 419 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
420 | { |
421 | if (mips64_transfers_32bit_regs_p) | |
422 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
423 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
424 | && FP_REGISTER_DOUBLE) | |
425 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
426 | registers. */ | |
427 | return 8; | |
43e526b9 JM |
428 | else |
429 | return MIPS_REGSIZE; | |
430 | } | |
431 | ||
432 | int | |
acdb74a0 | 433 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
434 | { |
435 | if (mips64_transfers_32bit_regs_p) | |
436 | return 0; | |
437 | else | |
438 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
439 | } | |
440 | ||
441 | void | |
acdb74a0 AC |
442 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
443 | char *raw_buf, char *virt_buf) | |
43e526b9 JM |
444 | { |
445 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
446 | memcpy (virt_buf, | |
447 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
448 | TYPE_LENGTH (virtual_type)); | |
449 | else | |
450 | memcpy (virt_buf, | |
451 | raw_buf, | |
452 | TYPE_LENGTH (virtual_type)); | |
453 | } | |
454 | ||
455 | void | |
acdb74a0 AC |
456 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
457 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
458 | { |
459 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
460 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
461 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
462 | virt_buf, | |
463 | TYPE_LENGTH (virtual_type)); | |
464 | else | |
465 | memcpy (raw_buf, | |
466 | virt_buf, | |
467 | TYPE_LENGTH (virtual_type)); | |
468 | } | |
469 | ||
c906108c | 470 | /* Should the upper word of 64-bit addresses be zeroed? */ |
4014092b AC |
471 | enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO; |
472 | ||
473 | static int | |
474 | mips_mask_address_p (void) | |
475 | { | |
476 | switch (mask_address_var) | |
477 | { | |
478 | case CMD_AUTO_BOOLEAN_TRUE: | |
479 | return 1; | |
480 | case CMD_AUTO_BOOLEAN_FALSE: | |
481 | return 0; | |
482 | break; | |
483 | case CMD_AUTO_BOOLEAN_AUTO: | |
92e1c15c | 484 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 485 | default: |
8e65ff28 AC |
486 | internal_error (__FILE__, __LINE__, |
487 | "mips_mask_address_p: bad switch"); | |
4014092b AC |
488 | return -1; |
489 | } | |
490 | } | |
491 | ||
492 | static void | |
493 | show_mask_address (char *cmd, int from_tty) | |
494 | { | |
495 | switch (mask_address_var) | |
496 | { | |
497 | case CMD_AUTO_BOOLEAN_TRUE: | |
498 | printf_filtered ("The 32 bit mips address mask is enabled\n"); | |
499 | break; | |
500 | case CMD_AUTO_BOOLEAN_FALSE: | |
501 | printf_filtered ("The 32 bit mips address mask is disabled\n"); | |
502 | break; | |
503 | case CMD_AUTO_BOOLEAN_AUTO: | |
504 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", | |
505 | mips_mask_address_p () ? "enabled" : "disabled"); | |
506 | break; | |
507 | default: | |
8e65ff28 AC |
508 | internal_error (__FILE__, __LINE__, |
509 | "show_mask_address: bad switch"); | |
4014092b AC |
510 | break; |
511 | } | |
512 | } | |
c906108c SS |
513 | |
514 | /* Should call_function allocate stack space for a struct return? */ | |
515 | int | |
fba45db2 | 516 | mips_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
517 | { |
518 | if (MIPS_EABI) | |
7a292a7a | 519 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
c906108c | 520 | else |
c5aa993b | 521 | return 1; /* Structures are returned by ref in extra arg0 */ |
c906108c SS |
522 | } |
523 | ||
524 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ | |
525 | ||
526 | static int | |
527 | pc_is_mips16 (bfd_vma memaddr) | |
528 | { | |
529 | struct minimal_symbol *sym; | |
530 | ||
531 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
532 | if (IS_MIPS16_ADDR (memaddr)) | |
533 | return 1; | |
534 | ||
535 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
536 | the high bit of the info field. Use this to decide if the function is | |
537 | MIPS16 or normal MIPS. */ | |
538 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
539 | if (sym) | |
540 | return MSYMBOL_IS_SPECIAL (sym); | |
541 | else | |
542 | return 0; | |
543 | } | |
544 | ||
6c997a34 AC |
545 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
546 | all registers should be sign extended for simplicity? */ | |
547 | ||
548 | static CORE_ADDR | |
39f77062 | 549 | mips_read_pc (ptid_t ptid) |
6c997a34 | 550 | { |
39f77062 | 551 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 552 | } |
c906108c SS |
553 | |
554 | /* This returns the PC of the first inst after the prologue. If we can't | |
555 | find the prologue, then return 0. */ | |
556 | ||
557 | static CORE_ADDR | |
acdb74a0 AC |
558 | after_prologue (CORE_ADDR pc, |
559 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
560 | { |
561 | struct symtab_and_line sal; | |
562 | CORE_ADDR func_addr, func_end; | |
563 | ||
479412cd DJ |
564 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
565 | to read the stack pointer from the current machine state, because | |
566 | the current machine state has nothing to do with the information | |
567 | we need from the proc_desc; and the process may or may not exist | |
568 | right now. */ | |
c906108c | 569 | if (!proc_desc) |
479412cd | 570 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
571 | |
572 | if (proc_desc) | |
573 | { | |
574 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 575 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
576 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
577 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
578 | return 0; | |
579 | } | |
580 | ||
581 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
582 | return 0; /* Unknown */ | |
583 | ||
584 | sal = find_pc_line (func_addr, 0); | |
585 | ||
586 | if (sal.end < func_end) | |
587 | return sal.end; | |
588 | ||
589 | /* The line after the prologue is after the end of the function. In this | |
590 | case, tell the caller to find the prologue the hard way. */ | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
596 | set the appropriate bit in the general register mask or float register mask | |
597 | to indicate which register is saved. This is a helper function | |
598 | for mips_find_saved_regs. */ | |
599 | ||
600 | static void | |
acdb74a0 AC |
601 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
602 | unsigned long *float_mask) | |
c906108c SS |
603 | { |
604 | int reg; | |
605 | ||
606 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
607 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
608 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
609 | { | |
610 | /* It might be possible to use the instruction to | |
c5aa993b JM |
611 | find the offset, rather than the code below which |
612 | is based on things being in a certain order in the | |
613 | frame, but figuring out what the instruction's offset | |
614 | is relative to might be a little tricky. */ | |
c906108c SS |
615 | reg = (inst & 0x001f0000) >> 16; |
616 | *gen_mask |= (1 << reg); | |
617 | } | |
618 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
619 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
620 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
621 | |
622 | { | |
623 | reg = ((inst & 0x001f0000) >> 16); | |
624 | *float_mask |= (1 << reg); | |
625 | } | |
626 | } | |
627 | ||
628 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
629 | set the appropriate bit in the general register or float register mask | |
630 | to indicate which register is saved. This is a helper function | |
631 | for mips_find_saved_regs. */ | |
632 | ||
633 | static void | |
acdb74a0 | 634 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 635 | { |
c5aa993b | 636 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
637 | { |
638 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
639 | *gen_mask |= (1 << reg); | |
640 | } | |
c5aa993b | 641 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
642 | { |
643 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
644 | *gen_mask |= (1 << reg); | |
645 | } | |
c5aa993b | 646 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
647 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
648 | *gen_mask |= (1 << RA_REGNUM); | |
649 | } | |
650 | ||
651 | ||
652 | /* Fetch and return instruction from the specified location. If the PC | |
653 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
654 | ||
655 | static t_inst | |
acdb74a0 | 656 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
657 | { |
658 | char buf[MIPS_INSTLEN]; | |
659 | int instlen; | |
660 | int status; | |
661 | ||
662 | if (pc_is_mips16 (addr)) | |
663 | { | |
664 | instlen = MIPS16_INSTLEN; | |
665 | addr = UNMAKE_MIPS16_ADDR (addr); | |
666 | } | |
667 | else | |
c5aa993b | 668 | instlen = MIPS_INSTLEN; |
c906108c SS |
669 | status = read_memory_nobpt (addr, buf, instlen); |
670 | if (status) | |
671 | memory_error (status, addr); | |
672 | return extract_unsigned_integer (buf, instlen); | |
673 | } | |
674 | ||
675 | ||
676 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
677 | #define mips32_op(x) (x >> 26) |
678 | #define itype_op(x) (x >> 26) | |
679 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 680 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 681 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 682 | |
e135b889 DJ |
683 | #define jtype_op(x) (x >> 26) |
684 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 685 | |
e135b889 DJ |
686 | #define rtype_op(x) (x >> 26) |
687 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
688 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
689 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
690 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
691 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
692 | |
693 | static CORE_ADDR | |
c5aa993b JM |
694 | mips32_relative_offset (unsigned long inst) |
695 | { | |
696 | long x; | |
697 | x = itype_immediate (inst); | |
698 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 699 | { |
c5aa993b | 700 | x |= 0xffff0000; /* sign extension */ |
c906108c | 701 | } |
c5aa993b JM |
702 | x = x << 2; |
703 | return x; | |
c906108c SS |
704 | } |
705 | ||
706 | /* Determine whate to set a single step breakpoint while considering | |
707 | branch prediction */ | |
708 | CORE_ADDR | |
c5aa993b JM |
709 | mips32_next_pc (CORE_ADDR pc) |
710 | { | |
711 | unsigned long inst; | |
712 | int op; | |
713 | inst = mips_fetch_instruction (pc); | |
e135b889 | 714 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 715 | { |
e135b889 DJ |
716 | if (itype_op (inst) >> 2 == 5) |
717 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 718 | { |
e135b889 | 719 | op = (itype_op (inst) & 0x03); |
c906108c SS |
720 | switch (op) |
721 | { | |
e135b889 DJ |
722 | case 0: /* BEQL */ |
723 | goto equal_branch; | |
724 | case 1: /* BNEL */ | |
725 | goto neq_branch; | |
726 | case 2: /* BLEZL */ | |
727 | goto less_branch; | |
728 | case 3: /* BGTZ */ | |
729 | goto greater_branch; | |
c5aa993b JM |
730 | default: |
731 | pc += 4; | |
c906108c SS |
732 | } |
733 | } | |
e135b889 DJ |
734 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
735 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
736 | { | |
737 | int tf = itype_rt (inst) & 0x01; | |
738 | int cnum = itype_rt (inst) >> 2; | |
739 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
740 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
741 | ||
742 | if (((cond >> cnum) & 0x01) == tf) | |
743 | pc += mips32_relative_offset (inst) + 4; | |
744 | else | |
745 | pc += 8; | |
746 | } | |
c5aa993b JM |
747 | else |
748 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
749 | } |
750 | else | |
c5aa993b JM |
751 | { /* This gets way messy */ |
752 | ||
c906108c | 753 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 754 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 755 | { |
c5aa993b JM |
756 | case 0: /* SPECIAL */ |
757 | op = rtype_funct (inst); | |
758 | switch (op) | |
759 | { | |
760 | case 8: /* JR */ | |
761 | case 9: /* JALR */ | |
6c997a34 AC |
762 | /* Set PC to that address */ |
763 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
764 | break; |
765 | default: | |
766 | pc += 4; | |
767 | } | |
768 | ||
e135b889 | 769 | break; /* end SPECIAL */ |
c5aa993b | 770 | case 1: /* REGIMM */ |
c906108c | 771 | { |
e135b889 DJ |
772 | op = itype_rt (inst); /* branch condition */ |
773 | switch (op) | |
c906108c | 774 | { |
c5aa993b | 775 | case 0: /* BLTZ */ |
e135b889 DJ |
776 | case 2: /* BLTZL */ |
777 | case 16: /* BLTZAL */ | |
c5aa993b | 778 | case 18: /* BLTZALL */ |
c906108c | 779 | less_branch: |
6c997a34 | 780 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
781 | pc += mips32_relative_offset (inst) + 4; |
782 | else | |
783 | pc += 8; /* after the delay slot */ | |
784 | break; | |
e135b889 | 785 | case 1: /* BGEZ */ |
c5aa993b JM |
786 | case 3: /* BGEZL */ |
787 | case 17: /* BGEZAL */ | |
788 | case 19: /* BGEZALL */ | |
c906108c | 789 | greater_equal_branch: |
6c997a34 | 790 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
791 | pc += mips32_relative_offset (inst) + 4; |
792 | else | |
793 | pc += 8; /* after the delay slot */ | |
794 | break; | |
e135b889 | 795 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
796 | default: |
797 | pc += 4; | |
c906108c SS |
798 | } |
799 | } | |
e135b889 | 800 | break; /* end REGIMM */ |
c5aa993b JM |
801 | case 2: /* J */ |
802 | case 3: /* JAL */ | |
803 | { | |
804 | unsigned long reg; | |
805 | reg = jtype_target (inst) << 2; | |
e135b889 | 806 | /* Upper four bits get never changed... */ |
c5aa993b | 807 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 808 | } |
c5aa993b JM |
809 | break; |
810 | /* FIXME case JALX : */ | |
811 | { | |
812 | unsigned long reg; | |
813 | reg = jtype_target (inst) << 2; | |
814 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
815 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
816 | } | |
c5aa993b | 817 | break; /* The new PC will be alternate mode */ |
e135b889 | 818 | case 4: /* BEQ, BEQL */ |
c5aa993b | 819 | equal_branch: |
6c997a34 AC |
820 | if (read_signed_register (itype_rs (inst)) == |
821 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
822 | pc += mips32_relative_offset (inst) + 4; |
823 | else | |
824 | pc += 8; | |
825 | break; | |
e135b889 | 826 | case 5: /* BNE, BNEL */ |
c5aa993b | 827 | neq_branch: |
6c997a34 | 828 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 829 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
830 | pc += mips32_relative_offset (inst) + 4; |
831 | else | |
832 | pc += 8; | |
833 | break; | |
e135b889 | 834 | case 6: /* BLEZ, BLEZL */ |
c906108c | 835 | less_zero_branch: |
6c997a34 | 836 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
837 | pc += mips32_relative_offset (inst) + 4; |
838 | else | |
839 | pc += 8; | |
840 | break; | |
841 | case 7: | |
e135b889 DJ |
842 | default: |
843 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 844 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
845 | pc += mips32_relative_offset (inst) + 4; |
846 | else | |
847 | pc += 8; | |
848 | break; | |
c5aa993b JM |
849 | } /* switch */ |
850 | } /* else */ | |
851 | return pc; | |
852 | } /* mips32_next_pc */ | |
c906108c SS |
853 | |
854 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 855 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
856 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
857 | We dont want to set a single step instruction on the extend instruction | |
858 | either. | |
c5aa993b | 859 | */ |
c906108c SS |
860 | |
861 | /* Lots of mips16 instruction formats */ | |
862 | /* Predicting jumps requires itype,ritype,i8type | |
863 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 864 | */ |
c906108c SS |
865 | enum mips16_inst_fmts |
866 | { | |
c5aa993b JM |
867 | itype, /* 0 immediate 5,10 */ |
868 | ritype, /* 1 5,3,8 */ | |
869 | rrtype, /* 2 5,3,3,5 */ | |
870 | rritype, /* 3 5,3,3,5 */ | |
871 | rrrtype, /* 4 5,3,3,3,2 */ | |
872 | rriatype, /* 5 5,3,3,1,4 */ | |
873 | shifttype, /* 6 5,3,3,3,2 */ | |
874 | i8type, /* 7 5,3,8 */ | |
875 | i8movtype, /* 8 5,3,3,5 */ | |
876 | i8mov32rtype, /* 9 5,3,5,3 */ | |
877 | i64type, /* 10 5,3,8 */ | |
878 | ri64type, /* 11 5,3,3,5 */ | |
879 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
880 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
881 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
882 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
883 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
884 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
885 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
886 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
887 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
888 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
889 | }; | |
12f02c2a AC |
890 | /* I am heaping all the fields of the formats into one structure and |
891 | then, only the fields which are involved in instruction extension */ | |
c906108c | 892 | struct upk_mips16 |
c5aa993b | 893 | { |
12f02c2a | 894 | CORE_ADDR offset; |
c5aa993b JM |
895 | unsigned int regx; /* Function in i8 type */ |
896 | unsigned int regy; | |
897 | }; | |
c906108c SS |
898 | |
899 | ||
12f02c2a AC |
900 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
901 | for the bits which make up the immediatate extension. */ | |
c906108c | 902 | |
12f02c2a AC |
903 | static CORE_ADDR |
904 | extended_offset (unsigned int extension) | |
c906108c | 905 | { |
12f02c2a | 906 | CORE_ADDR value; |
c5aa993b JM |
907 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
908 | value = value << 6; | |
909 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
910 | value = value << 5; | |
911 | value |= extension & 0x01f; /* extract 4:0 */ | |
912 | return value; | |
c906108c SS |
913 | } |
914 | ||
915 | /* Only call this function if you know that this is an extendable | |
916 | instruction, It wont malfunction, but why make excess remote memory references? | |
917 | If the immediate operands get sign extended or somthing, do it after | |
918 | the extension is performed. | |
c5aa993b | 919 | */ |
c906108c SS |
920 | /* FIXME: Every one of these cases needs to worry about sign extension |
921 | when the offset is to be used in relative addressing */ | |
922 | ||
923 | ||
12f02c2a | 924 | static unsigned int |
c5aa993b | 925 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 926 | { |
c5aa993b JM |
927 | char buf[8]; |
928 | pc &= 0xfffffffe; /* clear the low order bit */ | |
929 | target_read_memory (pc, buf, 2); | |
930 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
931 | } |
932 | ||
933 | static void | |
c5aa993b | 934 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
935 | unsigned int extension, |
936 | unsigned int inst, | |
937 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 938 | struct upk_mips16 *upk) |
c906108c | 939 | { |
12f02c2a AC |
940 | CORE_ADDR offset; |
941 | int regx; | |
942 | int regy; | |
943 | switch (insn_format) | |
c906108c | 944 | { |
c5aa993b | 945 | case itype: |
c906108c | 946 | { |
12f02c2a AC |
947 | CORE_ADDR value; |
948 | if (extension) | |
c5aa993b JM |
949 | { |
950 | value = extended_offset (extension); | |
951 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 952 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
953 | } |
954 | else | |
c5aa993b | 955 | { |
12f02c2a | 956 | value = inst & 0x7ff; |
c5aa993b | 957 | /* FIXME : Consider sign extension */ |
c906108c | 958 | } |
12f02c2a AC |
959 | offset = value; |
960 | regx = -1; | |
961 | regy = -1; | |
c906108c | 962 | } |
c5aa993b JM |
963 | break; |
964 | case ritype: | |
965 | case i8type: | |
966 | { /* A register identifier and an offset */ | |
c906108c SS |
967 | /* Most of the fields are the same as I type but the |
968 | immediate value is of a different length */ | |
12f02c2a AC |
969 | CORE_ADDR value; |
970 | if (extension) | |
c906108c | 971 | { |
c5aa993b JM |
972 | value = extended_offset (extension); |
973 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
974 | value |= inst & 0xff; /* eleven bits from instruction */ |
975 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
976 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
977 | { | |
978 | value &= ~0x3fff; /* remove the sign bit */ | |
979 | value = -value; | |
c906108c SS |
980 | } |
981 | } | |
c5aa993b JM |
982 | else |
983 | { | |
12f02c2a AC |
984 | value = inst & 0xff; /* 8 bits */ |
985 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
986 | /* FIXME: Do sign extension , this format needs it */ |
987 | if (value & 0x80) /* THIS CONFUSES ME */ | |
988 | { | |
989 | value &= 0xef; /* remove the sign bit */ | |
990 | value = -value; | |
991 | } | |
c5aa993b | 992 | } |
12f02c2a AC |
993 | offset = value; |
994 | regy = -1; | |
c5aa993b | 995 | break; |
c906108c | 996 | } |
c5aa993b | 997 | case jalxtype: |
c906108c | 998 | { |
c5aa993b | 999 | unsigned long value; |
12f02c2a AC |
1000 | unsigned int nexthalf; |
1001 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1002 | value = value << 16; |
1003 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1004 | value |= nexthalf; | |
12f02c2a AC |
1005 | offset = value; |
1006 | regx = -1; | |
1007 | regy = -1; | |
c5aa993b | 1008 | break; |
c906108c SS |
1009 | } |
1010 | default: | |
8e65ff28 AC |
1011 | internal_error (__FILE__, __LINE__, |
1012 | "bad switch"); | |
c906108c | 1013 | } |
12f02c2a AC |
1014 | upk->offset = offset; |
1015 | upk->regx = regx; | |
1016 | upk->regy = regy; | |
c906108c SS |
1017 | } |
1018 | ||
1019 | ||
c5aa993b JM |
1020 | static CORE_ADDR |
1021 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1022 | { |
c5aa993b JM |
1023 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
1024 | ||
c906108c SS |
1025 | } |
1026 | ||
12f02c2a AC |
1027 | static CORE_ADDR |
1028 | extended_mips16_next_pc (CORE_ADDR pc, | |
1029 | unsigned int extension, | |
1030 | unsigned int insn) | |
c906108c | 1031 | { |
12f02c2a AC |
1032 | int op = (insn >> 11); |
1033 | switch (op) | |
c906108c | 1034 | { |
12f02c2a AC |
1035 | case 2: /* Branch */ |
1036 | { | |
1037 | CORE_ADDR offset; | |
1038 | struct upk_mips16 upk; | |
1039 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1040 | offset = upk.offset; | |
1041 | if (offset & 0x800) | |
1042 | { | |
1043 | offset &= 0xeff; | |
1044 | offset = -offset; | |
1045 | } | |
1046 | pc += (offset << 1) + 2; | |
1047 | break; | |
1048 | } | |
1049 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1050 | { | |
1051 | struct upk_mips16 upk; | |
1052 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1053 | pc = add_offset_16 (pc, upk.offset); | |
1054 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1055 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1056 | else | |
1057 | pc |= 0x01; | |
1058 | break; | |
1059 | } | |
1060 | case 4: /* beqz */ | |
1061 | { | |
1062 | struct upk_mips16 upk; | |
1063 | int reg; | |
1064 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1065 | reg = read_signed_register (upk.regx); | |
1066 | if (reg == 0) | |
1067 | pc += (upk.offset << 1) + 2; | |
1068 | else | |
1069 | pc += 2; | |
1070 | break; | |
1071 | } | |
1072 | case 5: /* bnez */ | |
1073 | { | |
1074 | struct upk_mips16 upk; | |
1075 | int reg; | |
1076 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1077 | reg = read_signed_register (upk.regx); | |
1078 | if (reg != 0) | |
1079 | pc += (upk.offset << 1) + 2; | |
1080 | else | |
1081 | pc += 2; | |
1082 | break; | |
1083 | } | |
1084 | case 12: /* I8 Formats btez btnez */ | |
1085 | { | |
1086 | struct upk_mips16 upk; | |
1087 | int reg; | |
1088 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1089 | /* upk.regx contains the opcode */ | |
1090 | reg = read_signed_register (24); /* Test register is 24 */ | |
1091 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1092 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1093 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1094 | pc += (upk.offset << 1) + 2; | |
1095 | else | |
1096 | pc += 2; | |
1097 | break; | |
1098 | } | |
1099 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1100 | { | |
1101 | struct upk_mips16 upk; | |
1102 | /* upk.fmt = rrtype; */ | |
1103 | op = insn & 0x1f; | |
1104 | if (op == 0) | |
c5aa993b | 1105 | { |
12f02c2a AC |
1106 | int reg; |
1107 | upk.regx = (insn >> 8) & 0x07; | |
1108 | upk.regy = (insn >> 5) & 0x07; | |
1109 | switch (upk.regy) | |
c5aa993b | 1110 | { |
12f02c2a AC |
1111 | case 0: |
1112 | reg = upk.regx; | |
1113 | break; | |
1114 | case 1: | |
1115 | reg = 31; | |
1116 | break; /* Function return instruction */ | |
1117 | case 2: | |
1118 | reg = upk.regx; | |
1119 | break; | |
1120 | default: | |
1121 | reg = 31; | |
1122 | break; /* BOGUS Guess */ | |
c906108c | 1123 | } |
12f02c2a | 1124 | pc = read_signed_register (reg); |
c906108c | 1125 | } |
12f02c2a | 1126 | else |
c5aa993b | 1127 | pc += 2; |
12f02c2a AC |
1128 | break; |
1129 | } | |
1130 | case 30: | |
1131 | /* This is an instruction extension. Fetch the real instruction | |
1132 | (which follows the extension) and decode things based on | |
1133 | that. */ | |
1134 | { | |
1135 | pc += 2; | |
1136 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1137 | break; | |
1138 | } | |
1139 | default: | |
1140 | { | |
1141 | pc += 2; | |
1142 | break; | |
1143 | } | |
c906108c | 1144 | } |
c5aa993b | 1145 | return pc; |
12f02c2a | 1146 | } |
c906108c | 1147 | |
12f02c2a AC |
1148 | CORE_ADDR |
1149 | mips16_next_pc (CORE_ADDR pc) | |
1150 | { | |
1151 | unsigned int insn = fetch_mips_16 (pc); | |
1152 | return extended_mips16_next_pc (pc, 0, insn); | |
1153 | } | |
1154 | ||
1155 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1156 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1157 | It works by decoding the current instruction and predicting where a |
1158 | branch will go. This isnt hard because all the data is available. | |
1159 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1160 | CORE_ADDR |
1161 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1162 | { |
c5aa993b JM |
1163 | if (pc & 0x01) |
1164 | return mips16_next_pc (pc); | |
1165 | else | |
1166 | return mips32_next_pc (pc); | |
12f02c2a | 1167 | } |
c906108c SS |
1168 | |
1169 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
1170 | NULL). */ | |
1171 | ||
1172 | void | |
acdb74a0 | 1173 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1174 | { |
1175 | int ireg; | |
1176 | CORE_ADDR reg_position; | |
1177 | /* r0 bit means kernel trap */ | |
1178 | int kernel_trap; | |
1179 | /* What registers have been saved? Bitmasks. */ | |
1180 | unsigned long gen_mask, float_mask; | |
1181 | mips_extra_func_info_t proc_desc; | |
1182 | t_inst inst; | |
1183 | ||
1184 | frame_saved_regs_zalloc (fci); | |
1185 | ||
1186 | /* If it is the frame for sigtramp, the saved registers are located | |
1187 | in a sigcontext structure somewhere on the stack. | |
1188 | If the stack layout for sigtramp changes we might have to change these | |
1189 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1190 | #ifndef SIGFRAME_BASE | |
1191 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1192 | above the sigtramp frame. */ | |
1193 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1194 | /* FIXME! Are these correct?? */ | |
1195 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1196 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1197 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1198 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1199 | #endif | |
1200 | #ifndef SIGFRAME_REG_SIZE | |
1201 | /* FIXME! Is this correct?? */ | |
1202 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1203 | #endif | |
1204 | if (fci->signal_handler_caller) | |
1205 | { | |
1206 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1207 | { | |
c5aa993b JM |
1208 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1209 | + ireg * SIGFRAME_REG_SIZE; | |
1210 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1211 | } |
1212 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1213 | { | |
c5aa993b JM |
1214 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1215 | + ireg * SIGFRAME_REG_SIZE; | |
1216 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1217 | } |
1218 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1219 | return; | |
1220 | } | |
1221 | ||
cce74817 | 1222 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1223 | if (proc_desc == NULL) |
1224 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1225 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1226 | and set the saved_regs right away. */ | |
1227 | return; | |
1228 | ||
c5aa993b JM |
1229 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1230 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1231 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1232 | |
c5aa993b JM |
1233 | if ( /* In any frame other than the innermost or a frame interrupted by |
1234 | a signal, we assume that all registers have been saved. | |
1235 | This assumes that all register saves in a function happen before | |
1236 | the first function call. */ | |
1237 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1238 | |
c5aa993b JM |
1239 | /* In a dummy frame we know exactly where things are saved. */ |
1240 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1241 | |
c5aa993b JM |
1242 | /* Don't bother unless we are inside a function prologue. Outside the |
1243 | prologue, we know where everything is. */ | |
c906108c | 1244 | |
c5aa993b | 1245 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1246 | |
c5aa993b JM |
1247 | /* Not sure exactly what kernel_trap means, but if it means |
1248 | the kernel saves the registers without a prologue doing it, | |
1249 | we better not examine the prologue to see whether registers | |
1250 | have been saved yet. */ | |
1251 | && !kernel_trap) | |
c906108c SS |
1252 | { |
1253 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1254 | claims are saved have been saved yet. */ |
c906108c SS |
1255 | |
1256 | CORE_ADDR addr; | |
1257 | ||
1258 | /* Bitmasks; set if we have found a save for the register. */ | |
1259 | unsigned long gen_save_found = 0; | |
1260 | unsigned long float_save_found = 0; | |
1261 | int instlen; | |
1262 | ||
1263 | /* If the address is odd, assume this is MIPS16 code. */ | |
1264 | addr = PROC_LOW_ADDR (proc_desc); | |
1265 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1266 | ||
1267 | /* Scan through this function's instructions preceding the current | |
1268 | PC, and look for those that save registers. */ | |
1269 | while (addr < fci->pc) | |
1270 | { | |
1271 | inst = mips_fetch_instruction (addr); | |
1272 | if (pc_is_mips16 (addr)) | |
1273 | mips16_decode_reg_save (inst, &gen_save_found); | |
1274 | else | |
1275 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1276 | addr += instlen; | |
1277 | } | |
1278 | gen_mask = gen_save_found; | |
1279 | float_mask = float_save_found; | |
1280 | } | |
1281 | ||
1282 | /* Fill in the offsets for the registers which gen_mask says | |
1283 | were saved. */ | |
1284 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1285 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1286 | if (gen_mask & 0x80000000) |
1287 | { | |
1288 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1289 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1290 | } |
1291 | ||
1292 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1293 | of that normally used by gcc. Therefore, we have to fetch the first | |
1294 | instruction of the function, and if it's an entry instruction that | |
1295 | saves $s0 or $s1, correct their saved addresses. */ | |
1296 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1297 | { | |
1298 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1299 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1300 | { |
1301 | int reg; | |
1302 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1303 | |
c906108c SS |
1304 | /* Check if the ra register was pushed on the stack. */ |
1305 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1306 | if (inst & 0x20) | |
7a292a7a | 1307 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1308 | |
1309 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1310 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1311 | { |
1312 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1313 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1314 | } |
1315 | } | |
1316 | } | |
1317 | ||
1318 | /* Fill in the offsets for the registers which float_mask says | |
1319 | were saved. */ | |
1320 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1321 | ||
1322 | /* The freg_offset points to where the first *double* register | |
1323 | is saved. So skip to the high-order word. */ | |
c5aa993b | 1324 | if (!GDB_TARGET_IS_MIPS64) |
7a292a7a | 1325 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1326 | |
1327 | /* Fill in the offsets for the float registers which float_mask says | |
1328 | were saved. */ | |
c5aa993b | 1329 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1330 | if (float_mask & 0x80000000) |
1331 | { | |
c5aa993b | 1332 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1333 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1334 | } |
1335 | ||
1336 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1337 | } | |
1338 | ||
1339 | static CORE_ADDR | |
acdb74a0 | 1340 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c SS |
1341 | { |
1342 | for (; fi; fi = fi->next) | |
1343 | { | |
1344 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1345 | if it is a signal handler frame. */ |
c906108c SS |
1346 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1347 | return fi->frame; | |
1348 | else | |
1349 | { | |
1350 | if (fi->saved_regs == NULL) | |
1351 | mips_find_saved_regs (fi); | |
1352 | if (fi->saved_regs[regno]) | |
2acceee2 | 1353 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1354 | } |
1355 | } | |
6c997a34 | 1356 | return read_signed_register (regno); |
c906108c SS |
1357 | } |
1358 | ||
1359 | /* mips_addr_bits_remove - remove useless address bits */ | |
1360 | ||
875e1767 | 1361 | static CORE_ADDR |
acdb74a0 | 1362 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1363 | { |
5213ab06 AC |
1364 | if (GDB_TARGET_IS_MIPS64) |
1365 | { | |
4014092b | 1366 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1367 | { |
1368 | /* This hack is a work-around for existing boards using | |
1369 | PMON, the simulator, and any other 64-bit targets that | |
1370 | doesn't have true 64-bit addressing. On these targets, | |
1371 | the upper 32 bits of addresses are ignored by the | |
1372 | hardware. Thus, the PC or SP are likely to have been | |
1373 | sign extended to all 1s by instruction sequences that | |
1374 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1375 | code that loads an address is this: |
1376 | lui $r2, <upper 16 bits> | |
1377 | ori $r2, <lower 16 bits> | |
1378 | But the lui sign-extends the value such that the upper 32 | |
1379 | bits may be all 1s. The workaround is simply to mask off | |
1380 | these bits. In the future, gcc may be changed to support | |
1381 | true 64-bit addressing, and this masking will have to be | |
1382 | disabled. */ | |
5213ab06 AC |
1383 | addr &= (CORE_ADDR) 0xffffffff; |
1384 | } | |
1385 | } | |
4014092b | 1386 | else if (mips_mask_address_p ()) |
5213ab06 | 1387 | { |
4014092b AC |
1388 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1389 | masking off bits, instead, the actual target should be asking | |
1390 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1391 | /* Even when GDB is configured for some 32-bit targets |
1392 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1393 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1394 | useless bits from addresses. */ | |
c5aa993b | 1395 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1396 | } |
c906108c SS |
1397 | return addr; |
1398 | } | |
1399 | ||
9022177c DJ |
1400 | /* mips_software_single_step() is called just before we want to resume |
1401 | the inferior, if we want to single-step it but there is no hardware | |
1402 | or kernel single-step support (MIPS on Linux for example). We find | |
1403 | the target of the coming instruction and breakpoint it. | |
1404 | ||
1405 | single_step is also called just after the inferior stops. If we had | |
1406 | set up a simulated single-step, we undo our damage. */ | |
1407 | ||
1408 | void | |
1409 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1410 | { | |
1411 | static CORE_ADDR next_pc; | |
1412 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1413 | static binsn_quantum break_mem; | |
1414 | CORE_ADDR pc; | |
1415 | ||
1416 | if (insert_breakpoints_p) | |
1417 | { | |
1418 | pc = read_register (PC_REGNUM); | |
1419 | next_pc = mips_next_pc (pc); | |
1420 | ||
1421 | target_insert_breakpoint (next_pc, break_mem); | |
1422 | } | |
1423 | else | |
1424 | target_remove_breakpoint (next_pc, break_mem); | |
1425 | } | |
1426 | ||
10312cc4 | 1427 | static void |
acdb74a0 | 1428 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1429 | { |
1430 | CORE_ADDR pc, tmp; | |
1431 | ||
1432 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1433 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
c906108c | 1434 | tmp = mips_skip_stub (pc); |
c5aa993b | 1435 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1436 | } |
1437 | ||
1438 | ||
1439 | CORE_ADDR | |
acdb74a0 | 1440 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1441 | { |
1442 | CORE_ADDR saved_pc; | |
cce74817 | 1443 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1444 | /* We have to get the saved pc from the sigcontext |
1445 | if it is a signal handler frame. */ | |
1446 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1447 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1448 | |
c5aa993b | 1449 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1450 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1451 | else |
7a292a7a | 1452 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1453 | |
1454 | return ADDR_BITS_REMOVE (saved_pc); | |
1455 | } | |
1456 | ||
1457 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1458 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1459 | |
1460 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1461 | has already been set for this register, do nothing; this way we will | |
1462 | only recognize the first save of a given register in a function prologue. | |
1463 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1464 | ||
1465 | static void | |
acdb74a0 | 1466 | set_reg_offset (int regno, CORE_ADDR offset) |
c906108c | 1467 | { |
cce74817 JM |
1468 | if (temp_saved_regs[regno] == 0) |
1469 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1470 | } |
1471 | ||
1472 | ||
1473 | /* Test whether the PC points to the return instruction at the | |
1474 | end of a function. */ | |
1475 | ||
c5aa993b | 1476 | static int |
acdb74a0 | 1477 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1478 | { |
1479 | if (pc_is_mips16 (pc)) | |
1480 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1481 | generates a "jr $ra"; other times it generates code to load | |
1482 | the return address from the stack to an accessible register (such | |
1483 | as $a3), then a "jr" using that register. This second case | |
1484 | is almost impossible to distinguish from an indirect jump | |
1485 | used for switch statements, so we don't even try. */ | |
1486 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1487 | else | |
1488 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1489 | } | |
1490 | ||
1491 | ||
1492 | /* This fencepost looks highly suspicious to me. Removing it also | |
1493 | seems suspicious as it could affect remote debugging across serial | |
1494 | lines. */ | |
1495 | ||
1496 | static CORE_ADDR | |
acdb74a0 | 1497 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1498 | { |
c5aa993b JM |
1499 | CORE_ADDR start_pc; |
1500 | CORE_ADDR fence; | |
1501 | int instlen; | |
1502 | int seen_adjsp = 0; | |
c906108c | 1503 | |
c5aa993b JM |
1504 | pc = ADDR_BITS_REMOVE (pc); |
1505 | start_pc = pc; | |
1506 | fence = start_pc - heuristic_fence_post; | |
1507 | if (start_pc == 0) | |
1508 | return 0; | |
c906108c | 1509 | |
c5aa993b JM |
1510 | if (heuristic_fence_post == UINT_MAX |
1511 | || fence < VM_MIN_ADDRESS) | |
1512 | fence = VM_MIN_ADDRESS; | |
c906108c | 1513 | |
c5aa993b | 1514 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1515 | |
c5aa993b JM |
1516 | /* search back for previous return */ |
1517 | for (start_pc -= instlen;; start_pc -= instlen) | |
1518 | if (start_pc < fence) | |
1519 | { | |
1520 | /* It's not clear to me why we reach this point when | |
1521 | stop_soon_quietly, but with this test, at least we | |
1522 | don't print out warnings for every child forked (eg, on | |
1523 | decstation). 22apr93 rich@cygnus.com. */ | |
1524 | if (!stop_soon_quietly) | |
c906108c | 1525 | { |
c5aa993b JM |
1526 | static int blurb_printed = 0; |
1527 | ||
1528 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1529 | paddr_nz (pc)); | |
1530 | ||
1531 | if (!blurb_printed) | |
c906108c | 1532 | { |
c5aa993b JM |
1533 | /* This actually happens frequently in embedded |
1534 | development, when you first connect to a board | |
1535 | and your stack pointer and pc are nowhere in | |
1536 | particular. This message needs to give people | |
1537 | in that situation enough information to | |
1538 | determine that it's no big deal. */ | |
1539 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1540 | GDB is unable to find the start of the function at 0x%s\n\ |
1541 | and thus can't determine the size of that function's stack frame.\n\ | |
1542 | This means that GDB may be unable to access that stack frame, or\n\ | |
1543 | the frames below it.\n\ | |
1544 | This problem is most likely caused by an invalid program counter or\n\ | |
1545 | stack pointer.\n\ | |
1546 | However, if you think GDB should simply search farther back\n\ | |
1547 | from 0x%s for code which looks like the beginning of a\n\ | |
1548 | function, you can increase the range of the search using the `set\n\ | |
1549 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1550 | paddr_nz (pc), paddr_nz (pc)); |
1551 | blurb_printed = 1; | |
c906108c | 1552 | } |
c906108c SS |
1553 | } |
1554 | ||
c5aa993b JM |
1555 | return 0; |
1556 | } | |
1557 | else if (pc_is_mips16 (start_pc)) | |
1558 | { | |
1559 | unsigned short inst; | |
1560 | ||
1561 | /* On MIPS16, any one of the following is likely to be the | |
1562 | start of a function: | |
1563 | entry | |
1564 | addiu sp,-n | |
1565 | daddiu sp,-n | |
1566 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1567 | inst = mips_fetch_instruction (start_pc); | |
1568 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1569 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1570 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1571 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1572 | break; | |
1573 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1574 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1575 | seen_adjsp = 1; | |
1576 | else | |
1577 | seen_adjsp = 0; | |
1578 | } | |
1579 | else if (mips_about_to_return (start_pc)) | |
1580 | { | |
1581 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1582 | break; | |
1583 | } | |
1584 | ||
c5aa993b | 1585 | return start_pc; |
c906108c SS |
1586 | } |
1587 | ||
1588 | /* Fetch the immediate value from a MIPS16 instruction. | |
1589 | If the previous instruction was an EXTEND, use it to extend | |
1590 | the upper bits of the immediate value. This is a helper function | |
1591 | for mips16_heuristic_proc_desc. */ | |
1592 | ||
1593 | static int | |
acdb74a0 AC |
1594 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1595 | unsigned short inst, /* current instruction */ | |
1596 | int nbits, /* number of bits in imm field */ | |
1597 | int scale, /* scale factor to be applied to imm */ | |
1598 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1599 | { |
1600 | int offset; | |
1601 | ||
1602 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1603 | { | |
1604 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1605 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1606 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1607 | return offset | (inst & 0x1f); | |
1608 | } | |
1609 | else | |
1610 | { | |
1611 | int max_imm = 1 << nbits; | |
1612 | int mask = max_imm - 1; | |
1613 | int sign_bit = max_imm >> 1; | |
1614 | ||
1615 | offset = inst & mask; | |
1616 | if (is_signed && (offset & sign_bit)) | |
1617 | offset = 0 - (max_imm - offset); | |
1618 | return offset * scale; | |
1619 | } | |
1620 | } | |
1621 | ||
1622 | ||
1623 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1624 | stream from start_pc to limit_pc. */ | |
1625 | ||
1626 | static void | |
acdb74a0 AC |
1627 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1628 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1629 | { |
1630 | CORE_ADDR cur_pc; | |
1631 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1632 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1633 | unsigned inst = 0; /* current instruction */ | |
1634 | unsigned entry_inst = 0; /* the entry instruction */ | |
1635 | int reg, offset; | |
1636 | ||
c5aa993b JM |
1637 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1638 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1639 | |
1640 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1641 | { | |
1642 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1643 | the immediate offset extension from it in mips16_get_imm. */ | |
1644 | prev_inst = inst; | |
1645 | ||
1646 | /* Fetch and decode the instruction. */ | |
1647 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1648 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1649 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1650 | { | |
1651 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1652 | if (offset < 0) /* negative stack adjustment? */ |
1653 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1654 | else |
1655 | /* Exit loop if a positive stack adjustment is found, which | |
1656 | usually means that the stack cleanup code in the function | |
1657 | epilogue is reached. */ | |
1658 | break; | |
1659 | } | |
1660 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1661 | { | |
1662 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1663 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1664 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1665 | set_reg_offset (reg, sp + offset); |
1666 | } | |
1667 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1668 | { | |
1669 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1670 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1671 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1672 | set_reg_offset (reg, sp + offset); |
1673 | } | |
1674 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1675 | { | |
1676 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1677 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1678 | set_reg_offset (RA_REGNUM, sp + offset); |
1679 | } | |
1680 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1681 | { | |
1682 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1683 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1684 | set_reg_offset (RA_REGNUM, sp + offset); |
1685 | } | |
c5aa993b | 1686 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1687 | { |
1688 | frame_addr = sp; | |
1689 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1690 | } | |
1691 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1692 | { | |
1693 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1694 | frame_addr = sp + offset; | |
1695 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1696 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1697 | } | |
1698 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1699 | { | |
1700 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1701 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1702 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1703 | set_reg_offset (reg, frame_addr + offset); |
1704 | } | |
1705 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1706 | { | |
1707 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1708 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1709 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1710 | set_reg_offset (reg, frame_addr + offset); |
1711 | } | |
c5aa993b JM |
1712 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1713 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1714 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1715 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1716 | } |
1717 | ||
c5aa993b JM |
1718 | /* The entry instruction is typically the first instruction in a function, |
1719 | and it stores registers at offsets relative to the value of the old SP | |
1720 | (before the prologue). But the value of the sp parameter to this | |
1721 | function is the new SP (after the prologue has been executed). So we | |
1722 | can't calculate those offsets until we've seen the entire prologue, | |
1723 | and can calculate what the old SP must have been. */ | |
1724 | if (entry_inst != 0) | |
1725 | { | |
1726 | int areg_count = (entry_inst >> 8) & 7; | |
1727 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1728 | |
c5aa993b JM |
1729 | /* The entry instruction always subtracts 32 from the SP. */ |
1730 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1731 | |
c5aa993b JM |
1732 | /* Now we can calculate what the SP must have been at the |
1733 | start of the function prologue. */ | |
1734 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1735 | |
c5aa993b JM |
1736 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1737 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1738 | { | |
1739 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1740 | set_reg_offset (reg, sp + offset); | |
1741 | offset += MIPS_SAVED_REGSIZE; | |
1742 | } | |
c906108c | 1743 | |
c5aa993b JM |
1744 | /* Check if the ra register was pushed on the stack. */ |
1745 | offset = -4; | |
1746 | if (entry_inst & 0x20) | |
1747 | { | |
1748 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1749 | set_reg_offset (RA_REGNUM, sp + offset); | |
1750 | offset -= MIPS_SAVED_REGSIZE; | |
1751 | } | |
c906108c | 1752 | |
c5aa993b JM |
1753 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
1754 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1755 | { | |
1756 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1757 | set_reg_offset (reg, sp + offset); | |
1758 | offset -= MIPS_SAVED_REGSIZE; | |
1759 | } | |
1760 | } | |
c906108c SS |
1761 | } |
1762 | ||
1763 | static void | |
fba45db2 KB |
1764 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1765 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1766 | { |
1767 | CORE_ADDR cur_pc; | |
c5aa993b | 1768 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 1769 | restart: |
cce74817 | 1770 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 1771 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
1772 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
1773 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
1774 | { | |
1775 | unsigned long inst, high_word, low_word; | |
1776 | int reg; | |
1777 | ||
1778 | /* Fetch the instruction. */ | |
1779 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
1780 | ||
1781 | /* Save some code by pre-extracting some useful fields. */ | |
1782 | high_word = (inst >> 16) & 0xffff; | |
1783 | low_word = inst & 0xffff; | |
1784 | reg = high_word & 0x1f; | |
1785 | ||
c5aa993b | 1786 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
1787 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
1788 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1789 | { | |
1790 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 1791 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
1792 | else |
1793 | /* Exit loop if a positive stack adjustment is found, which | |
1794 | usually means that the stack cleanup code in the function | |
1795 | epilogue is reached. */ | |
1796 | break; | |
1797 | } | |
1798 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1799 | { | |
c5aa993b | 1800 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1801 | set_reg_offset (reg, sp + low_word); |
1802 | } | |
1803 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1804 | { | |
1805 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1806 | but the register size used is only 32 bits. Make the address | |
1807 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 1808 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1809 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
1810 | } | |
c5aa993b | 1811 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
1812 | { |
1813 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
1814 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
1815 | frame_addr = sp + low_word; | |
c906108c SS |
1816 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
1817 | { | |
1818 | unsigned alloca_adjust; | |
1819 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1820 | frame_addr = read_next_frame_reg (next_frame, 30); |
1821 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
1822 | if (alloca_adjust > 0) |
1823 | { | |
1824 | /* FP > SP + frame_size. This may be because | |
1825 | * of an alloca or somethings similar. | |
1826 | * Fix sp to "pre-alloca" value, and try again. | |
1827 | */ | |
1828 | sp += alloca_adjust; | |
1829 | goto restart; | |
1830 | } | |
1831 | } | |
1832 | } | |
c5aa993b JM |
1833 | /* move $30,$sp. With different versions of gas this will be either |
1834 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1835 | Accept any one of these. */ | |
c906108c SS |
1836 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
1837 | { | |
1838 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1839 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1840 | { | |
1841 | unsigned alloca_adjust; | |
1842 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1843 | frame_addr = read_next_frame_reg (next_frame, 30); |
1844 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
1845 | if (alloca_adjust > 0) |
1846 | { | |
1847 | /* FP > SP + frame_size. This may be because | |
1848 | * of an alloca or somethings similar. | |
1849 | * Fix sp to "pre-alloca" value, and try again. | |
1850 | */ | |
1851 | sp += alloca_adjust; | |
1852 | goto restart; | |
1853 | } | |
1854 | } | |
1855 | } | |
c5aa993b | 1856 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 1857 | { |
c5aa993b | 1858 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1859 | set_reg_offset (reg, frame_addr + low_word); |
1860 | } | |
1861 | } | |
1862 | } | |
1863 | ||
1864 | static mips_extra_func_info_t | |
acdb74a0 | 1865 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 1866 | struct frame_info *next_frame, int cur_frame) |
c906108c | 1867 | { |
479412cd DJ |
1868 | CORE_ADDR sp; |
1869 | ||
1870 | if (cur_frame) | |
1871 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1872 | else | |
1873 | sp = 0; | |
c906108c | 1874 | |
c5aa993b JM |
1875 | if (start_pc == 0) |
1876 | return NULL; | |
1877 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 1878 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1879 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
1880 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
1881 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
1882 | ||
1883 | if (start_pc + 200 < limit_pc) | |
1884 | limit_pc = start_pc + 200; | |
1885 | if (pc_is_mips16 (start_pc)) | |
1886 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1887 | else | |
1888 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1889 | return &temp_proc_desc; | |
1890 | } | |
1891 | ||
1892 | static mips_extra_func_info_t | |
acdb74a0 | 1893 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
1894 | { |
1895 | CORE_ADDR startaddr; | |
1896 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 1897 | struct block *b = block_for_pc (pc); |
c906108c SS |
1898 | struct symbol *sym; |
1899 | ||
1900 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
1901 | if (addrptr) | |
1902 | *addrptr = startaddr; | |
1903 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) | |
1904 | sym = NULL; | |
1905 | else | |
1906 | { | |
1907 | if (startaddr > BLOCK_START (b)) | |
1908 | /* This is the "pathological" case referred to in a comment in | |
1909 | print_frame_info. It might be better to move this check into | |
1910 | symbol reading. */ | |
1911 | sym = NULL; | |
1912 | else | |
1913 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
1914 | } | |
1915 | ||
1916 | /* If we never found a PDR for this function in symbol reading, then | |
1917 | examine prologues to find the information. */ | |
1918 | if (sym) | |
1919 | { | |
1920 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
1921 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1922 | return NULL; | |
1923 | else | |
1924 | return proc_desc; | |
1925 | } | |
1926 | else | |
1927 | return NULL; | |
1928 | } | |
1929 | ||
1930 | ||
1931 | static mips_extra_func_info_t | |
479412cd | 1932 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
1933 | { |
1934 | mips_extra_func_info_t proc_desc; | |
1935 | CORE_ADDR startaddr; | |
1936 | ||
1937 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1938 | ||
1939 | if (proc_desc) | |
1940 | { | |
1941 | /* IF this is the topmost frame AND | |
1942 | * (this proc does not have debugging information OR | |
1943 | * the PC is in the procedure prologue) | |
1944 | * THEN create a "heuristic" proc_desc (by analyzing | |
1945 | * the actual code) to replace the "official" proc_desc. | |
1946 | */ | |
1947 | if (next_frame == NULL) | |
1948 | { | |
1949 | struct symtab_and_line val; | |
1950 | struct symbol *proc_symbol = | |
c5aa993b | 1951 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
1952 | |
1953 | if (proc_symbol) | |
1954 | { | |
1955 | val = find_pc_line (BLOCK_START | |
c5aa993b | 1956 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
1957 | 0); |
1958 | val.pc = val.end ? val.end : pc; | |
1959 | } | |
1960 | if (!proc_symbol || pc < val.pc) | |
1961 | { | |
1962 | mips_extra_func_info_t found_heuristic = | |
c5aa993b | 1963 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
479412cd | 1964 | pc, next_frame, cur_frame); |
c906108c SS |
1965 | if (found_heuristic) |
1966 | proc_desc = found_heuristic; | |
1967 | } | |
1968 | } | |
1969 | } | |
1970 | else | |
1971 | { | |
1972 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
1973 | by procedure call dummys. However, the procedures being called ought |
1974 | to have their own proc_descs, and even if they don't, | |
1975 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
1976 | |
1977 | register struct linked_proc_info *link; | |
1978 | ||
1979 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
1980 | if (PROC_LOW_ADDR (&link->info) <= pc |
1981 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
1982 | return &link->info; |
1983 | ||
1984 | if (startaddr == 0) | |
1985 | startaddr = heuristic_proc_start (pc); | |
1986 | ||
1987 | proc_desc = | |
479412cd | 1988 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
1989 | } |
1990 | return proc_desc; | |
1991 | } | |
1992 | ||
1993 | static CORE_ADDR | |
acdb74a0 AC |
1994 | get_frame_pointer (struct frame_info *frame, |
1995 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
1996 | { |
1997 | return ADDR_BITS_REMOVE ( | |
c5aa993b JM |
1998 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + |
1999 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2000 | } |
2001 | ||
2002 | mips_extra_func_info_t cached_proc_desc; | |
2003 | ||
2004 | CORE_ADDR | |
acdb74a0 | 2005 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2006 | { |
2007 | mips_extra_func_info_t proc_desc; | |
2008 | CORE_ADDR tmp; | |
c5aa993b | 2009 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
2010 | |
2011 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2012 | return 0; | |
2013 | ||
2014 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2015 | PC of the caller of that stub. */ | |
2016 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
2017 | saved_pc = tmp; | |
2018 | ||
2019 | /* Look up the procedure descriptor for this PC. */ | |
479412cd | 2020 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2021 | if (!proc_desc) |
2022 | return 0; | |
2023 | ||
2024 | cached_proc_desc = proc_desc; | |
2025 | ||
2026 | /* If no frame pointer and frame size is zero, we must be at end | |
2027 | of stack (or otherwise hosed). If we don't check frame size, | |
2028 | we loop forever if we see a zero size frame. */ | |
2029 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2030 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
c5aa993b JM |
2031 | /* The previous frame from a sigtramp frame might be frameless |
2032 | and have frame size zero. */ | |
c906108c SS |
2033 | && !frame->signal_handler_caller) |
2034 | return 0; | |
2035 | else | |
2036 | return get_frame_pointer (frame, proc_desc); | |
2037 | } | |
2038 | ||
2039 | void | |
acdb74a0 | 2040 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2041 | { |
2042 | int regnum; | |
2043 | ||
2044 | /* Use proc_desc calculated in frame_chain */ | |
2045 | mips_extra_func_info_t proc_desc = | |
479412cd | 2046 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1); |
c906108c | 2047 | |
cce74817 JM |
2048 | fci->extra_info = (struct frame_extra_info *) |
2049 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
2050 | ||
c906108c | 2051 | fci->saved_regs = NULL; |
cce74817 | 2052 | fci->extra_info->proc_desc = |
c906108c SS |
2053 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2054 | if (proc_desc) | |
2055 | { | |
2056 | /* Fixup frame-pointer - only needed for top frame */ | |
2057 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2058 | Get the value of the frame relative sp, procedure might have been |
2059 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2060 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2061 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2062 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2063 | else | |
2064 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2065 | ||
2066 | if (proc_desc == &temp_proc_desc) | |
2067 | { | |
2068 | char *name; | |
2069 | ||
2070 | /* Do not set the saved registers for a sigtramp frame, | |
2071 | mips_find_saved_registers will do that for us. | |
2072 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2073 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2074 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
2075 | if (!IN_SIGTRAMP (fci->pc, name)) |
2076 | { | |
c5aa993b | 2077 | frame_saved_regs_zalloc (fci); |
cce74817 | 2078 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2079 | fci->saved_regs[PC_REGNUM] |
2080 | = fci->saved_regs[RA_REGNUM]; | |
2081 | } | |
2082 | } | |
2083 | ||
2084 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2085 | /* assume we can't tell how many args for now */ |
2086 | fci->extra_info->num_args = -1; | |
c906108c SS |
2087 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2088 | { | |
c5aa993b | 2089 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2090 | { |
cce74817 | 2091 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2092 | break; |
2093 | } | |
c5aa993b | 2094 | } |
c906108c SS |
2095 | } |
2096 | } | |
2097 | ||
2098 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2099 | we basically have to look at symbol information for the function | |
2100 | that we stopped in, which tells us *which* register (if any) is | |
2101 | the base of the frame pointer, and what offset from that register | |
2102 | the frame itself is at. | |
2103 | ||
2104 | This presents a problem when trying to examine a stack in memory | |
2105 | (that isn't executing at the moment), using the "frame" command. We | |
2106 | don't have a PC, nor do we have any registers except SP. | |
2107 | ||
2108 | This routine takes two arguments, SP and PC, and tries to make the | |
2109 | cached frames look as if these two arguments defined a frame on the | |
2110 | cache. This allows the rest of info frame to extract the important | |
2111 | arguments without difficulty. */ | |
2112 | ||
2113 | struct frame_info * | |
acdb74a0 | 2114 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2115 | { |
2116 | if (argc != 2) | |
2117 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2118 | ||
2119 | return create_new_frame (argv[0], argv[1]); | |
2120 | } | |
2121 | ||
f09ded24 AC |
2122 | /* According to the current ABI, should the type be passed in a |
2123 | floating-point register (assuming that there is space)? When there | |
2124 | is no FPU, FP are not even considered as possibile candidates for | |
2125 | FP registers and, consequently this returns false - forces FP | |
2126 | arguments into integer registers. */ | |
2127 | ||
2128 | static int | |
2129 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2130 | { | |
2131 | return ((typecode == TYPE_CODE_FLT | |
2132 | || (MIPS_EABI | |
2133 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2134 | && TYPE_NFIELDS (arg_type) == 1 | |
2135 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
2136 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); | |
2137 | } | |
2138 | ||
49e790b0 DJ |
2139 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2140 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2141 | ||
2142 | static int | |
2143 | mips_type_needs_double_align (struct type *type) | |
2144 | { | |
2145 | enum type_code typecode = TYPE_CODE (type); | |
2146 | ||
2147 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) | |
2148 | return 1; | |
2149 | else if (typecode == TYPE_CODE_STRUCT) | |
2150 | { | |
2151 | if (TYPE_NFIELDS (type) < 1) | |
2152 | return 0; | |
2153 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2154 | } | |
2155 | else if (typecode == TYPE_CODE_UNION) | |
2156 | { | |
2157 | int i, n; | |
2158 | ||
2159 | n = TYPE_NFIELDS (type); | |
2160 | for (i = 0; i < n; i++) | |
2161 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2162 | return 1; | |
2163 | return 0; | |
2164 | } | |
2165 | return 0; | |
2166 | } | |
2167 | ||
c906108c | 2168 | CORE_ADDR |
acdb74a0 | 2169 | mips_push_arguments (int nargs, |
ea7c478f | 2170 | struct value **args, |
acdb74a0 AC |
2171 | CORE_ADDR sp, |
2172 | int struct_return, | |
2173 | CORE_ADDR struct_addr) | |
c906108c SS |
2174 | { |
2175 | int argreg; | |
2176 | int float_argreg; | |
2177 | int argnum; | |
2178 | int len = 0; | |
2179 | int stack_offset = 0; | |
2180 | ||
2181 | /* Macros to round N up or down to the next A boundary; A must be | |
2182 | a power of two. */ | |
2183 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2184 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
c5aa993b | 2185 | |
c906108c SS |
2186 | /* First ensure that the stack and structure return address (if any) |
2187 | are properly aligned. The stack has to be at least 64-bit aligned | |
2188 | even on 32-bit machines, because doubles must be 64-bit aligned. | |
2189 | On at least one MIPS variant, stack frames need to be 128-bit | |
2190 | aligned, so we round to this widest known alignment. */ | |
2191 | sp = ROUND_DOWN (sp, 16); | |
cce41527 | 2192 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2193 | |
c906108c SS |
2194 | /* Now make space on the stack for the args. We allocate more |
2195 | than necessary for EABI, because the first few arguments are | |
2196 | passed in registers, but that's OK. */ | |
2197 | for (argnum = 0; argnum < nargs; argnum++) | |
cce41527 | 2198 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE); |
c906108c SS |
2199 | sp -= ROUND_UP (len, 16); |
2200 | ||
9ace0497 AC |
2201 | if (mips_debug) |
2202 | fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n", | |
2203 | (long) sp, ROUND_UP (len, 16)); | |
2204 | ||
c906108c SS |
2205 | /* Initialize the integer and float register pointers. */ |
2206 | argreg = A0_REGNUM; | |
2207 | float_argreg = FPA0_REGNUM; | |
2208 | ||
2209 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
2210 | if (struct_return) | |
9ace0497 AC |
2211 | { |
2212 | if (mips_debug) | |
2213 | fprintf_unfiltered (gdb_stdlog, | |
cce41527 | 2214 | "mips_push_arguments: struct_return reg=%d 0x%lx\n", |
9ace0497 AC |
2215 | argreg, (long) struct_addr); |
2216 | write_register (argreg++, struct_addr); | |
cce41527 AC |
2217 | if (MIPS_REGS_HAVE_HOME_P) |
2218 | stack_offset += MIPS_STACK_ARGSIZE; | |
9ace0497 | 2219 | } |
c906108c SS |
2220 | |
2221 | /* Now load as many as possible of the first arguments into | |
2222 | registers, and push the rest onto the stack. Loop thru args | |
2223 | from first to last. */ | |
2224 | for (argnum = 0; argnum < nargs; argnum++) | |
2225 | { | |
2226 | char *val; | |
2227 | char valbuf[MAX_REGISTER_RAW_SIZE]; | |
ea7c478f | 2228 | struct value *arg = args[argnum]; |
c906108c SS |
2229 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2230 | int len = TYPE_LENGTH (arg_type); | |
2231 | enum type_code typecode = TYPE_CODE (arg_type); | |
2232 | ||
9ace0497 AC |
2233 | if (mips_debug) |
2234 | fprintf_unfiltered (gdb_stdlog, | |
2235 | "mips_push_arguments: %d len=%d type=%d", | |
acdb74a0 | 2236 | argnum + 1, len, (int) typecode); |
9ace0497 | 2237 | |
c906108c | 2238 | /* The EABI passes structures that do not fit in a register by |
c5aa993b | 2239 | reference. In all other cases, pass the structure by value. */ |
9ace0497 AC |
2240 | if (MIPS_EABI |
2241 | && len > MIPS_SAVED_REGSIZE | |
2242 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
c906108c | 2243 | { |
7a292a7a | 2244 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2245 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2246 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2247 | val = valbuf; |
9ace0497 AC |
2248 | if (mips_debug) |
2249 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2250 | } |
2251 | else | |
c5aa993b | 2252 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2253 | |
2254 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2255 | even-numbered floating point register. Round the FP register |
2256 | up before the check to see if there are any FP registers | |
2257 | left. Non MIPS_EABI targets also pass the FP in the integer | |
2258 | registers so also round up normal registers. */ | |
2259 | if (!FP_REGISTER_DOUBLE | |
2260 | && fp_register_arg_p (typecode, arg_type)) | |
2261 | { | |
2262 | if ((float_argreg & 1)) | |
2263 | float_argreg++; | |
2264 | } | |
c906108c SS |
2265 | |
2266 | /* Floating point arguments passed in registers have to be | |
2267 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2268 | are passed in register pairs; the even register gets |
2269 | the low word, and the odd register gets the high word. | |
2270 | On non-EABI processors, the first two floating point arguments are | |
2271 | also copied to general registers, because MIPS16 functions | |
2272 | don't use float registers for arguments. This duplication of | |
2273 | arguments in general registers can't hurt non-MIPS16 functions | |
2274 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2275 | /* MIPS_EABI squeezes a struct that contains a single floating |
2276 | point value into an FP register instead of pushing it onto the | |
9a0149c6 | 2277 | stack. */ |
f09ded24 AC |
2278 | if (fp_register_arg_p (typecode, arg_type) |
2279 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2280 | { |
2281 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2282 | { | |
2283 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
2284 | unsigned long regval; | |
2285 | ||
2286 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2287 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2288 | if (mips_debug) |
acdb74a0 | 2289 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2290 | float_argreg, phex (regval, 4)); |
c906108c SS |
2291 | write_register (float_argreg++, regval); |
2292 | if (!MIPS_EABI) | |
9ace0497 AC |
2293 | { |
2294 | if (mips_debug) | |
acdb74a0 | 2295 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2296 | argreg, phex (regval, 4)); |
2297 | write_register (argreg++, regval); | |
2298 | } | |
c906108c SS |
2299 | |
2300 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2301 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2302 | if (mips_debug) |
acdb74a0 | 2303 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2304 | float_argreg, phex (regval, 4)); |
c906108c SS |
2305 | write_register (float_argreg++, regval); |
2306 | if (!MIPS_EABI) | |
c5aa993b | 2307 | { |
9ace0497 | 2308 | if (mips_debug) |
acdb74a0 | 2309 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2310 | argreg, phex (regval, 4)); |
2311 | write_register (argreg++, regval); | |
c906108c SS |
2312 | } |
2313 | ||
2314 | } | |
2315 | else | |
2316 | { | |
2317 | /* This is a floating point value that fits entirely | |
2318 | in a single register. */ | |
53a5351d JM |
2319 | /* On 32 bit ABI's the float_argreg is further adjusted |
2320 | above to ensure that it is even register aligned. */ | |
9ace0497 AC |
2321 | LONGEST regval = extract_unsigned_integer (val, len); |
2322 | if (mips_debug) | |
acdb74a0 | 2323 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2324 | float_argreg, phex (regval, len)); |
c906108c SS |
2325 | write_register (float_argreg++, regval); |
2326 | if (!MIPS_EABI) | |
c5aa993b | 2327 | { |
53a5351d JM |
2328 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
2329 | registers for each argument. The below is (my | |
2330 | guess) to ensure that the corresponding integer | |
2331 | register has reserved the same space. */ | |
9ace0497 | 2332 | if (mips_debug) |
acdb74a0 | 2333 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2334 | argreg, phex (regval, len)); |
c906108c SS |
2335 | write_register (argreg, regval); |
2336 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
2337 | } | |
2338 | } | |
cce41527 AC |
2339 | /* Reserve space for the FP register. */ |
2340 | if (MIPS_REGS_HAVE_HOME_P) | |
2341 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
c906108c SS |
2342 | } |
2343 | else | |
2344 | { | |
2345 | /* Copy the argument to general registers or the stack in | |
2346 | register-sized pieces. Large arguments are split between | |
2347 | registers and stack. */ | |
2348 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2349 | are treated specially: Irix cc passes them in registers | |
2350 | where gcc sometimes puts them on the stack. For maximum | |
2351 | compatibility, we will put them in both places. */ | |
c5aa993b | 2352 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2353 | (len % MIPS_SAVED_REGSIZE != 0)); |
49e790b0 DJ |
2354 | /* Structures should be aligned to eight bytes (even arg registers) |
2355 | on MIPS_ABI_O32 if their first member has double precision. */ | |
2356 | if (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_O32 | |
2357 | && mips_type_needs_double_align (arg_type)) | |
2358 | { | |
2359 | if ((argreg & 1)) | |
2360 | argreg++; | |
2361 | } | |
f09ded24 AC |
2362 | /* Note: Floating-point values that didn't fit into an FP |
2363 | register are only written to memory. */ | |
c906108c SS |
2364 | while (len > 0) |
2365 | { | |
566f0f7a AC |
2366 | /* Rememer if the argument was written to the stack. */ |
2367 | int stack_used_p = 0; | |
7a292a7a | 2368 | int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; |
c906108c | 2369 | |
acdb74a0 AC |
2370 | if (mips_debug) |
2371 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2372 | partial_len); | |
2373 | ||
566f0f7a | 2374 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2375 | if (argreg > MIPS_LAST_ARG_REGNUM |
2376 | || odd_sized_struct | |
2377 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2378 | { |
c906108c SS |
2379 | /* Should shorter than int integer values be |
2380 | promoted to int before being stored? */ | |
c906108c | 2381 | int longword_offset = 0; |
9ace0497 | 2382 | CORE_ADDR addr; |
566f0f7a | 2383 | stack_used_p = 1; |
c906108c | 2384 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
7a292a7a | 2385 | { |
d929b26f | 2386 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2387 | (typecode == TYPE_CODE_INT || |
2388 | typecode == TYPE_CODE_PTR || | |
2389 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2390 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2391 | else if ((typecode == TYPE_CODE_STRUCT || |
2392 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2393 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2394 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2395 | } |
c5aa993b | 2396 | |
9ace0497 AC |
2397 | if (mips_debug) |
2398 | { | |
acdb74a0 | 2399 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx", |
9ace0497 AC |
2400 | (long) stack_offset); |
2401 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx", | |
2402 | (long) longword_offset); | |
2403 | } | |
2404 | ||
2405 | addr = sp + stack_offset + longword_offset; | |
2406 | ||
2407 | if (mips_debug) | |
2408 | { | |
2409 | int i; | |
2410 | fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr); | |
2411 | for (i = 0; i < partial_len; i++) | |
2412 | { | |
2413 | fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff); | |
2414 | } | |
2415 | } | |
2416 | write_memory (addr, val, partial_len); | |
c906108c SS |
2417 | } |
2418 | ||
f09ded24 AC |
2419 | /* Note!!! This is NOT an else clause. Odd sized |
2420 | structs may go thru BOTH paths. Floating point | |
2421 | arguments will not. */ | |
566f0f7a AC |
2422 | /* Write this portion of the argument to a general |
2423 | purpose register. */ | |
f09ded24 AC |
2424 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2425 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2426 | { |
9ace0497 | 2427 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c SS |
2428 | |
2429 | /* A non-floating-point argument being passed in a | |
2430 | general register. If a struct or union, and if | |
2431 | the remaining length is smaller than the register | |
2432 | size, we have to adjust the register value on | |
2433 | big endian targets. | |
2434 | ||
2435 | It does not seem to be necessary to do the | |
2436 | same for integral types. | |
2437 | ||
2438 | Also don't do this adjustment on EABI and O64 | |
675fb869 AC |
2439 | binaries. |
2440 | ||
2441 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
2442 | outputting LE O32 with sizeof (struct) < | |
2443 | MIPS_SAVED_REGSIZE, generates a left shift as | |
2444 | part of storing the argument in a register a | |
2445 | register (the left shift isn't generated when | |
2446 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
2447 | is quite possible that this is GCC contradicting | |
2448 | the LE/O32 ABI, GDB has not been adjusted to | |
2449 | accommodate this. Either someone needs to | |
2450 | demonstrate that the LE/O32 ABI specifies such a | |
2451 | left shift OR this new ABI gets identified as | |
2452 | such and GDB gets tweaked accordingly. */ | |
c906108c SS |
2453 | |
2454 | if (!MIPS_EABI | |
7a292a7a | 2455 | && MIPS_SAVED_REGSIZE < 8 |
c906108c | 2456 | && TARGET_BYTE_ORDER == BIG_ENDIAN |
7a292a7a | 2457 | && partial_len < MIPS_SAVED_REGSIZE |
c906108c SS |
2458 | && (typecode == TYPE_CODE_STRUCT || |
2459 | typecode == TYPE_CODE_UNION)) | |
c5aa993b | 2460 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * |
c906108c SS |
2461 | TARGET_CHAR_BIT); |
2462 | ||
9ace0497 | 2463 | if (mips_debug) |
acdb74a0 | 2464 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2465 | argreg, |
2466 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2467 | write_register (argreg, regval); |
2468 | argreg++; | |
c5aa993b | 2469 | |
c906108c SS |
2470 | /* If this is the old ABI, prevent subsequent floating |
2471 | point arguments from being passed in floating point | |
2472 | registers. */ | |
2473 | if (!MIPS_EABI) | |
2474 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
2475 | } | |
c5aa993b | 2476 | |
c906108c SS |
2477 | len -= partial_len; |
2478 | val += partial_len; | |
2479 | ||
566f0f7a AC |
2480 | /* Compute the the offset into the stack at which we |
2481 | will copy the next parameter. | |
2482 | ||
2483 | In older ABIs, the caller reserved space for | |
2484 | registers that contained arguments. This was loosely | |
2485 | refered to as their "home". Consequently, space is | |
2486 | always allocated. | |
c906108c | 2487 | |
566f0f7a AC |
2488 | In the new EABI (and the NABI32), the stack_offset |
2489 | only needs to be adjusted when it has been used.. */ | |
c906108c | 2490 | |
566f0f7a | 2491 | if (MIPS_REGS_HAVE_HOME_P || stack_used_p) |
d929b26f | 2492 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2493 | } |
2494 | } | |
9ace0497 AC |
2495 | if (mips_debug) |
2496 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2497 | } |
2498 | ||
0f71a2f6 JM |
2499 | /* Return adjusted stack pointer. */ |
2500 | return sp; | |
2501 | } | |
2502 | ||
2503 | CORE_ADDR | |
acdb74a0 | 2504 | mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
0f71a2f6 | 2505 | { |
c906108c SS |
2506 | /* Set the return address register to point to the entry |
2507 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 2508 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
2509 | return sp; |
2510 | } | |
2511 | ||
2512 | static void | |
c5aa993b | 2513 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c SS |
2514 | { |
2515 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
7a292a7a SS |
2516 | int regsize; |
2517 | int offset; | |
2518 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
2519 | { | |
2520 | regsize = MIPS_SAVED_REGSIZE; | |
2521 | offset = (TARGET_BYTE_ORDER == BIG_ENDIAN | |
2522 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE | |
2523 | : 0); | |
2524 | } | |
2525 | else | |
2526 | { | |
2527 | regsize = REGISTER_RAW_SIZE (regno); | |
2528 | offset = 0; | |
2529 | } | |
c906108c SS |
2530 | *sp -= regsize; |
2531 | read_register_gen (regno, buffer); | |
7a292a7a | 2532 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
2533 | } |
2534 | ||
2535 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
2536 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
2537 | ||
2538 | void | |
acdb74a0 | 2539 | mips_push_dummy_frame (void) |
c906108c SS |
2540 | { |
2541 | int ireg; | |
c5aa993b JM |
2542 | struct linked_proc_info *link = (struct linked_proc_info *) |
2543 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c | 2544 | mips_extra_func_info_t proc_desc = &link->info; |
6c997a34 | 2545 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); |
c906108c SS |
2546 | CORE_ADDR old_sp = sp; |
2547 | link->next = linked_proc_desc_table; | |
2548 | linked_proc_desc_table = link; | |
2549 | ||
2550 | /* FIXME! are these correct ? */ | |
c5aa993b | 2551 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
2552 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
2553 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
2554 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
2555 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
2556 | /* | |
2557 | * The registers we must save are all those not preserved across | |
2558 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
2559 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
2560 | * and FP Control/Status registers. | |
2561 | * | |
2562 | * | |
2563 | * Dummy frame layout: | |
2564 | * (high memory) | |
c5aa993b JM |
2565 | * Saved PC |
2566 | * Saved MMHI, MMLO, FPC_CSR | |
2567 | * Saved R31 | |
2568 | * Saved R28 | |
2569 | * ... | |
2570 | * Saved R1 | |
c906108c SS |
2571 | * Saved D18 (i.e. F19, F18) |
2572 | * ... | |
2573 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 2574 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
2575 | * (low memory) |
2576 | */ | |
2577 | ||
2578 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
2579 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
2580 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
2581 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
2582 | mips_push_register (&sp, PC_REGNUM); |
2583 | mips_push_register (&sp, HI_REGNUM); | |
2584 | mips_push_register (&sp, LO_REGNUM); | |
2585 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
2586 | ||
2587 | /* Save general CPU registers */ | |
c5aa993b | 2588 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 2589 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
2590 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
2591 | for (ireg = 32; --ireg >= 0;) | |
2592 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2593 | mips_push_register (&sp, ireg); |
2594 | ||
2595 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 2596 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
2597 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
2598 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
2599 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
2600 | from FP. */ | |
c5aa993b JM |
2601 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
2602 | for (ireg = 32; --ireg >= 0;) | |
2603 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2604 | mips_push_register (&sp, ireg + FP0_REGNUM); |
2605 | ||
2606 | /* Update the frame pointer for the call dummy and the stack pointer. | |
2607 | Set the procedure's starting and ending addresses to point to the | |
2608 | call dummy address at the entry point. */ | |
2609 | write_register (PUSH_FP_REGNUM, old_sp); | |
2610 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
2611 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
2612 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
2613 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
2614 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
2615 | } |
2616 | ||
2617 | void | |
acdb74a0 | 2618 | mips_pop_frame (void) |
c906108c SS |
2619 | { |
2620 | register int regnum; | |
2621 | struct frame_info *frame = get_current_frame (); | |
2622 | CORE_ADDR new_sp = FRAME_FP (frame); | |
2623 | ||
cce74817 | 2624 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 2625 | |
c5aa993b | 2626 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c SS |
2627 | if (frame->saved_regs == NULL) |
2628 | mips_find_saved_regs (frame); | |
2629 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
2630 | { | |
2631 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
2632 | && frame->saved_regs[regnum]) | |
2633 | write_register (regnum, | |
2634 | read_memory_integer (frame->saved_regs[regnum], | |
c5aa993b | 2635 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2636 | } |
2637 | write_register (SP_REGNUM, new_sp); | |
2638 | flush_cached_frames (); | |
2639 | ||
c5aa993b | 2640 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
2641 | { |
2642 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
2643 | ||
2644 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
2645 | pi_ptr != NULL; | |
2646 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
2647 | { | |
2648 | if (&pi_ptr->info == proc_desc) | |
2649 | break; | |
2650 | } | |
2651 | ||
2652 | if (pi_ptr == NULL) | |
2653 | error ("Can't locate dummy extra frame info\n"); | |
2654 | ||
2655 | if (prev_ptr != NULL) | |
2656 | prev_ptr->next = pi_ptr->next; | |
2657 | else | |
2658 | linked_proc_desc_table = pi_ptr->next; | |
2659 | ||
b8c9b27d | 2660 | xfree (pi_ptr); |
c906108c SS |
2661 | |
2662 | write_register (HI_REGNUM, | |
c5aa993b | 2663 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2664 | MIPS_SAVED_REGSIZE)); |
c906108c | 2665 | write_register (LO_REGNUM, |
c5aa993b | 2666 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2667 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2668 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
2669 | write_register (FCRCS_REGNUM, | |
c5aa993b | 2670 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2671 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2672 | } |
2673 | } | |
2674 | ||
2675 | static void | |
acdb74a0 | 2676 | mips_print_register (int regnum, int all) |
c906108c SS |
2677 | { |
2678 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2679 | ||
2680 | /* Get the data in raw format. */ | |
2681 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2682 | { | |
2683 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
2684 | return; | |
2685 | } | |
2686 | ||
2687 | /* If an even floating point register, also print as double. */ | |
2688 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT | |
c5aa993b JM |
2689 | && !((regnum - FP0_REGNUM) & 1)) |
2690 | if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */ | |
c906108c | 2691 | { |
c5aa993b | 2692 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; |
c906108c SS |
2693 | |
2694 | read_relative_register_raw_bytes (regnum, dbuffer); | |
c5aa993b | 2695 | read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE); |
c906108c SS |
2696 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); |
2697 | ||
c5aa993b | 2698 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
c906108c SS |
2699 | val_print (builtin_type_double, dbuffer, 0, 0, |
2700 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2701 | printf_filtered ("); "); | |
2702 | } | |
2703 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
2704 | ||
2705 | /* The problem with printing numeric register names (r26, etc.) is that | |
2706 | the user can't use them on input. Probably the best solution is to | |
2707 | fix it so that either the numeric or the funky (a2, etc.) names | |
2708 | are accepted on input. */ | |
2709 | if (regnum < MIPS_NUMREGS) | |
2710 | printf_filtered ("(r%d): ", regnum); | |
2711 | else | |
2712 | printf_filtered (": "); | |
2713 | ||
2714 | /* If virtual format is floating, print it that way. */ | |
2715 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2716 | if (FP_REGISTER_DOUBLE) | |
c5aa993b | 2717 | { /* show 8-byte floats as float AND double: */ |
c906108c SS |
2718 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2719 | ||
2720 | printf_filtered (" (float) "); | |
2721 | val_print (builtin_type_float, raw_buffer + offset, 0, 0, | |
2722 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2723 | printf_filtered (", (double) "); | |
2724 | val_print (builtin_type_double, raw_buffer, 0, 0, | |
2725 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2726 | } | |
2727 | else | |
2728 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
2729 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2730 | /* Else print as integer in hex. */ | |
2731 | else | |
ed9a39eb JM |
2732 | { |
2733 | int offset; | |
2734 | ||
2735 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2736 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); | |
2737 | else | |
2738 | offset = 0; | |
2739 | ||
2740 | print_scalar_formatted (raw_buffer + offset, | |
2741 | REGISTER_VIRTUAL_TYPE (regnum), | |
2742 | 'x', 0, gdb_stdout); | |
2743 | } | |
c906108c SS |
2744 | } |
2745 | ||
2746 | /* Replacement for generic do_registers_info. | |
2747 | Print regs in pretty columns. */ | |
2748 | ||
2749 | static int | |
acdb74a0 | 2750 | do_fp_register_row (int regnum) |
c5aa993b | 2751 | { /* do values for FP (float) regs */ |
c906108c SS |
2752 | char *raw_buffer[2]; |
2753 | char *dbl_buffer; | |
2754 | /* use HI and LO to control the order of combining two flt regs */ | |
2755 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2756 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); | |
2757 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ | |
2758 | int inv1, inv2, inv3; | |
c5aa993b | 2759 | |
c906108c SS |
2760 | raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
2761 | raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2762 | dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2763 | ||
2764 | /* Get the data in raw format. */ | |
2765 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) | |
2766 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
c5aa993b | 2767 | if (REGISTER_RAW_SIZE (regnum) == 4) |
c906108c SS |
2768 | { |
2769 | /* 4-byte registers: we can fit two registers per row. */ | |
2770 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
2771 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) | |
c5aa993b | 2772 | error ("can't read register %d (%s)", |
c906108c SS |
2773 | regnum + 1, REGISTER_NAME (regnum + 1)); |
2774 | ||
2775 | /* copy the two floats into one double, and unpack both */ | |
65edb64b | 2776 | memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b JM |
2777 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); |
2778 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); | |
2779 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
2780 | ||
1adad886 AC |
2781 | printf_filtered (" %-5s", REGISTER_NAME (regnum)); |
2782 | if (inv1) | |
2783 | printf_filtered (": <invalid float>"); | |
2784 | else | |
2785 | printf_filtered ("%-17.9g", flt1); | |
2786 | ||
2787 | printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); | |
2788 | if (inv2) | |
2789 | printf_filtered (": <invalid float>"); | |
2790 | else | |
2791 | printf_filtered ("%-17.9g", flt2); | |
2792 | ||
2793 | printf_filtered (" dbl: "); | |
2794 | if (inv3) | |
2795 | printf_filtered ("<invalid double>"); | |
2796 | else | |
2797 | printf_filtered ("%-24.17g", doub); | |
2798 | printf_filtered ("\n"); | |
2799 | ||
c906108c | 2800 | /* may want to do hex display here (future enhancement) */ |
c5aa993b | 2801 | regnum += 2; |
c906108c SS |
2802 | } |
2803 | else | |
c5aa993b | 2804 | { /* eight byte registers: print each one as float AND as double. */ |
c906108c SS |
2805 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2806 | ||
65edb64b | 2807 | memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b | 2808 | flt1 = unpack_double (builtin_type_float, |
c906108c | 2809 | &raw_buffer[HI][offset], &inv1); |
c5aa993b | 2810 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); |
c906108c | 2811 | |
1adad886 AC |
2812 | printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); |
2813 | if (inv1) | |
2814 | printf_filtered ("<invalid float>"); | |
2815 | else | |
2816 | printf_filtered ("flt: %-17.9g", flt1); | |
2817 | ||
2818 | printf_filtered (" dbl: "); | |
2819 | if (inv3) | |
2820 | printf_filtered ("<invalid double>"); | |
2821 | else | |
2822 | printf_filtered ("%-24.17g", doub); | |
2823 | ||
2824 | printf_filtered ("\n"); | |
c906108c SS |
2825 | /* may want to do hex display here (future enhancement) */ |
2826 | regnum++; | |
2827 | } | |
2828 | return regnum; | |
2829 | } | |
2830 | ||
2831 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
2832 | ||
2833 | static int | |
acdb74a0 | 2834 | do_gp_register_row (int regnum) |
c906108c SS |
2835 | { |
2836 | /* do values for GP (int) regs */ | |
2837 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2838 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ | |
2839 | int col, byte; | |
2840 | int start_regnum = regnum; | |
2841 | int numregs = NUM_REGS; | |
2842 | ||
2843 | ||
2844 | /* For GP registers, we print a separate row of names above the vals */ | |
2845 | printf_filtered (" "); | |
2846 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2847 | { | |
2848 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2849 | continue; /* unused register */ |
c906108c | 2850 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
2851 | break; /* end the row: reached FP register */ |
2852 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
2853 | REGISTER_NAME (regnum)); |
2854 | col++; | |
2855 | } | |
c5aa993b | 2856 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
2857 | start_regnum); /* print the R0 to R31 names */ |
2858 | ||
2859 | regnum = start_regnum; /* go back to start of row */ | |
2860 | /* now print the values in hex, 4 or 8 to the row */ | |
2861 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2862 | { | |
2863 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2864 | continue; /* unused register */ |
c906108c | 2865 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 2866 | break; /* end row: reached FP register */ |
c906108c SS |
2867 | /* OK: get the data in raw format. */ |
2868 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2869 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
2870 | /* pad small registers */ | |
43e526b9 | 2871 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
2872 | printf_filtered (" "); |
2873 | /* Now print the register value in hex, endian order. */ | |
2874 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
43e526b9 JM |
2875 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
2876 | byte < REGISTER_RAW_SIZE (regnum); | |
2877 | byte++) | |
c906108c SS |
2878 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2879 | else | |
43e526b9 JM |
2880 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
2881 | byte >= 0; | |
2882 | byte--) | |
c906108c SS |
2883 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2884 | printf_filtered (" "); | |
2885 | col++; | |
2886 | } | |
c5aa993b | 2887 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
2888 | printf_filtered ("\n"); |
2889 | ||
2890 | return regnum; | |
2891 | } | |
2892 | ||
2893 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
2894 | ||
2895 | void | |
acdb74a0 | 2896 | mips_do_registers_info (int regnum, int fpregs) |
c906108c | 2897 | { |
c5aa993b | 2898 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
2899 | { |
2900 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2901 | error ("Not a valid register for the current processor type"); | |
2902 | ||
2903 | mips_print_register (regnum, 0); | |
2904 | printf_filtered ("\n"); | |
2905 | } | |
c5aa993b JM |
2906 | else |
2907 | /* do all (or most) registers */ | |
c906108c SS |
2908 | { |
2909 | regnum = 0; | |
2910 | while (regnum < NUM_REGS) | |
2911 | { | |
c5aa993b JM |
2912 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
2913 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
2914 | regnum = do_fp_register_row (regnum); /* FP regs */ |
2915 | else | |
2916 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
2917 | else | |
2918 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
2919 | } | |
2920 | } | |
2921 | } | |
2922 | ||
2923 | /* Return number of args passed to a frame. described by FIP. | |
2924 | Can return -1, meaning no way to tell. */ | |
2925 | ||
2926 | int | |
acdb74a0 | 2927 | mips_frame_num_args (struct frame_info *frame) |
c906108c | 2928 | { |
c906108c SS |
2929 | return -1; |
2930 | } | |
2931 | ||
2932 | /* Is this a branch with a delay slot? */ | |
2933 | ||
a14ed312 | 2934 | static int is_delayed (unsigned long); |
c906108c SS |
2935 | |
2936 | static int | |
acdb74a0 | 2937 | is_delayed (unsigned long insn) |
c906108c SS |
2938 | { |
2939 | int i; | |
2940 | for (i = 0; i < NUMOPCODES; ++i) | |
2941 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
2942 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
2943 | break; | |
2944 | return (i < NUMOPCODES | |
2945 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2946 | | INSN_COND_BRANCH_DELAY | |
2947 | | INSN_COND_BRANCH_LIKELY))); | |
2948 | } | |
2949 | ||
2950 | int | |
acdb74a0 | 2951 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
2952 | { |
2953 | char buf[MIPS_INSTLEN]; | |
2954 | ||
2955 | /* There is no branch delay slot on MIPS16. */ | |
2956 | if (pc_is_mips16 (pc)) | |
2957 | return 0; | |
2958 | ||
2959 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
2960 | /* If error reading memory, guess that it is not a delayed branch. */ | |
2961 | return 0; | |
c5aa993b | 2962 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
2963 | } |
2964 | ||
2965 | ||
2966 | /* Skip the PC past function prologue instructions (32-bit version). | |
2967 | This is a helper function for mips_skip_prologue. */ | |
2968 | ||
2969 | static CORE_ADDR | |
f7b9e9fc | 2970 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 2971 | { |
c5aa993b JM |
2972 | t_inst inst; |
2973 | CORE_ADDR end_pc; | |
2974 | int seen_sp_adjust = 0; | |
2975 | int load_immediate_bytes = 0; | |
2976 | ||
2977 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2978 | instruction and the instructions that save registers on the stack | |
2979 | or in the gcc frame. */ | |
2980 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
2981 | { | |
2982 | unsigned long high_word; | |
c906108c | 2983 | |
c5aa993b JM |
2984 | inst = mips_fetch_instruction (pc); |
2985 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 2986 | |
c5aa993b JM |
2987 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
2988 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
2989 | seen_sp_adjust = 1; | |
2990 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
2991 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
2992 | seen_sp_adjust = 1; | |
2993 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
2994 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
2995 | && (inst & 0x001F0000)) /* reg != $zero */ | |
2996 | continue; | |
2997 | ||
2998 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
2999 | continue; | |
3000 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
3001 | /* sx reg,n($s8) */ | |
3002 | continue; /* reg != $zero */ | |
3003 | ||
3004 | /* move $s8,$sp. With different versions of gas this will be either | |
3005 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
3006 | Accept any one of these. */ | |
3007 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3008 | continue; | |
3009 | ||
3010 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
3011 | continue; | |
3012 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
3013 | continue; | |
3014 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
3015 | continue; | |
3016 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3017 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
3018 | continue; | |
3019 | /* The following instructions load $at or $t0 with an immediate | |
3020 | value in preparation for a stack adjustment via | |
3021 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
3022 | a local variable, so we accept them only before a stack adjustment | |
3023 | instruction was seen. */ | |
3024 | else if (!seen_sp_adjust) | |
3025 | { | |
3026 | if (high_word == 0x3c01 || /* lui $at,n */ | |
3027 | high_word == 0x3c08) /* lui $t0,n */ | |
3028 | { | |
3029 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
3030 | continue; | |
3031 | } | |
3032 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
3033 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
3034 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
3035 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
3036 | { | |
3037 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
3038 | continue; | |
3039 | } | |
3040 | else | |
3041 | break; | |
3042 | } | |
3043 | else | |
3044 | break; | |
c906108c SS |
3045 | } |
3046 | ||
c5aa993b JM |
3047 | /* In a frameless function, we might have incorrectly |
3048 | skipped some load immediate instructions. Undo the skipping | |
3049 | if the load immediate was not followed by a stack adjustment. */ | |
3050 | if (load_immediate_bytes && !seen_sp_adjust) | |
3051 | pc -= load_immediate_bytes; | |
3052 | return pc; | |
c906108c SS |
3053 | } |
3054 | ||
3055 | /* Skip the PC past function prologue instructions (16-bit version). | |
3056 | This is a helper function for mips_skip_prologue. */ | |
3057 | ||
3058 | static CORE_ADDR | |
f7b9e9fc | 3059 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 3060 | { |
c5aa993b JM |
3061 | CORE_ADDR end_pc; |
3062 | int extend_bytes = 0; | |
3063 | int prev_extend_bytes; | |
c906108c | 3064 | |
c5aa993b JM |
3065 | /* Table of instructions likely to be found in a function prologue. */ |
3066 | static struct | |
c906108c SS |
3067 | { |
3068 | unsigned short inst; | |
3069 | unsigned short mask; | |
c5aa993b JM |
3070 | } |
3071 | table[] = | |
3072 | { | |
c906108c | 3073 | { |
c5aa993b JM |
3074 | 0x6300, 0xff00 |
3075 | } | |
3076 | , /* addiu $sp,offset */ | |
3077 | { | |
3078 | 0xfb00, 0xff00 | |
3079 | } | |
3080 | , /* daddiu $sp,offset */ | |
3081 | { | |
3082 | 0xd000, 0xf800 | |
3083 | } | |
3084 | , /* sw reg,n($sp) */ | |
3085 | { | |
3086 | 0xf900, 0xff00 | |
3087 | } | |
3088 | , /* sd reg,n($sp) */ | |
3089 | { | |
3090 | 0x6200, 0xff00 | |
3091 | } | |
3092 | , /* sw $ra,n($sp) */ | |
3093 | { | |
3094 | 0xfa00, 0xff00 | |
3095 | } | |
3096 | , /* sd $ra,n($sp) */ | |
3097 | { | |
3098 | 0x673d, 0xffff | |
3099 | } | |
3100 | , /* move $s1,sp */ | |
3101 | { | |
3102 | 0xd980, 0xff80 | |
3103 | } | |
3104 | , /* sw $a0-$a3,n($s1) */ | |
3105 | { | |
3106 | 0x6704, 0xff1c | |
3107 | } | |
3108 | , /* move reg,$a0-$a3 */ | |
3109 | { | |
3110 | 0xe809, 0xf81f | |
3111 | } | |
3112 | , /* entry pseudo-op */ | |
3113 | { | |
3114 | 0x0100, 0xff00 | |
3115 | } | |
3116 | , /* addiu $s1,$sp,n */ | |
3117 | { | |
3118 | 0, 0 | |
3119 | } /* end of table marker */ | |
3120 | }; | |
3121 | ||
3122 | /* Skip the typical prologue instructions. These are the stack adjustment | |
3123 | instruction and the instructions that save registers on the stack | |
3124 | or in the gcc frame. */ | |
3125 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
3126 | { | |
3127 | unsigned short inst; | |
3128 | int i; | |
c906108c | 3129 | |
c5aa993b | 3130 | inst = mips_fetch_instruction (pc); |
c906108c | 3131 | |
c5aa993b JM |
3132 | /* Normally we ignore an extend instruction. However, if it is |
3133 | not followed by a valid prologue instruction, we must adjust | |
3134 | the pc back over the extend so that it won't be considered | |
3135 | part of the prologue. */ | |
3136 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
3137 | { | |
3138 | extend_bytes = MIPS16_INSTLEN; | |
3139 | continue; | |
3140 | } | |
3141 | prev_extend_bytes = extend_bytes; | |
3142 | extend_bytes = 0; | |
c906108c | 3143 | |
c5aa993b JM |
3144 | /* Check for other valid prologue instructions besides extend. */ |
3145 | for (i = 0; table[i].mask != 0; i++) | |
3146 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
3147 | break; | |
3148 | if (table[i].mask != 0) /* it was in table? */ | |
3149 | continue; /* ignore it */ | |
3150 | else | |
3151 | /* non-prologue */ | |
3152 | { | |
3153 | /* Return the current pc, adjusted backwards by 2 if | |
3154 | the previous instruction was an extend. */ | |
3155 | return pc - prev_extend_bytes; | |
3156 | } | |
c906108c SS |
3157 | } |
3158 | return pc; | |
3159 | } | |
3160 | ||
3161 | /* To skip prologues, I use this predicate. Returns either PC itself | |
3162 | if the code at PC does not look like a function prologue; otherwise | |
3163 | returns an address that (if we're lucky) follows the prologue. If | |
3164 | LENIENT, then we must skip everything which is involved in setting | |
3165 | up the frame (it's OK to skip more, just so long as we don't skip | |
3166 | anything which might clobber the registers which are being saved. | |
3167 | We must skip more in the case where part of the prologue is in the | |
3168 | delay slot of a non-prologue instruction). */ | |
3169 | ||
3170 | CORE_ADDR | |
f7b9e9fc | 3171 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
3172 | { |
3173 | /* See if we can determine the end of the prologue via the symbol table. | |
3174 | If so, then return either PC, or the PC after the prologue, whichever | |
3175 | is greater. */ | |
3176 | ||
3177 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
3178 | ||
3179 | if (post_prologue_pc != 0) | |
3180 | return max (pc, post_prologue_pc); | |
3181 | ||
3182 | /* Can't determine prologue from the symbol table, need to examine | |
3183 | instructions. */ | |
3184 | ||
3185 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 3186 | return mips16_skip_prologue (pc); |
c906108c | 3187 | else |
f7b9e9fc | 3188 | return mips32_skip_prologue (pc); |
c906108c | 3189 | } |
c906108c | 3190 | |
7a292a7a SS |
3191 | /* Determine how a return value is stored within the MIPS register |
3192 | file, given the return type `valtype'. */ | |
3193 | ||
3194 | struct return_value_word | |
3195 | { | |
3196 | int len; | |
3197 | int reg; | |
3198 | int reg_offset; | |
3199 | int buf_offset; | |
3200 | }; | |
3201 | ||
7a292a7a | 3202 | static void |
acdb74a0 AC |
3203 | return_value_location (struct type *valtype, |
3204 | struct return_value_word *hi, | |
3205 | struct return_value_word *lo) | |
7a292a7a SS |
3206 | { |
3207 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3208 | |
7a292a7a SS |
3209 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
3210 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3211 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3212 | { | |
3213 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3214 | { | |
3215 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 3216 | spread them across a floating-point register pair. */ |
7a292a7a SS |
3217 | lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; |
3218 | hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4; | |
3219 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN | |
3220 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) | |
3221 | ? 4 : 0); | |
3222 | hi->reg_offset = lo->reg_offset; | |
3223 | lo->reg = FP0_REGNUM + 0; | |
3224 | hi->reg = FP0_REGNUM + 1; | |
3225 | lo->len = 4; | |
3226 | hi->len = 4; | |
3227 | } | |
3228 | else | |
3229 | { | |
3230 | /* The floating point value fits in a single floating-point | |
c5aa993b | 3231 | register. */ |
7a292a7a SS |
3232 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN |
3233 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 | |
3234 | && len == 4) | |
3235 | ? 4 : 0); | |
3236 | lo->reg = FP0_REGNUM; | |
3237 | lo->len = len; | |
3238 | lo->buf_offset = 0; | |
3239 | hi->len = 0; | |
3240 | hi->reg_offset = 0; | |
3241 | hi->buf_offset = 0; | |
3242 | hi->reg = 0; | |
3243 | } | |
3244 | } | |
3245 | else | |
3246 | { | |
3247 | /* Locate a result possibly spread across two registers. */ | |
3248 | int regnum = 2; | |
3249 | lo->reg = regnum + 0; | |
3250 | hi->reg = regnum + 1; | |
3251 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3252 | && len < MIPS_SAVED_REGSIZE) | |
3253 | { | |
3254 | /* "un-left-justify" the value in the low register */ | |
3255 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
3256 | lo->len = len; | |
3257 | hi->reg_offset = 0; | |
3258 | hi->len = 0; | |
3259 | } | |
3260 | else if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3261 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ | |
3262 | && len < MIPS_SAVED_REGSIZE * 2 | |
3263 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3264 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3265 | { | |
3266 | /* "un-left-justify" the value spread across two registers. */ | |
3267 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
3268 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
3269 | hi->reg_offset = 0; | |
3270 | hi->len = len - lo->len; | |
3271 | } | |
3272 | else | |
3273 | { | |
3274 | /* Only perform a partial copy of the second register. */ | |
3275 | lo->reg_offset = 0; | |
3276 | hi->reg_offset = 0; | |
3277 | if (len > MIPS_SAVED_REGSIZE) | |
3278 | { | |
3279 | lo->len = MIPS_SAVED_REGSIZE; | |
3280 | hi->len = len - MIPS_SAVED_REGSIZE; | |
3281 | } | |
3282 | else | |
3283 | { | |
3284 | lo->len = len; | |
3285 | hi->len = 0; | |
3286 | } | |
3287 | } | |
3288 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3289 | && REGISTER_RAW_SIZE (regnum) == 8 | |
3290 | && MIPS_SAVED_REGSIZE == 4) | |
3291 | { | |
3292 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 3293 | of the register is being used */ |
7a292a7a SS |
3294 | lo->reg_offset += 4; |
3295 | hi->reg_offset += 4; | |
3296 | } | |
3297 | lo->buf_offset = 0; | |
3298 | hi->buf_offset = lo->len; | |
3299 | } | |
3300 | } | |
3301 | ||
3302 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
3303 | copy its value into `valbuf'. */ | |
3304 | ||
c906108c | 3305 | void |
acdb74a0 AC |
3306 | mips_extract_return_value (struct type *valtype, |
3307 | char regbuf[REGISTER_BYTES], | |
3308 | char *valbuf) | |
c906108c | 3309 | { |
7a292a7a SS |
3310 | struct return_value_word lo; |
3311 | struct return_value_word hi; | |
99567b1b | 3312 | return_value_location (valtype, &hi, &lo); |
7a292a7a SS |
3313 | |
3314 | memcpy (valbuf + lo.buf_offset, | |
3315 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
3316 | lo.len); | |
3317 | ||
3318 | if (hi.len > 0) | |
3319 | memcpy (valbuf + hi.buf_offset, | |
3320 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
3321 | hi.len); | |
c906108c SS |
3322 | } |
3323 | ||
7a292a7a SS |
3324 | /* Given a return value in `valbuf' with a type `valtype', write it's |
3325 | value into the appropriate register. */ | |
3326 | ||
c906108c | 3327 | void |
acdb74a0 | 3328 | mips_store_return_value (struct type *valtype, char *valbuf) |
c906108c | 3329 | { |
7a292a7a SS |
3330 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
3331 | struct return_value_word lo; | |
3332 | struct return_value_word hi; | |
99567b1b | 3333 | return_value_location (valtype, &hi, &lo); |
7a292a7a SS |
3334 | |
3335 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3336 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3337 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
3338 | raw_buffer, | |
3339 | REGISTER_RAW_SIZE (lo.reg)); | |
c5aa993b | 3340 | |
7a292a7a SS |
3341 | if (hi.len > 0) |
3342 | { | |
3343 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3344 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3345 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
3346 | raw_buffer, | |
3347 | REGISTER_RAW_SIZE (hi.reg)); | |
3348 | } | |
c906108c SS |
3349 | } |
3350 | ||
3351 | /* Exported procedure: Is PC in the signal trampoline code */ | |
3352 | ||
3353 | int | |
acdb74a0 | 3354 | in_sigtramp (CORE_ADDR pc, char *ignore) |
c906108c SS |
3355 | { |
3356 | if (sigtramp_address == 0) | |
3357 | fixup_sigtramp (); | |
3358 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
3359 | } | |
3360 | ||
a5ea2558 AC |
3361 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
3362 | used for all MIPS-specific commands. */ | |
3363 | ||
a5ea2558 | 3364 | static void |
acdb74a0 | 3365 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
3366 | { |
3367 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
3368 | } | |
3369 | ||
a5ea2558 | 3370 | static void |
acdb74a0 | 3371 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
3372 | { |
3373 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
3374 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
3375 | } | |
3376 | ||
c906108c SS |
3377 | /* Commands to show/set the MIPS FPU type. */ |
3378 | ||
c906108c | 3379 | static void |
acdb74a0 | 3380 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 3381 | { |
c906108c SS |
3382 | char *fpu; |
3383 | switch (MIPS_FPU_TYPE) | |
3384 | { | |
3385 | case MIPS_FPU_SINGLE: | |
3386 | fpu = "single-precision"; | |
3387 | break; | |
3388 | case MIPS_FPU_DOUBLE: | |
3389 | fpu = "double-precision"; | |
3390 | break; | |
3391 | case MIPS_FPU_NONE: | |
3392 | fpu = "absent (none)"; | |
3393 | break; | |
93d56215 AC |
3394 | default: |
3395 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
3396 | } |
3397 | if (mips_fpu_type_auto) | |
3398 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
3399 | fpu); | |
3400 | else | |
3401 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
3402 | fpu); | |
3403 | } | |
3404 | ||
3405 | ||
c906108c | 3406 | static void |
acdb74a0 | 3407 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
3408 | { |
3409 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
3410 | show_mipsfpu_command (args, from_tty); | |
3411 | } | |
3412 | ||
c906108c | 3413 | static void |
acdb74a0 | 3414 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
3415 | { |
3416 | mips_fpu_type = MIPS_FPU_SINGLE; | |
3417 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3418 | if (GDB_MULTI_ARCH) |
3419 | { | |
3420 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; | |
3421 | } | |
c906108c SS |
3422 | } |
3423 | ||
c906108c | 3424 | static void |
acdb74a0 | 3425 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
3426 | { |
3427 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
3428 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3429 | if (GDB_MULTI_ARCH) |
3430 | { | |
3431 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; | |
3432 | } | |
c906108c SS |
3433 | } |
3434 | ||
c906108c | 3435 | static void |
acdb74a0 | 3436 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
3437 | { |
3438 | mips_fpu_type = MIPS_FPU_NONE; | |
3439 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3440 | if (GDB_MULTI_ARCH) |
3441 | { | |
3442 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; | |
3443 | } | |
c906108c SS |
3444 | } |
3445 | ||
c906108c | 3446 | static void |
acdb74a0 | 3447 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
3448 | { |
3449 | mips_fpu_type_auto = 1; | |
3450 | } | |
3451 | ||
3452 | /* Command to set the processor type. */ | |
3453 | ||
3454 | void | |
acdb74a0 | 3455 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
3456 | { |
3457 | int i; | |
3458 | ||
3459 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
3460 | { | |
3461 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
3462 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3463 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
3464 | ||
3465 | /* Restore the value. */ | |
4fcf66da | 3466 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
3467 | |
3468 | return; | |
3469 | } | |
c5aa993b | 3470 | |
c906108c SS |
3471 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
3472 | { | |
3473 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
3474 | /* Restore its value. */ | |
4fcf66da | 3475 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
3476 | } |
3477 | } | |
3478 | ||
3479 | static void | |
acdb74a0 | 3480 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
3481 | { |
3482 | } | |
3483 | ||
3484 | /* Modify the actual processor type. */ | |
3485 | ||
3486 | int | |
acdb74a0 | 3487 | mips_set_processor_type (char *str) |
c906108c | 3488 | { |
1012bd0e | 3489 | int i; |
c906108c SS |
3490 | |
3491 | if (str == NULL) | |
3492 | return 0; | |
3493 | ||
3494 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3495 | { | |
3496 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
3497 | { | |
3498 | mips_processor_type = str; | |
cce74817 | 3499 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 3500 | return 1; |
c906108c SS |
3501 | /* FIXME tweak fpu flag too */ |
3502 | } | |
3503 | } | |
3504 | ||
3505 | return 0; | |
3506 | } | |
3507 | ||
3508 | /* Attempt to identify the particular processor model by reading the | |
3509 | processor id. */ | |
3510 | ||
3511 | char * | |
acdb74a0 | 3512 | mips_read_processor_type (void) |
c906108c SS |
3513 | { |
3514 | CORE_ADDR prid; | |
3515 | ||
3516 | prid = read_register (PRID_REGNUM); | |
3517 | ||
3518 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 3519 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
3520 | |
3521 | return NULL; | |
3522 | } | |
3523 | ||
3524 | /* Just like reinit_frame_cache, but with the right arguments to be | |
3525 | callable as an sfunc. */ | |
3526 | ||
3527 | static void | |
acdb74a0 AC |
3528 | reinit_frame_cache_sfunc (char *args, int from_tty, |
3529 | struct cmd_list_element *c) | |
c906108c SS |
3530 | { |
3531 | reinit_frame_cache (); | |
3532 | } | |
3533 | ||
3534 | int | |
acdb74a0 | 3535 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
3536 | { |
3537 | mips_extra_func_info_t proc_desc; | |
3538 | ||
3539 | /* Search for the function containing this address. Set the low bit | |
3540 | of the address when searching, in case we were given an even address | |
3541 | that is the start of a 16-bit function. If we didn't do this, | |
3542 | the search would fail because the symbol table says the function | |
3543 | starts at an odd address, i.e. 1 byte past the given address. */ | |
3544 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
3545 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
3546 | ||
3547 | /* Make an attempt to determine if this is a 16-bit function. If | |
3548 | the procedure descriptor exists and the address therein is odd, | |
3549 | it's definitely a 16-bit function. Otherwise, we have to just | |
3550 | guess that if the address passed in is odd, it's 16-bits. */ | |
3551 | if (proc_desc) | |
65c11066 MS |
3552 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
3553 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; | |
c906108c | 3554 | else |
65c11066 MS |
3555 | info->mach = pc_is_mips16 (memaddr) ? |
3556 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; | |
c906108c SS |
3557 | |
3558 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 3559 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 3560 | |
c906108c SS |
3561 | /* Call the appropriate disassembler based on the target endian-ness. */ |
3562 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3563 | return print_insn_big_mips (memaddr, info); | |
3564 | else | |
3565 | return print_insn_little_mips (memaddr, info); | |
3566 | } | |
3567 | ||
3568 | /* Old-style breakpoint macros. | |
3569 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
3570 | confused when it sees the usual MIPS breakpoint instruction. */ | |
3571 | ||
3572 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
3573 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
3574 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
3575 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
3576 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
3577 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
3578 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
3579 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
3580 | ||
3581 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
3582 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
3583 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
3584 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
3585 | (if necessary) to point to the actual memory location where the | |
3586 | breakpoint should be inserted. */ | |
3587 | ||
c5aa993b | 3588 | unsigned char * |
acdb74a0 | 3589 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c SS |
3590 | { |
3591 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3592 | { | |
3593 | if (pc_is_mips16 (*pcptr)) | |
3594 | { | |
1012bd0e EZ |
3595 | static unsigned char mips16_big_breakpoint[] = |
3596 | MIPS16_BIG_BREAKPOINT; | |
c906108c | 3597 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 3598 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
3599 | return mips16_big_breakpoint; |
3600 | } | |
3601 | else | |
3602 | { | |
1012bd0e EZ |
3603 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
3604 | static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
3605 | static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
c906108c | 3606 | |
c5aa993b | 3607 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
3608 | |
3609 | if (strcmp (target_shortname, "mips") == 0) | |
3610 | return idt_big_breakpoint; | |
3611 | else if (strcmp (target_shortname, "ddb") == 0 | |
3612 | || strcmp (target_shortname, "pmon") == 0 | |
3613 | || strcmp (target_shortname, "lsi") == 0) | |
3614 | return pmon_big_breakpoint; | |
3615 | else | |
3616 | return big_breakpoint; | |
3617 | } | |
3618 | } | |
3619 | else | |
3620 | { | |
3621 | if (pc_is_mips16 (*pcptr)) | |
3622 | { | |
1012bd0e EZ |
3623 | static unsigned char mips16_little_breakpoint[] = |
3624 | MIPS16_LITTLE_BREAKPOINT; | |
c906108c | 3625 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 3626 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
3627 | return mips16_little_breakpoint; |
3628 | } | |
3629 | else | |
3630 | { | |
1012bd0e EZ |
3631 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; |
3632 | static unsigned char pmon_little_breakpoint[] = | |
3633 | PMON_LITTLE_BREAKPOINT; | |
3634 | static unsigned char idt_little_breakpoint[] = | |
3635 | IDT_LITTLE_BREAKPOINT; | |
c906108c | 3636 | |
c5aa993b | 3637 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
3638 | |
3639 | if (strcmp (target_shortname, "mips") == 0) | |
3640 | return idt_little_breakpoint; | |
3641 | else if (strcmp (target_shortname, "ddb") == 0 | |
3642 | || strcmp (target_shortname, "pmon") == 0 | |
3643 | || strcmp (target_shortname, "lsi") == 0) | |
3644 | return pmon_little_breakpoint; | |
3645 | else | |
3646 | return little_breakpoint; | |
3647 | } | |
3648 | } | |
3649 | } | |
3650 | ||
3651 | /* If PC is in a mips16 call or return stub, return the address of the target | |
3652 | PC, which is either the callee or the caller. There are several | |
3653 | cases which must be handled: | |
3654 | ||
3655 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 3656 | target PC is in $31 ($ra). |
c906108c | 3657 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 3658 | and the target PC is in $2. |
c906108c | 3659 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
3660 | before the jal instruction, this is effectively a call stub |
3661 | and the the target PC is in $2. Otherwise this is effectively | |
3662 | a return stub and the target PC is in $18. | |
c906108c SS |
3663 | |
3664 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
3665 | gory details. | |
3666 | ||
3667 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 3668 | */ |
c906108c SS |
3669 | |
3670 | CORE_ADDR | |
acdb74a0 | 3671 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
3672 | { |
3673 | char *name; | |
3674 | CORE_ADDR start_addr; | |
3675 | ||
3676 | /* Find the starting address and name of the function containing the PC. */ | |
3677 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3678 | return 0; | |
3679 | ||
3680 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3681 | target PC is in $31 ($ra). */ | |
3682 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3683 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 3684 | return read_signed_register (RA_REGNUM); |
c906108c SS |
3685 | |
3686 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3687 | { | |
3688 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3689 | and the target PC is in $2. */ | |
3690 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 3691 | return read_signed_register (2); |
c906108c SS |
3692 | |
3693 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
3694 | before the jal instruction, this is effectively a call stub |
3695 | and the the target PC is in $2. Otherwise this is effectively | |
3696 | a return stub and the target PC is in $18. */ | |
c906108c SS |
3697 | else if (name[19] == 's' || name[19] == 'd') |
3698 | { | |
3699 | if (pc == start_addr) | |
3700 | { | |
3701 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
3702 | stub. Such a stub for a function bar might have a name |
3703 | like __fn_stub_bar, and might look like this: | |
3704 | mfc1 $4,$f13 | |
3705 | mfc1 $5,$f12 | |
3706 | mfc1 $6,$f15 | |
3707 | mfc1 $7,$f14 | |
3708 | la $1,bar (becomes a lui/addiu pair) | |
3709 | jr $1 | |
3710 | So scan down to the lui/addi and extract the target | |
3711 | address from those two instructions. */ | |
c906108c | 3712 | |
6c997a34 | 3713 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
3714 | t_inst inst; |
3715 | int i; | |
3716 | ||
3717 | /* See if the name of the target function is __fn_stub_*. */ | |
3718 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
3719 | return target_pc; | |
3720 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
3721 | && strcmp (name, "etext") != 0 | |
3722 | && strcmp (name, "_etext") != 0) | |
3723 | return target_pc; | |
3724 | ||
3725 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
3726 | The limit on the search is arbitrarily set to 20 |
3727 | instructions. FIXME. */ | |
c906108c SS |
3728 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
3729 | { | |
c5aa993b JM |
3730 | inst = mips_fetch_instruction (target_pc); |
3731 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
3732 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
3733 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
3734 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
3735 | } |
3736 | ||
3737 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
3738 | return target_pc; | |
3739 | } | |
3740 | else | |
3741 | /* This is the 'return' part of a call stub. The return | |
3742 | address is in $r18. */ | |
6c997a34 | 3743 | return read_signed_register (18); |
c906108c SS |
3744 | } |
3745 | } | |
c5aa993b | 3746 | return 0; /* not a stub */ |
c906108c SS |
3747 | } |
3748 | ||
3749 | ||
3750 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
3751 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
3752 | ||
3753 | int | |
acdb74a0 | 3754 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
3755 | { |
3756 | CORE_ADDR start_addr; | |
3757 | ||
3758 | /* Find the starting address of the function containing the PC. If the | |
3759 | caller didn't give us a name, look it up at the same time. */ | |
3760 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
3761 | return 0; | |
3762 | ||
3763 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3764 | { | |
3765 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
3766 | if (name[19] >= '0' && name[19] <= '9') | |
3767 | return 1; | |
3768 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 3769 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
3770 | else if (name[19] == 's' || name[19] == 'd') |
3771 | return pc == start_addr; | |
3772 | } | |
3773 | ||
c5aa993b | 3774 | return 0; /* not a stub */ |
c906108c SS |
3775 | } |
3776 | ||
3777 | ||
3778 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
3779 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
3780 | ||
3781 | int | |
acdb74a0 | 3782 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
3783 | { |
3784 | CORE_ADDR start_addr; | |
3785 | ||
3786 | /* Find the starting address of the function containing the PC. */ | |
3787 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
3788 | return 0; | |
3789 | ||
3790 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
3791 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3792 | || strcmp (name, "__mips16_ret_df") == 0) | |
3793 | return 1; | |
3794 | ||
3795 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 3796 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
3797 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
3798 | && (name[19] == 's' || name[19] == 'd') | |
3799 | && pc != start_addr) | |
3800 | return 1; | |
3801 | ||
c5aa993b | 3802 | return 0; /* not a stub */ |
c906108c SS |
3803 | } |
3804 | ||
3805 | ||
3806 | /* Return non-zero if the PC is in a library helper function that should | |
3807 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
3808 | ||
3809 | int | |
acdb74a0 | 3810 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
3811 | { |
3812 | char *name; | |
3813 | ||
3814 | /* Find the starting address and name of the function containing the PC. */ | |
3815 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
3816 | return 0; | |
3817 | ||
3818 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
3819 | that we want to ignore. */ | |
3820 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
3821 | || strcmp (name, "__mips16_ret_df") == 0); | |
3822 | } | |
3823 | ||
3824 | ||
3825 | /* Return a location where we can set a breakpoint that will be hit | |
3826 | when an inferior function call returns. This is normally the | |
3827 | program's entry point. Executables that don't have an entry | |
3828 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
3829 | whose address is the location where the breakpoint should be placed. */ | |
3830 | ||
3831 | CORE_ADDR | |
acdb74a0 | 3832 | mips_call_dummy_address (void) |
c906108c SS |
3833 | { |
3834 | struct minimal_symbol *sym; | |
3835 | ||
3836 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
3837 | if (sym) | |
3838 | return SYMBOL_VALUE_ADDRESS (sym); | |
3839 | else | |
3840 | return entry_point_address (); | |
3841 | } | |
3842 | ||
3843 | ||
9dcb560c | 3844 | /* If the current gcc for this target does not produce correct debugging |
b9a8e3bf JB |
3845 | information for float parameters, both prototyped and unprototyped, then |
3846 | define this macro. This forces gdb to always assume that floats are | |
3847 | passed as doubles and then converted in the callee. | |
3848 | ||
3849 | For the mips chip, it appears that the debug info marks the parameters as | |
3850 | floats regardless of whether the function is prototyped, but the actual | |
3851 | values are passed as doubles for the non-prototyped case and floats for | |
3852 | the prototyped case. Thus we choose to make the non-prototyped case work | |
3853 | for C and break the prototyped case, since the non-prototyped case is | |
3854 | probably much more common. (FIXME). */ | |
3855 | ||
3856 | static int | |
3857 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
3858 | { | |
3859 | return current_language->la_language == language_c; | |
3860 | } | |
3861 | ||
47a8d4ba AC |
3862 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
3863 | the register stored on the stack (32) is different to its real raw | |
3864 | size (64). The below ensures that registers are fetched from the | |
3865 | stack using their ABI size and then stored into the RAW_BUFFER | |
3866 | using their raw size. | |
3867 | ||
3868 | The alternative to adding this function would be to add an ABI | |
3869 | macro - REGISTER_STACK_SIZE(). */ | |
3870 | ||
3871 | static void | |
acdb74a0 AC |
3872 | mips_get_saved_register (char *raw_buffer, |
3873 | int *optimized, | |
3874 | CORE_ADDR *addrp, | |
3875 | struct frame_info *frame, | |
3876 | int regnum, | |
3877 | enum lval_type *lval) | |
47a8d4ba AC |
3878 | { |
3879 | CORE_ADDR addr; | |
3880 | ||
3881 | if (!target_has_registers) | |
3882 | error ("No registers."); | |
3883 | ||
3884 | /* Normal systems don't optimize out things with register numbers. */ | |
3885 | if (optimized != NULL) | |
3886 | *optimized = 0; | |
3887 | addr = find_saved_register (frame, regnum); | |
3888 | if (addr != 0) | |
3889 | { | |
3890 | if (lval != NULL) | |
3891 | *lval = lval_memory; | |
3892 | if (regnum == SP_REGNUM) | |
3893 | { | |
3894 | if (raw_buffer != NULL) | |
3895 | { | |
3896 | /* Put it back in target format. */ | |
3897 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
3898 | (LONGEST) addr); | |
3899 | } | |
3900 | if (addrp != NULL) | |
3901 | *addrp = 0; | |
3902 | return; | |
3903 | } | |
3904 | if (raw_buffer != NULL) | |
3905 | { | |
3906 | LONGEST val; | |
3907 | if (regnum < 32) | |
3908 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
3909 | saved. */ | |
3910 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
3911 | else | |
3912 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
3913 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
3914 | } | |
3915 | } | |
3916 | else | |
3917 | { | |
3918 | if (lval != NULL) | |
3919 | *lval = lval_register; | |
3920 | addr = REGISTER_BYTE (regnum); | |
3921 | if (raw_buffer != NULL) | |
3922 | read_register_gen (regnum, raw_buffer); | |
3923 | } | |
3924 | if (addrp != NULL) | |
3925 | *addrp = addr; | |
3926 | } | |
2acceee2 | 3927 | |
f7b9e9fc AC |
3928 | /* Immediately after a function call, return the saved pc. |
3929 | Can't always go through the frames for this because on some machines | |
3930 | the new frame is not set up until the new function executes | |
3931 | some instructions. */ | |
3932 | ||
3933 | static CORE_ADDR | |
3934 | mips_saved_pc_after_call (struct frame_info *frame) | |
3935 | { | |
6c997a34 | 3936 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
3937 | } |
3938 | ||
3939 | ||
88c72b7d AC |
3940 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
3941 | REGNUM */ | |
3942 | ||
3943 | static int | |
3944 | mips_stab_reg_to_regnum (int num) | |
3945 | { | |
3946 | if (num < 32) | |
3947 | return num; | |
3948 | else | |
3949 | return num + FP0_REGNUM - 38; | |
3950 | } | |
3951 | ||
3952 | /* Convert a ecoff register number to a gdb REGNUM */ | |
3953 | ||
3954 | static int | |
3955 | mips_ecoff_reg_to_regnum (int num) | |
3956 | { | |
3957 | if (num < 32) | |
3958 | return num; | |
3959 | else | |
3960 | return num + FP0_REGNUM - 32; | |
3961 | } | |
3962 | ||
fc0c74b1 AC |
3963 | /* Convert an integer into an address. By first converting the value |
3964 | into a pointer and then extracting it signed, the address is | |
3965 | guarenteed to be correctly sign extended. */ | |
3966 | ||
3967 | static CORE_ADDR | |
3968 | mips_integer_to_address (struct type *type, void *buf) | |
3969 | { | |
3970 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
3971 | LONGEST val = unpack_long (type, buf); | |
3972 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
3973 | return extract_signed_integer (tmp, | |
3974 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
3975 | } | |
3976 | ||
c2d11a7d | 3977 | static struct gdbarch * |
acdb74a0 AC |
3978 | mips_gdbarch_init (struct gdbarch_info info, |
3979 | struct gdbarch_list *arches) | |
c2d11a7d JM |
3980 | { |
3981 | static LONGEST mips_call_dummy_words[] = | |
3982 | {0}; | |
3983 | struct gdbarch *gdbarch; | |
3984 | struct gdbarch_tdep *tdep; | |
3985 | int elf_flags; | |
0dadbba0 | 3986 | enum mips_abi mips_abi; |
c2d11a7d | 3987 | |
1d06468c EZ |
3988 | /* Reset the disassembly info, in case it was set to something |
3989 | non-default. */ | |
3990 | tm_print_insn_info.flavour = bfd_target_unknown_flavour; | |
3991 | tm_print_insn_info.arch = bfd_arch_unknown; | |
3992 | tm_print_insn_info.mach = 0; | |
3993 | ||
c2d11a7d JM |
3994 | /* Extract the elf_flags if available */ |
3995 | if (info.abfd != NULL | |
3996 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3997 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
3998 | else | |
3999 | elf_flags = 0; | |
4000 | ||
0dadbba0 AC |
4001 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
4002 | switch ((elf_flags & EF_MIPS_ABI)) | |
4003 | { | |
4004 | case E_MIPS_ABI_O32: | |
4005 | mips_abi = MIPS_ABI_O32; | |
4006 | break; | |
4007 | case E_MIPS_ABI_O64: | |
4008 | mips_abi = MIPS_ABI_O64; | |
4009 | break; | |
4010 | case E_MIPS_ABI_EABI32: | |
4011 | mips_abi = MIPS_ABI_EABI32; | |
4012 | break; | |
4013 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 4014 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4015 | break; |
4016 | default: | |
acdb74a0 AC |
4017 | if ((elf_flags & EF_MIPS_ABI2)) |
4018 | mips_abi = MIPS_ABI_N32; | |
4019 | else | |
4020 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
4021 | break; |
4022 | } | |
acdb74a0 | 4023 | |
bf64bfd6 AC |
4024 | /* Try the architecture for any hint of the corect ABI */ |
4025 | if (mips_abi == MIPS_ABI_UNKNOWN | |
4026 | && info.bfd_arch_info != NULL | |
4027 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4028 | { | |
4029 | switch (info.bfd_arch_info->mach) | |
4030 | { | |
4031 | case bfd_mach_mips3900: | |
4032 | mips_abi = MIPS_ABI_EABI32; | |
4033 | break; | |
4034 | case bfd_mach_mips4100: | |
4035 | case bfd_mach_mips5000: | |
4036 | mips_abi = MIPS_ABI_EABI64; | |
4037 | break; | |
1d06468c EZ |
4038 | case bfd_mach_mips8000: |
4039 | case bfd_mach_mips10000: | |
4040 | mips_abi = MIPS_ABI_N32; | |
4041 | break; | |
bf64bfd6 AC |
4042 | } |
4043 | } | |
0dadbba0 AC |
4044 | #ifdef MIPS_DEFAULT_ABI |
4045 | if (mips_abi == MIPS_ABI_UNKNOWN) | |
4046 | mips_abi = MIPS_DEFAULT_ABI; | |
4047 | #endif | |
4b9b3959 AC |
4048 | |
4049 | if (gdbarch_debug) | |
4050 | { | |
4051 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 4052 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 4053 | elf_flags); |
4b9b3959 AC |
4054 | fprintf_unfiltered (gdb_stdlog, |
4055 | "mips_gdbarch_init: mips_abi = %d\n", | |
4056 | mips_abi); | |
4057 | } | |
0dadbba0 | 4058 | |
c2d11a7d JM |
4059 | /* try to find a pre-existing architecture */ |
4060 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4061 | arches != NULL; | |
4062 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4063 | { | |
4064 | /* MIPS needs to be pedantic about which ABI the object is | |
4065 | using. */ | |
9103eae0 | 4066 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 4067 | continue; |
9103eae0 | 4068 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 4069 | continue; |
c2d11a7d JM |
4070 | return arches->gdbarch; |
4071 | } | |
4072 | ||
4073 | /* Need a new architecture. Fill in a target specific vector. */ | |
4074 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4075 | gdbarch = gdbarch_alloc (&info, tdep); | |
4076 | tdep->elf_flags = elf_flags; | |
4077 | ||
4078 | /* Initially set everything according to the ABI. */ | |
4079 | set_gdbarch_short_bit (gdbarch, 16); | |
4080 | set_gdbarch_int_bit (gdbarch, 32); | |
4081 | set_gdbarch_float_bit (gdbarch, 32); | |
4082 | set_gdbarch_double_bit (gdbarch, 64); | |
4083 | set_gdbarch_long_double_bit (gdbarch, 64); | |
0dadbba0 | 4084 | tdep->mips_abi = mips_abi; |
1d06468c | 4085 | |
0dadbba0 | 4086 | switch (mips_abi) |
c2d11a7d | 4087 | { |
0dadbba0 | 4088 | case MIPS_ABI_O32: |
acdb74a0 | 4089 | tdep->mips_abi_string = "o32"; |
a5ea2558 | 4090 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 4091 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 4092 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
4093 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
4094 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
0dadbba0 | 4095 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 4096 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4097 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4098 | set_gdbarch_long_bit (gdbarch, 32); |
4099 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4100 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4101 | break; | |
0dadbba0 | 4102 | case MIPS_ABI_O64: |
acdb74a0 | 4103 | tdep->mips_abi_string = "o64"; |
a5ea2558 | 4104 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 4105 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 4106 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
4107 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
4108 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
0dadbba0 | 4109 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 4110 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 4111 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4112 | set_gdbarch_long_bit (gdbarch, 32); |
4113 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4114 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4115 | break; | |
0dadbba0 | 4116 | case MIPS_ABI_EABI32: |
acdb74a0 | 4117 | tdep->mips_abi_string = "eabi32"; |
a5ea2558 | 4118 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 4119 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 4120 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
4121 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4122 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4123 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4124 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4125 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4126 | set_gdbarch_long_bit (gdbarch, 32); |
4127 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4128 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4129 | break; | |
0dadbba0 | 4130 | case MIPS_ABI_EABI64: |
3259a172 | 4131 | tdep->mips_abi_string = "eabi64"; |
a5ea2558 | 4132 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 4133 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 4134 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
4135 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4136 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4137 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4138 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 4139 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4140 | set_gdbarch_long_bit (gdbarch, 64); |
4141 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4142 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4143 | break; | |
0dadbba0 | 4144 | case MIPS_ABI_N32: |
acdb74a0 | 4145 | tdep->mips_abi_string = "n32"; |
0dadbba0 AC |
4146 | tdep->mips_default_saved_regsize = 4; |
4147 | tdep->mips_default_stack_argsize = 8; | |
4148 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
4149 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4150 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4151 | tdep->mips_regs_have_home_p = 0; |
5213ab06 | 4152 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4153 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
4154 | set_gdbarch_long_bit (gdbarch, 32); |
4155 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4156 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1d06468c EZ |
4157 | |
4158 | /* Set up the disassembler info, so that we get the right | |
4159 | register names from libopcodes. */ | |
4160 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
4161 | tm_print_insn_info.arch = bfd_arch_mips; | |
4162 | if (info.bfd_arch_info != NULL | |
4163 | && info.bfd_arch_info->arch == bfd_arch_mips | |
4164 | && info.bfd_arch_info->mach) | |
4165 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
4166 | else | |
4167 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
0dadbba0 | 4168 | break; |
c2d11a7d | 4169 | default: |
acdb74a0 | 4170 | tdep->mips_abi_string = "default"; |
a5ea2558 | 4171 | tdep->mips_default_saved_regsize = MIPS_REGSIZE; |
0dadbba0 | 4172 | tdep->mips_default_stack_argsize = MIPS_REGSIZE; |
c2d11a7d | 4173 | tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8); |
acdb74a0 AC |
4174 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
4175 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
0dadbba0 | 4176 | tdep->mips_regs_have_home_p = 1; |
5213ab06 | 4177 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4178 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4179 | set_gdbarch_long_bit (gdbarch, 32); |
4180 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4181 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4182 | break; | |
4183 | } | |
4184 | ||
a5ea2558 AC |
4185 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
4186 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
4187 | comment: | |
4188 | ||
4189 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
4190 | flag in object files because to do so would make it impossible to | |
4191 | link with libraries compiled without "-gp32". This is | |
4192 | unnecessarily restrictive. | |
4193 | ||
4194 | We could solve this problem by adding "-gp32" multilibs to gcc, | |
4195 | but to set this flag before gcc is built with such multilibs will | |
4196 | break too many systems.'' | |
4197 | ||
4198 | But even more unhelpfully, the default linker output target for | |
4199 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
4200 | for 64-bit programs - you need to change the ABI to change this, | |
4201 | and not all gcc targets support that currently. Therefore using | |
4202 | this flag to detect 32-bit mode would do the wrong thing given | |
4203 | the current gcc - it would make GDB treat these 64-bit programs | |
4204 | as 32-bit programs by default. */ | |
4205 | ||
c2d11a7d JM |
4206 | /* enable/disable the MIPS FPU */ |
4207 | if (!mips_fpu_type_auto) | |
4208 | tdep->mips_fpu_type = mips_fpu_type; | |
4209 | else if (info.bfd_arch_info != NULL | |
4210 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4211 | switch (info.bfd_arch_info->mach) | |
4212 | { | |
b0069a17 | 4213 | case bfd_mach_mips3900: |
c2d11a7d | 4214 | case bfd_mach_mips4100: |
ed9a39eb | 4215 | case bfd_mach_mips4111: |
c2d11a7d JM |
4216 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
4217 | break; | |
bf64bfd6 AC |
4218 | case bfd_mach_mips4650: |
4219 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
4220 | break; | |
c2d11a7d JM |
4221 | default: |
4222 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4223 | break; | |
4224 | } | |
4225 | else | |
4226 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4227 | ||
4228 | /* MIPS version of register names. NOTE: At present the MIPS | |
4229 | register name management is part way between the old - | |
4230 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
4231 | Further work on it is required. */ | |
4232 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6c997a34 | 4233 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d JM |
4234 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
4235 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
4236 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); | |
4237 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); | |
4238 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4239 | ||
875e1767 AC |
4240 | /* Add/remove bits from an address. The MIPS needs be careful to |
4241 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
4242 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); | |
4243 | ||
10312cc4 AC |
4244 | /* There's a mess in stack frame creation. See comments in |
4245 | blockframe.c near reference to INIT_FRAME_PC_FIRST. */ | |
4246 | set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
7824d2f2 | 4247 | set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 4248 | |
88c72b7d AC |
4249 | /* Map debug register numbers onto internal register numbers. */ |
4250 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); | |
4251 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); | |
4252 | ||
c2d11a7d JM |
4253 | /* Initialize a frame */ |
4254 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
4255 | ||
4256 | /* MIPS version of CALL_DUMMY */ | |
4257 | ||
4258 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4259 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
4260 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
4261 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
4262 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
4263 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
4264 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
4265 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4266 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
4267 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
4268 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
4269 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
4270 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
4271 | set_gdbarch_push_arguments (gdbarch, mips_push_arguments); | |
4272 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
b9a8e3bf | 4273 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 4274 | |
c4093a6a | 4275 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
47a8d4ba | 4276 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 4277 | |
f7b9e9fc AC |
4278 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
4279 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4280 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
4281 | set_gdbarch_ieee_float (gdbarch, 1); | |
4282 | ||
4283 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
4284 | set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); | |
4285 | ||
fc0c74b1 AC |
4286 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
4287 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
4288 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
4b9b3959 AC |
4289 | return gdbarch; |
4290 | } | |
4291 | ||
4292 | static void | |
4293 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4294 | { | |
4295 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4296 | if (tdep != NULL) | |
c2d11a7d | 4297 | { |
acdb74a0 AC |
4298 | int ef_mips_arch; |
4299 | int ef_mips_32bitmode; | |
4300 | /* determine the ISA */ | |
4301 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
4302 | { | |
4303 | case E_MIPS_ARCH_1: | |
4304 | ef_mips_arch = 1; | |
4305 | break; | |
4306 | case E_MIPS_ARCH_2: | |
4307 | ef_mips_arch = 2; | |
4308 | break; | |
4309 | case E_MIPS_ARCH_3: | |
4310 | ef_mips_arch = 3; | |
4311 | break; | |
4312 | case E_MIPS_ARCH_4: | |
93d56215 | 4313 | ef_mips_arch = 4; |
acdb74a0 AC |
4314 | break; |
4315 | default: | |
93d56215 | 4316 | ef_mips_arch = 0; |
acdb74a0 AC |
4317 | break; |
4318 | } | |
4319 | /* determine the size of a pointer */ | |
4320 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
4321 | fprintf_unfiltered (file, |
4322 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 4323 | tdep->elf_flags); |
4b9b3959 | 4324 | fprintf_unfiltered (file, |
acdb74a0 AC |
4325 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
4326 | ef_mips_32bitmode); | |
4327 | fprintf_unfiltered (file, | |
4328 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
4329 | ef_mips_arch); | |
4330 | fprintf_unfiltered (file, | |
4331 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
4332 | tdep->mips_abi, | |
4333 | tdep->mips_abi_string); | |
4014092b AC |
4334 | fprintf_unfiltered (file, |
4335 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
4336 | mips_mask_address_p (), | |
4337 | tdep->default_mask_address_p); | |
c2d11a7d | 4338 | } |
4b9b3959 AC |
4339 | fprintf_unfiltered (file, |
4340 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4341 | FP_REGISTER_DOUBLE); | |
4342 | fprintf_unfiltered (file, | |
4343 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
4344 | MIPS_DEFAULT_FPU_TYPE, | |
4345 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4346 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4347 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4348 | : "???")); | |
4349 | fprintf_unfiltered (file, | |
4350 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
4351 | MIPS_EABI); | |
4352 | fprintf_unfiltered (file, | |
acdb74a0 AC |
4353 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
4354 | MIPS_LAST_FP_ARG_REGNUM, | |
4355 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
4356 | fprintf_unfiltered (file, |
4357 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
4358 | MIPS_FPU_TYPE, | |
4359 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4360 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4361 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4362 | : "???")); | |
4363 | fprintf_unfiltered (file, | |
4364 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
4365 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
4366 | fprintf_unfiltered (file, |
4367 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4368 | FP_REGISTER_DOUBLE); | |
4369 | fprintf_unfiltered (file, | |
4370 | "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n", | |
4371 | MIPS_REGS_HAVE_HOME_P); | |
4372 | fprintf_unfiltered (file, | |
4373 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
4374 | MIPS_DEFAULT_STACK_ARGSIZE); | |
4375 | fprintf_unfiltered (file, | |
4376 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
4377 | MIPS_STACK_ARGSIZE); | |
4378 | fprintf_unfiltered (file, | |
4379 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
4380 | MIPS_REGSIZE); | |
2475bac3 AC |
4381 | fprintf_unfiltered (file, |
4382 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
4383 | A0_REGNUM); | |
4384 | fprintf_unfiltered (file, | |
4385 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
4386 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
4387 | fprintf_unfiltered (file, | |
4388 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
4389 | XSTRING (ATTACH_DETACH)); | |
4390 | fprintf_unfiltered (file, | |
4391 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
4392 | BADVADDR_REGNUM); | |
4393 | fprintf_unfiltered (file, | |
4394 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
4395 | fprintf_unfiltered (file, | |
4396 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
4397 | CAUSE_REGNUM); | |
4398 | fprintf_unfiltered (file, | |
4399 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
4400 | CPLUS_MARKER); | |
4401 | fprintf_unfiltered (file, | |
4402 | "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n", | |
4403 | DEFAULT_MIPS_TYPE); | |
4404 | fprintf_unfiltered (file, | |
4405 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
4406 | XSTRING (DO_REGISTERS_INFO)); | |
4407 | fprintf_unfiltered (file, | |
4408 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
4409 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
4410 | fprintf_unfiltered (file, | |
4411 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
4412 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
4413 | fprintf_unfiltered (file, | |
4414 | "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n", | |
4415 | XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM))); | |
4416 | fprintf_unfiltered (file, | |
4417 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
4418 | FCRCS_REGNUM); | |
4419 | fprintf_unfiltered (file, | |
4420 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
4421 | FCRIR_REGNUM); | |
4422 | fprintf_unfiltered (file, | |
4423 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
4424 | FIRST_EMBED_REGNUM); | |
4425 | fprintf_unfiltered (file, | |
4426 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
4427 | FPA0_REGNUM); | |
4428 | fprintf_unfiltered (file, | |
4429 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
4430 | GDB_TARGET_IS_MIPS64); | |
4431 | fprintf_unfiltered (file, | |
4432 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
4433 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
4434 | fprintf_unfiltered (file, | |
4435 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
4436 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
4437 | fprintf_unfiltered (file, | |
4438 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
4439 | GEN_REG_SAVE_MASK); | |
4440 | fprintf_unfiltered (file, | |
4441 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
4442 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
4443 | fprintf_unfiltered (file, | |
4444 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
4445 | HI_REGNUM); | |
4446 | fprintf_unfiltered (file, | |
4447 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
4448 | fprintf_unfiltered (file, | |
4449 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
4450 | fprintf_unfiltered (file, | |
4451 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
4452 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
4453 | fprintf_unfiltered (file, |
4454 | "mips_dump_tdep: IN_SIGTRAMP # %s\n", | |
4455 | XSTRING (IN_SIGTRAMP (PC, NAME))); | |
4456 | fprintf_unfiltered (file, | |
4457 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
4458 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
4459 | fprintf_unfiltered (file, | |
4460 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
4461 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
4462 | fprintf_unfiltered (file, | |
4463 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
4464 | fprintf_unfiltered (file, | |
4465 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
4466 | LAST_EMBED_REGNUM); | |
4467 | fprintf_unfiltered (file, | |
4468 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
4469 | fprintf_unfiltered (file, | |
4470 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
4471 | LO_REGNUM); | |
4472 | #ifdef MACHINE_CPROC_FP_OFFSET | |
4473 | fprintf_unfiltered (file, | |
4474 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
4475 | MACHINE_CPROC_FP_OFFSET); | |
4476 | #endif | |
4477 | #ifdef MACHINE_CPROC_PC_OFFSET | |
4478 | fprintf_unfiltered (file, | |
4479 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
4480 | MACHINE_CPROC_PC_OFFSET); | |
4481 | #endif | |
4482 | #ifdef MACHINE_CPROC_SP_OFFSET | |
4483 | fprintf_unfiltered (file, | |
4484 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
4485 | MACHINE_CPROC_SP_OFFSET); | |
4486 | #endif | |
4487 | fprintf_unfiltered (file, | |
4488 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
4489 | fprintf_unfiltered (file, | |
4490 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
4491 | fprintf_unfiltered (file, | |
4492 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
4493 | MIPS16_INSTLEN); | |
4494 | fprintf_unfiltered (file, | |
4495 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
4496 | fprintf_unfiltered (file, | |
4497 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
4498 | fprintf_unfiltered (file, | |
4499 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
4500 | fprintf_unfiltered (file, | |
4501 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
4502 | MIPS_INSTLEN); | |
4503 | fprintf_unfiltered (file, | |
acdb74a0 AC |
4504 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
4505 | MIPS_LAST_ARG_REGNUM, | |
4506 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
4507 | fprintf_unfiltered (file, |
4508 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
4509 | MIPS_NUMREGS); | |
4510 | fprintf_unfiltered (file, | |
4511 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
4512 | fprintf_unfiltered (file, | |
4513 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
4514 | MIPS_SAVED_REGSIZE); | |
4515 | fprintf_unfiltered (file, | |
4516 | "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n"); | |
4517 | fprintf_unfiltered (file, | |
4518 | "mips_dump_tdep: MSYMBOL_SIZE # %s\n", | |
4519 | XSTRING (MSYMBOL_SIZE (MSYM))); | |
4520 | fprintf_unfiltered (file, | |
4521 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
4522 | fprintf_unfiltered (file, | |
4523 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
4524 | fprintf_unfiltered (file, | |
4525 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
4526 | fprintf_unfiltered (file, | |
4527 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
4528 | fprintf_unfiltered (file, | |
4529 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
4530 | PRID_REGNUM); | |
4531 | fprintf_unfiltered (file, | |
4532 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
4533 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
4534 | fprintf_unfiltered (file, | |
4535 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
4536 | fprintf_unfiltered (file, | |
4537 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
4538 | fprintf_unfiltered (file, | |
4539 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
4540 | fprintf_unfiltered (file, | |
4541 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
4542 | fprintf_unfiltered (file, | |
4543 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
4544 | fprintf_unfiltered (file, | |
4545 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
4546 | fprintf_unfiltered (file, | |
4547 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
4548 | fprintf_unfiltered (file, | |
4549 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
4550 | fprintf_unfiltered (file, | |
4551 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
4552 | fprintf_unfiltered (file, | |
4553 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
4554 | fprintf_unfiltered (file, | |
4555 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
4556 | fprintf_unfiltered (file, | |
4557 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
4558 | fprintf_unfiltered (file, | |
4559 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
4560 | PS_REGNUM); | |
4561 | fprintf_unfiltered (file, | |
4562 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
4563 | PUSH_FP_REGNUM); | |
4564 | fprintf_unfiltered (file, | |
4565 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
4566 | RA_REGNUM); | |
4567 | fprintf_unfiltered (file, | |
4568 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
4569 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4570 | fprintf_unfiltered (file, | |
4571 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
4572 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4573 | fprintf_unfiltered (file, | |
4574 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
4575 | fprintf_unfiltered (file, | |
4576 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
4577 | fprintf_unfiltered (file, | |
4578 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
4579 | #ifdef SAVED_BYTES | |
4580 | fprintf_unfiltered (file, | |
4581 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
4582 | SAVED_BYTES); | |
4583 | #endif | |
4584 | #ifdef SAVED_FP | |
4585 | fprintf_unfiltered (file, | |
4586 | "mips_dump_tdep: SAVED_FP = %d\n", | |
4587 | SAVED_FP); | |
4588 | #endif | |
4589 | #ifdef SAVED_PC | |
4590 | fprintf_unfiltered (file, | |
4591 | "mips_dump_tdep: SAVED_PC = %d\n", | |
4592 | SAVED_PC); | |
4593 | #endif | |
4594 | fprintf_unfiltered (file, | |
4595 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
4596 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
4597 | fprintf_unfiltered (file, | |
4598 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
4599 | fprintf_unfiltered (file, | |
4600 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
4601 | SIGFRAME_BASE); | |
4602 | fprintf_unfiltered (file, | |
4603 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
4604 | SIGFRAME_FPREGSAVE_OFF); | |
4605 | fprintf_unfiltered (file, | |
4606 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
4607 | SIGFRAME_PC_OFF); | |
4608 | fprintf_unfiltered (file, | |
4609 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
4610 | SIGFRAME_REGSAVE_OFF); | |
4611 | fprintf_unfiltered (file, | |
4612 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
4613 | SIGFRAME_REG_SIZE); | |
4614 | fprintf_unfiltered (file, | |
4615 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
4616 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
4617 | fprintf_unfiltered (file, | |
4618 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
4619 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
4620 | fprintf_unfiltered (file, | |
b0ed3589 AC |
4621 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
4622 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
4623 | fprintf_unfiltered (file, |
4624 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
4625 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
4626 | #ifdef STACK_END_ADDR | |
4627 | fprintf_unfiltered (file, | |
4628 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
4629 | STACK_END_ADDR); | |
4630 | #endif | |
4631 | fprintf_unfiltered (file, | |
4632 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
4633 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
4634 | fprintf_unfiltered (file, | |
4635 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
4636 | STEP_SKIPS_DELAY_P); | |
4637 | fprintf_unfiltered (file, | |
4638 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
4639 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
4640 | fprintf_unfiltered (file, | |
4641 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
4642 | T9_REGNUM); | |
4643 | fprintf_unfiltered (file, | |
4644 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
4645 | fprintf_unfiltered (file, | |
4646 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
4647 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
4648 | fprintf_unfiltered (file, | |
4649 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
4650 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
4651 | fprintf_unfiltered (file, | |
4652 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
4653 | fprintf_unfiltered (file, | |
4654 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
4655 | XSTRING (TM_PRINT_INSN_MACH)); | |
4656 | #ifdef TRACE_CLEAR | |
4657 | fprintf_unfiltered (file, | |
4658 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
4659 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
4660 | #endif | |
4661 | #ifdef TRACE_FLAVOR | |
4662 | fprintf_unfiltered (file, | |
4663 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
4664 | TRACE_FLAVOR); | |
4665 | #endif | |
4666 | #ifdef TRACE_FLAVOR_SIZE | |
4667 | fprintf_unfiltered (file, | |
4668 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
4669 | TRACE_FLAVOR_SIZE); | |
4670 | #endif | |
4671 | #ifdef TRACE_SET | |
4672 | fprintf_unfiltered (file, | |
4673 | "mips_dump_tdep: TRACE_SET # %s\n", | |
4674 | XSTRING (TRACE_SET (X,STATE))); | |
4675 | #endif | |
4676 | fprintf_unfiltered (file, | |
4677 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
4678 | #ifdef UNUSED_REGNUM | |
4679 | fprintf_unfiltered (file, | |
4680 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
4681 | UNUSED_REGNUM); | |
4682 | #endif | |
4683 | fprintf_unfiltered (file, | |
4684 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
4685 | V0_REGNUM); | |
4686 | fprintf_unfiltered (file, | |
4687 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
4688 | (long) VM_MIN_ADDRESS); | |
4689 | #ifdef VX_NUM_REGS | |
4690 | fprintf_unfiltered (file, | |
4691 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
4692 | VX_NUM_REGS); | |
4693 | #endif | |
4694 | fprintf_unfiltered (file, | |
4695 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
4696 | ZERO_REGNUM); | |
4697 | fprintf_unfiltered (file, | |
4698 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
4699 | _PROC_MAGIC_); | |
c2d11a7d JM |
4700 | } |
4701 | ||
c906108c | 4702 | void |
acdb74a0 | 4703 | _initialize_mips_tdep (void) |
c906108c SS |
4704 | { |
4705 | static struct cmd_list_element *mipsfpulist = NULL; | |
4706 | struct cmd_list_element *c; | |
4707 | ||
4b9b3959 | 4708 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 4709 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
4710 | tm_print_insn = gdb_print_insn_mips; |
4711 | ||
a5ea2558 AC |
4712 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
4713 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
4714 | "Various MIPS specific commands.", | |
4715 | &setmipscmdlist, "set mips ", 0, &setlist); | |
4716 | ||
4717 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
4718 | "Various MIPS specific commands.", | |
4719 | &showmipscmdlist, "show mips ", 0, &showlist); | |
4720 | ||
4721 | /* Allow the user to override the saved register size. */ | |
4722 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
4723 | class_obscure, |
4724 | size_enums, | |
4725 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
4726 | Set size of general purpose registers saved on the stack.\n\ |
4727 | This option can be set to one of:\n\ | |
4728 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
4729 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
4730 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
4731 | saved GP register size from information contained in the executable.\n\ | |
4732 | (default: auto)", | |
1ed2a135 | 4733 | &setmipscmdlist), |
a5ea2558 AC |
4734 | &showmipscmdlist); |
4735 | ||
d929b26f AC |
4736 | /* Allow the user to override the argument stack size. */ |
4737 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
4738 | class_obscure, | |
4739 | size_enums, | |
1ed2a135 | 4740 | &mips_stack_argsize_string, "\ |
d929b26f AC |
4741 | Set the amount of stack space reserved for each argument.\n\ |
4742 | This option can be set to one of:\n\ | |
4743 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
4744 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
4745 | auto - Allow GDB to determine the correct setting from the current\n\ | |
4746 | target and executable (default)", | |
4747 | &setmipscmdlist), | |
4748 | &showmipscmdlist); | |
4749 | ||
c906108c SS |
4750 | /* Let the user turn off floating point and set the fence post for |
4751 | heuristic_proc_start. */ | |
4752 | ||
4753 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
4754 | "Set use of MIPS floating-point coprocessor.", | |
4755 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
4756 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
4757 | "Select single-precision MIPS floating-point coprocessor.", | |
4758 | &mipsfpulist); | |
4759 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 4760 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
4761 | &mipsfpulist); |
4762 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
4763 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
4764 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
4765 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
4766 | "Select no MIPS floating-point coprocessor.", | |
4767 | &mipsfpulist); | |
4768 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
4769 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
4770 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
4771 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
4772 | "Select MIPS floating-point coprocessor automatically.", | |
4773 | &mipsfpulist); | |
4774 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
4775 | "Show current use of MIPS floating-point coprocessor target.", | |
4776 | &showlist); | |
4777 | ||
c2d11a7d | 4778 | #if !GDB_MULTI_ARCH |
c906108c SS |
4779 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
4780 | (char *) &tmp_mips_processor_type, | |
4781 | "Set the type of MIPS processor in use.\n\ | |
4782 | Set this to be able to access processor-type-specific registers.\n\ | |
4783 | ", | |
4784 | &setlist); | |
4785 | c->function.cfunc = mips_set_processor_type_command; | |
4786 | c = add_show_from_set (c, &showlist); | |
4787 | c->function.cfunc = mips_show_processor_type_command; | |
4788 | ||
4fcf66da AC |
4789 | tmp_mips_processor_type = xstrdup (DEFAULT_MIPS_TYPE); |
4790 | mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE), 0); | |
c2d11a7d | 4791 | #endif |
c906108c SS |
4792 | |
4793 | /* We really would like to have both "0" and "unlimited" work, but | |
4794 | command.c doesn't deal with that. So make it a var_zinteger | |
4795 | because the user can always use "999999" or some such for unlimited. */ | |
4796 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
4797 | (char *) &heuristic_fence_post, | |
4798 | "\ | |
4799 | Set the distance searched for the start of a function.\n\ | |
4800 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
4801 | program for the start of a function. This command sets the distance of the\n\ | |
4802 | search. The only need to set it is when debugging a stripped executable.", | |
4803 | &setlist); | |
4804 | /* We need to throw away the frame cache when we set this, since it | |
4805 | might change our ability to get backtraces. */ | |
4806 | c->function.sfunc = reinit_frame_cache_sfunc; | |
4807 | add_show_from_set (c, &showlist); | |
4808 | ||
4809 | /* Allow the user to control whether the upper bits of 64-bit | |
4810 | addresses should be zeroed. */ | |
4014092b AC |
4811 | c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, |
4812 | "Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
4813 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\ | |
4814 | the correct value.\n", | |
4815 | &setmipscmdlist); | |
4816 | add_cmd ("mask-address", no_class, show_mask_address, | |
4817 | "Show current mask-address value", &showmipscmdlist); | |
43e526b9 JM |
4818 | |
4819 | /* Allow the user to control the size of 32 bit registers within the | |
4820 | raw remote packet. */ | |
4821 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
4822 | class_obscure, | |
4823 | var_boolean, | |
4824 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
4825 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
4826 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
4827 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
4828 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
4829 | &setlist), | |
4830 | &showlist); | |
9ace0497 AC |
4831 | |
4832 | /* Debug this files internals. */ | |
4833 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
4834 | &mips_debug, "Set mips debugging.\n\ | |
4835 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
4836 | &showdebuglist); | |
c906108c | 4837 | } |
9ace0497 | 4838 |