Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
e0f7ec59 | 61 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 62 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 63 | |
dd824b04 DJ |
64 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
65 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
66 | #define ST0_FR (1 << 26) | |
67 | ||
b0069a17 AC |
68 | /* The sizes of floating point registers. */ |
69 | ||
70 | enum | |
71 | { | |
72 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
73 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
74 | }; | |
75 | ||
0dadbba0 | 76 | |
2e4ebe70 DJ |
77 | static const char *mips_abi_string; |
78 | ||
79 | static const char *mips_abi_strings[] = { | |
80 | "auto", | |
81 | "n32", | |
82 | "o32", | |
28d169de | 83 | "n64", |
2e4ebe70 DJ |
84 | "o64", |
85 | "eabi32", | |
86 | "eabi64", | |
87 | NULL | |
88 | }; | |
89 | ||
cce74817 | 90 | struct frame_extra_info |
6d82d43b AC |
91 | { |
92 | mips_extra_func_info_t proc_desc; | |
93 | int num_args; | |
94 | }; | |
cce74817 | 95 | |
d929b26f AC |
96 | /* Various MIPS ISA options (related to stack analysis) can be |
97 | overridden dynamically. Establish an enum/array for managing | |
98 | them. */ | |
99 | ||
53904c9e AC |
100 | static const char size_auto[] = "auto"; |
101 | static const char size_32[] = "32"; | |
102 | static const char size_64[] = "64"; | |
d929b26f | 103 | |
53904c9e | 104 | static const char *size_enums[] = { |
d929b26f AC |
105 | size_auto, |
106 | size_32, | |
107 | size_64, | |
a5ea2558 AC |
108 | 0 |
109 | }; | |
110 | ||
7a292a7a | 111 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 112 | support single-precision floating-point operations. */ |
c906108c SS |
113 | |
114 | enum mips_fpu_type | |
6d82d43b AC |
115 | { |
116 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
117 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
118 | MIPS_FPU_NONE /* No floating point. */ | |
119 | }; | |
c906108c SS |
120 | |
121 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
122 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
123 | #endif | |
124 | static int mips_fpu_type_auto = 1; | |
125 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 126 | |
9ace0497 | 127 | static int mips_debug = 0; |
7a292a7a | 128 | |
c2d11a7d JM |
129 | /* MIPS specific per-architecture information */ |
130 | struct gdbarch_tdep | |
6d82d43b AC |
131 | { |
132 | /* from the elf header */ | |
133 | int elf_flags; | |
134 | ||
135 | /* mips options */ | |
136 | enum mips_abi mips_abi; | |
137 | enum mips_abi found_abi; | |
138 | enum mips_fpu_type mips_fpu_type; | |
139 | int mips_last_arg_regnum; | |
140 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
141 | int default_mask_address_p; |
142 | /* Is the target using 64-bit raw integer registers but only | |
143 | storing a left-aligned 32-bit value in each? */ | |
144 | int mips64_transfers_32bit_regs_p; | |
145 | /* Indexes for various registers. IRIX and embedded have | |
146 | different values. This contains the "public" fields. Don't | |
147 | add any that do not need to be public. */ | |
148 | const struct mips_regnum *regnum; | |
149 | /* Register names table for the current register set. */ | |
150 | const char **mips_processor_reg_names; | |
151 | }; | |
c2d11a7d | 152 | |
fed7ba43 JB |
153 | static int |
154 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
155 | const char *from) | |
156 | { | |
157 | return 1; | |
158 | } | |
159 | ||
160 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
161 | They are implemented as a pair of 64bit doubles where the high | |
162 | part holds the result of the operation rounded to double, and | |
163 | the low double holds the difference between the exact result and | |
164 | the rounded result. So "high" + "low" contains the result with | |
165 | added precision. Unfortunately, the floatformat structure used | |
166 | by GDB is not powerful enough to describe this format. As a temporary | |
167 | measure, we define a 128bit floatformat that only uses the high part. | |
168 | We lose a bit of precision but that's probably the best we can do | |
169 | for now with the current infrastructure. */ | |
170 | ||
171 | static const struct floatformat floatformat_n32n64_long_double_big = | |
172 | { | |
173 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
174 | floatformat_intbit_no, | |
175 | "floatformat_ieee_double_big", | |
176 | n32n64_floatformat_always_valid | |
177 | }; | |
178 | ||
56cea623 AC |
179 | const struct mips_regnum * |
180 | mips_regnum (struct gdbarch *gdbarch) | |
181 | { | |
182 | return gdbarch_tdep (gdbarch)->regnum; | |
183 | } | |
184 | ||
185 | static int | |
186 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
187 | { | |
188 | return mips_regnum (gdbarch)->fp0 + 12; | |
189 | } | |
190 | ||
0dadbba0 | 191 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 192 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 193 | |
c2d11a7d | 194 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 195 | |
c2d11a7d | 196 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 197 | |
c2d11a7d | 198 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 199 | |
95404a3e AC |
200 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
201 | functions to test, set, or clear bit 0 of addresses. */ | |
202 | ||
203 | static CORE_ADDR | |
204 | is_mips16_addr (CORE_ADDR addr) | |
205 | { | |
206 | return ((addr) & 1); | |
207 | } | |
208 | ||
209 | static CORE_ADDR | |
210 | make_mips16_addr (CORE_ADDR addr) | |
211 | { | |
212 | return ((addr) | 1); | |
213 | } | |
214 | ||
215 | static CORE_ADDR | |
216 | unmake_mips16_addr (CORE_ADDR addr) | |
217 | { | |
218 | return ((addr) & ~1); | |
219 | } | |
220 | ||
22540ece AC |
221 | /* Return the contents of register REGNUM as a signed integer. */ |
222 | ||
223 | static LONGEST | |
224 | read_signed_register (int regnum) | |
225 | { | |
719ec221 | 226 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 227 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
228 | return (extract_signed_integer |
229 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
230 | } |
231 | ||
232 | static LONGEST | |
233 | read_signed_register_pid (int regnum, ptid_t ptid) | |
234 | { | |
235 | ptid_t save_ptid; | |
236 | LONGEST retval; | |
237 | ||
238 | if (ptid_equal (ptid, inferior_ptid)) | |
239 | return read_signed_register (regnum); | |
240 | ||
241 | save_ptid = inferior_ptid; | |
242 | ||
243 | inferior_ptid = ptid; | |
244 | ||
245 | retval = read_signed_register (regnum); | |
246 | ||
247 | inferior_ptid = save_ptid; | |
248 | ||
249 | return retval; | |
250 | } | |
251 | ||
d1973055 KB |
252 | /* Return the MIPS ABI associated with GDBARCH. */ |
253 | enum mips_abi | |
254 | mips_abi (struct gdbarch *gdbarch) | |
255 | { | |
256 | return gdbarch_tdep (gdbarch)->mips_abi; | |
257 | } | |
258 | ||
4246e332 | 259 | int |
1b13c4f6 | 260 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
261 | { |
262 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
263 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
264 | } | |
265 | ||
480d3dd2 AC |
266 | /* Return the currently configured (or set) saved register size. */ |
267 | ||
1b13c4f6 | 268 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 269 | |
d929b26f | 270 | static unsigned int |
13326b4e | 271 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 272 | { |
1b13c4f6 | 273 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
274 | switch (mips_abi (gdbarch)) |
275 | { | |
276 | case MIPS_ABI_EABI32: | |
277 | case MIPS_ABI_O32: | |
278 | return 4; | |
279 | case MIPS_ABI_N32: | |
280 | case MIPS_ABI_N64: | |
281 | case MIPS_ABI_O64: | |
282 | case MIPS_ABI_EABI64: | |
283 | return 8; | |
284 | case MIPS_ABI_UNKNOWN: | |
285 | case MIPS_ABI_LAST: | |
286 | default: | |
287 | internal_error (__FILE__, __LINE__, "bad switch"); | |
288 | } | |
1b13c4f6 | 289 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 290 | return 8; |
1b13c4f6 | 291 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
292 | return 4; |
293 | } | |
294 | ||
71b8ef93 | 295 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 296 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 297 | "info" field is used for this purpose. |
5a89d8aa MS |
298 | |
299 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
300 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
301 | minimal symbol to mark it as a 16-bit function | |
302 | ||
f594e5e9 | 303 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 304 | |
5a89d8aa | 305 | static void |
6d82d43b AC |
306 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
307 | { | |
308 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
309 | { | |
310 | MSYMBOL_INFO (msym) = (char *) | |
311 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
312 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
313 | } | |
5a89d8aa MS |
314 | } |
315 | ||
71b8ef93 MS |
316 | static int |
317 | msymbol_is_special (struct minimal_symbol *msym) | |
318 | { | |
319 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
320 | } | |
321 | ||
88658117 AC |
322 | /* XFER a value from the big/little/left end of the register. |
323 | Depending on the size of the value it might occupy the entire | |
324 | register or just part of it. Make an allowance for this, aligning | |
325 | things accordingly. */ | |
326 | ||
327 | static void | |
328 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
329 | enum bfd_endian endian, bfd_byte * in, |
330 | const bfd_byte * out, int buf_offset) | |
88658117 | 331 | { |
88658117 | 332 | int reg_offset = 0; |
a4b8ebc8 | 333 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
334 | /* Need to transfer the left or right part of the register, based on |
335 | the targets byte order. */ | |
88658117 AC |
336 | switch (endian) |
337 | { | |
338 | case BFD_ENDIAN_BIG: | |
719ec221 | 339 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
340 | break; |
341 | case BFD_ENDIAN_LITTLE: | |
342 | reg_offset = 0; | |
343 | break; | |
6d82d43b | 344 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
345 | reg_offset = 0; |
346 | break; | |
347 | default: | |
348 | internal_error (__FILE__, __LINE__, "bad switch"); | |
349 | } | |
350 | if (mips_debug) | |
cb1d2653 AC |
351 | fprintf_unfiltered (gdb_stderr, |
352 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
353 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
354 | if (mips_debug && out != NULL) |
355 | { | |
356 | int i; | |
cb1d2653 | 357 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 358 | for (i = 0; i < length; i++) |
cb1d2653 | 359 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
360 | } |
361 | if (in != NULL) | |
6d82d43b AC |
362 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
363 | in + buf_offset); | |
88658117 | 364 | if (out != NULL) |
6d82d43b AC |
365 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
366 | out + buf_offset); | |
88658117 AC |
367 | if (mips_debug && in != NULL) |
368 | { | |
369 | int i; | |
cb1d2653 | 370 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 371 | for (i = 0; i < length; i++) |
cb1d2653 | 372 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
373 | } |
374 | if (mips_debug) | |
375 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
376 | } | |
377 | ||
dd824b04 DJ |
378 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
379 | compatiblity mode. A return value of 1 means that we have | |
380 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
381 | ||
382 | static int | |
383 | mips2_fp_compat (void) | |
384 | { | |
385 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
386 | meaningful. */ | |
6d82d43b AC |
387 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
388 | 4) | |
dd824b04 DJ |
389 | return 0; |
390 | ||
391 | #if 0 | |
392 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
393 | in all the places we deal with FP registers. PR gdb/413. */ | |
394 | /* Otherwise check the FR bit in the status register - it controls | |
395 | the FP compatiblity mode. If it is clear we are in compatibility | |
396 | mode. */ | |
397 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
398 | return 1; | |
399 | #endif | |
361d1df0 | 400 | |
dd824b04 DJ |
401 | return 0; |
402 | } | |
403 | ||
d929b26f | 404 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 405 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
406 | data allocated after the registers have run out. */ |
407 | ||
53904c9e | 408 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
409 | |
410 | static unsigned int | |
13326b4e | 411 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
412 | { |
413 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 414 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
415 | else if (mips_stack_argsize_string == size_64) |
416 | return 8; | |
6d82d43b | 417 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
418 | return 4; |
419 | } | |
420 | ||
7a292a7a | 421 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 422 | |
570b8f7c | 423 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
465f7520 | 424 | struct frame_info *); |
eec63939 AC |
425 | static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc, |
426 | CORE_ADDR *addrptr); | |
c906108c | 427 | |
a14ed312 | 428 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 429 | |
a14ed312 | 430 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 431 | |
a14ed312 | 432 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 433 | |
570b8f7c | 434 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
465f7520 | 435 | struct frame_info *next_frame); |
c906108c | 436 | |
a14ed312 KB |
437 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
438 | mips_extra_func_info_t proc_desc); | |
c906108c | 439 | |
67b2c998 DJ |
440 | static struct type *mips_float_register_type (void); |
441 | static struct type *mips_double_register_type (void); | |
442 | ||
acdb74a0 AC |
443 | /* The list of available "set mips " and "show mips " commands */ |
444 | ||
445 | static struct cmd_list_element *setmipscmdlist = NULL; | |
446 | static struct cmd_list_element *showmipscmdlist = NULL; | |
447 | ||
5e2e9765 KB |
448 | /* Integer registers 0 thru 31 are handled explicitly by |
449 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
450 | are listed in the followign tables. */ |
451 | ||
6d82d43b AC |
452 | enum |
453 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
454 | |
455 | /* Generic MIPS. */ | |
456 | ||
457 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
458 | "sr", "lo", "hi", "bad", "cause", "pc", |
459 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
460 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
461 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
462 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
463 | "fsr", "fir", "" /*"fp" */ , "", | |
464 | "", "", "", "", "", "", "", "", | |
465 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
466 | }; |
467 | ||
468 | /* Names of IDT R3041 registers. */ | |
469 | ||
470 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
471 | "sr", "lo", "hi", "bad", "cause", "pc", |
472 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
473 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
474 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
475 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
476 | "fsr", "fir", "", /*"fp" */ "", | |
477 | "", "", "bus", "ccfg", "", "", "", "", | |
478 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
479 | }; |
480 | ||
481 | /* Names of tx39 registers. */ | |
482 | ||
483 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
484 | "sr", "lo", "hi", "bad", "cause", "pc", |
485 | "", "", "", "", "", "", "", "", | |
486 | "", "", "", "", "", "", "", "", | |
487 | "", "", "", "", "", "", "", "", | |
488 | "", "", "", "", "", "", "", "", | |
489 | "", "", "", "", | |
490 | "", "", "", "", "", "", "", "", | |
491 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
492 | }; |
493 | ||
494 | /* Names of IRIX registers. */ | |
495 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
496 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
497 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
498 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
499 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
500 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
501 | }; |
502 | ||
cce74817 | 503 | |
5e2e9765 | 504 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 505 | static const char * |
5e2e9765 | 506 | mips_register_name (int regno) |
cce74817 | 507 | { |
691c0433 | 508 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
509 | /* GPR names for all ABIs other than n32/n64. */ |
510 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
511 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
512 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
513 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
514 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
515 | }; |
516 | ||
517 | /* GPR names for n32 and n64 ABIs. */ | |
518 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
519 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
520 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
521 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
522 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
523 | }; |
524 | ||
525 | enum mips_abi abi = mips_abi (current_gdbarch); | |
526 | ||
a4b8ebc8 AC |
527 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
528 | don't make the raw register names visible. */ | |
529 | int rawnum = regno % NUM_REGS; | |
530 | if (regno < NUM_REGS) | |
531 | return ""; | |
532 | ||
5e2e9765 KB |
533 | /* The MIPS integer registers are always mapped from 0 to 31. The |
534 | names of the registers (which reflects the conventions regarding | |
535 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 536 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
537 | { |
538 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 539 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 540 | else |
a4b8ebc8 | 541 | return mips_gpr_names[rawnum]; |
5e2e9765 | 542 | } |
a4b8ebc8 | 543 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
544 | { |
545 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
546 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
547 | } | |
5e2e9765 KB |
548 | else |
549 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 550 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 551 | } |
5e2e9765 | 552 | |
a4b8ebc8 | 553 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 554 | |
a4b8ebc8 AC |
555 | static int |
556 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
557 | struct reggroup *reggroup) | |
558 | { | |
559 | int vector_p; | |
560 | int float_p; | |
561 | int raw_p; | |
562 | int rawnum = regnum % NUM_REGS; | |
563 | int pseudo = regnum / NUM_REGS; | |
564 | if (reggroup == all_reggroup) | |
565 | return pseudo; | |
566 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
567 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
568 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
569 | (gdbarch), as not all architectures are multi-arch. */ | |
570 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 571 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
572 | return 0; |
573 | if (reggroup == float_reggroup) | |
574 | return float_p && pseudo; | |
575 | if (reggroup == vector_reggroup) | |
576 | return vector_p && pseudo; | |
577 | if (reggroup == general_reggroup) | |
578 | return (!vector_p && !float_p) && pseudo; | |
579 | /* Save the pseudo registers. Need to make certain that any code | |
580 | extracting register values from a saved register cache also uses | |
581 | pseudo registers. */ | |
582 | if (reggroup == save_reggroup) | |
583 | return raw_p && pseudo; | |
584 | /* Restore the same pseudo register. */ | |
585 | if (reggroup == restore_reggroup) | |
586 | return raw_p && pseudo; | |
6d82d43b | 587 | return 0; |
a4b8ebc8 AC |
588 | } |
589 | ||
590 | /* Map the symbol table registers which live in the range [1 * | |
591 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 592 | registers. Take care of alignment and size problems. */ |
c5aa993b | 593 | |
a4b8ebc8 AC |
594 | static void |
595 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
596 | int cookednum, void *buf) | |
597 | { | |
47ebcfbe | 598 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 599 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 600 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 601 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
602 | else if (register_size (gdbarch, rawnum) > |
603 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
604 | { |
605 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
606 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
607 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
608 | else | |
609 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
610 | } | |
611 | else | |
612 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
613 | } |
614 | ||
615 | static void | |
6d82d43b AC |
616 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
617 | struct regcache *regcache, int cookednum, | |
618 | const void *buf) | |
a4b8ebc8 | 619 | { |
47ebcfbe | 620 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 621 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 622 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 623 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
624 | else if (register_size (gdbarch, rawnum) > |
625 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
626 | { |
627 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
628 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
629 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
630 | else | |
631 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
632 | } | |
633 | else | |
634 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 635 | } |
c5aa993b | 636 | |
c906108c | 637 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 638 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
639 | |
640 | /* Heuristic_proc_start may hunt through the text section for a long | |
641 | time across a 2400 baud serial line. Allows the user to limit this | |
642 | search. */ | |
643 | ||
644 | static unsigned int heuristic_fence_post = 0; | |
645 | ||
c5aa993b JM |
646 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
647 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
648 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
649 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
650 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
651 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
652 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
653 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
654 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
655 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
656 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
657 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
658 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
659 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
660 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
661 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
662 | ||
46cd78fb | 663 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
664 | register N. NOTE: This defines the pseudo register type so need to |
665 | rebuild the architecture vector. */ | |
43e526b9 JM |
666 | |
667 | static int mips64_transfers_32bit_regs_p = 0; | |
668 | ||
719ec221 AC |
669 | static void |
670 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
671 | struct cmd_list_element *c) | |
43e526b9 | 672 | { |
719ec221 AC |
673 | struct gdbarch_info info; |
674 | gdbarch_info_init (&info); | |
675 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
676 | instead of relying on globals. Doing that would let generic code | |
677 | handle the search for this specific architecture. */ | |
678 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 679 | { |
719ec221 AC |
680 | mips64_transfers_32bit_regs_p = 0; |
681 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 682 | } |
a4b8ebc8 AC |
683 | } |
684 | ||
47ebcfbe | 685 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 686 | |
ff2e87ac AC |
687 | static int |
688 | mips_convert_register_p (int regnum, struct type *type) | |
689 | { | |
690 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 691 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
692 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
693 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 694 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
695 | } |
696 | ||
42c466d7 | 697 | static void |
ff2e87ac AC |
698 | mips_register_to_value (struct frame_info *frame, int regnum, |
699 | struct type *type, void *to) | |
102182a9 | 700 | { |
7f5f525d AC |
701 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
702 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
703 | } |
704 | ||
42c466d7 | 705 | static void |
ff2e87ac AC |
706 | mips_value_to_register (struct frame_info *frame, int regnum, |
707 | struct type *type, const void *from) | |
102182a9 | 708 | { |
ff2e87ac AC |
709 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
710 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
711 | } |
712 | ||
a4b8ebc8 AC |
713 | /* Return the GDB type object for the "standard" data type of data in |
714 | register REG. */ | |
78fde5f8 KB |
715 | |
716 | static struct type * | |
a4b8ebc8 AC |
717 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
718 | { | |
5ef80fb0 | 719 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
720 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
721 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 722 | { |
5ef80fb0 | 723 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 724 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
725 | switch (gdbarch_byte_order (gdbarch)) |
726 | { | |
727 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 728 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
729 | return builtin_type_ieee_single_big; |
730 | else | |
731 | return builtin_type_ieee_double_big; | |
732 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 733 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
734 | return builtin_type_ieee_single_little; |
735 | else | |
736 | return builtin_type_ieee_double_little; | |
737 | case BFD_ENDIAN_UNKNOWN: | |
738 | default: | |
739 | internal_error (__FILE__, __LINE__, "bad switch"); | |
740 | } | |
a6425924 | 741 | } |
d5ac5a39 AC |
742 | else if (regnum < NUM_REGS) |
743 | { | |
744 | /* The raw or ISA registers. These are all sized according to | |
745 | the ISA regsize. */ | |
746 | if (mips_isa_regsize (gdbarch) == 4) | |
747 | return builtin_type_int32; | |
748 | else | |
749 | return builtin_type_int64; | |
750 | } | |
78fde5f8 | 751 | else |
d5ac5a39 AC |
752 | { |
753 | /* The cooked or ABI registers. These are sized according to | |
754 | the ABI (with a few complications). */ | |
755 | if (regnum >= (NUM_REGS | |
756 | + mips_regnum (current_gdbarch)->fp_control_status) | |
757 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
758 | /* The pseudo/cooked view of the embedded registers is always | |
759 | 32-bit. The raw view is handled below. */ | |
760 | return builtin_type_int32; | |
761 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
762 | /* The target, while possibly using a 64-bit register buffer, | |
763 | is only transfering 32-bits of each integer register. | |
764 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
765 | return builtin_type_int32; | |
766 | else if (mips_abi_regsize (gdbarch) == 4) | |
767 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
768 | 32- or 64-bit). */ | |
769 | return builtin_type_int32; | |
770 | else | |
771 | /* 64-bit ABI. */ | |
772 | return builtin_type_int64; | |
773 | } | |
78fde5f8 KB |
774 | } |
775 | ||
bcb0cc15 MS |
776 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
777 | ||
778 | static CORE_ADDR | |
779 | mips_read_sp (void) | |
780 | { | |
f10683bb | 781 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
782 | } |
783 | ||
c906108c | 784 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 785 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
786 | |
787 | static int | |
480d3dd2 | 788 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
789 | { |
790 | switch (mask_address_var) | |
791 | { | |
7f19b9a2 | 792 | case AUTO_BOOLEAN_TRUE: |
4014092b | 793 | return 1; |
7f19b9a2 | 794 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
795 | return 0; |
796 | break; | |
7f19b9a2 | 797 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 798 | return tdep->default_mask_address_p; |
4014092b | 799 | default: |
6d82d43b | 800 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 801 | return -1; |
361d1df0 | 802 | } |
4014092b AC |
803 | } |
804 | ||
805 | static void | |
e9e68a56 | 806 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 807 | { |
480d3dd2 | 808 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
809 | switch (mask_address_var) |
810 | { | |
7f19b9a2 | 811 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
812 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
813 | break; | |
7f19b9a2 | 814 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
815 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
816 | break; | |
7f19b9a2 | 817 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
818 | printf_filtered |
819 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
820 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
821 | break; |
822 | default: | |
6d82d43b | 823 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 824 | break; |
361d1df0 | 825 | } |
4014092b | 826 | } |
c906108c | 827 | |
c906108c SS |
828 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
829 | ||
830 | static int | |
831 | pc_is_mips16 (bfd_vma memaddr) | |
832 | { | |
833 | struct minimal_symbol *sym; | |
834 | ||
835 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 836 | if (is_mips16_addr (memaddr)) |
c906108c SS |
837 | return 1; |
838 | ||
839 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
840 | the high bit of the info field. Use this to decide if the function is | |
841 | MIPS16 or normal MIPS. */ | |
842 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
843 | if (sym) | |
71b8ef93 | 844 | return msymbol_is_special (sym); |
c906108c SS |
845 | else |
846 | return 0; | |
847 | } | |
848 | ||
b2fa5097 | 849 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
850 | all registers should be sign extended for simplicity? */ |
851 | ||
852 | static CORE_ADDR | |
39f77062 | 853 | mips_read_pc (ptid_t ptid) |
6c997a34 | 854 | { |
b6cb9035 AC |
855 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
856 | } | |
857 | ||
58dfe9ff AC |
858 | static CORE_ADDR |
859 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
860 | { | |
edfae063 AC |
861 | return frame_unwind_register_signed (next_frame, |
862 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
863 | } | |
864 | ||
865 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
866 | dummy frame. The frame ID's base needs to match the TOS value | |
867 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
868 | breakpoint. */ | |
869 | ||
870 | static struct frame_id | |
871 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
872 | { | |
f10683bb | 873 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 874 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
875 | } |
876 | ||
b6cb9035 AC |
877 | static void |
878 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
879 | { | |
880 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 881 | } |
c906108c SS |
882 | |
883 | /* This returns the PC of the first inst after the prologue. If we can't | |
884 | find the prologue, then return 0. */ | |
885 | ||
886 | static CORE_ADDR | |
6d82d43b | 887 | after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc) |
c906108c SS |
888 | { |
889 | struct symtab_and_line sal; | |
890 | CORE_ADDR func_addr, func_end; | |
891 | ||
465f7520 | 892 | /* Pass a NULL next_frame to find_proc_desc. We should not attempt |
479412cd DJ |
893 | to read the stack pointer from the current machine state, because |
894 | the current machine state has nothing to do with the information | |
895 | we need from the proc_desc; and the process may or may not exist | |
896 | right now. */ | |
c906108c | 897 | if (!proc_desc) |
465f7520 | 898 | proc_desc = find_proc_desc (pc, NULL); |
c906108c SS |
899 | |
900 | if (proc_desc) | |
901 | { | |
902 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 903 | strongly suspect that frameless always means prologueless... */ |
f10683bb | 904 | if (PROC_FRAME_REG (proc_desc) == MIPS_SP_REGNUM |
c906108c SS |
905 | && PROC_FRAME_OFFSET (proc_desc) == 0) |
906 | return 0; | |
907 | } | |
908 | ||
909 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
910 | return 0; /* Unknown */ | |
911 | ||
912 | sal = find_pc_line (func_addr, 0); | |
913 | ||
914 | if (sal.end < func_end) | |
915 | return sal.end; | |
916 | ||
917 | /* The line after the prologue is after the end of the function. In this | |
918 | case, tell the caller to find the prologue the hard way. */ | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
923 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
924 | set the appropriate bit in the general register mask or float register mask | |
925 | to indicate which register is saved. This is a helper function | |
926 | for mips_find_saved_regs. */ | |
927 | ||
928 | static void | |
acdb74a0 AC |
929 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
930 | unsigned long *float_mask) | |
c906108c SS |
931 | { |
932 | int reg; | |
933 | ||
6d82d43b | 934 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
c906108c SS |
935 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
936 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
937 | { | |
938 | /* It might be possible to use the instruction to | |
c5aa993b JM |
939 | find the offset, rather than the code below which |
940 | is based on things being in a certain order in the | |
941 | frame, but figuring out what the instruction's offset | |
942 | is relative to might be a little tricky. */ | |
c906108c SS |
943 | reg = (inst & 0x001f0000) >> 16; |
944 | *gen_mask |= (1 << reg); | |
945 | } | |
946 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
6d82d43b | 947 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
c5aa993b | 948 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
c906108c SS |
949 | |
950 | { | |
951 | reg = ((inst & 0x001f0000) >> 16); | |
952 | *float_mask |= (1 << reg); | |
953 | } | |
954 | } | |
955 | ||
956 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
957 | set the appropriate bit in the general register or float register mask | |
958 | to indicate which register is saved. This is a helper function | |
959 | for mips_find_saved_regs. */ | |
960 | ||
961 | static void | |
acdb74a0 | 962 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 963 | { |
c5aa993b | 964 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
965 | { |
966 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
967 | *gen_mask |= (1 << reg); | |
968 | } | |
c5aa993b | 969 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
970 | { |
971 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
972 | *gen_mask |= (1 << reg); | |
973 | } | |
c5aa993b | 974 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
975 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
976 | *gen_mask |= (1 << RA_REGNUM); | |
977 | } | |
978 | ||
979 | ||
980 | /* Fetch and return instruction from the specified location. If the PC | |
981 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
982 | ||
983 | static t_inst | |
acdb74a0 | 984 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
985 | { |
986 | char buf[MIPS_INSTLEN]; | |
987 | int instlen; | |
988 | int status; | |
989 | ||
990 | if (pc_is_mips16 (addr)) | |
991 | { | |
992 | instlen = MIPS16_INSTLEN; | |
95404a3e | 993 | addr = unmake_mips16_addr (addr); |
c906108c SS |
994 | } |
995 | else | |
c5aa993b | 996 | instlen = MIPS_INSTLEN; |
1f602b35 | 997 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
998 | if (status) |
999 | memory_error (status, addr); | |
1000 | return extract_unsigned_integer (buf, instlen); | |
1001 | } | |
1002 | ||
edfae063 AC |
1003 | static ULONGEST |
1004 | mips16_fetch_instruction (CORE_ADDR addr) | |
1005 | { | |
1006 | char buf[MIPS_INSTLEN]; | |
1007 | int instlen; | |
1008 | int status; | |
1009 | ||
1010 | instlen = MIPS16_INSTLEN; | |
1011 | addr = unmake_mips16_addr (addr); | |
1f602b35 | 1012 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
1013 | if (status) |
1014 | memory_error (status, addr); | |
1015 | return extract_unsigned_integer (buf, instlen); | |
1016 | } | |
1017 | ||
1018 | static ULONGEST | |
1019 | mips32_fetch_instruction (CORE_ADDR addr) | |
1020 | { | |
1021 | char buf[MIPS_INSTLEN]; | |
1022 | int instlen; | |
1023 | int status; | |
1024 | instlen = MIPS_INSTLEN; | |
1f602b35 | 1025 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
1026 | if (status) |
1027 | memory_error (status, addr); | |
1028 | return extract_unsigned_integer (buf, instlen); | |
1029 | } | |
1030 | ||
c906108c SS |
1031 | |
1032 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
1033 | #define mips32_op(x) (x >> 26) |
1034 | #define itype_op(x) (x >> 26) | |
1035 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1036 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1037 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1038 | |
e135b889 DJ |
1039 | #define jtype_op(x) (x >> 26) |
1040 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1041 | |
e135b889 DJ |
1042 | #define rtype_op(x) (x >> 26) |
1043 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1044 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1045 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1046 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1047 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1048 | |
1049 | static CORE_ADDR | |
c5aa993b JM |
1050 | mips32_relative_offset (unsigned long inst) |
1051 | { | |
1052 | long x; | |
1053 | x = itype_immediate (inst); | |
1054 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1055 | { |
c5aa993b | 1056 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1057 | } |
c5aa993b JM |
1058 | x = x << 2; |
1059 | return x; | |
c906108c SS |
1060 | } |
1061 | ||
1062 | /* Determine whate to set a single step breakpoint while considering | |
1063 | branch prediction */ | |
5a89d8aa | 1064 | static CORE_ADDR |
c5aa993b JM |
1065 | mips32_next_pc (CORE_ADDR pc) |
1066 | { | |
1067 | unsigned long inst; | |
1068 | int op; | |
1069 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1070 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1071 | { |
e135b889 | 1072 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1073 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1074 | { |
e135b889 | 1075 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1076 | switch (op) |
1077 | { | |
e135b889 DJ |
1078 | case 0: /* BEQL */ |
1079 | goto equal_branch; | |
1080 | case 1: /* BNEL */ | |
1081 | goto neq_branch; | |
1082 | case 2: /* BLEZL */ | |
1083 | goto less_branch; | |
1084 | case 3: /* BGTZ */ | |
1085 | goto greater_branch; | |
c5aa993b JM |
1086 | default: |
1087 | pc += 4; | |
c906108c SS |
1088 | } |
1089 | } | |
e135b889 | 1090 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1091 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1092 | { |
1093 | int tf = itype_rt (inst) & 0x01; | |
1094 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1095 | int fcrcs = |
1096 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1097 | fp_control_status); | |
e135b889 DJ |
1098 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1099 | ||
1100 | if (((cond >> cnum) & 0x01) == tf) | |
1101 | pc += mips32_relative_offset (inst) + 4; | |
1102 | else | |
1103 | pc += 8; | |
1104 | } | |
c5aa993b JM |
1105 | else |
1106 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1107 | } |
1108 | else | |
c5aa993b JM |
1109 | { /* This gets way messy */ |
1110 | ||
c906108c | 1111 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1112 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1113 | { |
c5aa993b JM |
1114 | case 0: /* SPECIAL */ |
1115 | op = rtype_funct (inst); | |
1116 | switch (op) | |
1117 | { | |
1118 | case 8: /* JR */ | |
1119 | case 9: /* JALR */ | |
6c997a34 AC |
1120 | /* Set PC to that address */ |
1121 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1122 | break; |
1123 | default: | |
1124 | pc += 4; | |
1125 | } | |
1126 | ||
6d82d43b | 1127 | break; /* end SPECIAL */ |
c5aa993b | 1128 | case 1: /* REGIMM */ |
c906108c | 1129 | { |
e135b889 DJ |
1130 | op = itype_rt (inst); /* branch condition */ |
1131 | switch (op) | |
c906108c | 1132 | { |
c5aa993b | 1133 | case 0: /* BLTZ */ |
e135b889 DJ |
1134 | case 2: /* BLTZL */ |
1135 | case 16: /* BLTZAL */ | |
c5aa993b | 1136 | case 18: /* BLTZALL */ |
c906108c | 1137 | less_branch: |
6c997a34 | 1138 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1139 | pc += mips32_relative_offset (inst) + 4; |
1140 | else | |
1141 | pc += 8; /* after the delay slot */ | |
1142 | break; | |
e135b889 | 1143 | case 1: /* BGEZ */ |
c5aa993b JM |
1144 | case 3: /* BGEZL */ |
1145 | case 17: /* BGEZAL */ | |
1146 | case 19: /* BGEZALL */ | |
6c997a34 | 1147 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1148 | pc += mips32_relative_offset (inst) + 4; |
1149 | else | |
1150 | pc += 8; /* after the delay slot */ | |
1151 | break; | |
e135b889 | 1152 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1153 | default: |
1154 | pc += 4; | |
c906108c SS |
1155 | } |
1156 | } | |
6d82d43b | 1157 | break; /* end REGIMM */ |
c5aa993b JM |
1158 | case 2: /* J */ |
1159 | case 3: /* JAL */ | |
1160 | { | |
1161 | unsigned long reg; | |
1162 | reg = jtype_target (inst) << 2; | |
e135b889 | 1163 | /* Upper four bits get never changed... */ |
c5aa993b | 1164 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1165 | } |
c5aa993b JM |
1166 | break; |
1167 | /* FIXME case JALX : */ | |
1168 | { | |
1169 | unsigned long reg; | |
1170 | reg = jtype_target (inst) << 2; | |
1171 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1172 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1173 | } | |
c5aa993b | 1174 | break; /* The new PC will be alternate mode */ |
e135b889 | 1175 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1176 | equal_branch: |
6c997a34 AC |
1177 | if (read_signed_register (itype_rs (inst)) == |
1178 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1179 | pc += mips32_relative_offset (inst) + 4; |
1180 | else | |
1181 | pc += 8; | |
1182 | break; | |
e135b889 | 1183 | case 5: /* BNE, BNEL */ |
c5aa993b | 1184 | neq_branch: |
6c997a34 | 1185 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1186 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1187 | pc += mips32_relative_offset (inst) + 4; |
1188 | else | |
1189 | pc += 8; | |
1190 | break; | |
e135b889 | 1191 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1192 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1193 | pc += mips32_relative_offset (inst) + 4; |
1194 | else | |
1195 | pc += 8; | |
1196 | break; | |
1197 | case 7: | |
e135b889 DJ |
1198 | default: |
1199 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1200 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1201 | pc += mips32_relative_offset (inst) + 4; |
1202 | else | |
1203 | pc += 8; | |
1204 | break; | |
c5aa993b JM |
1205 | } /* switch */ |
1206 | } /* else */ | |
1207 | return pc; | |
1208 | } /* mips32_next_pc */ | |
c906108c SS |
1209 | |
1210 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1211 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1212 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1213 | We dont want to set a single step instruction on the extend instruction | |
1214 | either. | |
c5aa993b | 1215 | */ |
c906108c SS |
1216 | |
1217 | /* Lots of mips16 instruction formats */ | |
1218 | /* Predicting jumps requires itype,ritype,i8type | |
1219 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1220 | */ |
c906108c SS |
1221 | enum mips16_inst_fmts |
1222 | { | |
c5aa993b JM |
1223 | itype, /* 0 immediate 5,10 */ |
1224 | ritype, /* 1 5,3,8 */ | |
1225 | rrtype, /* 2 5,3,3,5 */ | |
1226 | rritype, /* 3 5,3,3,5 */ | |
1227 | rrrtype, /* 4 5,3,3,3,2 */ | |
1228 | rriatype, /* 5 5,3,3,1,4 */ | |
1229 | shifttype, /* 6 5,3,3,3,2 */ | |
1230 | i8type, /* 7 5,3,8 */ | |
1231 | i8movtype, /* 8 5,3,3,5 */ | |
1232 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1233 | i64type, /* 10 5,3,8 */ | |
1234 | ri64type, /* 11 5,3,3,5 */ | |
1235 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1236 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1237 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1238 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1239 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1240 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1241 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1242 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1243 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1244 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1245 | }; | |
12f02c2a AC |
1246 | /* I am heaping all the fields of the formats into one structure and |
1247 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1248 | struct upk_mips16 |
6d82d43b AC |
1249 | { |
1250 | CORE_ADDR offset; | |
1251 | unsigned int regx; /* Function in i8 type */ | |
1252 | unsigned int regy; | |
1253 | }; | |
c906108c SS |
1254 | |
1255 | ||
12f02c2a AC |
1256 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1257 | for the bits which make up the immediatate extension. */ | |
c906108c | 1258 | |
12f02c2a AC |
1259 | static CORE_ADDR |
1260 | extended_offset (unsigned int extension) | |
c906108c | 1261 | { |
12f02c2a | 1262 | CORE_ADDR value; |
c5aa993b JM |
1263 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1264 | value = value << 6; | |
1265 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1266 | value = value << 5; | |
1267 | value |= extension & 0x01f; /* extract 4:0 */ | |
1268 | return value; | |
c906108c SS |
1269 | } |
1270 | ||
1271 | /* Only call this function if you know that this is an extendable | |
1272 | instruction, It wont malfunction, but why make excess remote memory references? | |
1273 | If the immediate operands get sign extended or somthing, do it after | |
1274 | the extension is performed. | |
c5aa993b | 1275 | */ |
c906108c SS |
1276 | /* FIXME: Every one of these cases needs to worry about sign extension |
1277 | when the offset is to be used in relative addressing */ | |
1278 | ||
1279 | ||
12f02c2a | 1280 | static unsigned int |
c5aa993b | 1281 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1282 | { |
c5aa993b JM |
1283 | char buf[8]; |
1284 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1285 | target_read_memory (pc, buf, 2); | |
1286 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1287 | } |
1288 | ||
1289 | static void | |
c5aa993b | 1290 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1291 | unsigned int extension, |
1292 | unsigned int inst, | |
6d82d43b | 1293 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1294 | { |
12f02c2a AC |
1295 | CORE_ADDR offset; |
1296 | int regx; | |
1297 | int regy; | |
1298 | switch (insn_format) | |
c906108c | 1299 | { |
c5aa993b | 1300 | case itype: |
c906108c | 1301 | { |
12f02c2a AC |
1302 | CORE_ADDR value; |
1303 | if (extension) | |
c5aa993b JM |
1304 | { |
1305 | value = extended_offset (extension); | |
1306 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1307 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1308 | } |
1309 | else | |
c5aa993b | 1310 | { |
12f02c2a | 1311 | value = inst & 0x7ff; |
c5aa993b | 1312 | /* FIXME : Consider sign extension */ |
c906108c | 1313 | } |
12f02c2a AC |
1314 | offset = value; |
1315 | regx = -1; | |
1316 | regy = -1; | |
c906108c | 1317 | } |
c5aa993b JM |
1318 | break; |
1319 | case ritype: | |
1320 | case i8type: | |
1321 | { /* A register identifier and an offset */ | |
c906108c SS |
1322 | /* Most of the fields are the same as I type but the |
1323 | immediate value is of a different length */ | |
12f02c2a AC |
1324 | CORE_ADDR value; |
1325 | if (extension) | |
c906108c | 1326 | { |
c5aa993b JM |
1327 | value = extended_offset (extension); |
1328 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1329 | value |= inst & 0xff; /* eleven bits from instruction */ |
1330 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1331 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1332 | { | |
1333 | value &= ~0x3fff; /* remove the sign bit */ | |
1334 | value = -value; | |
c906108c SS |
1335 | } |
1336 | } | |
c5aa993b JM |
1337 | else |
1338 | { | |
12f02c2a AC |
1339 | value = inst & 0xff; /* 8 bits */ |
1340 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1341 | /* FIXME: Do sign extension , this format needs it */ |
1342 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1343 | { | |
1344 | value &= 0xef; /* remove the sign bit */ | |
1345 | value = -value; | |
1346 | } | |
c5aa993b | 1347 | } |
12f02c2a AC |
1348 | offset = value; |
1349 | regy = -1; | |
c5aa993b | 1350 | break; |
c906108c | 1351 | } |
c5aa993b | 1352 | case jalxtype: |
c906108c | 1353 | { |
c5aa993b | 1354 | unsigned long value; |
12f02c2a AC |
1355 | unsigned int nexthalf; |
1356 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1357 | value = value << 16; |
1358 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1359 | value |= nexthalf; | |
12f02c2a AC |
1360 | offset = value; |
1361 | regx = -1; | |
1362 | regy = -1; | |
c5aa993b | 1363 | break; |
c906108c SS |
1364 | } |
1365 | default: | |
6d82d43b | 1366 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1367 | } |
12f02c2a AC |
1368 | upk->offset = offset; |
1369 | upk->regx = regx; | |
1370 | upk->regy = regy; | |
c906108c SS |
1371 | } |
1372 | ||
1373 | ||
c5aa993b JM |
1374 | static CORE_ADDR |
1375 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1376 | { |
c5aa993b | 1377 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1378 | } |
1379 | ||
12f02c2a AC |
1380 | static CORE_ADDR |
1381 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1382 | unsigned int extension, unsigned int insn) |
c906108c | 1383 | { |
12f02c2a AC |
1384 | int op = (insn >> 11); |
1385 | switch (op) | |
c906108c | 1386 | { |
6d82d43b | 1387 | case 2: /* Branch */ |
12f02c2a AC |
1388 | { |
1389 | CORE_ADDR offset; | |
1390 | struct upk_mips16 upk; | |
1391 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1392 | offset = upk.offset; | |
1393 | if (offset & 0x800) | |
1394 | { | |
1395 | offset &= 0xeff; | |
1396 | offset = -offset; | |
1397 | } | |
1398 | pc += (offset << 1) + 2; | |
1399 | break; | |
1400 | } | |
6d82d43b | 1401 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1402 | { |
1403 | struct upk_mips16 upk; | |
1404 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1405 | pc = add_offset_16 (pc, upk.offset); | |
1406 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1407 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1408 | else | |
1409 | pc |= 0x01; | |
1410 | break; | |
1411 | } | |
6d82d43b | 1412 | case 4: /* beqz */ |
12f02c2a AC |
1413 | { |
1414 | struct upk_mips16 upk; | |
1415 | int reg; | |
1416 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1417 | reg = read_signed_register (upk.regx); | |
1418 | if (reg == 0) | |
1419 | pc += (upk.offset << 1) + 2; | |
1420 | else | |
1421 | pc += 2; | |
1422 | break; | |
1423 | } | |
6d82d43b | 1424 | case 5: /* bnez */ |
12f02c2a AC |
1425 | { |
1426 | struct upk_mips16 upk; | |
1427 | int reg; | |
1428 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1429 | reg = read_signed_register (upk.regx); | |
1430 | if (reg != 0) | |
1431 | pc += (upk.offset << 1) + 2; | |
1432 | else | |
1433 | pc += 2; | |
1434 | break; | |
1435 | } | |
6d82d43b | 1436 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1437 | { |
1438 | struct upk_mips16 upk; | |
1439 | int reg; | |
1440 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1441 | /* upk.regx contains the opcode */ | |
1442 | reg = read_signed_register (24); /* Test register is 24 */ | |
1443 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1444 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1445 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1446 | pc += (upk.offset << 1) + 2; | |
1447 | else | |
1448 | pc += 2; | |
1449 | break; | |
1450 | } | |
6d82d43b | 1451 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1452 | { |
1453 | struct upk_mips16 upk; | |
1454 | /* upk.fmt = rrtype; */ | |
1455 | op = insn & 0x1f; | |
1456 | if (op == 0) | |
c5aa993b | 1457 | { |
12f02c2a AC |
1458 | int reg; |
1459 | upk.regx = (insn >> 8) & 0x07; | |
1460 | upk.regy = (insn >> 5) & 0x07; | |
1461 | switch (upk.regy) | |
c5aa993b | 1462 | { |
12f02c2a AC |
1463 | case 0: |
1464 | reg = upk.regx; | |
1465 | break; | |
1466 | case 1: | |
1467 | reg = 31; | |
6d82d43b | 1468 | break; /* Function return instruction */ |
12f02c2a AC |
1469 | case 2: |
1470 | reg = upk.regx; | |
1471 | break; | |
1472 | default: | |
1473 | reg = 31; | |
6d82d43b | 1474 | break; /* BOGUS Guess */ |
c906108c | 1475 | } |
12f02c2a | 1476 | pc = read_signed_register (reg); |
c906108c | 1477 | } |
12f02c2a | 1478 | else |
c5aa993b | 1479 | pc += 2; |
12f02c2a AC |
1480 | break; |
1481 | } | |
1482 | case 30: | |
1483 | /* This is an instruction extension. Fetch the real instruction | |
1484 | (which follows the extension) and decode things based on | |
1485 | that. */ | |
1486 | { | |
1487 | pc += 2; | |
1488 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1489 | break; | |
1490 | } | |
1491 | default: | |
1492 | { | |
1493 | pc += 2; | |
1494 | break; | |
1495 | } | |
c906108c | 1496 | } |
c5aa993b | 1497 | return pc; |
12f02c2a | 1498 | } |
c906108c | 1499 | |
5a89d8aa | 1500 | static CORE_ADDR |
12f02c2a AC |
1501 | mips16_next_pc (CORE_ADDR pc) |
1502 | { | |
1503 | unsigned int insn = fetch_mips_16 (pc); | |
1504 | return extended_mips16_next_pc (pc, 0, insn); | |
1505 | } | |
1506 | ||
1507 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1508 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1509 | It works by decoding the current instruction and predicting where a |
1510 | branch will go. This isnt hard because all the data is available. | |
1511 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1512 | CORE_ADDR |
1513 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1514 | { |
c5aa993b JM |
1515 | if (pc & 0x01) |
1516 | return mips16_next_pc (pc); | |
1517 | else | |
1518 | return mips32_next_pc (pc); | |
12f02c2a | 1519 | } |
c906108c | 1520 | |
edfae063 AC |
1521 | struct mips_frame_cache |
1522 | { | |
1523 | CORE_ADDR base; | |
1524 | struct trad_frame_saved_reg *saved_regs; | |
1525 | }; | |
1526 | ||
1527 | ||
1528 | static struct mips_frame_cache * | |
1529 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1530 | { | |
1531 | mips_extra_func_info_t proc_desc; | |
1532 | struct mips_frame_cache *cache; | |
1533 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1534 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1535 | /* r0 bit means kernel trap */ | |
1536 | int kernel_trap; | |
1537 | /* What registers have been saved? Bitmasks. */ | |
1538 | unsigned long gen_mask, float_mask; | |
1539 | ||
1540 | if ((*this_cache) != NULL) | |
1541 | return (*this_cache); | |
1542 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1543 | (*this_cache) = cache; | |
1544 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1545 | ||
1546 | /* Get the mdebug proc descriptor. */ | |
465f7520 | 1547 | proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame); |
edfae063 AC |
1548 | if (proc_desc == NULL) |
1549 | /* I'm not sure how/whether this can happen. Normally when we | |
1550 | can't find a proc_desc, we "synthesize" one using | |
1551 | heuristic_proc_desc and set the saved_regs right away. */ | |
1552 | return cache; | |
1553 | ||
1554 | /* Extract the frame's base. */ | |
1555 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1556 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1557 | ||
1558 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1559 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1560 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1561 | ||
1562 | /* In any frame other than the innermost or a frame interrupted by a | |
1563 | signal, we assume that all registers have been saved. This | |
1564 | assumes that all register saves in a function happen before the | |
1565 | first function call. */ | |
1566 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1567 | /* Not sure exactly what kernel_trap means, but if it means the | |
1568 | kernel saves the registers without a prologue doing it, we | |
1569 | better not examine the prologue to see whether registers | |
1570 | have been saved yet. */ | |
1571 | && !kernel_trap) | |
1572 | { | |
1573 | /* We need to figure out whether the registers that the | |
1574 | proc_desc claims are saved have been saved yet. */ | |
1575 | ||
1576 | CORE_ADDR addr; | |
1577 | ||
1578 | /* Bitmasks; set if we have found a save for the register. */ | |
1579 | unsigned long gen_save_found = 0; | |
1580 | unsigned long float_save_found = 0; | |
1581 | int mips16; | |
1582 | ||
1583 | /* If the address is odd, assume this is MIPS16 code. */ | |
1584 | addr = PROC_LOW_ADDR (proc_desc); | |
1585 | mips16 = pc_is_mips16 (addr); | |
1586 | ||
1587 | /* Scan through this function's instructions preceding the | |
1588 | current PC, and look for those that save registers. */ | |
1589 | while (addr < frame_pc_unwind (next_frame)) | |
1590 | { | |
1591 | if (mips16) | |
1592 | { | |
1593 | mips16_decode_reg_save (mips16_fetch_instruction (addr), | |
1594 | &gen_save_found); | |
1595 | addr += MIPS16_INSTLEN; | |
1596 | } | |
1597 | else | |
1598 | { | |
1599 | mips32_decode_reg_save (mips32_fetch_instruction (addr), | |
1600 | &gen_save_found, &float_save_found); | |
1601 | addr += MIPS_INSTLEN; | |
1602 | } | |
1603 | } | |
1604 | gen_mask = gen_save_found; | |
1605 | float_mask = float_save_found; | |
1606 | } | |
1607 | ||
1608 | /* Fill in the offsets for the registers which gen_mask says were | |
1609 | saved. */ | |
1610 | { | |
4fbbbd07 | 1611 | CORE_ADDR reg_position = (cache->base + PROC_REG_OFFSET (proc_desc)); |
edfae063 | 1612 | int ireg; |
4fbbbd07 | 1613 | |
edfae063 AC |
1614 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
1615 | if (gen_mask & 0x80000000) | |
1616 | { | |
1617 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1618 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1619 | } |
1620 | } | |
1621 | ||
1622 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1623 | order of that normally used by gcc. Therefore, we have to fetch | |
1624 | the first instruction of the function, and if it's an entry | |
1625 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1626 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1627 | { | |
1628 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1629 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1630 | /* entry */ | |
1631 | { | |
1632 | int reg; | |
1633 | int sreg_count = (inst >> 6) & 3; | |
1634 | ||
1635 | /* Check if the ra register was pushed on the stack. */ | |
1636 | CORE_ADDR reg_position = (cache->base | |
1637 | + PROC_REG_OFFSET (proc_desc)); | |
1638 | if (inst & 0x20) | |
13326b4e | 1639 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1640 | |
1641 | /* Check if the s0 and s1 registers were pushed on the | |
1642 | stack. */ | |
1643 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1644 | check. */ | |
1645 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1646 | { | |
1647 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1648 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1649 | } |
1650 | } | |
1651 | } | |
1652 | ||
1653 | /* Fill in the offsets for the registers which float_mask says were | |
1654 | saved. */ | |
1655 | { | |
1656 | CORE_ADDR reg_position = (cache->base | |
1657 | + PROC_FREG_OFFSET (proc_desc)); | |
1658 | int ireg; | |
1659 | /* Fill in the offsets for the float registers which float_mask | |
1660 | says were saved. */ | |
1661 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1662 | if (float_mask & 0x80000000) | |
1663 | { | |
13326b4e | 1664 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1665 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1666 | { | |
1667 | /* On a big endian 32 bit ABI, floating point registers | |
1668 | are paired to form doubles such that the most | |
1669 | significant part is in $f[N+1] and the least | |
1670 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1671 | registers are also spilled as a pair and stored as a | |
1672 | double. | |
1673 | ||
1674 | When little-endian the least significant part is | |
1675 | stored first leading to the memory order $f[N] and | |
1676 | then $f[N+1]. | |
1677 | ||
1678 | Unfortunately, when big-endian the most significant | |
1679 | part of the double is stored first, and the least | |
1680 | significant is stored second. This leads to the | |
1681 | registers being ordered in memory as firt $f[N+1] and | |
1682 | then $f[N]. | |
1683 | ||
1684 | For the big-endian case make certain that the | |
1685 | addresses point at the correct (swapped) locations | |
1686 | $f[N] and $f[N+1] pair (keep in mind that | |
1687 | reg_position is decremented each time through the | |
1688 | loop). */ | |
1689 | if ((ireg & 1)) | |
1690 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1691 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1692 | else |
1693 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1694 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1695 | } |
1696 | else | |
1697 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1698 | .addr = reg_position; | |
13326b4e | 1699 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1700 | } |
1701 | ||
1702 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1703 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1704 | } | |
1705 | ||
1706 | /* SP_REGNUM, contains the value and not the address. */ | |
f10683bb | 1707 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); |
edfae063 AC |
1708 | |
1709 | return (*this_cache); | |
1710 | } | |
1711 | ||
1712 | static void | |
1713 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1714 | struct frame_id *this_id) | |
1715 | { | |
1716 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1717 | this_cache); | |
1718 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1719 | } | |
1720 | ||
1721 | static void | |
1722 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1723 | void **this_cache, | |
1724 | int regnum, int *optimizedp, | |
1725 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1726 | int *realnump, void *valuep) | |
1727 | { | |
1728 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1729 | this_cache); | |
1f67027d AC |
1730 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
1731 | optimizedp, lvalp, addrp, realnump, valuep); | |
edfae063 AC |
1732 | } |
1733 | ||
1734 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1735 | { | |
1736 | NORMAL_FRAME, | |
1737 | mips_mdebug_frame_this_id, | |
1738 | mips_mdebug_frame_prev_register | |
1739 | }; | |
1740 | ||
1741 | static const struct frame_unwind * | |
1742 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1743 | { | |
eec63939 AC |
1744 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1745 | CORE_ADDR startaddr = 0; | |
1746 | mips_extra_func_info_t proc_desc; | |
1747 | int kernel_trap; | |
1748 | ||
1749 | /* Only use the mdebug frame unwinder on mdebug frames where all the | |
1750 | registers have been saved. Leave hard cases such as no mdebug or | |
1751 | in prologue for the heuristic unwinders. */ | |
1752 | ||
1753 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1754 | if (proc_desc == NULL) | |
1755 | return NULL; | |
1756 | ||
1757 | /* Not sure exactly what kernel_trap means, but if it means the | |
1758 | kernel saves the registers without a prologue doing it, we better | |
1759 | not examine the prologue to see whether registers have been saved | |
1760 | yet. */ | |
1761 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1762 | if (kernel_trap) | |
1763 | return &mips_mdebug_frame_unwind; | |
1764 | ||
1765 | /* In any frame other than the innermost or a frame interrupted by a | |
1766 | signal, we assume that all registers have been saved. This | |
1767 | assumes that all register saves in a function happen before the | |
1768 | first function call. */ | |
1769 | if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc))) | |
1770 | return &mips_mdebug_frame_unwind; | |
1771 | ||
1772 | return NULL; | |
edfae063 AC |
1773 | } |
1774 | ||
1775 | static CORE_ADDR | |
1776 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1777 | void **this_cache) | |
1778 | { | |
1779 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1780 | this_cache); | |
1781 | return info->base; | |
1782 | } | |
1783 | ||
1784 | static const struct frame_base mips_mdebug_frame_base = { | |
1785 | &mips_mdebug_frame_unwind, | |
1786 | mips_mdebug_frame_base_address, | |
1787 | mips_mdebug_frame_base_address, | |
1788 | mips_mdebug_frame_base_address | |
1789 | }; | |
1790 | ||
1791 | static const struct frame_base * | |
1792 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1793 | { | |
eec63939 AC |
1794 | if (mips_mdebug_frame_sniffer (next_frame) != NULL) |
1795 | return &mips_mdebug_frame_base; | |
1796 | else | |
1797 | return NULL; | |
1798 | } | |
1799 | ||
45c9dd44 AC |
1800 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1801 | Procedures that use the 32-bit instruction set are handled by the | |
1802 | mips_insn32 unwinder. */ | |
1803 | ||
eec63939 | 1804 | static struct mips_frame_cache * |
45c9dd44 | 1805 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 AC |
1806 | { |
1807 | mips_extra_func_info_t proc_desc; | |
1808 | struct mips_frame_cache *cache; | |
1809 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1810 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1811 | /* r0 bit means kernel trap */ | |
1812 | int kernel_trap; | |
1813 | /* What registers have been saved? Bitmasks. */ | |
1814 | unsigned long gen_mask, float_mask; | |
1815 | ||
1816 | if ((*this_cache) != NULL) | |
1817 | return (*this_cache); | |
1818 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1819 | (*this_cache) = cache; | |
1820 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1821 | ||
1822 | /* Get the mdebug proc descriptor. */ | |
465f7520 | 1823 | proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame); |
eec63939 AC |
1824 | if (proc_desc == NULL) |
1825 | /* I'm not sure how/whether this can happen. Normally when we | |
1826 | can't find a proc_desc, we "synthesize" one using | |
1827 | heuristic_proc_desc and set the saved_regs right away. */ | |
1828 | return cache; | |
1829 | ||
1830 | /* Extract the frame's base. */ | |
1831 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1832 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1833 | ||
1834 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1835 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1836 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1837 | ||
1838 | /* In any frame other than the innermost or a frame interrupted by a | |
1839 | signal, we assume that all registers have been saved. This | |
1840 | assumes that all register saves in a function happen before the | |
1841 | first function call. */ | |
1842 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1843 | /* Not sure exactly what kernel_trap means, but if it means the | |
1844 | kernel saves the registers without a prologue doing it, we | |
1845 | better not examine the prologue to see whether registers | |
1846 | have been saved yet. */ | |
1847 | && !kernel_trap) | |
1848 | { | |
1849 | /* We need to figure out whether the registers that the | |
1850 | proc_desc claims are saved have been saved yet. */ | |
1851 | ||
1852 | CORE_ADDR addr; | |
1853 | ||
1854 | /* Bitmasks; set if we have found a save for the register. */ | |
1855 | unsigned long gen_save_found = 0; | |
1856 | unsigned long float_save_found = 0; | |
1857 | int mips16; | |
1858 | ||
1859 | /* If the address is odd, assume this is MIPS16 code. */ | |
1860 | addr = PROC_LOW_ADDR (proc_desc); | |
1861 | mips16 = pc_is_mips16 (addr); | |
1862 | ||
1863 | /* Scan through this function's instructions preceding the | |
1864 | current PC, and look for those that save registers. */ | |
1865 | while (addr < frame_pc_unwind (next_frame)) | |
1866 | { | |
1867 | if (mips16) | |
1868 | { | |
1869 | mips16_decode_reg_save (mips16_fetch_instruction (addr), | |
1870 | &gen_save_found); | |
1871 | addr += MIPS16_INSTLEN; | |
1872 | } | |
1873 | else | |
1874 | { | |
1875 | mips32_decode_reg_save (mips32_fetch_instruction (addr), | |
1876 | &gen_save_found, &float_save_found); | |
1877 | addr += MIPS_INSTLEN; | |
1878 | } | |
1879 | } | |
1880 | gen_mask = gen_save_found; | |
1881 | float_mask = float_save_found; | |
1882 | } | |
1883 | ||
1884 | /* Fill in the offsets for the registers which gen_mask says were | |
1885 | saved. */ | |
1886 | { | |
1887 | CORE_ADDR reg_position = (cache->base | |
1888 | + PROC_REG_OFFSET (proc_desc)); | |
1889 | int ireg; | |
1890 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1891 | if (gen_mask & 0x80000000) | |
1892 | { | |
1893 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
1894 | reg_position -= mips_abi_regsize (gdbarch); | |
1895 | } | |
1896 | } | |
1897 | ||
1898 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1899 | order of that normally used by gcc. Therefore, we have to fetch | |
1900 | the first instruction of the function, and if it's an entry | |
1901 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1902 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1903 | { | |
1904 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1905 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1906 | /* entry */ | |
1907 | { | |
1908 | int reg; | |
1909 | int sreg_count = (inst >> 6) & 3; | |
1910 | ||
1911 | /* Check if the ra register was pushed on the stack. */ | |
1912 | CORE_ADDR reg_position = (cache->base | |
1913 | + PROC_REG_OFFSET (proc_desc)); | |
1914 | if (inst & 0x20) | |
1915 | reg_position -= mips_abi_regsize (gdbarch); | |
1916 | ||
1917 | /* Check if the s0 and s1 registers were pushed on the | |
1918 | stack. */ | |
1919 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1920 | check. */ | |
1921 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1922 | { | |
1923 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
1924 | reg_position -= mips_abi_regsize (gdbarch); | |
1925 | } | |
1926 | } | |
1927 | } | |
1928 | ||
1929 | /* Fill in the offsets for the registers which float_mask says were | |
1930 | saved. */ | |
1931 | { | |
1932 | CORE_ADDR reg_position = (cache->base | |
1933 | + PROC_FREG_OFFSET (proc_desc)); | |
1934 | int ireg; | |
1935 | /* Fill in the offsets for the float registers which float_mask | |
1936 | says were saved. */ | |
1937 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1938 | if (float_mask & 0x80000000) | |
1939 | { | |
1940 | if (mips_abi_regsize (gdbarch) == 4 | |
1941 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1942 | { | |
1943 | /* On a big endian 32 bit ABI, floating point registers | |
1944 | are paired to form doubles such that the most | |
1945 | significant part is in $f[N+1] and the least | |
1946 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1947 | registers are also spilled as a pair and stored as a | |
1948 | double. | |
1949 | ||
1950 | When little-endian the least significant part is | |
1951 | stored first leading to the memory order $f[N] and | |
1952 | then $f[N+1]. | |
1953 | ||
1954 | Unfortunately, when big-endian the most significant | |
1955 | part of the double is stored first, and the least | |
1956 | significant is stored second. This leads to the | |
1957 | registers being ordered in memory as firt $f[N+1] and | |
1958 | then $f[N]. | |
1959 | ||
1960 | For the big-endian case make certain that the | |
1961 | addresses point at the correct (swapped) locations | |
1962 | $f[N] and $f[N+1] pair (keep in mind that | |
1963 | reg_position is decremented each time through the | |
1964 | loop). */ | |
1965 | if ((ireg & 1)) | |
1966 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1967 | .addr = reg_position - mips_abi_regsize (gdbarch); | |
1968 | else | |
1969 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1970 | .addr = reg_position + mips_abi_regsize (gdbarch); | |
1971 | } | |
1972 | else | |
1973 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1974 | .addr = reg_position; | |
1975 | reg_position -= mips_abi_regsize (gdbarch); | |
1976 | } | |
1977 | ||
1978 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1979 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1980 | } | |
1981 | ||
1982 | /* SP_REGNUM, contains the value and not the address. */ | |
1983 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
1984 | ||
1985 | return (*this_cache); | |
1986 | } | |
1987 | ||
1988 | static void | |
45c9dd44 | 1989 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
1990 | struct frame_id *this_id) |
1991 | { | |
45c9dd44 | 1992 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1993 | this_cache); |
1994 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1995 | } | |
1996 | ||
1997 | static void | |
45c9dd44 | 1998 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1999 | void **this_cache, |
2000 | int regnum, int *optimizedp, | |
2001 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2002 | int *realnump, void *valuep) | |
2003 | { | |
45c9dd44 | 2004 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
2005 | this_cache); |
2006 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2007 | optimizedp, lvalp, addrp, realnump, valuep); | |
2008 | } | |
2009 | ||
45c9dd44 | 2010 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2011 | { |
2012 | NORMAL_FRAME, | |
45c9dd44 AC |
2013 | mips_insn16_frame_this_id, |
2014 | mips_insn16_frame_prev_register | |
eec63939 AC |
2015 | }; |
2016 | ||
2017 | static const struct frame_unwind * | |
45c9dd44 | 2018 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2019 | { |
2020 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2021 | if (pc_is_mips16 (pc)) | |
45c9dd44 | 2022 | return &mips_insn16_frame_unwind; |
eec63939 AC |
2023 | return NULL; |
2024 | } | |
2025 | ||
2026 | static CORE_ADDR | |
45c9dd44 | 2027 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
2028 | void **this_cache) |
2029 | { | |
45c9dd44 | 2030 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
2031 | this_cache); |
2032 | return info->base; | |
2033 | } | |
2034 | ||
45c9dd44 | 2035 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2036 | { |
45c9dd44 AC |
2037 | &mips_insn16_frame_unwind, |
2038 | mips_insn16_frame_base_address, | |
2039 | mips_insn16_frame_base_address, | |
2040 | mips_insn16_frame_base_address | |
eec63939 AC |
2041 | }; |
2042 | ||
2043 | static const struct frame_base * | |
45c9dd44 | 2044 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2045 | { |
45c9dd44 AC |
2046 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
2047 | return &mips_insn16_frame_base; | |
eec63939 AC |
2048 | else |
2049 | return NULL; | |
2050 | } | |
2051 | ||
45c9dd44 AC |
2052 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2053 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2054 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2055 | unwinder. */ | |
2056 | ||
eec63939 | 2057 | static struct mips_frame_cache * |
45c9dd44 | 2058 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 AC |
2059 | { |
2060 | mips_extra_func_info_t proc_desc; | |
2061 | struct mips_frame_cache *cache; | |
2062 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2063 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2064 | /* r0 bit means kernel trap */ | |
2065 | int kernel_trap; | |
2066 | /* What registers have been saved? Bitmasks. */ | |
2067 | unsigned long gen_mask, float_mask; | |
2068 | ||
2069 | if ((*this_cache) != NULL) | |
2070 | return (*this_cache); | |
2071 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2072 | (*this_cache) = cache; | |
2073 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2074 | ||
a343eb3c JB |
2075 | /* Synthesize a proc descriptor. */ |
2076 | { | |
2077 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2078 | CORE_ADDR start_addr; | |
2079 | ||
2080 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2081 | if (start_addr == 0) | |
2082 | start_addr = heuristic_proc_start (pc); | |
2083 | ||
465f7520 | 2084 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame); |
a343eb3c JB |
2085 | } |
2086 | ||
eec63939 AC |
2087 | if (proc_desc == NULL) |
2088 | /* I'm not sure how/whether this can happen. Normally when we | |
2089 | can't find a proc_desc, we "synthesize" one using | |
2090 | heuristic_proc_desc and set the saved_regs right away. */ | |
2091 | return cache; | |
2092 | ||
2093 | /* Extract the frame's base. */ | |
2094 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
2095 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
2096 | ||
2097 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
2098 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
2099 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
2100 | ||
2101 | /* In any frame other than the innermost or a frame interrupted by a | |
2102 | signal, we assume that all registers have been saved. This | |
2103 | assumes that all register saves in a function happen before the | |
2104 | first function call. */ | |
2105 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
2106 | /* Not sure exactly what kernel_trap means, but if it means the | |
2107 | kernel saves the registers without a prologue doing it, we | |
2108 | better not examine the prologue to see whether registers | |
2109 | have been saved yet. */ | |
2110 | && !kernel_trap) | |
2111 | { | |
2112 | /* We need to figure out whether the registers that the | |
2113 | proc_desc claims are saved have been saved yet. */ | |
2114 | ||
2115 | CORE_ADDR addr; | |
2116 | ||
2117 | /* Bitmasks; set if we have found a save for the register. */ | |
2118 | unsigned long gen_save_found = 0; | |
2119 | unsigned long float_save_found = 0; | |
eec63939 | 2120 | |
eec63939 | 2121 | addr = PROC_LOW_ADDR (proc_desc); |
eec63939 AC |
2122 | |
2123 | /* Scan through this function's instructions preceding the | |
2124 | current PC, and look for those that save registers. */ | |
2125 | while (addr < frame_pc_unwind (next_frame)) | |
2126 | { | |
8ac2e020 JB |
2127 | mips32_decode_reg_save (mips32_fetch_instruction (addr), |
2128 | &gen_save_found, &float_save_found); | |
2129 | addr += MIPS_INSTLEN; | |
eec63939 AC |
2130 | } |
2131 | gen_mask = gen_save_found; | |
2132 | float_mask = float_save_found; | |
2133 | } | |
2134 | ||
2135 | /* Fill in the offsets for the registers which gen_mask says were | |
2136 | saved. */ | |
2137 | { | |
2138 | CORE_ADDR reg_position = (cache->base | |
2139 | + PROC_REG_OFFSET (proc_desc)); | |
2140 | int ireg; | |
2141 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
2142 | if (gen_mask & 0x80000000) | |
2143 | { | |
2144 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
2145 | reg_position -= mips_abi_regsize (gdbarch); | |
2146 | } | |
2147 | } | |
2148 | ||
eec63939 AC |
2149 | /* Fill in the offsets for the registers which float_mask says were |
2150 | saved. */ | |
2151 | { | |
8ac2e020 | 2152 | CORE_ADDR reg_position = (cache->base + PROC_FREG_OFFSET (proc_desc)); |
eec63939 | 2153 | int ireg; |
8ac2e020 | 2154 | |
eec63939 AC |
2155 | /* Fill in the offsets for the float registers which float_mask |
2156 | says were saved. */ | |
2157 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
2158 | if (float_mask & 0x80000000) | |
2159 | { | |
8ac2e020 JB |
2160 | const int regno = |
2161 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg; | |
2162 | ||
eec63939 AC |
2163 | if (mips_abi_regsize (gdbarch) == 4 |
2164 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2165 | { | |
2166 | /* On a big endian 32 bit ABI, floating point registers | |
2167 | are paired to form doubles such that the most | |
2168 | significant part is in $f[N+1] and the least | |
2169 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
2170 | registers are also spilled as a pair and stored as a | |
2171 | double. | |
2172 | ||
2173 | When little-endian the least significant part is | |
2174 | stored first leading to the memory order $f[N] and | |
2175 | then $f[N+1]. | |
2176 | ||
2177 | Unfortunately, when big-endian the most significant | |
2178 | part of the double is stored first, and the least | |
2179 | significant is stored second. This leads to the | |
2180 | registers being ordered in memory as firt $f[N+1] and | |
2181 | then $f[N]. | |
2182 | ||
2183 | For the big-endian case make certain that the | |
2184 | addresses point at the correct (swapped) locations | |
2185 | $f[N] and $f[N+1] pair (keep in mind that | |
2186 | reg_position is decremented each time through the | |
2187 | loop). */ | |
2188 | if ((ireg & 1)) | |
8ac2e020 JB |
2189 | cache->saved_regs[regno].addr = |
2190 | reg_position - mips_abi_regsize (gdbarch); | |
eec63939 | 2191 | else |
8ac2e020 JB |
2192 | cache->saved_regs[regno].addr = |
2193 | reg_position + mips_abi_regsize (gdbarch); | |
eec63939 AC |
2194 | } |
2195 | else | |
8ac2e020 | 2196 | cache->saved_regs[regno].addr = reg_position; |
eec63939 AC |
2197 | reg_position -= mips_abi_regsize (gdbarch); |
2198 | } | |
2199 | ||
2200 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
2201 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
2202 | } | |
2203 | ||
2204 | /* SP_REGNUM, contains the value and not the address. */ | |
2205 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
2206 | ||
2207 | return (*this_cache); | |
2208 | } | |
2209 | ||
2210 | static void | |
45c9dd44 | 2211 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
2212 | struct frame_id *this_id) |
2213 | { | |
45c9dd44 | 2214 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2215 | this_cache); |
2216 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2217 | } | |
2218 | ||
2219 | static void | |
45c9dd44 | 2220 | mips_insn32_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
2221 | void **this_cache, |
2222 | int regnum, int *optimizedp, | |
2223 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2224 | int *realnump, void *valuep) | |
2225 | { | |
45c9dd44 | 2226 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2227 | this_cache); |
2228 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2229 | optimizedp, lvalp, addrp, realnump, valuep); | |
2230 | } | |
2231 | ||
45c9dd44 | 2232 | static const struct frame_unwind mips_insn32_frame_unwind = |
eec63939 AC |
2233 | { |
2234 | NORMAL_FRAME, | |
45c9dd44 AC |
2235 | mips_insn32_frame_this_id, |
2236 | mips_insn32_frame_prev_register | |
eec63939 AC |
2237 | }; |
2238 | ||
2239 | static const struct frame_unwind * | |
45c9dd44 | 2240 | mips_insn32_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2241 | { |
2242 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2243 | if (! pc_is_mips16 (pc)) | |
45c9dd44 | 2244 | return &mips_insn32_frame_unwind; |
eec63939 AC |
2245 | return NULL; |
2246 | } | |
2247 | ||
2248 | static CORE_ADDR | |
45c9dd44 | 2249 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
2250 | void **this_cache) |
2251 | { | |
45c9dd44 | 2252 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2253 | this_cache); |
2254 | return info->base; | |
2255 | } | |
2256 | ||
45c9dd44 | 2257 | static const struct frame_base mips_insn32_frame_base = |
eec63939 | 2258 | { |
45c9dd44 AC |
2259 | &mips_insn32_frame_unwind, |
2260 | mips_insn32_frame_base_address, | |
2261 | mips_insn32_frame_base_address, | |
2262 | mips_insn32_frame_base_address | |
eec63939 AC |
2263 | }; |
2264 | ||
2265 | static const struct frame_base * | |
45c9dd44 | 2266 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2267 | { |
45c9dd44 AC |
2268 | if (mips_insn32_frame_sniffer (next_frame) != NULL) |
2269 | return &mips_insn32_frame_base; | |
eec63939 AC |
2270 | else |
2271 | return NULL; | |
2272 | } | |
2273 | ||
2274 | static struct trad_frame_cache * | |
2275 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2276 | { | |
2277 | CORE_ADDR pc; | |
2278 | CORE_ADDR start_addr; | |
2279 | CORE_ADDR stack_addr; | |
2280 | struct trad_frame_cache *this_trad_cache; | |
2281 | ||
2282 | if ((*this_cache) != NULL) | |
2283 | return (*this_cache); | |
2284 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2285 | (*this_cache) = this_trad_cache; | |
2286 | ||
2287 | /* The return address is in the link register. */ | |
2288 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, RA_REGNUM); | |
2289 | ||
2290 | /* Frame ID, since it's a frameless / stackless function, no stack | |
2291 | space is allocated and SP on entry is the current SP. */ | |
2292 | pc = frame_pc_unwind (next_frame); | |
2293 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2294 | stack_addr = frame_unwind_register_signed (next_frame, SP_REGNUM); | |
2295 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); | |
2296 | ||
2297 | /* Assume that the frame's base is the same as the | |
2298 | stack-pointer. */ | |
2299 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
2300 | ||
2301 | return this_trad_cache; | |
2302 | } | |
2303 | ||
2304 | static void | |
2305 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2306 | struct frame_id *this_id) | |
2307 | { | |
2308 | struct trad_frame_cache *this_trad_cache | |
2309 | = mips_stub_frame_cache (next_frame, this_cache); | |
2310 | trad_frame_get_id (this_trad_cache, this_id); | |
2311 | } | |
2312 | ||
2313 | static void | |
2314 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2315 | void **this_cache, | |
2316 | int regnum, int *optimizedp, | |
2317 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2318 | int *realnump, void *valuep) | |
2319 | { | |
2320 | struct trad_frame_cache *this_trad_cache | |
2321 | = mips_stub_frame_cache (next_frame, this_cache); | |
2322 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2323 | lvalp, addrp, realnump, valuep); | |
2324 | } | |
2325 | ||
2326 | static const struct frame_unwind mips_stub_frame_unwind = | |
2327 | { | |
2328 | NORMAL_FRAME, | |
2329 | mips_stub_frame_this_id, | |
2330 | mips_stub_frame_prev_register | |
2331 | }; | |
2332 | ||
2333 | static const struct frame_unwind * | |
2334 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2335 | { | |
2336 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2337 | if (in_plt_section (pc, NULL)) | |
2338 | return &mips_stub_frame_unwind; | |
2339 | else | |
2340 | return NULL; | |
2341 | } | |
2342 | ||
2343 | static CORE_ADDR | |
2344 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2345 | void **this_cache) | |
2346 | { | |
2347 | struct trad_frame_cache *this_trad_cache | |
2348 | = mips_stub_frame_cache (next_frame, this_cache); | |
2349 | return trad_frame_get_this_base (this_trad_cache); | |
2350 | } | |
2351 | ||
2352 | static const struct frame_base mips_stub_frame_base = | |
2353 | { | |
2354 | &mips_stub_frame_unwind, | |
2355 | mips_stub_frame_base_address, | |
2356 | mips_stub_frame_base_address, | |
2357 | mips_stub_frame_base_address | |
2358 | }; | |
2359 | ||
2360 | static const struct frame_base * | |
2361 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2362 | { | |
2363 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2364 | return &mips_stub_frame_base; | |
2365 | else | |
2366 | return NULL; | |
edfae063 AC |
2367 | } |
2368 | ||
c906108c | 2369 | static CORE_ADDR |
acdb74a0 | 2370 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 2371 | { |
a4b8ebc8 AC |
2372 | /* Always a pseudo. */ |
2373 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 2374 | if (fi == NULL) |
c906108c | 2375 | { |
a4b8ebc8 AC |
2376 | LONGEST val; |
2377 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2378 | return val; | |
f796e4be | 2379 | } |
f10683bb MH |
2380 | else if ((regno % NUM_REGS) == MIPS_SP_REGNUM) |
2381 | /* MIPS_SP_REGNUM is special, its value is stored in saved_regs. | |
a4b8ebc8 AC |
2382 | In fact, it is so special that it can even only be fetched |
2383 | using a raw register number! Once this code as been converted | |
2384 | to frame-unwind the problem goes away. */ | |
2385 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 2386 | else |
a4b8ebc8 | 2387 | return frame_unwind_register_signed (fi, regno); |
64159455 | 2388 | |
c906108c SS |
2389 | } |
2390 | ||
2391 | /* mips_addr_bits_remove - remove useless address bits */ | |
2392 | ||
875e1767 | 2393 | static CORE_ADDR |
acdb74a0 | 2394 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 2395 | { |
480d3dd2 | 2396 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 2397 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
2398 | /* This hack is a work-around for existing boards using PMON, the |
2399 | simulator, and any other 64-bit targets that doesn't have true | |
2400 | 64-bit addressing. On these targets, the upper 32 bits of | |
2401 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2402 | likely to have been sign extended to all 1s by instruction | |
2403 | sequences that load 32-bit addresses. For example, a typical | |
2404 | piece of code that loads an address is this: | |
2405 | ||
2406 | lui $r2, <upper 16 bits> | |
2407 | ori $r2, <lower 16 bits> | |
2408 | ||
2409 | But the lui sign-extends the value such that the upper 32 bits | |
2410 | may be all 1s. The workaround is simply to mask off these | |
2411 | bits. In the future, gcc may be changed to support true 64-bit | |
2412 | addressing, and this masking will have to be disabled. */ | |
2413 | return addr &= 0xffffffffUL; | |
2414 | else | |
2415 | return addr; | |
c906108c SS |
2416 | } |
2417 | ||
9022177c DJ |
2418 | /* mips_software_single_step() is called just before we want to resume |
2419 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 2420 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
2421 | the target of the coming instruction and breakpoint it. |
2422 | ||
2423 | single_step is also called just after the inferior stops. If we had | |
2424 | set up a simulated single-step, we undo our damage. */ | |
2425 | ||
2426 | void | |
2427 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
2428 | { | |
2429 | static CORE_ADDR next_pc; | |
2430 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2431 | static binsn_quantum break_mem; | |
2432 | CORE_ADDR pc; | |
2433 | ||
2434 | if (insert_breakpoints_p) | |
2435 | { | |
b6cb9035 | 2436 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
2437 | next_pc = mips_next_pc (pc); |
2438 | ||
2439 | target_insert_breakpoint (next_pc, break_mem); | |
2440 | } | |
2441 | else | |
2442 | target_remove_breakpoint (next_pc, break_mem); | |
2443 | } | |
2444 | ||
c906108c | 2445 | static struct mips_extra_func_info temp_proc_desc; |
fe29b929 KB |
2446 | |
2447 | /* This hack will go away once the get_prev_frame() code has been | |
2448 | modified to set the frame's type first. That is BEFORE init extra | |
2449 | frame info et.al. is called. This is because it will become | |
2450 | possible to skip the init extra info call for sigtramp and dummy | |
2451 | frames. */ | |
2452 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 2453 | |
e0f7ec59 AC |
2454 | /* Set a register's saved stack address in temp_saved_regs. If an |
2455 | address has already been set for this register, do nothing; this | |
2456 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
2457 | function prologue. |
2458 | ||
2459 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
2460 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
2461 | is used as it is only second range (the ABI instead of ISA | |
2462 | registers) that comes into play when finding saved registers in a | |
2463 | frame. */ | |
c906108c SS |
2464 | |
2465 | static void | |
e0f7ec59 | 2466 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 2467 | { |
e0f7ec59 | 2468 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
2469 | { |
2470 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
2471 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
2472 | } | |
c906108c SS |
2473 | } |
2474 | ||
2475 | ||
2476 | /* Test whether the PC points to the return instruction at the | |
2477 | end of a function. */ | |
2478 | ||
c5aa993b | 2479 | static int |
acdb74a0 | 2480 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
2481 | { |
2482 | if (pc_is_mips16 (pc)) | |
2483 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
2484 | generates a "jr $ra"; other times it generates code to load | |
2485 | the return address from the stack to an accessible register (such | |
2486 | as $a3), then a "jr" using that register. This second case | |
2487 | is almost impossible to distinguish from an indirect jump | |
2488 | used for switch statements, so we don't even try. */ | |
2489 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2490 | else | |
2491 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2492 | } | |
2493 | ||
2494 | ||
2495 | /* This fencepost looks highly suspicious to me. Removing it also | |
2496 | seems suspicious as it could affect remote debugging across serial | |
2497 | lines. */ | |
2498 | ||
2499 | static CORE_ADDR | |
acdb74a0 | 2500 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 2501 | { |
c5aa993b JM |
2502 | CORE_ADDR start_pc; |
2503 | CORE_ADDR fence; | |
2504 | int instlen; | |
2505 | int seen_adjsp = 0; | |
c906108c | 2506 | |
c5aa993b JM |
2507 | pc = ADDR_BITS_REMOVE (pc); |
2508 | start_pc = pc; | |
2509 | fence = start_pc - heuristic_fence_post; | |
2510 | if (start_pc == 0) | |
2511 | return 0; | |
c906108c | 2512 | |
6d82d43b | 2513 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 2514 | fence = VM_MIN_ADDRESS; |
c906108c | 2515 | |
c5aa993b | 2516 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 2517 | |
c5aa993b JM |
2518 | /* search back for previous return */ |
2519 | for (start_pc -= instlen;; start_pc -= instlen) | |
2520 | if (start_pc < fence) | |
2521 | { | |
2522 | /* It's not clear to me why we reach this point when | |
c0236d92 | 2523 | stop_soon, but with this test, at least we |
c5aa993b JM |
2524 | don't print out warnings for every child forked (eg, on |
2525 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 2526 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 2527 | { |
c5aa993b JM |
2528 | static int blurb_printed = 0; |
2529 | ||
dc305454 MS |
2530 | warning ("GDB can't find the start of the function at 0x%s.", |
2531 | paddr_nz (pc)); | |
c5aa993b JM |
2532 | |
2533 | if (!blurb_printed) | |
c906108c | 2534 | { |
c5aa993b JM |
2535 | /* This actually happens frequently in embedded |
2536 | development, when you first connect to a board | |
2537 | and your stack pointer and pc are nowhere in | |
2538 | particular. This message needs to give people | |
2539 | in that situation enough information to | |
2540 | determine that it's no big deal. */ | |
2541 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
2542 | GDB is unable to find the start of the function at 0x%s\n\ |
2543 | and thus can't determine the size of that function's stack frame.\n\ | |
2544 | This means that GDB may be unable to access that stack frame, or\n\ | |
2545 | the frames below it.\n\ | |
2546 | This problem is most likely caused by an invalid program counter or\n\ | |
2547 | stack pointer.\n\ | |
2548 | However, if you think GDB should simply search farther back\n\ | |
2549 | from 0x%s for code which looks like the beginning of a\n\ | |
2550 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 2551 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 2552 | blurb_printed = 1; |
c906108c | 2553 | } |
c906108c SS |
2554 | } |
2555 | ||
c5aa993b JM |
2556 | return 0; |
2557 | } | |
2558 | else if (pc_is_mips16 (start_pc)) | |
2559 | { | |
2560 | unsigned short inst; | |
2561 | ||
2562 | /* On MIPS16, any one of the following is likely to be the | |
2563 | start of a function: | |
2564 | entry | |
2565 | addiu sp,-n | |
2566 | daddiu sp,-n | |
2567 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2568 | inst = mips_fetch_instruction (start_pc); | |
2569 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2570 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2571 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2572 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2573 | break; | |
2574 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2575 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2576 | seen_adjsp = 1; | |
2577 | else | |
2578 | seen_adjsp = 0; | |
2579 | } | |
2580 | else if (mips_about_to_return (start_pc)) | |
2581 | { | |
2582 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
2583 | break; | |
2584 | } | |
2585 | ||
c5aa993b | 2586 | return start_pc; |
c906108c SS |
2587 | } |
2588 | ||
2589 | /* Fetch the immediate value from a MIPS16 instruction. | |
2590 | If the previous instruction was an EXTEND, use it to extend | |
2591 | the upper bits of the immediate value. This is a helper function | |
2592 | for mips16_heuristic_proc_desc. */ | |
2593 | ||
2594 | static int | |
acdb74a0 AC |
2595 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
2596 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
2597 | int nbits, /* number of bits in imm field */ |
2598 | int scale, /* scale factor to be applied to imm */ | |
2599 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
2600 | { |
2601 | int offset; | |
2602 | ||
2603 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
2604 | { | |
2605 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 2606 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
2607 | offset = 0 - (0x10000 - (offset & 0xffff)); |
2608 | return offset | (inst & 0x1f); | |
2609 | } | |
2610 | else | |
2611 | { | |
2612 | int max_imm = 1 << nbits; | |
2613 | int mask = max_imm - 1; | |
2614 | int sign_bit = max_imm >> 1; | |
2615 | ||
2616 | offset = inst & mask; | |
2617 | if (is_signed && (offset & sign_bit)) | |
2618 | offset = 0 - (max_imm - offset); | |
2619 | return offset * scale; | |
2620 | } | |
2621 | } | |
2622 | ||
2623 | ||
2624 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
2625 | stream from start_pc to limit_pc. */ | |
2626 | ||
2627 | static void | |
acdb74a0 AC |
2628 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2629 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2630 | { |
2631 | CORE_ADDR cur_pc; | |
2632 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
2633 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
2634 | unsigned inst = 0; /* current instruction */ | |
2635 | unsigned entry_inst = 0; /* the entry instruction */ | |
2636 | int reg, offset; | |
480d3dd2 | 2637 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 2638 | |
c5aa993b JM |
2639 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
2640 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2641 | |
2642 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2643 | { | |
2644 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2645 | the immediate offset extension from it in mips16_get_imm. */ | |
2646 | prev_inst = inst; | |
2647 | ||
2648 | /* Fetch and decode the instruction. */ | |
2649 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2650 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 2651 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
2652 | { |
2653 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2654 | if (offset < 0) /* negative stack adjustment? */ |
2655 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2656 | else |
2657 | /* Exit loop if a positive stack adjustment is found, which | |
2658 | usually means that the stack cleanup code in the function | |
2659 | epilogue is reached. */ | |
2660 | break; | |
2661 | } | |
2662 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2663 | { | |
2664 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2665 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2666 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2667 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2668 | } |
2669 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2670 | { | |
2671 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2672 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2673 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2674 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2675 | } |
2676 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2677 | { | |
2678 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2679 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2680 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2681 | } |
2682 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2683 | { | |
2684 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2685 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2686 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2687 | } |
c5aa993b | 2688 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2689 | { |
2690 | frame_addr = sp; | |
2691 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2692 | } | |
2693 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2694 | { | |
2695 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2696 | frame_addr = sp + offset; | |
2697 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2698 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2699 | } | |
2700 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2701 | { | |
2702 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2703 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2704 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2705 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2706 | } |
2707 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2708 | { | |
2709 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2710 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2711 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2712 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2713 | } |
c5aa993b JM |
2714 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2715 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2716 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2717 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2718 | } |
2719 | ||
c5aa993b JM |
2720 | /* The entry instruction is typically the first instruction in a function, |
2721 | and it stores registers at offsets relative to the value of the old SP | |
2722 | (before the prologue). But the value of the sp parameter to this | |
2723 | function is the new SP (after the prologue has been executed). So we | |
2724 | can't calculate those offsets until we've seen the entire prologue, | |
2725 | and can calculate what the old SP must have been. */ | |
2726 | if (entry_inst != 0) | |
2727 | { | |
2728 | int areg_count = (entry_inst >> 8) & 7; | |
2729 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2730 | |
c5aa993b JM |
2731 | /* The entry instruction always subtracts 32 from the SP. */ |
2732 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2733 | |
c5aa993b JM |
2734 | /* Now we can calculate what the SP must have been at the |
2735 | start of the function prologue. */ | |
2736 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2737 | |
c5aa993b JM |
2738 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2739 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2740 | { | |
2741 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2742 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
13326b4e | 2743 | offset += mips_abi_regsize (current_gdbarch); |
c5aa993b | 2744 | } |
c906108c | 2745 | |
c5aa993b JM |
2746 | /* Check if the ra register was pushed on the stack. */ |
2747 | offset = -4; | |
2748 | if (entry_inst & 0x20) | |
2749 | { | |
2750 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2751 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
13326b4e | 2752 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b | 2753 | } |
c906108c | 2754 | |
c5aa993b JM |
2755 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2756 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2757 | { | |
2758 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2759 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
13326b4e | 2760 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b JM |
2761 | } |
2762 | } | |
c906108c SS |
2763 | } |
2764 | ||
2765 | static void | |
fba45db2 KB |
2766 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2767 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2768 | { |
2769 | CORE_ADDR cur_pc; | |
c5aa993b | 2770 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2771 | restart: |
fe29b929 | 2772 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2773 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2774 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2775 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2776 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2777 | { | |
2778 | unsigned long inst, high_word, low_word; | |
2779 | int reg; | |
2780 | ||
2781 | /* Fetch the instruction. */ | |
2782 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2783 | ||
2784 | /* Save some code by pre-extracting some useful fields. */ | |
2785 | high_word = (inst >> 16) & 0xffff; | |
2786 | low_word = inst & 0xffff; | |
2787 | reg = high_word & 0x1f; | |
2788 | ||
c5aa993b | 2789 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2790 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2791 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2792 | { | |
2793 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2794 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2795 | else |
2796 | /* Exit loop if a positive stack adjustment is found, which | |
2797 | usually means that the stack cleanup code in the function | |
2798 | epilogue is reached. */ | |
2799 | break; | |
2800 | } | |
2801 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2802 | { | |
c5aa993b | 2803 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2804 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2805 | } |
2806 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2807 | { | |
d5ac5a39 AC |
2808 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and |
2809 | $ra. */ | |
c5aa993b | 2810 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
d5ac5a39 | 2811 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c | 2812 | } |
c5aa993b | 2813 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2814 | { |
2815 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2816 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2817 | frame_addr = sp + low_word; | |
f10683bb | 2818 | else if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM) |
c906108c SS |
2819 | { |
2820 | unsigned alloca_adjust; | |
2821 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2822 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2823 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2824 | if (alloca_adjust > 0) |
2825 | { | |
2826 | /* FP > SP + frame_size. This may be because | |
2827 | * of an alloca or somethings similar. | |
2828 | * Fix sp to "pre-alloca" value, and try again. | |
2829 | */ | |
2830 | sp += alloca_adjust; | |
2831 | goto restart; | |
2832 | } | |
2833 | } | |
2834 | } | |
c5aa993b JM |
2835 | /* move $30,$sp. With different versions of gas this will be either |
2836 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2837 | Accept any one of these. */ | |
c906108c SS |
2838 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2839 | { | |
2840 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
f10683bb | 2841 | if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM) |
c906108c SS |
2842 | { |
2843 | unsigned alloca_adjust; | |
2844 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2845 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2846 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2847 | if (alloca_adjust > 0) |
2848 | { | |
2849 | /* FP > SP + frame_size. This may be because | |
2850 | * of an alloca or somethings similar. | |
2851 | * Fix sp to "pre-alloca" value, and try again. | |
2852 | */ | |
2853 | sp += alloca_adjust; | |
2854 | goto restart; | |
2855 | } | |
2856 | } | |
2857 | } | |
c5aa993b | 2858 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2859 | { |
c5aa993b | 2860 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2861 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2862 | } |
2863 | } | |
2864 | } | |
2865 | ||
2866 | static mips_extra_func_info_t | |
acdb74a0 | 2867 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
465f7520 | 2868 | struct frame_info *next_frame) |
c906108c | 2869 | { |
479412cd DJ |
2870 | CORE_ADDR sp; |
2871 | ||
465f7520 AC |
2872 | /* Can be called when there's no process, and hence when there's no |
2873 | NEXT_FRAME. */ | |
2874 | if (next_frame != NULL) | |
f10683bb | 2875 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); |
479412cd DJ |
2876 | else |
2877 | sp = 0; | |
c906108c | 2878 | |
c5aa993b JM |
2879 | if (start_pc == 0) |
2880 | return NULL; | |
2881 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2882 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2883 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c | 2884 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
f10683bb | 2885 | PROC_FRAME_REG (&temp_proc_desc) = MIPS_SP_REGNUM; |
c906108c SS |
2886 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; |
2887 | ||
2888 | if (start_pc + 200 < limit_pc) | |
2889 | limit_pc = start_pc + 200; | |
2890 | if (pc_is_mips16 (start_pc)) | |
2891 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2892 | else | |
2893 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2894 | return &temp_proc_desc; | |
2895 | } | |
2896 | ||
6c0d6680 DJ |
2897 | struct mips_objfile_private |
2898 | { | |
2899 | bfd_size_type size; | |
2900 | char *contents; | |
2901 | }; | |
2902 | ||
2903 | /* Global used to communicate between non_heuristic_proc_desc and | |
2904 | compare_pdr_entries within qsort (). */ | |
2905 | static bfd *the_bfd; | |
2906 | ||
2907 | static int | |
2908 | compare_pdr_entries (const void *a, const void *b) | |
2909 | { | |
2910 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2911 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2912 | ||
2913 | if (lhs < rhs) | |
2914 | return -1; | |
2915 | else if (lhs == rhs) | |
2916 | return 0; | |
2917 | else | |
2918 | return 1; | |
2919 | } | |
2920 | ||
c906108c | 2921 | static mips_extra_func_info_t |
acdb74a0 | 2922 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2923 | { |
2924 | CORE_ADDR startaddr; | |
2925 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2926 | struct block *b = block_for_pc (pc); |
c906108c | 2927 | struct symbol *sym; |
6c0d6680 DJ |
2928 | struct obj_section *sec; |
2929 | struct mips_objfile_private *priv; | |
2930 | ||
c906108c SS |
2931 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
2932 | if (addrptr) | |
2933 | *addrptr = startaddr; | |
6c0d6680 DJ |
2934 | |
2935 | priv = NULL; | |
2936 | ||
2937 | sec = find_pc_section (pc); | |
2938 | if (sec != NULL) | |
c906108c | 2939 | { |
8d5f9dcb | 2940 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2941 | |
2942 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2943 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2944 | |
2945 | the_bfd = sec->objfile->obfd; | |
2946 | if (priv == NULL | |
2947 | && (the_bfd->format == bfd_object | |
2948 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2949 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2950 | { | |
2951 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2952 | This means that we should not bother with this method on 64-bit | |
2953 | targets (until that is fixed). */ | |
2954 | ||
8b92e4d5 | 2955 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2956 | sizeof (struct mips_objfile_private)); |
2957 | priv->size = 0; | |
8d5f9dcb | 2958 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2959 | } |
2960 | else if (priv == NULL) | |
2961 | { | |
2962 | asection *bfdsec; | |
2963 | ||
8b92e4d5 | 2964 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2965 | sizeof (struct mips_objfile_private)); |
2966 | ||
2967 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2968 | if (bfdsec != NULL) | |
2969 | { | |
2970 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2971 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2972 | priv->size); |
2973 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2974 | priv->contents, 0, priv->size); | |
2975 | ||
2976 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2977 | presence of multiple code sections (and other corner cases) |
2978 | it can become unsorted. Sort it so that we can use a faster | |
2979 | binary search. */ | |
2980 | qsort (priv->contents, priv->size / 32, 32, | |
2981 | compare_pdr_entries); | |
6c0d6680 DJ |
2982 | } |
2983 | else | |
2984 | priv->size = 0; | |
2985 | ||
8d5f9dcb | 2986 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2987 | } |
2988 | the_bfd = NULL; | |
2989 | ||
2990 | if (priv->size != 0) | |
2991 | { | |
2992 | int low, mid, high; | |
2993 | char *ptr; | |
34fcf120 | 2994 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2995 | |
2996 | low = 0; | |
2997 | high = priv->size / 32; | |
2998 | ||
34fcf120 DJ |
2999 | /* We've found a .pdr section describing this objfile. We want to |
3000 | find the entry which describes this code address. The .pdr | |
3001 | information is not very descriptive; we have only a function | |
3002 | start address. We have to look for the closest entry, because | |
3003 | the local symbol at the beginning of this function may have | |
3004 | been stripped - so if we ask the symbol table for the start | |
3005 | address we may get a preceding global function. */ | |
3006 | ||
3007 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
3008 | do |
3009 | { | |
6c0d6680 DJ |
3010 | mid = (low + high) / 2; |
3011 | ||
3012 | ptr = priv->contents + mid * 32; | |
3013 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
3014 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
3015 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
3016 | |
3017 | if (pdr_pc > pc) | |
6c0d6680 DJ |
3018 | high = mid; |
3019 | else | |
3020 | low = mid + 1; | |
3021 | } | |
3022 | while (low != high); | |
3023 | ||
34fcf120 DJ |
3024 | /* Both low and high point one past the PDR of interest. If |
3025 | both are zero, that means this PC is before any region | |
3026 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
3027 | greater than PC. */ | |
3028 | if (low > 0) | |
3029 | { | |
3030 | ptr = priv->contents + (low - 1) * 32; | |
3031 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
3032 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
3033 | SECT_OFF_TEXT (sec->objfile)); | |
3034 | } | |
3035 | ||
3036 | /* We don't have a range, so we have no way to know for sure | |
3037 | whether we're in the correct PDR or a PDR for a preceding | |
3038 | function and the current function was a stripped local | |
3039 | symbol. But if the PDR's PC is at least as great as the | |
3040 | best guess from the symbol table, assume that it does cover | |
3041 | the right area; if a .pdr section is present at all then | |
3042 | nearly every function will have an entry. The biggest exception | |
3043 | will be the dynamic linker stubs; conveniently these are | |
3044 | placed before .text instead of after. */ | |
3045 | ||
3046 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
3047 | { |
3048 | struct symbol *sym = find_pc_function (pc); | |
3049 | ||
34fcf120 DJ |
3050 | if (addrptr) |
3051 | *addrptr = pdr_pc; | |
3052 | ||
6c0d6680 DJ |
3053 | /* Fill in what we need of the proc_desc. */ |
3054 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 3055 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 3056 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 3057 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
3058 | |
3059 | /* Only used for dummy frames. */ | |
3060 | PROC_HIGH_ADDR (proc_desc) = 0; | |
3061 | ||
3062 | PROC_FRAME_OFFSET (proc_desc) | |
3063 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
3064 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3065 | ptr + 24); | |
3066 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
3067 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3068 | ptr + 4); | |
3069 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3070 | ptr + 12); | |
3071 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3072 | ptr + 8); | |
3073 | PROC_FREG_OFFSET (proc_desc) | |
3074 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
3075 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3076 | ptr + 28); | |
3077 | proc_desc->pdr.isym = (long) sym; | |
3078 | ||
3079 | return proc_desc; | |
3080 | } | |
3081 | } | |
c906108c SS |
3082 | } |
3083 | ||
6c0d6680 DJ |
3084 | if (b == NULL) |
3085 | return NULL; | |
3086 | ||
3087 | if (startaddr > BLOCK_START (b)) | |
3088 | { | |
3089 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
3090 | print_frame_info. It might be better to move this check into |
3091 | symbol reading. */ | |
6c0d6680 DJ |
3092 | return NULL; |
3093 | } | |
3094 | ||
176620f1 | 3095 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 3096 | |
c906108c SS |
3097 | /* If we never found a PDR for this function in symbol reading, then |
3098 | examine prologues to find the information. */ | |
3099 | if (sym) | |
3100 | { | |
3101 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
3102 | if (PROC_FRAME_REG (proc_desc) == -1) | |
3103 | return NULL; | |
3104 | else | |
3105 | return proc_desc; | |
3106 | } | |
3107 | else | |
3108 | return NULL; | |
3109 | } | |
3110 | ||
3111 | ||
3112 | static mips_extra_func_info_t | |
465f7520 | 3113 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame) |
c906108c SS |
3114 | { |
3115 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 3116 | CORE_ADDR startaddr = 0; |
c906108c SS |
3117 | |
3118 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
3119 | ||
3120 | if (proc_desc) | |
3121 | { | |
3122 | /* IF this is the topmost frame AND | |
3123 | * (this proc does not have debugging information OR | |
3124 | * the PC is in the procedure prologue) | |
3125 | * THEN create a "heuristic" proc_desc (by analyzing | |
3126 | * the actual code) to replace the "official" proc_desc. | |
3127 | */ | |
3128 | if (next_frame == NULL) | |
3129 | { | |
3130 | struct symtab_and_line val; | |
3131 | struct symbol *proc_symbol = | |
c86b5b38 | 3132 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
3133 | |
3134 | if (proc_symbol) | |
3135 | { | |
3136 | val = find_pc_line (BLOCK_START | |
6d82d43b | 3137 | (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); |
c906108c SS |
3138 | val.pc = val.end ? val.end : pc; |
3139 | } | |
3140 | if (!proc_symbol || pc < val.pc) | |
3141 | { | |
3142 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 | 3143 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
465f7520 | 3144 | pc, next_frame); |
c906108c SS |
3145 | if (found_heuristic) |
3146 | proc_desc = found_heuristic; | |
3147 | } | |
3148 | } | |
3149 | } | |
3150 | else | |
3151 | { | |
c906108c SS |
3152 | if (startaddr == 0) |
3153 | startaddr = heuristic_proc_start (pc); | |
3154 | ||
465f7520 | 3155 | proc_desc = heuristic_proc_desc (startaddr, pc, next_frame); |
c906108c SS |
3156 | } |
3157 | return proc_desc; | |
3158 | } | |
3159 | ||
c906108c SS |
3160 | /* MIPS stack frames are almost impenetrable. When execution stops, |
3161 | we basically have to look at symbol information for the function | |
3162 | that we stopped in, which tells us *which* register (if any) is | |
3163 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 3164 | the frame itself is at. |
c906108c SS |
3165 | |
3166 | This presents a problem when trying to examine a stack in memory | |
3167 | (that isn't executing at the moment), using the "frame" command. We | |
3168 | don't have a PC, nor do we have any registers except SP. | |
3169 | ||
3170 | This routine takes two arguments, SP and PC, and tries to make the | |
3171 | cached frames look as if these two arguments defined a frame on the | |
3172 | cache. This allows the rest of info frame to extract the important | |
3173 | arguments without difficulty. */ | |
3174 | ||
3175 | struct frame_info * | |
acdb74a0 | 3176 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
3177 | { |
3178 | if (argc != 2) | |
3179 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
3180 | ||
3181 | return create_new_frame (argv[0], argv[1]); | |
3182 | } | |
3183 | ||
f09ded24 AC |
3184 | /* According to the current ABI, should the type be passed in a |
3185 | floating-point register (assuming that there is space)? When there | |
3186 | is no FPU, FP are not even considered as possibile candidates for | |
3187 | FP registers and, consequently this returns false - forces FP | |
3188 | arguments into integer registers. */ | |
3189 | ||
3190 | static int | |
3191 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
3192 | { | |
3193 | return ((typecode == TYPE_CODE_FLT | |
3194 | || (MIPS_EABI | |
6d82d43b AC |
3195 | && (typecode == TYPE_CODE_STRUCT |
3196 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
3197 | && TYPE_NFIELDS (arg_type) == 1 |
3198 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 3199 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
3200 | } |
3201 | ||
49e790b0 DJ |
3202 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
3203 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
3204 | ||
3205 | static int | |
3206 | mips_type_needs_double_align (struct type *type) | |
3207 | { | |
3208 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 3209 | |
49e790b0 DJ |
3210 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
3211 | return 1; | |
3212 | else if (typecode == TYPE_CODE_STRUCT) | |
3213 | { | |
3214 | if (TYPE_NFIELDS (type) < 1) | |
3215 | return 0; | |
3216 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
3217 | } | |
3218 | else if (typecode == TYPE_CODE_UNION) | |
3219 | { | |
361d1df0 | 3220 | int i, n; |
49e790b0 DJ |
3221 | |
3222 | n = TYPE_NFIELDS (type); | |
3223 | for (i = 0; i < n; i++) | |
3224 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
3225 | return 1; | |
3226 | return 0; | |
3227 | } | |
3228 | return 0; | |
3229 | } | |
3230 | ||
dc604539 AC |
3231 | /* Adjust the address downward (direction of stack growth) so that it |
3232 | is correctly aligned for a new stack frame. */ | |
3233 | static CORE_ADDR | |
3234 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
3235 | { | |
5b03f266 | 3236 | return align_down (addr, 16); |
dc604539 AC |
3237 | } |
3238 | ||
6d82d43b AC |
3239 | /* Determine how a return value is stored within the MIPS register |
3240 | file, given the return type `valtype'. */ | |
3241 | ||
3242 | struct return_value_word | |
3243 | { | |
3244 | int len; | |
3245 | int reg; | |
3246 | int reg_offset; | |
3247 | int buf_offset; | |
3248 | }; | |
3249 | ||
3250 | static void | |
3251 | return_value_location (struct type *valtype, | |
3252 | struct return_value_word *hi, | |
3253 | struct return_value_word *lo) | |
3254 | { | |
3255 | int len = TYPE_LENGTH (valtype); | |
3256 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3257 | ||
3258 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3259 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3260 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3261 | { | |
ceae6e75 | 3262 | if (mips_abi_regsize (current_gdbarch) < 8 && len == 8) |
6d82d43b AC |
3263 | { |
3264 | /* We need to break a 64bit float in two 32 bit halves and | |
ceae6e75 | 3265 | spread them across a floating-point register pair. */ |
6d82d43b AC |
3266 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
3267 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
3268 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3269 | && register_size (current_gdbarch, | |
3270 | mips_regnum (current_gdbarch)-> | |
3271 | fp0) == 8) ? 4 : 0); | |
3272 | hi->reg_offset = lo->reg_offset; | |
3273 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
3274 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
3275 | lo->len = 4; | |
3276 | hi->len = 4; | |
3277 | } | |
3278 | else | |
3279 | { | |
3280 | /* The floating point value fits in a single floating-point | |
3281 | register. */ | |
3282 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3283 | && register_size (current_gdbarch, | |
3284 | mips_regnum (current_gdbarch)-> | |
3285 | fp0) == 8 | |
3286 | && len == 4) ? 4 : 0); | |
3287 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
3288 | lo->len = len; | |
3289 | lo->buf_offset = 0; | |
3290 | hi->len = 0; | |
3291 | hi->reg_offset = 0; | |
3292 | hi->buf_offset = 0; | |
3293 | hi->reg = 0; | |
3294 | } | |
3295 | } | |
3296 | else | |
3297 | { | |
3298 | /* Locate a result possibly spread across two registers. */ | |
3299 | int regnum = 2; | |
3300 | lo->reg = regnum + 0; | |
3301 | hi->reg = regnum + 1; | |
3302 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3303 | && len < mips_abi_regsize (current_gdbarch)) |
6d82d43b AC |
3304 | { |
3305 | /* "un-left-justify" the value in the low register */ | |
13326b4e | 3306 | lo->reg_offset = mips_abi_regsize (current_gdbarch) - len; |
6d82d43b AC |
3307 | lo->len = len; |
3308 | hi->reg_offset = 0; | |
3309 | hi->len = 0; | |
3310 | } | |
13326b4e AC |
3311 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_abi_regsize (current_gdbarch) /* odd-size structs */ |
3312 | && len < mips_abi_regsize (current_gdbarch) * 2 | |
6d82d43b AC |
3313 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
3314 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3315 | { | |
3316 | /* "un-left-justify" the value spread across two registers. */ | |
13326b4e AC |
3317 | lo->reg_offset = 2 * mips_abi_regsize (current_gdbarch) - len; |
3318 | lo->len = mips_abi_regsize (current_gdbarch) - lo->reg_offset; | |
6d82d43b AC |
3319 | hi->reg_offset = 0; |
3320 | hi->len = len - lo->len; | |
3321 | } | |
3322 | else | |
3323 | { | |
3324 | /* Only perform a partial copy of the second register. */ | |
3325 | lo->reg_offset = 0; | |
3326 | hi->reg_offset = 0; | |
13326b4e | 3327 | if (len > mips_abi_regsize (current_gdbarch)) |
6d82d43b | 3328 | { |
13326b4e AC |
3329 | lo->len = mips_abi_regsize (current_gdbarch); |
3330 | hi->len = len - mips_abi_regsize (current_gdbarch); | |
6d82d43b AC |
3331 | } |
3332 | else | |
3333 | { | |
3334 | lo->len = len; | |
3335 | hi->len = 0; | |
3336 | } | |
3337 | } | |
3338 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3339 | && register_size (current_gdbarch, regnum) == 8 | |
13326b4e | 3340 | && mips_abi_regsize (current_gdbarch) == 4) |
6d82d43b AC |
3341 | { |
3342 | /* Account for the fact that only the least-signficant part | |
3343 | of the register is being used */ | |
3344 | lo->reg_offset += 4; | |
3345 | hi->reg_offset += 4; | |
3346 | } | |
3347 | lo->buf_offset = 0; | |
3348 | hi->buf_offset = lo->len; | |
3349 | } | |
3350 | } | |
3351 | ||
3352 | /* Should call_function allocate stack space for a struct return? */ | |
3353 | ||
3354 | static int | |
3355 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
3356 | { | |
3357 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
13326b4e | 3358 | return (TYPE_LENGTH (type) > 2 * mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3359 | } |
3360 | ||
3361 | /* Should call_function pass struct by reference? | |
3362 | For each architecture, structs are passed either by | |
3363 | value or by reference, depending on their size. */ | |
3364 | ||
3365 | static int | |
3366 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
3367 | { | |
3368 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
3369 | int len = TYPE_LENGTH (check_typedef (type)); | |
3370 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3371 | ||
3372 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
13326b4e | 3373 | return (len > mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3374 | |
3375 | return 0; | |
3376 | } | |
3377 | ||
f7ab6ec6 | 3378 | static CORE_ADDR |
7d9b040b | 3379 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3380 | struct regcache *regcache, CORE_ADDR bp_addr, |
3381 | int nargs, struct value **args, CORE_ADDR sp, | |
3382 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
3383 | { |
3384 | int argreg; | |
3385 | int float_argreg; | |
3386 | int argnum; | |
3387 | int len = 0; | |
3388 | int stack_offset = 0; | |
480d3dd2 | 3389 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3390 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 3391 | |
25ab4790 AC |
3392 | /* For shared libraries, "t9" needs to point at the function |
3393 | address. */ | |
3394 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3395 | ||
3396 | /* Set the return address register to point to the entry point of | |
3397 | the program, where a breakpoint lies in wait. */ | |
3398 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3399 | ||
c906108c | 3400 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
3401 | are properly aligned. The stack has to be at least 64-bit |
3402 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3403 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3404 | aligned, so we round to this widest known alignment. */ | |
3405 | ||
5b03f266 AC |
3406 | sp = align_down (sp, 16); |
3407 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 3408 | |
46e0f506 | 3409 | /* Now make space on the stack for the args. We allocate more |
c906108c | 3410 | than necessary for EABI, because the first few arguments are |
46e0f506 | 3411 | passed in registers, but that's OK. */ |
c906108c | 3412 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 3413 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3414 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3415 | sp -= align_up (len, 16); |
c906108c | 3416 | |
9ace0497 | 3417 | if (mips_debug) |
6d82d43b | 3418 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3419 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
3420 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 3421 | |
c906108c SS |
3422 | /* Initialize the integer and float register pointers. */ |
3423 | argreg = A0_REGNUM; | |
56cea623 | 3424 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 3425 | |
46e0f506 | 3426 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 3427 | if (struct_return) |
9ace0497 AC |
3428 | { |
3429 | if (mips_debug) | |
3430 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3431 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3432 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
3433 | write_register (argreg++, struct_addr); |
3434 | } | |
c906108c SS |
3435 | |
3436 | /* Now load as many as possible of the first arguments into | |
3437 | registers, and push the rest onto the stack. Loop thru args | |
3438 | from first to last. */ | |
3439 | for (argnum = 0; argnum < nargs; argnum++) | |
3440 | { | |
3441 | char *val; | |
d9d9c31f | 3442 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 3443 | struct value *arg = args[argnum]; |
c906108c SS |
3444 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
3445 | int len = TYPE_LENGTH (arg_type); | |
3446 | enum type_code typecode = TYPE_CODE (arg_type); | |
3447 | ||
9ace0497 AC |
3448 | if (mips_debug) |
3449 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3450 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3451 | argnum + 1, len, (int) typecode); |
9ace0497 | 3452 | |
c906108c | 3453 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3454 | reference. */ |
13326b4e | 3455 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 3456 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3457 | { |
13326b4e | 3458 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 3459 | VALUE_ADDRESS (arg)); |
c906108c | 3460 | typecode = TYPE_CODE_PTR; |
13326b4e | 3461 | len = mips_abi_regsize (gdbarch); |
c906108c | 3462 | val = valbuf; |
9ace0497 AC |
3463 | if (mips_debug) |
3464 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3465 | } |
3466 | else | |
c5aa993b | 3467 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
3468 | |
3469 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3470 | even-numbered floating point register. Round the FP register |
3471 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3472 | left. Non MIPS_EABI targets also pass the FP in the integer |
3473 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3474 | if (mips_abi_regsize (gdbarch) < 8 |
3475 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
3476 | { |
3477 | if ((float_argreg & 1)) | |
3478 | float_argreg++; | |
3479 | } | |
c906108c SS |
3480 | |
3481 | /* Floating point arguments passed in registers have to be | |
3482 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3483 | are passed in register pairs; the even register gets |
3484 | the low word, and the odd register gets the high word. | |
3485 | On non-EABI processors, the first two floating point arguments are | |
3486 | also copied to general registers, because MIPS16 functions | |
3487 | don't use float registers for arguments. This duplication of | |
3488 | arguments in general registers can't hurt non-MIPS16 functions | |
3489 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3490 | /* MIPS_EABI squeezes a struct that contains a single floating |
3491 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3492 | stack. */ |
f09ded24 AC |
3493 | if (fp_register_arg_p (typecode, arg_type) |
3494 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 3495 | { |
ceae6e75 | 3496 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 3497 | { |
d7449b42 | 3498 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
3499 | unsigned long regval; |
3500 | ||
3501 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 3502 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 3503 | if (mips_debug) |
acdb74a0 | 3504 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3505 | float_argreg, phex (regval, 4)); |
c906108c | 3506 | write_register (float_argreg++, regval); |
c906108c SS |
3507 | |
3508 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 3509 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 3510 | if (mips_debug) |
acdb74a0 | 3511 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3512 | float_argreg, phex (regval, 4)); |
c906108c | 3513 | write_register (float_argreg++, regval); |
c906108c SS |
3514 | } |
3515 | else | |
3516 | { | |
3517 | /* This is a floating point value that fits entirely | |
3518 | in a single register. */ | |
53a5351d | 3519 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3520 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
3521 | LONGEST regval = extract_unsigned_integer (val, len); |
3522 | if (mips_debug) | |
acdb74a0 | 3523 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3524 | float_argreg, phex (regval, len)); |
c906108c | 3525 | write_register (float_argreg++, regval); |
c906108c SS |
3526 | } |
3527 | } | |
3528 | else | |
3529 | { | |
3530 | /* Copy the argument to general registers or the stack in | |
3531 | register-sized pieces. Large arguments are split between | |
3532 | registers and stack. */ | |
4246e332 | 3533 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3534 | mips_abi_regsize() are treated specially: Irix cc passes |
3535 | them in registers where gcc sometimes puts them on the | |
3536 | stack. For maximum compatibility, we will put them in | |
3537 | both places. */ | |
13326b4e AC |
3538 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3539 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 3540 | |
f09ded24 | 3541 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3542 | register are only written to memory. */ |
c906108c SS |
3543 | while (len > 0) |
3544 | { | |
ebafbe83 | 3545 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3546 | int stack_used_p = 0; |
13326b4e AC |
3547 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3548 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 3549 | |
acdb74a0 AC |
3550 | if (mips_debug) |
3551 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3552 | partial_len); | |
3553 | ||
566f0f7a | 3554 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3555 | if (argreg > MIPS_LAST_ARG_REGNUM |
3556 | || odd_sized_struct | |
3557 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3558 | { |
c906108c SS |
3559 | /* Should shorter than int integer values be |
3560 | promoted to int before being stored? */ | |
c906108c | 3561 | int longword_offset = 0; |
9ace0497 | 3562 | CORE_ADDR addr; |
566f0f7a | 3563 | stack_used_p = 1; |
d7449b42 | 3564 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3565 | { |
13326b4e | 3566 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3567 | && (typecode == TYPE_CODE_INT |
3568 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3569 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3570 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
3571 | else if ((typecode == TYPE_CODE_STRUCT |
3572 | || typecode == TYPE_CODE_UNION) | |
3573 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
3574 | < mips_stack_argsize (gdbarch))) |
3575 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 3576 | } |
c5aa993b | 3577 | |
9ace0497 AC |
3578 | if (mips_debug) |
3579 | { | |
cb3d25d1 MS |
3580 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3581 | paddr_nz (stack_offset)); | |
3582 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3583 | paddr_nz (longword_offset)); | |
9ace0497 | 3584 | } |
361d1df0 | 3585 | |
9ace0497 AC |
3586 | addr = sp + stack_offset + longword_offset; |
3587 | ||
3588 | if (mips_debug) | |
3589 | { | |
3590 | int i; | |
6d82d43b | 3591 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3592 | paddr_nz (addr)); |
9ace0497 AC |
3593 | for (i = 0; i < partial_len; i++) |
3594 | { | |
6d82d43b | 3595 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3596 | val[i] & 0xff); |
9ace0497 AC |
3597 | } |
3598 | } | |
3599 | write_memory (addr, val, partial_len); | |
c906108c SS |
3600 | } |
3601 | ||
f09ded24 AC |
3602 | /* Note!!! This is NOT an else clause. Odd sized |
3603 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3604 | arguments will not. */ |
566f0f7a | 3605 | /* Write this portion of the argument to a general |
6d82d43b | 3606 | purpose register. */ |
f09ded24 AC |
3607 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3608 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3609 | { |
6d82d43b AC |
3610 | LONGEST regval = |
3611 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3612 | |
9ace0497 | 3613 | if (mips_debug) |
acdb74a0 | 3614 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3615 | argreg, |
6d82d43b | 3616 | phex (regval, |
13326b4e | 3617 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3618 | write_register (argreg, regval); |
3619 | argreg++; | |
c906108c | 3620 | } |
c5aa993b | 3621 | |
c906108c SS |
3622 | len -= partial_len; |
3623 | val += partial_len; | |
3624 | ||
566f0f7a | 3625 | /* Compute the the offset into the stack at which we |
6d82d43b | 3626 | will copy the next parameter. |
566f0f7a | 3627 | |
566f0f7a | 3628 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3629 | only needs to be adjusted when it has been used. */ |
c906108c | 3630 | |
46e0f506 | 3631 | if (stack_used_p) |
480d3dd2 | 3632 | stack_offset += align_up (partial_len, |
13326b4e | 3633 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3634 | } |
3635 | } | |
9ace0497 AC |
3636 | if (mips_debug) |
3637 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3638 | } |
3639 | ||
f10683bb | 3640 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3641 | |
0f71a2f6 JM |
3642 | /* Return adjusted stack pointer. */ |
3643 | return sp; | |
3644 | } | |
3645 | ||
6d82d43b AC |
3646 | /* Given a return value in `regbuf' with a type `valtype', extract and |
3647 | copy its value into `valbuf'. */ | |
3648 | ||
3649 | static void | |
3650 | mips_eabi_extract_return_value (struct type *valtype, | |
3651 | char regbuf[], char *valbuf) | |
3652 | { | |
3653 | struct return_value_word lo; | |
3654 | struct return_value_word hi; | |
3655 | return_value_location (valtype, &hi, &lo); | |
3656 | ||
3657 | memcpy (valbuf + lo.buf_offset, | |
3658 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
3659 | lo.reg_offset, lo.len); | |
3660 | ||
3661 | if (hi.len > 0) | |
3662 | memcpy (valbuf + hi.buf_offset, | |
3663 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3664 | hi.reg_offset, hi.len); | |
3665 | } | |
3666 | ||
3667 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3668 | value into the appropriate register. */ | |
3669 | ||
3670 | static void | |
3671 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3672 | { | |
3673 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3674 | struct return_value_word lo; | |
3675 | struct return_value_word hi; | |
3676 | return_value_location (valtype, &hi, &lo); | |
3677 | ||
3678 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3679 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3680 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3681 | raw_buffer, register_size (current_gdbarch, | |
3682 | lo.reg)); | |
3683 | ||
3684 | if (hi.len > 0) | |
3685 | { | |
3686 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3687 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3688 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3689 | raw_buffer, | |
3690 | register_size (current_gdbarch, | |
3691 | hi.reg)); | |
3692 | } | |
3693 | } | |
3694 | ||
3695 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3696 | |
f7ab6ec6 | 3697 | static CORE_ADDR |
7d9b040b | 3698 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3699 | struct regcache *regcache, CORE_ADDR bp_addr, |
3700 | int nargs, struct value **args, CORE_ADDR sp, | |
3701 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3702 | { |
3703 | int argreg; | |
3704 | int float_argreg; | |
3705 | int argnum; | |
3706 | int len = 0; | |
3707 | int stack_offset = 0; | |
480d3dd2 | 3708 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3709 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3710 | |
25ab4790 AC |
3711 | /* For shared libraries, "t9" needs to point at the function |
3712 | address. */ | |
3713 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3714 | ||
3715 | /* Set the return address register to point to the entry point of | |
3716 | the program, where a breakpoint lies in wait. */ | |
3717 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3718 | ||
cb3d25d1 MS |
3719 | /* First ensure that the stack and structure return address (if any) |
3720 | are properly aligned. The stack has to be at least 64-bit | |
3721 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3722 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3723 | aligned, so we round to this widest known alignment. */ | |
3724 | ||
5b03f266 AC |
3725 | sp = align_down (sp, 16); |
3726 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3727 | |
3728 | /* Now make space on the stack for the args. */ | |
3729 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3730 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3731 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3732 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3733 | |
3734 | if (mips_debug) | |
6d82d43b | 3735 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3736 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3737 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3738 | |
3739 | /* Initialize the integer and float register pointers. */ | |
3740 | argreg = A0_REGNUM; | |
56cea623 | 3741 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3742 | |
46e0f506 | 3743 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3744 | if (struct_return) |
3745 | { | |
3746 | if (mips_debug) | |
3747 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3748 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3749 | argreg, paddr_nz (struct_addr)); |
3750 | write_register (argreg++, struct_addr); | |
3751 | } | |
3752 | ||
3753 | /* Now load as many as possible of the first arguments into | |
3754 | registers, and push the rest onto the stack. Loop thru args | |
3755 | from first to last. */ | |
3756 | for (argnum = 0; argnum < nargs; argnum++) | |
3757 | { | |
3758 | char *val; | |
cb3d25d1 MS |
3759 | struct value *arg = args[argnum]; |
3760 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3761 | int len = TYPE_LENGTH (arg_type); | |
3762 | enum type_code typecode = TYPE_CODE (arg_type); | |
3763 | ||
3764 | if (mips_debug) | |
3765 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3766 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3767 | argnum + 1, len, (int) typecode); |
3768 | ||
3769 | val = (char *) VALUE_CONTENTS (arg); | |
3770 | ||
3771 | if (fp_register_arg_p (typecode, arg_type) | |
3772 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3773 | { | |
3774 | /* This is a floating point value that fits entirely | |
3775 | in a single register. */ | |
3776 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3777 | above to ensure that it is even register aligned. */ | |
3778 | LONGEST regval = extract_unsigned_integer (val, len); | |
3779 | if (mips_debug) | |
3780 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3781 | float_argreg, phex (regval, len)); | |
3782 | write_register (float_argreg++, regval); | |
3783 | ||
3784 | if (mips_debug) | |
3785 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3786 | argreg, phex (regval, len)); | |
3787 | write_register (argreg, regval); | |
3788 | argreg += 1; | |
3789 | } | |
3790 | else | |
3791 | { | |
3792 | /* Copy the argument to general registers or the stack in | |
3793 | register-sized pieces. Large arguments are split between | |
3794 | registers and stack. */ | |
4246e332 | 3795 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3796 | mips_abi_regsize() are treated specially: Irix cc passes |
3797 | them in registers where gcc sometimes puts them on the | |
3798 | stack. For maximum compatibility, we will put them in | |
3799 | both places. */ | |
13326b4e AC |
3800 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3801 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3802 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3803 | register are only written to memory. */ |
cb3d25d1 MS |
3804 | while (len > 0) |
3805 | { | |
3806 | /* Rememer if the argument was written to the stack. */ | |
3807 | int stack_used_p = 0; | |
13326b4e AC |
3808 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3809 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3810 | |
3811 | if (mips_debug) | |
3812 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3813 | partial_len); | |
3814 | ||
3815 | /* Write this portion of the argument to the stack. */ | |
3816 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3817 | || odd_sized_struct | |
3818 | || fp_register_arg_p (typecode, arg_type)) | |
3819 | { | |
3820 | /* Should shorter than int integer values be | |
3821 | promoted to int before being stored? */ | |
3822 | int longword_offset = 0; | |
3823 | CORE_ADDR addr; | |
3824 | stack_used_p = 1; | |
3825 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3826 | { | |
13326b4e | 3827 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3828 | && (typecode == TYPE_CODE_INT |
3829 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3830 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3831 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3832 | } |
3833 | ||
3834 | if (mips_debug) | |
3835 | { | |
3836 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3837 | paddr_nz (stack_offset)); | |
3838 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3839 | paddr_nz (longword_offset)); | |
3840 | } | |
3841 | ||
3842 | addr = sp + stack_offset + longword_offset; | |
3843 | ||
3844 | if (mips_debug) | |
3845 | { | |
3846 | int i; | |
6d82d43b | 3847 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3848 | paddr_nz (addr)); |
3849 | for (i = 0; i < partial_len; i++) | |
3850 | { | |
6d82d43b | 3851 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3852 | val[i] & 0xff); |
3853 | } | |
3854 | } | |
3855 | write_memory (addr, val, partial_len); | |
3856 | } | |
3857 | ||
3858 | /* Note!!! This is NOT an else clause. Odd sized | |
3859 | structs may go thru BOTH paths. Floating point | |
3860 | arguments will not. */ | |
3861 | /* Write this portion of the argument to a general | |
6d82d43b | 3862 | purpose register. */ |
cb3d25d1 MS |
3863 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3864 | && !fp_register_arg_p (typecode, arg_type)) | |
3865 | { | |
6d82d43b AC |
3866 | LONGEST regval = |
3867 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3868 | |
3869 | /* A non-floating-point argument being passed in a | |
3870 | general register. If a struct or union, and if | |
3871 | the remaining length is smaller than the register | |
3872 | size, we have to adjust the register value on | |
3873 | big endian targets. | |
3874 | ||
3875 | It does not seem to be necessary to do the | |
3876 | same for integral types. | |
3877 | ||
3878 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3879 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3880 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3881 | part of storing the argument in a register a |
3882 | register (the left shift isn't generated when | |
1b13c4f6 | 3883 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3884 | it is quite possible that this is GCC |
3885 | contradicting the LE/O32 ABI, GDB has not been | |
3886 | adjusted to accommodate this. Either someone | |
3887 | needs to demonstrate that the LE/O32 ABI | |
3888 | specifies such a left shift OR this new ABI gets | |
3889 | identified as such and GDB gets tweaked | |
3890 | accordingly. */ | |
cb3d25d1 MS |
3891 | |
3892 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3893 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3894 | && (typecode == TYPE_CODE_STRUCT || |
3895 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3896 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3897 | TARGET_CHAR_BIT); |
3898 | ||
3899 | if (mips_debug) | |
3900 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3901 | argreg, | |
6d82d43b | 3902 | phex (regval, |
13326b4e | 3903 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3904 | write_register (argreg, regval); |
3905 | argreg++; | |
3906 | } | |
3907 | ||
3908 | len -= partial_len; | |
3909 | val += partial_len; | |
3910 | ||
3911 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3912 | will copy the next parameter. |
cb3d25d1 MS |
3913 | |
3914 | In N32 (N64?), the stack_offset only needs to be | |
3915 | adjusted when it has been used. */ | |
3916 | ||
3917 | if (stack_used_p) | |
480d3dd2 | 3918 | stack_offset += align_up (partial_len, |
13326b4e | 3919 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3920 | } |
3921 | } | |
3922 | if (mips_debug) | |
3923 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3924 | } | |
3925 | ||
f10683bb | 3926 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3927 | |
cb3d25d1 MS |
3928 | /* Return adjusted stack pointer. */ |
3929 | return sp; | |
3930 | } | |
3931 | ||
6d82d43b AC |
3932 | static enum return_value_convention |
3933 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3934 | struct type *type, struct regcache *regcache, | |
3935 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3936 | { |
6d82d43b AC |
3937 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3938 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3939 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3940 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3941 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3942 | return RETURN_VALUE_STRUCT_CONVENTION; |
3943 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3944 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3945 | { | |
3946 | /* A floating-point value belongs in the least significant part | |
3947 | of FP0. */ | |
3948 | if (mips_debug) | |
3949 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3950 | mips_xfer_register (regcache, | |
3951 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3952 | TYPE_LENGTH (type), | |
3953 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3954 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3955 | } | |
3956 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3957 | && TYPE_NFIELDS (type) <= 2 | |
3958 | && TYPE_NFIELDS (type) >= 1 | |
3959 | && ((TYPE_NFIELDS (type) == 1 | |
3960 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3961 | == TYPE_CODE_FLT)) | |
3962 | || (TYPE_NFIELDS (type) == 2 | |
3963 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3964 | == TYPE_CODE_FLT) | |
3965 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3966 | == TYPE_CODE_FLT))) | |
3967 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3968 | { | |
3969 | /* A struct that contains one or two floats. Each value is part | |
3970 | in the least significant part of their floating point | |
3971 | register.. */ | |
6d82d43b AC |
3972 | int regnum; |
3973 | int field; | |
3974 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3975 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3976 | { | |
3977 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3978 | / TARGET_CHAR_BIT); | |
3979 | if (mips_debug) | |
3980 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3981 | offset); | |
3982 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3983 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3984 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3985 | } | |
3986 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3987 | } | |
3988 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3989 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3990 | { | |
3991 | /* A structure or union. Extract the left justified value, | |
3992 | regardless of the byte order. I.e. DO NOT USE | |
3993 | mips_xfer_lower. */ | |
3994 | int offset; | |
3995 | int regnum; | |
3996 | for (offset = 0, regnum = V0_REGNUM; | |
3997 | offset < TYPE_LENGTH (type); | |
3998 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3999 | { | |
4000 | int xfer = register_size (current_gdbarch, regnum); | |
4001 | if (offset + xfer > TYPE_LENGTH (type)) | |
4002 | xfer = TYPE_LENGTH (type) - offset; | |
4003 | if (mips_debug) | |
4004 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4005 | offset, xfer, regnum); | |
4006 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4007 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
4008 | } | |
4009 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4010 | } | |
4011 | else | |
4012 | { | |
4013 | /* A scalar extract each part but least-significant-byte | |
4014 | justified. */ | |
4015 | int offset; | |
4016 | int regnum; | |
4017 | for (offset = 0, regnum = V0_REGNUM; | |
4018 | offset < TYPE_LENGTH (type); | |
4019 | offset += register_size (current_gdbarch, regnum), regnum++) | |
4020 | { | |
4021 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
4022 | if (offset + xfer > TYPE_LENGTH (type)) |
4023 | xfer = TYPE_LENGTH (type) - offset; | |
4024 | if (mips_debug) | |
4025 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4026 | offset, xfer, regnum); | |
4027 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4028 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4029 | } | |
4030 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4031 | } | |
4032 | } | |
4033 | ||
4034 | /* O32 ABI stuff. */ | |
4035 | ||
4036 | static CORE_ADDR | |
7d9b040b | 4037 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4038 | struct regcache *regcache, CORE_ADDR bp_addr, |
4039 | int nargs, struct value **args, CORE_ADDR sp, | |
4040 | int struct_return, CORE_ADDR struct_addr) | |
4041 | { | |
4042 | int argreg; | |
4043 | int float_argreg; | |
4044 | int argnum; | |
4045 | int len = 0; | |
4046 | int stack_offset = 0; | |
4047 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 4048 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
4049 | |
4050 | /* For shared libraries, "t9" needs to point at the function | |
4051 | address. */ | |
4052 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
4053 | ||
4054 | /* Set the return address register to point to the entry point of | |
4055 | the program, where a breakpoint lies in wait. */ | |
4056 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
4057 | ||
4058 | /* First ensure that the stack and structure return address (if any) | |
4059 | are properly aligned. The stack has to be at least 64-bit | |
4060 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
4061 | aligned. For n32 and n64, stack frames need to be 128-bit |
4062 | aligned, so we round to this widest known alignment. */ | |
4063 | ||
5b03f266 AC |
4064 | sp = align_down (sp, 16); |
4065 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
4066 | |
4067 | /* Now make space on the stack for the args. */ | |
4068 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4069 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4070 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4071 | sp -= align_up (len, 16); |
ebafbe83 MS |
4072 | |
4073 | if (mips_debug) | |
6d82d43b | 4074 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4075 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
4076 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
4077 | |
4078 | /* Initialize the integer and float register pointers. */ | |
4079 | argreg = A0_REGNUM; | |
56cea623 | 4080 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 4081 | |
bcb0cc15 | 4082 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
4083 | if (struct_return) |
4084 | { | |
4085 | if (mips_debug) | |
4086 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4087 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
4088 | argreg, paddr_nz (struct_addr)); |
4089 | write_register (argreg++, struct_addr); | |
13326b4e | 4090 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
4091 | } |
4092 | ||
4093 | /* Now load as many as possible of the first arguments into | |
4094 | registers, and push the rest onto the stack. Loop thru args | |
4095 | from first to last. */ | |
4096 | for (argnum = 0; argnum < nargs; argnum++) | |
4097 | { | |
4098 | char *val; | |
ebafbe83 MS |
4099 | struct value *arg = args[argnum]; |
4100 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4101 | int len = TYPE_LENGTH (arg_type); | |
4102 | enum type_code typecode = TYPE_CODE (arg_type); | |
4103 | ||
4104 | if (mips_debug) | |
4105 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4106 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
4107 | argnum + 1, len, (int) typecode); |
4108 | ||
4109 | val = (char *) VALUE_CONTENTS (arg); | |
4110 | ||
4111 | /* 32-bit ABIs always start floating point arguments in an | |
4112 | even-numbered floating point register. Round the FP register | |
4113 | up before the check to see if there are any FP registers | |
4114 | left. O32/O64 targets also pass the FP in the integer | |
4115 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4116 | if (mips_abi_regsize (gdbarch) < 8 |
4117 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
4118 | { |
4119 | if ((float_argreg & 1)) | |
4120 | float_argreg++; | |
4121 | } | |
4122 | ||
4123 | /* Floating point arguments passed in registers have to be | |
4124 | treated specially. On 32-bit architectures, doubles | |
4125 | are passed in register pairs; the even register gets | |
4126 | the low word, and the odd register gets the high word. | |
4127 | On O32/O64, the first two floating point arguments are | |
4128 | also copied to general registers, because MIPS16 functions | |
4129 | don't use float registers for arguments. This duplication of | |
4130 | arguments in general registers can't hurt non-MIPS16 functions | |
4131 | because those registers are normally skipped. */ | |
4132 | ||
4133 | if (fp_register_arg_p (typecode, arg_type) | |
4134 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4135 | { | |
ceae6e75 | 4136 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
4137 | { |
4138 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4139 | unsigned long regval; | |
4140 | ||
4141 | /* Write the low word of the double to the even register(s). */ | |
4142 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4143 | if (mips_debug) | |
4144 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4145 | float_argreg, phex (regval, 4)); | |
4146 | write_register (float_argreg++, regval); | |
4147 | if (mips_debug) | |
4148 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4149 | argreg, phex (regval, 4)); | |
4150 | write_register (argreg++, regval); | |
4151 | ||
4152 | /* Write the high word of the double to the odd register(s). */ | |
4153 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4154 | if (mips_debug) | |
4155 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4156 | float_argreg, phex (regval, 4)); | |
4157 | write_register (float_argreg++, regval); | |
4158 | ||
4159 | if (mips_debug) | |
4160 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4161 | argreg, phex (regval, 4)); | |
4162 | write_register (argreg++, regval); | |
4163 | } | |
4164 | else | |
4165 | { | |
4166 | /* This is a floating point value that fits entirely | |
4167 | in a single register. */ | |
4168 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4169 | above to ensure that it is even register aligned. */ |
46cac009 AC |
4170 | LONGEST regval = extract_unsigned_integer (val, len); |
4171 | if (mips_debug) | |
4172 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4173 | float_argreg, phex (regval, len)); | |
4174 | write_register (float_argreg++, regval); | |
4175 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4176 | registers for each argument. The below is (my |
4177 | guess) to ensure that the corresponding integer | |
4178 | register has reserved the same space. */ | |
46cac009 AC |
4179 | if (mips_debug) |
4180 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4181 | argreg, phex (regval, len)); | |
4182 | write_register (argreg, regval); | |
ceae6e75 | 4183 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
4184 | } |
4185 | /* Reserve space for the FP register. */ | |
13326b4e | 4186 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
4187 | } |
4188 | else | |
4189 | { | |
4190 | /* Copy the argument to general registers or the stack in | |
4191 | register-sized pieces. Large arguments are split between | |
4192 | registers and stack. */ | |
4246e332 | 4193 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4194 | mips_abi_regsize() are treated specially: Irix cc passes |
4195 | them in registers where gcc sometimes puts them on the | |
4196 | stack. For maximum compatibility, we will put them in | |
4197 | both places. */ | |
13326b4e AC |
4198 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4199 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
4200 | /* Structures should be aligned to eight bytes (even arg registers) |
4201 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4202 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
4203 | && mips_type_needs_double_align (arg_type)) |
4204 | { | |
4205 | if ((argreg & 1)) | |
6d82d43b | 4206 | argreg++; |
46cac009 AC |
4207 | } |
4208 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4209 | register are only written to memory. */ |
46cac009 AC |
4210 | while (len > 0) |
4211 | { | |
4212 | /* Remember if the argument was written to the stack. */ | |
4213 | int stack_used_p = 0; | |
13326b4e AC |
4214 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4215 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
4216 | |
4217 | if (mips_debug) | |
4218 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4219 | partial_len); | |
4220 | ||
4221 | /* Write this portion of the argument to the stack. */ | |
4222 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4223 | || odd_sized_struct | |
4224 | || fp_register_arg_p (typecode, arg_type)) | |
4225 | { | |
4226 | /* Should shorter than int integer values be | |
4227 | promoted to int before being stored? */ | |
4228 | int longword_offset = 0; | |
4229 | CORE_ADDR addr; | |
4230 | stack_used_p = 1; | |
4231 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4232 | { | |
13326b4e | 4233 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4234 | && (typecode == TYPE_CODE_INT |
4235 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4236 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4237 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
4238 | } |
4239 | ||
4240 | if (mips_debug) | |
4241 | { | |
4242 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4243 | paddr_nz (stack_offset)); | |
4244 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4245 | paddr_nz (longword_offset)); | |
4246 | } | |
4247 | ||
4248 | addr = sp + stack_offset + longword_offset; | |
4249 | ||
4250 | if (mips_debug) | |
4251 | { | |
4252 | int i; | |
6d82d43b | 4253 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
4254 | paddr_nz (addr)); |
4255 | for (i = 0; i < partial_len; i++) | |
4256 | { | |
6d82d43b | 4257 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
4258 | val[i] & 0xff); |
4259 | } | |
4260 | } | |
4261 | write_memory (addr, val, partial_len); | |
4262 | } | |
4263 | ||
4264 | /* Note!!! This is NOT an else clause. Odd sized | |
4265 | structs may go thru BOTH paths. Floating point | |
4266 | arguments will not. */ | |
4267 | /* Write this portion of the argument to a general | |
6d82d43b | 4268 | purpose register. */ |
46cac009 AC |
4269 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4270 | && !fp_register_arg_p (typecode, arg_type)) | |
4271 | { | |
4272 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4273 | /* Value may need to be sign extended, because |
1b13c4f6 | 4274 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
4275 | |
4276 | /* A non-floating-point argument being passed in a | |
4277 | general register. If a struct or union, and if | |
4278 | the remaining length is smaller than the register | |
4279 | size, we have to adjust the register value on | |
4280 | big endian targets. | |
4281 | ||
4282 | It does not seem to be necessary to do the | |
4283 | same for integral types. | |
4284 | ||
4285 | Also don't do this adjustment on O64 binaries. | |
4286 | ||
4287 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4288 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4289 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
4290 | part of storing the argument in a register a |
4291 | register (the left shift isn't generated when | |
1b13c4f6 | 4292 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4293 | it is quite possible that this is GCC |
4294 | contradicting the LE/O32 ABI, GDB has not been | |
4295 | adjusted to accommodate this. Either someone | |
4296 | needs to demonstrate that the LE/O32 ABI | |
4297 | specifies such a left shift OR this new ABI gets | |
4298 | identified as such and GDB gets tweaked | |
4299 | accordingly. */ | |
4300 | ||
13326b4e | 4301 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 4302 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4303 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
4304 | && (typecode == TYPE_CODE_STRUCT || |
4305 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4306 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
4307 | TARGET_CHAR_BIT); |
4308 | ||
4309 | if (mips_debug) | |
4310 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4311 | argreg, | |
6d82d43b | 4312 | phex (regval, |
13326b4e | 4313 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
4314 | write_register (argreg, regval); |
4315 | argreg++; | |
4316 | ||
4317 | /* Prevent subsequent floating point arguments from | |
4318 | being passed in floating point registers. */ | |
4319 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4320 | } | |
4321 | ||
4322 | len -= partial_len; | |
4323 | val += partial_len; | |
4324 | ||
4325 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4326 | will copy the next parameter. |
46cac009 | 4327 | |
6d82d43b AC |
4328 | In older ABIs, the caller reserved space for |
4329 | registers that contained arguments. This was loosely | |
4330 | refered to as their "home". Consequently, space is | |
4331 | always allocated. */ | |
46cac009 | 4332 | |
480d3dd2 | 4333 | stack_offset += align_up (partial_len, |
13326b4e | 4334 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
4335 | } |
4336 | } | |
4337 | if (mips_debug) | |
4338 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4339 | } | |
4340 | ||
f10683bb | 4341 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4342 | |
46cac009 AC |
4343 | /* Return adjusted stack pointer. */ |
4344 | return sp; | |
4345 | } | |
4346 | ||
6d82d43b AC |
4347 | static enum return_value_convention |
4348 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4349 | struct regcache *regcache, | |
4350 | void *readbuf, const void *writebuf) | |
4351 | { | |
4352 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4353 | ||
4354 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4355 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4356 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4357 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4358 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4359 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4360 | { | |
4361 | /* A single-precision floating-point value. It fits in the | |
4362 | least significant part of FP0. */ | |
4363 | if (mips_debug) | |
4364 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4365 | mips_xfer_register (regcache, | |
4366 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4367 | TYPE_LENGTH (type), | |
4368 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4369 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4370 | } | |
4371 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4372 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4373 | { | |
4374 | /* A double-precision floating-point value. The most | |
4375 | significant part goes in FP1, and the least significant in | |
4376 | FP0. */ | |
4377 | if (mips_debug) | |
4378 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4379 | switch (TARGET_BYTE_ORDER) | |
4380 | { | |
4381 | case BFD_ENDIAN_LITTLE: | |
4382 | mips_xfer_register (regcache, | |
4383 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4384 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4385 | mips_xfer_register (regcache, | |
4386 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4387 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4388 | break; | |
4389 | case BFD_ENDIAN_BIG: | |
4390 | mips_xfer_register (regcache, | |
4391 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4392 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4393 | mips_xfer_register (regcache, | |
4394 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4395 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4396 | break; | |
4397 | default: | |
4398 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4399 | } | |
4400 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4401 | } | |
4402 | #if 0 | |
4403 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4404 | && TYPE_NFIELDS (type) <= 2 | |
4405 | && TYPE_NFIELDS (type) >= 1 | |
4406 | && ((TYPE_NFIELDS (type) == 1 | |
4407 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4408 | == TYPE_CODE_FLT)) | |
4409 | || (TYPE_NFIELDS (type) == 2 | |
4410 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4411 | == TYPE_CODE_FLT) | |
4412 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4413 | == TYPE_CODE_FLT))) | |
4414 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4415 | { | |
4416 | /* A struct that contains one or two floats. Each value is part | |
4417 | in the least significant part of their floating point | |
4418 | register.. */ | |
4419 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
4420 | int regnum; | |
4421 | int field; | |
4422 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
4423 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
4424 | { | |
4425 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4426 | / TARGET_CHAR_BIT); | |
4427 | if (mips_debug) | |
4428 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4429 | offset); | |
4430 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
4431 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4432 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4433 | } | |
4434 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4435 | } | |
4436 | #endif | |
4437 | #if 0 | |
4438 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4439 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4440 | { | |
4441 | /* A structure or union. Extract the left justified value, | |
4442 | regardless of the byte order. I.e. DO NOT USE | |
4443 | mips_xfer_lower. */ | |
4444 | int offset; | |
4445 | int regnum; | |
4446 | for (offset = 0, regnum = V0_REGNUM; | |
4447 | offset < TYPE_LENGTH (type); | |
4448 | offset += register_size (current_gdbarch, regnum), regnum++) | |
4449 | { | |
4450 | int xfer = register_size (current_gdbarch, regnum); | |
4451 | if (offset + xfer > TYPE_LENGTH (type)) | |
4452 | xfer = TYPE_LENGTH (type) - offset; | |
4453 | if (mips_debug) | |
4454 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4455 | offset, xfer, regnum); | |
4456 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4457 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
4458 | } | |
4459 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4460 | } | |
4461 | #endif | |
4462 | else | |
4463 | { | |
4464 | /* A scalar extract each part but least-significant-byte | |
4465 | justified. o32 thinks registers are 4 byte, regardless of | |
4466 | the ISA. mips_stack_argsize controls this. */ | |
4467 | int offset; | |
4468 | int regnum; | |
4469 | for (offset = 0, regnum = V0_REGNUM; | |
4470 | offset < TYPE_LENGTH (type); | |
13326b4e | 4471 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 4472 | { |
13326b4e | 4473 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
4474 | if (offset + xfer > TYPE_LENGTH (type)) |
4475 | xfer = TYPE_LENGTH (type) - offset; | |
4476 | if (mips_debug) | |
4477 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4478 | offset, xfer, regnum); | |
4479 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4480 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4481 | } | |
4482 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4483 | } | |
4484 | } | |
4485 | ||
4486 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4487 | ABI. */ | |
46cac009 AC |
4488 | |
4489 | static CORE_ADDR | |
7d9b040b | 4490 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4491 | struct regcache *regcache, CORE_ADDR bp_addr, |
4492 | int nargs, | |
4493 | struct value **args, CORE_ADDR sp, | |
4494 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4495 | { |
4496 | int argreg; | |
4497 | int float_argreg; | |
4498 | int argnum; | |
4499 | int len = 0; | |
4500 | int stack_offset = 0; | |
480d3dd2 | 4501 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 4502 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4503 | |
25ab4790 AC |
4504 | /* For shared libraries, "t9" needs to point at the function |
4505 | address. */ | |
4506 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
4507 | ||
4508 | /* Set the return address register to point to the entry point of | |
4509 | the program, where a breakpoint lies in wait. */ | |
4510 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
4511 | ||
46cac009 AC |
4512 | /* First ensure that the stack and structure return address (if any) |
4513 | are properly aligned. The stack has to be at least 64-bit | |
4514 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4515 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4516 | aligned, so we round to this widest known alignment. */ | |
4517 | ||
5b03f266 AC |
4518 | sp = align_down (sp, 16); |
4519 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4520 | |
4521 | /* Now make space on the stack for the args. */ | |
4522 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4523 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4524 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4525 | sp -= align_up (len, 16); |
46cac009 AC |
4526 | |
4527 | if (mips_debug) | |
6d82d43b | 4528 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4529 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
4530 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
4531 | |
4532 | /* Initialize the integer and float register pointers. */ | |
4533 | argreg = A0_REGNUM; | |
56cea623 | 4534 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4535 | |
4536 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4537 | if (struct_return) | |
4538 | { | |
4539 | if (mips_debug) | |
4540 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4541 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4542 | argreg, paddr_nz (struct_addr)); |
4543 | write_register (argreg++, struct_addr); | |
13326b4e | 4544 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
4545 | } |
4546 | ||
4547 | /* Now load as many as possible of the first arguments into | |
4548 | registers, and push the rest onto the stack. Loop thru args | |
4549 | from first to last. */ | |
4550 | for (argnum = 0; argnum < nargs; argnum++) | |
4551 | { | |
4552 | char *val; | |
46cac009 AC |
4553 | struct value *arg = args[argnum]; |
4554 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4555 | int len = TYPE_LENGTH (arg_type); | |
4556 | enum type_code typecode = TYPE_CODE (arg_type); | |
4557 | ||
4558 | if (mips_debug) | |
4559 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4560 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4561 | argnum + 1, len, (int) typecode); |
4562 | ||
4563 | val = (char *) VALUE_CONTENTS (arg); | |
4564 | ||
4565 | /* 32-bit ABIs always start floating point arguments in an | |
4566 | even-numbered floating point register. Round the FP register | |
4567 | up before the check to see if there are any FP registers | |
4568 | left. O32/O64 targets also pass the FP in the integer | |
4569 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4570 | if (mips_abi_regsize (gdbarch) < 8 |
4571 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
4572 | { |
4573 | if ((float_argreg & 1)) | |
4574 | float_argreg++; | |
4575 | } | |
4576 | ||
4577 | /* Floating point arguments passed in registers have to be | |
4578 | treated specially. On 32-bit architectures, doubles | |
4579 | are passed in register pairs; the even register gets | |
4580 | the low word, and the odd register gets the high word. | |
4581 | On O32/O64, the first two floating point arguments are | |
4582 | also copied to general registers, because MIPS16 functions | |
4583 | don't use float registers for arguments. This duplication of | |
4584 | arguments in general registers can't hurt non-MIPS16 functions | |
4585 | because those registers are normally skipped. */ | |
4586 | ||
4587 | if (fp_register_arg_p (typecode, arg_type) | |
4588 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4589 | { | |
ceae6e75 | 4590 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
4591 | { |
4592 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4593 | unsigned long regval; | |
4594 | ||
4595 | /* Write the low word of the double to the even register(s). */ | |
4596 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4597 | if (mips_debug) | |
4598 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4599 | float_argreg, phex (regval, 4)); | |
4600 | write_register (float_argreg++, regval); | |
4601 | if (mips_debug) | |
4602 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4603 | argreg, phex (regval, 4)); | |
4604 | write_register (argreg++, regval); | |
4605 | ||
4606 | /* Write the high word of the double to the odd register(s). */ | |
4607 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4608 | if (mips_debug) | |
4609 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4610 | float_argreg, phex (regval, 4)); | |
4611 | write_register (float_argreg++, regval); | |
4612 | ||
4613 | if (mips_debug) | |
4614 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4615 | argreg, phex (regval, 4)); | |
4616 | write_register (argreg++, regval); | |
4617 | } | |
4618 | else | |
4619 | { | |
4620 | /* This is a floating point value that fits entirely | |
4621 | in a single register. */ | |
4622 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4623 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4624 | LONGEST regval = extract_unsigned_integer (val, len); |
4625 | if (mips_debug) | |
4626 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4627 | float_argreg, phex (regval, len)); | |
4628 | write_register (float_argreg++, regval); | |
4629 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4630 | registers for each argument. The below is (my |
4631 | guess) to ensure that the corresponding integer | |
4632 | register has reserved the same space. */ | |
ebafbe83 MS |
4633 | if (mips_debug) |
4634 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4635 | argreg, phex (regval, len)); | |
4636 | write_register (argreg, regval); | |
ceae6e75 | 4637 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4638 | } |
4639 | /* Reserve space for the FP register. */ | |
13326b4e | 4640 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4641 | } |
4642 | else | |
4643 | { | |
4644 | /* Copy the argument to general registers or the stack in | |
4645 | register-sized pieces. Large arguments are split between | |
4646 | registers and stack. */ | |
4246e332 | 4647 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4648 | mips_abi_regsize() are treated specially: Irix cc passes |
4649 | them in registers where gcc sometimes puts them on the | |
4650 | stack. For maximum compatibility, we will put them in | |
4651 | both places. */ | |
13326b4e AC |
4652 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4653 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4654 | /* Structures should be aligned to eight bytes (even arg registers) |
4655 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4656 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4657 | && mips_type_needs_double_align (arg_type)) |
4658 | { | |
4659 | if ((argreg & 1)) | |
6d82d43b | 4660 | argreg++; |
ebafbe83 MS |
4661 | } |
4662 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4663 | register are only written to memory. */ |
ebafbe83 MS |
4664 | while (len > 0) |
4665 | { | |
4666 | /* Remember if the argument was written to the stack. */ | |
4667 | int stack_used_p = 0; | |
13326b4e AC |
4668 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4669 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4670 | |
4671 | if (mips_debug) | |
4672 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4673 | partial_len); | |
4674 | ||
4675 | /* Write this portion of the argument to the stack. */ | |
4676 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4677 | || odd_sized_struct | |
4678 | || fp_register_arg_p (typecode, arg_type)) | |
4679 | { | |
4680 | /* Should shorter than int integer values be | |
4681 | promoted to int before being stored? */ | |
4682 | int longword_offset = 0; | |
4683 | CORE_ADDR addr; | |
4684 | stack_used_p = 1; | |
4685 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4686 | { | |
13326b4e | 4687 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4688 | && (typecode == TYPE_CODE_INT |
4689 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4690 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4691 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4692 | } |
4693 | ||
4694 | if (mips_debug) | |
4695 | { | |
4696 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4697 | paddr_nz (stack_offset)); | |
4698 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4699 | paddr_nz (longword_offset)); | |
4700 | } | |
4701 | ||
4702 | addr = sp + stack_offset + longword_offset; | |
4703 | ||
4704 | if (mips_debug) | |
4705 | { | |
4706 | int i; | |
6d82d43b | 4707 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4708 | paddr_nz (addr)); |
4709 | for (i = 0; i < partial_len; i++) | |
4710 | { | |
6d82d43b | 4711 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4712 | val[i] & 0xff); |
4713 | } | |
4714 | } | |
4715 | write_memory (addr, val, partial_len); | |
4716 | } | |
4717 | ||
4718 | /* Note!!! This is NOT an else clause. Odd sized | |
4719 | structs may go thru BOTH paths. Floating point | |
4720 | arguments will not. */ | |
4721 | /* Write this portion of the argument to a general | |
6d82d43b | 4722 | purpose register. */ |
ebafbe83 MS |
4723 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4724 | && !fp_register_arg_p (typecode, arg_type)) | |
4725 | { | |
4726 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4727 | /* Value may need to be sign extended, because |
1b13c4f6 | 4728 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4729 | |
4730 | /* A non-floating-point argument being passed in a | |
4731 | general register. If a struct or union, and if | |
4732 | the remaining length is smaller than the register | |
4733 | size, we have to adjust the register value on | |
4734 | big endian targets. | |
4735 | ||
4736 | It does not seem to be necessary to do the | |
4737 | same for integral types. | |
4738 | ||
4739 | Also don't do this adjustment on O64 binaries. | |
4740 | ||
4741 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4742 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4743 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4744 | part of storing the argument in a register a |
4745 | register (the left shift isn't generated when | |
1b13c4f6 | 4746 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4747 | it is quite possible that this is GCC |
4748 | contradicting the LE/O32 ABI, GDB has not been | |
4749 | adjusted to accommodate this. Either someone | |
4750 | needs to demonstrate that the LE/O32 ABI | |
4751 | specifies such a left shift OR this new ABI gets | |
4752 | identified as such and GDB gets tweaked | |
4753 | accordingly. */ | |
4754 | ||
13326b4e | 4755 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4756 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4757 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4758 | && (typecode == TYPE_CODE_STRUCT || |
4759 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4760 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4761 | TARGET_CHAR_BIT); |
4762 | ||
4763 | if (mips_debug) | |
4764 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4765 | argreg, | |
6d82d43b | 4766 | phex (regval, |
13326b4e | 4767 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4768 | write_register (argreg, regval); |
4769 | argreg++; | |
4770 | ||
4771 | /* Prevent subsequent floating point arguments from | |
4772 | being passed in floating point registers. */ | |
4773 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4774 | } | |
4775 | ||
4776 | len -= partial_len; | |
4777 | val += partial_len; | |
4778 | ||
4779 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4780 | will copy the next parameter. |
ebafbe83 | 4781 | |
6d82d43b AC |
4782 | In older ABIs, the caller reserved space for |
4783 | registers that contained arguments. This was loosely | |
4784 | refered to as their "home". Consequently, space is | |
4785 | always allocated. */ | |
ebafbe83 | 4786 | |
480d3dd2 | 4787 | stack_offset += align_up (partial_len, |
13326b4e | 4788 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4789 | } |
4790 | } | |
4791 | if (mips_debug) | |
4792 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4793 | } | |
4794 | ||
f10683bb | 4795 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4796 | |
ebafbe83 MS |
4797 | /* Return adjusted stack pointer. */ |
4798 | return sp; | |
4799 | } | |
4800 | ||
f7ab6ec6 | 4801 | static void |
6d82d43b AC |
4802 | mips_o64_extract_return_value (struct type *valtype, |
4803 | char regbuf[], char *valbuf) | |
c906108c | 4804 | { |
6d82d43b AC |
4805 | struct return_value_word lo; |
4806 | struct return_value_word hi; | |
4807 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4808 | |
6d82d43b AC |
4809 | memcpy (valbuf + lo.buf_offset, |
4810 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4811 | lo.reg_offset, lo.len); | |
4812 | ||
4813 | if (hi.len > 0) | |
4814 | memcpy (valbuf + hi.buf_offset, | |
4815 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4816 | hi.reg_offset, hi.len); | |
4817 | } | |
4818 | ||
4819 | static void | |
4820 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4821 | { | |
4822 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4823 | struct return_value_word lo; | |
4824 | struct return_value_word hi; | |
4825 | return_value_location (valtype, &hi, &lo); | |
4826 | ||
4827 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4828 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4829 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4830 | raw_buffer, register_size (current_gdbarch, | |
4831 | lo.reg)); | |
4832 | ||
4833 | if (hi.len > 0) | |
4834 | { | |
4835 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4836 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4837 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4838 | raw_buffer, | |
4839 | register_size (current_gdbarch, | |
4840 | hi.reg)); | |
4841 | } | |
4842 | } | |
4843 | ||
dd824b04 DJ |
4844 | /* Floating point register management. |
4845 | ||
4846 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4847 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4848 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4849 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4850 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4851 | double precision floats into two 32-bit chunks and store them in | |
4852 | consecutive fp regs. To display 64-bit floats stored in this | |
4853 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4854 | Throw in user-configurable endianness and you have a real mess. | |
4855 | ||
4856 | The way this works is: | |
4857 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4858 | double-precision value will be split across two logical registers. | |
4859 | The lower-numbered logical register will hold the low-order bits, | |
4860 | regardless of the processor's endianness. | |
4861 | - If we are on a 64-bit processor, and we are looking for a | |
4862 | single-precision value, it will be in the low ordered bits | |
4863 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4864 | save slot in memory. | |
4865 | - If we are in 64-bit mode, everything is straightforward. | |
4866 | ||
4867 | Note that this code only deals with "live" registers at the top of the | |
4868 | stack. We will attempt to deal with saved registers later, when | |
4869 | the raw/cooked register interface is in place. (We need a general | |
4870 | interface that can deal with dynamic saved register sizes -- fp | |
4871 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4872 | and below). */ | |
4873 | ||
67b2c998 DJ |
4874 | static struct type * |
4875 | mips_float_register_type (void) | |
4876 | { | |
361d1df0 | 4877 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4878 | return builtin_type_ieee_single_big; |
4879 | else | |
4880 | return builtin_type_ieee_single_little; | |
4881 | } | |
4882 | ||
4883 | static struct type * | |
4884 | mips_double_register_type (void) | |
4885 | { | |
361d1df0 | 4886 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4887 | return builtin_type_ieee_double_big; |
4888 | else | |
4889 | return builtin_type_ieee_double_little; | |
4890 | } | |
4891 | ||
dd824b04 DJ |
4892 | /* Copy a 32-bit single-precision value from the current frame |
4893 | into rare_buffer. */ | |
4894 | ||
4895 | static void | |
e11c53d2 AC |
4896 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4897 | char *rare_buffer) | |
dd824b04 | 4898 | { |
719ec221 | 4899 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4900 | char *raw_buffer = alloca (raw_size); |
4901 | ||
e11c53d2 | 4902 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4903 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4904 | if (raw_size == 8) | |
4905 | { | |
4906 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4907 | 32 bits. */ |
dd824b04 DJ |
4908 | int offset; |
4909 | ||
4910 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4911 | offset = 4; | |
4912 | else | |
4913 | offset = 0; | |
4914 | ||
4915 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4916 | } | |
4917 | else | |
4918 | { | |
4919 | memcpy (rare_buffer, raw_buffer, 4); | |
4920 | } | |
4921 | } | |
4922 | ||
4923 | /* Copy a 64-bit double-precision value from the current frame into | |
4924 | rare_buffer. This may include getting half of it from the next | |
4925 | register. */ | |
4926 | ||
4927 | static void | |
e11c53d2 AC |
4928 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4929 | char *rare_buffer) | |
dd824b04 | 4930 | { |
719ec221 | 4931 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4932 | |
4933 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4934 | { | |
4935 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4936 | all 64 bits. */ |
e11c53d2 | 4937 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4938 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4939 | } | |
4940 | else | |
4941 | { | |
56cea623 | 4942 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4943 | internal_error (__FILE__, __LINE__, |
4944 | "mips_read_fp_register_double: bad access to " | |
4945 | "odd-numbered FP register"); | |
4946 | ||
4947 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4948 | each register. */ |
dd824b04 DJ |
4949 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4950 | { | |
e11c53d2 AC |
4951 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4952 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4953 | } |
361d1df0 | 4954 | else |
dd824b04 | 4955 | { |
e11c53d2 AC |
4956 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4957 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4958 | } |
4959 | } | |
4960 | } | |
4961 | ||
c906108c | 4962 | static void |
e11c53d2 AC |
4963 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4964 | int regnum) | |
c5aa993b | 4965 | { /* do values for FP (float) regs */ |
dd824b04 | 4966 | char *raw_buffer; |
3903d437 AC |
4967 | double doub, flt1; /* doubles extracted from raw hex data */ |
4968 | int inv1, inv2; | |
c5aa993b | 4969 | |
6d82d43b AC |
4970 | raw_buffer = |
4971 | (char *) alloca (2 * | |
4972 | register_size (current_gdbarch, | |
4973 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4974 | |
e11c53d2 AC |
4975 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4976 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4977 | ""); | |
f0ef6b29 | 4978 | |
719ec221 | 4979 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4980 | { |
f0ef6b29 KB |
4981 | /* 4-byte registers: Print hex and floating. Also print even |
4982 | numbered registers as doubles. */ | |
e11c53d2 | 4983 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4984 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4985 | |
6d82d43b AC |
4986 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4987 | file); | |
dd824b04 | 4988 | |
e11c53d2 | 4989 | fprintf_filtered (file, " flt: "); |
1adad886 | 4990 | if (inv1) |
e11c53d2 | 4991 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4992 | else |
e11c53d2 | 4993 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4994 | |
f0ef6b29 KB |
4995 | if (regnum % 2 == 0) |
4996 | { | |
e11c53d2 | 4997 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4998 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4999 | &inv2); |
1adad886 | 5000 | |
e11c53d2 | 5001 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 5002 | if (inv2) |
e11c53d2 | 5003 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 5004 | else |
e11c53d2 | 5005 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 5006 | } |
c906108c SS |
5007 | } |
5008 | else | |
dd824b04 | 5009 | { |
f0ef6b29 | 5010 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 5011 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 5012 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 5013 | |
e11c53d2 | 5014 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
5015 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
5016 | ||
361d1df0 | 5017 | |
6d82d43b AC |
5018 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
5019 | file); | |
f0ef6b29 | 5020 | |
e11c53d2 | 5021 | fprintf_filtered (file, " flt: "); |
1adad886 | 5022 | if (inv1) |
e11c53d2 | 5023 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 5024 | else |
e11c53d2 | 5025 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 5026 | |
e11c53d2 | 5027 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 5028 | if (inv2) |
e11c53d2 | 5029 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 5030 | else |
e11c53d2 | 5031 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
5032 | } |
5033 | } | |
5034 | ||
5035 | static void | |
e11c53d2 AC |
5036 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
5037 | int regnum, int all) | |
f0ef6b29 | 5038 | { |
a4b8ebc8 | 5039 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 5040 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 5041 | int offset; |
1adad886 | 5042 | |
a4b8ebc8 | 5043 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 5044 | { |
e11c53d2 | 5045 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
5046 | return; |
5047 | } | |
5048 | ||
5049 | /* Get the data in raw format. */ | |
e11c53d2 | 5050 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 5051 | { |
e11c53d2 | 5052 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 5053 | return; |
c906108c | 5054 | } |
f0ef6b29 | 5055 | |
e11c53d2 | 5056 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
5057 | |
5058 | /* The problem with printing numeric register names (r26, etc.) is that | |
5059 | the user can't use them on input. Probably the best solution is to | |
5060 | fix it so that either the numeric or the funky (a2, etc.) names | |
5061 | are accepted on input. */ | |
5062 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 5063 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 5064 | else |
e11c53d2 | 5065 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
5066 | |
5067 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
5068 | offset = |
5069 | register_size (current_gdbarch, | |
5070 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
5071 | else |
5072 | offset = 0; | |
5073 | ||
6d82d43b AC |
5074 | print_scalar_formatted (raw_buffer + offset, |
5075 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
5076 | file); | |
c906108c SS |
5077 | } |
5078 | ||
f0ef6b29 KB |
5079 | /* Replacement for generic do_registers_info. |
5080 | Print regs in pretty columns. */ | |
5081 | ||
5082 | static int | |
e11c53d2 AC |
5083 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
5084 | int regnum) | |
f0ef6b29 | 5085 | { |
e11c53d2 AC |
5086 | fprintf_filtered (file, " "); |
5087 | mips_print_fp_register (file, frame, regnum); | |
5088 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
5089 | return regnum + 1; |
5090 | } | |
5091 | ||
5092 | ||
c906108c SS |
5093 | /* Print a row's worth of GP (int) registers, with name labels above */ |
5094 | ||
5095 | static int | |
e11c53d2 | 5096 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 5097 | int start_regnum) |
c906108c | 5098 | { |
a4b8ebc8 | 5099 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 5100 | /* do values for GP (int) regs */ |
d9d9c31f | 5101 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 5102 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 5103 | int col, byte; |
a4b8ebc8 | 5104 | int regnum; |
c906108c SS |
5105 | |
5106 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 5107 | fprintf_filtered (file, " "); |
a4b8ebc8 | 5108 | for (col = 0, regnum = start_regnum; |
6d82d43b | 5109 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
5110 | { |
5111 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 5112 | continue; /* unused register */ |
6d82d43b AC |
5113 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5114 | TYPE_CODE_FLT) | |
c5aa993b | 5115 | break; /* end the row: reached FP register */ |
6d82d43b | 5116 | fprintf_filtered (file, |
d5ac5a39 | 5117 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 5118 | REGISTER_NAME (regnum)); |
c906108c SS |
5119 | col++; |
5120 | } | |
a4b8ebc8 | 5121 | /* print the R0 to R31 names */ |
20e6603c AC |
5122 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
5123 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
5124 | else | |
5125 | fprintf_filtered (file, "\n "); | |
c906108c | 5126 | |
c906108c | 5127 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 5128 | for (col = 0, regnum = start_regnum; |
6d82d43b | 5129 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
5130 | { |
5131 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 5132 | continue; /* unused register */ |
6d82d43b AC |
5133 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5134 | TYPE_CODE_FLT) | |
c5aa993b | 5135 | break; /* end row: reached FP register */ |
c906108c | 5136 | /* OK: get the data in raw format. */ |
e11c53d2 | 5137 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
5138 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
5139 | /* pad small registers */ | |
4246e332 | 5140 | for (byte = 0; |
d5ac5a39 | 5141 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 5142 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
5143 | printf_filtered (" "); |
5144 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 5145 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
5146 | for (byte = |
5147 | register_size (current_gdbarch, | |
5148 | regnum) - register_size (current_gdbarch, regnum); | |
5149 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 5150 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 5151 | else |
c73e8f27 | 5152 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 5153 | byte >= 0; byte--) |
e11c53d2 AC |
5154 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
5155 | fprintf_filtered (file, " "); | |
c906108c SS |
5156 | col++; |
5157 | } | |
c5aa993b | 5158 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 5159 | fprintf_filtered (file, "\n"); |
c906108c SS |
5160 | |
5161 | return regnum; | |
5162 | } | |
5163 | ||
5164 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
5165 | ||
bf1f5b4c | 5166 | static void |
e11c53d2 AC |
5167 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
5168 | struct frame_info *frame, int regnum, int all) | |
c906108c | 5169 | { |
c5aa993b | 5170 | if (regnum != -1) /* do one specified register */ |
c906108c | 5171 | { |
a4b8ebc8 | 5172 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
5173 | if (*(REGISTER_NAME (regnum)) == '\0') |
5174 | error ("Not a valid register for the current processor type"); | |
5175 | ||
e11c53d2 AC |
5176 | mips_print_register (file, frame, regnum, 0); |
5177 | fprintf_filtered (file, "\n"); | |
c906108c | 5178 | } |
c5aa993b JM |
5179 | else |
5180 | /* do all (or most) registers */ | |
c906108c | 5181 | { |
a4b8ebc8 AC |
5182 | regnum = NUM_REGS; |
5183 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 5184 | { |
6d82d43b AC |
5185 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5186 | TYPE_CODE_FLT) | |
e11c53d2 AC |
5187 | { |
5188 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
5189 | regnum = print_fp_register_row (file, frame, regnum); | |
5190 | else | |
5191 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
5192 | } | |
c906108c | 5193 | else |
e11c53d2 | 5194 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
5195 | } |
5196 | } | |
5197 | } | |
5198 | ||
c906108c SS |
5199 | /* Is this a branch with a delay slot? */ |
5200 | ||
a14ed312 | 5201 | static int is_delayed (unsigned long); |
c906108c SS |
5202 | |
5203 | static int | |
acdb74a0 | 5204 | is_delayed (unsigned long insn) |
c906108c SS |
5205 | { |
5206 | int i; | |
5207 | for (i = 0; i < NUMOPCODES; ++i) | |
5208 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
5209 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
5210 | break; | |
5211 | return (i < NUMOPCODES | |
5212 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
5213 | | INSN_COND_BRANCH_DELAY | |
5214 | | INSN_COND_BRANCH_LIKELY))); | |
5215 | } | |
5216 | ||
5217 | int | |
acdb74a0 | 5218 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
5219 | { |
5220 | char buf[MIPS_INSTLEN]; | |
5221 | ||
5222 | /* There is no branch delay slot on MIPS16. */ | |
5223 | if (pc_is_mips16 (pc)) | |
5224 | return 0; | |
5225 | ||
5226 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
5227 | /* If error reading memory, guess that it is not a delayed branch. */ | |
5228 | return 0; | |
6d82d43b AC |
5229 | return is_delayed ((unsigned long) |
5230 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
5231 | } |
5232 | ||
c906108c SS |
5233 | /* Skip the PC past function prologue instructions (32-bit version). |
5234 | This is a helper function for mips_skip_prologue. */ | |
5235 | ||
5236 | static CORE_ADDR | |
f7b9e9fc | 5237 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 5238 | { |
c5aa993b JM |
5239 | t_inst inst; |
5240 | CORE_ADDR end_pc; | |
5241 | int seen_sp_adjust = 0; | |
5242 | int load_immediate_bytes = 0; | |
5243 | ||
74da7425 AC |
5244 | /* Find an upper bound on the prologue. */ |
5245 | end_pc = skip_prologue_using_sal (pc); | |
5246 | if (end_pc == 0) | |
6d82d43b | 5247 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 5248 | |
c5aa993b JM |
5249 | /* Skip the typical prologue instructions. These are the stack adjustment |
5250 | instruction and the instructions that save registers on the stack | |
5251 | or in the gcc frame. */ | |
74da7425 | 5252 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
5253 | { |
5254 | unsigned long high_word; | |
c906108c | 5255 | |
c5aa993b JM |
5256 | inst = mips_fetch_instruction (pc); |
5257 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 5258 | |
c5aa993b JM |
5259 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
5260 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
5261 | seen_sp_adjust = 1; | |
5262 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
5263 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
5264 | seen_sp_adjust = 1; | |
5265 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
5266 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
5267 | && (inst & 0x001F0000)) /* reg != $zero */ | |
5268 | continue; | |
5269 | ||
5270 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
5271 | continue; | |
5272 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
5273 | /* sx reg,n($s8) */ | |
5274 | continue; /* reg != $zero */ | |
5275 | ||
5276 | /* move $s8,$sp. With different versions of gas this will be either | |
5277 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
5278 | Accept any one of these. */ | |
5279 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
5280 | continue; | |
5281 | ||
5282 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
5283 | continue; | |
6d82d43b AC |
5284 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
5285 | continue; | |
5286 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
5287 | continue; | |
5288 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
5289 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
5290 | continue; | |
5291 | /* The following instructions load $at or $t0 with an immediate | |
5292 | value in preparation for a stack adjustment via | |
5293 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
5294 | a local variable, so we accept them only before a stack adjustment | |
5295 | instruction was seen. */ | |
5296 | else if (!seen_sp_adjust) | |
cb1d2653 | 5297 | { |
6d82d43b AC |
5298 | if (high_word == 0x3c01 || /* lui $at,n */ |
5299 | high_word == 0x3c08) /* lui $t0,n */ | |
5300 | { | |
5301 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
5302 | continue; | |
5303 | } | |
5304 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
5305 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
5306 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
5307 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
5308 | { | |
5309 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
5310 | continue; | |
5311 | } | |
5312 | else | |
5313 | break; | |
cb1d2653 | 5314 | } |
6d82d43b AC |
5315 | else |
5316 | break; | |
46cac009 | 5317 | } |
6d82d43b AC |
5318 | |
5319 | /* In a frameless function, we might have incorrectly | |
5320 | skipped some load immediate instructions. Undo the skipping | |
5321 | if the load immediate was not followed by a stack adjustment. */ | |
5322 | if (load_immediate_bytes && !seen_sp_adjust) | |
5323 | pc -= load_immediate_bytes; | |
5324 | return pc; | |
46cac009 AC |
5325 | } |
5326 | ||
6d82d43b AC |
5327 | /* Skip the PC past function prologue instructions (16-bit version). |
5328 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 5329 | |
6d82d43b AC |
5330 | static CORE_ADDR |
5331 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 5332 | { |
6d82d43b AC |
5333 | CORE_ADDR end_pc; |
5334 | int extend_bytes = 0; | |
5335 | int prev_extend_bytes; | |
5336 | ||
5337 | /* Table of instructions likely to be found in a function prologue. */ | |
5338 | static struct | |
5339 | { | |
5340 | unsigned short inst; | |
5341 | unsigned short mask; | |
5342 | } | |
5343 | table[] = | |
5344 | { | |
7a292a7a | 5345 | { |
6d82d43b AC |
5346 | 0x6300, 0xff00} |
5347 | , /* addiu $sp,offset */ | |
88658117 | 5348 | { |
6d82d43b AC |
5349 | 0xfb00, 0xff00} |
5350 | , /* daddiu $sp,offset */ | |
88658117 | 5351 | { |
6d82d43b AC |
5352 | 0xd000, 0xf800} |
5353 | , /* sw reg,n($sp) */ | |
5354 | { | |
5355 | 0xf900, 0xff00} | |
5356 | , /* sd reg,n($sp) */ | |
5357 | { | |
5358 | 0x6200, 0xff00} | |
5359 | , /* sw $ra,n($sp) */ | |
5360 | { | |
5361 | 0xfa00, 0xff00} | |
5362 | , /* sd $ra,n($sp) */ | |
5363 | { | |
5364 | 0x673d, 0xffff} | |
5365 | , /* move $s1,sp */ | |
5366 | { | |
5367 | 0xd980, 0xff80} | |
5368 | , /* sw $a0-$a3,n($s1) */ | |
5369 | { | |
5370 | 0x6704, 0xff1c} | |
5371 | , /* move reg,$a0-$a3 */ | |
5372 | { | |
5373 | 0xe809, 0xf81f} | |
5374 | , /* entry pseudo-op */ | |
5375 | { | |
5376 | 0x0100, 0xff00} | |
5377 | , /* addiu $s1,$sp,n */ | |
5378 | { | |
5379 | 0, 0} /* end of table marker */ | |
5380 | }; | |
5381 | ||
5382 | /* Find an upper bound on the prologue. */ | |
5383 | end_pc = skip_prologue_using_sal (pc); | |
5384 | if (end_pc == 0) | |
5385 | end_pc = pc + 100; /* Magic. */ | |
5386 | ||
5387 | /* Skip the typical prologue instructions. These are the stack adjustment | |
5388 | instruction and the instructions that save registers on the stack | |
5389 | or in the gcc frame. */ | |
5390 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
5391 | { | |
5392 | unsigned short inst; | |
5393 | int i; | |
5394 | ||
5395 | inst = mips_fetch_instruction (pc); | |
5396 | ||
5397 | /* Normally we ignore an extend instruction. However, if it is | |
5398 | not followed by a valid prologue instruction, we must adjust | |
5399 | the pc back over the extend so that it won't be considered | |
5400 | part of the prologue. */ | |
5401 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 5402 | { |
6d82d43b AC |
5403 | extend_bytes = MIPS16_INSTLEN; |
5404 | continue; | |
88658117 | 5405 | } |
6d82d43b AC |
5406 | prev_extend_bytes = extend_bytes; |
5407 | extend_bytes = 0; | |
5408 | ||
5409 | /* Check for other valid prologue instructions besides extend. */ | |
5410 | for (i = 0; table[i].mask != 0; i++) | |
5411 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
5412 | break; | |
5413 | if (table[i].mask != 0) /* it was in table? */ | |
5414 | continue; /* ignore it */ | |
5415 | else | |
5416 | /* non-prologue */ | |
88658117 | 5417 | { |
6d82d43b AC |
5418 | /* Return the current pc, adjusted backwards by 2 if |
5419 | the previous instruction was an extend. */ | |
5420 | return pc - prev_extend_bytes; | |
88658117 AC |
5421 | } |
5422 | } | |
6d82d43b AC |
5423 | return pc; |
5424 | } | |
5425 | ||
5426 | /* To skip prologues, I use this predicate. Returns either PC itself | |
5427 | if the code at PC does not look like a function prologue; otherwise | |
5428 | returns an address that (if we're lucky) follows the prologue. If | |
5429 | LENIENT, then we must skip everything which is involved in setting | |
5430 | up the frame (it's OK to skip more, just so long as we don't skip | |
5431 | anything which might clobber the registers which are being saved. | |
5432 | We must skip more in the case where part of the prologue is in the | |
5433 | delay slot of a non-prologue instruction). */ | |
5434 | ||
5435 | static CORE_ADDR | |
5436 | mips_skip_prologue (CORE_ADDR pc) | |
5437 | { | |
5438 | /* See if we can determine the end of the prologue via the symbol table. | |
5439 | If so, then return either PC, or the PC after the prologue, whichever | |
5440 | is greater. */ | |
5441 | ||
5442 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
5443 | ||
5444 | if (post_prologue_pc != 0) | |
5445 | return max (pc, post_prologue_pc); | |
5446 | ||
5447 | /* Can't determine prologue from the symbol table, need to examine | |
5448 | instructions. */ | |
5449 | ||
5450 | if (pc_is_mips16 (pc)) | |
5451 | return mips16_skip_prologue (pc); | |
5452 | else | |
5453 | return mips32_skip_prologue (pc); | |
88658117 AC |
5454 | } |
5455 | ||
a5ea2558 AC |
5456 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5457 | used for all MIPS-specific commands. */ | |
5458 | ||
a5ea2558 | 5459 | static void |
acdb74a0 | 5460 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5461 | { |
5462 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5463 | } | |
5464 | ||
a5ea2558 | 5465 | static void |
acdb74a0 | 5466 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5467 | { |
6d82d43b AC |
5468 | printf_unfiltered |
5469 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5470 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5471 | } | |
5472 | ||
c906108c SS |
5473 | /* Commands to show/set the MIPS FPU type. */ |
5474 | ||
c906108c | 5475 | static void |
acdb74a0 | 5476 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5477 | { |
c906108c SS |
5478 | char *fpu; |
5479 | switch (MIPS_FPU_TYPE) | |
5480 | { | |
5481 | case MIPS_FPU_SINGLE: | |
5482 | fpu = "single-precision"; | |
5483 | break; | |
5484 | case MIPS_FPU_DOUBLE: | |
5485 | fpu = "double-precision"; | |
5486 | break; | |
5487 | case MIPS_FPU_NONE: | |
5488 | fpu = "absent (none)"; | |
5489 | break; | |
93d56215 AC |
5490 | default: |
5491 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5492 | } |
5493 | if (mips_fpu_type_auto) | |
6d82d43b AC |
5494 | printf_unfiltered |
5495 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5496 | fpu); | |
c906108c | 5497 | else |
6d82d43b AC |
5498 | printf_unfiltered |
5499 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5500 | } |
5501 | ||
5502 | ||
c906108c | 5503 | static void |
acdb74a0 | 5504 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5505 | { |
6d82d43b AC |
5506 | printf_unfiltered |
5507 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5508 | show_mipsfpu_command (args, from_tty); |
5509 | } | |
5510 | ||
c906108c | 5511 | static void |
acdb74a0 | 5512 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5513 | { |
8d5838b5 AC |
5514 | struct gdbarch_info info; |
5515 | gdbarch_info_init (&info); | |
c906108c SS |
5516 | mips_fpu_type = MIPS_FPU_SINGLE; |
5517 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5518 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5519 | instead of relying on globals. Doing that would let generic code | |
5520 | handle the search for this specific architecture. */ | |
5521 | if (!gdbarch_update_p (info)) | |
5522 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5523 | } |
5524 | ||
c906108c | 5525 | static void |
acdb74a0 | 5526 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5527 | { |
8d5838b5 AC |
5528 | struct gdbarch_info info; |
5529 | gdbarch_info_init (&info); | |
c906108c SS |
5530 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5531 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5532 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5533 | instead of relying on globals. Doing that would let generic code | |
5534 | handle the search for this specific architecture. */ | |
5535 | if (!gdbarch_update_p (info)) | |
5536 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5537 | } |
5538 | ||
c906108c | 5539 | static void |
acdb74a0 | 5540 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5541 | { |
8d5838b5 AC |
5542 | struct gdbarch_info info; |
5543 | gdbarch_info_init (&info); | |
c906108c SS |
5544 | mips_fpu_type = MIPS_FPU_NONE; |
5545 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5546 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5547 | instead of relying on globals. Doing that would let generic code | |
5548 | handle the search for this specific architecture. */ | |
5549 | if (!gdbarch_update_p (info)) | |
5550 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5551 | } |
5552 | ||
c906108c | 5553 | static void |
acdb74a0 | 5554 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5555 | { |
5556 | mips_fpu_type_auto = 1; | |
5557 | } | |
5558 | ||
c906108c | 5559 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5560 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5561 | the relevant processor still exists (it dates back to '94) and | |
5562 | secondly this is not the way to do this. The processor type should | |
5563 | be set by forcing an architecture change. */ | |
c906108c | 5564 | |
691c0433 AC |
5565 | void |
5566 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5567 | { |
691c0433 | 5568 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5569 | CORE_ADDR prid; |
5570 | ||
5571 | prid = read_register (PRID_REGNUM); | |
5572 | ||
5573 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5574 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5575 | } |
5576 | ||
5577 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5578 | callable as an sfunc. */ | |
5579 | ||
5580 | static void | |
acdb74a0 AC |
5581 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5582 | struct cmd_list_element *c) | |
c906108c SS |
5583 | { |
5584 | reinit_frame_cache (); | |
5585 | } | |
5586 | ||
a89aa300 AC |
5587 | static int |
5588 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5589 | { |
e5ab0dce | 5590 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5591 | mips_extra_func_info_t proc_desc; |
5592 | ||
5593 | /* Search for the function containing this address. Set the low bit | |
5594 | of the address when searching, in case we were given an even address | |
5595 | that is the start of a 16-bit function. If we didn't do this, | |
5596 | the search would fail because the symbol table says the function | |
5597 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5598 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5599 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5600 | |
5601 | /* Make an attempt to determine if this is a 16-bit function. If | |
5602 | the procedure descriptor exists and the address therein is odd, | |
5603 | it's definitely a 16-bit function. Otherwise, we have to just | |
5604 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5605 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5606 | disassembler needs to be able to locally determine the ISA, and | |
5607 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5608 | work. */ | |
c906108c | 5609 | if (proc_desc) |
d31431ed AC |
5610 | { |
5611 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 5612 | info->mach = bfd_mach_mips16; |
d31431ed | 5613 | } |
c906108c | 5614 | else |
d31431ed AC |
5615 | { |
5616 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5617 | info->mach = bfd_mach_mips16; |
5618 | } | |
c906108c SS |
5619 | |
5620 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5621 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5622 | |
e5ab0dce | 5623 | /* Set the disassembler options. */ |
6d82d43b | 5624 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5625 | { |
5626 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5627 | register names from libopcodes. */ |
e5ab0dce AC |
5628 | if (tdep->mips_abi == MIPS_ABI_N32) |
5629 | info->disassembler_options = "gpr-names=n32"; | |
5630 | else | |
5631 | info->disassembler_options = "gpr-names=64"; | |
5632 | info->flavour = bfd_target_elf_flavour; | |
5633 | } | |
5634 | else | |
5635 | /* This string is not recognized explicitly by the disassembler, | |
5636 | but it tells the disassembler to not try to guess the ABI from | |
5637 | the bfd elf headers, such that, if the user overrides the ABI | |
5638 | of a program linked as NewABI, the disassembly will follow the | |
5639 | register naming conventions specified by the user. */ | |
5640 | info->disassembler_options = "gpr-names=32"; | |
5641 | ||
c906108c | 5642 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5643 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5644 | return print_insn_big_mips (memaddr, info); |
5645 | else | |
5646 | return print_insn_little_mips (memaddr, info); | |
5647 | } | |
5648 | ||
c906108c SS |
5649 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5650 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5651 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5652 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5653 | (if necessary) to point to the actual memory location where the | |
5654 | breakpoint should be inserted. */ | |
5655 | ||
f7ab6ec6 | 5656 | static const unsigned char * |
6d82d43b | 5657 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5658 | { |
d7449b42 | 5659 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5660 | { |
5661 | if (pc_is_mips16 (*pcptr)) | |
5662 | { | |
6d82d43b | 5663 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5664 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5665 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5666 | return mips16_big_breakpoint; |
5667 | } | |
5668 | else | |
5669 | { | |
aaab4dba AC |
5670 | /* The IDT board uses an unusual breakpoint value, and |
5671 | sometimes gets confused when it sees the usual MIPS | |
5672 | breakpoint instruction. */ | |
6d82d43b AC |
5673 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5674 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5675 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5676 | |
c5aa993b | 5677 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5678 | |
5679 | if (strcmp (target_shortname, "mips") == 0) | |
5680 | return idt_big_breakpoint; | |
5681 | else if (strcmp (target_shortname, "ddb") == 0 | |
5682 | || strcmp (target_shortname, "pmon") == 0 | |
5683 | || strcmp (target_shortname, "lsi") == 0) | |
5684 | return pmon_big_breakpoint; | |
5685 | else | |
5686 | return big_breakpoint; | |
5687 | } | |
5688 | } | |
5689 | else | |
5690 | { | |
5691 | if (pc_is_mips16 (*pcptr)) | |
5692 | { | |
6d82d43b | 5693 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5694 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5695 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5696 | return mips16_little_breakpoint; |
5697 | } | |
5698 | else | |
5699 | { | |
6d82d43b AC |
5700 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5701 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5702 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5703 | |
c5aa993b | 5704 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5705 | |
5706 | if (strcmp (target_shortname, "mips") == 0) | |
5707 | return idt_little_breakpoint; | |
5708 | else if (strcmp (target_shortname, "ddb") == 0 | |
5709 | || strcmp (target_shortname, "pmon") == 0 | |
5710 | || strcmp (target_shortname, "lsi") == 0) | |
5711 | return pmon_little_breakpoint; | |
5712 | else | |
5713 | return little_breakpoint; | |
5714 | } | |
5715 | } | |
5716 | } | |
5717 | ||
5718 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5719 | PC, which is either the callee or the caller. There are several | |
5720 | cases which must be handled: | |
5721 | ||
5722 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5723 | target PC is in $31 ($ra). |
c906108c | 5724 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5725 | and the target PC is in $2. |
c906108c | 5726 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5727 | before the jal instruction, this is effectively a call stub |
5728 | and the the target PC is in $2. Otherwise this is effectively | |
5729 | a return stub and the target PC is in $18. | |
c906108c SS |
5730 | |
5731 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5732 | gory details. | |
5733 | ||
5734 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5735 | */ |
c906108c | 5736 | |
757a7cc6 | 5737 | static CORE_ADDR |
acdb74a0 | 5738 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5739 | { |
5740 | char *name; | |
5741 | CORE_ADDR start_addr; | |
5742 | ||
5743 | /* Find the starting address and name of the function containing the PC. */ | |
5744 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5745 | return 0; | |
5746 | ||
5747 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5748 | target PC is in $31 ($ra). */ | |
5749 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5750 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5751 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5752 | |
5753 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5754 | { | |
5755 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5756 | and the target PC is in $2. */ | |
5757 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5758 | return read_signed_register (2); |
c906108c SS |
5759 | |
5760 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5761 | before the jal instruction, this is effectively a call stub |
5762 | and the the target PC is in $2. Otherwise this is effectively | |
5763 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5764 | else if (name[19] == 's' || name[19] == 'd') |
5765 | { | |
5766 | if (pc == start_addr) | |
5767 | { | |
5768 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5769 | stub. Such a stub for a function bar might have a name |
5770 | like __fn_stub_bar, and might look like this: | |
5771 | mfc1 $4,$f13 | |
5772 | mfc1 $5,$f12 | |
5773 | mfc1 $6,$f15 | |
5774 | mfc1 $7,$f14 | |
5775 | la $1,bar (becomes a lui/addiu pair) | |
5776 | jr $1 | |
5777 | So scan down to the lui/addi and extract the target | |
5778 | address from those two instructions. */ | |
c906108c | 5779 | |
6c997a34 | 5780 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5781 | t_inst inst; |
5782 | int i; | |
5783 | ||
5784 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5785 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5786 | 0) | |
c906108c SS |
5787 | return target_pc; |
5788 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5789 | && strcmp (name, "etext") != 0 | |
5790 | && strcmp (name, "_etext") != 0) | |
5791 | return target_pc; | |
5792 | ||
5793 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5794 | The limit on the search is arbitrarily set to 20 |
5795 | instructions. FIXME. */ | |
c906108c SS |
5796 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5797 | { | |
c5aa993b JM |
5798 | inst = mips_fetch_instruction (target_pc); |
5799 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5800 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5801 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5802 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5803 | } |
5804 | ||
5805 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5806 | return target_pc; | |
5807 | } | |
5808 | else | |
5809 | /* This is the 'return' part of a call stub. The return | |
5810 | address is in $r18. */ | |
6c997a34 | 5811 | return read_signed_register (18); |
c906108c SS |
5812 | } |
5813 | } | |
c5aa993b | 5814 | return 0; /* not a stub */ |
c906108c SS |
5815 | } |
5816 | ||
5817 | ||
5818 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5819 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5820 | ||
757a7cc6 | 5821 | static int |
acdb74a0 | 5822 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5823 | { |
5824 | CORE_ADDR start_addr; | |
5825 | ||
5826 | /* Find the starting address of the function containing the PC. If the | |
5827 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5828 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5829 | 0) | |
c906108c SS |
5830 | return 0; |
5831 | ||
5832 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5833 | { | |
5834 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5835 | if (name[19] >= '0' && name[19] <= '9') | |
5836 | return 1; | |
5837 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5838 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5839 | else if (name[19] == 's' || name[19] == 'd') |
5840 | return pc == start_addr; | |
5841 | } | |
5842 | ||
c5aa993b | 5843 | return 0; /* not a stub */ |
c906108c SS |
5844 | } |
5845 | ||
5846 | ||
5847 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5848 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5849 | ||
e41b17f0 | 5850 | static int |
acdb74a0 | 5851 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5852 | { |
5853 | CORE_ADDR start_addr; | |
5854 | ||
5855 | /* Find the starting address of the function containing the PC. */ | |
5856 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5857 | return 0; | |
5858 | ||
5859 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5860 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5861 | || strcmp (name, "__mips16_ret_df") == 0) | |
5862 | return 1; | |
5863 | ||
5864 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5865 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5866 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5867 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5868 | return 1; |
5869 | ||
c5aa993b | 5870 | return 0; /* not a stub */ |
c906108c SS |
5871 | } |
5872 | ||
5873 | ||
a53c66de AC |
5874 | /* Return non-zero if the PC is in a library helper function that |
5875 | should be ignored. This implements the | |
5876 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
5877 | |
5878 | int | |
acdb74a0 | 5879 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5880 | { |
5881 | char *name; | |
5882 | ||
5883 | /* Find the starting address and name of the function containing the PC. */ | |
5884 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5885 | return 0; | |
5886 | ||
5887 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5888 | that we want to ignore. */ | |
5889 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5890 | || strcmp (name, "__mips16_ret_df") == 0); | |
5891 | } | |
5892 | ||
5893 | ||
a4b8ebc8 AC |
5894 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5895 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5896 | |
5897 | static int | |
5898 | mips_stab_reg_to_regnum (int num) | |
5899 | { | |
a4b8ebc8 | 5900 | int regnum; |
2f38ef89 | 5901 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5902 | regnum = num; |
2f38ef89 | 5903 | else if (num >= 38 && num < 70) |
56cea623 | 5904 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5905 | else if (num == 70) |
56cea623 | 5906 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5907 | else if (num == 71) |
56cea623 | 5908 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5909 | else |
a4b8ebc8 AC |
5910 | /* This will hopefully (eventually) provoke a warning. Should |
5911 | we be calling complaint() here? */ | |
5912 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5913 | return NUM_REGS + regnum; | |
88c72b7d AC |
5914 | } |
5915 | ||
2f38ef89 | 5916 | |
a4b8ebc8 AC |
5917 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5918 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5919 | |
5920 | static int | |
2f38ef89 | 5921 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5922 | { |
a4b8ebc8 | 5923 | int regnum; |
2f38ef89 | 5924 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5925 | regnum = num; |
2f38ef89 | 5926 | else if (num >= 32 && num < 64) |
56cea623 | 5927 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5928 | else if (num == 64) |
56cea623 | 5929 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5930 | else if (num == 65) |
56cea623 | 5931 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5932 | else |
a4b8ebc8 AC |
5933 | /* This will hopefully (eventually) provoke a warning. Should we |
5934 | be calling complaint() here? */ | |
5935 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5936 | return NUM_REGS + regnum; | |
5937 | } | |
5938 | ||
5939 | static int | |
5940 | mips_register_sim_regno (int regnum) | |
5941 | { | |
5942 | /* Only makes sense to supply raw registers. */ | |
5943 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5944 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5945 | decide if it is valid. Should instead define a standard sim/gdb | |
5946 | register numbering scheme. */ | |
5947 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5948 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5949 | return regnum; | |
5950 | else | |
6d82d43b | 5951 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5952 | } |
5953 | ||
2f38ef89 | 5954 | |
fc0c74b1 AC |
5955 | /* Convert an integer into an address. By first converting the value |
5956 | into a pointer and then extracting it signed, the address is | |
5957 | guarenteed to be correctly sign extended. */ | |
5958 | ||
5959 | static CORE_ADDR | |
5960 | mips_integer_to_address (struct type *type, void *buf) | |
5961 | { | |
5962 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5963 | LONGEST val = unpack_long (type, buf); | |
5964 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5965 | return extract_signed_integer (tmp, | |
5966 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5967 | } | |
5968 | ||
caaa3122 DJ |
5969 | static void |
5970 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5971 | { | |
5972 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5973 | const char *name = bfd_get_section_name (abfd, sect); | |
5974 | ||
5975 | if (*abip != MIPS_ABI_UNKNOWN) | |
5976 | return; | |
5977 | ||
5978 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5979 | return; | |
5980 | ||
5981 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5982 | *abip = MIPS_ABI_O32; | |
5983 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5984 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5985 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5986 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5987 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5988 | *abip = MIPS_ABI_O64; | |
5989 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5990 | *abip = MIPS_ABI_EABI32; | |
5991 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5992 | *abip = MIPS_ABI_EABI64; | |
5993 | else | |
5994 | warning ("unsupported ABI %s.", name + 8); | |
5995 | } | |
5996 | ||
2e4ebe70 DJ |
5997 | static enum mips_abi |
5998 | global_mips_abi (void) | |
5999 | { | |
6000 | int i; | |
6001 | ||
6002 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
6003 | if (mips_abi_strings[i] == mips_abi_string) | |
6004 | return (enum mips_abi) i; | |
6005 | ||
6d82d43b | 6006 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
6007 | } |
6008 | ||
c2d11a7d | 6009 | static struct gdbarch * |
6d82d43b | 6010 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 6011 | { |
c2d11a7d JM |
6012 | struct gdbarch *gdbarch; |
6013 | struct gdbarch_tdep *tdep; | |
6014 | int elf_flags; | |
2e4ebe70 | 6015 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 6016 | int num_regs; |
8d5838b5 | 6017 | enum mips_fpu_type fpu_type; |
c2d11a7d | 6018 | |
ec03c1ac AC |
6019 | /* First of all, extract the elf_flags, if available. */ |
6020 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6021 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
6022 | else if (arches != NULL) |
6023 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
6024 | else |
6025 | elf_flags = 0; | |
6026 | if (gdbarch_debug) | |
6027 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6028 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 6029 | |
102182a9 | 6030 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
6031 | switch ((elf_flags & EF_MIPS_ABI)) |
6032 | { | |
6033 | case E_MIPS_ABI_O32: | |
ec03c1ac | 6034 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
6035 | break; |
6036 | case E_MIPS_ABI_O64: | |
ec03c1ac | 6037 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
6038 | break; |
6039 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 6040 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
6041 | break; |
6042 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 6043 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
6044 | break; |
6045 | default: | |
acdb74a0 | 6046 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 6047 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 6048 | else |
ec03c1ac | 6049 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
6050 | break; |
6051 | } | |
acdb74a0 | 6052 | |
caaa3122 | 6053 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
6054 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
6055 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 6056 | |
dc305454 | 6057 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
6058 | MIPS architecture (if there is one). */ |
6059 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
6060 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 6061 | |
32a6503c | 6062 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 6063 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
6064 | && info.bfd_arch_info != NULL |
6065 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6066 | { | |
6067 | switch (info.bfd_arch_info->mach) | |
6068 | { | |
6069 | case bfd_mach_mips3900: | |
ec03c1ac | 6070 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
6071 | break; |
6072 | case bfd_mach_mips4100: | |
6073 | case bfd_mach_mips5000: | |
ec03c1ac | 6074 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 6075 | break; |
1d06468c EZ |
6076 | case bfd_mach_mips8000: |
6077 | case bfd_mach_mips10000: | |
32a6503c KB |
6078 | /* On Irix, ELF64 executables use the N64 ABI. The |
6079 | pseudo-sections which describe the ABI aren't present | |
6080 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
6081 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
6082 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 6083 | found_abi = MIPS_ABI_N64; |
28d169de | 6084 | else |
ec03c1ac | 6085 | found_abi = MIPS_ABI_N32; |
1d06468c | 6086 | break; |
bf64bfd6 AC |
6087 | } |
6088 | } | |
2e4ebe70 | 6089 | |
ec03c1ac AC |
6090 | if (gdbarch_debug) |
6091 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
6092 | found_abi); | |
6093 | ||
6094 | /* What has the user specified from the command line? */ | |
6095 | wanted_abi = global_mips_abi (); | |
6096 | if (gdbarch_debug) | |
6097 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
6098 | wanted_abi); | |
2e4ebe70 DJ |
6099 | |
6100 | /* Now that we have found what the ABI for this binary would be, | |
6101 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
6102 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
6103 | mips_abi = wanted_abi; | |
ec03c1ac AC |
6104 | else if (found_abi != MIPS_ABI_UNKNOWN) |
6105 | mips_abi = found_abi; | |
6106 | else | |
6107 | mips_abi = MIPS_ABI_O32; | |
6108 | if (gdbarch_debug) | |
6109 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
6110 | mips_abi); | |
2e4ebe70 | 6111 | |
ec03c1ac | 6112 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 6113 | if (gdbarch_debug) |
ec03c1ac AC |
6114 | fprintf_unfiltered (gdb_stdlog, |
6115 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
6116 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 6117 | |
8d5838b5 AC |
6118 | /* Determine the MIPS FPU type. */ |
6119 | if (!mips_fpu_type_auto) | |
6120 | fpu_type = mips_fpu_type; | |
6121 | else if (info.bfd_arch_info != NULL | |
6122 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6123 | switch (info.bfd_arch_info->mach) | |
6124 | { | |
6125 | case bfd_mach_mips3900: | |
6126 | case bfd_mach_mips4100: | |
6127 | case bfd_mach_mips4111: | |
a9d61c86 | 6128 | case bfd_mach_mips4120: |
8d5838b5 AC |
6129 | fpu_type = MIPS_FPU_NONE; |
6130 | break; | |
6131 | case bfd_mach_mips4650: | |
6132 | fpu_type = MIPS_FPU_SINGLE; | |
6133 | break; | |
6134 | default: | |
6135 | fpu_type = MIPS_FPU_DOUBLE; | |
6136 | break; | |
6137 | } | |
6138 | else if (arches != NULL) | |
6139 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
6140 | else | |
6141 | fpu_type = MIPS_FPU_DOUBLE; | |
6142 | if (gdbarch_debug) | |
6143 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6144 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 6145 | |
c2d11a7d JM |
6146 | /* try to find a pre-existing architecture */ |
6147 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
6148 | arches != NULL; | |
6149 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6150 | { | |
6151 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 6152 | using. */ |
9103eae0 | 6153 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 6154 | continue; |
9103eae0 | 6155 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 6156 | continue; |
719ec221 AC |
6157 | /* Need to be pedantic about which register virtual size is |
6158 | used. */ | |
6159 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
6160 | != mips64_transfers_32bit_regs_p) | |
6161 | continue; | |
8d5838b5 AC |
6162 | /* Be pedantic about which FPU is selected. */ |
6163 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
6164 | continue; | |
4be87837 | 6165 | return arches->gdbarch; |
c2d11a7d JM |
6166 | } |
6167 | ||
102182a9 | 6168 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
6169 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
6170 | gdbarch = gdbarch_alloc (&info, tdep); | |
6171 | tdep->elf_flags = elf_flags; | |
719ec221 | 6172 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
6173 | tdep->found_abi = found_abi; |
6174 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 6175 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 6176 | |
102182a9 | 6177 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6178 | set_gdbarch_short_bit (gdbarch, 16); |
6179 | set_gdbarch_int_bit (gdbarch, 32); | |
6180 | set_gdbarch_float_bit (gdbarch, 32); | |
6181 | set_gdbarch_double_bit (gdbarch, 64); | |
6182 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6183 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6184 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6185 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6186 | |
6d82d43b | 6187 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6188 | mips_elf_make_msymbol_special); |
6189 | ||
16e109ca | 6190 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 6191 | { |
16e109ca | 6192 | const char **reg_names; |
56cea623 AC |
6193 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
6194 | struct mips_regnum); | |
56cea623 AC |
6195 | if (info.osabi == GDB_OSABI_IRIX) |
6196 | { | |
6197 | regnum->fp0 = 32; | |
6198 | regnum->pc = 64; | |
6199 | regnum->cause = 65; | |
6200 | regnum->badvaddr = 66; | |
6201 | regnum->hi = 67; | |
6202 | regnum->lo = 68; | |
6203 | regnum->fp_control_status = 69; | |
6204 | regnum->fp_implementation_revision = 70; | |
6205 | num_regs = 71; | |
16e109ca | 6206 | reg_names = mips_irix_reg_names; |
56cea623 AC |
6207 | } |
6208 | else | |
6209 | { | |
6210 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6211 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6212 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6213 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6214 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6215 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6216 | regnum->fp_control_status = 70; | |
6217 | regnum->fp_implementation_revision = 71; | |
6218 | num_regs = 90; | |
16e109ca AC |
6219 | if (info.bfd_arch_info != NULL |
6220 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6221 | reg_names = mips_tx39_reg_names; | |
6222 | else | |
6223 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
6224 | } |
6225 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
6226 | replaced by read_pc? */ | |
f10683bb MH |
6227 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
6228 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
6229 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6230 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6231 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
6232 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6233 | tdep->mips_processor_reg_names = reg_names; | |
6234 | tdep->regnum = regnum; | |
56cea623 | 6235 | } |
fe29b929 | 6236 | |
0dadbba0 | 6237 | switch (mips_abi) |
c2d11a7d | 6238 | { |
0dadbba0 | 6239 | case MIPS_ABI_O32: |
25ab4790 | 6240 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6241 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
acdb74a0 | 6242 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 6243 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6244 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6245 | set_gdbarch_long_bit (gdbarch, 32); |
6246 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6247 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6248 | break; | |
0dadbba0 | 6249 | case MIPS_ABI_O64: |
25ab4790 | 6250 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
6251 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6252 | mips_o64_store_return_value); | |
6253 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6254 | mips_o64_extract_return_value); | |
acdb74a0 | 6255 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 6256 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6257 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6258 | set_gdbarch_long_bit (gdbarch, 32); |
6259 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6260 | set_gdbarch_long_long_bit (gdbarch, 64); | |
b5622e8d | 6261 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 6262 | break; |
0dadbba0 | 6263 | case MIPS_ABI_EABI32: |
25ab4790 | 6264 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
6265 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6266 | mips_eabi_store_return_value); | |
6267 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6268 | mips_eabi_extract_return_value); | |
acdb74a0 | 6269 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6270 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6271 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6272 | set_gdbarch_long_bit (gdbarch, 32); |
6273 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6274 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
6275 | set_gdbarch_deprecated_reg_struct_has_addr |
6276 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 6277 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 6278 | break; |
0dadbba0 | 6279 | case MIPS_ABI_EABI64: |
25ab4790 | 6280 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
6281 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6282 | mips_eabi_store_return_value); | |
6283 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6284 | mips_eabi_extract_return_value); | |
acdb74a0 | 6285 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6286 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6287 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6288 | set_gdbarch_long_bit (gdbarch, 64); |
6289 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6290 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
6291 | set_gdbarch_deprecated_reg_struct_has_addr |
6292 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 6293 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 6294 | break; |
0dadbba0 | 6295 | case MIPS_ABI_N32: |
25ab4790 | 6296 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6297 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
acdb74a0 | 6298 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6299 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6300 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6301 | set_gdbarch_long_bit (gdbarch, 32); |
6302 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6303 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
6304 | set_gdbarch_long_double_bit (gdbarch, 128); |
6305 | set_gdbarch_long_double_format (gdbarch, | |
6306 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
6307 | break; |
6308 | case MIPS_ABI_N64: | |
25ab4790 | 6309 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6310 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de | 6311 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6312 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6313 | tdep->default_mask_address_p = 0; |
6314 | set_gdbarch_long_bit (gdbarch, 64); | |
6315 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6316 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
6317 | set_gdbarch_long_double_bit (gdbarch, 128); |
6318 | set_gdbarch_long_double_format (gdbarch, | |
6319 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 6320 | break; |
c2d11a7d | 6321 | default: |
6d82d43b | 6322 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
6323 | } |
6324 | ||
a5ea2558 AC |
6325 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6326 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6327 | comment: | |
6328 | ||
6329 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6330 | flag in object files because to do so would make it impossible to | |
102182a9 | 6331 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6332 | unnecessarily restrictive. |
361d1df0 | 6333 | |
a5ea2558 AC |
6334 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6335 | but to set this flag before gcc is built with such multilibs will | |
6336 | break too many systems.'' | |
6337 | ||
6338 | But even more unhelpfully, the default linker output target for | |
6339 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6340 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6341 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6342 | this flag to detect 32-bit mode would do the wrong thing given |
6343 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6344 | as 32-bit programs by default. */ |
a5ea2558 | 6345 | |
6c997a34 | 6346 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6347 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 6348 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6349 | |
102182a9 MS |
6350 | /* Add/remove bits from an address. The MIPS needs be careful to |
6351 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6352 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6353 | ||
58dfe9ff AC |
6354 | /* Unwind the frame. */ |
6355 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 6356 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 6357 | |
102182a9 | 6358 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6359 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6360 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6361 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6362 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
6363 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6364 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
6365 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6366 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6367 | |
c2d11a7d JM |
6368 | /* MIPS version of CALL_DUMMY */ |
6369 | ||
9710e734 AC |
6370 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6371 | replaced by a command, and all targets will default to on stack | |
6372 | (regardless of the stack's execute status). */ | |
6373 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6374 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6375 | |
87783b8b AC |
6376 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6377 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6378 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6379 | ||
f7b9e9fc AC |
6380 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6381 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6382 | |
6383 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6384 | |
fc0c74b1 AC |
6385 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6386 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6387 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6388 | |
a4b8ebc8 | 6389 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6390 | |
e11c53d2 | 6391 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6392 | |
e5ab0dce AC |
6393 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6394 | ||
3a3bc038 AC |
6395 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6396 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6397 | need to all be folded into the target vector. Since they are | |
6398 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6399 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6400 | is sitting on? */ | |
6401 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6402 | ||
757a7cc6 MS |
6403 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
6404 | ||
6de918a6 DJ |
6405 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
6406 | to support MIPS16. This is a bad thing. Make sure not to do it | |
6407 | if we have an OS ABI that actually supports shared libraries, since | |
6408 | shared library support is more important. If we have an OS someday | |
6409 | that supports both shared libraries and MIPS16, we'll have to find | |
6410 | a better place for these. */ | |
6411 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
6412 | { | |
6413 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
6414 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
6415 | } | |
6416 | ||
6417 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
6418 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 6419 | |
5792a79b | 6420 | /* Unwind the frame. */ |
eec63939 | 6421 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
5792a79b | 6422 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
45c9dd44 AC |
6423 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
6424 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 6425 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
5792a79b | 6426 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); |
45c9dd44 AC |
6427 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6428 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6429 | |
4b9b3959 AC |
6430 | return gdbarch; |
6431 | } | |
6432 | ||
2e4ebe70 | 6433 | static void |
6d82d43b | 6434 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6435 | { |
6436 | struct gdbarch_info info; | |
6437 | ||
6438 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6439 | mips_gdbarch_init will take care of the rest. */ | |
6440 | gdbarch_info_init (&info); | |
6441 | gdbarch_update_p (info); | |
6442 | } | |
6443 | ||
ad188201 KB |
6444 | /* Print out which MIPS ABI is in use. */ |
6445 | ||
6446 | static void | |
6447 | show_mips_abi (char *ignore_args, int from_tty) | |
6448 | { | |
6449 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
6450 | printf_filtered |
6451 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
6452 | else |
6453 | { | |
6454 | enum mips_abi global_abi = global_mips_abi (); | |
6455 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6456 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6457 | ||
6458 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
6459 | printf_filtered |
6460 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6461 | actual_abi_str); | |
ad188201 | 6462 | else if (global_abi == actual_abi) |
6d82d43b AC |
6463 | printf_filtered |
6464 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6465 | actual_abi_str); | |
ad188201 KB |
6466 | else |
6467 | { | |
6468 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
6469 | printf_filtered |
6470 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6471 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
6472 | } |
6473 | } | |
6474 | } | |
6475 | ||
4b9b3959 AC |
6476 | static void |
6477 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6478 | { | |
6479 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6480 | if (tdep != NULL) | |
c2d11a7d | 6481 | { |
acdb74a0 AC |
6482 | int ef_mips_arch; |
6483 | int ef_mips_32bitmode; | |
6484 | /* determine the ISA */ | |
6485 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6486 | { | |
6487 | case E_MIPS_ARCH_1: | |
6488 | ef_mips_arch = 1; | |
6489 | break; | |
6490 | case E_MIPS_ARCH_2: | |
6491 | ef_mips_arch = 2; | |
6492 | break; | |
6493 | case E_MIPS_ARCH_3: | |
6494 | ef_mips_arch = 3; | |
6495 | break; | |
6496 | case E_MIPS_ARCH_4: | |
93d56215 | 6497 | ef_mips_arch = 4; |
acdb74a0 AC |
6498 | break; |
6499 | default: | |
93d56215 | 6500 | ef_mips_arch = 0; |
acdb74a0 AC |
6501 | break; |
6502 | } | |
6503 | /* determine the size of a pointer */ | |
6504 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6505 | fprintf_unfiltered (file, |
6506 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6507 | tdep->elf_flags); |
4b9b3959 | 6508 | fprintf_unfiltered (file, |
acdb74a0 AC |
6509 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6510 | ef_mips_32bitmode); | |
6511 | fprintf_unfiltered (file, | |
6512 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6513 | ef_mips_arch); | |
6514 | fprintf_unfiltered (file, | |
6515 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6516 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6517 | fprintf_unfiltered (file, |
6518 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6519 | mips_mask_address_p (tdep), |
4014092b | 6520 | tdep->default_mask_address_p); |
c2d11a7d | 6521 | } |
4b9b3959 AC |
6522 | fprintf_unfiltered (file, |
6523 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6524 | MIPS_DEFAULT_FPU_TYPE, | |
6525 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6526 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6527 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6528 | : "???")); | |
6d82d43b | 6529 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
6530 | fprintf_unfiltered (file, |
6531 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6532 | MIPS_FPU_TYPE, | |
6533 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6534 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6535 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6536 | : "???")); | |
4b9b3959 | 6537 | fprintf_unfiltered (file, |
480d3dd2 | 6538 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 6539 | mips_stack_argsize (current_gdbarch)); |
6d82d43b | 6540 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
6541 | fprintf_unfiltered (file, |
6542 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 6543 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
6544 | fprintf_unfiltered (file, |
6545 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6546 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6547 | fprintf_unfiltered (file, |
6548 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6549 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6550 | fprintf_unfiltered (file, | |
6551 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6552 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6553 | fprintf_unfiltered (file, |
6554 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6555 | FIRST_EMBED_REGNUM); | |
2475bac3 | 6556 | fprintf_unfiltered (file, |
a53c66de AC |
6557 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
6558 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6559 | fprintf_unfiltered (file, |
6560 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6561 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6562 | fprintf_unfiltered (file, | |
6563 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6564 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6565 | fprintf_unfiltered (file, |
6566 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6567 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6568 | #ifdef MACHINE_CPROC_FP_OFFSET |
6569 | fprintf_unfiltered (file, | |
6570 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6571 | MACHINE_CPROC_FP_OFFSET); | |
6572 | #endif | |
6573 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6574 | fprintf_unfiltered (file, | |
6575 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6576 | MACHINE_CPROC_PC_OFFSET); | |
6577 | #endif | |
6578 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6579 | fprintf_unfiltered (file, | |
6580 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6581 | MACHINE_CPROC_SP_OFFSET); | |
6582 | #endif | |
2475bac3 AC |
6583 | fprintf_unfiltered (file, |
6584 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6585 | MIPS16_INSTLEN); | |
6d82d43b | 6586 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
6587 | fprintf_unfiltered (file, |
6588 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6589 | fprintf_unfiltered (file, | |
6d82d43b | 6590 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 6591 | fprintf_unfiltered (file, |
acdb74a0 AC |
6592 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6593 | MIPS_LAST_ARG_REGNUM, | |
6594 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 6595 | fprintf_unfiltered (file, |
6d82d43b | 6596 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 6597 | fprintf_unfiltered (file, |
1b13c4f6 | 6598 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 6599 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 6600 | fprintf_unfiltered (file, |
6d82d43b | 6601 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
6602 | fprintf_unfiltered (file, |
6603 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6604 | fprintf_unfiltered (file, | |
6605 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6606 | fprintf_unfiltered (file, | |
6607 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
6608 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
6609 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6610 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6611 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6612 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6613 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6614 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6615 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6616 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6617 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
6618 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
6619 | #ifdef SAVED_BYTES |
6620 | fprintf_unfiltered (file, | |
6d82d43b | 6621 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
6622 | #endif |
6623 | #ifdef SAVED_FP | |
6d82d43b | 6624 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6625 | #endif |
6626 | #ifdef SAVED_PC | |
6d82d43b | 6627 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6628 | #endif |
6629 | fprintf_unfiltered (file, | |
6630 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6631 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6632 | fprintf_unfiltered (file, | |
6633 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
2475bac3 AC |
6634 | fprintf_unfiltered (file, |
6635 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6636 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6637 | fprintf_unfiltered (file, | |
6638 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6639 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6640 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6641 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6642 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6643 | fprintf_unfiltered (file, |
6644 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6645 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6646 | #ifdef STACK_END_ADDR | |
6647 | fprintf_unfiltered (file, | |
6648 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6649 | STACK_END_ADDR); | |
6650 | #endif | |
6651 | fprintf_unfiltered (file, | |
6652 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6653 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6654 | fprintf_unfiltered (file, | |
6655 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6656 | STEP_SKIPS_DELAY_P); | |
6657 | fprintf_unfiltered (file, | |
6658 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6659 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6660 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6661 | fprintf_unfiltered (file, |
6662 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6663 | fprintf_unfiltered (file, | |
6664 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6665 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6666 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6667 | fprintf_unfiltered (file, |
6668 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6669 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6670 | #ifdef TRACE_CLEAR |
6671 | fprintf_unfiltered (file, | |
6672 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6673 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6674 | #endif | |
6675 | #ifdef TRACE_FLAVOR | |
6676 | fprintf_unfiltered (file, | |
6d82d43b | 6677 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6678 | #endif |
6679 | #ifdef TRACE_FLAVOR_SIZE | |
6680 | fprintf_unfiltered (file, | |
6681 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6682 | TRACE_FLAVOR_SIZE); | |
6683 | #endif | |
6684 | #ifdef TRACE_SET | |
6685 | fprintf_unfiltered (file, | |
6686 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6687 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6688 | #endif |
2475bac3 AC |
6689 | #ifdef UNUSED_REGNUM |
6690 | fprintf_unfiltered (file, | |
6d82d43b | 6691 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6692 | #endif |
6d82d43b | 6693 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6694 | fprintf_unfiltered (file, |
6695 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6696 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6697 | fprintf_unfiltered (file, |
6d82d43b | 6698 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
2475bac3 | 6699 | fprintf_unfiltered (file, |
6d82d43b | 6700 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); |
c2d11a7d JM |
6701 | } |
6702 | ||
6d82d43b | 6703 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6704 | |
c906108c | 6705 | void |
acdb74a0 | 6706 | _initialize_mips_tdep (void) |
c906108c SS |
6707 | { |
6708 | static struct cmd_list_element *mipsfpulist = NULL; | |
6709 | struct cmd_list_element *c; | |
6710 | ||
6d82d43b | 6711 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6712 | if (MIPS_ABI_LAST + 1 |
6713 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6714 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6715 | ||
4b9b3959 | 6716 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6717 | |
8d5f9dcb DJ |
6718 | mips_pdr_data = register_objfile_data (); |
6719 | ||
a5ea2558 AC |
6720 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6721 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6722 | "Various MIPS specific commands.", | |
6723 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6724 | ||
6725 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6726 | "Various MIPS specific commands.", | |
6727 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6728 | ||
6729 | /* Allow the user to override the saved register size. */ | |
cb1a6d5f AC |
6730 | deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", |
6731 | class_obscure, | |
6732 | size_enums, | |
6733 | &mips_abi_regsize_string, "\ | |
a5ea2558 AC |
6734 | Set size of general purpose registers saved on the stack.\n\ |
6735 | This option can be set to one of:\n\ | |
6736 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6737 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6738 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6739 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6740 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6741 | |
d929b26f | 6742 | /* Allow the user to override the argument stack size. */ |
cb1a6d5f AC |
6743 | deprecated_add_show_from_set |
6744 | (add_set_enum_cmd ("stack-arg-size", | |
6745 | class_obscure, | |
6746 | size_enums, | |
6747 | &mips_stack_argsize_string, "\ | |
d929b26f AC |
6748 | Set the amount of stack space reserved for each argument.\n\ |
6749 | This option can be set to one of:\n\ | |
6750 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6751 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6752 | auto - Allow GDB to determine the correct setting from the current\n\ | |
cb1a6d5f AC |
6753 | target and executable (default)", &setmipscmdlist), |
6754 | &showmipscmdlist); | |
d929b26f | 6755 | |
2e4ebe70 DJ |
6756 | /* Allow the user to override the ABI. */ |
6757 | c = add_set_enum_cmd | |
6758 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6759 | "Set the ABI used by this program.\n" | |
6760 | "This option can be set to one of:\n" | |
6761 | " auto - the default ABI associated with the current binary\n" | |
6762 | " o32\n" | |
6d82d43b | 6763 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6764 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6765 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6766 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6767 | |
c906108c SS |
6768 | /* Let the user turn off floating point and set the fence post for |
6769 | heuristic_proc_start. */ | |
6770 | ||
6771 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6772 | "Set use of MIPS floating-point coprocessor.", | |
6773 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6774 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6775 | "Select single-precision MIPS floating-point coprocessor.", | |
6776 | &mipsfpulist); | |
6777 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6778 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6779 | &mipsfpulist); |
6780 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6781 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6782 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6783 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6784 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6785 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6786 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6787 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6788 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6789 | "Select MIPS floating-point coprocessor automatically.", | |
6790 | &mipsfpulist); | |
6791 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6792 | "Show current use of MIPS floating-point coprocessor target.", | |
6793 | &showlist); | |
6794 | ||
c906108c SS |
6795 | /* We really would like to have both "0" and "unlimited" work, but |
6796 | command.c doesn't deal with that. So make it a var_zinteger | |
6797 | because the user can always use "999999" or some such for unlimited. */ | |
6798 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6799 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6800 | Set the distance searched for the start of a function.\n\ |
6801 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6802 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6803 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6804 | /* We need to throw away the frame cache when we set this, since it |
6805 | might change our ability to get backtraces. */ | |
9f60d481 | 6806 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
cb1a6d5f | 6807 | deprecated_add_show_from_set (c, &showlist); |
c906108c SS |
6808 | |
6809 | /* Allow the user to control whether the upper bits of 64-bit | |
6810 | addresses should be zeroed. */ | |
e9e68a56 | 6811 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
6812 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
6813 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
6814 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
6815 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 6816 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 6817 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6818 | |
6819 | /* Allow the user to control the size of 32 bit registers within the | |
6820 | raw remote packet. */ | |
b3f42336 AC |
6821 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6822 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
6823 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
6824 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
6825 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6826 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6827 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
6828 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
6829 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
6830 | |
6831 | /* Debug this files internals. */ | |
cb1a6d5f AC |
6832 | deprecated_add_show_from_set |
6833 | (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6834 | &mips_debug, "Set mips debugging.\n\ | |
6835 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6836 | &showdebuglist); | |
c906108c | 6837 | } |