Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
1e698235 | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
5e2e9765 | 28 | #include "gdb_assert.h" |
c906108c SS |
29 | #include "frame.h" |
30 | #include "inferior.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "language.h" | |
35 | #include "gdbcore.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "target.h" | |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
70f80edf | 42 | #include "osabi.h" |
d1973055 | 43 | #include "mips-tdep.h" |
fe898f56 | 44 | #include "block.h" |
a4b8ebc8 | 45 | #include "reggroups.h" |
c906108c | 46 | #include "opcode/mips.h" |
c2d11a7d JM |
47 | #include "elf/mips.h" |
48 | #include "elf-bfd.h" | |
2475bac3 | 49 | #include "symcat.h" |
a4b8ebc8 | 50 | #include "sim-regno.h" |
a89aa300 | 51 | #include "dis-asm.h" |
c906108c | 52 | |
e0f7ec59 | 53 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 54 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 55 | |
dd824b04 DJ |
56 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
57 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
58 | #define ST0_FR (1 << 26) | |
59 | ||
b0069a17 AC |
60 | /* The sizes of floating point registers. */ |
61 | ||
62 | enum | |
63 | { | |
64 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
65 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
66 | }; | |
67 | ||
0dadbba0 | 68 | |
2e4ebe70 DJ |
69 | static const char *mips_abi_string; |
70 | ||
71 | static const char *mips_abi_strings[] = { | |
72 | "auto", | |
73 | "n32", | |
74 | "o32", | |
28d169de | 75 | "n64", |
2e4ebe70 DJ |
76 | "o64", |
77 | "eabi32", | |
78 | "eabi64", | |
79 | NULL | |
80 | }; | |
81 | ||
cce74817 | 82 | struct frame_extra_info |
c5aa993b JM |
83 | { |
84 | mips_extra_func_info_t proc_desc; | |
85 | int num_args; | |
86 | }; | |
cce74817 | 87 | |
d929b26f AC |
88 | /* Various MIPS ISA options (related to stack analysis) can be |
89 | overridden dynamically. Establish an enum/array for managing | |
90 | them. */ | |
91 | ||
53904c9e AC |
92 | static const char size_auto[] = "auto"; |
93 | static const char size_32[] = "32"; | |
94 | static const char size_64[] = "64"; | |
d929b26f | 95 | |
53904c9e | 96 | static const char *size_enums[] = { |
d929b26f AC |
97 | size_auto, |
98 | size_32, | |
99 | size_64, | |
a5ea2558 AC |
100 | 0 |
101 | }; | |
102 | ||
7a292a7a SS |
103 | /* Some MIPS boards don't support floating point while others only |
104 | support single-precision floating-point operations. See also | |
105 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
106 | |
107 | enum mips_fpu_type | |
c5aa993b JM |
108 | { |
109 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
110 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
111 | MIPS_FPU_NONE /* No floating point. */ | |
112 | }; | |
c906108c SS |
113 | |
114 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
115 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
116 | #endif | |
117 | static int mips_fpu_type_auto = 1; | |
118 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 119 | |
9ace0497 | 120 | static int mips_debug = 0; |
7a292a7a | 121 | |
c2d11a7d JM |
122 | /* MIPS specific per-architecture information */ |
123 | struct gdbarch_tdep | |
124 | { | |
125 | /* from the elf header */ | |
126 | int elf_flags; | |
70f80edf | 127 | |
c2d11a7d | 128 | /* mips options */ |
0dadbba0 | 129 | enum mips_abi mips_abi; |
2e4ebe70 | 130 | enum mips_abi found_abi; |
c2d11a7d JM |
131 | enum mips_fpu_type mips_fpu_type; |
132 | int mips_last_arg_regnum; | |
133 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 134 | int mips_default_saved_regsize; |
c2d11a7d | 135 | int mips_fp_register_double; |
d929b26f | 136 | int mips_default_stack_argsize; |
4014092b | 137 | int default_mask_address_p; |
719ec221 AC |
138 | /* Is the target using 64-bit raw integer registers but only |
139 | storing a left-aligned 32-bit value in each? */ | |
140 | int mips64_transfers_32bit_regs_p; | |
56cea623 AC |
141 | /* Indexes for various registers. IRIX and embedded have |
142 | different values. This contains the "public" fields. Don't | |
143 | add any that do not need to be public. */ | |
144 | const struct mips_regnum *regnum; | |
c2d11a7d JM |
145 | }; |
146 | ||
56cea623 AC |
147 | const struct mips_regnum * |
148 | mips_regnum (struct gdbarch *gdbarch) | |
149 | { | |
150 | return gdbarch_tdep (gdbarch)->regnum; | |
151 | } | |
152 | ||
153 | static int | |
154 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
155 | { | |
156 | return mips_regnum (gdbarch)->fp0 + 12; | |
157 | } | |
158 | ||
0dadbba0 | 159 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 160 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 161 | |
c2d11a7d | 162 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 163 | |
c2d11a7d | 164 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 165 | |
c2d11a7d | 166 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 167 | |
d929b26f AC |
168 | /* Return the currently configured (or set) saved register size. */ |
169 | ||
a5ea2558 | 170 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 171 | |
53904c9e | 172 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
173 | |
174 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
175 | ||
95404a3e AC |
176 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
177 | functions to test, set, or clear bit 0 of addresses. */ | |
178 | ||
179 | static CORE_ADDR | |
180 | is_mips16_addr (CORE_ADDR addr) | |
181 | { | |
182 | return ((addr) & 1); | |
183 | } | |
184 | ||
185 | static CORE_ADDR | |
186 | make_mips16_addr (CORE_ADDR addr) | |
187 | { | |
188 | return ((addr) | 1); | |
189 | } | |
190 | ||
191 | static CORE_ADDR | |
192 | unmake_mips16_addr (CORE_ADDR addr) | |
193 | { | |
194 | return ((addr) & ~1); | |
195 | } | |
196 | ||
22540ece AC |
197 | /* Return the contents of register REGNUM as a signed integer. */ |
198 | ||
199 | static LONGEST | |
200 | read_signed_register (int regnum) | |
201 | { | |
719ec221 | 202 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 203 | deprecated_read_register_gen (regnum, buf); |
719ec221 | 204 | return (extract_signed_integer (buf, register_size (current_gdbarch, regnum))); |
22540ece AC |
205 | } |
206 | ||
207 | static LONGEST | |
208 | read_signed_register_pid (int regnum, ptid_t ptid) | |
209 | { | |
210 | ptid_t save_ptid; | |
211 | LONGEST retval; | |
212 | ||
213 | if (ptid_equal (ptid, inferior_ptid)) | |
214 | return read_signed_register (regnum); | |
215 | ||
216 | save_ptid = inferior_ptid; | |
217 | ||
218 | inferior_ptid = ptid; | |
219 | ||
220 | retval = read_signed_register (regnum); | |
221 | ||
222 | inferior_ptid = save_ptid; | |
223 | ||
224 | return retval; | |
225 | } | |
226 | ||
d1973055 KB |
227 | /* Return the MIPS ABI associated with GDBARCH. */ |
228 | enum mips_abi | |
229 | mips_abi (struct gdbarch *gdbarch) | |
230 | { | |
231 | return gdbarch_tdep (gdbarch)->mips_abi; | |
232 | } | |
233 | ||
4246e332 AC |
234 | int |
235 | mips_regsize (struct gdbarch *gdbarch) | |
236 | { | |
237 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
238 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
239 | } | |
240 | ||
d929b26f | 241 | static unsigned int |
acdb74a0 | 242 | mips_saved_regsize (void) |
d929b26f AC |
243 | { |
244 | if (mips_saved_regsize_string == size_auto) | |
245 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
246 | else if (mips_saved_regsize_string == size_64) | |
247 | return 8; | |
248 | else /* if (mips_saved_regsize_string == size_32) */ | |
249 | return 4; | |
250 | } | |
251 | ||
71b8ef93 | 252 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 253 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 254 | "info" field is used for this purpose. |
5a89d8aa MS |
255 | |
256 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
257 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
258 | minimal symbol to mark it as a 16-bit function | |
259 | ||
f594e5e9 | 260 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 261 | |
5a89d8aa MS |
262 | static void |
263 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
264 | { | |
265 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
266 | { | |
267 | MSYMBOL_INFO (msym) = (char *) | |
268 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
269 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
270 | } | |
271 | } | |
272 | ||
71b8ef93 MS |
273 | static int |
274 | msymbol_is_special (struct minimal_symbol *msym) | |
275 | { | |
276 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
277 | } | |
278 | ||
88658117 AC |
279 | /* XFER a value from the big/little/left end of the register. |
280 | Depending on the size of the value it might occupy the entire | |
281 | register or just part of it. Make an allowance for this, aligning | |
282 | things accordingly. */ | |
283 | ||
284 | static void | |
285 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
286 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
287 | int buf_offset) | |
288 | { | |
d9d9c31f | 289 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 290 | int reg_offset = 0; |
a4b8ebc8 | 291 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
292 | /* Need to transfer the left or right part of the register, based on |
293 | the targets byte order. */ | |
88658117 AC |
294 | switch (endian) |
295 | { | |
296 | case BFD_ENDIAN_BIG: | |
719ec221 | 297 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
298 | break; |
299 | case BFD_ENDIAN_LITTLE: | |
300 | reg_offset = 0; | |
301 | break; | |
302 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
303 | reg_offset = 0; | |
304 | break; | |
305 | default: | |
306 | internal_error (__FILE__, __LINE__, "bad switch"); | |
307 | } | |
308 | if (mips_debug) | |
cb1d2653 AC |
309 | fprintf_unfiltered (gdb_stderr, |
310 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
311 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
312 | if (mips_debug && out != NULL) |
313 | { | |
314 | int i; | |
cb1d2653 | 315 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 316 | for (i = 0; i < length; i++) |
cb1d2653 | 317 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
318 | } |
319 | if (in != NULL) | |
a4b8ebc8 | 320 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); |
88658117 | 321 | if (out != NULL) |
a4b8ebc8 | 322 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
323 | if (mips_debug && in != NULL) |
324 | { | |
325 | int i; | |
cb1d2653 | 326 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 327 | for (i = 0; i < length; i++) |
cb1d2653 | 328 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
329 | } |
330 | if (mips_debug) | |
331 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
332 | } | |
333 | ||
dd824b04 DJ |
334 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
335 | compatiblity mode. A return value of 1 means that we have | |
336 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
337 | ||
338 | static int | |
339 | mips2_fp_compat (void) | |
340 | { | |
341 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
342 | meaningful. */ | |
56cea623 | 343 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 4) |
dd824b04 DJ |
344 | return 0; |
345 | ||
346 | #if 0 | |
347 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
348 | in all the places we deal with FP registers. PR gdb/413. */ | |
349 | /* Otherwise check the FR bit in the status register - it controls | |
350 | the FP compatiblity mode. If it is clear we are in compatibility | |
351 | mode. */ | |
352 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
353 | return 1; | |
354 | #endif | |
361d1df0 | 355 | |
dd824b04 DJ |
356 | return 0; |
357 | } | |
358 | ||
c2d11a7d JM |
359 | /* Indicate that the ABI makes use of double-precision registers |
360 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 361 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 362 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 363 | |
d929b26f AC |
364 | /* The amount of space reserved on the stack for registers. This is |
365 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
366 | data allocated after the registers have run out. */ | |
367 | ||
0dadbba0 | 368 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
369 | |
370 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
371 | ||
53904c9e | 372 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
373 | |
374 | static unsigned int | |
375 | mips_stack_argsize (void) | |
376 | { | |
377 | if (mips_stack_argsize_string == size_auto) | |
378 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
379 | else if (mips_stack_argsize_string == size_64) | |
380 | return 8; | |
381 | else /* if (mips_stack_argsize_string == size_32) */ | |
382 | return 4; | |
383 | } | |
384 | ||
92e1c15c | 385 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 386 | |
7a292a7a | 387 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 388 | |
570b8f7c AC |
389 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
390 | struct frame_info *, int); | |
c906108c | 391 | |
a14ed312 | 392 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 393 | |
a14ed312 | 394 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 395 | |
5a89d8aa | 396 | static int mips_set_processor_type (char *); |
c906108c | 397 | |
a14ed312 | 398 | static void mips_show_processor_type_command (char *, int); |
c906108c | 399 | |
a14ed312 | 400 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 401 | |
570b8f7c AC |
402 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
403 | struct frame_info *next_frame, | |
404 | int cur_frame); | |
c906108c | 405 | |
a14ed312 KB |
406 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
407 | mips_extra_func_info_t proc_desc); | |
c906108c | 408 | |
67b2c998 DJ |
409 | static struct type *mips_float_register_type (void); |
410 | static struct type *mips_double_register_type (void); | |
411 | ||
c906108c SS |
412 | /* This value is the model of MIPS in use. It is derived from the value |
413 | of the PrID register. */ | |
414 | ||
415 | char *mips_processor_type; | |
416 | ||
417 | char *tmp_mips_processor_type; | |
418 | ||
acdb74a0 AC |
419 | /* The list of available "set mips " and "show mips " commands */ |
420 | ||
421 | static struct cmd_list_element *setmipscmdlist = NULL; | |
422 | static struct cmd_list_element *showmipscmdlist = NULL; | |
423 | ||
c906108c SS |
424 | /* A set of original names, to be used when restoring back to generic |
425 | registers from a specific set. */ | |
5e2e9765 | 426 | static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
c906108c | 427 | |
5e2e9765 KB |
428 | /* Integer registers 0 thru 31 are handled explicitly by |
429 | mips_register_name(). Processor specific registers 32 and above | |
430 | are listed in the sets of register names assigned to | |
431 | mips_processor_reg_names. */ | |
432 | static char **mips_processor_reg_names = mips_generic_reg_names; | |
cce74817 | 433 | |
5e2e9765 | 434 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 435 | static const char * |
5e2e9765 | 436 | mips_register_name (int regno) |
cce74817 | 437 | { |
5e2e9765 KB |
438 | /* GPR names for all ABIs other than n32/n64. */ |
439 | static char *mips_gpr_names[] = { | |
440 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
441 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
442 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
443 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
444 | }; | |
445 | ||
446 | /* GPR names for n32 and n64 ABIs. */ | |
447 | static char *mips_n32_n64_gpr_names[] = { | |
448 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
449 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
450 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
451 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
452 | }; | |
453 | ||
454 | enum mips_abi abi = mips_abi (current_gdbarch); | |
455 | ||
a4b8ebc8 AC |
456 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
457 | don't make the raw register names visible. */ | |
458 | int rawnum = regno % NUM_REGS; | |
459 | if (regno < NUM_REGS) | |
460 | return ""; | |
461 | ||
5e2e9765 KB |
462 | /* The MIPS integer registers are always mapped from 0 to 31. The |
463 | names of the registers (which reflects the conventions regarding | |
464 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 465 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
466 | { |
467 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 468 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 469 | else |
a4b8ebc8 | 470 | return mips_gpr_names[rawnum]; |
5e2e9765 | 471 | } |
a4b8ebc8 AC |
472 | else if (32 <= rawnum && rawnum < NUM_REGS) |
473 | return mips_processor_reg_names[rawnum - 32]; | |
5e2e9765 KB |
474 | else |
475 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 476 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 477 | } |
5e2e9765 | 478 | |
9846de1b | 479 | /* *INDENT-OFF* */ |
c906108c SS |
480 | /* Names of IDT R3041 registers. */ |
481 | ||
482 | char *mips_r3041_reg_names[] = { | |
c906108c SS |
483 | "sr", "lo", "hi", "bad", "cause","pc", |
484 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
485 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
486 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
487 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 488 | "fsr", "fir", "",/*"fp"*/ "", |
c906108c SS |
489 | "", "", "bus", "ccfg", "", "", "", "", |
490 | "", "", "port", "cmp", "", "", "epc", "prid", | |
491 | }; | |
492 | ||
493 | /* Names of IDT R3051 registers. */ | |
494 | ||
495 | char *mips_r3051_reg_names[] = { | |
c906108c SS |
496 | "sr", "lo", "hi", "bad", "cause","pc", |
497 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
498 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
499 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
500 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 501 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
502 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
503 | "", "", "ehi", "", "", "", "epc", "prid", | |
504 | }; | |
505 | ||
506 | /* Names of IDT R3081 registers. */ | |
507 | ||
508 | char *mips_r3081_reg_names[] = { | |
c906108c SS |
509 | "sr", "lo", "hi", "bad", "cause","pc", |
510 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
511 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
512 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
513 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 514 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
515 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
516 | "", "", "ehi", "", "", "", "epc", "prid", | |
517 | }; | |
518 | ||
519 | /* Names of LSI 33k registers. */ | |
520 | ||
521 | char *mips_lsi33k_reg_names[] = { | |
c906108c SS |
522 | "epc", "hi", "lo", "sr", "cause","badvaddr", |
523 | "dcic", "bpc", "bda", "", "", "", "", "", | |
524 | "", "", "", "", "", "", "", "", | |
525 | "", "", "", "", "", "", "", "", | |
526 | "", "", "", "", "", "", "", "", | |
527 | "", "", "", "", | |
528 | "", "", "", "", "", "", "", "", | |
529 | "", "", "", "", "", "", "", "", | |
530 | }; | |
531 | ||
532 | struct { | |
533 | char *name; | |
534 | char **regnames; | |
535 | } mips_processor_type_table[] = { | |
536 | { "generic", mips_generic_reg_names }, | |
537 | { "r3041", mips_r3041_reg_names }, | |
538 | { "r3051", mips_r3051_reg_names }, | |
539 | { "r3071", mips_r3081_reg_names }, | |
540 | { "r3081", mips_r3081_reg_names }, | |
541 | { "lsi33k", mips_lsi33k_reg_names }, | |
542 | { NULL, NULL } | |
543 | }; | |
9846de1b | 544 | /* *INDENT-ON* */ |
c906108c | 545 | |
a4b8ebc8 | 546 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 547 | |
a4b8ebc8 AC |
548 | static int |
549 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
550 | struct reggroup *reggroup) | |
551 | { | |
552 | int vector_p; | |
553 | int float_p; | |
554 | int raw_p; | |
555 | int rawnum = regnum % NUM_REGS; | |
556 | int pseudo = regnum / NUM_REGS; | |
557 | if (reggroup == all_reggroup) | |
558 | return pseudo; | |
559 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
560 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
561 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
562 | (gdbarch), as not all architectures are multi-arch. */ | |
563 | raw_p = rawnum < NUM_REGS; | |
564 | if (REGISTER_NAME (regnum) == NULL | |
565 | || REGISTER_NAME (regnum)[0] == '\0') | |
566 | return 0; | |
567 | if (reggroup == float_reggroup) | |
568 | return float_p && pseudo; | |
569 | if (reggroup == vector_reggroup) | |
570 | return vector_p && pseudo; | |
571 | if (reggroup == general_reggroup) | |
572 | return (!vector_p && !float_p) && pseudo; | |
573 | /* Save the pseudo registers. Need to make certain that any code | |
574 | extracting register values from a saved register cache also uses | |
575 | pseudo registers. */ | |
576 | if (reggroup == save_reggroup) | |
577 | return raw_p && pseudo; | |
578 | /* Restore the same pseudo register. */ | |
579 | if (reggroup == restore_reggroup) | |
580 | return raw_p && pseudo; | |
581 | return 0; | |
582 | } | |
583 | ||
584 | /* Map the symbol table registers which live in the range [1 * | |
585 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
586 | registers. */ | |
c5aa993b | 587 | |
a4b8ebc8 AC |
588 | static void |
589 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
590 | int cookednum, void *buf) | |
591 | { | |
592 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); | |
593 | return regcache_raw_read (regcache, cookednum % NUM_REGS, buf); | |
594 | } | |
595 | ||
596 | static void | |
597 | mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
598 | int cookednum, const void *buf) | |
599 | { | |
600 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); | |
601 | return regcache_raw_write (regcache, cookednum % NUM_REGS, buf); | |
602 | } | |
c5aa993b | 603 | |
c906108c | 604 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
605 | static int mips16_to_32_reg[8] = |
606 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
607 | |
608 | /* Heuristic_proc_start may hunt through the text section for a long | |
609 | time across a 2400 baud serial line. Allows the user to limit this | |
610 | search. */ | |
611 | ||
612 | static unsigned int heuristic_fence_post = 0; | |
613 | ||
c5aa993b JM |
614 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
615 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
616 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
617 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
618 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
619 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
620 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
621 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
622 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
623 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
624 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
625 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
626 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
627 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
628 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
629 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
630 | ||
631 | struct linked_proc_info | |
c5aa993b JM |
632 | { |
633 | struct mips_extra_func_info info; | |
634 | struct linked_proc_info *next; | |
635 | } | |
636 | *linked_proc_desc_table = NULL; | |
c906108c | 637 | |
46cd78fb | 638 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
639 | register N. NOTE: This defines the pseudo register type so need to |
640 | rebuild the architecture vector. */ | |
43e526b9 JM |
641 | |
642 | static int mips64_transfers_32bit_regs_p = 0; | |
643 | ||
719ec221 AC |
644 | static void |
645 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
646 | struct cmd_list_element *c) | |
43e526b9 | 647 | { |
719ec221 AC |
648 | struct gdbarch_info info; |
649 | gdbarch_info_init (&info); | |
650 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
651 | instead of relying on globals. Doing that would let generic code | |
652 | handle the search for this specific architecture. */ | |
653 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 654 | { |
719ec221 AC |
655 | mips64_transfers_32bit_regs_p = 0; |
656 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 657 | } |
a4b8ebc8 AC |
658 | } |
659 | ||
46cd78fb AC |
660 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
661 | defines the remote-gdb packet. */ | |
662 | ||
d05285fa | 663 | static int |
acdb74a0 | 664 | mips_register_convertible (int reg_nr) |
43e526b9 | 665 | { |
719ec221 | 666 | if (gdbarch_tdep (current_gdbarch)->mips64_transfers_32bit_regs_p) |
43e526b9 JM |
667 | return 0; |
668 | else | |
719ec221 | 669 | return (register_size (current_gdbarch, reg_nr) > register_size (current_gdbarch, reg_nr)); |
43e526b9 JM |
670 | } |
671 | ||
d05285fa | 672 | static void |
acdb74a0 AC |
673 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
674 | char *raw_buf, char *virt_buf) | |
43e526b9 | 675 | { |
d7449b42 | 676 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 | 677 | memcpy (virt_buf, |
719ec221 | 678 | raw_buf + (register_size (current_gdbarch, n) - TYPE_LENGTH (virtual_type)), |
43e526b9 JM |
679 | TYPE_LENGTH (virtual_type)); |
680 | else | |
681 | memcpy (virt_buf, | |
682 | raw_buf, | |
683 | TYPE_LENGTH (virtual_type)); | |
684 | } | |
685 | ||
d05285fa | 686 | static void |
acdb74a0 | 687 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
781a750d | 688 | const char *virt_buf, char *raw_buf) |
43e526b9 | 689 | { |
719ec221 | 690 | memset (raw_buf, 0, register_size (current_gdbarch, n)); |
d7449b42 | 691 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
719ec221 | 692 | memcpy (raw_buf + (register_size (current_gdbarch, n) - TYPE_LENGTH (virtual_type)), |
43e526b9 JM |
693 | virt_buf, |
694 | TYPE_LENGTH (virtual_type)); | |
695 | else | |
696 | memcpy (raw_buf, | |
697 | virt_buf, | |
698 | TYPE_LENGTH (virtual_type)); | |
699 | } | |
700 | ||
ff2e87ac AC |
701 | static int |
702 | mips_convert_register_p (int regnum, struct type *type) | |
703 | { | |
704 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 705 | && register_size (current_gdbarch, regnum) == 4 |
56cea623 | 706 | && (regnum) >= mips_regnum (current_gdbarch)->fp0 && (regnum) < mips_regnum (current_gdbarch)->fp0 + 32 |
ff2e87ac AC |
707 | && TYPE_CODE(type) == TYPE_CODE_FLT |
708 | && TYPE_LENGTH(type) == 8); | |
709 | } | |
710 | ||
42c466d7 | 711 | static void |
ff2e87ac AC |
712 | mips_register_to_value (struct frame_info *frame, int regnum, |
713 | struct type *type, void *to) | |
102182a9 | 714 | { |
7f5f525d AC |
715 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
716 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
717 | } |
718 | ||
42c466d7 | 719 | static void |
ff2e87ac AC |
720 | mips_value_to_register (struct frame_info *frame, int regnum, |
721 | struct type *type, const void *from) | |
102182a9 | 722 | { |
ff2e87ac AC |
723 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
724 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
725 | } |
726 | ||
a4b8ebc8 AC |
727 | /* Return the GDB type object for the "standard" data type of data in |
728 | register REG. */ | |
78fde5f8 KB |
729 | |
730 | static struct type * | |
a4b8ebc8 AC |
731 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
732 | { | |
5ef80fb0 | 733 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
734 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
735 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 736 | { |
5ef80fb0 AC |
737 | /* The floating-point registers raw, or cooked, always match |
738 | mips_regsize(), and also map 1:1, byte for byte. */ | |
739 | switch (gdbarch_byte_order (gdbarch)) | |
740 | { | |
741 | case BFD_ENDIAN_BIG: | |
742 | if (mips_regsize (gdbarch) == 4) | |
743 | return builtin_type_ieee_single_big; | |
744 | else | |
745 | return builtin_type_ieee_double_big; | |
746 | case BFD_ENDIAN_LITTLE: | |
747 | if (mips_regsize (gdbarch) == 4) | |
748 | return builtin_type_ieee_single_little; | |
749 | else | |
750 | return builtin_type_ieee_double_little; | |
751 | case BFD_ENDIAN_UNKNOWN: | |
752 | default: | |
753 | internal_error (__FILE__, __LINE__, "bad switch"); | |
754 | } | |
a6425924 | 755 | } |
56cea623 | 756 | else if (regnum >= (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) |
5ef80fb0 AC |
757 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
758 | /* The pseudo/cooked view of the embedded registers is always | |
759 | 32-bit. The raw view is handled below. */ | |
760 | return builtin_type_int32; | |
719ec221 AC |
761 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
762 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
763 | /* The target, while using a 64-bit register buffer, is only | |
764 | transfering 32-bits of each integer register. Reflect this in | |
765 | the cooked/pseudo register value. */ | |
766 | return builtin_type_int32; | |
5ef80fb0 AC |
767 | else if (mips_regsize (gdbarch) == 8) |
768 | /* 64-bit ISA. */ | |
769 | return builtin_type_int64; | |
78fde5f8 | 770 | else |
5ef80fb0 AC |
771 | /* 32-bit ISA. */ |
772 | return builtin_type_int32; | |
78fde5f8 KB |
773 | } |
774 | ||
bcb0cc15 MS |
775 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
776 | ||
777 | static CORE_ADDR | |
778 | mips_read_sp (void) | |
779 | { | |
e227b13c | 780 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
781 | } |
782 | ||
c906108c | 783 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 784 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
785 | |
786 | static int | |
787 | mips_mask_address_p (void) | |
788 | { | |
789 | switch (mask_address_var) | |
790 | { | |
7f19b9a2 | 791 | case AUTO_BOOLEAN_TRUE: |
4014092b | 792 | return 1; |
7f19b9a2 | 793 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
794 | return 0; |
795 | break; | |
7f19b9a2 | 796 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 797 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 798 | default: |
8e65ff28 AC |
799 | internal_error (__FILE__, __LINE__, |
800 | "mips_mask_address_p: bad switch"); | |
4014092b | 801 | return -1; |
361d1df0 | 802 | } |
4014092b AC |
803 | } |
804 | ||
805 | static void | |
e9e68a56 | 806 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
807 | { |
808 | switch (mask_address_var) | |
809 | { | |
7f19b9a2 | 810 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
811 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
812 | break; | |
7f19b9a2 | 813 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
814 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
815 | break; | |
7f19b9a2 | 816 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
817 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
818 | mips_mask_address_p () ? "enabled" : "disabled"); | |
819 | break; | |
820 | default: | |
8e65ff28 AC |
821 | internal_error (__FILE__, __LINE__, |
822 | "show_mask_address: bad switch"); | |
4014092b | 823 | break; |
361d1df0 | 824 | } |
4014092b | 825 | } |
c906108c SS |
826 | |
827 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 828 | |
f7ab6ec6 | 829 | static int |
cb811fe7 | 830 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 831 | { |
cb811fe7 MS |
832 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
833 | } | |
834 | ||
f7ab6ec6 | 835 | static int |
cb811fe7 MS |
836 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) |
837 | { | |
b78bcb18 | 838 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
839 | } |
840 | ||
8b389c40 MS |
841 | /* Should call_function pass struct by reference? |
842 | For each architecture, structs are passed either by | |
843 | value or by reference, depending on their size. */ | |
844 | ||
845 | static int | |
846 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
847 | { | |
848 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
849 | int len = TYPE_LENGTH (check_typedef (type)); | |
850 | ||
851 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
852 | return (len > MIPS_SAVED_REGSIZE); | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
857 | static int | |
858 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
859 | { | |
860 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
861 | } | |
862 | ||
f7ab6ec6 | 863 | static int |
8b389c40 MS |
864 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
865 | { | |
866 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
867 | } | |
868 | ||
c906108c SS |
869 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
870 | ||
871 | static int | |
872 | pc_is_mips16 (bfd_vma memaddr) | |
873 | { | |
874 | struct minimal_symbol *sym; | |
875 | ||
876 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 877 | if (is_mips16_addr (memaddr)) |
c906108c SS |
878 | return 1; |
879 | ||
880 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
881 | the high bit of the info field. Use this to decide if the function is | |
882 | MIPS16 or normal MIPS. */ | |
883 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
884 | if (sym) | |
71b8ef93 | 885 | return msymbol_is_special (sym); |
c906108c SS |
886 | else |
887 | return 0; | |
888 | } | |
889 | ||
6c997a34 AC |
890 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
891 | all registers should be sign extended for simplicity? */ | |
892 | ||
893 | static CORE_ADDR | |
39f77062 | 894 | mips_read_pc (ptid_t ptid) |
6c997a34 | 895 | { |
39f77062 | 896 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 897 | } |
c906108c SS |
898 | |
899 | /* This returns the PC of the first inst after the prologue. If we can't | |
900 | find the prologue, then return 0. */ | |
901 | ||
902 | static CORE_ADDR | |
acdb74a0 AC |
903 | after_prologue (CORE_ADDR pc, |
904 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
905 | { |
906 | struct symtab_and_line sal; | |
907 | CORE_ADDR func_addr, func_end; | |
908 | ||
479412cd DJ |
909 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
910 | to read the stack pointer from the current machine state, because | |
911 | the current machine state has nothing to do with the information | |
912 | we need from the proc_desc; and the process may or may not exist | |
913 | right now. */ | |
c906108c | 914 | if (!proc_desc) |
479412cd | 915 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
916 | |
917 | if (proc_desc) | |
918 | { | |
919 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 920 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
921 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
922 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
923 | return 0; | |
924 | } | |
925 | ||
926 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
927 | return 0; /* Unknown */ | |
928 | ||
929 | sal = find_pc_line (func_addr, 0); | |
930 | ||
931 | if (sal.end < func_end) | |
932 | return sal.end; | |
933 | ||
934 | /* The line after the prologue is after the end of the function. In this | |
935 | case, tell the caller to find the prologue the hard way. */ | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
941 | set the appropriate bit in the general register mask or float register mask | |
942 | to indicate which register is saved. This is a helper function | |
943 | for mips_find_saved_regs. */ | |
944 | ||
945 | static void | |
acdb74a0 AC |
946 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
947 | unsigned long *float_mask) | |
c906108c SS |
948 | { |
949 | int reg; | |
950 | ||
951 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
952 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
953 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
954 | { | |
955 | /* It might be possible to use the instruction to | |
c5aa993b JM |
956 | find the offset, rather than the code below which |
957 | is based on things being in a certain order in the | |
958 | frame, but figuring out what the instruction's offset | |
959 | is relative to might be a little tricky. */ | |
c906108c SS |
960 | reg = (inst & 0x001f0000) >> 16; |
961 | *gen_mask |= (1 << reg); | |
962 | } | |
963 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
964 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
965 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
966 | |
967 | { | |
968 | reg = ((inst & 0x001f0000) >> 16); | |
969 | *float_mask |= (1 << reg); | |
970 | } | |
971 | } | |
972 | ||
973 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
974 | set the appropriate bit in the general register or float register mask | |
975 | to indicate which register is saved. This is a helper function | |
976 | for mips_find_saved_regs. */ | |
977 | ||
978 | static void | |
acdb74a0 | 979 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 980 | { |
c5aa993b | 981 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
982 | { |
983 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
984 | *gen_mask |= (1 << reg); | |
985 | } | |
c5aa993b | 986 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
987 | { |
988 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
989 | *gen_mask |= (1 << reg); | |
990 | } | |
c5aa993b | 991 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
992 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
993 | *gen_mask |= (1 << RA_REGNUM); | |
994 | } | |
995 | ||
996 | ||
997 | /* Fetch and return instruction from the specified location. If the PC | |
998 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
999 | ||
1000 | static t_inst | |
acdb74a0 | 1001 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
1002 | { |
1003 | char buf[MIPS_INSTLEN]; | |
1004 | int instlen; | |
1005 | int status; | |
1006 | ||
1007 | if (pc_is_mips16 (addr)) | |
1008 | { | |
1009 | instlen = MIPS16_INSTLEN; | |
95404a3e | 1010 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1011 | } |
1012 | else | |
c5aa993b | 1013 | instlen = MIPS_INSTLEN; |
c906108c SS |
1014 | status = read_memory_nobpt (addr, buf, instlen); |
1015 | if (status) | |
1016 | memory_error (status, addr); | |
1017 | return extract_unsigned_integer (buf, instlen); | |
1018 | } | |
1019 | ||
1020 | ||
1021 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
1022 | #define mips32_op(x) (x >> 26) |
1023 | #define itype_op(x) (x >> 26) | |
1024 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1025 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1026 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1027 | |
e135b889 DJ |
1028 | #define jtype_op(x) (x >> 26) |
1029 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1030 | |
e135b889 DJ |
1031 | #define rtype_op(x) (x >> 26) |
1032 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1033 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1034 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1035 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1036 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1037 | |
1038 | static CORE_ADDR | |
c5aa993b JM |
1039 | mips32_relative_offset (unsigned long inst) |
1040 | { | |
1041 | long x; | |
1042 | x = itype_immediate (inst); | |
1043 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1044 | { |
c5aa993b | 1045 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1046 | } |
c5aa993b JM |
1047 | x = x << 2; |
1048 | return x; | |
c906108c SS |
1049 | } |
1050 | ||
1051 | /* Determine whate to set a single step breakpoint while considering | |
1052 | branch prediction */ | |
5a89d8aa | 1053 | static CORE_ADDR |
c5aa993b JM |
1054 | mips32_next_pc (CORE_ADDR pc) |
1055 | { | |
1056 | unsigned long inst; | |
1057 | int op; | |
1058 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1059 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1060 | { |
e135b889 DJ |
1061 | if (itype_op (inst) >> 2 == 5) |
1062 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 1063 | { |
e135b889 | 1064 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1065 | switch (op) |
1066 | { | |
e135b889 DJ |
1067 | case 0: /* BEQL */ |
1068 | goto equal_branch; | |
1069 | case 1: /* BNEL */ | |
1070 | goto neq_branch; | |
1071 | case 2: /* BLEZL */ | |
1072 | goto less_branch; | |
1073 | case 3: /* BGTZ */ | |
1074 | goto greater_branch; | |
c5aa993b JM |
1075 | default: |
1076 | pc += 4; | |
c906108c SS |
1077 | } |
1078 | } | |
e135b889 DJ |
1079 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1080 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1081 | { | |
1082 | int tf = itype_rt (inst) & 0x01; | |
1083 | int cnum = itype_rt (inst) >> 2; | |
56cea623 | 1084 | int fcrcs = read_signed_register (mips_regnum (current_gdbarch)->fp_control_status); |
e135b889 DJ |
1085 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1086 | ||
1087 | if (((cond >> cnum) & 0x01) == tf) | |
1088 | pc += mips32_relative_offset (inst) + 4; | |
1089 | else | |
1090 | pc += 8; | |
1091 | } | |
c5aa993b JM |
1092 | else |
1093 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1094 | } |
1095 | else | |
c5aa993b JM |
1096 | { /* This gets way messy */ |
1097 | ||
c906108c | 1098 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1099 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1100 | { |
c5aa993b JM |
1101 | case 0: /* SPECIAL */ |
1102 | op = rtype_funct (inst); | |
1103 | switch (op) | |
1104 | { | |
1105 | case 8: /* JR */ | |
1106 | case 9: /* JALR */ | |
6c997a34 AC |
1107 | /* Set PC to that address */ |
1108 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1109 | break; |
1110 | default: | |
1111 | pc += 4; | |
1112 | } | |
1113 | ||
e135b889 | 1114 | break; /* end SPECIAL */ |
c5aa993b | 1115 | case 1: /* REGIMM */ |
c906108c | 1116 | { |
e135b889 DJ |
1117 | op = itype_rt (inst); /* branch condition */ |
1118 | switch (op) | |
c906108c | 1119 | { |
c5aa993b | 1120 | case 0: /* BLTZ */ |
e135b889 DJ |
1121 | case 2: /* BLTZL */ |
1122 | case 16: /* BLTZAL */ | |
c5aa993b | 1123 | case 18: /* BLTZALL */ |
c906108c | 1124 | less_branch: |
6c997a34 | 1125 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1126 | pc += mips32_relative_offset (inst) + 4; |
1127 | else | |
1128 | pc += 8; /* after the delay slot */ | |
1129 | break; | |
e135b889 | 1130 | case 1: /* BGEZ */ |
c5aa993b JM |
1131 | case 3: /* BGEZL */ |
1132 | case 17: /* BGEZAL */ | |
1133 | case 19: /* BGEZALL */ | |
c906108c | 1134 | greater_equal_branch: |
6c997a34 | 1135 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1136 | pc += mips32_relative_offset (inst) + 4; |
1137 | else | |
1138 | pc += 8; /* after the delay slot */ | |
1139 | break; | |
e135b889 | 1140 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1141 | default: |
1142 | pc += 4; | |
c906108c SS |
1143 | } |
1144 | } | |
e135b889 | 1145 | break; /* end REGIMM */ |
c5aa993b JM |
1146 | case 2: /* J */ |
1147 | case 3: /* JAL */ | |
1148 | { | |
1149 | unsigned long reg; | |
1150 | reg = jtype_target (inst) << 2; | |
e135b889 | 1151 | /* Upper four bits get never changed... */ |
c5aa993b | 1152 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1153 | } |
c5aa993b JM |
1154 | break; |
1155 | /* FIXME case JALX : */ | |
1156 | { | |
1157 | unsigned long reg; | |
1158 | reg = jtype_target (inst) << 2; | |
1159 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1160 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1161 | } | |
c5aa993b | 1162 | break; /* The new PC will be alternate mode */ |
e135b889 | 1163 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1164 | equal_branch: |
6c997a34 AC |
1165 | if (read_signed_register (itype_rs (inst)) == |
1166 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1167 | pc += mips32_relative_offset (inst) + 4; |
1168 | else | |
1169 | pc += 8; | |
1170 | break; | |
e135b889 | 1171 | case 5: /* BNE, BNEL */ |
c5aa993b | 1172 | neq_branch: |
6c997a34 | 1173 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1174 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1175 | pc += mips32_relative_offset (inst) + 4; |
1176 | else | |
1177 | pc += 8; | |
1178 | break; | |
e135b889 | 1179 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1180 | less_zero_branch: |
6c997a34 | 1181 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1182 | pc += mips32_relative_offset (inst) + 4; |
1183 | else | |
1184 | pc += 8; | |
1185 | break; | |
1186 | case 7: | |
e135b889 DJ |
1187 | default: |
1188 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1189 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1190 | pc += mips32_relative_offset (inst) + 4; |
1191 | else | |
1192 | pc += 8; | |
1193 | break; | |
c5aa993b JM |
1194 | } /* switch */ |
1195 | } /* else */ | |
1196 | return pc; | |
1197 | } /* mips32_next_pc */ | |
c906108c SS |
1198 | |
1199 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1200 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1201 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1202 | We dont want to set a single step instruction on the extend instruction | |
1203 | either. | |
c5aa993b | 1204 | */ |
c906108c SS |
1205 | |
1206 | /* Lots of mips16 instruction formats */ | |
1207 | /* Predicting jumps requires itype,ritype,i8type | |
1208 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1209 | */ |
c906108c SS |
1210 | enum mips16_inst_fmts |
1211 | { | |
c5aa993b JM |
1212 | itype, /* 0 immediate 5,10 */ |
1213 | ritype, /* 1 5,3,8 */ | |
1214 | rrtype, /* 2 5,3,3,5 */ | |
1215 | rritype, /* 3 5,3,3,5 */ | |
1216 | rrrtype, /* 4 5,3,3,3,2 */ | |
1217 | rriatype, /* 5 5,3,3,1,4 */ | |
1218 | shifttype, /* 6 5,3,3,3,2 */ | |
1219 | i8type, /* 7 5,3,8 */ | |
1220 | i8movtype, /* 8 5,3,3,5 */ | |
1221 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1222 | i64type, /* 10 5,3,8 */ | |
1223 | ri64type, /* 11 5,3,3,5 */ | |
1224 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1225 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1226 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1227 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1228 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1229 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1230 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1231 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1232 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1233 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1234 | }; | |
12f02c2a AC |
1235 | /* I am heaping all the fields of the formats into one structure and |
1236 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1237 | struct upk_mips16 |
c5aa993b | 1238 | { |
12f02c2a | 1239 | CORE_ADDR offset; |
c5aa993b JM |
1240 | unsigned int regx; /* Function in i8 type */ |
1241 | unsigned int regy; | |
1242 | }; | |
c906108c SS |
1243 | |
1244 | ||
12f02c2a AC |
1245 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1246 | for the bits which make up the immediatate extension. */ | |
c906108c | 1247 | |
12f02c2a AC |
1248 | static CORE_ADDR |
1249 | extended_offset (unsigned int extension) | |
c906108c | 1250 | { |
12f02c2a | 1251 | CORE_ADDR value; |
c5aa993b JM |
1252 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1253 | value = value << 6; | |
1254 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1255 | value = value << 5; | |
1256 | value |= extension & 0x01f; /* extract 4:0 */ | |
1257 | return value; | |
c906108c SS |
1258 | } |
1259 | ||
1260 | /* Only call this function if you know that this is an extendable | |
1261 | instruction, It wont malfunction, but why make excess remote memory references? | |
1262 | If the immediate operands get sign extended or somthing, do it after | |
1263 | the extension is performed. | |
c5aa993b | 1264 | */ |
c906108c SS |
1265 | /* FIXME: Every one of these cases needs to worry about sign extension |
1266 | when the offset is to be used in relative addressing */ | |
1267 | ||
1268 | ||
12f02c2a | 1269 | static unsigned int |
c5aa993b | 1270 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1271 | { |
c5aa993b JM |
1272 | char buf[8]; |
1273 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1274 | target_read_memory (pc, buf, 2); | |
1275 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1276 | } |
1277 | ||
1278 | static void | |
c5aa993b | 1279 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1280 | unsigned int extension, |
1281 | unsigned int inst, | |
1282 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1283 | struct upk_mips16 *upk) |
c906108c | 1284 | { |
12f02c2a AC |
1285 | CORE_ADDR offset; |
1286 | int regx; | |
1287 | int regy; | |
1288 | switch (insn_format) | |
c906108c | 1289 | { |
c5aa993b | 1290 | case itype: |
c906108c | 1291 | { |
12f02c2a AC |
1292 | CORE_ADDR value; |
1293 | if (extension) | |
c5aa993b JM |
1294 | { |
1295 | value = extended_offset (extension); | |
1296 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1297 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1298 | } |
1299 | else | |
c5aa993b | 1300 | { |
12f02c2a | 1301 | value = inst & 0x7ff; |
c5aa993b | 1302 | /* FIXME : Consider sign extension */ |
c906108c | 1303 | } |
12f02c2a AC |
1304 | offset = value; |
1305 | regx = -1; | |
1306 | regy = -1; | |
c906108c | 1307 | } |
c5aa993b JM |
1308 | break; |
1309 | case ritype: | |
1310 | case i8type: | |
1311 | { /* A register identifier and an offset */ | |
c906108c SS |
1312 | /* Most of the fields are the same as I type but the |
1313 | immediate value is of a different length */ | |
12f02c2a AC |
1314 | CORE_ADDR value; |
1315 | if (extension) | |
c906108c | 1316 | { |
c5aa993b JM |
1317 | value = extended_offset (extension); |
1318 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1319 | value |= inst & 0xff; /* eleven bits from instruction */ |
1320 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1321 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1322 | { | |
1323 | value &= ~0x3fff; /* remove the sign bit */ | |
1324 | value = -value; | |
c906108c SS |
1325 | } |
1326 | } | |
c5aa993b JM |
1327 | else |
1328 | { | |
12f02c2a AC |
1329 | value = inst & 0xff; /* 8 bits */ |
1330 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1331 | /* FIXME: Do sign extension , this format needs it */ |
1332 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1333 | { | |
1334 | value &= 0xef; /* remove the sign bit */ | |
1335 | value = -value; | |
1336 | } | |
c5aa993b | 1337 | } |
12f02c2a AC |
1338 | offset = value; |
1339 | regy = -1; | |
c5aa993b | 1340 | break; |
c906108c | 1341 | } |
c5aa993b | 1342 | case jalxtype: |
c906108c | 1343 | { |
c5aa993b | 1344 | unsigned long value; |
12f02c2a AC |
1345 | unsigned int nexthalf; |
1346 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1347 | value = value << 16; |
1348 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1349 | value |= nexthalf; | |
12f02c2a AC |
1350 | offset = value; |
1351 | regx = -1; | |
1352 | regy = -1; | |
c5aa993b | 1353 | break; |
c906108c SS |
1354 | } |
1355 | default: | |
8e65ff28 AC |
1356 | internal_error (__FILE__, __LINE__, |
1357 | "bad switch"); | |
c906108c | 1358 | } |
12f02c2a AC |
1359 | upk->offset = offset; |
1360 | upk->regx = regx; | |
1361 | upk->regy = regy; | |
c906108c SS |
1362 | } |
1363 | ||
1364 | ||
c5aa993b JM |
1365 | static CORE_ADDR |
1366 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1367 | { |
c5aa993b | 1368 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1369 | } |
1370 | ||
12f02c2a AC |
1371 | static CORE_ADDR |
1372 | extended_mips16_next_pc (CORE_ADDR pc, | |
1373 | unsigned int extension, | |
1374 | unsigned int insn) | |
c906108c | 1375 | { |
12f02c2a AC |
1376 | int op = (insn >> 11); |
1377 | switch (op) | |
c906108c | 1378 | { |
12f02c2a AC |
1379 | case 2: /* Branch */ |
1380 | { | |
1381 | CORE_ADDR offset; | |
1382 | struct upk_mips16 upk; | |
1383 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1384 | offset = upk.offset; | |
1385 | if (offset & 0x800) | |
1386 | { | |
1387 | offset &= 0xeff; | |
1388 | offset = -offset; | |
1389 | } | |
1390 | pc += (offset << 1) + 2; | |
1391 | break; | |
1392 | } | |
1393 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1394 | { | |
1395 | struct upk_mips16 upk; | |
1396 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1397 | pc = add_offset_16 (pc, upk.offset); | |
1398 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1399 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1400 | else | |
1401 | pc |= 0x01; | |
1402 | break; | |
1403 | } | |
1404 | case 4: /* beqz */ | |
1405 | { | |
1406 | struct upk_mips16 upk; | |
1407 | int reg; | |
1408 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1409 | reg = read_signed_register (upk.regx); | |
1410 | if (reg == 0) | |
1411 | pc += (upk.offset << 1) + 2; | |
1412 | else | |
1413 | pc += 2; | |
1414 | break; | |
1415 | } | |
1416 | case 5: /* bnez */ | |
1417 | { | |
1418 | struct upk_mips16 upk; | |
1419 | int reg; | |
1420 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1421 | reg = read_signed_register (upk.regx); | |
1422 | if (reg != 0) | |
1423 | pc += (upk.offset << 1) + 2; | |
1424 | else | |
1425 | pc += 2; | |
1426 | break; | |
1427 | } | |
1428 | case 12: /* I8 Formats btez btnez */ | |
1429 | { | |
1430 | struct upk_mips16 upk; | |
1431 | int reg; | |
1432 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1433 | /* upk.regx contains the opcode */ | |
1434 | reg = read_signed_register (24); /* Test register is 24 */ | |
1435 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1436 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1437 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1438 | pc += (upk.offset << 1) + 2; | |
1439 | else | |
1440 | pc += 2; | |
1441 | break; | |
1442 | } | |
1443 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1444 | { | |
1445 | struct upk_mips16 upk; | |
1446 | /* upk.fmt = rrtype; */ | |
1447 | op = insn & 0x1f; | |
1448 | if (op == 0) | |
c5aa993b | 1449 | { |
12f02c2a AC |
1450 | int reg; |
1451 | upk.regx = (insn >> 8) & 0x07; | |
1452 | upk.regy = (insn >> 5) & 0x07; | |
1453 | switch (upk.regy) | |
c5aa993b | 1454 | { |
12f02c2a AC |
1455 | case 0: |
1456 | reg = upk.regx; | |
1457 | break; | |
1458 | case 1: | |
1459 | reg = 31; | |
1460 | break; /* Function return instruction */ | |
1461 | case 2: | |
1462 | reg = upk.regx; | |
1463 | break; | |
1464 | default: | |
1465 | reg = 31; | |
1466 | break; /* BOGUS Guess */ | |
c906108c | 1467 | } |
12f02c2a | 1468 | pc = read_signed_register (reg); |
c906108c | 1469 | } |
12f02c2a | 1470 | else |
c5aa993b | 1471 | pc += 2; |
12f02c2a AC |
1472 | break; |
1473 | } | |
1474 | case 30: | |
1475 | /* This is an instruction extension. Fetch the real instruction | |
1476 | (which follows the extension) and decode things based on | |
1477 | that. */ | |
1478 | { | |
1479 | pc += 2; | |
1480 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1481 | break; | |
1482 | } | |
1483 | default: | |
1484 | { | |
1485 | pc += 2; | |
1486 | break; | |
1487 | } | |
c906108c | 1488 | } |
c5aa993b | 1489 | return pc; |
12f02c2a | 1490 | } |
c906108c | 1491 | |
5a89d8aa | 1492 | static CORE_ADDR |
12f02c2a AC |
1493 | mips16_next_pc (CORE_ADDR pc) |
1494 | { | |
1495 | unsigned int insn = fetch_mips_16 (pc); | |
1496 | return extended_mips16_next_pc (pc, 0, insn); | |
1497 | } | |
1498 | ||
1499 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1500 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1501 | It works by decoding the current instruction and predicting where a |
1502 | branch will go. This isnt hard because all the data is available. | |
1503 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1504 | CORE_ADDR |
1505 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1506 | { |
c5aa993b JM |
1507 | if (pc & 0x01) |
1508 | return mips16_next_pc (pc); | |
1509 | else | |
1510 | return mips32_next_pc (pc); | |
12f02c2a | 1511 | } |
c906108c | 1512 | |
e0f7ec59 AC |
1513 | /* Set up the 'saved_regs' array. This is a data structure containing |
1514 | the addresses on the stack where each register has been saved, for | |
1515 | each stack frame. Registers that have not been saved will have | |
1516 | zero here. The stack pointer register is special: rather than the | |
1517 | address where the stack register has been saved, | |
1518 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1519 | frame's stack register. */ | |
c906108c | 1520 | |
d28e01f4 | 1521 | static void |
acdb74a0 | 1522 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1523 | { |
1524 | int ireg; | |
c906108c SS |
1525 | /* r0 bit means kernel trap */ |
1526 | int kernel_trap; | |
1527 | /* What registers have been saved? Bitmasks. */ | |
1528 | unsigned long gen_mask, float_mask; | |
1529 | mips_extra_func_info_t proc_desc; | |
1530 | t_inst inst; | |
e0f7ec59 | 1531 | CORE_ADDR *saved_regs; |
c906108c | 1532 | |
1b1d3794 | 1533 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1534 | return; |
1535 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1536 | |
1537 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1538 | in a sigcontext structure somewhere on the stack. If the stack |
1539 | layout for sigtramp changes we might have to change these | |
1540 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1541 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1542 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1543 | above the sigtramp frame. */ | |
4246e332 | 1544 | #define SIGFRAME_BASE mips_regsize (current_gdbarch) |
c906108c | 1545 | /* FIXME! Are these correct?? */ |
4246e332 AC |
1546 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch)) |
1547 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch)) | |
c906108c | 1548 | #define SIGFRAME_FPREGSAVE_OFF \ |
4246e332 | 1549 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch)) |
c906108c SS |
1550 | #endif |
1551 | #ifndef SIGFRAME_REG_SIZE | |
e0f7ec59 | 1552 | /* FIXME! Is this correct?? */ |
4246e332 | 1553 | #define SIGFRAME_REG_SIZE mips_regsize (current_gdbarch) |
c906108c | 1554 | #endif |
5a203e44 | 1555 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1556 | { |
1557 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1558 | { | |
e0f7ec59 AC |
1559 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
1560 | + ireg * SIGFRAME_REG_SIZE); | |
1561 | set_reg_offset (saved_regs, ireg, reg_position); | |
c906108c SS |
1562 | } |
1563 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1564 | { | |
e0f7ec59 AC |
1565 | CORE_ADDR reg_position = (get_frame_base (fci) |
1566 | + SIGFRAME_FPREGSAVE_OFF | |
1567 | + ireg * SIGFRAME_REG_SIZE); | |
56cea623 | 1568 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
c906108c | 1569 | } |
e0f7ec59 AC |
1570 | |
1571 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1572 | /* SP_REGNUM, contains the value and not the address. */ | |
1573 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1574 | return; |
1575 | } | |
1576 | ||
da50a4b7 | 1577 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1578 | if (proc_desc == NULL) |
e0f7ec59 AC |
1579 | /* I'm not sure how/whether this can happen. Normally when we |
1580 | can't find a proc_desc, we "synthesize" one using | |
1581 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1582 | return; |
1583 | ||
c5aa993b JM |
1584 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1585 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1586 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1587 | |
e0f7ec59 AC |
1588 | if (/* In any frame other than the innermost or a frame interrupted |
1589 | by a signal, we assume that all registers have been saved. | |
1590 | This assumes that all register saves in a function happen | |
1591 | before the first function call. */ | |
11c02a10 AC |
1592 | (get_next_frame (fci) == NULL |
1593 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1594 | |
e0f7ec59 | 1595 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1596 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1597 | |
e0f7ec59 AC |
1598 | /* Don't bother unless we are inside a function prologue. |
1599 | Outside the prologue, we know where everything is. */ | |
c906108c | 1600 | |
50abf9e5 | 1601 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1602 | |
e0f7ec59 AC |
1603 | /* Not sure exactly what kernel_trap means, but if it means the |
1604 | kernel saves the registers without a prologue doing it, we | |
1605 | better not examine the prologue to see whether registers | |
1606 | have been saved yet. */ | |
c5aa993b | 1607 | && !kernel_trap) |
c906108c | 1608 | { |
e0f7ec59 AC |
1609 | /* We need to figure out whether the registers that the |
1610 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1611 | |
1612 | CORE_ADDR addr; | |
1613 | ||
1614 | /* Bitmasks; set if we have found a save for the register. */ | |
1615 | unsigned long gen_save_found = 0; | |
1616 | unsigned long float_save_found = 0; | |
1617 | int instlen; | |
1618 | ||
1619 | /* If the address is odd, assume this is MIPS16 code. */ | |
1620 | addr = PROC_LOW_ADDR (proc_desc); | |
1621 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1622 | ||
e0f7ec59 AC |
1623 | /* Scan through this function's instructions preceding the |
1624 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1625 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1626 | { |
1627 | inst = mips_fetch_instruction (addr); | |
1628 | if (pc_is_mips16 (addr)) | |
1629 | mips16_decode_reg_save (inst, &gen_save_found); | |
1630 | else | |
1631 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1632 | addr += instlen; | |
1633 | } | |
1634 | gen_mask = gen_save_found; | |
1635 | float_mask = float_save_found; | |
1636 | } | |
1637 | ||
e0f7ec59 AC |
1638 | /* Fill in the offsets for the registers which gen_mask says were |
1639 | saved. */ | |
1640 | { | |
1641 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1642 | + PROC_REG_OFFSET (proc_desc)); | |
1643 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1644 | if (gen_mask & 0x80000000) | |
1645 | { | |
1646 | set_reg_offset (saved_regs, ireg, reg_position); | |
1647 | reg_position -= MIPS_SAVED_REGSIZE; | |
1648 | } | |
1649 | } | |
c906108c | 1650 | |
e0f7ec59 AC |
1651 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1652 | order of that normally used by gcc. Therefore, we have to fetch | |
1653 | the first instruction of the function, and if it's an entry | |
1654 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1655 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1656 | { | |
1657 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1658 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1659 | /* entry */ | |
c906108c SS |
1660 | { |
1661 | int reg; | |
1662 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1663 | |
c906108c | 1664 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1665 | CORE_ADDR reg_position = (get_frame_base (fci) |
1666 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1667 | if (inst & 0x20) |
7a292a7a | 1668 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1669 | |
e0f7ec59 AC |
1670 | /* Check if the s0 and s1 registers were pushed on the |
1671 | stack. */ | |
c5aa993b | 1672 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1673 | { |
e0f7ec59 | 1674 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1675 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1676 | } |
1677 | } | |
1678 | } | |
1679 | ||
e0f7ec59 AC |
1680 | /* Fill in the offsets for the registers which float_mask says were |
1681 | saved. */ | |
1682 | { | |
1683 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1684 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1685 | |
e0f7ec59 AC |
1686 | /* Fill in the offsets for the float registers which float_mask |
1687 | says were saved. */ | |
1688 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1689 | if (float_mask & 0x80000000) | |
1690 | { | |
c57bb9fa AC |
1691 | if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1692 | { | |
1693 | /* On a big endian 32 bit ABI, floating point registers | |
1694 | are paired to form doubles such that the most | |
1695 | significant part is in $f[N+1] and the least | |
1696 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1697 | registers are also spilled as a pair and stored as a | |
1698 | double. | |
1699 | ||
1700 | When little-endian the least significant part is | |
1701 | stored first leading to the memory order $f[N] and | |
1702 | then $f[N+1]. | |
1703 | ||
ce2826aa | 1704 | Unfortunately, when big-endian the most significant |
c57bb9fa AC |
1705 | part of the double is stored first, and the least |
1706 | significant is stored second. This leads to the | |
1707 | registers being ordered in memory as firt $f[N+1] and | |
1708 | then $f[N]. | |
1709 | ||
1710 | For the big-endian case make certain that the | |
1711 | addresses point at the correct (swapped) locations | |
1712 | $f[N] and $f[N+1] pair (keep in mind that | |
1713 | reg_position is decremented each time through the | |
1714 | loop). */ | |
1715 | if ((ireg & 1)) | |
56cea623 | 1716 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1717 | reg_position - MIPS_SAVED_REGSIZE); |
1718 | else | |
56cea623 | 1719 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1720 | reg_position + MIPS_SAVED_REGSIZE); |
1721 | } | |
1722 | else | |
56cea623 | 1723 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
e0f7ec59 AC |
1724 | reg_position -= MIPS_SAVED_REGSIZE; |
1725 | } | |
c906108c | 1726 | |
e0f7ec59 AC |
1727 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1728 | } | |
d28e01f4 | 1729 | |
e0f7ec59 AC |
1730 | /* SP_REGNUM, contains the value and not the address. */ |
1731 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1732 | } |
1733 | ||
c906108c | 1734 | static CORE_ADDR |
acdb74a0 | 1735 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1736 | { |
a4b8ebc8 AC |
1737 | /* Always a pseudo. */ |
1738 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1739 | if (fi == NULL) |
c906108c | 1740 | { |
a4b8ebc8 AC |
1741 | LONGEST val; |
1742 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1743 | return val; | |
f796e4be | 1744 | } |
a4b8ebc8 AC |
1745 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1746 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1747 | In fact, it is so special that it can even only be fetched | |
1748 | using a raw register number! Once this code as been converted | |
1749 | to frame-unwind the problem goes away. */ | |
1750 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1751 | else |
a4b8ebc8 | 1752 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1753 | |
c906108c SS |
1754 | } |
1755 | ||
1756 | /* mips_addr_bits_remove - remove useless address bits */ | |
1757 | ||
875e1767 | 1758 | static CORE_ADDR |
acdb74a0 | 1759 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1760 | { |
8fa9cfa1 AC |
1761 | if (mips_mask_address_p () |
1762 | && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
1763 | /* This hack is a work-around for existing boards using PMON, the | |
1764 | simulator, and any other 64-bit targets that doesn't have true | |
1765 | 64-bit addressing. On these targets, the upper 32 bits of | |
1766 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1767 | likely to have been sign extended to all 1s by instruction | |
1768 | sequences that load 32-bit addresses. For example, a typical | |
1769 | piece of code that loads an address is this: | |
1770 | ||
1771 | lui $r2, <upper 16 bits> | |
1772 | ori $r2, <lower 16 bits> | |
1773 | ||
1774 | But the lui sign-extends the value such that the upper 32 bits | |
1775 | may be all 1s. The workaround is simply to mask off these | |
1776 | bits. In the future, gcc may be changed to support true 64-bit | |
1777 | addressing, and this masking will have to be disabled. */ | |
1778 | return addr &= 0xffffffffUL; | |
1779 | else | |
1780 | return addr; | |
c906108c SS |
1781 | } |
1782 | ||
9022177c DJ |
1783 | /* mips_software_single_step() is called just before we want to resume |
1784 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1785 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1786 | the target of the coming instruction and breakpoint it. |
1787 | ||
1788 | single_step is also called just after the inferior stops. If we had | |
1789 | set up a simulated single-step, we undo our damage. */ | |
1790 | ||
1791 | void | |
1792 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1793 | { | |
1794 | static CORE_ADDR next_pc; | |
1795 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1796 | static binsn_quantum break_mem; | |
1797 | CORE_ADDR pc; | |
1798 | ||
1799 | if (insert_breakpoints_p) | |
1800 | { | |
1801 | pc = read_register (PC_REGNUM); | |
1802 | next_pc = mips_next_pc (pc); | |
1803 | ||
1804 | target_insert_breakpoint (next_pc, break_mem); | |
1805 | } | |
1806 | else | |
1807 | target_remove_breakpoint (next_pc, break_mem); | |
1808 | } | |
1809 | ||
97f46953 | 1810 | static CORE_ADDR |
acdb74a0 | 1811 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1812 | { |
1813 | CORE_ADDR pc, tmp; | |
1814 | ||
11c02a10 | 1815 | pc = ((fromleaf) |
6913c89a | 1816 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1817 | : get_next_frame (prev) |
8bedc050 | 1818 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1819 | : read_pc ()); |
5a89d8aa | 1820 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1821 | return tmp ? tmp : pc; |
c906108c SS |
1822 | } |
1823 | ||
1824 | ||
f7ab6ec6 | 1825 | static CORE_ADDR |
acdb74a0 | 1826 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1827 | { |
1828 | CORE_ADDR saved_pc; | |
c906108c | 1829 | |
50abf9e5 | 1830 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
1831 | { |
1832 | LONGEST tmp; | |
a4b8ebc8 AC |
1833 | /* Always unwind the cooked PC register value. */ |
1834 | frame_unwind_signed_register (frame, NUM_REGS + PC_REGNUM, &tmp); | |
cedea778 AC |
1835 | saved_pc = tmp; |
1836 | } | |
c906108c | 1837 | else |
a4b8ebc8 AC |
1838 | { |
1839 | mips_extra_func_info_t proc_desc | |
1840 | = get_frame_extra_info (frame)->proc_desc; | |
1841 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1842 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); | |
1843 | else | |
1844 | { | |
1845 | /* We have to get the saved pc from the sigcontext if it is | |
1846 | a signal handler frame. */ | |
1847 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM | |
1848 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); | |
1849 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1850 | } | |
1851 | } | |
c906108c SS |
1852 | return ADDR_BITS_REMOVE (saved_pc); |
1853 | } | |
1854 | ||
1855 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1856 | |
1857 | /* This hack will go away once the get_prev_frame() code has been | |
1858 | modified to set the frame's type first. That is BEFORE init extra | |
1859 | frame info et.al. is called. This is because it will become | |
1860 | possible to skip the init extra info call for sigtramp and dummy | |
1861 | frames. */ | |
1862 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1863 | |
e0f7ec59 AC |
1864 | /* Set a register's saved stack address in temp_saved_regs. If an |
1865 | address has already been set for this register, do nothing; this | |
1866 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1867 | function prologue. |
1868 | ||
1869 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1870 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1871 | is used as it is only second range (the ABI instead of ISA | |
1872 | registers) that comes into play when finding saved registers in a | |
1873 | frame. */ | |
c906108c SS |
1874 | |
1875 | static void | |
e0f7ec59 | 1876 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1877 | { |
e0f7ec59 | 1878 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1879 | { |
1880 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1881 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1882 | } | |
c906108c SS |
1883 | } |
1884 | ||
1885 | ||
1886 | /* Test whether the PC points to the return instruction at the | |
1887 | end of a function. */ | |
1888 | ||
c5aa993b | 1889 | static int |
acdb74a0 | 1890 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1891 | { |
1892 | if (pc_is_mips16 (pc)) | |
1893 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1894 | generates a "jr $ra"; other times it generates code to load | |
1895 | the return address from the stack to an accessible register (such | |
1896 | as $a3), then a "jr" using that register. This second case | |
1897 | is almost impossible to distinguish from an indirect jump | |
1898 | used for switch statements, so we don't even try. */ | |
1899 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1900 | else | |
1901 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1902 | } | |
1903 | ||
1904 | ||
1905 | /* This fencepost looks highly suspicious to me. Removing it also | |
1906 | seems suspicious as it could affect remote debugging across serial | |
1907 | lines. */ | |
1908 | ||
1909 | static CORE_ADDR | |
acdb74a0 | 1910 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1911 | { |
c5aa993b JM |
1912 | CORE_ADDR start_pc; |
1913 | CORE_ADDR fence; | |
1914 | int instlen; | |
1915 | int seen_adjsp = 0; | |
c906108c | 1916 | |
c5aa993b JM |
1917 | pc = ADDR_BITS_REMOVE (pc); |
1918 | start_pc = pc; | |
1919 | fence = start_pc - heuristic_fence_post; | |
1920 | if (start_pc == 0) | |
1921 | return 0; | |
c906108c | 1922 | |
c5aa993b JM |
1923 | if (heuristic_fence_post == UINT_MAX |
1924 | || fence < VM_MIN_ADDRESS) | |
1925 | fence = VM_MIN_ADDRESS; | |
c906108c | 1926 | |
c5aa993b | 1927 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1928 | |
c5aa993b JM |
1929 | /* search back for previous return */ |
1930 | for (start_pc -= instlen;; start_pc -= instlen) | |
1931 | if (start_pc < fence) | |
1932 | { | |
1933 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1934 | stop_soon, but with this test, at least we |
c5aa993b JM |
1935 | don't print out warnings for every child forked (eg, on |
1936 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1937 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1938 | { |
c5aa993b JM |
1939 | static int blurb_printed = 0; |
1940 | ||
1941 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1942 | paddr_nz (pc)); | |
1943 | ||
1944 | if (!blurb_printed) | |
c906108c | 1945 | { |
c5aa993b JM |
1946 | /* This actually happens frequently in embedded |
1947 | development, when you first connect to a board | |
1948 | and your stack pointer and pc are nowhere in | |
1949 | particular. This message needs to give people | |
1950 | in that situation enough information to | |
1951 | determine that it's no big deal. */ | |
1952 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1953 | GDB is unable to find the start of the function at 0x%s\n\ |
1954 | and thus can't determine the size of that function's stack frame.\n\ | |
1955 | This means that GDB may be unable to access that stack frame, or\n\ | |
1956 | the frames below it.\n\ | |
1957 | This problem is most likely caused by an invalid program counter or\n\ | |
1958 | stack pointer.\n\ | |
1959 | However, if you think GDB should simply search farther back\n\ | |
1960 | from 0x%s for code which looks like the beginning of a\n\ | |
1961 | function, you can increase the range of the search using the `set\n\ | |
1962 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1963 | paddr_nz (pc), paddr_nz (pc)); |
1964 | blurb_printed = 1; | |
c906108c | 1965 | } |
c906108c SS |
1966 | } |
1967 | ||
c5aa993b JM |
1968 | return 0; |
1969 | } | |
1970 | else if (pc_is_mips16 (start_pc)) | |
1971 | { | |
1972 | unsigned short inst; | |
1973 | ||
1974 | /* On MIPS16, any one of the following is likely to be the | |
1975 | start of a function: | |
1976 | entry | |
1977 | addiu sp,-n | |
1978 | daddiu sp,-n | |
1979 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1980 | inst = mips_fetch_instruction (start_pc); | |
1981 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1982 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1983 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1984 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1985 | break; | |
1986 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1987 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1988 | seen_adjsp = 1; | |
1989 | else | |
1990 | seen_adjsp = 0; | |
1991 | } | |
1992 | else if (mips_about_to_return (start_pc)) | |
1993 | { | |
1994 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1995 | break; | |
1996 | } | |
1997 | ||
c5aa993b | 1998 | return start_pc; |
c906108c SS |
1999 | } |
2000 | ||
2001 | /* Fetch the immediate value from a MIPS16 instruction. | |
2002 | If the previous instruction was an EXTEND, use it to extend | |
2003 | the upper bits of the immediate value. This is a helper function | |
2004 | for mips16_heuristic_proc_desc. */ | |
2005 | ||
2006 | static int | |
acdb74a0 AC |
2007 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
2008 | unsigned short inst, /* current instruction */ | |
2009 | int nbits, /* number of bits in imm field */ | |
2010 | int scale, /* scale factor to be applied to imm */ | |
2011 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
2012 | { |
2013 | int offset; | |
2014 | ||
2015 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
2016 | { | |
2017 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 2018 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
2019 | offset = 0 - (0x10000 - (offset & 0xffff)); |
2020 | return offset | (inst & 0x1f); | |
2021 | } | |
2022 | else | |
2023 | { | |
2024 | int max_imm = 1 << nbits; | |
2025 | int mask = max_imm - 1; | |
2026 | int sign_bit = max_imm >> 1; | |
2027 | ||
2028 | offset = inst & mask; | |
2029 | if (is_signed && (offset & sign_bit)) | |
2030 | offset = 0 - (max_imm - offset); | |
2031 | return offset * scale; | |
2032 | } | |
2033 | } | |
2034 | ||
2035 | ||
2036 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
2037 | stream from start_pc to limit_pc. */ | |
2038 | ||
2039 | static void | |
acdb74a0 AC |
2040 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2041 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2042 | { |
2043 | CORE_ADDR cur_pc; | |
2044 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
2045 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
2046 | unsigned inst = 0; /* current instruction */ | |
2047 | unsigned entry_inst = 0; /* the entry instruction */ | |
2048 | int reg, offset; | |
2049 | ||
c5aa993b JM |
2050 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
2051 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2052 | |
2053 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2054 | { | |
2055 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2056 | the immediate offset extension from it in mips16_get_imm. */ | |
2057 | prev_inst = inst; | |
2058 | ||
2059 | /* Fetch and decode the instruction. */ | |
2060 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2061 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
2062 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
2063 | { | |
2064 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2065 | if (offset < 0) /* negative stack adjustment? */ |
2066 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2067 | else |
2068 | /* Exit loop if a positive stack adjustment is found, which | |
2069 | usually means that the stack cleanup code in the function | |
2070 | epilogue is reached. */ | |
2071 | break; | |
2072 | } | |
2073 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2074 | { | |
2075 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2076 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2077 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2078 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2079 | } |
2080 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2081 | { | |
2082 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2083 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2084 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2085 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2086 | } |
2087 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2088 | { | |
2089 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2090 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2091 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2092 | } |
2093 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2094 | { | |
2095 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2096 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2097 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2098 | } |
c5aa993b | 2099 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2100 | { |
2101 | frame_addr = sp; | |
2102 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2103 | } | |
2104 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2105 | { | |
2106 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2107 | frame_addr = sp + offset; | |
2108 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2109 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2110 | } | |
2111 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2112 | { | |
2113 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2114 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2115 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2116 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2117 | } |
2118 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2119 | { | |
2120 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2121 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2122 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2123 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2124 | } |
c5aa993b JM |
2125 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2126 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2127 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2128 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2129 | } |
2130 | ||
c5aa993b JM |
2131 | /* The entry instruction is typically the first instruction in a function, |
2132 | and it stores registers at offsets relative to the value of the old SP | |
2133 | (before the prologue). But the value of the sp parameter to this | |
2134 | function is the new SP (after the prologue has been executed). So we | |
2135 | can't calculate those offsets until we've seen the entire prologue, | |
2136 | and can calculate what the old SP must have been. */ | |
2137 | if (entry_inst != 0) | |
2138 | { | |
2139 | int areg_count = (entry_inst >> 8) & 7; | |
2140 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2141 | |
c5aa993b JM |
2142 | /* The entry instruction always subtracts 32 from the SP. */ |
2143 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2144 | |
c5aa993b JM |
2145 | /* Now we can calculate what the SP must have been at the |
2146 | start of the function prologue. */ | |
2147 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2148 | |
c5aa993b JM |
2149 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2150 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2151 | { | |
2152 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2153 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2154 | offset += MIPS_SAVED_REGSIZE; |
2155 | } | |
c906108c | 2156 | |
c5aa993b JM |
2157 | /* Check if the ra register was pushed on the stack. */ |
2158 | offset = -4; | |
2159 | if (entry_inst & 0x20) | |
2160 | { | |
2161 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2162 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2163 | offset -= MIPS_SAVED_REGSIZE; |
2164 | } | |
c906108c | 2165 | |
c5aa993b JM |
2166 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2167 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2168 | { | |
2169 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2170 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2171 | offset -= MIPS_SAVED_REGSIZE; |
2172 | } | |
2173 | } | |
c906108c SS |
2174 | } |
2175 | ||
2176 | static void | |
fba45db2 KB |
2177 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2178 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2179 | { |
2180 | CORE_ADDR cur_pc; | |
c5aa993b | 2181 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2182 | restart: |
fe29b929 | 2183 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2184 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2185 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2186 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2187 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2188 | { | |
2189 | unsigned long inst, high_word, low_word; | |
2190 | int reg; | |
2191 | ||
2192 | /* Fetch the instruction. */ | |
2193 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2194 | ||
2195 | /* Save some code by pre-extracting some useful fields. */ | |
2196 | high_word = (inst >> 16) & 0xffff; | |
2197 | low_word = inst & 0xffff; | |
2198 | reg = high_word & 0x1f; | |
2199 | ||
c5aa993b | 2200 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2201 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2202 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2203 | { | |
2204 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2205 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2206 | else |
2207 | /* Exit loop if a positive stack adjustment is found, which | |
2208 | usually means that the stack cleanup code in the function | |
2209 | epilogue is reached. */ | |
2210 | break; | |
2211 | } | |
2212 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2213 | { | |
c5aa993b | 2214 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2215 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2216 | } |
2217 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2218 | { | |
2219 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2220 | but the register size used is only 32 bits. Make the address | |
2221 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2222 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
4246e332 | 2223 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch)); |
c906108c | 2224 | } |
c5aa993b | 2225 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2226 | { |
2227 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2228 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2229 | frame_addr = sp + low_word; | |
c906108c SS |
2230 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2231 | { | |
2232 | unsigned alloca_adjust; | |
2233 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2234 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2235 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2236 | if (alloca_adjust > 0) |
2237 | { | |
2238 | /* FP > SP + frame_size. This may be because | |
2239 | * of an alloca or somethings similar. | |
2240 | * Fix sp to "pre-alloca" value, and try again. | |
2241 | */ | |
2242 | sp += alloca_adjust; | |
2243 | goto restart; | |
2244 | } | |
2245 | } | |
2246 | } | |
c5aa993b JM |
2247 | /* move $30,$sp. With different versions of gas this will be either |
2248 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2249 | Accept any one of these. */ | |
c906108c SS |
2250 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2251 | { | |
2252 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2253 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2254 | { | |
2255 | unsigned alloca_adjust; | |
2256 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2257 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2258 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2259 | if (alloca_adjust > 0) |
2260 | { | |
2261 | /* FP > SP + frame_size. This may be because | |
2262 | * of an alloca or somethings similar. | |
2263 | * Fix sp to "pre-alloca" value, and try again. | |
2264 | */ | |
2265 | sp += alloca_adjust; | |
2266 | goto restart; | |
2267 | } | |
2268 | } | |
2269 | } | |
c5aa993b | 2270 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2271 | { |
c5aa993b | 2272 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2273 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2274 | } |
2275 | } | |
2276 | } | |
2277 | ||
2278 | static mips_extra_func_info_t | |
acdb74a0 | 2279 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2280 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2281 | { |
479412cd DJ |
2282 | CORE_ADDR sp; |
2283 | ||
2284 | if (cur_frame) | |
a4b8ebc8 | 2285 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2286 | else |
2287 | sp = 0; | |
c906108c | 2288 | |
c5aa993b JM |
2289 | if (start_pc == 0) |
2290 | return NULL; | |
2291 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2292 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2293 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2294 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2295 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2296 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2297 | ||
2298 | if (start_pc + 200 < limit_pc) | |
2299 | limit_pc = start_pc + 200; | |
2300 | if (pc_is_mips16 (start_pc)) | |
2301 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2302 | else | |
2303 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2304 | return &temp_proc_desc; | |
2305 | } | |
2306 | ||
6c0d6680 DJ |
2307 | struct mips_objfile_private |
2308 | { | |
2309 | bfd_size_type size; | |
2310 | char *contents; | |
2311 | }; | |
2312 | ||
2313 | /* Global used to communicate between non_heuristic_proc_desc and | |
2314 | compare_pdr_entries within qsort (). */ | |
2315 | static bfd *the_bfd; | |
2316 | ||
2317 | static int | |
2318 | compare_pdr_entries (const void *a, const void *b) | |
2319 | { | |
2320 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2321 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2322 | ||
2323 | if (lhs < rhs) | |
2324 | return -1; | |
2325 | else if (lhs == rhs) | |
2326 | return 0; | |
2327 | else | |
2328 | return 1; | |
2329 | } | |
2330 | ||
c906108c | 2331 | static mips_extra_func_info_t |
acdb74a0 | 2332 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2333 | { |
2334 | CORE_ADDR startaddr; | |
2335 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2336 | struct block *b = block_for_pc (pc); |
c906108c | 2337 | struct symbol *sym; |
6c0d6680 DJ |
2338 | struct obj_section *sec; |
2339 | struct mips_objfile_private *priv; | |
2340 | ||
ae45cd16 | 2341 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2342 | return NULL; |
c906108c SS |
2343 | |
2344 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2345 | if (addrptr) | |
2346 | *addrptr = startaddr; | |
6c0d6680 DJ |
2347 | |
2348 | priv = NULL; | |
2349 | ||
2350 | sec = find_pc_section (pc); | |
2351 | if (sec != NULL) | |
c906108c | 2352 | { |
6c0d6680 DJ |
2353 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2354 | ||
2355 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2356 | the information normally found in ECOFF PDRs. */ | |
2357 | ||
2358 | the_bfd = sec->objfile->obfd; | |
2359 | if (priv == NULL | |
2360 | && (the_bfd->format == bfd_object | |
2361 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2362 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2363 | { | |
2364 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2365 | This means that we should not bother with this method on 64-bit | |
2366 | targets (until that is fixed). */ | |
2367 | ||
2368 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2369 | sizeof (struct mips_objfile_private)); | |
2370 | priv->size = 0; | |
2371 | sec->objfile->obj_private = priv; | |
2372 | } | |
2373 | else if (priv == NULL) | |
2374 | { | |
2375 | asection *bfdsec; | |
2376 | ||
2377 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2378 | sizeof (struct mips_objfile_private)); | |
2379 | ||
2380 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2381 | if (bfdsec != NULL) | |
2382 | { | |
2383 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2384 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2385 | priv->size); | |
2386 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2387 | priv->contents, 0, priv->size); | |
2388 | ||
2389 | /* In general, the .pdr section is sorted. However, in the | |
2390 | presence of multiple code sections (and other corner cases) | |
2391 | it can become unsorted. Sort it so that we can use a faster | |
2392 | binary search. */ | |
2393 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2394 | } | |
2395 | else | |
2396 | priv->size = 0; | |
2397 | ||
2398 | sec->objfile->obj_private = priv; | |
2399 | } | |
2400 | the_bfd = NULL; | |
2401 | ||
2402 | if (priv->size != 0) | |
2403 | { | |
2404 | int low, mid, high; | |
2405 | char *ptr; | |
2406 | ||
2407 | low = 0; | |
2408 | high = priv->size / 32; | |
2409 | ||
2410 | do | |
2411 | { | |
2412 | CORE_ADDR pdr_pc; | |
2413 | ||
2414 | mid = (low + high) / 2; | |
2415 | ||
2416 | ptr = priv->contents + mid * 32; | |
2417 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2418 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2419 | SECT_OFF_TEXT (sec->objfile)); | |
2420 | if (pdr_pc == startaddr) | |
2421 | break; | |
2422 | if (pdr_pc > startaddr) | |
2423 | high = mid; | |
2424 | else | |
2425 | low = mid + 1; | |
2426 | } | |
2427 | while (low != high); | |
2428 | ||
2429 | if (low != high) | |
2430 | { | |
2431 | struct symbol *sym = find_pc_function (pc); | |
2432 | ||
2433 | /* Fill in what we need of the proc_desc. */ | |
2434 | proc_desc = (mips_extra_func_info_t) | |
2435 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2436 | sizeof (struct mips_extra_func_info)); | |
2437 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2438 | ||
2439 | /* Only used for dummy frames. */ | |
2440 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2441 | ||
2442 | PROC_FRAME_OFFSET (proc_desc) | |
2443 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2444 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2445 | ptr + 24); | |
2446 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2447 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2448 | ptr + 4); | |
2449 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2450 | ptr + 12); | |
2451 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2452 | ptr + 8); | |
2453 | PROC_FREG_OFFSET (proc_desc) | |
2454 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2455 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2456 | ptr + 28); | |
2457 | proc_desc->pdr.isym = (long) sym; | |
2458 | ||
2459 | return proc_desc; | |
2460 | } | |
2461 | } | |
c906108c SS |
2462 | } |
2463 | ||
6c0d6680 DJ |
2464 | if (b == NULL) |
2465 | return NULL; | |
2466 | ||
2467 | if (startaddr > BLOCK_START (b)) | |
2468 | { | |
2469 | /* This is the "pathological" case referred to in a comment in | |
2470 | print_frame_info. It might be better to move this check into | |
2471 | symbol reading. */ | |
2472 | return NULL; | |
2473 | } | |
2474 | ||
176620f1 | 2475 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2476 | |
c906108c SS |
2477 | /* If we never found a PDR for this function in symbol reading, then |
2478 | examine prologues to find the information. */ | |
2479 | if (sym) | |
2480 | { | |
2481 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2482 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2483 | return NULL; | |
2484 | else | |
2485 | return proc_desc; | |
2486 | } | |
2487 | else | |
2488 | return NULL; | |
2489 | } | |
2490 | ||
2491 | ||
2492 | static mips_extra_func_info_t | |
479412cd | 2493 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2494 | { |
2495 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2496 | CORE_ADDR startaddr = 0; |
c906108c SS |
2497 | |
2498 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2499 | ||
2500 | if (proc_desc) | |
2501 | { | |
2502 | /* IF this is the topmost frame AND | |
2503 | * (this proc does not have debugging information OR | |
2504 | * the PC is in the procedure prologue) | |
2505 | * THEN create a "heuristic" proc_desc (by analyzing | |
2506 | * the actual code) to replace the "official" proc_desc. | |
2507 | */ | |
2508 | if (next_frame == NULL) | |
2509 | { | |
2510 | struct symtab_and_line val; | |
2511 | struct symbol *proc_symbol = | |
c86b5b38 | 2512 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2513 | |
2514 | if (proc_symbol) | |
2515 | { | |
2516 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2517 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2518 | 0); |
2519 | val.pc = val.end ? val.end : pc; | |
2520 | } | |
2521 | if (!proc_symbol || pc < val.pc) | |
2522 | { | |
2523 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2524 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2525 | pc, next_frame, cur_frame); | |
c906108c SS |
2526 | if (found_heuristic) |
2527 | proc_desc = found_heuristic; | |
2528 | } | |
2529 | } | |
2530 | } | |
2531 | else | |
2532 | { | |
2533 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2534 | by procedure call dummys. However, the procedures being called ought |
2535 | to have their own proc_descs, and even if they don't, | |
2536 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2537 | |
aa1ee363 | 2538 | struct linked_proc_info *link; |
c906108c SS |
2539 | |
2540 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2541 | if (PROC_LOW_ADDR (&link->info) <= pc |
2542 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2543 | return &link->info; |
2544 | ||
2545 | if (startaddr == 0) | |
2546 | startaddr = heuristic_proc_start (pc); | |
2547 | ||
2548 | proc_desc = | |
479412cd | 2549 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2550 | } |
2551 | return proc_desc; | |
2552 | } | |
2553 | ||
2554 | static CORE_ADDR | |
acdb74a0 AC |
2555 | get_frame_pointer (struct frame_info *frame, |
2556 | mips_extra_func_info_t proc_desc) | |
c906108c | 2557 | { |
a4b8ebc8 | 2558 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
e227b13c AC |
2559 | + PROC_FRAME_OFFSET (proc_desc) |
2560 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2561 | } |
2562 | ||
5a89d8aa | 2563 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2564 | |
f7ab6ec6 | 2565 | static CORE_ADDR |
acdb74a0 | 2566 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2567 | { |
2568 | mips_extra_func_info_t proc_desc; | |
2569 | CORE_ADDR tmp; | |
8bedc050 | 2570 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2571 | |
627b3ba2 | 2572 | if (saved_pc == 0 || deprecated_inside_entry_file (saved_pc)) |
c906108c SS |
2573 | return 0; |
2574 | ||
2575 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2576 | PC of the caller of that stub. */ | |
5a89d8aa | 2577 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2578 | saved_pc = tmp; |
2579 | ||
ae45cd16 | 2580 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2581 | { |
2582 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2583 | is well, frame->frame the bottom of the current frame will | |
2584 | contain that value. */ | |
1e2330ba | 2585 | return get_frame_base (frame); |
cedea778 AC |
2586 | } |
2587 | ||
c906108c | 2588 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2589 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2590 | if (!proc_desc) |
2591 | return 0; | |
2592 | ||
2593 | cached_proc_desc = proc_desc; | |
2594 | ||
2595 | /* If no frame pointer and frame size is zero, we must be at end | |
2596 | of stack (or otherwise hosed). If we don't check frame size, | |
2597 | we loop forever if we see a zero size frame. */ | |
2598 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2599 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2600 | /* The previous frame from a sigtramp frame might be frameless |
2601 | and have frame size zero. */ | |
5a203e44 | 2602 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2603 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2604 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2605 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2606 | return 0; |
2607 | else | |
2608 | return get_frame_pointer (frame, proc_desc); | |
2609 | } | |
2610 | ||
f7ab6ec6 | 2611 | static void |
acdb74a0 | 2612 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2613 | { |
2614 | int regnum; | |
f2c16bd6 KB |
2615 | mips_extra_func_info_t proc_desc; |
2616 | ||
2617 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2618 | return; | |
c906108c | 2619 | |
f796e4be KB |
2620 | /* Use proc_desc calculated in frame_chain. When there is no |
2621 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2622 | find_proc_desc () to calculate it, passing an explicit | |
2623 | NULL as the frame parameter. */ | |
f2c16bd6 | 2624 | proc_desc = |
11c02a10 AC |
2625 | get_next_frame (fci) |
2626 | ? cached_proc_desc | |
f796e4be KB |
2627 | : find_proc_desc (get_frame_pc (fci), |
2628 | NULL /* i.e, get_next_frame (fci) */, | |
2629 | 1); | |
c906108c | 2630 | |
a00a19e9 | 2631 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2632 | |
7b5849cc | 2633 | deprecated_set_frame_saved_regs_hack (fci, NULL); |
da50a4b7 | 2634 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2635 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2636 | if (proc_desc) | |
2637 | { | |
2638 | /* Fixup frame-pointer - only needed for top frame */ | |
2639 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2640 | Get the value of the frame relative sp, procedure might have been |
2641 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2642 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2643 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
a4b8ebc8 | 2644 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM)); |
50abf9e5 | 2645 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2646 | /* Do not ``fix'' fci->frame. It will have the value of the |
2647 | generic dummy frame's top-of-stack (since the draft | |
2648 | fci->frame is obtained by returning the unwound stack | |
2649 | pointer) and that is what we want. That way the fci->frame | |
2650 | value will match the top-of-stack value that was saved as | |
2651 | part of the dummy frames data. */ | |
2652 | /* Do nothing. */; | |
c906108c | 2653 | else |
11c02a10 | 2654 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2655 | |
2656 | if (proc_desc == &temp_proc_desc) | |
2657 | { | |
2658 | char *name; | |
2659 | ||
2660 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2661 | mips_find_saved_registers will do that for us. We can't |
2662 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2663 | yet set. */ | |
2664 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2665 | frame.c:get_prev_frame() is modified to set the frame's | |
2666 | type before calling functions like this. */ | |
50abf9e5 | 2667 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2668 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2669 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2670 | { |
c5aa993b | 2671 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2672 | /* Set value of previous frame's stack pointer. |
2673 | Remember that saved_regs[SP_REGNUM] is special in | |
2674 | that it contains the value of the stack pointer | |
2675 | register. The other saved_regs values are addresses | |
2676 | (in the inferior) at which a given register's value | |
2677 | may be found. */ | |
2678 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2679 | get_frame_base (fci)); | |
2680 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2681 | temp_saved_regs[RA_REGNUM]); | |
1b1d3794 | 2682 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2683 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2684 | } |
2685 | } | |
2686 | ||
2687 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2688 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2689 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2690 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2691 | { | |
c5aa993b | 2692 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2693 | { |
da50a4b7 | 2694 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2695 | break; |
2696 | } | |
c5aa993b | 2697 | } |
c906108c SS |
2698 | } |
2699 | } | |
2700 | ||
2701 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2702 | we basically have to look at symbol information for the function | |
2703 | that we stopped in, which tells us *which* register (if any) is | |
2704 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2705 | the frame itself is at. |
c906108c SS |
2706 | |
2707 | This presents a problem when trying to examine a stack in memory | |
2708 | (that isn't executing at the moment), using the "frame" command. We | |
2709 | don't have a PC, nor do we have any registers except SP. | |
2710 | ||
2711 | This routine takes two arguments, SP and PC, and tries to make the | |
2712 | cached frames look as if these two arguments defined a frame on the | |
2713 | cache. This allows the rest of info frame to extract the important | |
2714 | arguments without difficulty. */ | |
2715 | ||
2716 | struct frame_info * | |
acdb74a0 | 2717 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2718 | { |
2719 | if (argc != 2) | |
2720 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2721 | ||
2722 | return create_new_frame (argv[0], argv[1]); | |
2723 | } | |
2724 | ||
f09ded24 AC |
2725 | /* According to the current ABI, should the type be passed in a |
2726 | floating-point register (assuming that there is space)? When there | |
2727 | is no FPU, FP are not even considered as possibile candidates for | |
2728 | FP registers and, consequently this returns false - forces FP | |
2729 | arguments into integer registers. */ | |
2730 | ||
2731 | static int | |
2732 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2733 | { | |
2734 | return ((typecode == TYPE_CODE_FLT | |
2735 | || (MIPS_EABI | |
2736 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2737 | && TYPE_NFIELDS (arg_type) == 1 | |
2738 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2739 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2740 | } |
2741 | ||
49e790b0 DJ |
2742 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2743 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2744 | ||
2745 | static int | |
2746 | mips_type_needs_double_align (struct type *type) | |
2747 | { | |
2748 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2749 | |
49e790b0 DJ |
2750 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2751 | return 1; | |
2752 | else if (typecode == TYPE_CODE_STRUCT) | |
2753 | { | |
2754 | if (TYPE_NFIELDS (type) < 1) | |
2755 | return 0; | |
2756 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2757 | } | |
2758 | else if (typecode == TYPE_CODE_UNION) | |
2759 | { | |
361d1df0 | 2760 | int i, n; |
49e790b0 DJ |
2761 | |
2762 | n = TYPE_NFIELDS (type); | |
2763 | for (i = 0; i < n; i++) | |
2764 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2765 | return 1; | |
2766 | return 0; | |
2767 | } | |
2768 | return 0; | |
2769 | } | |
2770 | ||
dc604539 AC |
2771 | /* Adjust the address downward (direction of stack growth) so that it |
2772 | is correctly aligned for a new stack frame. */ | |
2773 | static CORE_ADDR | |
2774 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2775 | { | |
5b03f266 | 2776 | return align_down (addr, 16); |
dc604539 AC |
2777 | } |
2778 | ||
f7ab6ec6 | 2779 | static CORE_ADDR |
25ab4790 AC |
2780 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2781 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2782 | struct value **args, CORE_ADDR sp, int struct_return, | |
2783 | CORE_ADDR struct_addr) | |
c906108c SS |
2784 | { |
2785 | int argreg; | |
2786 | int float_argreg; | |
2787 | int argnum; | |
2788 | int len = 0; | |
2789 | int stack_offset = 0; | |
2790 | ||
25ab4790 AC |
2791 | /* For shared libraries, "t9" needs to point at the function |
2792 | address. */ | |
2793 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2794 | ||
2795 | /* Set the return address register to point to the entry point of | |
2796 | the program, where a breakpoint lies in wait. */ | |
2797 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2798 | ||
c906108c | 2799 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2800 | are properly aligned. The stack has to be at least 64-bit |
2801 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2802 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2803 | aligned, so we round to this widest known alignment. */ | |
2804 | ||
5b03f266 AC |
2805 | sp = align_down (sp, 16); |
2806 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2807 | |
46e0f506 | 2808 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2809 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2810 | passed in registers, but that's OK. */ |
c906108c | 2811 | for (argnum = 0; argnum < nargs; argnum++) |
5b03f266 | 2812 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46e0f506 | 2813 | MIPS_STACK_ARGSIZE); |
5b03f266 | 2814 | sp -= align_up (len, 16); |
c906108c | 2815 | |
9ace0497 | 2816 | if (mips_debug) |
46e0f506 | 2817 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2818 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2819 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2820 | |
c906108c SS |
2821 | /* Initialize the integer and float register pointers. */ |
2822 | argreg = A0_REGNUM; | |
56cea623 | 2823 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2824 | |
46e0f506 | 2825 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2826 | if (struct_return) |
9ace0497 AC |
2827 | { |
2828 | if (mips_debug) | |
2829 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2830 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2831 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2832 | write_register (argreg++, struct_addr); |
2833 | } | |
c906108c SS |
2834 | |
2835 | /* Now load as many as possible of the first arguments into | |
2836 | registers, and push the rest onto the stack. Loop thru args | |
2837 | from first to last. */ | |
2838 | for (argnum = 0; argnum < nargs; argnum++) | |
2839 | { | |
2840 | char *val; | |
d9d9c31f | 2841 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2842 | struct value *arg = args[argnum]; |
c906108c SS |
2843 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2844 | int len = TYPE_LENGTH (arg_type); | |
2845 | enum type_code typecode = TYPE_CODE (arg_type); | |
2846 | ||
9ace0497 AC |
2847 | if (mips_debug) |
2848 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2849 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2850 | argnum + 1, len, (int) typecode); |
9ace0497 | 2851 | |
c906108c | 2852 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2853 | reference. */ |
2854 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2855 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2856 | { |
fbd9dcd3 | 2857 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2858 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2859 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2860 | val = valbuf; |
9ace0497 AC |
2861 | if (mips_debug) |
2862 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2863 | } |
2864 | else | |
c5aa993b | 2865 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2866 | |
2867 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2868 | even-numbered floating point register. Round the FP register |
2869 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2870 | left. Non MIPS_EABI targets also pass the FP in the integer |
2871 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2872 | if (!FP_REGISTER_DOUBLE |
2873 | && fp_register_arg_p (typecode, arg_type)) | |
2874 | { | |
2875 | if ((float_argreg & 1)) | |
2876 | float_argreg++; | |
2877 | } | |
c906108c SS |
2878 | |
2879 | /* Floating point arguments passed in registers have to be | |
2880 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2881 | are passed in register pairs; the even register gets |
2882 | the low word, and the odd register gets the high word. | |
2883 | On non-EABI processors, the first two floating point arguments are | |
2884 | also copied to general registers, because MIPS16 functions | |
2885 | don't use float registers for arguments. This duplication of | |
2886 | arguments in general registers can't hurt non-MIPS16 functions | |
2887 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2888 | /* MIPS_EABI squeezes a struct that contains a single floating |
2889 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2890 | stack. */ |
f09ded24 AC |
2891 | if (fp_register_arg_p (typecode, arg_type) |
2892 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2893 | { |
2894 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2895 | { | |
d7449b42 | 2896 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2897 | unsigned long regval; |
2898 | ||
2899 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2900 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2901 | if (mips_debug) |
acdb74a0 | 2902 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2903 | float_argreg, phex (regval, 4)); |
c906108c | 2904 | write_register (float_argreg++, regval); |
c906108c SS |
2905 | |
2906 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2907 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2908 | if (mips_debug) |
acdb74a0 | 2909 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2910 | float_argreg, phex (regval, 4)); |
c906108c | 2911 | write_register (float_argreg++, regval); |
c906108c SS |
2912 | } |
2913 | else | |
2914 | { | |
2915 | /* This is a floating point value that fits entirely | |
2916 | in a single register. */ | |
53a5351d | 2917 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2918 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2919 | LONGEST regval = extract_unsigned_integer (val, len); |
2920 | if (mips_debug) | |
acdb74a0 | 2921 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2922 | float_argreg, phex (regval, len)); |
c906108c | 2923 | write_register (float_argreg++, regval); |
c906108c SS |
2924 | } |
2925 | } | |
2926 | else | |
2927 | { | |
2928 | /* Copy the argument to general registers or the stack in | |
2929 | register-sized pieces. Large arguments are split between | |
2930 | registers and stack. */ | |
4246e332 AC |
2931 | /* Note: structs whose size is not a multiple of |
2932 | mips_regsize() are treated specially: Irix cc passes them | |
2933 | in registers where gcc sometimes puts them on the stack. | |
2934 | For maximum compatibility, we will put them in both | |
2935 | places. */ | |
c5aa993b | 2936 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2937 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2938 | |
f09ded24 | 2939 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2940 | register are only written to memory. */ |
c906108c SS |
2941 | while (len > 0) |
2942 | { | |
ebafbe83 | 2943 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2944 | int stack_used_p = 0; |
46e0f506 MS |
2945 | int partial_len = |
2946 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2947 | |
acdb74a0 AC |
2948 | if (mips_debug) |
2949 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2950 | partial_len); | |
2951 | ||
566f0f7a | 2952 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2953 | if (argreg > MIPS_LAST_ARG_REGNUM |
2954 | || odd_sized_struct | |
2955 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2956 | { |
c906108c SS |
2957 | /* Should shorter than int integer values be |
2958 | promoted to int before being stored? */ | |
c906108c | 2959 | int longword_offset = 0; |
9ace0497 | 2960 | CORE_ADDR addr; |
566f0f7a | 2961 | stack_used_p = 1; |
d7449b42 | 2962 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2963 | { |
d929b26f | 2964 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2965 | (typecode == TYPE_CODE_INT || |
2966 | typecode == TYPE_CODE_PTR || | |
2967 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2968 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2969 | else if ((typecode == TYPE_CODE_STRUCT || |
2970 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2971 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2972 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2973 | } |
c5aa993b | 2974 | |
9ace0497 AC |
2975 | if (mips_debug) |
2976 | { | |
cb3d25d1 MS |
2977 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2978 | paddr_nz (stack_offset)); | |
2979 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2980 | paddr_nz (longword_offset)); | |
9ace0497 | 2981 | } |
361d1df0 | 2982 | |
9ace0497 AC |
2983 | addr = sp + stack_offset + longword_offset; |
2984 | ||
2985 | if (mips_debug) | |
2986 | { | |
2987 | int i; | |
cb3d25d1 MS |
2988 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2989 | paddr_nz (addr)); | |
9ace0497 AC |
2990 | for (i = 0; i < partial_len; i++) |
2991 | { | |
cb3d25d1 MS |
2992 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2993 | val[i] & 0xff); | |
9ace0497 AC |
2994 | } |
2995 | } | |
2996 | write_memory (addr, val, partial_len); | |
c906108c SS |
2997 | } |
2998 | ||
f09ded24 AC |
2999 | /* Note!!! This is NOT an else clause. Odd sized |
3000 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3001 | arguments will not. */ |
566f0f7a | 3002 | /* Write this portion of the argument to a general |
46e0f506 | 3003 | purpose register. */ |
f09ded24 AC |
3004 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3005 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3006 | { |
9ace0497 | 3007 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 3008 | |
9ace0497 | 3009 | if (mips_debug) |
acdb74a0 | 3010 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
3011 | argreg, |
3012 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
3013 | write_register (argreg, regval); |
3014 | argreg++; | |
c906108c | 3015 | } |
c5aa993b | 3016 | |
c906108c SS |
3017 | len -= partial_len; |
3018 | val += partial_len; | |
3019 | ||
566f0f7a AC |
3020 | /* Compute the the offset into the stack at which we |
3021 | will copy the next parameter. | |
3022 | ||
566f0f7a | 3023 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3024 | only needs to be adjusted when it has been used. */ |
c906108c | 3025 | |
46e0f506 | 3026 | if (stack_used_p) |
5b03f266 | 3027 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
3028 | } |
3029 | } | |
9ace0497 AC |
3030 | if (mips_debug) |
3031 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3032 | } |
3033 | ||
310e9b6a AC |
3034 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3035 | ||
0f71a2f6 JM |
3036 | /* Return adjusted stack pointer. */ |
3037 | return sp; | |
3038 | } | |
3039 | ||
25ab4790 | 3040 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 3041 | |
f7ab6ec6 | 3042 | static CORE_ADDR |
25ab4790 AC |
3043 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3044 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3045 | struct value **args, CORE_ADDR sp, int struct_return, | |
3046 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3047 | { |
3048 | int argreg; | |
3049 | int float_argreg; | |
3050 | int argnum; | |
3051 | int len = 0; | |
3052 | int stack_offset = 0; | |
3053 | ||
25ab4790 AC |
3054 | /* For shared libraries, "t9" needs to point at the function |
3055 | address. */ | |
3056 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3057 | ||
3058 | /* Set the return address register to point to the entry point of | |
3059 | the program, where a breakpoint lies in wait. */ | |
3060 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3061 | ||
cb3d25d1 MS |
3062 | /* First ensure that the stack and structure return address (if any) |
3063 | are properly aligned. The stack has to be at least 64-bit | |
3064 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3065 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3066 | aligned, so we round to this widest known alignment. */ | |
3067 | ||
5b03f266 AC |
3068 | sp = align_down (sp, 16); |
3069 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3070 | |
3071 | /* Now make space on the stack for the args. */ | |
3072 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3073 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
cb3d25d1 | 3074 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3075 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3076 | |
3077 | if (mips_debug) | |
3078 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3079 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3080 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3081 | |
3082 | /* Initialize the integer and float register pointers. */ | |
3083 | argreg = A0_REGNUM; | |
56cea623 | 3084 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3085 | |
46e0f506 | 3086 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3087 | if (struct_return) |
3088 | { | |
3089 | if (mips_debug) | |
3090 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3091 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3092 | argreg, paddr_nz (struct_addr)); |
3093 | write_register (argreg++, struct_addr); | |
3094 | } | |
3095 | ||
3096 | /* Now load as many as possible of the first arguments into | |
3097 | registers, and push the rest onto the stack. Loop thru args | |
3098 | from first to last. */ | |
3099 | for (argnum = 0; argnum < nargs; argnum++) | |
3100 | { | |
3101 | char *val; | |
d9d9c31f | 3102 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3103 | struct value *arg = args[argnum]; |
3104 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3105 | int len = TYPE_LENGTH (arg_type); | |
3106 | enum type_code typecode = TYPE_CODE (arg_type); | |
3107 | ||
3108 | if (mips_debug) | |
3109 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3110 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3111 | argnum + 1, len, (int) typecode); |
3112 | ||
3113 | val = (char *) VALUE_CONTENTS (arg); | |
3114 | ||
3115 | if (fp_register_arg_p (typecode, arg_type) | |
3116 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3117 | { | |
3118 | /* This is a floating point value that fits entirely | |
3119 | in a single register. */ | |
3120 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3121 | above to ensure that it is even register aligned. */ | |
3122 | LONGEST regval = extract_unsigned_integer (val, len); | |
3123 | if (mips_debug) | |
3124 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3125 | float_argreg, phex (regval, len)); | |
3126 | write_register (float_argreg++, regval); | |
3127 | ||
3128 | if (mips_debug) | |
3129 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3130 | argreg, phex (regval, len)); | |
3131 | write_register (argreg, regval); | |
3132 | argreg += 1; | |
3133 | } | |
3134 | else | |
3135 | { | |
3136 | /* Copy the argument to general registers or the stack in | |
3137 | register-sized pieces. Large arguments are split between | |
3138 | registers and stack. */ | |
4246e332 AC |
3139 | /* Note: structs whose size is not a multiple of |
3140 | mips_regsize() are treated specially: Irix cc passes them | |
3141 | in registers where gcc sometimes puts them on the stack. | |
3142 | For maximum compatibility, we will put them in both | |
3143 | places. */ | |
cb3d25d1 MS |
3144 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3145 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3146 | /* Note: Floating-point values that didn't fit into an FP | |
3147 | register are only written to memory. */ | |
3148 | while (len > 0) | |
3149 | { | |
3150 | /* Rememer if the argument was written to the stack. */ | |
3151 | int stack_used_p = 0; | |
3152 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3153 | len : MIPS_SAVED_REGSIZE; | |
3154 | ||
3155 | if (mips_debug) | |
3156 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3157 | partial_len); | |
3158 | ||
3159 | /* Write this portion of the argument to the stack. */ | |
3160 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3161 | || odd_sized_struct | |
3162 | || fp_register_arg_p (typecode, arg_type)) | |
3163 | { | |
3164 | /* Should shorter than int integer values be | |
3165 | promoted to int before being stored? */ | |
3166 | int longword_offset = 0; | |
3167 | CORE_ADDR addr; | |
3168 | stack_used_p = 1; | |
3169 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3170 | { | |
3171 | if (MIPS_STACK_ARGSIZE == 8 && | |
3172 | (typecode == TYPE_CODE_INT || | |
3173 | typecode == TYPE_CODE_PTR || | |
3174 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3175 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3176 | } |
3177 | ||
3178 | if (mips_debug) | |
3179 | { | |
3180 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3181 | paddr_nz (stack_offset)); | |
3182 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3183 | paddr_nz (longword_offset)); | |
3184 | } | |
3185 | ||
3186 | addr = sp + stack_offset + longword_offset; | |
3187 | ||
3188 | if (mips_debug) | |
3189 | { | |
3190 | int i; | |
3191 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3192 | paddr_nz (addr)); | |
3193 | for (i = 0; i < partial_len; i++) | |
3194 | { | |
3195 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3196 | val[i] & 0xff); | |
3197 | } | |
3198 | } | |
3199 | write_memory (addr, val, partial_len); | |
3200 | } | |
3201 | ||
3202 | /* Note!!! This is NOT an else clause. Odd sized | |
3203 | structs may go thru BOTH paths. Floating point | |
3204 | arguments will not. */ | |
3205 | /* Write this portion of the argument to a general | |
3206 | purpose register. */ | |
3207 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3208 | && !fp_register_arg_p (typecode, arg_type)) | |
3209 | { | |
3210 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3211 | ||
3212 | /* A non-floating-point argument being passed in a | |
3213 | general register. If a struct or union, and if | |
3214 | the remaining length is smaller than the register | |
3215 | size, we have to adjust the register value on | |
3216 | big endian targets. | |
3217 | ||
3218 | It does not seem to be necessary to do the | |
3219 | same for integral types. | |
3220 | ||
3221 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3222 | outputting LE O32 with sizeof (struct) < | |
3223 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3224 | part of storing the argument in a register a | |
3225 | register (the left shift isn't generated when | |
3226 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3227 | is quite possible that this is GCC contradicting | |
3228 | the LE/O32 ABI, GDB has not been adjusted to | |
3229 | accommodate this. Either someone needs to | |
3230 | demonstrate that the LE/O32 ABI specifies such a | |
3231 | left shift OR this new ABI gets identified as | |
3232 | such and GDB gets tweaked accordingly. */ | |
3233 | ||
3234 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3235 | && partial_len < MIPS_SAVED_REGSIZE | |
3236 | && (typecode == TYPE_CODE_STRUCT || | |
3237 | typecode == TYPE_CODE_UNION)) | |
3238 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3239 | TARGET_CHAR_BIT); | |
3240 | ||
3241 | if (mips_debug) | |
3242 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3243 | argreg, | |
3244 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3245 | write_register (argreg, regval); | |
3246 | argreg++; | |
3247 | } | |
3248 | ||
3249 | len -= partial_len; | |
3250 | val += partial_len; | |
3251 | ||
3252 | /* Compute the the offset into the stack at which we | |
3253 | will copy the next parameter. | |
3254 | ||
3255 | In N32 (N64?), the stack_offset only needs to be | |
3256 | adjusted when it has been used. */ | |
3257 | ||
3258 | if (stack_used_p) | |
5b03f266 | 3259 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
cb3d25d1 MS |
3260 | } |
3261 | } | |
3262 | if (mips_debug) | |
3263 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3264 | } | |
3265 | ||
310e9b6a AC |
3266 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3267 | ||
cb3d25d1 MS |
3268 | /* Return adjusted stack pointer. */ |
3269 | return sp; | |
3270 | } | |
3271 | ||
25ab4790 | 3272 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3273 | |
46cac009 | 3274 | static CORE_ADDR |
25ab4790 AC |
3275 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3276 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3277 | struct value **args, CORE_ADDR sp, int struct_return, | |
3278 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3279 | { |
3280 | int argreg; | |
3281 | int float_argreg; | |
3282 | int argnum; | |
3283 | int len = 0; | |
3284 | int stack_offset = 0; | |
ebafbe83 | 3285 | |
25ab4790 AC |
3286 | /* For shared libraries, "t9" needs to point at the function |
3287 | address. */ | |
3288 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3289 | ||
3290 | /* Set the return address register to point to the entry point of | |
3291 | the program, where a breakpoint lies in wait. */ | |
3292 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3293 | ||
ebafbe83 MS |
3294 | /* First ensure that the stack and structure return address (if any) |
3295 | are properly aligned. The stack has to be at least 64-bit | |
3296 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3297 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3298 | aligned, so we round to this widest known alignment. */ | |
3299 | ||
5b03f266 AC |
3300 | sp = align_down (sp, 16); |
3301 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3302 | |
3303 | /* Now make space on the stack for the args. */ | |
3304 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3305 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
ebafbe83 | 3306 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3307 | sp -= align_up (len, 16); |
ebafbe83 MS |
3308 | |
3309 | if (mips_debug) | |
3310 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3311 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3312 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3313 | |
3314 | /* Initialize the integer and float register pointers. */ | |
3315 | argreg = A0_REGNUM; | |
56cea623 | 3316 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3317 | |
bcb0cc15 | 3318 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3319 | if (struct_return) |
3320 | { | |
3321 | if (mips_debug) | |
3322 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3323 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3324 | argreg, paddr_nz (struct_addr)); |
3325 | write_register (argreg++, struct_addr); | |
3326 | stack_offset += MIPS_STACK_ARGSIZE; | |
3327 | } | |
3328 | ||
3329 | /* Now load as many as possible of the first arguments into | |
3330 | registers, and push the rest onto the stack. Loop thru args | |
3331 | from first to last. */ | |
3332 | for (argnum = 0; argnum < nargs; argnum++) | |
3333 | { | |
3334 | char *val; | |
d9d9c31f | 3335 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3336 | struct value *arg = args[argnum]; |
3337 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3338 | int len = TYPE_LENGTH (arg_type); | |
3339 | enum type_code typecode = TYPE_CODE (arg_type); | |
3340 | ||
3341 | if (mips_debug) | |
3342 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3343 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3344 | argnum + 1, len, (int) typecode); |
3345 | ||
3346 | val = (char *) VALUE_CONTENTS (arg); | |
3347 | ||
3348 | /* 32-bit ABIs always start floating point arguments in an | |
3349 | even-numbered floating point register. Round the FP register | |
3350 | up before the check to see if there are any FP registers | |
3351 | left. O32/O64 targets also pass the FP in the integer | |
3352 | registers so also round up normal registers. */ | |
3353 | if (!FP_REGISTER_DOUBLE | |
3354 | && fp_register_arg_p (typecode, arg_type)) | |
3355 | { | |
3356 | if ((float_argreg & 1)) | |
3357 | float_argreg++; | |
3358 | } | |
3359 | ||
3360 | /* Floating point arguments passed in registers have to be | |
3361 | treated specially. On 32-bit architectures, doubles | |
3362 | are passed in register pairs; the even register gets | |
3363 | the low word, and the odd register gets the high word. | |
3364 | On O32/O64, the first two floating point arguments are | |
3365 | also copied to general registers, because MIPS16 functions | |
3366 | don't use float registers for arguments. This duplication of | |
3367 | arguments in general registers can't hurt non-MIPS16 functions | |
3368 | because those registers are normally skipped. */ | |
3369 | ||
3370 | if (fp_register_arg_p (typecode, arg_type) | |
3371 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3372 | { | |
3373 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3374 | { | |
3375 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3376 | unsigned long regval; | |
3377 | ||
3378 | /* Write the low word of the double to the even register(s). */ | |
3379 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3380 | if (mips_debug) | |
3381 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3382 | float_argreg, phex (regval, 4)); | |
3383 | write_register (float_argreg++, regval); | |
3384 | if (mips_debug) | |
3385 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3386 | argreg, phex (regval, 4)); | |
3387 | write_register (argreg++, regval); | |
3388 | ||
3389 | /* Write the high word of the double to the odd register(s). */ | |
3390 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3391 | if (mips_debug) | |
3392 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3393 | float_argreg, phex (regval, 4)); | |
3394 | write_register (float_argreg++, regval); | |
3395 | ||
3396 | if (mips_debug) | |
3397 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3398 | argreg, phex (regval, 4)); | |
3399 | write_register (argreg++, regval); | |
3400 | } | |
3401 | else | |
3402 | { | |
3403 | /* This is a floating point value that fits entirely | |
3404 | in a single register. */ | |
3405 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3406 | above to ensure that it is even register aligned. */ | |
3407 | LONGEST regval = extract_unsigned_integer (val, len); | |
3408 | if (mips_debug) | |
3409 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3410 | float_argreg, phex (regval, len)); | |
3411 | write_register (float_argreg++, regval); | |
3412 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3413 | registers for each argument. The below is (my | |
3414 | guess) to ensure that the corresponding integer | |
3415 | register has reserved the same space. */ | |
3416 | if (mips_debug) | |
3417 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3418 | argreg, phex (regval, len)); | |
3419 | write_register (argreg, regval); | |
3420 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3421 | } | |
3422 | /* Reserve space for the FP register. */ | |
5b03f266 | 3423 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3424 | } |
3425 | else | |
3426 | { | |
3427 | /* Copy the argument to general registers or the stack in | |
3428 | register-sized pieces. Large arguments are split between | |
3429 | registers and stack. */ | |
4246e332 AC |
3430 | /* Note: structs whose size is not a multiple of |
3431 | mips_regsize() are treated specially: Irix cc passes them | |
3432 | in registers where gcc sometimes puts them on the stack. | |
3433 | For maximum compatibility, we will put them in both | |
3434 | places. */ | |
46cac009 AC |
3435 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3436 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3437 | /* Structures should be aligned to eight bytes (even arg registers) | |
3438 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3439 | if (MIPS_SAVED_REGSIZE < 8 | |
3440 | && mips_type_needs_double_align (arg_type)) | |
3441 | { | |
3442 | if ((argreg & 1)) | |
3443 | argreg++; | |
3444 | } | |
3445 | /* Note: Floating-point values that didn't fit into an FP | |
3446 | register are only written to memory. */ | |
3447 | while (len > 0) | |
3448 | { | |
3449 | /* Remember if the argument was written to the stack. */ | |
3450 | int stack_used_p = 0; | |
3451 | int partial_len = | |
3452 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3453 | ||
3454 | if (mips_debug) | |
3455 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3456 | partial_len); | |
3457 | ||
3458 | /* Write this portion of the argument to the stack. */ | |
3459 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3460 | || odd_sized_struct | |
3461 | || fp_register_arg_p (typecode, arg_type)) | |
3462 | { | |
3463 | /* Should shorter than int integer values be | |
3464 | promoted to int before being stored? */ | |
3465 | int longword_offset = 0; | |
3466 | CORE_ADDR addr; | |
3467 | stack_used_p = 1; | |
3468 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3469 | { | |
3470 | if (MIPS_STACK_ARGSIZE == 8 && | |
3471 | (typecode == TYPE_CODE_INT || | |
3472 | typecode == TYPE_CODE_PTR || | |
3473 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3474 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3475 | } | |
3476 | ||
3477 | if (mips_debug) | |
3478 | { | |
3479 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3480 | paddr_nz (stack_offset)); | |
3481 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3482 | paddr_nz (longword_offset)); | |
3483 | } | |
3484 | ||
3485 | addr = sp + stack_offset + longword_offset; | |
3486 | ||
3487 | if (mips_debug) | |
3488 | { | |
3489 | int i; | |
3490 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3491 | paddr_nz (addr)); | |
3492 | for (i = 0; i < partial_len; i++) | |
3493 | { | |
3494 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3495 | val[i] & 0xff); | |
3496 | } | |
3497 | } | |
3498 | write_memory (addr, val, partial_len); | |
3499 | } | |
3500 | ||
3501 | /* Note!!! This is NOT an else clause. Odd sized | |
3502 | structs may go thru BOTH paths. Floating point | |
3503 | arguments will not. */ | |
3504 | /* Write this portion of the argument to a general | |
3505 | purpose register. */ | |
3506 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3507 | && !fp_register_arg_p (typecode, arg_type)) | |
3508 | { | |
3509 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3510 | /* Value may need to be sign extended, because |
3511 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
46cac009 AC |
3512 | |
3513 | /* A non-floating-point argument being passed in a | |
3514 | general register. If a struct or union, and if | |
3515 | the remaining length is smaller than the register | |
3516 | size, we have to adjust the register value on | |
3517 | big endian targets. | |
3518 | ||
3519 | It does not seem to be necessary to do the | |
3520 | same for integral types. | |
3521 | ||
3522 | Also don't do this adjustment on O64 binaries. | |
3523 | ||
3524 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3525 | outputting LE O32 with sizeof (struct) < | |
3526 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3527 | part of storing the argument in a register a | |
3528 | register (the left shift isn't generated when | |
3529 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3530 | is quite possible that this is GCC contradicting | |
3531 | the LE/O32 ABI, GDB has not been adjusted to | |
3532 | accommodate this. Either someone needs to | |
3533 | demonstrate that the LE/O32 ABI specifies such a | |
3534 | left shift OR this new ABI gets identified as | |
3535 | such and GDB gets tweaked accordingly. */ | |
3536 | ||
3537 | if (MIPS_SAVED_REGSIZE < 8 | |
3538 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3539 | && partial_len < MIPS_SAVED_REGSIZE | |
3540 | && (typecode == TYPE_CODE_STRUCT || | |
3541 | typecode == TYPE_CODE_UNION)) | |
3542 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3543 | TARGET_CHAR_BIT); | |
3544 | ||
3545 | if (mips_debug) | |
3546 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3547 | argreg, | |
3548 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3549 | write_register (argreg, regval); | |
3550 | argreg++; | |
3551 | ||
3552 | /* Prevent subsequent floating point arguments from | |
3553 | being passed in floating point registers. */ | |
3554 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3555 | } | |
3556 | ||
3557 | len -= partial_len; | |
3558 | val += partial_len; | |
3559 | ||
3560 | /* Compute the the offset into the stack at which we | |
3561 | will copy the next parameter. | |
3562 | ||
3563 | In older ABIs, the caller reserved space for | |
3564 | registers that contained arguments. This was loosely | |
3565 | refered to as their "home". Consequently, space is | |
3566 | always allocated. */ | |
3567 | ||
5b03f266 | 3568 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3569 | } |
3570 | } | |
3571 | if (mips_debug) | |
3572 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3573 | } | |
3574 | ||
310e9b6a AC |
3575 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3576 | ||
46cac009 AC |
3577 | /* Return adjusted stack pointer. */ |
3578 | return sp; | |
3579 | } | |
3580 | ||
25ab4790 | 3581 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3582 | |
3583 | static CORE_ADDR | |
25ab4790 AC |
3584 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3585 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3586 | struct value **args, CORE_ADDR sp, int struct_return, | |
3587 | CORE_ADDR struct_addr) | |
46cac009 AC |
3588 | { |
3589 | int argreg; | |
3590 | int float_argreg; | |
3591 | int argnum; | |
3592 | int len = 0; | |
3593 | int stack_offset = 0; | |
3594 | ||
25ab4790 AC |
3595 | /* For shared libraries, "t9" needs to point at the function |
3596 | address. */ | |
3597 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3598 | ||
3599 | /* Set the return address register to point to the entry point of | |
3600 | the program, where a breakpoint lies in wait. */ | |
3601 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3602 | ||
46cac009 AC |
3603 | /* First ensure that the stack and structure return address (if any) |
3604 | are properly aligned. The stack has to be at least 64-bit | |
3605 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3606 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3607 | aligned, so we round to this widest known alignment. */ | |
3608 | ||
5b03f266 AC |
3609 | sp = align_down (sp, 16); |
3610 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3611 | |
3612 | /* Now make space on the stack for the args. */ | |
3613 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3614 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46cac009 | 3615 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3616 | sp -= align_up (len, 16); |
46cac009 AC |
3617 | |
3618 | if (mips_debug) | |
3619 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3620 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3621 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3622 | |
3623 | /* Initialize the integer and float register pointers. */ | |
3624 | argreg = A0_REGNUM; | |
56cea623 | 3625 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3626 | |
3627 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3628 | if (struct_return) | |
3629 | { | |
3630 | if (mips_debug) | |
3631 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3632 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3633 | argreg, paddr_nz (struct_addr)); |
3634 | write_register (argreg++, struct_addr); | |
3635 | stack_offset += MIPS_STACK_ARGSIZE; | |
3636 | } | |
3637 | ||
3638 | /* Now load as many as possible of the first arguments into | |
3639 | registers, and push the rest onto the stack. Loop thru args | |
3640 | from first to last. */ | |
3641 | for (argnum = 0; argnum < nargs; argnum++) | |
3642 | { | |
3643 | char *val; | |
d9d9c31f | 3644 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3645 | struct value *arg = args[argnum]; |
3646 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3647 | int len = TYPE_LENGTH (arg_type); | |
3648 | enum type_code typecode = TYPE_CODE (arg_type); | |
3649 | ||
3650 | if (mips_debug) | |
3651 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3652 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3653 | argnum + 1, len, (int) typecode); |
3654 | ||
3655 | val = (char *) VALUE_CONTENTS (arg); | |
3656 | ||
3657 | /* 32-bit ABIs always start floating point arguments in an | |
3658 | even-numbered floating point register. Round the FP register | |
3659 | up before the check to see if there are any FP registers | |
3660 | left. O32/O64 targets also pass the FP in the integer | |
3661 | registers so also round up normal registers. */ | |
3662 | if (!FP_REGISTER_DOUBLE | |
3663 | && fp_register_arg_p (typecode, arg_type)) | |
3664 | { | |
3665 | if ((float_argreg & 1)) | |
3666 | float_argreg++; | |
3667 | } | |
3668 | ||
3669 | /* Floating point arguments passed in registers have to be | |
3670 | treated specially. On 32-bit architectures, doubles | |
3671 | are passed in register pairs; the even register gets | |
3672 | the low word, and the odd register gets the high word. | |
3673 | On O32/O64, the first two floating point arguments are | |
3674 | also copied to general registers, because MIPS16 functions | |
3675 | don't use float registers for arguments. This duplication of | |
3676 | arguments in general registers can't hurt non-MIPS16 functions | |
3677 | because those registers are normally skipped. */ | |
3678 | ||
3679 | if (fp_register_arg_p (typecode, arg_type) | |
3680 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3681 | { | |
3682 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3683 | { | |
3684 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3685 | unsigned long regval; | |
3686 | ||
3687 | /* Write the low word of the double to the even register(s). */ | |
3688 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3689 | if (mips_debug) | |
3690 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3691 | float_argreg, phex (regval, 4)); | |
3692 | write_register (float_argreg++, regval); | |
3693 | if (mips_debug) | |
3694 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3695 | argreg, phex (regval, 4)); | |
3696 | write_register (argreg++, regval); | |
3697 | ||
3698 | /* Write the high word of the double to the odd register(s). */ | |
3699 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3700 | if (mips_debug) | |
3701 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3702 | float_argreg, phex (regval, 4)); | |
3703 | write_register (float_argreg++, regval); | |
3704 | ||
3705 | if (mips_debug) | |
3706 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3707 | argreg, phex (regval, 4)); | |
3708 | write_register (argreg++, regval); | |
3709 | } | |
3710 | else | |
3711 | { | |
3712 | /* This is a floating point value that fits entirely | |
3713 | in a single register. */ | |
3714 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3715 | above to ensure that it is even register aligned. */ | |
3716 | LONGEST regval = extract_unsigned_integer (val, len); | |
3717 | if (mips_debug) | |
3718 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3719 | float_argreg, phex (regval, len)); | |
3720 | write_register (float_argreg++, regval); | |
3721 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3722 | registers for each argument. The below is (my | |
3723 | guess) to ensure that the corresponding integer | |
3724 | register has reserved the same space. */ | |
3725 | if (mips_debug) | |
3726 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3727 | argreg, phex (regval, len)); | |
3728 | write_register (argreg, regval); | |
3729 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3730 | } | |
3731 | /* Reserve space for the FP register. */ | |
5b03f266 | 3732 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3733 | } |
3734 | else | |
3735 | { | |
3736 | /* Copy the argument to general registers or the stack in | |
3737 | register-sized pieces. Large arguments are split between | |
3738 | registers and stack. */ | |
4246e332 AC |
3739 | /* Note: structs whose size is not a multiple of |
3740 | mips_regsize() are treated specially: Irix cc passes them | |
3741 | in registers where gcc sometimes puts them on the stack. | |
3742 | For maximum compatibility, we will put them in both | |
3743 | places. */ | |
ebafbe83 MS |
3744 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3745 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3746 | /* Structures should be aligned to eight bytes (even arg registers) | |
3747 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3748 | if (MIPS_SAVED_REGSIZE < 8 | |
3749 | && mips_type_needs_double_align (arg_type)) | |
3750 | { | |
3751 | if ((argreg & 1)) | |
3752 | argreg++; | |
3753 | } | |
3754 | /* Note: Floating-point values that didn't fit into an FP | |
3755 | register are only written to memory. */ | |
3756 | while (len > 0) | |
3757 | { | |
3758 | /* Remember if the argument was written to the stack. */ | |
3759 | int stack_used_p = 0; | |
3760 | int partial_len = | |
3761 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3762 | ||
3763 | if (mips_debug) | |
3764 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3765 | partial_len); | |
3766 | ||
3767 | /* Write this portion of the argument to the stack. */ | |
3768 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3769 | || odd_sized_struct | |
3770 | || fp_register_arg_p (typecode, arg_type)) | |
3771 | { | |
3772 | /* Should shorter than int integer values be | |
3773 | promoted to int before being stored? */ | |
3774 | int longword_offset = 0; | |
3775 | CORE_ADDR addr; | |
3776 | stack_used_p = 1; | |
3777 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3778 | { | |
3779 | if (MIPS_STACK_ARGSIZE == 8 && | |
3780 | (typecode == TYPE_CODE_INT || | |
3781 | typecode == TYPE_CODE_PTR || | |
3782 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3783 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3784 | } | |
3785 | ||
3786 | if (mips_debug) | |
3787 | { | |
3788 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3789 | paddr_nz (stack_offset)); | |
3790 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3791 | paddr_nz (longword_offset)); | |
3792 | } | |
3793 | ||
3794 | addr = sp + stack_offset + longword_offset; | |
3795 | ||
3796 | if (mips_debug) | |
3797 | { | |
3798 | int i; | |
3799 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3800 | paddr_nz (addr)); | |
3801 | for (i = 0; i < partial_len; i++) | |
3802 | { | |
3803 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3804 | val[i] & 0xff); | |
3805 | } | |
3806 | } | |
3807 | write_memory (addr, val, partial_len); | |
3808 | } | |
3809 | ||
3810 | /* Note!!! This is NOT an else clause. Odd sized | |
3811 | structs may go thru BOTH paths. Floating point | |
3812 | arguments will not. */ | |
3813 | /* Write this portion of the argument to a general | |
3814 | purpose register. */ | |
3815 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3816 | && !fp_register_arg_p (typecode, arg_type)) | |
3817 | { | |
3818 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3819 | /* Value may need to be sign extended, because |
3820 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
ebafbe83 MS |
3821 | |
3822 | /* A non-floating-point argument being passed in a | |
3823 | general register. If a struct or union, and if | |
3824 | the remaining length is smaller than the register | |
3825 | size, we have to adjust the register value on | |
3826 | big endian targets. | |
3827 | ||
3828 | It does not seem to be necessary to do the | |
3829 | same for integral types. | |
3830 | ||
3831 | Also don't do this adjustment on O64 binaries. | |
3832 | ||
3833 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3834 | outputting LE O32 with sizeof (struct) < | |
3835 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3836 | part of storing the argument in a register a | |
3837 | register (the left shift isn't generated when | |
3838 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3839 | is quite possible that this is GCC contradicting | |
3840 | the LE/O32 ABI, GDB has not been adjusted to | |
3841 | accommodate this. Either someone needs to | |
3842 | demonstrate that the LE/O32 ABI specifies such a | |
3843 | left shift OR this new ABI gets identified as | |
3844 | such and GDB gets tweaked accordingly. */ | |
3845 | ||
3846 | if (MIPS_SAVED_REGSIZE < 8 | |
3847 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3848 | && partial_len < MIPS_SAVED_REGSIZE | |
3849 | && (typecode == TYPE_CODE_STRUCT || | |
3850 | typecode == TYPE_CODE_UNION)) | |
3851 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3852 | TARGET_CHAR_BIT); | |
3853 | ||
3854 | if (mips_debug) | |
3855 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3856 | argreg, | |
3857 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3858 | write_register (argreg, regval); | |
3859 | argreg++; | |
3860 | ||
3861 | /* Prevent subsequent floating point arguments from | |
3862 | being passed in floating point registers. */ | |
3863 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3864 | } | |
3865 | ||
3866 | len -= partial_len; | |
3867 | val += partial_len; | |
3868 | ||
3869 | /* Compute the the offset into the stack at which we | |
3870 | will copy the next parameter. | |
3871 | ||
3872 | In older ABIs, the caller reserved space for | |
3873 | registers that contained arguments. This was loosely | |
3874 | refered to as their "home". Consequently, space is | |
3875 | always allocated. */ | |
3876 | ||
5b03f266 | 3877 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3878 | } |
3879 | } | |
3880 | if (mips_debug) | |
3881 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3882 | } | |
3883 | ||
310e9b6a AC |
3884 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3885 | ||
ebafbe83 MS |
3886 | /* Return adjusted stack pointer. */ |
3887 | return sp; | |
3888 | } | |
3889 | ||
f7ab6ec6 | 3890 | static void |
acdb74a0 | 3891 | mips_pop_frame (void) |
c906108c | 3892 | { |
52f0bd74 | 3893 | int regnum; |
c906108c | 3894 | struct frame_info *frame = get_current_frame (); |
c193f6ac | 3895 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3896 | mips_extra_func_info_t proc_desc; |
c906108c | 3897 | |
50abf9e5 | 3898 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3899 | { |
3900 | generic_pop_dummy_frame (); | |
3901 | flush_cached_frames (); | |
3902 | return; | |
3903 | } | |
3904 | ||
e227b13c | 3905 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3906 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3907 | mips_find_saved_regs (frame); |
c906108c | 3908 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3909 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1b1d3794 | 3910 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3911 | { |
3912 | /* Floating point registers must not be sign extended, | |
3913 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3914 | ||
56cea623 | 3915 | if (mips_regnum (current_gdbarch)->fp0 <= regnum && regnum < mips_regnum (current_gdbarch)->fp0 + 32) |
21f87145 | 3916 | write_register (regnum, |
1b1d3794 | 3917 | read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3918 | MIPS_SAVED_REGSIZE)); |
3919 | else | |
3920 | write_register (regnum, | |
1b1d3794 | 3921 | read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3922 | MIPS_SAVED_REGSIZE)); |
3923 | } | |
757a7cc6 | 3924 | |
c906108c SS |
3925 | write_register (SP_REGNUM, new_sp); |
3926 | flush_cached_frames (); | |
3927 | ||
c5aa993b | 3928 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3929 | { |
3930 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3931 | ||
3932 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3933 | pi_ptr != NULL; | |
3934 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3935 | { | |
3936 | if (&pi_ptr->info == proc_desc) | |
3937 | break; | |
3938 | } | |
3939 | ||
3940 | if (pi_ptr == NULL) | |
3941 | error ("Can't locate dummy extra frame info\n"); | |
3942 | ||
3943 | if (prev_ptr != NULL) | |
3944 | prev_ptr->next = pi_ptr->next; | |
3945 | else | |
3946 | linked_proc_desc_table = pi_ptr->next; | |
3947 | ||
b8c9b27d | 3948 | xfree (pi_ptr); |
c906108c | 3949 | |
56cea623 | 3950 | write_register (mips_regnum (current_gdbarch)->hi, |
c5aa993b | 3951 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3952 | MIPS_SAVED_REGSIZE)); |
56cea623 | 3953 | write_register (mips_regnum (current_gdbarch)->lo, |
c5aa993b | 3954 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3955 | MIPS_SAVED_REGSIZE)); |
c906108c | 3956 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
56cea623 | 3957 | write_register (mips_regnum (current_gdbarch)->fp_control_status, |
c5aa993b | 3958 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3959 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3960 | } |
3961 | } | |
3962 | ||
dd824b04 DJ |
3963 | /* Floating point register management. |
3964 | ||
3965 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3966 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3967 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3968 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3969 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3970 | double precision floats into two 32-bit chunks and store them in | |
3971 | consecutive fp regs. To display 64-bit floats stored in this | |
3972 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3973 | Throw in user-configurable endianness and you have a real mess. | |
3974 | ||
3975 | The way this works is: | |
3976 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3977 | double-precision value will be split across two logical registers. | |
3978 | The lower-numbered logical register will hold the low-order bits, | |
3979 | regardless of the processor's endianness. | |
3980 | - If we are on a 64-bit processor, and we are looking for a | |
3981 | single-precision value, it will be in the low ordered bits | |
3982 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3983 | save slot in memory. | |
3984 | - If we are in 64-bit mode, everything is straightforward. | |
3985 | ||
3986 | Note that this code only deals with "live" registers at the top of the | |
3987 | stack. We will attempt to deal with saved registers later, when | |
3988 | the raw/cooked register interface is in place. (We need a general | |
3989 | interface that can deal with dynamic saved register sizes -- fp | |
3990 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3991 | and below). */ | |
3992 | ||
67b2c998 DJ |
3993 | static struct type * |
3994 | mips_float_register_type (void) | |
3995 | { | |
361d1df0 | 3996 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3997 | return builtin_type_ieee_single_big; |
3998 | else | |
3999 | return builtin_type_ieee_single_little; | |
4000 | } | |
4001 | ||
4002 | static struct type * | |
4003 | mips_double_register_type (void) | |
4004 | { | |
361d1df0 | 4005 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4006 | return builtin_type_ieee_double_big; |
4007 | else | |
4008 | return builtin_type_ieee_double_little; | |
4009 | } | |
4010 | ||
dd824b04 DJ |
4011 | /* Copy a 32-bit single-precision value from the current frame |
4012 | into rare_buffer. */ | |
4013 | ||
4014 | static void | |
e11c53d2 AC |
4015 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4016 | char *rare_buffer) | |
dd824b04 | 4017 | { |
719ec221 | 4018 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4019 | char *raw_buffer = alloca (raw_size); |
4020 | ||
e11c53d2 | 4021 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4022 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4023 | if (raw_size == 8) | |
4024 | { | |
4025 | /* We have a 64-bit value for this register. Find the low-order | |
4026 | 32 bits. */ | |
4027 | int offset; | |
4028 | ||
4029 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4030 | offset = 4; | |
4031 | else | |
4032 | offset = 0; | |
4033 | ||
4034 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4035 | } | |
4036 | else | |
4037 | { | |
4038 | memcpy (rare_buffer, raw_buffer, 4); | |
4039 | } | |
4040 | } | |
4041 | ||
4042 | /* Copy a 64-bit double-precision value from the current frame into | |
4043 | rare_buffer. This may include getting half of it from the next | |
4044 | register. */ | |
4045 | ||
4046 | static void | |
e11c53d2 AC |
4047 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4048 | char *rare_buffer) | |
dd824b04 | 4049 | { |
719ec221 | 4050 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4051 | |
4052 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4053 | { | |
4054 | /* We have a 64-bit value for this register, and we should use | |
4055 | all 64 bits. */ | |
e11c53d2 | 4056 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4057 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4058 | } | |
4059 | else | |
4060 | { | |
56cea623 | 4061 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4062 | internal_error (__FILE__, __LINE__, |
4063 | "mips_read_fp_register_double: bad access to " | |
4064 | "odd-numbered FP register"); | |
4065 | ||
4066 | /* mips_read_fp_register_single will find the correct 32 bits from | |
4067 | each register. */ | |
4068 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4069 | { | |
e11c53d2 AC |
4070 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4071 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4072 | } |
361d1df0 | 4073 | else |
dd824b04 | 4074 | { |
e11c53d2 AC |
4075 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4076 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4077 | } |
4078 | } | |
4079 | } | |
4080 | ||
c906108c | 4081 | static void |
e11c53d2 AC |
4082 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4083 | int regnum) | |
c5aa993b | 4084 | { /* do values for FP (float) regs */ |
dd824b04 | 4085 | char *raw_buffer; |
c906108c | 4086 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4087 | int inv1, inv2, namelen; |
c5aa993b | 4088 | |
56cea623 | 4089 | raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0)); |
c906108c | 4090 | |
e11c53d2 AC |
4091 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4092 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4093 | ""); | |
f0ef6b29 | 4094 | |
719ec221 | 4095 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4096 | { |
f0ef6b29 KB |
4097 | /* 4-byte registers: Print hex and floating. Also print even |
4098 | numbered registers as doubles. */ | |
e11c53d2 | 4099 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4100 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4101 | |
e11c53d2 | 4102 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4103 | |
e11c53d2 | 4104 | fprintf_filtered (file, " flt: "); |
1adad886 | 4105 | if (inv1) |
e11c53d2 | 4106 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4107 | else |
e11c53d2 | 4108 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4109 | |
f0ef6b29 KB |
4110 | if (regnum % 2 == 0) |
4111 | { | |
e11c53d2 | 4112 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4113 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4114 | &inv2); | |
1adad886 | 4115 | |
e11c53d2 | 4116 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4117 | if (inv2) |
e11c53d2 | 4118 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4119 | else |
e11c53d2 | 4120 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4121 | } |
c906108c SS |
4122 | } |
4123 | else | |
dd824b04 | 4124 | { |
f0ef6b29 | 4125 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4126 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4127 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4128 | |
e11c53d2 | 4129 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4130 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4131 | ||
361d1df0 | 4132 | |
e11c53d2 | 4133 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4134 | |
e11c53d2 | 4135 | fprintf_filtered (file, " flt: "); |
1adad886 | 4136 | if (inv1) |
e11c53d2 | 4137 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4138 | else |
e11c53d2 | 4139 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4140 | |
e11c53d2 | 4141 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4142 | if (inv2) |
e11c53d2 | 4143 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4144 | else |
e11c53d2 | 4145 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4146 | } |
4147 | } | |
4148 | ||
4149 | static void | |
e11c53d2 AC |
4150 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4151 | int regnum, int all) | |
f0ef6b29 | 4152 | { |
a4b8ebc8 | 4153 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4154 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4155 | int offset; |
1adad886 | 4156 | |
a4b8ebc8 | 4157 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4158 | { |
e11c53d2 | 4159 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4160 | return; |
4161 | } | |
4162 | ||
4163 | /* Get the data in raw format. */ | |
e11c53d2 | 4164 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4165 | { |
e11c53d2 | 4166 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4167 | return; |
c906108c | 4168 | } |
f0ef6b29 | 4169 | |
e11c53d2 | 4170 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4171 | |
4172 | /* The problem with printing numeric register names (r26, etc.) is that | |
4173 | the user can't use them on input. Probably the best solution is to | |
4174 | fix it so that either the numeric or the funky (a2, etc.) names | |
4175 | are accepted on input. */ | |
4176 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4177 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4178 | else |
e11c53d2 | 4179 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4180 | |
4181 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
719ec221 | 4182 | offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
f0ef6b29 KB |
4183 | else |
4184 | offset = 0; | |
4185 | ||
a4b8ebc8 | 4186 | print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum), |
e11c53d2 | 4187 | 'x', 0, file); |
c906108c SS |
4188 | } |
4189 | ||
f0ef6b29 KB |
4190 | /* Replacement for generic do_registers_info. |
4191 | Print regs in pretty columns. */ | |
4192 | ||
4193 | static int | |
e11c53d2 AC |
4194 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4195 | int regnum) | |
f0ef6b29 | 4196 | { |
e11c53d2 AC |
4197 | fprintf_filtered (file, " "); |
4198 | mips_print_fp_register (file, frame, regnum); | |
4199 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4200 | return regnum + 1; |
4201 | } | |
4202 | ||
4203 | ||
c906108c SS |
4204 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4205 | ||
4206 | static int | |
e11c53d2 | 4207 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4208 | int start_regnum) |
c906108c | 4209 | { |
a4b8ebc8 | 4210 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4211 | /* do values for GP (int) regs */ |
d9d9c31f | 4212 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4213 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4214 | int col, byte; |
a4b8ebc8 | 4215 | int regnum; |
c906108c SS |
4216 | |
4217 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4218 | fprintf_filtered (file, " "); |
a4b8ebc8 AC |
4219 | for (col = 0, regnum = start_regnum; |
4220 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4221 | regnum++) | |
c906108c SS |
4222 | { |
4223 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4224 | continue; /* unused register */ |
a4b8ebc8 | 4225 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4226 | break; /* end the row: reached FP register */ |
4246e332 | 4227 | fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4228 | REGISTER_NAME (regnum)); |
c906108c SS |
4229 | col++; |
4230 | } | |
a4b8ebc8 | 4231 | /* print the R0 to R31 names */ |
20e6603c AC |
4232 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4233 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4234 | else | |
4235 | fprintf_filtered (file, "\n "); | |
c906108c | 4236 | |
c906108c | 4237 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 AC |
4238 | for (col = 0, regnum = start_regnum; |
4239 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4240 | regnum++) | |
c906108c SS |
4241 | { |
4242 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4243 | continue; /* unused register */ |
a4b8ebc8 | 4244 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4245 | break; /* end row: reached FP register */ |
c906108c | 4246 | /* OK: get the data in raw format. */ |
e11c53d2 | 4247 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4248 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4249 | /* pad small registers */ | |
4246e332 AC |
4250 | for (byte = 0; |
4251 | byte < (mips_regsize (current_gdbarch) | |
c73e8f27 | 4252 | - register_size (current_gdbarch, regnum)); |
4246e332 | 4253 | byte++) |
c906108c SS |
4254 | printf_filtered (" "); |
4255 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4256 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
719ec221 AC |
4257 | for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
4258 | byte < register_size (current_gdbarch, regnum); | |
43e526b9 | 4259 | byte++) |
e11c53d2 | 4260 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4261 | else |
c73e8f27 | 4262 | for (byte = register_size (current_gdbarch, regnum) - 1; |
43e526b9 JM |
4263 | byte >= 0; |
4264 | byte--) | |
e11c53d2 AC |
4265 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4266 | fprintf_filtered (file, " "); | |
c906108c SS |
4267 | col++; |
4268 | } | |
c5aa993b | 4269 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4270 | fprintf_filtered (file, "\n"); |
c906108c SS |
4271 | |
4272 | return regnum; | |
4273 | } | |
4274 | ||
4275 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4276 | ||
bf1f5b4c | 4277 | static void |
e11c53d2 AC |
4278 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4279 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4280 | { |
c5aa993b | 4281 | if (regnum != -1) /* do one specified register */ |
c906108c | 4282 | { |
a4b8ebc8 | 4283 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4284 | if (*(REGISTER_NAME (regnum)) == '\0') |
4285 | error ("Not a valid register for the current processor type"); | |
4286 | ||
e11c53d2 AC |
4287 | mips_print_register (file, frame, regnum, 0); |
4288 | fprintf_filtered (file, "\n"); | |
c906108c | 4289 | } |
c5aa993b JM |
4290 | else |
4291 | /* do all (or most) registers */ | |
c906108c | 4292 | { |
a4b8ebc8 AC |
4293 | regnum = NUM_REGS; |
4294 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4295 | { |
a4b8ebc8 | 4296 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4297 | { |
4298 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4299 | regnum = print_fp_register_row (file, frame, regnum); | |
4300 | else | |
4301 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4302 | } | |
c906108c | 4303 | else |
e11c53d2 | 4304 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4305 | } |
4306 | } | |
4307 | } | |
4308 | ||
c906108c SS |
4309 | /* Is this a branch with a delay slot? */ |
4310 | ||
a14ed312 | 4311 | static int is_delayed (unsigned long); |
c906108c SS |
4312 | |
4313 | static int | |
acdb74a0 | 4314 | is_delayed (unsigned long insn) |
c906108c SS |
4315 | { |
4316 | int i; | |
4317 | for (i = 0; i < NUMOPCODES; ++i) | |
4318 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4319 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4320 | break; | |
4321 | return (i < NUMOPCODES | |
4322 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4323 | | INSN_COND_BRANCH_DELAY | |
4324 | | INSN_COND_BRANCH_LIKELY))); | |
4325 | } | |
4326 | ||
4327 | int | |
acdb74a0 | 4328 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4329 | { |
4330 | char buf[MIPS_INSTLEN]; | |
4331 | ||
4332 | /* There is no branch delay slot on MIPS16. */ | |
4333 | if (pc_is_mips16 (pc)) | |
4334 | return 0; | |
4335 | ||
4336 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4337 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4338 | return 0; | |
c5aa993b | 4339 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4340 | } |
4341 | ||
4342 | ||
4343 | /* Skip the PC past function prologue instructions (32-bit version). | |
4344 | This is a helper function for mips_skip_prologue. */ | |
4345 | ||
4346 | static CORE_ADDR | |
f7b9e9fc | 4347 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4348 | { |
c5aa993b JM |
4349 | t_inst inst; |
4350 | CORE_ADDR end_pc; | |
4351 | int seen_sp_adjust = 0; | |
4352 | int load_immediate_bytes = 0; | |
4353 | ||
4354 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4355 | instruction and the instructions that save registers on the stack | |
4356 | or in the gcc frame. */ | |
4357 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
4358 | { | |
4359 | unsigned long high_word; | |
c906108c | 4360 | |
c5aa993b JM |
4361 | inst = mips_fetch_instruction (pc); |
4362 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4363 | |
c5aa993b JM |
4364 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4365 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4366 | seen_sp_adjust = 1; | |
4367 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4368 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4369 | seen_sp_adjust = 1; | |
4370 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4371 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4372 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4373 | continue; | |
4374 | ||
4375 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4376 | continue; | |
4377 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4378 | /* sx reg,n($s8) */ | |
4379 | continue; /* reg != $zero */ | |
4380 | ||
4381 | /* move $s8,$sp. With different versions of gas this will be either | |
4382 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4383 | Accept any one of these. */ | |
4384 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4385 | continue; | |
4386 | ||
4387 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4388 | continue; | |
4389 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4390 | continue; | |
4391 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4392 | continue; | |
4393 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4394 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4395 | continue; | |
4396 | /* The following instructions load $at or $t0 with an immediate | |
4397 | value in preparation for a stack adjustment via | |
4398 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4399 | a local variable, so we accept them only before a stack adjustment | |
4400 | instruction was seen. */ | |
4401 | else if (!seen_sp_adjust) | |
4402 | { | |
4403 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4404 | high_word == 0x3c08) /* lui $t0,n */ | |
4405 | { | |
4406 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4407 | continue; | |
4408 | } | |
4409 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4410 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4411 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4412 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4413 | { | |
4414 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4415 | continue; | |
4416 | } | |
4417 | else | |
4418 | break; | |
4419 | } | |
4420 | else | |
4421 | break; | |
c906108c SS |
4422 | } |
4423 | ||
c5aa993b JM |
4424 | /* In a frameless function, we might have incorrectly |
4425 | skipped some load immediate instructions. Undo the skipping | |
4426 | if the load immediate was not followed by a stack adjustment. */ | |
4427 | if (load_immediate_bytes && !seen_sp_adjust) | |
4428 | pc -= load_immediate_bytes; | |
4429 | return pc; | |
c906108c SS |
4430 | } |
4431 | ||
4432 | /* Skip the PC past function prologue instructions (16-bit version). | |
4433 | This is a helper function for mips_skip_prologue. */ | |
4434 | ||
4435 | static CORE_ADDR | |
f7b9e9fc | 4436 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4437 | { |
c5aa993b JM |
4438 | CORE_ADDR end_pc; |
4439 | int extend_bytes = 0; | |
4440 | int prev_extend_bytes; | |
c906108c | 4441 | |
c5aa993b JM |
4442 | /* Table of instructions likely to be found in a function prologue. */ |
4443 | static struct | |
c906108c SS |
4444 | { |
4445 | unsigned short inst; | |
4446 | unsigned short mask; | |
c5aa993b JM |
4447 | } |
4448 | table[] = | |
4449 | { | |
c906108c | 4450 | { |
c5aa993b JM |
4451 | 0x6300, 0xff00 |
4452 | } | |
4453 | , /* addiu $sp,offset */ | |
4454 | { | |
4455 | 0xfb00, 0xff00 | |
4456 | } | |
4457 | , /* daddiu $sp,offset */ | |
4458 | { | |
4459 | 0xd000, 0xf800 | |
4460 | } | |
4461 | , /* sw reg,n($sp) */ | |
4462 | { | |
4463 | 0xf900, 0xff00 | |
4464 | } | |
4465 | , /* sd reg,n($sp) */ | |
4466 | { | |
4467 | 0x6200, 0xff00 | |
4468 | } | |
4469 | , /* sw $ra,n($sp) */ | |
4470 | { | |
4471 | 0xfa00, 0xff00 | |
4472 | } | |
4473 | , /* sd $ra,n($sp) */ | |
4474 | { | |
4475 | 0x673d, 0xffff | |
4476 | } | |
4477 | , /* move $s1,sp */ | |
4478 | { | |
4479 | 0xd980, 0xff80 | |
4480 | } | |
4481 | , /* sw $a0-$a3,n($s1) */ | |
4482 | { | |
4483 | 0x6704, 0xff1c | |
4484 | } | |
4485 | , /* move reg,$a0-$a3 */ | |
4486 | { | |
4487 | 0xe809, 0xf81f | |
4488 | } | |
4489 | , /* entry pseudo-op */ | |
4490 | { | |
4491 | 0x0100, 0xff00 | |
4492 | } | |
4493 | , /* addiu $s1,$sp,n */ | |
4494 | { | |
4495 | 0, 0 | |
4496 | } /* end of table marker */ | |
4497 | }; | |
4498 | ||
4499 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4500 | instruction and the instructions that save registers on the stack | |
4501 | or in the gcc frame. */ | |
4502 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
4503 | { | |
4504 | unsigned short inst; | |
4505 | int i; | |
c906108c | 4506 | |
c5aa993b | 4507 | inst = mips_fetch_instruction (pc); |
c906108c | 4508 | |
c5aa993b JM |
4509 | /* Normally we ignore an extend instruction. However, if it is |
4510 | not followed by a valid prologue instruction, we must adjust | |
4511 | the pc back over the extend so that it won't be considered | |
4512 | part of the prologue. */ | |
4513 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4514 | { | |
4515 | extend_bytes = MIPS16_INSTLEN; | |
4516 | continue; | |
4517 | } | |
4518 | prev_extend_bytes = extend_bytes; | |
4519 | extend_bytes = 0; | |
c906108c | 4520 | |
c5aa993b JM |
4521 | /* Check for other valid prologue instructions besides extend. */ |
4522 | for (i = 0; table[i].mask != 0; i++) | |
4523 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4524 | break; | |
4525 | if (table[i].mask != 0) /* it was in table? */ | |
4526 | continue; /* ignore it */ | |
4527 | else | |
4528 | /* non-prologue */ | |
4529 | { | |
4530 | /* Return the current pc, adjusted backwards by 2 if | |
4531 | the previous instruction was an extend. */ | |
4532 | return pc - prev_extend_bytes; | |
4533 | } | |
c906108c SS |
4534 | } |
4535 | return pc; | |
4536 | } | |
4537 | ||
4538 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4539 | if the code at PC does not look like a function prologue; otherwise | |
4540 | returns an address that (if we're lucky) follows the prologue. If | |
4541 | LENIENT, then we must skip everything which is involved in setting | |
4542 | up the frame (it's OK to skip more, just so long as we don't skip | |
4543 | anything which might clobber the registers which are being saved. | |
4544 | We must skip more in the case where part of the prologue is in the | |
4545 | delay slot of a non-prologue instruction). */ | |
4546 | ||
f7ab6ec6 | 4547 | static CORE_ADDR |
f7b9e9fc | 4548 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4549 | { |
4550 | /* See if we can determine the end of the prologue via the symbol table. | |
4551 | If so, then return either PC, or the PC after the prologue, whichever | |
4552 | is greater. */ | |
4553 | ||
4554 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4555 | ||
4556 | if (post_prologue_pc != 0) | |
4557 | return max (pc, post_prologue_pc); | |
4558 | ||
4559 | /* Can't determine prologue from the symbol table, need to examine | |
4560 | instructions. */ | |
4561 | ||
4562 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4563 | return mips16_skip_prologue (pc); |
c906108c | 4564 | else |
f7b9e9fc | 4565 | return mips32_skip_prologue (pc); |
c906108c | 4566 | } |
c906108c | 4567 | |
7a292a7a SS |
4568 | /* Determine how a return value is stored within the MIPS register |
4569 | file, given the return type `valtype'. */ | |
4570 | ||
4571 | struct return_value_word | |
4572 | { | |
4573 | int len; | |
4574 | int reg; | |
4575 | int reg_offset; | |
4576 | int buf_offset; | |
4577 | }; | |
4578 | ||
7a292a7a | 4579 | static void |
acdb74a0 AC |
4580 | return_value_location (struct type *valtype, |
4581 | struct return_value_word *hi, | |
4582 | struct return_value_word *lo) | |
7a292a7a SS |
4583 | { |
4584 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4585 | |
7a292a7a SS |
4586 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4587 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4588 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4589 | { | |
4590 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4591 | { | |
4592 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4593 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4594 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4595 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4596 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
56cea623 | 4597 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8) |
7a292a7a SS |
4598 | ? 4 : 0); |
4599 | hi->reg_offset = lo->reg_offset; | |
56cea623 AC |
4600 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; |
4601 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
7a292a7a SS |
4602 | lo->len = 4; |
4603 | hi->len = 4; | |
4604 | } | |
4605 | else | |
4606 | { | |
4607 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4608 | register. */ |
d7449b42 | 4609 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
56cea623 | 4610 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8 |
7a292a7a SS |
4611 | && len == 4) |
4612 | ? 4 : 0); | |
56cea623 | 4613 | lo->reg = mips_regnum (current_gdbarch)->fp0; |
7a292a7a SS |
4614 | lo->len = len; |
4615 | lo->buf_offset = 0; | |
4616 | hi->len = 0; | |
4617 | hi->reg_offset = 0; | |
4618 | hi->buf_offset = 0; | |
4619 | hi->reg = 0; | |
4620 | } | |
4621 | } | |
4622 | else | |
4623 | { | |
4624 | /* Locate a result possibly spread across two registers. */ | |
4625 | int regnum = 2; | |
4626 | lo->reg = regnum + 0; | |
4627 | hi->reg = regnum + 1; | |
d7449b42 | 4628 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4629 | && len < MIPS_SAVED_REGSIZE) |
4630 | { | |
bf1f5b4c MS |
4631 | /* "un-left-justify" the value in the low register */ |
4632 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4633 | lo->len = len; |
bf1f5b4c | 4634 | hi->reg_offset = 0; |
7a292a7a SS |
4635 | hi->len = 0; |
4636 | } | |
d7449b42 | 4637 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4638 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4639 | && len < MIPS_SAVED_REGSIZE * 2 | |
4640 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4641 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4642 | { | |
4643 | /* "un-left-justify" the value spread across two registers. */ | |
4644 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4645 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4646 | hi->reg_offset = 0; | |
4647 | hi->len = len - lo->len; | |
4648 | } | |
4649 | else | |
4650 | { | |
4651 | /* Only perform a partial copy of the second register. */ | |
4652 | lo->reg_offset = 0; | |
4653 | hi->reg_offset = 0; | |
4654 | if (len > MIPS_SAVED_REGSIZE) | |
4655 | { | |
4656 | lo->len = MIPS_SAVED_REGSIZE; | |
4657 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4658 | } | |
4659 | else | |
4660 | { | |
4661 | lo->len = len; | |
4662 | hi->len = 0; | |
4663 | } | |
4664 | } | |
d7449b42 | 4665 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
719ec221 | 4666 | && register_size (current_gdbarch, regnum) == 8 |
7a292a7a SS |
4667 | && MIPS_SAVED_REGSIZE == 4) |
4668 | { | |
4669 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4670 | of the register is being used */ |
7a292a7a SS |
4671 | lo->reg_offset += 4; |
4672 | hi->reg_offset += 4; | |
4673 | } | |
4674 | lo->buf_offset = 0; | |
4675 | hi->buf_offset = lo->len; | |
4676 | } | |
4677 | } | |
4678 | ||
4679 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4680 | copy its value into `valbuf'. */ | |
4681 | ||
46cac009 AC |
4682 | static void |
4683 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4684 | char regbuf[], |
46cac009 AC |
4685 | char *valbuf) |
4686 | { | |
4687 | struct return_value_word lo; | |
4688 | struct return_value_word hi; | |
4689 | return_value_location (valtype, &hi, &lo); | |
4690 | ||
4691 | memcpy (valbuf + lo.buf_offset, | |
62700349 | 4692 | regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset, |
46cac009 AC |
4693 | lo.len); |
4694 | ||
4695 | if (hi.len > 0) | |
4696 | memcpy (valbuf + hi.buf_offset, | |
62700349 | 4697 | regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset, |
46cac009 AC |
4698 | hi.len); |
4699 | } | |
4700 | ||
46cac009 AC |
4701 | static void |
4702 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4703 | char regbuf[], |
46cac009 AC |
4704 | char *valbuf) |
4705 | { | |
4706 | struct return_value_word lo; | |
4707 | struct return_value_word hi; | |
4708 | return_value_location (valtype, &hi, &lo); | |
4709 | ||
4710 | memcpy (valbuf + lo.buf_offset, | |
62700349 | 4711 | regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset, |
46cac009 AC |
4712 | lo.len); |
4713 | ||
4714 | if (hi.len > 0) | |
4715 | memcpy (valbuf + hi.buf_offset, | |
62700349 | 4716 | regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset, |
46cac009 AC |
4717 | hi.len); |
4718 | } | |
4719 | ||
7a292a7a SS |
4720 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4721 | value into the appropriate register. */ | |
4722 | ||
46cac009 AC |
4723 | static void |
4724 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4725 | { | |
d9d9c31f | 4726 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4727 | struct return_value_word lo; |
4728 | struct return_value_word hi; | |
4729 | return_value_location (valtype, &hi, &lo); | |
4730 | ||
4731 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4732 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4733 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4734 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4735 | |
4736 | if (hi.len > 0) | |
4737 | { | |
4738 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4739 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4740 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4741 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4742 | } |
4743 | } | |
4744 | ||
4745 | static void | |
cb1d2653 | 4746 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4747 | { |
d9d9c31f | 4748 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4749 | struct return_value_word lo; |
4750 | struct return_value_word hi; | |
4751 | return_value_location (valtype, &hi, &lo); | |
4752 | ||
4753 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4754 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4755 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4756 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4757 | |
4758 | if (hi.len > 0) | |
4759 | { | |
4760 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4761 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4762 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4763 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4764 | } |
4765 | } | |
4766 | ||
cb1d2653 AC |
4767 | /* O32 ABI stuff. */ |
4768 | ||
46cac009 | 4769 | static void |
cb1d2653 AC |
4770 | mips_o32_xfer_return_value (struct type *type, |
4771 | struct regcache *regcache, | |
4772 | bfd_byte *in, const bfd_byte *out) | |
46cac009 | 4773 | { |
cb1d2653 AC |
4774 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4775 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4776 | && TYPE_LENGTH (type) == 4 | |
4777 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4778 | { |
cb1d2653 AC |
4779 | /* A single-precision floating-point value. It fits in the |
4780 | least significant part of FP0. */ | |
4781 | if (mips_debug) | |
4782 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
56cea623 | 4783 | mips_xfer_register (regcache, NUM_REGS + mips_regnum (current_gdbarch)->fp0, TYPE_LENGTH (type), |
cb1d2653 AC |
4784 | TARGET_BYTE_ORDER, in, out, 0); |
4785 | } | |
4786 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4787 | && TYPE_LENGTH (type) == 8 | |
4788 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4789 | { | |
a4b8ebc8 AC |
4790 | /* A double-precision floating-point value. The most |
4791 | significant part goes in FP1, and the least significant in | |
4792 | FP0. */ | |
cb1d2653 | 4793 | if (mips_debug) |
a4b8ebc8 | 4794 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
cb1d2653 AC |
4795 | switch (TARGET_BYTE_ORDER) |
4796 | { | |
4797 | case BFD_ENDIAN_LITTLE: | |
56cea623 | 4798 | mips_xfer_register (regcache, NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, 4, |
cb1d2653 | 4799 | TARGET_BYTE_ORDER, in, out, 0); |
56cea623 | 4800 | mips_xfer_register (regcache, NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, 4, |
cb1d2653 AC |
4801 | TARGET_BYTE_ORDER, in, out, 4); |
4802 | break; | |
4803 | case BFD_ENDIAN_BIG: | |
56cea623 | 4804 | mips_xfer_register (regcache, NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, 4, |
cb1d2653 | 4805 | TARGET_BYTE_ORDER, in, out, 0); |
56cea623 | 4806 | mips_xfer_register (regcache, NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, 4, |
cb1d2653 AC |
4807 | TARGET_BYTE_ORDER, in, out, 4); |
4808 | break; | |
4809 | default: | |
4810 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4811 | } | |
4812 | } | |
4813 | #if 0 | |
4814 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4815 | && TYPE_NFIELDS (type) <= 2 | |
4816 | && TYPE_NFIELDS (type) >= 1 | |
4817 | && ((TYPE_NFIELDS (type) == 1 | |
4818 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4819 | == TYPE_CODE_FLT)) | |
4820 | || (TYPE_NFIELDS (type) == 2 | |
4821 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4822 | == TYPE_CODE_FLT) | |
4823 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4824 | == TYPE_CODE_FLT))) | |
4825 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4826 | { | |
4827 | /* A struct that contains one or two floats. Each value is part | |
4828 | in the least significant part of their floating point | |
4829 | register.. */ | |
d9d9c31f | 4830 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4831 | int regnum; |
4832 | int field; | |
56cea623 | 4833 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
cb1d2653 AC |
4834 | field < TYPE_NFIELDS (type); |
4835 | field++, regnum += 2) | |
4836 | { | |
4837 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4838 | / TARGET_CHAR_BIT); | |
4839 | if (mips_debug) | |
4840 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4841 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4842 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
cb1d2653 AC |
4843 | TARGET_BYTE_ORDER, in, out, offset); |
4844 | } | |
4845 | } | |
4846 | #endif | |
4847 | #if 0 | |
4848 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4849 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4850 | { | |
4851 | /* A structure or union. Extract the left justified value, | |
4852 | regardless of the byte order. I.e. DO NOT USE | |
4853 | mips_xfer_lower. */ | |
4854 | int offset; | |
4855 | int regnum; | |
4856 | for (offset = 0, regnum = V0_REGNUM; | |
4857 | offset < TYPE_LENGTH (type); | |
719ec221 | 4858 | offset += register_size (current_gdbarch, regnum), regnum++) |
cb1d2653 | 4859 | { |
719ec221 | 4860 | int xfer = register_size (current_gdbarch, regnum); |
cb1d2653 AC |
4861 | if (offset + xfer > TYPE_LENGTH (type)) |
4862 | xfer = TYPE_LENGTH (type) - offset; | |
4863 | if (mips_debug) | |
4864 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4865 | offset, xfer, regnum); | |
a4b8ebc8 AC |
4866 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
4867 | BFD_ENDIAN_UNKNOWN, in, out, offset); | |
cb1d2653 AC |
4868 | } |
4869 | } | |
4870 | #endif | |
4871 | else | |
4872 | { | |
4873 | /* A scalar extract each part but least-significant-byte | |
4874 | justified. o32 thinks registers are 4 byte, regardless of | |
4875 | the ISA. mips_stack_argsize controls this. */ | |
4876 | int offset; | |
4877 | int regnum; | |
4878 | for (offset = 0, regnum = V0_REGNUM; | |
4879 | offset < TYPE_LENGTH (type); | |
4880 | offset += mips_stack_argsize (), regnum++) | |
4881 | { | |
4882 | int xfer = mips_stack_argsize (); | |
4883 | int pos = 0; | |
4884 | if (offset + xfer > TYPE_LENGTH (type)) | |
4885 | xfer = TYPE_LENGTH (type) - offset; | |
4886 | if (mips_debug) | |
4887 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4888 | offset, xfer, regnum); | |
a4b8ebc8 AC |
4889 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
4890 | TARGET_BYTE_ORDER, in, out, offset); | |
cb1d2653 | 4891 | } |
46cac009 AC |
4892 | } |
4893 | } | |
4894 | ||
cb1d2653 AC |
4895 | static void |
4896 | mips_o32_extract_return_value (struct type *type, | |
4897 | struct regcache *regcache, | |
ebba8386 | 4898 | void *valbuf) |
cb1d2653 AC |
4899 | { |
4900 | mips_o32_xfer_return_value (type, regcache, valbuf, NULL); | |
4901 | } | |
4902 | ||
4903 | static void | |
4904 | mips_o32_store_return_value (struct type *type, char *valbuf) | |
4905 | { | |
4906 | mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf); | |
4907 | } | |
4908 | ||
4909 | /* N32/N44 ABI stuff. */ | |
4910 | ||
46cac009 | 4911 | static void |
88658117 AC |
4912 | mips_n32n64_xfer_return_value (struct type *type, |
4913 | struct regcache *regcache, | |
4914 | bfd_byte *in, const bfd_byte *out) | |
c906108c | 4915 | { |
88658117 AC |
4916 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4917 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4918 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4919 | { |
88658117 AC |
4920 | /* A floating-point value belongs in the least significant part |
4921 | of FP0. */ | |
4922 | if (mips_debug) | |
4923 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
56cea623 | 4924 | mips_xfer_register (regcache, NUM_REGS + mips_regnum (current_gdbarch)->fp0, TYPE_LENGTH (type), |
88658117 AC |
4925 | TARGET_BYTE_ORDER, in, out, 0); |
4926 | } | |
4927 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4928 | && TYPE_NFIELDS (type) <= 2 | |
4929 | && TYPE_NFIELDS (type) >= 1 | |
4930 | && ((TYPE_NFIELDS (type) == 1 | |
4931 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4932 | == TYPE_CODE_FLT)) | |
4933 | || (TYPE_NFIELDS (type) == 2 | |
4934 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4935 | == TYPE_CODE_FLT) | |
4936 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4937 | == TYPE_CODE_FLT))) | |
4938 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4939 | { | |
4940 | /* A struct that contains one or two floats. Each value is part | |
4941 | in the least significant part of their floating point | |
4942 | register.. */ | |
d9d9c31f | 4943 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4944 | int regnum; |
4945 | int field; | |
56cea623 | 4946 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
88658117 AC |
4947 | field < TYPE_NFIELDS (type); |
4948 | field++, regnum += 2) | |
4949 | { | |
4950 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4951 | / TARGET_CHAR_BIT); | |
4952 | if (mips_debug) | |
4953 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4954 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4955 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
88658117 AC |
4956 | TARGET_BYTE_ORDER, in, out, offset); |
4957 | } | |
7a292a7a | 4958 | } |
88658117 AC |
4959 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4960 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4961 | { | |
4962 | /* A structure or union. Extract the left justified value, | |
4963 | regardless of the byte order. I.e. DO NOT USE | |
4964 | mips_xfer_lower. */ | |
4965 | int offset; | |
4966 | int regnum; | |
4967 | for (offset = 0, regnum = V0_REGNUM; | |
4968 | offset < TYPE_LENGTH (type); | |
719ec221 | 4969 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 4970 | { |
719ec221 | 4971 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
4972 | if (offset + xfer > TYPE_LENGTH (type)) |
4973 | xfer = TYPE_LENGTH (type) - offset; | |
4974 | if (mips_debug) | |
4975 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4976 | offset, xfer, regnum); | |
a4b8ebc8 AC |
4977 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
4978 | BFD_ENDIAN_UNKNOWN, in, out, offset); | |
88658117 AC |
4979 | } |
4980 | } | |
4981 | else | |
4982 | { | |
4983 | /* A scalar extract each part but least-significant-byte | |
4984 | justified. */ | |
4985 | int offset; | |
4986 | int regnum; | |
4987 | for (offset = 0, regnum = V0_REGNUM; | |
4988 | offset < TYPE_LENGTH (type); | |
719ec221 | 4989 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 4990 | { |
719ec221 | 4991 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
4992 | int pos = 0; |
4993 | if (offset + xfer > TYPE_LENGTH (type)) | |
4994 | xfer = TYPE_LENGTH (type) - offset; | |
4995 | if (mips_debug) | |
4996 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4997 | offset, xfer, regnum); | |
a4b8ebc8 AC |
4998 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
4999 | TARGET_BYTE_ORDER, in, out, offset); | |
88658117 AC |
5000 | } |
5001 | } | |
5002 | } | |
5003 | ||
5004 | static void | |
5005 | mips_n32n64_extract_return_value (struct type *type, | |
5006 | struct regcache *regcache, | |
ebba8386 | 5007 | void *valbuf) |
88658117 AC |
5008 | { |
5009 | mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); | |
5010 | } | |
5011 | ||
5012 | static void | |
5013 | mips_n32n64_store_return_value (struct type *type, char *valbuf) | |
5014 | { | |
5015 | mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); | |
c906108c SS |
5016 | } |
5017 | ||
2f1488ce | 5018 | static CORE_ADDR |
6672060b | 5019 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
5020 | { |
5021 | /* FIXME: This will only work at random. The caller passes the | |
5022 | struct_return address in V0, but it is not preserved. It may | |
5023 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
5024 | LONGEST val; |
5025 | ||
5026 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 5027 | return val; |
2f1488ce MS |
5028 | } |
5029 | ||
c906108c SS |
5030 | /* Exported procedure: Is PC in the signal trampoline code */ |
5031 | ||
102182a9 MS |
5032 | static int |
5033 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5034 | { |
5035 | if (sigtramp_address == 0) | |
5036 | fixup_sigtramp (); | |
5037 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5038 | } | |
5039 | ||
a5ea2558 AC |
5040 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5041 | used for all MIPS-specific commands. */ | |
5042 | ||
a5ea2558 | 5043 | static void |
acdb74a0 | 5044 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5045 | { |
5046 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5047 | } | |
5048 | ||
a5ea2558 | 5049 | static void |
acdb74a0 | 5050 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5051 | { |
5052 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
5053 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
5054 | } | |
5055 | ||
c906108c SS |
5056 | /* Commands to show/set the MIPS FPU type. */ |
5057 | ||
c906108c | 5058 | static void |
acdb74a0 | 5059 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5060 | { |
c906108c SS |
5061 | char *fpu; |
5062 | switch (MIPS_FPU_TYPE) | |
5063 | { | |
5064 | case MIPS_FPU_SINGLE: | |
5065 | fpu = "single-precision"; | |
5066 | break; | |
5067 | case MIPS_FPU_DOUBLE: | |
5068 | fpu = "double-precision"; | |
5069 | break; | |
5070 | case MIPS_FPU_NONE: | |
5071 | fpu = "absent (none)"; | |
5072 | break; | |
93d56215 AC |
5073 | default: |
5074 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5075 | } |
5076 | if (mips_fpu_type_auto) | |
5077 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5078 | fpu); | |
5079 | else | |
5080 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
5081 | fpu); | |
5082 | } | |
5083 | ||
5084 | ||
c906108c | 5085 | static void |
acdb74a0 | 5086 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5087 | { |
5088 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5089 | show_mipsfpu_command (args, from_tty); | |
5090 | } | |
5091 | ||
c906108c | 5092 | static void |
acdb74a0 | 5093 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
5094 | { |
5095 | mips_fpu_type = MIPS_FPU_SINGLE; | |
5096 | mips_fpu_type_auto = 0; | |
9e364162 | 5097 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5098 | } |
5099 | ||
c906108c | 5100 | static void |
acdb74a0 | 5101 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5102 | { |
5103 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5104 | mips_fpu_type_auto = 0; | |
9e364162 | 5105 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5106 | } |
5107 | ||
c906108c | 5108 | static void |
acdb74a0 | 5109 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5110 | { |
5111 | mips_fpu_type = MIPS_FPU_NONE; | |
5112 | mips_fpu_type_auto = 0; | |
9e364162 | 5113 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5114 | } |
5115 | ||
c906108c | 5116 | static void |
acdb74a0 | 5117 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5118 | { |
5119 | mips_fpu_type_auto = 1; | |
5120 | } | |
5121 | ||
5122 | /* Command to set the processor type. */ | |
5123 | ||
5124 | void | |
acdb74a0 | 5125 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
5126 | { |
5127 | int i; | |
5128 | ||
5129 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
5130 | { | |
5131 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
5132 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5133 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
5134 | ||
5135 | /* Restore the value. */ | |
4fcf66da | 5136 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5137 | |
5138 | return; | |
5139 | } | |
c5aa993b | 5140 | |
c906108c SS |
5141 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
5142 | { | |
5143 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
5144 | /* Restore its value. */ | |
4fcf66da | 5145 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5146 | } |
5147 | } | |
5148 | ||
5149 | static void | |
acdb74a0 | 5150 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
5151 | { |
5152 | } | |
5153 | ||
5154 | /* Modify the actual processor type. */ | |
5155 | ||
5a89d8aa | 5156 | static int |
acdb74a0 | 5157 | mips_set_processor_type (char *str) |
c906108c | 5158 | { |
1012bd0e | 5159 | int i; |
c906108c SS |
5160 | |
5161 | if (str == NULL) | |
5162 | return 0; | |
5163 | ||
5164 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5165 | { | |
5166 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
5167 | { | |
5168 | mips_processor_type = str; | |
cce74817 | 5169 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 5170 | return 1; |
c906108c SS |
5171 | /* FIXME tweak fpu flag too */ |
5172 | } | |
5173 | } | |
5174 | ||
5175 | return 0; | |
5176 | } | |
5177 | ||
5178 | /* Attempt to identify the particular processor model by reading the | |
5179 | processor id. */ | |
5180 | ||
5181 | char * | |
acdb74a0 | 5182 | mips_read_processor_type (void) |
c906108c SS |
5183 | { |
5184 | CORE_ADDR prid; | |
5185 | ||
5186 | prid = read_register (PRID_REGNUM); | |
5187 | ||
5188 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 5189 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
5190 | |
5191 | return NULL; | |
5192 | } | |
5193 | ||
5194 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5195 | callable as an sfunc. */ | |
5196 | ||
5197 | static void | |
acdb74a0 AC |
5198 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5199 | struct cmd_list_element *c) | |
c906108c SS |
5200 | { |
5201 | reinit_frame_cache (); | |
5202 | } | |
5203 | ||
a89aa300 AC |
5204 | static int |
5205 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5206 | { |
e5ab0dce | 5207 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5208 | mips_extra_func_info_t proc_desc; |
5209 | ||
5210 | /* Search for the function containing this address. Set the low bit | |
5211 | of the address when searching, in case we were given an even address | |
5212 | that is the start of a 16-bit function. If we didn't do this, | |
5213 | the search would fail because the symbol table says the function | |
5214 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5215 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5216 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5217 | |
5218 | /* Make an attempt to determine if this is a 16-bit function. If | |
5219 | the procedure descriptor exists and the address therein is odd, | |
5220 | it's definitely a 16-bit function. Otherwise, we have to just | |
5221 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5222 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5223 | disassembler needs to be able to locally determine the ISA, and | |
5224 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5225 | work. */ | |
c906108c | 5226 | if (proc_desc) |
d31431ed AC |
5227 | { |
5228 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
5229 | info->mach = bfd_mach_mips16; | |
5230 | } | |
c906108c | 5231 | else |
d31431ed AC |
5232 | { |
5233 | if (pc_is_mips16 (memaddr)) | |
5234 | info->mach = bfd_mach_mips16; | |
5235 | } | |
c906108c SS |
5236 | |
5237 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5238 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5239 | |
e5ab0dce AC |
5240 | /* Set the disassembler options. */ |
5241 | if (tdep->mips_abi == MIPS_ABI_N32 | |
5242 | || tdep->mips_abi == MIPS_ABI_N64) | |
5243 | { | |
5244 | /* Set up the disassembler info, so that we get the right | |
5245 | register names from libopcodes. */ | |
5246 | if (tdep->mips_abi == MIPS_ABI_N32) | |
5247 | info->disassembler_options = "gpr-names=n32"; | |
5248 | else | |
5249 | info->disassembler_options = "gpr-names=64"; | |
5250 | info->flavour = bfd_target_elf_flavour; | |
5251 | } | |
5252 | else | |
5253 | /* This string is not recognized explicitly by the disassembler, | |
5254 | but it tells the disassembler to not try to guess the ABI from | |
5255 | the bfd elf headers, such that, if the user overrides the ABI | |
5256 | of a program linked as NewABI, the disassembly will follow the | |
5257 | register naming conventions specified by the user. */ | |
5258 | info->disassembler_options = "gpr-names=32"; | |
5259 | ||
c906108c | 5260 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5261 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5262 | return print_insn_big_mips (memaddr, info); |
5263 | else | |
5264 | return print_insn_little_mips (memaddr, info); | |
5265 | } | |
5266 | ||
c906108c SS |
5267 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5268 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5269 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5270 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5271 | (if necessary) to point to the actual memory location where the | |
5272 | breakpoint should be inserted. */ | |
5273 | ||
f7ab6ec6 | 5274 | static const unsigned char * |
acdb74a0 | 5275 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5276 | { |
d7449b42 | 5277 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5278 | { |
5279 | if (pc_is_mips16 (*pcptr)) | |
5280 | { | |
aaab4dba | 5281 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5282 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5283 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5284 | return mips16_big_breakpoint; |
5285 | } | |
5286 | else | |
5287 | { | |
aaab4dba AC |
5288 | /* The IDT board uses an unusual breakpoint value, and |
5289 | sometimes gets confused when it sees the usual MIPS | |
5290 | breakpoint instruction. */ | |
5291 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5292 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5293 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5294 | |
c5aa993b | 5295 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5296 | |
5297 | if (strcmp (target_shortname, "mips") == 0) | |
5298 | return idt_big_breakpoint; | |
5299 | else if (strcmp (target_shortname, "ddb") == 0 | |
5300 | || strcmp (target_shortname, "pmon") == 0 | |
5301 | || strcmp (target_shortname, "lsi") == 0) | |
5302 | return pmon_big_breakpoint; | |
5303 | else | |
5304 | return big_breakpoint; | |
5305 | } | |
5306 | } | |
5307 | else | |
5308 | { | |
5309 | if (pc_is_mips16 (*pcptr)) | |
5310 | { | |
aaab4dba | 5311 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5312 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5313 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5314 | return mips16_little_breakpoint; |
5315 | } | |
5316 | else | |
5317 | { | |
aaab4dba AC |
5318 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5319 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5320 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5321 | |
c5aa993b | 5322 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5323 | |
5324 | if (strcmp (target_shortname, "mips") == 0) | |
5325 | return idt_little_breakpoint; | |
5326 | else if (strcmp (target_shortname, "ddb") == 0 | |
5327 | || strcmp (target_shortname, "pmon") == 0 | |
5328 | || strcmp (target_shortname, "lsi") == 0) | |
5329 | return pmon_little_breakpoint; | |
5330 | else | |
5331 | return little_breakpoint; | |
5332 | } | |
5333 | } | |
5334 | } | |
5335 | ||
5336 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5337 | PC, which is either the callee or the caller. There are several | |
5338 | cases which must be handled: | |
5339 | ||
5340 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5341 | target PC is in $31 ($ra). |
c906108c | 5342 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5343 | and the target PC is in $2. |
c906108c | 5344 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5345 | before the jal instruction, this is effectively a call stub |
5346 | and the the target PC is in $2. Otherwise this is effectively | |
5347 | a return stub and the target PC is in $18. | |
c906108c SS |
5348 | |
5349 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5350 | gory details. | |
5351 | ||
5352 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5353 | */ |
c906108c | 5354 | |
757a7cc6 | 5355 | static CORE_ADDR |
acdb74a0 | 5356 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5357 | { |
5358 | char *name; | |
5359 | CORE_ADDR start_addr; | |
5360 | ||
5361 | /* Find the starting address and name of the function containing the PC. */ | |
5362 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5363 | return 0; | |
5364 | ||
5365 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5366 | target PC is in $31 ($ra). */ | |
5367 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5368 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5369 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5370 | |
5371 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5372 | { | |
5373 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5374 | and the target PC is in $2. */ | |
5375 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5376 | return read_signed_register (2); |
c906108c SS |
5377 | |
5378 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5379 | before the jal instruction, this is effectively a call stub |
5380 | and the the target PC is in $2. Otherwise this is effectively | |
5381 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5382 | else if (name[19] == 's' || name[19] == 'd') |
5383 | { | |
5384 | if (pc == start_addr) | |
5385 | { | |
5386 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5387 | stub. Such a stub for a function bar might have a name |
5388 | like __fn_stub_bar, and might look like this: | |
5389 | mfc1 $4,$f13 | |
5390 | mfc1 $5,$f12 | |
5391 | mfc1 $6,$f15 | |
5392 | mfc1 $7,$f14 | |
5393 | la $1,bar (becomes a lui/addiu pair) | |
5394 | jr $1 | |
5395 | So scan down to the lui/addi and extract the target | |
5396 | address from those two instructions. */ | |
c906108c | 5397 | |
6c997a34 | 5398 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5399 | t_inst inst; |
5400 | int i; | |
5401 | ||
5402 | /* See if the name of the target function is __fn_stub_*. */ | |
5403 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5404 | return target_pc; | |
5405 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5406 | && strcmp (name, "etext") != 0 | |
5407 | && strcmp (name, "_etext") != 0) | |
5408 | return target_pc; | |
5409 | ||
5410 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5411 | The limit on the search is arbitrarily set to 20 |
5412 | instructions. FIXME. */ | |
c906108c SS |
5413 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5414 | { | |
c5aa993b JM |
5415 | inst = mips_fetch_instruction (target_pc); |
5416 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5417 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5418 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5419 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5420 | } |
5421 | ||
5422 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5423 | return target_pc; | |
5424 | } | |
5425 | else | |
5426 | /* This is the 'return' part of a call stub. The return | |
5427 | address is in $r18. */ | |
6c997a34 | 5428 | return read_signed_register (18); |
c906108c SS |
5429 | } |
5430 | } | |
c5aa993b | 5431 | return 0; /* not a stub */ |
c906108c SS |
5432 | } |
5433 | ||
5434 | ||
5435 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5436 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5437 | ||
757a7cc6 | 5438 | static int |
acdb74a0 | 5439 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5440 | { |
5441 | CORE_ADDR start_addr; | |
5442 | ||
5443 | /* Find the starting address of the function containing the PC. If the | |
5444 | caller didn't give us a name, look it up at the same time. */ | |
5445 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5446 | return 0; | |
5447 | ||
5448 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5449 | { | |
5450 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5451 | if (name[19] >= '0' && name[19] <= '9') | |
5452 | return 1; | |
5453 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5454 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5455 | else if (name[19] == 's' || name[19] == 'd') |
5456 | return pc == start_addr; | |
5457 | } | |
5458 | ||
c5aa993b | 5459 | return 0; /* not a stub */ |
c906108c SS |
5460 | } |
5461 | ||
5462 | ||
5463 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5464 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5465 | ||
e41b17f0 | 5466 | static int |
acdb74a0 | 5467 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5468 | { |
5469 | CORE_ADDR start_addr; | |
5470 | ||
5471 | /* Find the starting address of the function containing the PC. */ | |
5472 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5473 | return 0; | |
5474 | ||
5475 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5476 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5477 | || strcmp (name, "__mips16_ret_df") == 0) | |
5478 | return 1; | |
5479 | ||
5480 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5481 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5482 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5483 | && (name[19] == 's' || name[19] == 'd') | |
5484 | && pc != start_addr) | |
5485 | return 1; | |
5486 | ||
c5aa993b | 5487 | return 0; /* not a stub */ |
c906108c SS |
5488 | } |
5489 | ||
5490 | ||
5491 | /* Return non-zero if the PC is in a library helper function that should | |
5492 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5493 | ||
5494 | int | |
acdb74a0 | 5495 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5496 | { |
5497 | char *name; | |
5498 | ||
5499 | /* Find the starting address and name of the function containing the PC. */ | |
5500 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5501 | return 0; | |
5502 | ||
5503 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5504 | that we want to ignore. */ | |
5505 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5506 | || strcmp (name, "__mips16_ret_df") == 0); | |
5507 | } | |
5508 | ||
5509 | ||
47a8d4ba AC |
5510 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5511 | the register stored on the stack (32) is different to its real raw | |
5512 | size (64). The below ensures that registers are fetched from the | |
5513 | stack using their ABI size and then stored into the RAW_BUFFER | |
5514 | using their raw size. | |
5515 | ||
5516 | The alternative to adding this function would be to add an ABI | |
5517 | macro - REGISTER_STACK_SIZE(). */ | |
5518 | ||
5519 | static void | |
acdb74a0 | 5520 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5521 | int *optimizedp, |
acdb74a0 AC |
5522 | CORE_ADDR *addrp, |
5523 | struct frame_info *frame, | |
5524 | int regnum, | |
795e1e11 | 5525 | enum lval_type *lvalp) |
47a8d4ba | 5526 | { |
795e1e11 AC |
5527 | CORE_ADDR addrx; |
5528 | enum lval_type lvalx; | |
5529 | int optimizedx; | |
6e51443a | 5530 | int realnumx; |
47a8d4ba | 5531 | |
a4b8ebc8 AC |
5532 | /* Always a pseudo. */ |
5533 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5534 | |
795e1e11 AC |
5535 | /* Make certain that all needed parameters are present. */ |
5536 | if (addrp == NULL) | |
5537 | addrp = &addrx; | |
5538 | if (lvalp == NULL) | |
5539 | lvalp = &lvalx; | |
5540 | if (optimizedp == NULL) | |
5541 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5542 | |
5543 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5544 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5545 | In fact, it is so special that it can even only be fetched | |
5546 | using a raw register number! Once this code as been converted | |
5547 | to frame-unwind the problem goes away. */ | |
5548 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5549 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5550 | &realnumx, raw_buffer); | |
5551 | else | |
5552 | /* Get it from the next frame. */ | |
5553 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5554 | regnum, optimizedp, lvalp, addrp, | |
5555 | &realnumx, raw_buffer); | |
47a8d4ba | 5556 | } |
2acceee2 | 5557 | |
f7b9e9fc AC |
5558 | /* Immediately after a function call, return the saved pc. |
5559 | Can't always go through the frames for this because on some machines | |
5560 | the new frame is not set up until the new function executes | |
5561 | some instructions. */ | |
5562 | ||
5563 | static CORE_ADDR | |
5564 | mips_saved_pc_after_call (struct frame_info *frame) | |
5565 | { | |
6c997a34 | 5566 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5567 | } |
5568 | ||
5569 | ||
a4b8ebc8 AC |
5570 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5571 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5572 | |
5573 | static int | |
5574 | mips_stab_reg_to_regnum (int num) | |
5575 | { | |
a4b8ebc8 | 5576 | int regnum; |
2f38ef89 | 5577 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5578 | regnum = num; |
2f38ef89 | 5579 | else if (num >= 38 && num < 70) |
56cea623 | 5580 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5581 | else if (num == 70) |
56cea623 | 5582 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5583 | else if (num == 71) |
56cea623 | 5584 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5585 | else |
a4b8ebc8 AC |
5586 | /* This will hopefully (eventually) provoke a warning. Should |
5587 | we be calling complaint() here? */ | |
5588 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5589 | return NUM_REGS + regnum; | |
88c72b7d AC |
5590 | } |
5591 | ||
2f38ef89 | 5592 | |
a4b8ebc8 AC |
5593 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5594 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5595 | |
5596 | static int | |
2f38ef89 | 5597 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5598 | { |
a4b8ebc8 | 5599 | int regnum; |
2f38ef89 | 5600 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5601 | regnum = num; |
2f38ef89 | 5602 | else if (num >= 32 && num < 64) |
56cea623 | 5603 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5604 | else if (num == 64) |
56cea623 | 5605 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5606 | else if (num == 65) |
56cea623 | 5607 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5608 | else |
a4b8ebc8 AC |
5609 | /* This will hopefully (eventually) provoke a warning. Should we |
5610 | be calling complaint() here? */ | |
5611 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5612 | return NUM_REGS + regnum; | |
5613 | } | |
5614 | ||
5615 | static int | |
5616 | mips_register_sim_regno (int regnum) | |
5617 | { | |
5618 | /* Only makes sense to supply raw registers. */ | |
5619 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5620 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5621 | decide if it is valid. Should instead define a standard sim/gdb | |
5622 | register numbering scheme. */ | |
5623 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5624 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5625 | return regnum; | |
5626 | else | |
5627 | return LEGACY_SIM_REGNO_IGNORE; | |
88c72b7d AC |
5628 | } |
5629 | ||
2f38ef89 | 5630 | |
fc0c74b1 AC |
5631 | /* Convert an integer into an address. By first converting the value |
5632 | into a pointer and then extracting it signed, the address is | |
5633 | guarenteed to be correctly sign extended. */ | |
5634 | ||
5635 | static CORE_ADDR | |
5636 | mips_integer_to_address (struct type *type, void *buf) | |
5637 | { | |
5638 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5639 | LONGEST val = unpack_long (type, buf); | |
5640 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5641 | return extract_signed_integer (tmp, | |
5642 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5643 | } | |
5644 | ||
caaa3122 DJ |
5645 | static void |
5646 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5647 | { | |
5648 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5649 | const char *name = bfd_get_section_name (abfd, sect); | |
5650 | ||
5651 | if (*abip != MIPS_ABI_UNKNOWN) | |
5652 | return; | |
5653 | ||
5654 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5655 | return; | |
5656 | ||
5657 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5658 | *abip = MIPS_ABI_O32; | |
5659 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5660 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5661 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5662 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5663 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5664 | *abip = MIPS_ABI_O64; | |
5665 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5666 | *abip = MIPS_ABI_EABI32; | |
5667 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5668 | *abip = MIPS_ABI_EABI64; | |
5669 | else | |
5670 | warning ("unsupported ABI %s.", name + 8); | |
5671 | } | |
5672 | ||
2e4ebe70 DJ |
5673 | static enum mips_abi |
5674 | global_mips_abi (void) | |
5675 | { | |
5676 | int i; | |
5677 | ||
5678 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5679 | if (mips_abi_strings[i] == mips_abi_string) | |
5680 | return (enum mips_abi) i; | |
5681 | ||
5682 | internal_error (__FILE__, __LINE__, | |
5683 | "unknown ABI string"); | |
5684 | } | |
5685 | ||
c2d11a7d | 5686 | static struct gdbarch * |
acdb74a0 AC |
5687 | mips_gdbarch_init (struct gdbarch_info info, |
5688 | struct gdbarch_list *arches) | |
c2d11a7d | 5689 | { |
c2d11a7d JM |
5690 | struct gdbarch *gdbarch; |
5691 | struct gdbarch_tdep *tdep; | |
5692 | int elf_flags; | |
2e4ebe70 | 5693 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5694 | int num_regs; |
c2d11a7d | 5695 | |
70f80edf JT |
5696 | elf_flags = 0; |
5697 | ||
5698 | if (info.abfd) | |
5699 | { | |
5700 | /* First of all, extract the elf_flags, if available. */ | |
5701 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5702 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5703 | } |
c2d11a7d | 5704 | |
102182a9 | 5705 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5706 | switch ((elf_flags & EF_MIPS_ABI)) |
5707 | { | |
5708 | case E_MIPS_ABI_O32: | |
5709 | mips_abi = MIPS_ABI_O32; | |
5710 | break; | |
5711 | case E_MIPS_ABI_O64: | |
5712 | mips_abi = MIPS_ABI_O64; | |
5713 | break; | |
5714 | case E_MIPS_ABI_EABI32: | |
5715 | mips_abi = MIPS_ABI_EABI32; | |
5716 | break; | |
5717 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5718 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5719 | break; |
5720 | default: | |
acdb74a0 AC |
5721 | if ((elf_flags & EF_MIPS_ABI2)) |
5722 | mips_abi = MIPS_ABI_N32; | |
5723 | else | |
5724 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5725 | break; |
5726 | } | |
acdb74a0 | 5727 | |
caaa3122 DJ |
5728 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5729 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5730 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5731 | ||
2e4ebe70 DJ |
5732 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5733 | Use the ABI from the last architecture if there is one. */ | |
5734 | if (info.abfd == NULL && arches != NULL) | |
5735 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5736 | ||
32a6503c | 5737 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5738 | if (mips_abi == MIPS_ABI_UNKNOWN |
5739 | && info.bfd_arch_info != NULL | |
5740 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5741 | { | |
5742 | switch (info.bfd_arch_info->mach) | |
5743 | { | |
5744 | case bfd_mach_mips3900: | |
5745 | mips_abi = MIPS_ABI_EABI32; | |
5746 | break; | |
5747 | case bfd_mach_mips4100: | |
5748 | case bfd_mach_mips5000: | |
5749 | mips_abi = MIPS_ABI_EABI64; | |
5750 | break; | |
1d06468c EZ |
5751 | case bfd_mach_mips8000: |
5752 | case bfd_mach_mips10000: | |
32a6503c KB |
5753 | /* On Irix, ELF64 executables use the N64 ABI. The |
5754 | pseudo-sections which describe the ABI aren't present | |
5755 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5756 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5757 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5758 | mips_abi = MIPS_ABI_N64; | |
5759 | else | |
5760 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5761 | break; |
bf64bfd6 AC |
5762 | } |
5763 | } | |
2e4ebe70 | 5764 | |
2e4ebe70 DJ |
5765 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5766 | mips_abi = MIPS_ABI_O32; | |
5767 | ||
5768 | /* Now that we have found what the ABI for this binary would be, | |
5769 | check whether the user is overriding it. */ | |
5770 | found_abi = mips_abi; | |
5771 | wanted_abi = global_mips_abi (); | |
5772 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5773 | mips_abi = wanted_abi; | |
5774 | ||
4b9b3959 AC |
5775 | if (gdbarch_debug) |
5776 | { | |
5777 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5778 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5779 | elf_flags); |
4b9b3959 AC |
5780 | fprintf_unfiltered (gdb_stdlog, |
5781 | "mips_gdbarch_init: mips_abi = %d\n", | |
5782 | mips_abi); | |
2e4ebe70 DJ |
5783 | fprintf_unfiltered (gdb_stdlog, |
5784 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5785 | found_abi); | |
4b9b3959 | 5786 | } |
0dadbba0 | 5787 | |
c2d11a7d JM |
5788 | /* try to find a pre-existing architecture */ |
5789 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5790 | arches != NULL; | |
5791 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5792 | { | |
5793 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5794 | using. */ |
9103eae0 | 5795 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5796 | continue; |
9103eae0 | 5797 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5798 | continue; |
719ec221 AC |
5799 | /* Need to be pedantic about which register virtual size is |
5800 | used. */ | |
5801 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5802 | != mips64_transfers_32bit_regs_p) | |
5803 | continue; | |
4be87837 | 5804 | return arches->gdbarch; |
c2d11a7d JM |
5805 | } |
5806 | ||
102182a9 | 5807 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5808 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5809 | gdbarch = gdbarch_alloc (&info, tdep); | |
5810 | tdep->elf_flags = elf_flags; | |
719ec221 | 5811 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
c2d11a7d | 5812 | |
102182a9 | 5813 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5814 | set_gdbarch_short_bit (gdbarch, 16); |
5815 | set_gdbarch_int_bit (gdbarch, 32); | |
5816 | set_gdbarch_float_bit (gdbarch, 32); | |
5817 | set_gdbarch_double_bit (gdbarch, 64); | |
5818 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5819 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5820 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5821 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
2e4ebe70 | 5822 | tdep->found_abi = found_abi; |
0dadbba0 | 5823 | tdep->mips_abi = mips_abi; |
1d06468c | 5824 | |
f7ab6ec6 MS |
5825 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5826 | mips_elf_make_msymbol_special); | |
5827 | ||
56cea623 AC |
5828 | /* Fill in the OS dependant register numbers. */ |
5829 | { | |
5830 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, | |
5831 | struct mips_regnum); | |
5832 | tdep->regnum = regnum; | |
5833 | if (info.osabi == GDB_OSABI_IRIX) | |
5834 | { | |
5835 | regnum->fp0 = 32; | |
5836 | regnum->pc = 64; | |
5837 | regnum->cause = 65; | |
5838 | regnum->badvaddr = 66; | |
5839 | regnum->hi = 67; | |
5840 | regnum->lo = 68; | |
5841 | regnum->fp_control_status = 69; | |
5842 | regnum->fp_implementation_revision = 70; | |
5843 | num_regs = 71; | |
5844 | } | |
5845 | else | |
5846 | { | |
5847 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5848 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5849 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5850 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5851 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5852 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5853 | regnum->fp_control_status = 70; | |
5854 | regnum->fp_implementation_revision = 71; | |
5855 | num_regs = 90; | |
5856 | } | |
5857 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5858 | replaced by read_pc? */ | |
5859 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5860 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5861 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5862 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5863 | } | |
fe29b929 | 5864 | |
0dadbba0 | 5865 | switch (mips_abi) |
c2d11a7d | 5866 | { |
0dadbba0 | 5867 | case MIPS_ABI_O32: |
25ab4790 | 5868 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
ebba8386 | 5869 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); |
cb1d2653 | 5870 | set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); |
a5ea2558 | 5871 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5872 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5873 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5874 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5875 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5876 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5877 | set_gdbarch_long_bit (gdbarch, 32); |
5878 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5879 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5880 | set_gdbarch_deprecated_reg_struct_has_addr |
5881 | (gdbarch, mips_o32_reg_struct_has_addr); | |
cb811fe7 | 5882 | set_gdbarch_use_struct_convention (gdbarch, |
1fd35568 | 5883 | always_use_struct_convention); |
c2d11a7d | 5884 | break; |
0dadbba0 | 5885 | case MIPS_ABI_O64: |
25ab4790 | 5886 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5887 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5888 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5889 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5890 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5891 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5892 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5893 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5894 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5895 | set_gdbarch_long_bit (gdbarch, 32); |
5896 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5897 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5898 | set_gdbarch_deprecated_reg_struct_has_addr |
5899 | (gdbarch, mips_o32_reg_struct_has_addr); | |
b060cbea | 5900 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5901 | break; |
0dadbba0 | 5902 | case MIPS_ABI_EABI32: |
25ab4790 | 5903 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5904 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5905 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5906 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5907 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5908 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5909 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5910 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5911 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5912 | set_gdbarch_long_bit (gdbarch, 32); |
5913 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5914 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5915 | set_gdbarch_deprecated_reg_struct_has_addr |
5916 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5917 | set_gdbarch_use_struct_convention (gdbarch, |
5918 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5919 | break; |
0dadbba0 | 5920 | case MIPS_ABI_EABI64: |
25ab4790 | 5921 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5922 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5923 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5924 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5925 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5926 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5927 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5928 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5929 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5930 | set_gdbarch_long_bit (gdbarch, 64); |
5931 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5932 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5933 | set_gdbarch_deprecated_reg_struct_has_addr |
5934 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5935 | set_gdbarch_use_struct_convention (gdbarch, |
5936 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5937 | break; |
0dadbba0 | 5938 | case MIPS_ABI_N32: |
25ab4790 | 5939 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5940 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5941 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
63db5580 | 5942 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5943 | tdep->mips_default_stack_argsize = 8; |
5944 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5945 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5946 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5947 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5948 | set_gdbarch_long_bit (gdbarch, 32); |
5949 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5950 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5951 | set_gdbarch_use_struct_convention (gdbarch, |
5952 | mips_n32n64_use_struct_convention); | |
2110b94f MK |
5953 | set_gdbarch_deprecated_reg_struct_has_addr |
5954 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5955 | break; |
5956 | case MIPS_ABI_N64: | |
25ab4790 | 5957 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5958 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5959 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
28d169de KB |
5960 | tdep->mips_default_saved_regsize = 8; |
5961 | tdep->mips_default_stack_argsize = 8; | |
5962 | tdep->mips_fp_register_double = 1; | |
5963 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 5964 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5965 | tdep->default_mask_address_p = 0; |
5966 | set_gdbarch_long_bit (gdbarch, 64); | |
5967 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5968 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5969 | set_gdbarch_use_struct_convention (gdbarch, |
5970 | mips_n32n64_use_struct_convention); | |
2110b94f MK |
5971 | set_gdbarch_deprecated_reg_struct_has_addr |
5972 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5973 | break; |
c2d11a7d | 5974 | default: |
2e4ebe70 DJ |
5975 | internal_error (__FILE__, __LINE__, |
5976 | "unknown ABI in switch"); | |
c2d11a7d JM |
5977 | } |
5978 | ||
a5ea2558 AC |
5979 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5980 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5981 | comment: | |
5982 | ||
5983 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5984 | flag in object files because to do so would make it impossible to | |
102182a9 | 5985 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5986 | unnecessarily restrictive. |
361d1df0 | 5987 | |
a5ea2558 AC |
5988 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5989 | but to set this flag before gcc is built with such multilibs will | |
5990 | break too many systems.'' | |
5991 | ||
5992 | But even more unhelpfully, the default linker output target for | |
5993 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5994 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5995 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5996 | this flag to detect 32-bit mode would do the wrong thing given |
5997 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5998 | as 32-bit programs by default. */ |
a5ea2558 | 5999 | |
c2d11a7d JM |
6000 | /* enable/disable the MIPS FPU */ |
6001 | if (!mips_fpu_type_auto) | |
6002 | tdep->mips_fpu_type = mips_fpu_type; | |
6003 | else if (info.bfd_arch_info != NULL | |
6004 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6005 | switch (info.bfd_arch_info->mach) | |
6006 | { | |
b0069a17 | 6007 | case bfd_mach_mips3900: |
c2d11a7d | 6008 | case bfd_mach_mips4100: |
ed9a39eb | 6009 | case bfd_mach_mips4111: |
c2d11a7d JM |
6010 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
6011 | break; | |
bf64bfd6 AC |
6012 | case bfd_mach_mips4650: |
6013 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
6014 | break; | |
c2d11a7d JM |
6015 | default: |
6016 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
6017 | break; | |
6018 | } | |
6019 | else | |
6020 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
6021 | ||
6022 | /* MIPS version of register names. NOTE: At present the MIPS | |
6023 | register name management is part way between the old - | |
77949794 | 6024 | #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr). |
102182a9 | 6025 | Further work on it is required. */ |
c2d11a7d | 6026 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6c997a34 | 6027 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 6028 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 6029 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 6030 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6031 | |
102182a9 MS |
6032 | /* Add/remove bits from an address. The MIPS needs be careful to |
6033 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6034 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6035 | ||
10312cc4 | 6036 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
6037 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
6038 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
10312cc4 | 6039 | |
102182a9 | 6040 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6041 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
6042 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
6043 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6044 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6045 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6046 | |
c2d11a7d | 6047 | /* Initialize a frame */ |
e0f7ec59 | 6048 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 6049 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
6050 | |
6051 | /* MIPS version of CALL_DUMMY */ | |
6052 | ||
9710e734 AC |
6053 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6054 | replaced by a command, and all targets will default to on stack | |
6055 | (regardless of the stack's execute status). */ | |
6056 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
749b82f6 | 6057 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 6058 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 6059 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
781a750d AC |
6060 | set_gdbarch_deprecated_register_convertible (gdbarch, mips_register_convertible); |
6061 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, mips_register_convert_to_virtual); | |
6062 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, mips_register_convert_to_raw); | |
d05285fa | 6063 | |
618ce49f | 6064 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
6065 | set_gdbarch_frameless_function_invocation (gdbarch, |
6066 | generic_frameless_function_invocation_not); | |
8bedc050 | 6067 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
6068 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6069 | ||
129c1cd6 | 6070 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 6071 | |
f7b9e9fc AC |
6072 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6073 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
6074 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
6075 | |
6076 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 6077 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 6078 | |
fc0c74b1 AC |
6079 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6080 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6081 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6082 | |
102182a9 MS |
6083 | set_gdbarch_function_start_offset (gdbarch, 0); |
6084 | ||
a4b8ebc8 | 6085 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6086 | |
e11c53d2 | 6087 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6088 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6089 | |
e5ab0dce AC |
6090 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6091 | ||
3a3bc038 AC |
6092 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6093 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6094 | need to all be folded into the target vector. Since they are | |
6095 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6096 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6097 | is sitting on? */ | |
6098 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6099 | ||
70f80edf | 6100 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6101 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6102 | |
2f1488ce MS |
6103 | set_gdbarch_extract_struct_value_address (gdbarch, |
6104 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6105 | |
6106 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6107 | ||
6108 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6109 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6110 | |
4b9b3959 AC |
6111 | return gdbarch; |
6112 | } | |
6113 | ||
2e4ebe70 DJ |
6114 | static void |
6115 | mips_abi_update (char *ignore_args, int from_tty, | |
6116 | struct cmd_list_element *c) | |
6117 | { | |
6118 | struct gdbarch_info info; | |
6119 | ||
6120 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6121 | mips_gdbarch_init will take care of the rest. */ | |
6122 | gdbarch_info_init (&info); | |
6123 | gdbarch_update_p (info); | |
6124 | } | |
6125 | ||
ad188201 KB |
6126 | /* Print out which MIPS ABI is in use. */ |
6127 | ||
6128 | static void | |
6129 | show_mips_abi (char *ignore_args, int from_tty) | |
6130 | { | |
6131 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6132 | printf_filtered ( | |
6133 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6134 | else | |
6135 | { | |
6136 | enum mips_abi global_abi = global_mips_abi (); | |
6137 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6138 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6139 | ||
6140 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6141 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6142 | actual_abi_str); | |
6143 | else if (global_abi == actual_abi) | |
6144 | printf_filtered ( | |
6145 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6146 | actual_abi_str); | |
6147 | else | |
6148 | { | |
6149 | /* Probably shouldn't happen... */ | |
6150 | printf_filtered ( | |
6151 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6152 | actual_abi_str, | |
6153 | mips_abi_strings[global_abi]); | |
6154 | } | |
6155 | } | |
6156 | } | |
6157 | ||
4b9b3959 AC |
6158 | static void |
6159 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6160 | { | |
6161 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6162 | if (tdep != NULL) | |
c2d11a7d | 6163 | { |
acdb74a0 AC |
6164 | int ef_mips_arch; |
6165 | int ef_mips_32bitmode; | |
6166 | /* determine the ISA */ | |
6167 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6168 | { | |
6169 | case E_MIPS_ARCH_1: | |
6170 | ef_mips_arch = 1; | |
6171 | break; | |
6172 | case E_MIPS_ARCH_2: | |
6173 | ef_mips_arch = 2; | |
6174 | break; | |
6175 | case E_MIPS_ARCH_3: | |
6176 | ef_mips_arch = 3; | |
6177 | break; | |
6178 | case E_MIPS_ARCH_4: | |
93d56215 | 6179 | ef_mips_arch = 4; |
acdb74a0 AC |
6180 | break; |
6181 | default: | |
93d56215 | 6182 | ef_mips_arch = 0; |
acdb74a0 AC |
6183 | break; |
6184 | } | |
6185 | /* determine the size of a pointer */ | |
6186 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6187 | fprintf_unfiltered (file, |
6188 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6189 | tdep->elf_flags); |
4b9b3959 | 6190 | fprintf_unfiltered (file, |
acdb74a0 AC |
6191 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6192 | ef_mips_32bitmode); | |
6193 | fprintf_unfiltered (file, | |
6194 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6195 | ef_mips_arch); | |
6196 | fprintf_unfiltered (file, | |
6197 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6198 | tdep->mips_abi, | |
2e4ebe70 | 6199 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6200 | fprintf_unfiltered (file, |
6201 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6202 | mips_mask_address_p (), | |
6203 | tdep->default_mask_address_p); | |
c2d11a7d | 6204 | } |
4b9b3959 AC |
6205 | fprintf_unfiltered (file, |
6206 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6207 | FP_REGISTER_DOUBLE); | |
6208 | fprintf_unfiltered (file, | |
6209 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6210 | MIPS_DEFAULT_FPU_TYPE, | |
6211 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6212 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6213 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6214 | : "???")); | |
6215 | fprintf_unfiltered (file, | |
6216 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6217 | MIPS_EABI); | |
4b9b3959 AC |
6218 | fprintf_unfiltered (file, |
6219 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6220 | MIPS_FPU_TYPE, | |
6221 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6222 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6223 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6224 | : "???")); | |
6225 | fprintf_unfiltered (file, | |
6226 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6227 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6228 | fprintf_unfiltered (file, |
6229 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6230 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6231 | fprintf_unfiltered (file, |
6232 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6233 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6234 | fprintf_unfiltered (file, | |
6235 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6236 | MIPS_STACK_ARGSIZE); | |
2475bac3 AC |
6237 | fprintf_unfiltered (file, |
6238 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6239 | A0_REGNUM); | |
6240 | fprintf_unfiltered (file, | |
6241 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6242 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6243 | fprintf_unfiltered (file, | |
6244 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6245 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6246 | fprintf_unfiltered (file, |
6247 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6248 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6249 | fprintf_unfiltered (file, | |
6250 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6251 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6252 | fprintf_unfiltered (file, |
6253 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6254 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
6255 | fprintf_unfiltered (file, |
6256 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6257 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6258 | fprintf_unfiltered (file, |
6259 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6260 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6261 | fprintf_unfiltered (file, | |
6262 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6263 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6264 | fprintf_unfiltered (file, |
6265 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6266 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6267 | #ifdef MACHINE_CPROC_FP_OFFSET |
6268 | fprintf_unfiltered (file, | |
6269 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6270 | MACHINE_CPROC_FP_OFFSET); | |
6271 | #endif | |
6272 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6273 | fprintf_unfiltered (file, | |
6274 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6275 | MACHINE_CPROC_PC_OFFSET); | |
6276 | #endif | |
6277 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6278 | fprintf_unfiltered (file, | |
6279 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6280 | MACHINE_CPROC_SP_OFFSET); | |
6281 | #endif | |
2475bac3 AC |
6282 | fprintf_unfiltered (file, |
6283 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6284 | MIPS16_INSTLEN); | |
2475bac3 AC |
6285 | fprintf_unfiltered (file, |
6286 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6287 | fprintf_unfiltered (file, | |
6288 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6289 | fprintf_unfiltered (file, | |
6290 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6291 | MIPS_INSTLEN); | |
6292 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6293 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6294 | MIPS_LAST_ARG_REGNUM, | |
6295 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6296 | fprintf_unfiltered (file, |
6297 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6298 | MIPS_NUMREGS); | |
6299 | fprintf_unfiltered (file, | |
6300 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
6301 | fprintf_unfiltered (file, | |
6302 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6303 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6304 | fprintf_unfiltered (file, |
6305 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6306 | PRID_REGNUM); | |
2475bac3 AC |
6307 | fprintf_unfiltered (file, |
6308 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6309 | fprintf_unfiltered (file, | |
6310 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6311 | fprintf_unfiltered (file, | |
6312 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6313 | fprintf_unfiltered (file, | |
6314 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6315 | fprintf_unfiltered (file, | |
6316 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6317 | fprintf_unfiltered (file, | |
6318 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6319 | fprintf_unfiltered (file, | |
6320 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6321 | fprintf_unfiltered (file, | |
6322 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6323 | fprintf_unfiltered (file, | |
6324 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6325 | fprintf_unfiltered (file, | |
6326 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6327 | fprintf_unfiltered (file, | |
6328 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6329 | fprintf_unfiltered (file, | |
6330 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6331 | fprintf_unfiltered (file, | |
6332 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6333 | PS_REGNUM); | |
2475bac3 AC |
6334 | fprintf_unfiltered (file, |
6335 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6336 | RA_REGNUM); | |
2475bac3 AC |
6337 | #ifdef SAVED_BYTES |
6338 | fprintf_unfiltered (file, | |
6339 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6340 | SAVED_BYTES); | |
6341 | #endif | |
6342 | #ifdef SAVED_FP | |
6343 | fprintf_unfiltered (file, | |
6344 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6345 | SAVED_FP); | |
6346 | #endif | |
6347 | #ifdef SAVED_PC | |
6348 | fprintf_unfiltered (file, | |
6349 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6350 | SAVED_PC); | |
6351 | #endif | |
6352 | fprintf_unfiltered (file, | |
6353 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6354 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6355 | fprintf_unfiltered (file, | |
6356 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6357 | fprintf_unfiltered (file, | |
6358 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6359 | SIGFRAME_BASE); | |
6360 | fprintf_unfiltered (file, | |
6361 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6362 | SIGFRAME_FPREGSAVE_OFF); | |
6363 | fprintf_unfiltered (file, | |
6364 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6365 | SIGFRAME_PC_OFF); | |
6366 | fprintf_unfiltered (file, | |
6367 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6368 | SIGFRAME_REGSAVE_OFF); | |
6369 | fprintf_unfiltered (file, | |
6370 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
6371 | SIGFRAME_REG_SIZE); | |
6372 | fprintf_unfiltered (file, | |
6373 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6374 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6375 | fprintf_unfiltered (file, | |
6376 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6377 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6378 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6379 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6380 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6381 | fprintf_unfiltered (file, |
6382 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6383 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6384 | #ifdef STACK_END_ADDR | |
6385 | fprintf_unfiltered (file, | |
6386 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6387 | STACK_END_ADDR); | |
6388 | #endif | |
6389 | fprintf_unfiltered (file, | |
6390 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6391 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6392 | fprintf_unfiltered (file, | |
6393 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6394 | STEP_SKIPS_DELAY_P); | |
6395 | fprintf_unfiltered (file, | |
6396 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6397 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6398 | fprintf_unfiltered (file, | |
6399 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6400 | T9_REGNUM); | |
6401 | fprintf_unfiltered (file, | |
6402 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6403 | fprintf_unfiltered (file, | |
6404 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6405 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6406 | fprintf_unfiltered (file, | |
6407 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6408 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6409 | #ifdef TRACE_CLEAR |
6410 | fprintf_unfiltered (file, | |
6411 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6412 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6413 | #endif | |
6414 | #ifdef TRACE_FLAVOR | |
6415 | fprintf_unfiltered (file, | |
6416 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6417 | TRACE_FLAVOR); | |
6418 | #endif | |
6419 | #ifdef TRACE_FLAVOR_SIZE | |
6420 | fprintf_unfiltered (file, | |
6421 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6422 | TRACE_FLAVOR_SIZE); | |
6423 | #endif | |
6424 | #ifdef TRACE_SET | |
6425 | fprintf_unfiltered (file, | |
6426 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6427 | XSTRING (TRACE_SET (X,STATE))); | |
6428 | #endif | |
2475bac3 AC |
6429 | #ifdef UNUSED_REGNUM |
6430 | fprintf_unfiltered (file, | |
6431 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6432 | UNUSED_REGNUM); | |
6433 | #endif | |
6434 | fprintf_unfiltered (file, | |
6435 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6436 | V0_REGNUM); | |
6437 | fprintf_unfiltered (file, | |
6438 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6439 | (long) VM_MIN_ADDRESS); | |
2475bac3 AC |
6440 | fprintf_unfiltered (file, |
6441 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6442 | ZERO_REGNUM); | |
6443 | fprintf_unfiltered (file, | |
6444 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6445 | _PROC_MAGIC_); | |
c2d11a7d JM |
6446 | } |
6447 | ||
a78f21af AC |
6448 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6449 | ||
c906108c | 6450 | void |
acdb74a0 | 6451 | _initialize_mips_tdep (void) |
c906108c SS |
6452 | { |
6453 | static struct cmd_list_element *mipsfpulist = NULL; | |
6454 | struct cmd_list_element *c; | |
6455 | ||
2e4ebe70 DJ |
6456 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6457 | if (MIPS_ABI_LAST + 1 | |
6458 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6459 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6460 | ||
4b9b3959 | 6461 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6462 | |
a5ea2558 AC |
6463 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6464 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6465 | "Various MIPS specific commands.", | |
6466 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6467 | ||
6468 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6469 | "Various MIPS specific commands.", | |
6470 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6471 | ||
6472 | /* Allow the user to override the saved register size. */ | |
6473 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6474 | class_obscure, |
6475 | size_enums, | |
6476 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6477 | Set size of general purpose registers saved on the stack.\n\ |
6478 | This option can be set to one of:\n\ | |
6479 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6480 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6481 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6482 | saved GP register size from information contained in the executable.\n\ | |
6483 | (default: auto)", | |
1ed2a135 | 6484 | &setmipscmdlist), |
a5ea2558 AC |
6485 | &showmipscmdlist); |
6486 | ||
d929b26f AC |
6487 | /* Allow the user to override the argument stack size. */ |
6488 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6489 | class_obscure, | |
6490 | size_enums, | |
1ed2a135 | 6491 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6492 | Set the amount of stack space reserved for each argument.\n\ |
6493 | This option can be set to one of:\n\ | |
6494 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6495 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6496 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6497 | target and executable (default)", | |
6498 | &setmipscmdlist), | |
6499 | &showmipscmdlist); | |
6500 | ||
2e4ebe70 DJ |
6501 | /* Allow the user to override the ABI. */ |
6502 | c = add_set_enum_cmd | |
6503 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6504 | "Set the ABI used by this program.\n" | |
6505 | "This option can be set to one of:\n" | |
6506 | " auto - the default ABI associated with the current binary\n" | |
6507 | " o32\n" | |
6508 | " o64\n" | |
6509 | " n32\n" | |
f3a7b3a5 | 6510 | " n64\n" |
2e4ebe70 DJ |
6511 | " eabi32\n" |
6512 | " eabi64", | |
6513 | &setmipscmdlist); | |
2e4ebe70 | 6514 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6515 | add_cmd ("abi", class_obscure, show_mips_abi, |
6516 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6517 | |
c906108c SS |
6518 | /* Let the user turn off floating point and set the fence post for |
6519 | heuristic_proc_start. */ | |
6520 | ||
6521 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6522 | "Set use of MIPS floating-point coprocessor.", | |
6523 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6524 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6525 | "Select single-precision MIPS floating-point coprocessor.", | |
6526 | &mipsfpulist); | |
6527 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6528 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6529 | &mipsfpulist); |
6530 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6531 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6532 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6533 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6534 | "Select no MIPS floating-point coprocessor.", | |
6535 | &mipsfpulist); | |
6536 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6537 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6538 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6539 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6540 | "Select MIPS floating-point coprocessor automatically.", | |
6541 | &mipsfpulist); | |
6542 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6543 | "Show current use of MIPS floating-point coprocessor target.", | |
6544 | &showlist); | |
6545 | ||
c906108c SS |
6546 | /* We really would like to have both "0" and "unlimited" work, but |
6547 | command.c doesn't deal with that. So make it a var_zinteger | |
6548 | because the user can always use "999999" or some such for unlimited. */ | |
6549 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6550 | (char *) &heuristic_fence_post, | |
6551 | "\ | |
6552 | Set the distance searched for the start of a function.\n\ | |
6553 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6554 | program for the start of a function. This command sets the distance of the\n\ | |
6555 | search. The only need to set it is when debugging a stripped executable.", | |
6556 | &setlist); | |
6557 | /* We need to throw away the frame cache when we set this, since it | |
6558 | might change our ability to get backtraces. */ | |
9f60d481 | 6559 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6560 | add_show_from_set (c, &showlist); |
6561 | ||
6562 | /* Allow the user to control whether the upper bits of 64-bit | |
6563 | addresses should be zeroed. */ | |
e9e68a56 AC |
6564 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6565 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6566 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6567 | allow GDB to determine the correct value.\n", "\ | |
6568 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6569 | NULL, show_mask_address, | |
6570 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6571 | |
6572 | /* Allow the user to control the size of 32 bit registers within the | |
6573 | raw remote packet. */ | |
719ec221 AC |
6574 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6575 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6576 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6577 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6578 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6579 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ | |
6580 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
43e526b9 JM |
6581 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6582 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6583 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
719ec221 AC |
6584 | set_mips64_transfers_32bit_regs, NULL, |
6585 | &setlist, &showlist); | |
9ace0497 AC |
6586 | |
6587 | /* Debug this files internals. */ | |
6588 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6589 | &mips_debug, "Set mips debugging.\n\ | |
6590 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6591 | &showdebuglist); | |
c906108c | 6592 | } |