Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 AC |
2 | |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, | |
4 | 1997, 1998, 1999, 2000, Free Software Foundation, Inc. | |
5 | ||
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
c906108c SS |
40 | |
41 | #include "opcode/mips.h" | |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
c906108c | 45 | |
b0069a17 AC |
46 | /* The sizes of floating point registers. */ |
47 | ||
48 | enum | |
49 | { | |
50 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
51 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
52 | }; | |
53 | ||
0dadbba0 AC |
54 | /* All the possible MIPS ABIs. */ |
55 | ||
56 | enum mips_abi | |
57 | { | |
58 | MIPS_ABI_UNKNOWN, | |
59 | MIPS_ABI_N32, | |
60 | MIPS_ABI_O32, | |
61 | MIPS_ABI_O64, | |
62 | MIPS_ABI_EABI32, | |
63 | MIPS_ABI_EABI64 | |
64 | }; | |
65 | ||
cce74817 | 66 | struct frame_extra_info |
c5aa993b JM |
67 | { |
68 | mips_extra_func_info_t proc_desc; | |
69 | int num_args; | |
70 | }; | |
cce74817 | 71 | |
d929b26f AC |
72 | /* Various MIPS ISA options (related to stack analysis) can be |
73 | overridden dynamically. Establish an enum/array for managing | |
74 | them. */ | |
75 | ||
53904c9e AC |
76 | static const char size_auto[] = "auto"; |
77 | static const char size_32[] = "32"; | |
78 | static const char size_64[] = "64"; | |
d929b26f | 79 | |
53904c9e | 80 | static const char *size_enums[] = { |
d929b26f AC |
81 | size_auto, |
82 | size_32, | |
83 | size_64, | |
a5ea2558 AC |
84 | 0 |
85 | }; | |
86 | ||
7a292a7a SS |
87 | /* Some MIPS boards don't support floating point while others only |
88 | support single-precision floating-point operations. See also | |
89 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
90 | |
91 | enum mips_fpu_type | |
c5aa993b JM |
92 | { |
93 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
94 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
95 | MIPS_FPU_NONE /* No floating point. */ | |
96 | }; | |
c906108c SS |
97 | |
98 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
99 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
100 | #endif | |
101 | static int mips_fpu_type_auto = 1; | |
102 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
103 | #define MIPS_FPU_TYPE mips_fpu_type | |
104 | ||
c906108c | 105 | /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */ |
7a292a7a | 106 | #ifndef FP_REGISTER_DOUBLE |
c906108c | 107 | #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8) |
7a292a7a SS |
108 | #endif |
109 | ||
110 | ||
c2d11a7d JM |
111 | /* MIPS specific per-architecture information */ |
112 | struct gdbarch_tdep | |
113 | { | |
114 | /* from the elf header */ | |
115 | int elf_flags; | |
116 | /* mips options */ | |
0dadbba0 | 117 | enum mips_abi mips_abi; |
c2d11a7d JM |
118 | enum mips_fpu_type mips_fpu_type; |
119 | int mips_last_arg_regnum; | |
120 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 121 | int mips_default_saved_regsize; |
c2d11a7d | 122 | int mips_fp_register_double; |
d929b26f AC |
123 | int mips_regs_have_home_p; |
124 | int mips_default_stack_argsize; | |
5213ab06 | 125 | int gdb_target_is_mips64; |
c2d11a7d JM |
126 | }; |
127 | ||
128 | #if GDB_MULTI_ARCH | |
129 | #undef MIPS_EABI | |
0dadbba0 | 130 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 131 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d JM |
132 | #endif |
133 | ||
134 | #if GDB_MULTI_ARCH | |
135 | #undef MIPS_LAST_FP_ARG_REGNUM | |
136 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) | |
137 | #endif | |
138 | ||
139 | #if GDB_MULTI_ARCH | |
140 | #undef MIPS_LAST_ARG_REGNUM | |
141 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) | |
142 | #endif | |
143 | ||
144 | #if GDB_MULTI_ARCH | |
145 | #undef MIPS_FPU_TYPE | |
146 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) | |
147 | #endif | |
148 | ||
d929b26f AC |
149 | /* Return the currently configured (or set) saved register size. */ |
150 | ||
c2d11a7d | 151 | #if GDB_MULTI_ARCH |
a5ea2558 AC |
152 | #undef MIPS_DEFAULT_SAVED_REGSIZE |
153 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) | |
d929b26f AC |
154 | #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE) |
155 | #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE | |
c2d11a7d JM |
156 | #endif |
157 | ||
53904c9e | 158 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
159 | |
160 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
161 | ||
162 | static unsigned int | |
163 | mips_saved_regsize () | |
164 | { | |
165 | if (mips_saved_regsize_string == size_auto) | |
166 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
167 | else if (mips_saved_regsize_string == size_64) | |
168 | return 8; | |
169 | else /* if (mips_saved_regsize_string == size_32) */ | |
170 | return 4; | |
171 | } | |
172 | ||
c2d11a7d JM |
173 | /* Indicate that the ABI makes use of double-precision registers |
174 | provided by the FPU (rather than combining pairs of registers to | |
175 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
176 | determine if the ABI is using double-precision registers. See also | |
177 | MIPS_FPU_TYPE. */ | |
178 | #if GDB_MULTI_ARCH | |
179 | #undef FP_REGISTER_DOUBLE | |
180 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) | |
181 | #endif | |
182 | ||
d929b26f AC |
183 | /* Does the caller allocate a ``home'' for each register used in the |
184 | function call? The N32 ABI and MIPS_EABI do not, the others do. */ | |
185 | ||
186 | #if GDB_MULTI_ARCH | |
187 | #undef MIPS_REGS_HAVE_HOME_P | |
188 | #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p) | |
189 | #elif !defined (MIPS_REGS_HAVE_HOME_P) | |
190 | #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI) | |
191 | #endif | |
192 | ||
193 | /* The amount of space reserved on the stack for registers. This is | |
194 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
195 | data allocated after the registers have run out. */ | |
196 | ||
197 | #if GDB_MULTI_ARCH | |
198 | #undef MIPS_DEFAULT_STACK_ARGSIZE | |
0dadbba0 | 199 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
200 | #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE) |
201 | #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE) | |
202 | #endif | |
203 | ||
204 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
205 | ||
53904c9e | 206 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
207 | |
208 | static unsigned int | |
209 | mips_stack_argsize (void) | |
210 | { | |
211 | if (mips_stack_argsize_string == size_auto) | |
212 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
213 | else if (mips_stack_argsize_string == size_64) | |
214 | return 8; | |
215 | else /* if (mips_stack_argsize_string == size_32) */ | |
216 | return 4; | |
217 | } | |
218 | ||
5213ab06 AC |
219 | #if GDB_MULTI_ARCH |
220 | #undef GDB_TARGET_IS_MIPS64 | |
221 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) | |
222 | #endif | |
c2d11a7d | 223 | |
7a292a7a | 224 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c SS |
225 | |
226 | #if 0 | |
a14ed312 | 227 | static int mips_in_lenient_prologue (CORE_ADDR, CORE_ADDR); |
c906108c SS |
228 | #endif |
229 | ||
a14ed312 | 230 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 231 | |
a14ed312 | 232 | static void mips_print_register (int, int); |
c906108c SS |
233 | |
234 | static mips_extra_func_info_t | |
a14ed312 | 235 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *); |
c906108c | 236 | |
a14ed312 | 237 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 238 | |
a14ed312 | 239 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 240 | |
a14ed312 | 241 | int mips_set_processor_type (char *); |
c906108c | 242 | |
a14ed312 | 243 | static void mips_show_processor_type_command (char *, int); |
c906108c | 244 | |
a14ed312 | 245 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
246 | |
247 | static mips_extra_func_info_t | |
a14ed312 | 248 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame); |
c906108c | 249 | |
a14ed312 KB |
250 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
251 | mips_extra_func_info_t proc_desc); | |
c906108c SS |
252 | |
253 | /* This value is the model of MIPS in use. It is derived from the value | |
254 | of the PrID register. */ | |
255 | ||
256 | char *mips_processor_type; | |
257 | ||
258 | char *tmp_mips_processor_type; | |
259 | ||
260 | /* A set of original names, to be used when restoring back to generic | |
261 | registers from a specific set. */ | |
262 | ||
cce74817 JM |
263 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
264 | char **mips_processor_reg_names = mips_generic_reg_names; | |
265 | ||
a5ea2558 AC |
266 | /* The list of available "set mips " and "show mips " commands */ |
267 | static struct cmd_list_element *setmipscmdlist = NULL; | |
268 | static struct cmd_list_element *showmipscmdlist = NULL; | |
269 | ||
cce74817 JM |
270 | char * |
271 | mips_register_name (i) | |
272 | int i; | |
273 | { | |
274 | return mips_processor_reg_names[i]; | |
275 | } | |
9846de1b | 276 | /* *INDENT-OFF* */ |
c906108c SS |
277 | /* Names of IDT R3041 registers. */ |
278 | ||
279 | char *mips_r3041_reg_names[] = { | |
280 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
281 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
282 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
283 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
284 | "sr", "lo", "hi", "bad", "cause","pc", | |
285 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
286 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
287 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
288 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
289 | "fsr", "fir", "fp", "", | |
290 | "", "", "bus", "ccfg", "", "", "", "", | |
291 | "", "", "port", "cmp", "", "", "epc", "prid", | |
292 | }; | |
293 | ||
294 | /* Names of IDT R3051 registers. */ | |
295 | ||
296 | char *mips_r3051_reg_names[] = { | |
297 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
298 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
299 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
300 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
301 | "sr", "lo", "hi", "bad", "cause","pc", | |
302 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
303 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
304 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
305 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
306 | "fsr", "fir", "fp", "", | |
307 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
308 | "", "", "ehi", "", "", "", "epc", "prid", | |
309 | }; | |
310 | ||
311 | /* Names of IDT R3081 registers. */ | |
312 | ||
313 | char *mips_r3081_reg_names[] = { | |
314 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
315 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
316 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
317 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
318 | "sr", "lo", "hi", "bad", "cause","pc", | |
319 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
320 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
321 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
322 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
323 | "fsr", "fir", "fp", "", | |
324 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
325 | "", "", "ehi", "", "", "", "epc", "prid", | |
326 | }; | |
327 | ||
328 | /* Names of LSI 33k registers. */ | |
329 | ||
330 | char *mips_lsi33k_reg_names[] = { | |
331 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
332 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
333 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
334 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
335 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
336 | "dcic", "bpc", "bda", "", "", "", "", "", | |
337 | "", "", "", "", "", "", "", "", | |
338 | "", "", "", "", "", "", "", "", | |
339 | "", "", "", "", "", "", "", "", | |
340 | "", "", "", "", | |
341 | "", "", "", "", "", "", "", "", | |
342 | "", "", "", "", "", "", "", "", | |
343 | }; | |
344 | ||
345 | struct { | |
346 | char *name; | |
347 | char **regnames; | |
348 | } mips_processor_type_table[] = { | |
349 | { "generic", mips_generic_reg_names }, | |
350 | { "r3041", mips_r3041_reg_names }, | |
351 | { "r3051", mips_r3051_reg_names }, | |
352 | { "r3071", mips_r3081_reg_names }, | |
353 | { "r3081", mips_r3081_reg_names }, | |
354 | { "lsi33k", mips_lsi33k_reg_names }, | |
355 | { NULL, NULL } | |
356 | }; | |
9846de1b | 357 | /* *INDENT-ON* */ |
c906108c | 358 | |
c5aa993b JM |
359 | |
360 | ||
361 | ||
c906108c | 362 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
363 | static int mips16_to_32_reg[8] = |
364 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
365 | |
366 | /* Heuristic_proc_start may hunt through the text section for a long | |
367 | time across a 2400 baud serial line. Allows the user to limit this | |
368 | search. */ | |
369 | ||
370 | static unsigned int heuristic_fence_post = 0; | |
371 | ||
c5aa993b JM |
372 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
373 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
374 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
375 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
376 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
377 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
378 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
379 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
380 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
381 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
382 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) | |
383 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
384 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
385 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
386 | ||
387 | struct linked_proc_info | |
c5aa993b JM |
388 | { |
389 | struct mips_extra_func_info info; | |
390 | struct linked_proc_info *next; | |
391 | } | |
392 | *linked_proc_desc_table = NULL; | |
c906108c | 393 | |
cce74817 JM |
394 | void |
395 | mips_print_extra_frame_info (fi) | |
396 | struct frame_info *fi; | |
397 | { | |
398 | if (fi | |
399 | && fi->extra_info | |
400 | && fi->extra_info->proc_desc | |
401 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 402 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 403 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 404 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 405 | } |
c906108c | 406 | |
43e526b9 JM |
407 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
408 | defines the remote-gdb packet. */ | |
409 | ||
410 | static int mips64_transfers_32bit_regs_p = 0; | |
411 | ||
412 | int | |
413 | mips_register_raw_size (reg_nr) | |
414 | int reg_nr; | |
415 | { | |
416 | if (mips64_transfers_32bit_regs_p) | |
417 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
418 | else | |
419 | return MIPS_REGSIZE; | |
420 | } | |
421 | ||
422 | int | |
423 | mips_register_convertible (reg_nr) | |
424 | int reg_nr; | |
425 | { | |
426 | if (mips64_transfers_32bit_regs_p) | |
427 | return 0; | |
428 | else | |
429 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
430 | } | |
431 | ||
432 | void | |
433 | mips_register_convert_to_virtual (n, virtual_type, raw_buf, virt_buf) | |
434 | int n; | |
435 | struct type *virtual_type; | |
436 | char *raw_buf; | |
437 | char *virt_buf; | |
438 | { | |
439 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
440 | memcpy (virt_buf, | |
441 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
442 | TYPE_LENGTH (virtual_type)); | |
443 | else | |
444 | memcpy (virt_buf, | |
445 | raw_buf, | |
446 | TYPE_LENGTH (virtual_type)); | |
447 | } | |
448 | ||
449 | void | |
450 | mips_register_convert_to_raw (virtual_type, n, virt_buf, raw_buf) | |
451 | struct type *virtual_type; | |
452 | int n; | |
453 | char *virt_buf; | |
454 | char *raw_buf; | |
455 | { | |
456 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
457 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
458 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
459 | virt_buf, | |
460 | TYPE_LENGTH (virtual_type)); | |
461 | else | |
462 | memcpy (raw_buf, | |
463 | virt_buf, | |
464 | TYPE_LENGTH (virtual_type)); | |
465 | } | |
466 | ||
c906108c SS |
467 | /* Should the upper word of 64-bit addresses be zeroed? */ |
468 | static int mask_address_p = 1; | |
469 | ||
470 | /* Should call_function allocate stack space for a struct return? */ | |
471 | int | |
472 | mips_use_struct_convention (gcc_p, type) | |
473 | int gcc_p; | |
474 | struct type *type; | |
475 | { | |
476 | if (MIPS_EABI) | |
7a292a7a | 477 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
c906108c | 478 | else |
c5aa993b | 479 | return 1; /* Structures are returned by ref in extra arg0 */ |
c906108c SS |
480 | } |
481 | ||
482 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ | |
483 | ||
484 | static int | |
485 | pc_is_mips16 (bfd_vma memaddr) | |
486 | { | |
487 | struct minimal_symbol *sym; | |
488 | ||
489 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
490 | if (IS_MIPS16_ADDR (memaddr)) | |
491 | return 1; | |
492 | ||
493 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
494 | the high bit of the info field. Use this to decide if the function is | |
495 | MIPS16 or normal MIPS. */ | |
496 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
497 | if (sym) | |
498 | return MSYMBOL_IS_SPECIAL (sym); | |
499 | else | |
500 | return 0; | |
501 | } | |
502 | ||
503 | ||
504 | /* This returns the PC of the first inst after the prologue. If we can't | |
505 | find the prologue, then return 0. */ | |
506 | ||
507 | static CORE_ADDR | |
508 | after_prologue (pc, proc_desc) | |
509 | CORE_ADDR pc; | |
510 | mips_extra_func_info_t proc_desc; | |
511 | { | |
512 | struct symtab_and_line sal; | |
513 | CORE_ADDR func_addr, func_end; | |
514 | ||
515 | if (!proc_desc) | |
516 | proc_desc = find_proc_desc (pc, NULL); | |
517 | ||
518 | if (proc_desc) | |
519 | { | |
520 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 521 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
522 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
523 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
524 | return 0; | |
525 | } | |
526 | ||
527 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
528 | return 0; /* Unknown */ | |
529 | ||
530 | sal = find_pc_line (func_addr, 0); | |
531 | ||
532 | if (sal.end < func_end) | |
533 | return sal.end; | |
534 | ||
535 | /* The line after the prologue is after the end of the function. In this | |
536 | case, tell the caller to find the prologue the hard way. */ | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
542 | set the appropriate bit in the general register mask or float register mask | |
543 | to indicate which register is saved. This is a helper function | |
544 | for mips_find_saved_regs. */ | |
545 | ||
546 | static void | |
547 | mips32_decode_reg_save (inst, gen_mask, float_mask) | |
548 | t_inst inst; | |
549 | unsigned long *gen_mask; | |
550 | unsigned long *float_mask; | |
551 | { | |
552 | int reg; | |
553 | ||
554 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
555 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
556 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
557 | { | |
558 | /* It might be possible to use the instruction to | |
c5aa993b JM |
559 | find the offset, rather than the code below which |
560 | is based on things being in a certain order in the | |
561 | frame, but figuring out what the instruction's offset | |
562 | is relative to might be a little tricky. */ | |
c906108c SS |
563 | reg = (inst & 0x001f0000) >> 16; |
564 | *gen_mask |= (1 << reg); | |
565 | } | |
566 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
567 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
568 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
569 | |
570 | { | |
571 | reg = ((inst & 0x001f0000) >> 16); | |
572 | *float_mask |= (1 << reg); | |
573 | } | |
574 | } | |
575 | ||
576 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
577 | set the appropriate bit in the general register or float register mask | |
578 | to indicate which register is saved. This is a helper function | |
579 | for mips_find_saved_regs. */ | |
580 | ||
581 | static void | |
582 | mips16_decode_reg_save (inst, gen_mask) | |
583 | t_inst inst; | |
584 | unsigned long *gen_mask; | |
585 | { | |
c5aa993b | 586 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
587 | { |
588 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
589 | *gen_mask |= (1 << reg); | |
590 | } | |
c5aa993b | 591 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
592 | { |
593 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
594 | *gen_mask |= (1 << reg); | |
595 | } | |
c5aa993b | 596 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
597 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
598 | *gen_mask |= (1 << RA_REGNUM); | |
599 | } | |
600 | ||
601 | ||
602 | /* Fetch and return instruction from the specified location. If the PC | |
603 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
604 | ||
605 | static t_inst | |
606 | mips_fetch_instruction (addr) | |
c5aa993b | 607 | CORE_ADDR addr; |
c906108c SS |
608 | { |
609 | char buf[MIPS_INSTLEN]; | |
610 | int instlen; | |
611 | int status; | |
612 | ||
613 | if (pc_is_mips16 (addr)) | |
614 | { | |
615 | instlen = MIPS16_INSTLEN; | |
616 | addr = UNMAKE_MIPS16_ADDR (addr); | |
617 | } | |
618 | else | |
c5aa993b | 619 | instlen = MIPS_INSTLEN; |
c906108c SS |
620 | status = read_memory_nobpt (addr, buf, instlen); |
621 | if (status) | |
622 | memory_error (status, addr); | |
623 | return extract_unsigned_integer (buf, instlen); | |
624 | } | |
625 | ||
626 | ||
627 | /* These the fields of 32 bit mips instructions */ | |
628 | #define mips32_op(x) (x >> 25) | |
629 | #define itype_op(x) (x >> 25) | |
630 | #define itype_rs(x) ((x >> 21)& 0x1f) | |
631 | #define itype_rt(x) ((x >> 16) & 0x1f) | |
632 | #define itype_immediate(x) ( x & 0xffff) | |
633 | ||
634 | #define jtype_op(x) (x >> 25) | |
635 | #define jtype_target(x) ( x & 0x03fffff) | |
636 | ||
637 | #define rtype_op(x) (x >>25) | |
638 | #define rtype_rs(x) ((x>>21) & 0x1f) | |
639 | #define rtype_rt(x) ((x>>16) & 0x1f) | |
c5aa993b | 640 | #define rtype_rd(x) ((x>>11) & 0x1f) |
c906108c SS |
641 | #define rtype_shamt(x) ((x>>6) & 0x1f) |
642 | #define rtype_funct(x) (x & 0x3f ) | |
643 | ||
644 | static CORE_ADDR | |
c5aa993b JM |
645 | mips32_relative_offset (unsigned long inst) |
646 | { | |
647 | long x; | |
648 | x = itype_immediate (inst); | |
649 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 650 | { |
c5aa993b | 651 | x |= 0xffff0000; /* sign extension */ |
c906108c | 652 | } |
c5aa993b JM |
653 | x = x << 2; |
654 | return x; | |
c906108c SS |
655 | } |
656 | ||
657 | /* Determine whate to set a single step breakpoint while considering | |
658 | branch prediction */ | |
659 | CORE_ADDR | |
c5aa993b JM |
660 | mips32_next_pc (CORE_ADDR pc) |
661 | { | |
662 | unsigned long inst; | |
663 | int op; | |
664 | inst = mips_fetch_instruction (pc); | |
665 | if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */ | |
666 | { | |
667 | if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */ | |
668 | { | |
669 | op = ((inst >> 25) & 0x03); | |
c906108c SS |
670 | switch (op) |
671 | { | |
c5aa993b JM |
672 | case 0: |
673 | goto equal_branch; /* BEQL */ | |
674 | case 1: | |
675 | goto neq_branch; /* BNEZ */ | |
676 | case 2: | |
677 | goto less_branch; /* BLEZ */ | |
678 | case 3: | |
679 | goto greater_branch; /* BGTZ */ | |
680 | default: | |
681 | pc += 4; | |
c906108c SS |
682 | } |
683 | } | |
c5aa993b JM |
684 | else |
685 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
686 | } |
687 | else | |
c5aa993b JM |
688 | { /* This gets way messy */ |
689 | ||
c906108c | 690 | /* Further subdivide into SPECIAL, REGIMM and other */ |
c5aa993b | 691 | switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */ |
c906108c | 692 | { |
c5aa993b JM |
693 | case 0: /* SPECIAL */ |
694 | op = rtype_funct (inst); | |
695 | switch (op) | |
696 | { | |
697 | case 8: /* JR */ | |
698 | case 9: /* JALR */ | |
699 | pc = read_register (rtype_rs (inst)); /* Set PC to that address */ | |
700 | break; | |
701 | default: | |
702 | pc += 4; | |
703 | } | |
704 | ||
705 | break; /* end special */ | |
706 | case 1: /* REGIMM */ | |
c906108c | 707 | { |
c5aa993b JM |
708 | op = jtype_op (inst); /* branch condition */ |
709 | switch (jtype_op (inst)) | |
c906108c | 710 | { |
c5aa993b JM |
711 | case 0: /* BLTZ */ |
712 | case 2: /* BLTXL */ | |
713 | case 16: /* BLTZALL */ | |
714 | case 18: /* BLTZALL */ | |
c906108c | 715 | less_branch: |
c5aa993b JM |
716 | if (read_register (itype_rs (inst)) < 0) |
717 | pc += mips32_relative_offset (inst) + 4; | |
718 | else | |
719 | pc += 8; /* after the delay slot */ | |
720 | break; | |
721 | case 1: /* GEZ */ | |
722 | case 3: /* BGEZL */ | |
723 | case 17: /* BGEZAL */ | |
724 | case 19: /* BGEZALL */ | |
c906108c | 725 | greater_equal_branch: |
c5aa993b JM |
726 | if (read_register (itype_rs (inst)) >= 0) |
727 | pc += mips32_relative_offset (inst) + 4; | |
728 | else | |
729 | pc += 8; /* after the delay slot */ | |
730 | break; | |
731 | /* All of the other intructions in the REGIMM catagory */ | |
732 | default: | |
733 | pc += 4; | |
c906108c SS |
734 | } |
735 | } | |
c5aa993b JM |
736 | break; /* end REGIMM */ |
737 | case 2: /* J */ | |
738 | case 3: /* JAL */ | |
739 | { | |
740 | unsigned long reg; | |
741 | reg = jtype_target (inst) << 2; | |
742 | pc = reg + ((pc + 4) & 0xf0000000); | |
c906108c SS |
743 | /* Whats this mysterious 0xf000000 adjustment ??? */ |
744 | } | |
c5aa993b JM |
745 | break; |
746 | /* FIXME case JALX : */ | |
747 | { | |
748 | unsigned long reg; | |
749 | reg = jtype_target (inst) << 2; | |
750 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
751 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
752 | } | |
c5aa993b JM |
753 | break; /* The new PC will be alternate mode */ |
754 | case 4: /* BEQ , BEQL */ | |
755 | equal_branch: | |
756 | if (read_register (itype_rs (inst)) == | |
757 | read_register (itype_rt (inst))) | |
758 | pc += mips32_relative_offset (inst) + 4; | |
759 | else | |
760 | pc += 8; | |
761 | break; | |
762 | case 5: /* BNE , BNEL */ | |
763 | neq_branch: | |
764 | if (read_register (itype_rs (inst)) != | |
765 | read_register (itype_rs (inst))) | |
766 | pc += mips32_relative_offset (inst) + 4; | |
767 | else | |
768 | pc += 8; | |
769 | break; | |
770 | case 6: /* BLEZ , BLEZL */ | |
c906108c | 771 | less_zero_branch: |
c5aa993b JM |
772 | if (read_register (itype_rs (inst) <= 0)) |
773 | pc += mips32_relative_offset (inst) + 4; | |
774 | else | |
775 | pc += 8; | |
776 | break; | |
777 | case 7: | |
778 | greater_branch: /* BGTZ BGTZL */ | |
779 | if (read_register (itype_rs (inst) > 0)) | |
780 | pc += mips32_relative_offset (inst) + 4; | |
781 | else | |
782 | pc += 8; | |
783 | break; | |
784 | default: | |
785 | pc += 8; | |
786 | } /* switch */ | |
787 | } /* else */ | |
788 | return pc; | |
789 | } /* mips32_next_pc */ | |
c906108c SS |
790 | |
791 | /* Decoding the next place to set a breakpoint is irregular for the | |
792 | mips 16 variant, but fortunatly, there fewer instructions. We have to cope | |
793 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. | |
794 | We dont want to set a single step instruction on the extend instruction | |
795 | either. | |
c5aa993b | 796 | */ |
c906108c SS |
797 | |
798 | /* Lots of mips16 instruction formats */ | |
799 | /* Predicting jumps requires itype,ritype,i8type | |
800 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 801 | */ |
c906108c SS |
802 | enum mips16_inst_fmts |
803 | { | |
c5aa993b JM |
804 | itype, /* 0 immediate 5,10 */ |
805 | ritype, /* 1 5,3,8 */ | |
806 | rrtype, /* 2 5,3,3,5 */ | |
807 | rritype, /* 3 5,3,3,5 */ | |
808 | rrrtype, /* 4 5,3,3,3,2 */ | |
809 | rriatype, /* 5 5,3,3,1,4 */ | |
810 | shifttype, /* 6 5,3,3,3,2 */ | |
811 | i8type, /* 7 5,3,8 */ | |
812 | i8movtype, /* 8 5,3,3,5 */ | |
813 | i8mov32rtype, /* 9 5,3,5,3 */ | |
814 | i64type, /* 10 5,3,8 */ | |
815 | ri64type, /* 11 5,3,3,5 */ | |
816 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
817 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
818 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
819 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
820 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
821 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
822 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
823 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
824 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
825 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
826 | }; | |
c906108c SS |
827 | /* I am heaping all the fields of the formats into one structure and then, |
828 | only the fields which are involved in instruction extension */ | |
829 | struct upk_mips16 | |
c5aa993b JM |
830 | { |
831 | unsigned short inst; | |
832 | enum mips16_inst_fmts fmt; | |
833 | unsigned long offset; | |
834 | unsigned int regx; /* Function in i8 type */ | |
835 | unsigned int regy; | |
836 | }; | |
c906108c SS |
837 | |
838 | ||
839 | ||
c5aa993b JM |
840 | static void |
841 | print_unpack (char *comment, | |
842 | struct upk_mips16 *u) | |
c906108c | 843 | { |
d4f3574e SS |
844 | printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n", |
845 | comment, u->inst, u->fmt, paddr (u->offset), u->regx, u->regy); | |
c906108c SS |
846 | } |
847 | ||
848 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same | |
849 | format for the bits which make up the immediatate extension. | |
c5aa993b | 850 | */ |
c906108c | 851 | static unsigned long |
c5aa993b | 852 | extended_offset (unsigned long extension) |
c906108c | 853 | { |
c5aa993b JM |
854 | unsigned long value; |
855 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ | |
856 | value = value << 6; | |
857 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
858 | value = value << 5; | |
859 | value |= extension & 0x01f; /* extract 4:0 */ | |
860 | return value; | |
c906108c SS |
861 | } |
862 | ||
863 | /* Only call this function if you know that this is an extendable | |
864 | instruction, It wont malfunction, but why make excess remote memory references? | |
865 | If the immediate operands get sign extended or somthing, do it after | |
866 | the extension is performed. | |
c5aa993b | 867 | */ |
c906108c SS |
868 | /* FIXME: Every one of these cases needs to worry about sign extension |
869 | when the offset is to be used in relative addressing */ | |
870 | ||
871 | ||
c5aa993b JM |
872 | static unsigned short |
873 | fetch_mips_16 (CORE_ADDR pc) | |
c906108c | 874 | { |
c5aa993b JM |
875 | char buf[8]; |
876 | pc &= 0xfffffffe; /* clear the low order bit */ | |
877 | target_read_memory (pc, buf, 2); | |
878 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
879 | } |
880 | ||
881 | static void | |
c5aa993b JM |
882 | unpack_mips16 (CORE_ADDR pc, |
883 | struct upk_mips16 *upk) | |
c906108c | 884 | { |
c5aa993b JM |
885 | CORE_ADDR extpc; |
886 | unsigned long extension; | |
887 | int extended; | |
888 | extpc = (pc - 4) & ~0x01; /* Extensions are 32 bit instructions */ | |
c906108c SS |
889 | /* Decrement to previous address and loose the 16bit mode flag */ |
890 | /* return if the instruction was extendable, but not actually extended */ | |
c5aa993b JM |
891 | extended = ((mips32_op (extension) == 30) ? 1 : 0); |
892 | if (extended) | |
893 | { | |
894 | extension = mips_fetch_instruction (extpc); | |
895 | } | |
c906108c SS |
896 | switch (upk->fmt) |
897 | { | |
c5aa993b | 898 | case itype: |
c906108c | 899 | { |
c5aa993b | 900 | unsigned long value; |
c906108c | 901 | if (extended) |
c5aa993b JM |
902 | { |
903 | value = extended_offset (extension); | |
904 | value = value << 11; /* rom for the original value */ | |
905 | value |= upk->inst & 0x7ff; /* eleven bits from instruction */ | |
c906108c SS |
906 | } |
907 | else | |
c5aa993b JM |
908 | { |
909 | value = upk->inst & 0x7ff; | |
910 | /* FIXME : Consider sign extension */ | |
c906108c | 911 | } |
c5aa993b | 912 | upk->offset = value; |
c906108c | 913 | } |
c5aa993b JM |
914 | break; |
915 | case ritype: | |
916 | case i8type: | |
917 | { /* A register identifier and an offset */ | |
c906108c SS |
918 | /* Most of the fields are the same as I type but the |
919 | immediate value is of a different length */ | |
c5aa993b | 920 | unsigned long value; |
c906108c SS |
921 | if (extended) |
922 | { | |
c5aa993b JM |
923 | value = extended_offset (extension); |
924 | value = value << 8; /* from the original instruction */ | |
925 | value |= upk->inst & 0xff; /* eleven bits from instruction */ | |
926 | upk->regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
927 | if (value & 0x4000) /* test the sign bit , bit 26 */ | |
928 | { | |
929 | value &= ~0x3fff; /* remove the sign bit */ | |
930 | value = -value; | |
c906108c SS |
931 | } |
932 | } | |
c5aa993b JM |
933 | else |
934 | { | |
935 | value = upk->inst & 0xff; /* 8 bits */ | |
936 | upk->regx = (upk->inst >> 8) & 0x07; /* or i8 funct */ | |
937 | /* FIXME: Do sign extension , this format needs it */ | |
938 | if (value & 0x80) /* THIS CONFUSES ME */ | |
939 | { | |
940 | value &= 0xef; /* remove the sign bit */ | |
941 | value = -value; | |
942 | } | |
943 | ||
944 | } | |
945 | upk->offset = value; | |
946 | break; | |
c906108c | 947 | } |
c5aa993b | 948 | case jalxtype: |
c906108c | 949 | { |
c5aa993b JM |
950 | unsigned long value; |
951 | unsigned short nexthalf; | |
952 | value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f); | |
953 | value = value << 16; | |
954 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
955 | value |= nexthalf; | |
956 | upk->offset = value; | |
957 | break; | |
c906108c SS |
958 | } |
959 | default: | |
c5aa993b JM |
960 | printf_filtered ("Decoding unimplemented instruction format type\n"); |
961 | break; | |
c906108c SS |
962 | } |
963 | /* print_unpack("UPK",upk) ; */ | |
964 | } | |
965 | ||
966 | ||
967 | #define mips16_op(x) (x >> 11) | |
968 | ||
969 | /* This is a map of the opcodes which ae known to perform branches */ | |
970 | static unsigned char map16[32] = | |
c5aa993b JM |
971 | {0, 0, 1, 1, 1, 1, 0, 0, |
972 | 0, 0, 0, 0, 1, 0, 0, 0, | |
973 | 0, 0, 0, 0, 0, 0, 0, 0, | |
974 | 0, 0, 0, 0, 0, 1, 1, 0 | |
975 | }; | |
c906108c | 976 | |
c5aa993b JM |
977 | static CORE_ADDR |
978 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 979 | { |
c5aa993b JM |
980 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
981 | ||
c906108c SS |
982 | } |
983 | ||
984 | ||
985 | ||
c5aa993b | 986 | static struct upk_mips16 upk; |
c906108c | 987 | |
c5aa993b JM |
988 | CORE_ADDR |
989 | mips16_next_pc (CORE_ADDR pc) | |
c906108c | 990 | { |
c5aa993b JM |
991 | int op; |
992 | t_inst inst; | |
c906108c | 993 | /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */ |
c5aa993b JM |
994 | inst = fetch_mips_16 (pc); |
995 | upk.inst = inst; | |
996 | op = mips16_op (upk.inst); | |
c906108c SS |
997 | if (map16[op]) |
998 | { | |
c5aa993b | 999 | int reg; |
c906108c SS |
1000 | switch (op) |
1001 | { | |
c5aa993b JM |
1002 | case 2: /* Branch */ |
1003 | upk.fmt = itype; | |
1004 | unpack_mips16 (pc, &upk); | |
1005 | { | |
1006 | long offset; | |
1007 | offset = upk.offset; | |
c906108c | 1008 | if (offset & 0x800) |
c5aa993b JM |
1009 | { |
1010 | offset &= 0xeff; | |
1011 | offset = -offset; | |
c906108c | 1012 | } |
c5aa993b | 1013 | pc += (offset << 1) + 2; |
c906108c | 1014 | } |
c5aa993b JM |
1015 | break; |
1016 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1017 | upk.fmt = jalxtype; | |
1018 | unpack_mips16 (pc, &upk); | |
1019 | pc = add_offset_16 (pc, upk.offset); | |
1020 | if ((upk.inst >> 10) & 0x01) /* Exchange mode */ | |
1021 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1022 | else | |
1023 | pc |= 0x01; | |
1024 | break; | |
1025 | case 4: /* beqz */ | |
1026 | upk.fmt = ritype; | |
1027 | unpack_mips16 (pc, &upk); | |
1028 | reg = read_register (upk.regx); | |
1029 | if (reg == 0) | |
1030 | pc += (upk.offset << 1) + 2; | |
1031 | else | |
1032 | pc += 2; | |
1033 | break; | |
1034 | case 5: /* bnez */ | |
1035 | upk.fmt = ritype; | |
1036 | unpack_mips16 (pc, &upk); | |
1037 | reg = read_register (upk.regx); | |
1038 | if (reg != 0) | |
1039 | pc += (upk.offset << 1) + 2; | |
1040 | else | |
1041 | pc += 2; | |
1042 | break; | |
1043 | case 12: /* I8 Formats btez btnez */ | |
1044 | upk.fmt = i8type; | |
1045 | unpack_mips16 (pc, &upk); | |
1046 | /* upk.regx contains the opcode */ | |
1047 | reg = read_register (24); /* Test register is 24 */ | |
1048 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1049 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1050 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1051 | pc += (upk.offset << 1) + 2; | |
1052 | else | |
1053 | pc += 2; | |
1054 | break; | |
1055 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1056 | upk.fmt = rrtype; | |
1057 | op = upk.inst & 0x1f; | |
c906108c | 1058 | if (op == 0) |
c5aa993b JM |
1059 | { |
1060 | upk.regx = (upk.inst >> 8) & 0x07; | |
1061 | upk.regy = (upk.inst >> 5) & 0x07; | |
c906108c SS |
1062 | switch (upk.regy) |
1063 | { | |
c5aa993b JM |
1064 | case 0: |
1065 | reg = upk.regx; | |
1066 | break; | |
1067 | case 1: | |
1068 | reg = 31; | |
1069 | break; /* Function return instruction */ | |
1070 | case 2: | |
1071 | reg = upk.regx; | |
1072 | break; | |
1073 | default: | |
1074 | reg = 31; | |
1075 | break; /* BOGUS Guess */ | |
c906108c | 1076 | } |
c5aa993b | 1077 | pc = read_register (reg); |
c906108c | 1078 | } |
c5aa993b JM |
1079 | else |
1080 | pc += 2; | |
1081 | break; | |
1082 | case 30: /* This is an extend instruction */ | |
1083 | pc += 4; /* Dont be setting breakpints on the second half */ | |
1084 | break; | |
1085 | default: | |
1086 | printf ("Filtered - next PC probably incorrrect due to jump inst\n"); | |
1087 | pc += 2; | |
1088 | break; | |
c906108c SS |
1089 | } |
1090 | } | |
c5aa993b JM |
1091 | else |
1092 | pc += 2; /* just a good old instruction */ | |
c906108c SS |
1093 | /* See if we CAN actually break on the next instruction */ |
1094 | /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */ | |
c5aa993b JM |
1095 | return pc; |
1096 | } /* mips16_next_pc */ | |
c906108c SS |
1097 | |
1098 | /* The mips_next_pc function supports single_tep when the remote target monitor or | |
1099 | stub is not developed enough to so a single_step. | |
1100 | It works by decoding the current instruction and predicting where a branch | |
1101 | will go. This isnt hard because all the data is available. | |
1102 | The MIPS32 and MIPS16 variants are quite different | |
c5aa993b JM |
1103 | */ |
1104 | CORE_ADDR | |
1105 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1106 | { |
c5aa993b | 1107 | t_inst inst; |
c906108c SS |
1108 | /* inst = mips_fetch_instruction(pc) ; */ |
1109 | /* if (pc_is_mips16) <----- This is failing */ | |
c5aa993b JM |
1110 | if (pc & 0x01) |
1111 | return mips16_next_pc (pc); | |
1112 | else | |
1113 | return mips32_next_pc (pc); | |
1114 | } /* mips_next_pc */ | |
c906108c SS |
1115 | |
1116 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
1117 | NULL). */ | |
1118 | ||
1119 | void | |
1120 | mips_find_saved_regs (fci) | |
1121 | struct frame_info *fci; | |
1122 | { | |
1123 | int ireg; | |
1124 | CORE_ADDR reg_position; | |
1125 | /* r0 bit means kernel trap */ | |
1126 | int kernel_trap; | |
1127 | /* What registers have been saved? Bitmasks. */ | |
1128 | unsigned long gen_mask, float_mask; | |
1129 | mips_extra_func_info_t proc_desc; | |
1130 | t_inst inst; | |
1131 | ||
1132 | frame_saved_regs_zalloc (fci); | |
1133 | ||
1134 | /* If it is the frame for sigtramp, the saved registers are located | |
1135 | in a sigcontext structure somewhere on the stack. | |
1136 | If the stack layout for sigtramp changes we might have to change these | |
1137 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1138 | #ifndef SIGFRAME_BASE | |
1139 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1140 | above the sigtramp frame. */ | |
1141 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1142 | /* FIXME! Are these correct?? */ | |
1143 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1144 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1145 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1146 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1147 | #endif | |
1148 | #ifndef SIGFRAME_REG_SIZE | |
1149 | /* FIXME! Is this correct?? */ | |
1150 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1151 | #endif | |
1152 | if (fci->signal_handler_caller) | |
1153 | { | |
1154 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1155 | { | |
c5aa993b JM |
1156 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1157 | + ireg * SIGFRAME_REG_SIZE; | |
1158 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1159 | } |
1160 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1161 | { | |
c5aa993b JM |
1162 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1163 | + ireg * SIGFRAME_REG_SIZE; | |
1164 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1165 | } |
1166 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1167 | return; | |
1168 | } | |
1169 | ||
cce74817 | 1170 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1171 | if (proc_desc == NULL) |
1172 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1173 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1174 | and set the saved_regs right away. */ | |
1175 | return; | |
1176 | ||
c5aa993b JM |
1177 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1178 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1179 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1180 | |
c5aa993b JM |
1181 | if ( /* In any frame other than the innermost or a frame interrupted by |
1182 | a signal, we assume that all registers have been saved. | |
1183 | This assumes that all register saves in a function happen before | |
1184 | the first function call. */ | |
1185 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1186 | |
c5aa993b JM |
1187 | /* In a dummy frame we know exactly where things are saved. */ |
1188 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1189 | |
c5aa993b JM |
1190 | /* Don't bother unless we are inside a function prologue. Outside the |
1191 | prologue, we know where everything is. */ | |
c906108c | 1192 | |
c5aa993b | 1193 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1194 | |
c5aa993b JM |
1195 | /* Not sure exactly what kernel_trap means, but if it means |
1196 | the kernel saves the registers without a prologue doing it, | |
1197 | we better not examine the prologue to see whether registers | |
1198 | have been saved yet. */ | |
1199 | && !kernel_trap) | |
c906108c SS |
1200 | { |
1201 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1202 | claims are saved have been saved yet. */ |
c906108c SS |
1203 | |
1204 | CORE_ADDR addr; | |
1205 | ||
1206 | /* Bitmasks; set if we have found a save for the register. */ | |
1207 | unsigned long gen_save_found = 0; | |
1208 | unsigned long float_save_found = 0; | |
1209 | int instlen; | |
1210 | ||
1211 | /* If the address is odd, assume this is MIPS16 code. */ | |
1212 | addr = PROC_LOW_ADDR (proc_desc); | |
1213 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1214 | ||
1215 | /* Scan through this function's instructions preceding the current | |
1216 | PC, and look for those that save registers. */ | |
1217 | while (addr < fci->pc) | |
1218 | { | |
1219 | inst = mips_fetch_instruction (addr); | |
1220 | if (pc_is_mips16 (addr)) | |
1221 | mips16_decode_reg_save (inst, &gen_save_found); | |
1222 | else | |
1223 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1224 | addr += instlen; | |
1225 | } | |
1226 | gen_mask = gen_save_found; | |
1227 | float_mask = float_save_found; | |
1228 | } | |
1229 | ||
1230 | /* Fill in the offsets for the registers which gen_mask says | |
1231 | were saved. */ | |
1232 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1233 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1234 | if (gen_mask & 0x80000000) |
1235 | { | |
1236 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1237 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1238 | } |
1239 | ||
1240 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1241 | of that normally used by gcc. Therefore, we have to fetch the first | |
1242 | instruction of the function, and if it's an entry instruction that | |
1243 | saves $s0 or $s1, correct their saved addresses. */ | |
1244 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1245 | { | |
1246 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1247 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1248 | { |
1249 | int reg; | |
1250 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1251 | |
c906108c SS |
1252 | /* Check if the ra register was pushed on the stack. */ |
1253 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1254 | if (inst & 0x20) | |
7a292a7a | 1255 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1256 | |
1257 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1258 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1259 | { |
1260 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1261 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1262 | } |
1263 | } | |
1264 | } | |
1265 | ||
1266 | /* Fill in the offsets for the registers which float_mask says | |
1267 | were saved. */ | |
1268 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1269 | ||
1270 | /* The freg_offset points to where the first *double* register | |
1271 | is saved. So skip to the high-order word. */ | |
c5aa993b | 1272 | if (!GDB_TARGET_IS_MIPS64) |
7a292a7a | 1273 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1274 | |
1275 | /* Fill in the offsets for the float registers which float_mask says | |
1276 | were saved. */ | |
c5aa993b | 1277 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1278 | if (float_mask & 0x80000000) |
1279 | { | |
c5aa993b | 1280 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1281 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1282 | } |
1283 | ||
1284 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1285 | } | |
1286 | ||
1287 | static CORE_ADDR | |
c5aa993b | 1288 | read_next_frame_reg (fi, regno) |
c906108c SS |
1289 | struct frame_info *fi; |
1290 | int regno; | |
1291 | { | |
1292 | for (; fi; fi = fi->next) | |
1293 | { | |
1294 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1295 | if it is a signal handler frame. */ |
c906108c SS |
1296 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1297 | return fi->frame; | |
1298 | else | |
1299 | { | |
1300 | if (fi->saved_regs == NULL) | |
1301 | mips_find_saved_regs (fi); | |
1302 | if (fi->saved_regs[regno]) | |
2acceee2 | 1303 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1304 | } |
1305 | } | |
1306 | return read_register (regno); | |
1307 | } | |
1308 | ||
1309 | /* mips_addr_bits_remove - remove useless address bits */ | |
1310 | ||
1311 | CORE_ADDR | |
1312 | mips_addr_bits_remove (addr) | |
c5aa993b | 1313 | CORE_ADDR addr; |
c906108c | 1314 | { |
5213ab06 AC |
1315 | if (GDB_TARGET_IS_MIPS64) |
1316 | { | |
1317 | if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff)) | |
1318 | { | |
1319 | /* This hack is a work-around for existing boards using | |
1320 | PMON, the simulator, and any other 64-bit targets that | |
1321 | doesn't have true 64-bit addressing. On these targets, | |
1322 | the upper 32 bits of addresses are ignored by the | |
1323 | hardware. Thus, the PC or SP are likely to have been | |
1324 | sign extended to all 1s by instruction sequences that | |
1325 | load 32-bit addresses. For example, a typical piece of | |
1326 | code that loads an address is this: lui $r2, <upper 16 | |
1327 | bits> ori $r2, <lower 16 bits> But the lui sign-extends | |
1328 | the value such that the upper 32 bits may be all 1s. The | |
1329 | workaround is simply to mask off these bits. In the | |
1330 | future, gcc may be changed to support true 64-bit | |
1331 | addressing, and this masking will have to be disabled. */ | |
1332 | addr &= (CORE_ADDR) 0xffffffff; | |
1333 | } | |
1334 | } | |
1335 | else | |
1336 | { | |
1337 | /* Even when GDB is configured for some 32-bit targets | |
1338 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1339 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1340 | useless bits from addresses. */ | |
c5aa993b | 1341 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1342 | } |
c906108c SS |
1343 | return addr; |
1344 | } | |
1345 | ||
1346 | void | |
1347 | mips_init_frame_pc_first (fromleaf, prev) | |
1348 | int fromleaf; | |
1349 | struct frame_info *prev; | |
1350 | { | |
1351 | CORE_ADDR pc, tmp; | |
1352 | ||
1353 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1354 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
c906108c | 1355 | tmp = mips_skip_stub (pc); |
c5aa993b | 1356 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1357 | } |
1358 | ||
1359 | ||
1360 | CORE_ADDR | |
c5aa993b | 1361 | mips_frame_saved_pc (frame) |
c906108c SS |
1362 | struct frame_info *frame; |
1363 | { | |
1364 | CORE_ADDR saved_pc; | |
cce74817 | 1365 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1366 | /* We have to get the saved pc from the sigcontext |
1367 | if it is a signal handler frame. */ | |
1368 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1369 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1370 | |
c5aa993b | 1371 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1372 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1373 | else |
7a292a7a | 1374 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1375 | |
1376 | return ADDR_BITS_REMOVE (saved_pc); | |
1377 | } | |
1378 | ||
1379 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1380 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1381 | |
1382 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1383 | has already been set for this register, do nothing; this way we will | |
1384 | only recognize the first save of a given register in a function prologue. | |
1385 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1386 | ||
1387 | static void | |
1388 | set_reg_offset (regno, offset) | |
1389 | int regno; | |
1390 | CORE_ADDR offset; | |
1391 | { | |
cce74817 JM |
1392 | if (temp_saved_regs[regno] == 0) |
1393 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1394 | } |
1395 | ||
1396 | ||
1397 | /* Test whether the PC points to the return instruction at the | |
1398 | end of a function. */ | |
1399 | ||
c5aa993b | 1400 | static int |
c906108c SS |
1401 | mips_about_to_return (pc) |
1402 | CORE_ADDR pc; | |
1403 | { | |
1404 | if (pc_is_mips16 (pc)) | |
1405 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1406 | generates a "jr $ra"; other times it generates code to load | |
1407 | the return address from the stack to an accessible register (such | |
1408 | as $a3), then a "jr" using that register. This second case | |
1409 | is almost impossible to distinguish from an indirect jump | |
1410 | used for switch statements, so we don't even try. */ | |
1411 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1412 | else | |
1413 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1414 | } | |
1415 | ||
1416 | ||
1417 | /* This fencepost looks highly suspicious to me. Removing it also | |
1418 | seems suspicious as it could affect remote debugging across serial | |
1419 | lines. */ | |
1420 | ||
1421 | static CORE_ADDR | |
1422 | heuristic_proc_start (pc) | |
c5aa993b | 1423 | CORE_ADDR pc; |
c906108c | 1424 | { |
c5aa993b JM |
1425 | CORE_ADDR start_pc; |
1426 | CORE_ADDR fence; | |
1427 | int instlen; | |
1428 | int seen_adjsp = 0; | |
c906108c | 1429 | |
c5aa993b JM |
1430 | pc = ADDR_BITS_REMOVE (pc); |
1431 | start_pc = pc; | |
1432 | fence = start_pc - heuristic_fence_post; | |
1433 | if (start_pc == 0) | |
1434 | return 0; | |
c906108c | 1435 | |
c5aa993b JM |
1436 | if (heuristic_fence_post == UINT_MAX |
1437 | || fence < VM_MIN_ADDRESS) | |
1438 | fence = VM_MIN_ADDRESS; | |
c906108c | 1439 | |
c5aa993b | 1440 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1441 | |
c5aa993b JM |
1442 | /* search back for previous return */ |
1443 | for (start_pc -= instlen;; start_pc -= instlen) | |
1444 | if (start_pc < fence) | |
1445 | { | |
1446 | /* It's not clear to me why we reach this point when | |
1447 | stop_soon_quietly, but with this test, at least we | |
1448 | don't print out warnings for every child forked (eg, on | |
1449 | decstation). 22apr93 rich@cygnus.com. */ | |
1450 | if (!stop_soon_quietly) | |
c906108c | 1451 | { |
c5aa993b JM |
1452 | static int blurb_printed = 0; |
1453 | ||
1454 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1455 | paddr_nz (pc)); | |
1456 | ||
1457 | if (!blurb_printed) | |
c906108c | 1458 | { |
c5aa993b JM |
1459 | /* This actually happens frequently in embedded |
1460 | development, when you first connect to a board | |
1461 | and your stack pointer and pc are nowhere in | |
1462 | particular. This message needs to give people | |
1463 | in that situation enough information to | |
1464 | determine that it's no big deal. */ | |
1465 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1466 | GDB is unable to find the start of the function at 0x%s\n\ |
1467 | and thus can't determine the size of that function's stack frame.\n\ | |
1468 | This means that GDB may be unable to access that stack frame, or\n\ | |
1469 | the frames below it.\n\ | |
1470 | This problem is most likely caused by an invalid program counter or\n\ | |
1471 | stack pointer.\n\ | |
1472 | However, if you think GDB should simply search farther back\n\ | |
1473 | from 0x%s for code which looks like the beginning of a\n\ | |
1474 | function, you can increase the range of the search using the `set\n\ | |
1475 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1476 | paddr_nz (pc), paddr_nz (pc)); |
1477 | blurb_printed = 1; | |
c906108c | 1478 | } |
c906108c SS |
1479 | } |
1480 | ||
c5aa993b JM |
1481 | return 0; |
1482 | } | |
1483 | else if (pc_is_mips16 (start_pc)) | |
1484 | { | |
1485 | unsigned short inst; | |
1486 | ||
1487 | /* On MIPS16, any one of the following is likely to be the | |
1488 | start of a function: | |
1489 | entry | |
1490 | addiu sp,-n | |
1491 | daddiu sp,-n | |
1492 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1493 | inst = mips_fetch_instruction (start_pc); | |
1494 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1495 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1496 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1497 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1498 | break; | |
1499 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1500 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1501 | seen_adjsp = 1; | |
1502 | else | |
1503 | seen_adjsp = 0; | |
1504 | } | |
1505 | else if (mips_about_to_return (start_pc)) | |
1506 | { | |
1507 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1508 | break; | |
1509 | } | |
1510 | ||
c906108c | 1511 | #if 0 |
c5aa993b JM |
1512 | /* skip nops (usually 1) 0 - is this */ |
1513 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) | |
1514 | start_pc += MIPS_INSTLEN; | |
c906108c | 1515 | #endif |
c5aa993b | 1516 | return start_pc; |
c906108c SS |
1517 | } |
1518 | ||
1519 | /* Fetch the immediate value from a MIPS16 instruction. | |
1520 | If the previous instruction was an EXTEND, use it to extend | |
1521 | the upper bits of the immediate value. This is a helper function | |
1522 | for mips16_heuristic_proc_desc. */ | |
1523 | ||
1524 | static int | |
1525 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) | |
c5aa993b JM |
1526 | unsigned short prev_inst; /* previous instruction */ |
1527 | unsigned short inst; /* current instruction */ | |
1528 | int nbits; /* number of bits in imm field */ | |
1529 | int scale; /* scale factor to be applied to imm */ | |
1530 | int is_signed; /* is the imm field signed? */ | |
c906108c SS |
1531 | { |
1532 | int offset; | |
1533 | ||
1534 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1535 | { | |
1536 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1537 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1538 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1539 | return offset | (inst & 0x1f); | |
1540 | } | |
1541 | else | |
1542 | { | |
1543 | int max_imm = 1 << nbits; | |
1544 | int mask = max_imm - 1; | |
1545 | int sign_bit = max_imm >> 1; | |
1546 | ||
1547 | offset = inst & mask; | |
1548 | if (is_signed && (offset & sign_bit)) | |
1549 | offset = 0 - (max_imm - offset); | |
1550 | return offset * scale; | |
1551 | } | |
1552 | } | |
1553 | ||
1554 | ||
1555 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1556 | stream from start_pc to limit_pc. */ | |
1557 | ||
1558 | static void | |
c5aa993b JM |
1559 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp) |
1560 | CORE_ADDR start_pc, limit_pc; | |
1561 | struct frame_info *next_frame; | |
1562 | CORE_ADDR sp; | |
c906108c SS |
1563 | { |
1564 | CORE_ADDR cur_pc; | |
1565 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1566 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1567 | unsigned inst = 0; /* current instruction */ | |
1568 | unsigned entry_inst = 0; /* the entry instruction */ | |
1569 | int reg, offset; | |
1570 | ||
c5aa993b JM |
1571 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1572 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1573 | |
1574 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1575 | { | |
1576 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1577 | the immediate offset extension from it in mips16_get_imm. */ | |
1578 | prev_inst = inst; | |
1579 | ||
1580 | /* Fetch and decode the instruction. */ | |
1581 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1582 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1583 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1584 | { | |
1585 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1586 | if (offset < 0) /* negative stack adjustment? */ |
1587 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1588 | else |
1589 | /* Exit loop if a positive stack adjustment is found, which | |
1590 | usually means that the stack cleanup code in the function | |
1591 | epilogue is reached. */ | |
1592 | break; | |
1593 | } | |
1594 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1595 | { | |
1596 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1597 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1598 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1599 | set_reg_offset (reg, sp + offset); |
1600 | } | |
1601 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1602 | { | |
1603 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1604 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1605 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1606 | set_reg_offset (reg, sp + offset); |
1607 | } | |
1608 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1609 | { | |
1610 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1611 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1612 | set_reg_offset (RA_REGNUM, sp + offset); |
1613 | } | |
1614 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1615 | { | |
1616 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1617 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1618 | set_reg_offset (RA_REGNUM, sp + offset); |
1619 | } | |
c5aa993b | 1620 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1621 | { |
1622 | frame_addr = sp; | |
1623 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1624 | } | |
1625 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1626 | { | |
1627 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1628 | frame_addr = sp + offset; | |
1629 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1630 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1631 | } | |
1632 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1633 | { | |
1634 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1635 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1636 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1637 | set_reg_offset (reg, frame_addr + offset); |
1638 | } | |
1639 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1640 | { | |
1641 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1642 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1643 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1644 | set_reg_offset (reg, frame_addr + offset); |
1645 | } | |
c5aa993b JM |
1646 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1647 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1648 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1649 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1650 | } |
1651 | ||
c5aa993b JM |
1652 | /* The entry instruction is typically the first instruction in a function, |
1653 | and it stores registers at offsets relative to the value of the old SP | |
1654 | (before the prologue). But the value of the sp parameter to this | |
1655 | function is the new SP (after the prologue has been executed). So we | |
1656 | can't calculate those offsets until we've seen the entire prologue, | |
1657 | and can calculate what the old SP must have been. */ | |
1658 | if (entry_inst != 0) | |
1659 | { | |
1660 | int areg_count = (entry_inst >> 8) & 7; | |
1661 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1662 | |
c5aa993b JM |
1663 | /* The entry instruction always subtracts 32 from the SP. */ |
1664 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1665 | |
c5aa993b JM |
1666 | /* Now we can calculate what the SP must have been at the |
1667 | start of the function prologue. */ | |
1668 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1669 | |
c5aa993b JM |
1670 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1671 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1672 | { | |
1673 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1674 | set_reg_offset (reg, sp + offset); | |
1675 | offset += MIPS_SAVED_REGSIZE; | |
1676 | } | |
c906108c | 1677 | |
c5aa993b JM |
1678 | /* Check if the ra register was pushed on the stack. */ |
1679 | offset = -4; | |
1680 | if (entry_inst & 0x20) | |
1681 | { | |
1682 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1683 | set_reg_offset (RA_REGNUM, sp + offset); | |
1684 | offset -= MIPS_SAVED_REGSIZE; | |
1685 | } | |
c906108c | 1686 | |
c5aa993b JM |
1687 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
1688 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1689 | { | |
1690 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1691 | set_reg_offset (reg, sp + offset); | |
1692 | offset -= MIPS_SAVED_REGSIZE; | |
1693 | } | |
1694 | } | |
c906108c SS |
1695 | } |
1696 | ||
1697 | static void | |
c5aa993b JM |
1698 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp) |
1699 | CORE_ADDR start_pc, limit_pc; | |
1700 | struct frame_info *next_frame; | |
1701 | CORE_ADDR sp; | |
c906108c SS |
1702 | { |
1703 | CORE_ADDR cur_pc; | |
c5aa993b | 1704 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 1705 | restart: |
cce74817 | 1706 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 1707 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
1708 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
1709 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
1710 | { | |
1711 | unsigned long inst, high_word, low_word; | |
1712 | int reg; | |
1713 | ||
1714 | /* Fetch the instruction. */ | |
1715 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
1716 | ||
1717 | /* Save some code by pre-extracting some useful fields. */ | |
1718 | high_word = (inst >> 16) & 0xffff; | |
1719 | low_word = inst & 0xffff; | |
1720 | reg = high_word & 0x1f; | |
1721 | ||
c5aa993b | 1722 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
1723 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
1724 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1725 | { | |
1726 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 1727 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
1728 | else |
1729 | /* Exit loop if a positive stack adjustment is found, which | |
1730 | usually means that the stack cleanup code in the function | |
1731 | epilogue is reached. */ | |
1732 | break; | |
1733 | } | |
1734 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1735 | { | |
c5aa993b | 1736 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1737 | set_reg_offset (reg, sp + low_word); |
1738 | } | |
1739 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1740 | { | |
1741 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1742 | but the register size used is only 32 bits. Make the address | |
1743 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 1744 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1745 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
1746 | } | |
c5aa993b | 1747 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
1748 | { |
1749 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
1750 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
1751 | frame_addr = sp + low_word; | |
c906108c SS |
1752 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
1753 | { | |
1754 | unsigned alloca_adjust; | |
1755 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1756 | frame_addr = read_next_frame_reg (next_frame, 30); |
1757 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
1758 | if (alloca_adjust > 0) |
1759 | { | |
1760 | /* FP > SP + frame_size. This may be because | |
1761 | * of an alloca or somethings similar. | |
1762 | * Fix sp to "pre-alloca" value, and try again. | |
1763 | */ | |
1764 | sp += alloca_adjust; | |
1765 | goto restart; | |
1766 | } | |
1767 | } | |
1768 | } | |
c5aa993b JM |
1769 | /* move $30,$sp. With different versions of gas this will be either |
1770 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1771 | Accept any one of these. */ | |
c906108c SS |
1772 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
1773 | { | |
1774 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1775 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1776 | { | |
1777 | unsigned alloca_adjust; | |
1778 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1779 | frame_addr = read_next_frame_reg (next_frame, 30); |
1780 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
1781 | if (alloca_adjust > 0) |
1782 | { | |
1783 | /* FP > SP + frame_size. This may be because | |
1784 | * of an alloca or somethings similar. | |
1785 | * Fix sp to "pre-alloca" value, and try again. | |
1786 | */ | |
1787 | sp += alloca_adjust; | |
1788 | goto restart; | |
1789 | } | |
1790 | } | |
1791 | } | |
c5aa993b | 1792 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 1793 | { |
c5aa993b | 1794 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1795 | set_reg_offset (reg, frame_addr + low_word); |
1796 | } | |
1797 | } | |
1798 | } | |
1799 | ||
1800 | static mips_extra_func_info_t | |
c5aa993b JM |
1801 | heuristic_proc_desc (start_pc, limit_pc, next_frame) |
1802 | CORE_ADDR start_pc, limit_pc; | |
1803 | struct frame_info *next_frame; | |
c906108c SS |
1804 | { |
1805 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1806 | ||
c5aa993b JM |
1807 | if (start_pc == 0) |
1808 | return NULL; | |
1809 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 1810 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1811 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
1812 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
1813 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
1814 | ||
1815 | if (start_pc + 200 < limit_pc) | |
1816 | limit_pc = start_pc + 200; | |
1817 | if (pc_is_mips16 (start_pc)) | |
1818 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1819 | else | |
1820 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
1821 | return &temp_proc_desc; | |
1822 | } | |
1823 | ||
1824 | static mips_extra_func_info_t | |
1825 | non_heuristic_proc_desc (pc, addrptr) | |
1826 | CORE_ADDR pc; | |
1827 | CORE_ADDR *addrptr; | |
1828 | { | |
1829 | CORE_ADDR startaddr; | |
1830 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 1831 | struct block *b = block_for_pc (pc); |
c906108c SS |
1832 | struct symbol *sym; |
1833 | ||
1834 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
1835 | if (addrptr) | |
1836 | *addrptr = startaddr; | |
1837 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) | |
1838 | sym = NULL; | |
1839 | else | |
1840 | { | |
1841 | if (startaddr > BLOCK_START (b)) | |
1842 | /* This is the "pathological" case referred to in a comment in | |
1843 | print_frame_info. It might be better to move this check into | |
1844 | symbol reading. */ | |
1845 | sym = NULL; | |
1846 | else | |
1847 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
1848 | } | |
1849 | ||
1850 | /* If we never found a PDR for this function in symbol reading, then | |
1851 | examine prologues to find the information. */ | |
1852 | if (sym) | |
1853 | { | |
1854 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
1855 | if (PROC_FRAME_REG (proc_desc) == -1) | |
1856 | return NULL; | |
1857 | else | |
1858 | return proc_desc; | |
1859 | } | |
1860 | else | |
1861 | return NULL; | |
1862 | } | |
1863 | ||
1864 | ||
1865 | static mips_extra_func_info_t | |
1866 | find_proc_desc (pc, next_frame) | |
1867 | CORE_ADDR pc; | |
1868 | struct frame_info *next_frame; | |
1869 | { | |
1870 | mips_extra_func_info_t proc_desc; | |
1871 | CORE_ADDR startaddr; | |
1872 | ||
1873 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1874 | ||
1875 | if (proc_desc) | |
1876 | { | |
1877 | /* IF this is the topmost frame AND | |
1878 | * (this proc does not have debugging information OR | |
1879 | * the PC is in the procedure prologue) | |
1880 | * THEN create a "heuristic" proc_desc (by analyzing | |
1881 | * the actual code) to replace the "official" proc_desc. | |
1882 | */ | |
1883 | if (next_frame == NULL) | |
1884 | { | |
1885 | struct symtab_and_line val; | |
1886 | struct symbol *proc_symbol = | |
c5aa993b | 1887 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
1888 | |
1889 | if (proc_symbol) | |
1890 | { | |
1891 | val = find_pc_line (BLOCK_START | |
c5aa993b | 1892 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
1893 | 0); |
1894 | val.pc = val.end ? val.end : pc; | |
1895 | } | |
1896 | if (!proc_symbol || pc < val.pc) | |
1897 | { | |
1898 | mips_extra_func_info_t found_heuristic = | |
c5aa993b JM |
1899 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
1900 | pc, next_frame); | |
c906108c SS |
1901 | if (found_heuristic) |
1902 | proc_desc = found_heuristic; | |
1903 | } | |
1904 | } | |
1905 | } | |
1906 | else | |
1907 | { | |
1908 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
1909 | by procedure call dummys. However, the procedures being called ought |
1910 | to have their own proc_descs, and even if they don't, | |
1911 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
1912 | |
1913 | register struct linked_proc_info *link; | |
1914 | ||
1915 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
1916 | if (PROC_LOW_ADDR (&link->info) <= pc |
1917 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
1918 | return &link->info; |
1919 | ||
1920 | if (startaddr == 0) | |
1921 | startaddr = heuristic_proc_start (pc); | |
1922 | ||
1923 | proc_desc = | |
1924 | heuristic_proc_desc (startaddr, pc, next_frame); | |
1925 | } | |
1926 | return proc_desc; | |
1927 | } | |
1928 | ||
1929 | static CORE_ADDR | |
c5aa993b JM |
1930 | get_frame_pointer (frame, proc_desc) |
1931 | struct frame_info *frame; | |
1932 | mips_extra_func_info_t proc_desc; | |
c906108c SS |
1933 | { |
1934 | return ADDR_BITS_REMOVE ( | |
c5aa993b JM |
1935 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + |
1936 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
1937 | } |
1938 | ||
1939 | mips_extra_func_info_t cached_proc_desc; | |
1940 | ||
1941 | CORE_ADDR | |
c5aa993b JM |
1942 | mips_frame_chain (frame) |
1943 | struct frame_info *frame; | |
c906108c SS |
1944 | { |
1945 | mips_extra_func_info_t proc_desc; | |
1946 | CORE_ADDR tmp; | |
c5aa993b | 1947 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
1948 | |
1949 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
1950 | return 0; | |
1951 | ||
1952 | /* Check if the PC is inside a call stub. If it is, fetch the | |
1953 | PC of the caller of that stub. */ | |
1954 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
1955 | saved_pc = tmp; | |
1956 | ||
1957 | /* Look up the procedure descriptor for this PC. */ | |
c5aa993b | 1958 | proc_desc = find_proc_desc (saved_pc, frame); |
c906108c SS |
1959 | if (!proc_desc) |
1960 | return 0; | |
1961 | ||
1962 | cached_proc_desc = proc_desc; | |
1963 | ||
1964 | /* If no frame pointer and frame size is zero, we must be at end | |
1965 | of stack (or otherwise hosed). If we don't check frame size, | |
1966 | we loop forever if we see a zero size frame. */ | |
1967 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
1968 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
c5aa993b JM |
1969 | /* The previous frame from a sigtramp frame might be frameless |
1970 | and have frame size zero. */ | |
c906108c SS |
1971 | && !frame->signal_handler_caller) |
1972 | return 0; | |
1973 | else | |
1974 | return get_frame_pointer (frame, proc_desc); | |
1975 | } | |
1976 | ||
1977 | void | |
c5aa993b | 1978 | mips_init_extra_frame_info (fromleaf, fci) |
cce74817 | 1979 | int fromleaf; |
c906108c SS |
1980 | struct frame_info *fci; |
1981 | { | |
1982 | int regnum; | |
1983 | ||
1984 | /* Use proc_desc calculated in frame_chain */ | |
1985 | mips_extra_func_info_t proc_desc = | |
c5aa993b | 1986 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next); |
c906108c | 1987 | |
cce74817 JM |
1988 | fci->extra_info = (struct frame_extra_info *) |
1989 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1990 | ||
c906108c | 1991 | fci->saved_regs = NULL; |
cce74817 | 1992 | fci->extra_info->proc_desc = |
c906108c SS |
1993 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
1994 | if (proc_desc) | |
1995 | { | |
1996 | /* Fixup frame-pointer - only needed for top frame */ | |
1997 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
1998 | Get the value of the frame relative sp, procedure might have been |
1999 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2000 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2001 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2002 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2003 | else | |
2004 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2005 | ||
2006 | if (proc_desc == &temp_proc_desc) | |
2007 | { | |
2008 | char *name; | |
2009 | ||
2010 | /* Do not set the saved registers for a sigtramp frame, | |
2011 | mips_find_saved_registers will do that for us. | |
2012 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2013 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2014 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
2015 | if (!IN_SIGTRAMP (fci->pc, name)) |
2016 | { | |
c5aa993b | 2017 | frame_saved_regs_zalloc (fci); |
cce74817 | 2018 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2019 | fci->saved_regs[PC_REGNUM] |
2020 | = fci->saved_regs[RA_REGNUM]; | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2025 | /* assume we can't tell how many args for now */ |
2026 | fci->extra_info->num_args = -1; | |
c906108c SS |
2027 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2028 | { | |
c5aa993b | 2029 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2030 | { |
cce74817 | 2031 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2032 | break; |
2033 | } | |
c5aa993b | 2034 | } |
c906108c SS |
2035 | } |
2036 | } | |
2037 | ||
2038 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2039 | we basically have to look at symbol information for the function | |
2040 | that we stopped in, which tells us *which* register (if any) is | |
2041 | the base of the frame pointer, and what offset from that register | |
2042 | the frame itself is at. | |
2043 | ||
2044 | This presents a problem when trying to examine a stack in memory | |
2045 | (that isn't executing at the moment), using the "frame" command. We | |
2046 | don't have a PC, nor do we have any registers except SP. | |
2047 | ||
2048 | This routine takes two arguments, SP and PC, and tries to make the | |
2049 | cached frames look as if these two arguments defined a frame on the | |
2050 | cache. This allows the rest of info frame to extract the important | |
2051 | arguments without difficulty. */ | |
2052 | ||
2053 | struct frame_info * | |
2054 | setup_arbitrary_frame (argc, argv) | |
2055 | int argc; | |
2056 | CORE_ADDR *argv; | |
2057 | { | |
2058 | if (argc != 2) | |
2059 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2060 | ||
2061 | return create_new_frame (argv[0], argv[1]); | |
2062 | } | |
2063 | ||
c906108c | 2064 | CORE_ADDR |
c5aa993b | 2065 | mips_push_arguments (nargs, args, sp, struct_return, struct_addr) |
c906108c SS |
2066 | int nargs; |
2067 | value_ptr *args; | |
2068 | CORE_ADDR sp; | |
2069 | int struct_return; | |
2070 | CORE_ADDR struct_addr; | |
2071 | { | |
2072 | int argreg; | |
2073 | int float_argreg; | |
2074 | int argnum; | |
2075 | int len = 0; | |
2076 | int stack_offset = 0; | |
2077 | ||
2078 | /* Macros to round N up or down to the next A boundary; A must be | |
2079 | a power of two. */ | |
2080 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2081 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
c5aa993b | 2082 | |
c906108c SS |
2083 | /* First ensure that the stack and structure return address (if any) |
2084 | are properly aligned. The stack has to be at least 64-bit aligned | |
2085 | even on 32-bit machines, because doubles must be 64-bit aligned. | |
2086 | On at least one MIPS variant, stack frames need to be 128-bit | |
2087 | aligned, so we round to this widest known alignment. */ | |
2088 | sp = ROUND_DOWN (sp, 16); | |
7a292a7a | 2089 | struct_addr = ROUND_DOWN (struct_addr, MIPS_SAVED_REGSIZE); |
c5aa993b | 2090 | |
c906108c SS |
2091 | /* Now make space on the stack for the args. We allocate more |
2092 | than necessary for EABI, because the first few arguments are | |
2093 | passed in registers, but that's OK. */ | |
2094 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 2095 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_SAVED_REGSIZE); |
c906108c SS |
2096 | sp -= ROUND_UP (len, 16); |
2097 | ||
2098 | /* Initialize the integer and float register pointers. */ | |
2099 | argreg = A0_REGNUM; | |
2100 | float_argreg = FPA0_REGNUM; | |
2101 | ||
2102 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
2103 | if (struct_return) | |
c5aa993b | 2104 | write_register (argreg++, struct_addr); |
c906108c SS |
2105 | |
2106 | /* Now load as many as possible of the first arguments into | |
2107 | registers, and push the rest onto the stack. Loop thru args | |
2108 | from first to last. */ | |
2109 | for (argnum = 0; argnum < nargs; argnum++) | |
2110 | { | |
2111 | char *val; | |
2112 | char valbuf[MAX_REGISTER_RAW_SIZE]; | |
2113 | value_ptr arg = args[argnum]; | |
2114 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2115 | int len = TYPE_LENGTH (arg_type); | |
2116 | enum type_code typecode = TYPE_CODE (arg_type); | |
2117 | ||
2118 | /* The EABI passes structures that do not fit in a register by | |
c5aa993b | 2119 | reference. In all other cases, pass the structure by value. */ |
7a292a7a | 2120 | if (MIPS_EABI && len > MIPS_SAVED_REGSIZE && |
c906108c SS |
2121 | (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
2122 | { | |
7a292a7a | 2123 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2124 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2125 | len = MIPS_SAVED_REGSIZE; |
c906108c SS |
2126 | val = valbuf; |
2127 | } | |
2128 | else | |
c5aa993b | 2129 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2130 | |
2131 | /* 32-bit ABIs always start floating point arguments in an | |
2132 | even-numbered floating point register. */ | |
2133 | if (!FP_REGISTER_DOUBLE && typecode == TYPE_CODE_FLT | |
c5aa993b | 2134 | && (float_argreg & 1)) |
c906108c SS |
2135 | float_argreg++; |
2136 | ||
2137 | /* Floating point arguments passed in registers have to be | |
2138 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2139 | are passed in register pairs; the even register gets |
2140 | the low word, and the odd register gets the high word. | |
2141 | On non-EABI processors, the first two floating point arguments are | |
2142 | also copied to general registers, because MIPS16 functions | |
2143 | don't use float registers for arguments. This duplication of | |
2144 | arguments in general registers can't hurt non-MIPS16 functions | |
2145 | because those registers are normally skipped. */ | |
c906108c SS |
2146 | if (typecode == TYPE_CODE_FLT |
2147 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM | |
2148 | && MIPS_FPU_TYPE != MIPS_FPU_NONE) | |
2149 | { | |
2150 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2151 | { | |
2152 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; | |
2153 | unsigned long regval; | |
2154 | ||
2155 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2156 | regval = extract_unsigned_integer (val + low_offset, 4); |
c906108c SS |
2157 | write_register (float_argreg++, regval); |
2158 | if (!MIPS_EABI) | |
c5aa993b | 2159 | write_register (argreg + 1, regval); |
c906108c SS |
2160 | |
2161 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2162 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
c906108c SS |
2163 | write_register (float_argreg++, regval); |
2164 | if (!MIPS_EABI) | |
c5aa993b | 2165 | { |
c906108c SS |
2166 | write_register (argreg, regval); |
2167 | argreg += 2; | |
2168 | } | |
2169 | ||
2170 | } | |
2171 | else | |
2172 | { | |
2173 | /* This is a floating point value that fits entirely | |
2174 | in a single register. */ | |
53a5351d JM |
2175 | /* On 32 bit ABI's the float_argreg is further adjusted |
2176 | above to ensure that it is even register aligned. */ | |
c906108c SS |
2177 | CORE_ADDR regval = extract_address (val, len); |
2178 | write_register (float_argreg++, regval); | |
2179 | if (!MIPS_EABI) | |
c5aa993b | 2180 | { |
53a5351d JM |
2181 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
2182 | registers for each argument. The below is (my | |
2183 | guess) to ensure that the corresponding integer | |
2184 | register has reserved the same space. */ | |
c906108c SS |
2185 | write_register (argreg, regval); |
2186 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
2187 | } | |
2188 | } | |
2189 | } | |
2190 | else | |
2191 | { | |
2192 | /* Copy the argument to general registers or the stack in | |
2193 | register-sized pieces. Large arguments are split between | |
2194 | registers and stack. */ | |
2195 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2196 | are treated specially: Irix cc passes them in registers | |
2197 | where gcc sometimes puts them on the stack. For maximum | |
2198 | compatibility, we will put them in both places. */ | |
2199 | ||
c5aa993b | 2200 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2201 | (len % MIPS_SAVED_REGSIZE != 0)); |
c906108c SS |
2202 | while (len > 0) |
2203 | { | |
7a292a7a | 2204 | int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; |
c906108c SS |
2205 | |
2206 | if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct) | |
2207 | { | |
2208 | /* Write this portion of the argument to the stack. */ | |
2209 | /* Should shorter than int integer values be | |
2210 | promoted to int before being stored? */ | |
2211 | ||
2212 | int longword_offset = 0; | |
2213 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
7a292a7a | 2214 | { |
d929b26f | 2215 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2216 | (typecode == TYPE_CODE_INT || |
2217 | typecode == TYPE_CODE_PTR || | |
2218 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2219 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2220 | else if ((typecode == TYPE_CODE_STRUCT || |
2221 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2222 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2223 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2224 | } |
c5aa993b JM |
2225 | |
2226 | write_memory (sp + stack_offset + longword_offset, | |
c906108c SS |
2227 | val, partial_len); |
2228 | } | |
2229 | ||
2230 | /* Note!!! This is NOT an else clause. | |
c5aa993b | 2231 | Odd sized structs may go thru BOTH paths. */ |
c906108c SS |
2232 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
2233 | { | |
2234 | CORE_ADDR regval = extract_address (val, partial_len); | |
2235 | ||
2236 | /* A non-floating-point argument being passed in a | |
2237 | general register. If a struct or union, and if | |
2238 | the remaining length is smaller than the register | |
2239 | size, we have to adjust the register value on | |
2240 | big endian targets. | |
2241 | ||
2242 | It does not seem to be necessary to do the | |
2243 | same for integral types. | |
2244 | ||
2245 | Also don't do this adjustment on EABI and O64 | |
2246 | binaries. */ | |
2247 | ||
2248 | if (!MIPS_EABI | |
7a292a7a | 2249 | && MIPS_SAVED_REGSIZE < 8 |
c906108c | 2250 | && TARGET_BYTE_ORDER == BIG_ENDIAN |
7a292a7a | 2251 | && partial_len < MIPS_SAVED_REGSIZE |
c906108c SS |
2252 | && (typecode == TYPE_CODE_STRUCT || |
2253 | typecode == TYPE_CODE_UNION)) | |
c5aa993b | 2254 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * |
c906108c SS |
2255 | TARGET_CHAR_BIT); |
2256 | ||
2257 | write_register (argreg, regval); | |
2258 | argreg++; | |
c5aa993b | 2259 | |
c906108c SS |
2260 | /* If this is the old ABI, prevent subsequent floating |
2261 | point arguments from being passed in floating point | |
2262 | registers. */ | |
2263 | if (!MIPS_EABI) | |
2264 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
2265 | } | |
c5aa993b | 2266 | |
c906108c SS |
2267 | len -= partial_len; |
2268 | val += partial_len; | |
2269 | ||
2270 | /* The offset onto the stack at which we will start | |
c5aa993b JM |
2271 | copying parameters (after the registers are used up) |
2272 | begins at (4 * MIPS_REGSIZE) in the old ABI. This | |
2273 | leaves room for the "home" area for register parameters. | |
c906108c | 2274 | |
c5aa993b JM |
2275 | In the new EABI (and the NABI32), the 8 register parameters |
2276 | do not have "home" stack space reserved for them, so the | |
2277 | stack offset does not get incremented until after | |
2278 | we have used up the 8 parameter registers. */ | |
c906108c | 2279 | |
d929b26f AC |
2280 | if (MIPS_REGS_HAVE_HOME_P || argnum >= 8) |
2281 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
c906108c SS |
2282 | } |
2283 | } | |
2284 | } | |
2285 | ||
0f71a2f6 JM |
2286 | /* Return adjusted stack pointer. */ |
2287 | return sp; | |
2288 | } | |
2289 | ||
2290 | CORE_ADDR | |
2291 | mips_push_return_address (pc, sp) | |
2292 | CORE_ADDR pc; | |
2293 | CORE_ADDR sp; | |
2294 | { | |
c906108c SS |
2295 | /* Set the return address register to point to the entry |
2296 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 2297 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
2298 | return sp; |
2299 | } | |
2300 | ||
2301 | static void | |
c5aa993b | 2302 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c SS |
2303 | { |
2304 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
7a292a7a SS |
2305 | int regsize; |
2306 | int offset; | |
2307 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
2308 | { | |
2309 | regsize = MIPS_SAVED_REGSIZE; | |
2310 | offset = (TARGET_BYTE_ORDER == BIG_ENDIAN | |
2311 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE | |
2312 | : 0); | |
2313 | } | |
2314 | else | |
2315 | { | |
2316 | regsize = REGISTER_RAW_SIZE (regno); | |
2317 | offset = 0; | |
2318 | } | |
c906108c SS |
2319 | *sp -= regsize; |
2320 | read_register_gen (regno, buffer); | |
7a292a7a | 2321 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
2322 | } |
2323 | ||
2324 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
2325 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
2326 | ||
2327 | void | |
7a292a7a | 2328 | mips_push_dummy_frame () |
c906108c SS |
2329 | { |
2330 | int ireg; | |
c5aa993b JM |
2331 | struct linked_proc_info *link = (struct linked_proc_info *) |
2332 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c SS |
2333 | mips_extra_func_info_t proc_desc = &link->info; |
2334 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); | |
2335 | CORE_ADDR old_sp = sp; | |
2336 | link->next = linked_proc_desc_table; | |
2337 | linked_proc_desc_table = link; | |
2338 | ||
2339 | /* FIXME! are these correct ? */ | |
c5aa993b | 2340 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
2341 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
2342 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
2343 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
2344 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
2345 | /* | |
2346 | * The registers we must save are all those not preserved across | |
2347 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
2348 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
2349 | * and FP Control/Status registers. | |
2350 | * | |
2351 | * | |
2352 | * Dummy frame layout: | |
2353 | * (high memory) | |
c5aa993b JM |
2354 | * Saved PC |
2355 | * Saved MMHI, MMLO, FPC_CSR | |
2356 | * Saved R31 | |
2357 | * Saved R28 | |
2358 | * ... | |
2359 | * Saved R1 | |
c906108c SS |
2360 | * Saved D18 (i.e. F19, F18) |
2361 | * ... | |
2362 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 2363 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
2364 | * (low memory) |
2365 | */ | |
2366 | ||
2367 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
2368 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
2369 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
2370 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
2371 | mips_push_register (&sp, PC_REGNUM); |
2372 | mips_push_register (&sp, HI_REGNUM); | |
2373 | mips_push_register (&sp, LO_REGNUM); | |
2374 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
2375 | ||
2376 | /* Save general CPU registers */ | |
c5aa993b | 2377 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 2378 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
2379 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
2380 | for (ireg = 32; --ireg >= 0;) | |
2381 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2382 | mips_push_register (&sp, ireg); |
2383 | ||
2384 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 2385 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
2386 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
2387 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
2388 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
2389 | from FP. */ | |
c5aa993b JM |
2390 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
2391 | for (ireg = 32; --ireg >= 0;) | |
2392 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
2393 | mips_push_register (&sp, ireg + FP0_REGNUM); |
2394 | ||
2395 | /* Update the frame pointer for the call dummy and the stack pointer. | |
2396 | Set the procedure's starting and ending addresses to point to the | |
2397 | call dummy address at the entry point. */ | |
2398 | write_register (PUSH_FP_REGNUM, old_sp); | |
2399 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
2400 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
2401 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
2402 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
2403 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
2404 | } |
2405 | ||
2406 | void | |
c5aa993b | 2407 | mips_pop_frame () |
c906108c SS |
2408 | { |
2409 | register int regnum; | |
2410 | struct frame_info *frame = get_current_frame (); | |
2411 | CORE_ADDR new_sp = FRAME_FP (frame); | |
2412 | ||
cce74817 | 2413 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 2414 | |
c5aa993b | 2415 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c SS |
2416 | if (frame->saved_regs == NULL) |
2417 | mips_find_saved_regs (frame); | |
2418 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
2419 | { | |
2420 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
2421 | && frame->saved_regs[regnum]) | |
2422 | write_register (regnum, | |
2423 | read_memory_integer (frame->saved_regs[regnum], | |
c5aa993b | 2424 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2425 | } |
2426 | write_register (SP_REGNUM, new_sp); | |
2427 | flush_cached_frames (); | |
2428 | ||
c5aa993b | 2429 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
2430 | { |
2431 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
2432 | ||
2433 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
2434 | pi_ptr != NULL; | |
2435 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
2436 | { | |
2437 | if (&pi_ptr->info == proc_desc) | |
2438 | break; | |
2439 | } | |
2440 | ||
2441 | if (pi_ptr == NULL) | |
2442 | error ("Can't locate dummy extra frame info\n"); | |
2443 | ||
2444 | if (prev_ptr != NULL) | |
2445 | prev_ptr->next = pi_ptr->next; | |
2446 | else | |
2447 | linked_proc_desc_table = pi_ptr->next; | |
2448 | ||
2449 | free (pi_ptr); | |
2450 | ||
2451 | write_register (HI_REGNUM, | |
c5aa993b | 2452 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2453 | MIPS_SAVED_REGSIZE)); |
c906108c | 2454 | write_register (LO_REGNUM, |
c5aa993b | 2455 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2456 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2457 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
2458 | write_register (FCRCS_REGNUM, | |
c5aa993b | 2459 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 2460 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
2461 | } |
2462 | } | |
2463 | ||
2464 | static void | |
2465 | mips_print_register (regnum, all) | |
2466 | int regnum, all; | |
2467 | { | |
2468 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2469 | ||
2470 | /* Get the data in raw format. */ | |
2471 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2472 | { | |
2473 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
2474 | return; | |
2475 | } | |
2476 | ||
2477 | /* If an even floating point register, also print as double. */ | |
2478 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT | |
c5aa993b JM |
2479 | && !((regnum - FP0_REGNUM) & 1)) |
2480 | if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */ | |
c906108c | 2481 | { |
c5aa993b | 2482 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; |
c906108c SS |
2483 | |
2484 | read_relative_register_raw_bytes (regnum, dbuffer); | |
c5aa993b | 2485 | read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE); |
c906108c SS |
2486 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); |
2487 | ||
c5aa993b | 2488 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
c906108c SS |
2489 | val_print (builtin_type_double, dbuffer, 0, 0, |
2490 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2491 | printf_filtered ("); "); | |
2492 | } | |
2493 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
2494 | ||
2495 | /* The problem with printing numeric register names (r26, etc.) is that | |
2496 | the user can't use them on input. Probably the best solution is to | |
2497 | fix it so that either the numeric or the funky (a2, etc.) names | |
2498 | are accepted on input. */ | |
2499 | if (regnum < MIPS_NUMREGS) | |
2500 | printf_filtered ("(r%d): ", regnum); | |
2501 | else | |
2502 | printf_filtered (": "); | |
2503 | ||
2504 | /* If virtual format is floating, print it that way. */ | |
2505 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
2506 | if (FP_REGISTER_DOUBLE) | |
c5aa993b | 2507 | { /* show 8-byte floats as float AND double: */ |
c906108c SS |
2508 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2509 | ||
2510 | printf_filtered (" (float) "); | |
2511 | val_print (builtin_type_float, raw_buffer + offset, 0, 0, | |
2512 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2513 | printf_filtered (", (double) "); | |
2514 | val_print (builtin_type_double, raw_buffer, 0, 0, | |
2515 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2516 | } | |
2517 | else | |
2518 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
2519 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
2520 | /* Else print as integer in hex. */ | |
2521 | else | |
ed9a39eb JM |
2522 | { |
2523 | int offset; | |
2524 | ||
2525 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
2526 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); | |
2527 | else | |
2528 | offset = 0; | |
2529 | ||
2530 | print_scalar_formatted (raw_buffer + offset, | |
2531 | REGISTER_VIRTUAL_TYPE (regnum), | |
2532 | 'x', 0, gdb_stdout); | |
2533 | } | |
c906108c SS |
2534 | } |
2535 | ||
2536 | /* Replacement for generic do_registers_info. | |
2537 | Print regs in pretty columns. */ | |
2538 | ||
2539 | static int | |
2540 | do_fp_register_row (regnum) | |
2541 | int regnum; | |
c5aa993b | 2542 | { /* do values for FP (float) regs */ |
c906108c SS |
2543 | char *raw_buffer[2]; |
2544 | char *dbl_buffer; | |
2545 | /* use HI and LO to control the order of combining two flt regs */ | |
2546 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); | |
2547 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); | |
2548 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ | |
2549 | int inv1, inv2, inv3; | |
c5aa993b | 2550 | |
c906108c SS |
2551 | raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
2552 | raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2553 | dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); | |
2554 | ||
2555 | /* Get the data in raw format. */ | |
2556 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) | |
2557 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
c5aa993b | 2558 | if (REGISTER_RAW_SIZE (regnum) == 4) |
c906108c SS |
2559 | { |
2560 | /* 4-byte registers: we can fit two registers per row. */ | |
2561 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
2562 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) | |
c5aa993b | 2563 | error ("can't read register %d (%s)", |
c906108c SS |
2564 | regnum + 1, REGISTER_NAME (regnum + 1)); |
2565 | ||
2566 | /* copy the two floats into one double, and unpack both */ | |
65edb64b | 2567 | memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b JM |
2568 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); |
2569 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); | |
2570 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); | |
2571 | ||
2572 | printf_filtered (inv1 ? " %-5s: <invalid float>" : | |
2573 | " %-5s%-17.9g", REGISTER_NAME (regnum), flt1); | |
2574 | printf_filtered (inv2 ? " %-5s: <invalid float>" : | |
c906108c | 2575 | " %-5s%-17.9g", REGISTER_NAME (regnum + 1), flt2); |
c5aa993b | 2576 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
c906108c SS |
2577 | " dbl: %-24.17g\n", doub); |
2578 | /* may want to do hex display here (future enhancement) */ | |
c5aa993b | 2579 | regnum += 2; |
c906108c SS |
2580 | } |
2581 | else | |
c5aa993b | 2582 | { /* eight byte registers: print each one as float AND as double. */ |
c906108c SS |
2583 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
2584 | ||
65edb64b | 2585 | memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c5aa993b | 2586 | flt1 = unpack_double (builtin_type_float, |
c906108c | 2587 | &raw_buffer[HI][offset], &inv1); |
c5aa993b | 2588 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); |
c906108c | 2589 | |
c5aa993b | 2590 | printf_filtered (inv1 ? " %-5s: <invalid float>" : |
c906108c | 2591 | " %-5s flt: %-17.9g", REGISTER_NAME (regnum), flt1); |
c5aa993b | 2592 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
c906108c SS |
2593 | " dbl: %-24.17g\n", doub); |
2594 | /* may want to do hex display here (future enhancement) */ | |
2595 | regnum++; | |
2596 | } | |
2597 | return regnum; | |
2598 | } | |
2599 | ||
2600 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
2601 | ||
2602 | static int | |
2603 | do_gp_register_row (regnum) | |
2604 | int regnum; | |
2605 | { | |
2606 | /* do values for GP (int) regs */ | |
2607 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
2608 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ | |
2609 | int col, byte; | |
2610 | int start_regnum = regnum; | |
2611 | int numregs = NUM_REGS; | |
2612 | ||
2613 | ||
2614 | /* For GP registers, we print a separate row of names above the vals */ | |
2615 | printf_filtered (" "); | |
2616 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2617 | { | |
2618 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2619 | continue; /* unused register */ |
c906108c | 2620 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
2621 | break; /* end the row: reached FP register */ |
2622 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
2623 | REGISTER_NAME (regnum)); |
2624 | col++; | |
2625 | } | |
c5aa993b | 2626 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
2627 | start_regnum); /* print the R0 to R31 names */ |
2628 | ||
2629 | regnum = start_regnum; /* go back to start of row */ | |
2630 | /* now print the values in hex, 4 or 8 to the row */ | |
2631 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
2632 | { | |
2633 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 2634 | continue; /* unused register */ |
c906108c | 2635 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 2636 | break; /* end row: reached FP register */ |
c906108c SS |
2637 | /* OK: get the data in raw format. */ |
2638 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
2639 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
2640 | /* pad small registers */ | |
43e526b9 | 2641 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
2642 | printf_filtered (" "); |
2643 | /* Now print the register value in hex, endian order. */ | |
2644 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
43e526b9 JM |
2645 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
2646 | byte < REGISTER_RAW_SIZE (regnum); | |
2647 | byte++) | |
c906108c SS |
2648 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2649 | else | |
43e526b9 JM |
2650 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
2651 | byte >= 0; | |
2652 | byte--) | |
c906108c SS |
2653 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
2654 | printf_filtered (" "); | |
2655 | col++; | |
2656 | } | |
c5aa993b | 2657 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
2658 | printf_filtered ("\n"); |
2659 | ||
2660 | return regnum; | |
2661 | } | |
2662 | ||
2663 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
2664 | ||
2665 | void | |
2666 | mips_do_registers_info (regnum, fpregs) | |
2667 | int regnum; | |
2668 | int fpregs; | |
2669 | { | |
c5aa993b | 2670 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
2671 | { |
2672 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2673 | error ("Not a valid register for the current processor type"); | |
2674 | ||
2675 | mips_print_register (regnum, 0); | |
2676 | printf_filtered ("\n"); | |
2677 | } | |
c5aa993b JM |
2678 | else |
2679 | /* do all (or most) registers */ | |
c906108c SS |
2680 | { |
2681 | regnum = 0; | |
2682 | while (regnum < NUM_REGS) | |
2683 | { | |
c5aa993b JM |
2684 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
2685 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
2686 | regnum = do_fp_register_row (regnum); /* FP regs */ |
2687 | else | |
2688 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
2689 | else | |
2690 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
2691 | } | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | /* Return number of args passed to a frame. described by FIP. | |
2696 | Can return -1, meaning no way to tell. */ | |
2697 | ||
2698 | int | |
2699 | mips_frame_num_args (frame) | |
c5aa993b | 2700 | struct frame_info *frame; |
c906108c | 2701 | { |
c5aa993b | 2702 | #if 0 /* FIXME Use or lose this! */ |
c906108c SS |
2703 | struct chain_info_t *p; |
2704 | ||
2705 | p = mips_find_cached_frame (FRAME_FP (frame)); | |
2706 | if (p->valid) | |
2707 | return p->the_info.numargs; | |
2708 | #endif | |
2709 | return -1; | |
2710 | } | |
2711 | ||
2712 | /* Is this a branch with a delay slot? */ | |
2713 | ||
a14ed312 | 2714 | static int is_delayed (unsigned long); |
c906108c SS |
2715 | |
2716 | static int | |
2717 | is_delayed (insn) | |
2718 | unsigned long insn; | |
2719 | { | |
2720 | int i; | |
2721 | for (i = 0; i < NUMOPCODES; ++i) | |
2722 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
2723 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
2724 | break; | |
2725 | return (i < NUMOPCODES | |
2726 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2727 | | INSN_COND_BRANCH_DELAY | |
2728 | | INSN_COND_BRANCH_LIKELY))); | |
2729 | } | |
2730 | ||
2731 | int | |
2732 | mips_step_skips_delay (pc) | |
2733 | CORE_ADDR pc; | |
2734 | { | |
2735 | char buf[MIPS_INSTLEN]; | |
2736 | ||
2737 | /* There is no branch delay slot on MIPS16. */ | |
2738 | if (pc_is_mips16 (pc)) | |
2739 | return 0; | |
2740 | ||
2741 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
2742 | /* If error reading memory, guess that it is not a delayed branch. */ | |
2743 | return 0; | |
c5aa993b | 2744 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
2745 | } |
2746 | ||
2747 | ||
2748 | /* Skip the PC past function prologue instructions (32-bit version). | |
2749 | This is a helper function for mips_skip_prologue. */ | |
2750 | ||
2751 | static CORE_ADDR | |
2752 | mips32_skip_prologue (pc, lenient) | |
c5aa993b | 2753 | CORE_ADDR pc; /* starting PC to search from */ |
c906108c SS |
2754 | int lenient; |
2755 | { | |
c5aa993b JM |
2756 | t_inst inst; |
2757 | CORE_ADDR end_pc; | |
2758 | int seen_sp_adjust = 0; | |
2759 | int load_immediate_bytes = 0; | |
2760 | ||
2761 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2762 | instruction and the instructions that save registers on the stack | |
2763 | or in the gcc frame. */ | |
2764 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
2765 | { | |
2766 | unsigned long high_word; | |
c906108c | 2767 | |
c5aa993b JM |
2768 | inst = mips_fetch_instruction (pc); |
2769 | high_word = (inst >> 16) & 0xffff; | |
c906108c SS |
2770 | |
2771 | #if 0 | |
c5aa993b JM |
2772 | if (lenient && is_delayed (inst)) |
2773 | continue; | |
c906108c SS |
2774 | #endif |
2775 | ||
c5aa993b JM |
2776 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
2777 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
2778 | seen_sp_adjust = 1; | |
2779 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
2780 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
2781 | seen_sp_adjust = 1; | |
2782 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
2783 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
2784 | && (inst & 0x001F0000)) /* reg != $zero */ | |
2785 | continue; | |
2786 | ||
2787 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
2788 | continue; | |
2789 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
2790 | /* sx reg,n($s8) */ | |
2791 | continue; /* reg != $zero */ | |
2792 | ||
2793 | /* move $s8,$sp. With different versions of gas this will be either | |
2794 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
2795 | Accept any one of these. */ | |
2796 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2797 | continue; | |
2798 | ||
2799 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
2800 | continue; | |
2801 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
2802 | continue; | |
2803 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
2804 | continue; | |
2805 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2806 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
2807 | continue; | |
2808 | /* The following instructions load $at or $t0 with an immediate | |
2809 | value in preparation for a stack adjustment via | |
2810 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
2811 | a local variable, so we accept them only before a stack adjustment | |
2812 | instruction was seen. */ | |
2813 | else if (!seen_sp_adjust) | |
2814 | { | |
2815 | if (high_word == 0x3c01 || /* lui $at,n */ | |
2816 | high_word == 0x3c08) /* lui $t0,n */ | |
2817 | { | |
2818 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
2819 | continue; | |
2820 | } | |
2821 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
2822 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
2823 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
2824 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
2825 | { | |
2826 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
2827 | continue; | |
2828 | } | |
2829 | else | |
2830 | break; | |
2831 | } | |
2832 | else | |
2833 | break; | |
c906108c SS |
2834 | } |
2835 | ||
c5aa993b JM |
2836 | /* In a frameless function, we might have incorrectly |
2837 | skipped some load immediate instructions. Undo the skipping | |
2838 | if the load immediate was not followed by a stack adjustment. */ | |
2839 | if (load_immediate_bytes && !seen_sp_adjust) | |
2840 | pc -= load_immediate_bytes; | |
2841 | return pc; | |
c906108c SS |
2842 | } |
2843 | ||
2844 | /* Skip the PC past function prologue instructions (16-bit version). | |
2845 | This is a helper function for mips_skip_prologue. */ | |
2846 | ||
2847 | static CORE_ADDR | |
2848 | mips16_skip_prologue (pc, lenient) | |
c5aa993b | 2849 | CORE_ADDR pc; /* starting PC to search from */ |
c906108c SS |
2850 | int lenient; |
2851 | { | |
c5aa993b JM |
2852 | CORE_ADDR end_pc; |
2853 | int extend_bytes = 0; | |
2854 | int prev_extend_bytes; | |
c906108c | 2855 | |
c5aa993b JM |
2856 | /* Table of instructions likely to be found in a function prologue. */ |
2857 | static struct | |
c906108c SS |
2858 | { |
2859 | unsigned short inst; | |
2860 | unsigned short mask; | |
c5aa993b JM |
2861 | } |
2862 | table[] = | |
2863 | { | |
c906108c | 2864 | { |
c5aa993b JM |
2865 | 0x6300, 0xff00 |
2866 | } | |
2867 | , /* addiu $sp,offset */ | |
2868 | { | |
2869 | 0xfb00, 0xff00 | |
2870 | } | |
2871 | , /* daddiu $sp,offset */ | |
2872 | { | |
2873 | 0xd000, 0xf800 | |
2874 | } | |
2875 | , /* sw reg,n($sp) */ | |
2876 | { | |
2877 | 0xf900, 0xff00 | |
2878 | } | |
2879 | , /* sd reg,n($sp) */ | |
2880 | { | |
2881 | 0x6200, 0xff00 | |
2882 | } | |
2883 | , /* sw $ra,n($sp) */ | |
2884 | { | |
2885 | 0xfa00, 0xff00 | |
2886 | } | |
2887 | , /* sd $ra,n($sp) */ | |
2888 | { | |
2889 | 0x673d, 0xffff | |
2890 | } | |
2891 | , /* move $s1,sp */ | |
2892 | { | |
2893 | 0xd980, 0xff80 | |
2894 | } | |
2895 | , /* sw $a0-$a3,n($s1) */ | |
2896 | { | |
2897 | 0x6704, 0xff1c | |
2898 | } | |
2899 | , /* move reg,$a0-$a3 */ | |
2900 | { | |
2901 | 0xe809, 0xf81f | |
2902 | } | |
2903 | , /* entry pseudo-op */ | |
2904 | { | |
2905 | 0x0100, 0xff00 | |
2906 | } | |
2907 | , /* addiu $s1,$sp,n */ | |
2908 | { | |
2909 | 0, 0 | |
2910 | } /* end of table marker */ | |
2911 | }; | |
2912 | ||
2913 | /* Skip the typical prologue instructions. These are the stack adjustment | |
2914 | instruction and the instructions that save registers on the stack | |
2915 | or in the gcc frame. */ | |
2916 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
2917 | { | |
2918 | unsigned short inst; | |
2919 | int i; | |
c906108c | 2920 | |
c5aa993b | 2921 | inst = mips_fetch_instruction (pc); |
c906108c | 2922 | |
c5aa993b JM |
2923 | /* Normally we ignore an extend instruction. However, if it is |
2924 | not followed by a valid prologue instruction, we must adjust | |
2925 | the pc back over the extend so that it won't be considered | |
2926 | part of the prologue. */ | |
2927 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2928 | { | |
2929 | extend_bytes = MIPS16_INSTLEN; | |
2930 | continue; | |
2931 | } | |
2932 | prev_extend_bytes = extend_bytes; | |
2933 | extend_bytes = 0; | |
c906108c | 2934 | |
c5aa993b JM |
2935 | /* Check for other valid prologue instructions besides extend. */ |
2936 | for (i = 0; table[i].mask != 0; i++) | |
2937 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
2938 | break; | |
2939 | if (table[i].mask != 0) /* it was in table? */ | |
2940 | continue; /* ignore it */ | |
2941 | else | |
2942 | /* non-prologue */ | |
2943 | { | |
2944 | /* Return the current pc, adjusted backwards by 2 if | |
2945 | the previous instruction was an extend. */ | |
2946 | return pc - prev_extend_bytes; | |
2947 | } | |
c906108c SS |
2948 | } |
2949 | return pc; | |
2950 | } | |
2951 | ||
2952 | /* To skip prologues, I use this predicate. Returns either PC itself | |
2953 | if the code at PC does not look like a function prologue; otherwise | |
2954 | returns an address that (if we're lucky) follows the prologue. If | |
2955 | LENIENT, then we must skip everything which is involved in setting | |
2956 | up the frame (it's OK to skip more, just so long as we don't skip | |
2957 | anything which might clobber the registers which are being saved. | |
2958 | We must skip more in the case where part of the prologue is in the | |
2959 | delay slot of a non-prologue instruction). */ | |
2960 | ||
2961 | CORE_ADDR | |
2962 | mips_skip_prologue (pc, lenient) | |
2963 | CORE_ADDR pc; | |
2964 | int lenient; | |
2965 | { | |
2966 | /* See if we can determine the end of the prologue via the symbol table. | |
2967 | If so, then return either PC, or the PC after the prologue, whichever | |
2968 | is greater. */ | |
2969 | ||
2970 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
2971 | ||
2972 | if (post_prologue_pc != 0) | |
2973 | return max (pc, post_prologue_pc); | |
2974 | ||
2975 | /* Can't determine prologue from the symbol table, need to examine | |
2976 | instructions. */ | |
2977 | ||
2978 | if (pc_is_mips16 (pc)) | |
2979 | return mips16_skip_prologue (pc, lenient); | |
2980 | else | |
2981 | return mips32_skip_prologue (pc, lenient); | |
2982 | } | |
2983 | ||
2984 | #if 0 | |
2985 | /* The lenient prologue stuff should be superseded by the code in | |
2986 | init_extra_frame_info which looks to see whether the stores mentioned | |
2987 | in the proc_desc have actually taken place. */ | |
2988 | ||
2989 | /* Is address PC in the prologue (loosely defined) for function at | |
2990 | STARTADDR? */ | |
2991 | ||
2992 | static int | |
2993 | mips_in_lenient_prologue (startaddr, pc) | |
2994 | CORE_ADDR startaddr; | |
2995 | CORE_ADDR pc; | |
2996 | { | |
2997 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); | |
2998 | return pc >= startaddr && pc < end_prologue; | |
2999 | } | |
3000 | #endif | |
3001 | ||
7a292a7a SS |
3002 | /* Determine how a return value is stored within the MIPS register |
3003 | file, given the return type `valtype'. */ | |
3004 | ||
3005 | struct return_value_word | |
3006 | { | |
3007 | int len; | |
3008 | int reg; | |
3009 | int reg_offset; | |
3010 | int buf_offset; | |
3011 | }; | |
3012 | ||
a14ed312 KB |
3013 | static void return_value_location (struct type *, struct return_value_word *, |
3014 | struct return_value_word *); | |
7a292a7a SS |
3015 | |
3016 | static void | |
3017 | return_value_location (valtype, hi, lo) | |
3018 | struct type *valtype; | |
3019 | struct return_value_word *hi; | |
3020 | struct return_value_word *lo; | |
3021 | { | |
3022 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3023 | |
7a292a7a SS |
3024 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
3025 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3026 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3027 | { | |
3028 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3029 | { | |
3030 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 3031 | spread them across a floating-point register pair. */ |
7a292a7a SS |
3032 | lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; |
3033 | hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4; | |
3034 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN | |
3035 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) | |
3036 | ? 4 : 0); | |
3037 | hi->reg_offset = lo->reg_offset; | |
3038 | lo->reg = FP0_REGNUM + 0; | |
3039 | hi->reg = FP0_REGNUM + 1; | |
3040 | lo->len = 4; | |
3041 | hi->len = 4; | |
3042 | } | |
3043 | else | |
3044 | { | |
3045 | /* The floating point value fits in a single floating-point | |
c5aa993b | 3046 | register. */ |
7a292a7a SS |
3047 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN |
3048 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 | |
3049 | && len == 4) | |
3050 | ? 4 : 0); | |
3051 | lo->reg = FP0_REGNUM; | |
3052 | lo->len = len; | |
3053 | lo->buf_offset = 0; | |
3054 | hi->len = 0; | |
3055 | hi->reg_offset = 0; | |
3056 | hi->buf_offset = 0; | |
3057 | hi->reg = 0; | |
3058 | } | |
3059 | } | |
3060 | else | |
3061 | { | |
3062 | /* Locate a result possibly spread across two registers. */ | |
3063 | int regnum = 2; | |
3064 | lo->reg = regnum + 0; | |
3065 | hi->reg = regnum + 1; | |
3066 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3067 | && len < MIPS_SAVED_REGSIZE) | |
3068 | { | |
3069 | /* "un-left-justify" the value in the low register */ | |
3070 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
3071 | lo->len = len; | |
3072 | hi->reg_offset = 0; | |
3073 | hi->len = 0; | |
3074 | } | |
3075 | else if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3076 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ | |
3077 | && len < MIPS_SAVED_REGSIZE * 2 | |
3078 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3079 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3080 | { | |
3081 | /* "un-left-justify" the value spread across two registers. */ | |
3082 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
3083 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
3084 | hi->reg_offset = 0; | |
3085 | hi->len = len - lo->len; | |
3086 | } | |
3087 | else | |
3088 | { | |
3089 | /* Only perform a partial copy of the second register. */ | |
3090 | lo->reg_offset = 0; | |
3091 | hi->reg_offset = 0; | |
3092 | if (len > MIPS_SAVED_REGSIZE) | |
3093 | { | |
3094 | lo->len = MIPS_SAVED_REGSIZE; | |
3095 | hi->len = len - MIPS_SAVED_REGSIZE; | |
3096 | } | |
3097 | else | |
3098 | { | |
3099 | lo->len = len; | |
3100 | hi->len = 0; | |
3101 | } | |
3102 | } | |
3103 | if (TARGET_BYTE_ORDER == BIG_ENDIAN | |
3104 | && REGISTER_RAW_SIZE (regnum) == 8 | |
3105 | && MIPS_SAVED_REGSIZE == 4) | |
3106 | { | |
3107 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 3108 | of the register is being used */ |
7a292a7a SS |
3109 | lo->reg_offset += 4; |
3110 | hi->reg_offset += 4; | |
3111 | } | |
3112 | lo->buf_offset = 0; | |
3113 | hi->buf_offset = lo->len; | |
3114 | } | |
3115 | } | |
3116 | ||
3117 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
3118 | copy its value into `valbuf'. */ | |
3119 | ||
c906108c SS |
3120 | void |
3121 | mips_extract_return_value (valtype, regbuf, valbuf) | |
c5aa993b JM |
3122 | struct type *valtype; |
3123 | char regbuf[REGISTER_BYTES]; | |
3124 | char *valbuf; | |
c906108c | 3125 | { |
7a292a7a SS |
3126 | struct return_value_word lo; |
3127 | struct return_value_word hi; | |
3128 | return_value_location (valtype, &lo, &hi); | |
3129 | ||
3130 | memcpy (valbuf + lo.buf_offset, | |
3131 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
3132 | lo.len); | |
3133 | ||
3134 | if (hi.len > 0) | |
3135 | memcpy (valbuf + hi.buf_offset, | |
3136 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
3137 | hi.len); | |
3138 | ||
3139 | #if 0 | |
c906108c SS |
3140 | int regnum; |
3141 | int offset = 0; | |
3142 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 3143 | |
c906108c SS |
3144 | regnum = 2; |
3145 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3146 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE | |
3147 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE | |
3148 | && len <= MIPS_FPU_SINGLE_REGSIZE))) | |
3149 | regnum = FP0_REGNUM; | |
3150 | ||
3151 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b | 3152 | { /* "un-left-justify" the value from the register */ |
c906108c SS |
3153 | if (len < REGISTER_RAW_SIZE (regnum)) |
3154 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
c5aa993b | 3155 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ |
c906108c SS |
3156 | len < REGISTER_RAW_SIZE (regnum) * 2 && |
3157 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3158 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3159 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
3160 | } | |
3161 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); | |
3162 | REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf); | |
7a292a7a | 3163 | #endif |
c906108c SS |
3164 | } |
3165 | ||
7a292a7a SS |
3166 | /* Given a return value in `valbuf' with a type `valtype', write it's |
3167 | value into the appropriate register. */ | |
3168 | ||
c906108c SS |
3169 | void |
3170 | mips_store_return_value (valtype, valbuf) | |
c5aa993b JM |
3171 | struct type *valtype; |
3172 | char *valbuf; | |
c906108c | 3173 | { |
7a292a7a SS |
3174 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
3175 | struct return_value_word lo; | |
3176 | struct return_value_word hi; | |
3177 | return_value_location (valtype, &lo, &hi); | |
3178 | ||
3179 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3180 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3181 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
3182 | raw_buffer, | |
3183 | REGISTER_RAW_SIZE (lo.reg)); | |
c5aa993b | 3184 | |
7a292a7a SS |
3185 | if (hi.len > 0) |
3186 | { | |
3187 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3188 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3189 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
3190 | raw_buffer, | |
3191 | REGISTER_RAW_SIZE (hi.reg)); | |
3192 | } | |
3193 | ||
3194 | #if 0 | |
c906108c SS |
3195 | int regnum; |
3196 | int offset = 0; | |
3197 | int len = TYPE_LENGTH (valtype); | |
3198 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
c5aa993b | 3199 | |
c906108c SS |
3200 | regnum = 2; |
3201 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3202 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE | |
3203 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE | |
3204 | && len <= MIPS_REGSIZE))) | |
3205 | regnum = FP0_REGNUM; | |
3206 | ||
3207 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b | 3208 | { /* "left-justify" the value in the register */ |
c906108c SS |
3209 | if (len < REGISTER_RAW_SIZE (regnum)) |
3210 | offset = REGISTER_RAW_SIZE (regnum) - len; | |
c5aa993b | 3211 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ |
c906108c SS |
3212 | len < REGISTER_RAW_SIZE (regnum) * 2 && |
3213 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
3214 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3215 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; | |
3216 | } | |
c5aa993b JM |
3217 | memcpy (raw_buffer + offset, valbuf, len); |
3218 | REGISTER_CONVERT_FROM_TYPE (regnum, valtype, raw_buffer); | |
3219 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, | |
3220 | len > REGISTER_RAW_SIZE (regnum) ? | |
3221 | len : REGISTER_RAW_SIZE (regnum)); | |
7a292a7a | 3222 | #endif |
c906108c SS |
3223 | } |
3224 | ||
3225 | /* Exported procedure: Is PC in the signal trampoline code */ | |
3226 | ||
3227 | int | |
3228 | in_sigtramp (pc, ignore) | |
3229 | CORE_ADDR pc; | |
3230 | char *ignore; /* function name */ | |
3231 | { | |
3232 | if (sigtramp_address == 0) | |
3233 | fixup_sigtramp (); | |
3234 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
3235 | } | |
3236 | ||
a5ea2558 AC |
3237 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
3238 | used for all MIPS-specific commands. */ | |
3239 | ||
a14ed312 | 3240 | static void show_mips_command (char *, int); |
a5ea2558 AC |
3241 | static void |
3242 | show_mips_command (args, from_tty) | |
3243 | char *args; | |
3244 | int from_tty; | |
3245 | { | |
3246 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
3247 | } | |
3248 | ||
a14ed312 | 3249 | static void set_mips_command (char *, int); |
a5ea2558 AC |
3250 | static void |
3251 | set_mips_command (args, from_tty) | |
3252 | char *args; | |
3253 | int from_tty; | |
3254 | { | |
3255 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
3256 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
3257 | } | |
3258 | ||
c906108c SS |
3259 | /* Commands to show/set the MIPS FPU type. */ |
3260 | ||
a14ed312 | 3261 | static void show_mipsfpu_command (char *, int); |
c906108c SS |
3262 | static void |
3263 | show_mipsfpu_command (args, from_tty) | |
3264 | char *args; | |
3265 | int from_tty; | |
3266 | { | |
3267 | char *msg; | |
3268 | char *fpu; | |
3269 | switch (MIPS_FPU_TYPE) | |
3270 | { | |
3271 | case MIPS_FPU_SINGLE: | |
3272 | fpu = "single-precision"; | |
3273 | break; | |
3274 | case MIPS_FPU_DOUBLE: | |
3275 | fpu = "double-precision"; | |
3276 | break; | |
3277 | case MIPS_FPU_NONE: | |
3278 | fpu = "absent (none)"; | |
3279 | break; | |
3280 | } | |
3281 | if (mips_fpu_type_auto) | |
3282 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
3283 | fpu); | |
3284 | else | |
3285 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
3286 | fpu); | |
3287 | } | |
3288 | ||
3289 | ||
a14ed312 | 3290 | static void set_mipsfpu_command (char *, int); |
c906108c SS |
3291 | static void |
3292 | set_mipsfpu_command (args, from_tty) | |
3293 | char *args; | |
3294 | int from_tty; | |
3295 | { | |
3296 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
3297 | show_mipsfpu_command (args, from_tty); | |
3298 | } | |
3299 | ||
a14ed312 | 3300 | static void set_mipsfpu_single_command (char *, int); |
c906108c SS |
3301 | static void |
3302 | set_mipsfpu_single_command (args, from_tty) | |
3303 | char *args; | |
3304 | int from_tty; | |
3305 | { | |
3306 | mips_fpu_type = MIPS_FPU_SINGLE; | |
3307 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3308 | if (GDB_MULTI_ARCH) |
3309 | { | |
3310 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; | |
3311 | } | |
c906108c SS |
3312 | } |
3313 | ||
a14ed312 | 3314 | static void set_mipsfpu_double_command (char *, int); |
c906108c SS |
3315 | static void |
3316 | set_mipsfpu_double_command (args, from_tty) | |
3317 | char *args; | |
3318 | int from_tty; | |
3319 | { | |
3320 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
3321 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3322 | if (GDB_MULTI_ARCH) |
3323 | { | |
3324 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; | |
3325 | } | |
c906108c SS |
3326 | } |
3327 | ||
a14ed312 | 3328 | static void set_mipsfpu_none_command (char *, int); |
c906108c SS |
3329 | static void |
3330 | set_mipsfpu_none_command (args, from_tty) | |
3331 | char *args; | |
3332 | int from_tty; | |
3333 | { | |
3334 | mips_fpu_type = MIPS_FPU_NONE; | |
3335 | mips_fpu_type_auto = 0; | |
c2d11a7d JM |
3336 | if (GDB_MULTI_ARCH) |
3337 | { | |
3338 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; | |
3339 | } | |
c906108c SS |
3340 | } |
3341 | ||
a14ed312 | 3342 | static void set_mipsfpu_auto_command (char *, int); |
c906108c SS |
3343 | static void |
3344 | set_mipsfpu_auto_command (args, from_tty) | |
3345 | char *args; | |
3346 | int from_tty; | |
3347 | { | |
3348 | mips_fpu_type_auto = 1; | |
3349 | } | |
3350 | ||
3351 | /* Command to set the processor type. */ | |
3352 | ||
3353 | void | |
3354 | mips_set_processor_type_command (args, from_tty) | |
3355 | char *args; | |
3356 | int from_tty; | |
3357 | { | |
3358 | int i; | |
3359 | ||
3360 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
3361 | { | |
3362 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
3363 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3364 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
3365 | ||
3366 | /* Restore the value. */ | |
3367 | tmp_mips_processor_type = strsave (mips_processor_type); | |
3368 | ||
3369 | return; | |
3370 | } | |
c5aa993b | 3371 | |
c906108c SS |
3372 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
3373 | { | |
3374 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
3375 | /* Restore its value. */ | |
3376 | tmp_mips_processor_type = strsave (mips_processor_type); | |
3377 | } | |
3378 | } | |
3379 | ||
3380 | static void | |
3381 | mips_show_processor_type_command (args, from_tty) | |
3382 | char *args; | |
3383 | int from_tty; | |
3384 | { | |
3385 | } | |
3386 | ||
3387 | /* Modify the actual processor type. */ | |
3388 | ||
3389 | int | |
3390 | mips_set_processor_type (str) | |
3391 | char *str; | |
3392 | { | |
3393 | int i, j; | |
3394 | ||
3395 | if (str == NULL) | |
3396 | return 0; | |
3397 | ||
3398 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
3399 | { | |
3400 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
3401 | { | |
3402 | mips_processor_type = str; | |
cce74817 | 3403 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 3404 | return 1; |
c906108c SS |
3405 | /* FIXME tweak fpu flag too */ |
3406 | } | |
3407 | } | |
3408 | ||
3409 | return 0; | |
3410 | } | |
3411 | ||
3412 | /* Attempt to identify the particular processor model by reading the | |
3413 | processor id. */ | |
3414 | ||
3415 | char * | |
3416 | mips_read_processor_type () | |
3417 | { | |
3418 | CORE_ADDR prid; | |
3419 | ||
3420 | prid = read_register (PRID_REGNUM); | |
3421 | ||
3422 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 3423 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
3424 | |
3425 | return NULL; | |
3426 | } | |
3427 | ||
3428 | /* Just like reinit_frame_cache, but with the right arguments to be | |
3429 | callable as an sfunc. */ | |
3430 | ||
3431 | static void | |
3432 | reinit_frame_cache_sfunc (args, from_tty, c) | |
3433 | char *args; | |
3434 | int from_tty; | |
3435 | struct cmd_list_element *c; | |
3436 | { | |
3437 | reinit_frame_cache (); | |
3438 | } | |
3439 | ||
3440 | int | |
3441 | gdb_print_insn_mips (memaddr, info) | |
3442 | bfd_vma memaddr; | |
3443 | disassemble_info *info; | |
3444 | { | |
3445 | mips_extra_func_info_t proc_desc; | |
3446 | ||
3447 | /* Search for the function containing this address. Set the low bit | |
3448 | of the address when searching, in case we were given an even address | |
3449 | that is the start of a 16-bit function. If we didn't do this, | |
3450 | the search would fail because the symbol table says the function | |
3451 | starts at an odd address, i.e. 1 byte past the given address. */ | |
3452 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
3453 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
3454 | ||
3455 | /* Make an attempt to determine if this is a 16-bit function. If | |
3456 | the procedure descriptor exists and the address therein is odd, | |
3457 | it's definitely a 16-bit function. Otherwise, we have to just | |
3458 | guess that if the address passed in is odd, it's 16-bits. */ | |
3459 | if (proc_desc) | |
3460 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH; | |
3461 | else | |
3462 | info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH; | |
3463 | ||
3464 | /* Round down the instruction address to the appropriate boundary. */ | |
3465 | memaddr &= (info->mach == 16 ? ~1 : ~3); | |
c5aa993b | 3466 | |
c906108c SS |
3467 | /* Call the appropriate disassembler based on the target endian-ness. */ |
3468 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3469 | return print_insn_big_mips (memaddr, info); | |
3470 | else | |
3471 | return print_insn_little_mips (memaddr, info); | |
3472 | } | |
3473 | ||
3474 | /* Old-style breakpoint macros. | |
3475 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
3476 | confused when it sees the usual MIPS breakpoint instruction. */ | |
3477 | ||
3478 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
3479 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
3480 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
3481 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
3482 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
3483 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
3484 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
3485 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
3486 | ||
3487 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
3488 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
3489 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
3490 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
3491 | (if necessary) to point to the actual memory location where the | |
3492 | breakpoint should be inserted. */ | |
3493 | ||
c5aa993b JM |
3494 | unsigned char * |
3495 | mips_breakpoint_from_pc (pcptr, lenptr) | |
c906108c SS |
3496 | CORE_ADDR *pcptr; |
3497 | int *lenptr; | |
3498 | { | |
3499 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
3500 | { | |
3501 | if (pc_is_mips16 (*pcptr)) | |
3502 | { | |
3503 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; | |
3504 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); | |
c5aa993b | 3505 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
3506 | return mips16_big_breakpoint; |
3507 | } | |
3508 | else | |
3509 | { | |
3510 | static char big_breakpoint[] = BIG_BREAKPOINT; | |
3511 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
3512 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
3513 | ||
c5aa993b | 3514 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
3515 | |
3516 | if (strcmp (target_shortname, "mips") == 0) | |
3517 | return idt_big_breakpoint; | |
3518 | else if (strcmp (target_shortname, "ddb") == 0 | |
3519 | || strcmp (target_shortname, "pmon") == 0 | |
3520 | || strcmp (target_shortname, "lsi") == 0) | |
3521 | return pmon_big_breakpoint; | |
3522 | else | |
3523 | return big_breakpoint; | |
3524 | } | |
3525 | } | |
3526 | else | |
3527 | { | |
3528 | if (pc_is_mips16 (*pcptr)) | |
3529 | { | |
3530 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; | |
3531 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); | |
c5aa993b | 3532 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
3533 | return mips16_little_breakpoint; |
3534 | } | |
3535 | else | |
3536 | { | |
3537 | static char little_breakpoint[] = LITTLE_BREAKPOINT; | |
3538 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; | |
3539 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; | |
3540 | ||
c5aa993b | 3541 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
3542 | |
3543 | if (strcmp (target_shortname, "mips") == 0) | |
3544 | return idt_little_breakpoint; | |
3545 | else if (strcmp (target_shortname, "ddb") == 0 | |
3546 | || strcmp (target_shortname, "pmon") == 0 | |
3547 | || strcmp (target_shortname, "lsi") == 0) | |
3548 | return pmon_little_breakpoint; | |
3549 | else | |
3550 | return little_breakpoint; | |
3551 | } | |
3552 | } | |
3553 | } | |
3554 | ||
3555 | /* If PC is in a mips16 call or return stub, return the address of the target | |
3556 | PC, which is either the callee or the caller. There are several | |
3557 | cases which must be handled: | |
3558 | ||
3559 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 3560 | target PC is in $31 ($ra). |
c906108c | 3561 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 3562 | and the target PC is in $2. |
c906108c | 3563 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
3564 | before the jal instruction, this is effectively a call stub |
3565 | and the the target PC is in $2. Otherwise this is effectively | |
3566 | a return stub and the target PC is in $18. | |
c906108c SS |
3567 | |
3568 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
3569 | gory details. | |
3570 | ||
3571 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 3572 | */ |
c906108c SS |
3573 | |
3574 | CORE_ADDR | |
3575 | mips_skip_stub (pc) | |
3576 | CORE_ADDR pc; | |
3577 | { | |
3578 | char *name; | |
3579 | CORE_ADDR start_addr; | |
3580 | ||
3581 | /* Find the starting address and name of the function containing the PC. */ | |
3582 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
3583 | return 0; | |
3584 | ||
3585 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
3586 | target PC is in $31 ($ra). */ | |
3587 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3588 | || strcmp (name, "__mips16_ret_df") == 0) | |
3589 | return read_register (RA_REGNUM); | |
3590 | ||
3591 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3592 | { | |
3593 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
3594 | and the target PC is in $2. */ | |
3595 | if (name[19] >= '0' && name[19] <= '9') | |
3596 | return read_register (2); | |
3597 | ||
3598 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
3599 | before the jal instruction, this is effectively a call stub |
3600 | and the the target PC is in $2. Otherwise this is effectively | |
3601 | a return stub and the target PC is in $18. */ | |
c906108c SS |
3602 | else if (name[19] == 's' || name[19] == 'd') |
3603 | { | |
3604 | if (pc == start_addr) | |
3605 | { | |
3606 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
3607 | stub. Such a stub for a function bar might have a name |
3608 | like __fn_stub_bar, and might look like this: | |
3609 | mfc1 $4,$f13 | |
3610 | mfc1 $5,$f12 | |
3611 | mfc1 $6,$f15 | |
3612 | mfc1 $7,$f14 | |
3613 | la $1,bar (becomes a lui/addiu pair) | |
3614 | jr $1 | |
3615 | So scan down to the lui/addi and extract the target | |
3616 | address from those two instructions. */ | |
c906108c SS |
3617 | |
3618 | CORE_ADDR target_pc = read_register (2); | |
3619 | t_inst inst; | |
3620 | int i; | |
3621 | ||
3622 | /* See if the name of the target function is __fn_stub_*. */ | |
3623 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
3624 | return target_pc; | |
3625 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
3626 | && strcmp (name, "etext") != 0 | |
3627 | && strcmp (name, "_etext") != 0) | |
3628 | return target_pc; | |
3629 | ||
3630 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
3631 | The limit on the search is arbitrarily set to 20 |
3632 | instructions. FIXME. */ | |
c906108c SS |
3633 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
3634 | { | |
c5aa993b JM |
3635 | inst = mips_fetch_instruction (target_pc); |
3636 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
3637 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
3638 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
3639 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
3640 | } |
3641 | ||
3642 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
3643 | return target_pc; | |
3644 | } | |
3645 | else | |
3646 | /* This is the 'return' part of a call stub. The return | |
3647 | address is in $r18. */ | |
3648 | return read_register (18); | |
3649 | } | |
3650 | } | |
c5aa993b | 3651 | return 0; /* not a stub */ |
c906108c SS |
3652 | } |
3653 | ||
3654 | ||
3655 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
3656 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
3657 | ||
3658 | int | |
3659 | mips_in_call_stub (pc, name) | |
3660 | CORE_ADDR pc; | |
3661 | char *name; | |
3662 | { | |
3663 | CORE_ADDR start_addr; | |
3664 | ||
3665 | /* Find the starting address of the function containing the PC. If the | |
3666 | caller didn't give us a name, look it up at the same time. */ | |
3667 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
3668 | return 0; | |
3669 | ||
3670 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
3671 | { | |
3672 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
3673 | if (name[19] >= '0' && name[19] <= '9') | |
3674 | return 1; | |
3675 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 3676 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
3677 | else if (name[19] == 's' || name[19] == 'd') |
3678 | return pc == start_addr; | |
3679 | } | |
3680 | ||
c5aa993b | 3681 | return 0; /* not a stub */ |
c906108c SS |
3682 | } |
3683 | ||
3684 | ||
3685 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
3686 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
3687 | ||
3688 | int | |
3689 | mips_in_return_stub (pc, name) | |
3690 | CORE_ADDR pc; | |
3691 | char *name; | |
3692 | { | |
3693 | CORE_ADDR start_addr; | |
3694 | ||
3695 | /* Find the starting address of the function containing the PC. */ | |
3696 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
3697 | return 0; | |
3698 | ||
3699 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
3700 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
3701 | || strcmp (name, "__mips16_ret_df") == 0) | |
3702 | return 1; | |
3703 | ||
3704 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 3705 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
3706 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
3707 | && (name[19] == 's' || name[19] == 'd') | |
3708 | && pc != start_addr) | |
3709 | return 1; | |
3710 | ||
c5aa993b | 3711 | return 0; /* not a stub */ |
c906108c SS |
3712 | } |
3713 | ||
3714 | ||
3715 | /* Return non-zero if the PC is in a library helper function that should | |
3716 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
3717 | ||
3718 | int | |
3719 | mips_ignore_helper (pc) | |
3720 | CORE_ADDR pc; | |
3721 | { | |
3722 | char *name; | |
3723 | ||
3724 | /* Find the starting address and name of the function containing the PC. */ | |
3725 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
3726 | return 0; | |
3727 | ||
3728 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
3729 | that we want to ignore. */ | |
3730 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
3731 | || strcmp (name, "__mips16_ret_df") == 0); | |
3732 | } | |
3733 | ||
3734 | ||
3735 | /* Return a location where we can set a breakpoint that will be hit | |
3736 | when an inferior function call returns. This is normally the | |
3737 | program's entry point. Executables that don't have an entry | |
3738 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
3739 | whose address is the location where the breakpoint should be placed. */ | |
3740 | ||
3741 | CORE_ADDR | |
3742 | mips_call_dummy_address () | |
3743 | { | |
3744 | struct minimal_symbol *sym; | |
3745 | ||
3746 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
3747 | if (sym) | |
3748 | return SYMBOL_VALUE_ADDRESS (sym); | |
3749 | else | |
3750 | return entry_point_address (); | |
3751 | } | |
3752 | ||
3753 | ||
b9a8e3bf JB |
3754 | /* If the current gcc for for this target does not produce correct debugging |
3755 | information for float parameters, both prototyped and unprototyped, then | |
3756 | define this macro. This forces gdb to always assume that floats are | |
3757 | passed as doubles and then converted in the callee. | |
3758 | ||
3759 | For the mips chip, it appears that the debug info marks the parameters as | |
3760 | floats regardless of whether the function is prototyped, but the actual | |
3761 | values are passed as doubles for the non-prototyped case and floats for | |
3762 | the prototyped case. Thus we choose to make the non-prototyped case work | |
3763 | for C and break the prototyped case, since the non-prototyped case is | |
3764 | probably much more common. (FIXME). */ | |
3765 | ||
3766 | static int | |
3767 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
3768 | { | |
3769 | return current_language->la_language == language_c; | |
3770 | } | |
3771 | ||
47a8d4ba AC |
3772 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
3773 | the register stored on the stack (32) is different to its real raw | |
3774 | size (64). The below ensures that registers are fetched from the | |
3775 | stack using their ABI size and then stored into the RAW_BUFFER | |
3776 | using their raw size. | |
3777 | ||
3778 | The alternative to adding this function would be to add an ABI | |
3779 | macro - REGISTER_STACK_SIZE(). */ | |
3780 | ||
3781 | static void | |
3782 | mips_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) | |
3783 | char *raw_buffer; | |
3784 | int *optimized; | |
3785 | CORE_ADDR *addrp; | |
3786 | struct frame_info *frame; | |
3787 | int regnum; | |
3788 | enum lval_type *lval; | |
3789 | { | |
3790 | CORE_ADDR addr; | |
3791 | ||
3792 | if (!target_has_registers) | |
3793 | error ("No registers."); | |
3794 | ||
3795 | /* Normal systems don't optimize out things with register numbers. */ | |
3796 | if (optimized != NULL) | |
3797 | *optimized = 0; | |
3798 | addr = find_saved_register (frame, regnum); | |
3799 | if (addr != 0) | |
3800 | { | |
3801 | if (lval != NULL) | |
3802 | *lval = lval_memory; | |
3803 | if (regnum == SP_REGNUM) | |
3804 | { | |
3805 | if (raw_buffer != NULL) | |
3806 | { | |
3807 | /* Put it back in target format. */ | |
3808 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
3809 | (LONGEST) addr); | |
3810 | } | |
3811 | if (addrp != NULL) | |
3812 | *addrp = 0; | |
3813 | return; | |
3814 | } | |
3815 | if (raw_buffer != NULL) | |
3816 | { | |
3817 | LONGEST val; | |
3818 | if (regnum < 32) | |
3819 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
3820 | saved. */ | |
3821 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
3822 | else | |
3823 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
3824 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
3825 | } | |
3826 | } | |
3827 | else | |
3828 | { | |
3829 | if (lval != NULL) | |
3830 | *lval = lval_register; | |
3831 | addr = REGISTER_BYTE (regnum); | |
3832 | if (raw_buffer != NULL) | |
3833 | read_register_gen (regnum, raw_buffer); | |
3834 | } | |
3835 | if (addrp != NULL) | |
3836 | *addrp = addr; | |
3837 | } | |
2acceee2 | 3838 | |
c2d11a7d JM |
3839 | static gdbarch_init_ftype mips_gdbarch_init; |
3840 | static struct gdbarch * | |
3841 | mips_gdbarch_init (info, arches) | |
3842 | struct gdbarch_info info; | |
3843 | struct gdbarch_list *arches; | |
3844 | { | |
3845 | static LONGEST mips_call_dummy_words[] = | |
3846 | {0}; | |
3847 | struct gdbarch *gdbarch; | |
3848 | struct gdbarch_tdep *tdep; | |
3849 | int elf_flags; | |
c2d11a7d JM |
3850 | int ef_mips_bitptrs; |
3851 | int ef_mips_arch; | |
0dadbba0 | 3852 | enum mips_abi mips_abi; |
c2d11a7d JM |
3853 | |
3854 | /* Extract the elf_flags if available */ | |
3855 | if (info.abfd != NULL | |
3856 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3857 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
3858 | else | |
3859 | elf_flags = 0; | |
3860 | ||
0dadbba0 AC |
3861 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
3862 | switch ((elf_flags & EF_MIPS_ABI)) | |
3863 | { | |
3864 | case E_MIPS_ABI_O32: | |
3865 | mips_abi = MIPS_ABI_O32; | |
3866 | break; | |
3867 | case E_MIPS_ABI_O64: | |
3868 | mips_abi = MIPS_ABI_O64; | |
3869 | break; | |
3870 | case E_MIPS_ABI_EABI32: | |
3871 | mips_abi = MIPS_ABI_EABI32; | |
3872 | break; | |
3873 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 3874 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
3875 | break; |
3876 | default: | |
3877 | mips_abi = MIPS_ABI_UNKNOWN; | |
3878 | break; | |
3879 | } | |
bf64bfd6 AC |
3880 | /* Try the architecture for any hint of the corect ABI */ |
3881 | if (mips_abi == MIPS_ABI_UNKNOWN | |
3882 | && info.bfd_arch_info != NULL | |
3883 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
3884 | { | |
3885 | switch (info.bfd_arch_info->mach) | |
3886 | { | |
3887 | case bfd_mach_mips3900: | |
3888 | mips_abi = MIPS_ABI_EABI32; | |
3889 | break; | |
3890 | case bfd_mach_mips4100: | |
3891 | case bfd_mach_mips5000: | |
3892 | mips_abi = MIPS_ABI_EABI64; | |
3893 | break; | |
3894 | } | |
3895 | } | |
0dadbba0 AC |
3896 | #ifdef MIPS_DEFAULT_ABI |
3897 | if (mips_abi == MIPS_ABI_UNKNOWN) | |
3898 | mips_abi = MIPS_DEFAULT_ABI; | |
3899 | #endif | |
4b9b3959 AC |
3900 | |
3901 | if (gdbarch_debug) | |
3902 | { | |
3903 | fprintf_unfiltered (gdb_stdlog, | |
3904 | "mips_gdbarch_init: elf_flags = %08x\n", | |
3905 | elf_flags); | |
3906 | fprintf_unfiltered (gdb_stdlog, | |
3907 | "mips_gdbarch_init: ef_mips_arch = %d\n", | |
3908 | ef_mips_arch); | |
3909 | fprintf_unfiltered (gdb_stdlog, | |
3910 | "mips_gdbarch_init: ef_mips_bitptrs = %d\n", | |
3911 | ef_mips_bitptrs); | |
3912 | fprintf_unfiltered (gdb_stdlog, | |
3913 | "mips_gdbarch_init: mips_abi = %d\n", | |
3914 | mips_abi); | |
3915 | } | |
0dadbba0 | 3916 | |
c2d11a7d JM |
3917 | /* try to find a pre-existing architecture */ |
3918 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3919 | arches != NULL; | |
3920 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3921 | { | |
3922 | /* MIPS needs to be pedantic about which ABI the object is | |
3923 | using. */ | |
3924 | if (gdbarch_tdep (current_gdbarch)->elf_flags != elf_flags) | |
3925 | continue; | |
0dadbba0 AC |
3926 | if (gdbarch_tdep (current_gdbarch)->mips_abi != mips_abi) |
3927 | continue; | |
c2d11a7d JM |
3928 | return arches->gdbarch; |
3929 | } | |
3930 | ||
3931 | /* Need a new architecture. Fill in a target specific vector. */ | |
3932 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3933 | gdbarch = gdbarch_alloc (&info, tdep); | |
3934 | tdep->elf_flags = elf_flags; | |
3935 | ||
3936 | /* Initially set everything according to the ABI. */ | |
3937 | set_gdbarch_short_bit (gdbarch, 16); | |
3938 | set_gdbarch_int_bit (gdbarch, 32); | |
3939 | set_gdbarch_float_bit (gdbarch, 32); | |
3940 | set_gdbarch_double_bit (gdbarch, 64); | |
3941 | set_gdbarch_long_double_bit (gdbarch, 64); | |
0dadbba0 AC |
3942 | tdep->mips_abi = mips_abi; |
3943 | switch (mips_abi) | |
c2d11a7d | 3944 | { |
0dadbba0 | 3945 | case MIPS_ABI_O32: |
a5ea2558 | 3946 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 3947 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 3948 | tdep->mips_fp_register_double = 0; |
0dadbba0 AC |
3949 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 7; |
3950 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15; | |
3951 | tdep->mips_regs_have_home_p = 1; | |
5213ab06 | 3952 | tdep->gdb_target_is_mips64 = 0; |
c2d11a7d JM |
3953 | set_gdbarch_long_bit (gdbarch, 32); |
3954 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3955 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3956 | break; | |
0dadbba0 | 3957 | case MIPS_ABI_O64: |
a5ea2558 | 3958 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 3959 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 3960 | tdep->mips_fp_register_double = 1; |
0dadbba0 AC |
3961 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 7; |
3962 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15; | |
3963 | tdep->mips_regs_have_home_p = 1; | |
5213ab06 | 3964 | tdep->gdb_target_is_mips64 = 1; |
c2d11a7d JM |
3965 | set_gdbarch_long_bit (gdbarch, 32); |
3966 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3967 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3968 | break; | |
0dadbba0 | 3969 | case MIPS_ABI_EABI32: |
a5ea2558 | 3970 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 3971 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 3972 | tdep->mips_fp_register_double = 0; |
0dadbba0 AC |
3973 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; |
3974 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3975 | tdep->mips_regs_have_home_p = 0; | |
5213ab06 | 3976 | tdep->gdb_target_is_mips64 = 0; |
c2d11a7d JM |
3977 | set_gdbarch_long_bit (gdbarch, 32); |
3978 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3979 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3980 | break; | |
0dadbba0 | 3981 | case MIPS_ABI_EABI64: |
a5ea2558 | 3982 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 3983 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 3984 | tdep->mips_fp_register_double = 1; |
0dadbba0 AC |
3985 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; |
3986 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3987 | tdep->mips_regs_have_home_p = 0; | |
5213ab06 | 3988 | tdep->gdb_target_is_mips64 = 1; |
c2d11a7d JM |
3989 | set_gdbarch_long_bit (gdbarch, 64); |
3990 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3991 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3992 | break; | |
0dadbba0 | 3993 | case MIPS_ABI_N32: |
0dadbba0 AC |
3994 | tdep->mips_default_saved_regsize = 4; |
3995 | tdep->mips_default_stack_argsize = 8; | |
3996 | tdep->mips_fp_register_double = 1; | |
3997 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; | |
3998 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
3999 | tdep->mips_regs_have_home_p = 0; | |
5213ab06 | 4000 | tdep->gdb_target_is_mips64 = 0; |
0dadbba0 AC |
4001 | set_gdbarch_long_bit (gdbarch, 32); |
4002 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4003 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4004 | break; | |
c2d11a7d | 4005 | default: |
a5ea2558 | 4006 | tdep->mips_default_saved_regsize = MIPS_REGSIZE; |
0dadbba0 | 4007 | tdep->mips_default_stack_argsize = MIPS_REGSIZE; |
c2d11a7d | 4008 | tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8); |
0dadbba0 AC |
4009 | tdep->mips_last_arg_regnum = ZERO_REGNUM + 11; |
4010 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; | |
4011 | tdep->mips_regs_have_home_p = 1; | |
5213ab06 | 4012 | tdep->gdb_target_is_mips64 = 0; |
c2d11a7d JM |
4013 | set_gdbarch_long_bit (gdbarch, 32); |
4014 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4015 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4016 | break; | |
4017 | } | |
4018 | ||
a5ea2558 AC |
4019 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
4020 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
4021 | comment: | |
4022 | ||
4023 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
4024 | flag in object files because to do so would make it impossible to | |
4025 | link with libraries compiled without "-gp32". This is | |
4026 | unnecessarily restrictive. | |
4027 | ||
4028 | We could solve this problem by adding "-gp32" multilibs to gcc, | |
4029 | but to set this flag before gcc is built with such multilibs will | |
4030 | break too many systems.'' | |
4031 | ||
4032 | But even more unhelpfully, the default linker output target for | |
4033 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
4034 | for 64-bit programs - you need to change the ABI to change this, | |
4035 | and not all gcc targets support that currently. Therefore using | |
4036 | this flag to detect 32-bit mode would do the wrong thing given | |
4037 | the current gcc - it would make GDB treat these 64-bit programs | |
4038 | as 32-bit programs by default. */ | |
4039 | ||
c2d11a7d JM |
4040 | /* determine the ISA */ |
4041 | switch (elf_flags & EF_MIPS_ARCH) | |
4042 | { | |
4043 | case E_MIPS_ARCH_1: | |
4044 | ef_mips_arch = 1; | |
4045 | break; | |
4046 | case E_MIPS_ARCH_2: | |
4047 | ef_mips_arch = 2; | |
4048 | break; | |
4049 | case E_MIPS_ARCH_3: | |
4050 | ef_mips_arch = 3; | |
4051 | break; | |
4052 | case E_MIPS_ARCH_4: | |
4053 | ef_mips_arch = 0; | |
4054 | break; | |
4055 | default: | |
4056 | break; | |
4057 | } | |
4058 | ||
4059 | #if 0 | |
4060 | /* determine the size of a pointer */ | |
4061 | if ((elf_flags & EF_MIPS_32BITPTRS)) | |
4062 | { | |
4063 | ef_mips_bitptrs = 32; | |
4064 | } | |
4065 | else if ((elf_flags & EF_MIPS_64BITPTRS)) | |
4066 | { | |
4067 | ef_mips_bitptrs = 64; | |
4068 | } | |
4069 | else | |
4070 | { | |
4071 | ef_mips_bitptrs = 0; | |
4072 | } | |
4073 | #endif | |
4074 | ||
c2d11a7d JM |
4075 | /* enable/disable the MIPS FPU */ |
4076 | if (!mips_fpu_type_auto) | |
4077 | tdep->mips_fpu_type = mips_fpu_type; | |
4078 | else if (info.bfd_arch_info != NULL | |
4079 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4080 | switch (info.bfd_arch_info->mach) | |
4081 | { | |
b0069a17 | 4082 | case bfd_mach_mips3900: |
c2d11a7d | 4083 | case bfd_mach_mips4100: |
ed9a39eb | 4084 | case bfd_mach_mips4111: |
c2d11a7d JM |
4085 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
4086 | break; | |
bf64bfd6 AC |
4087 | case bfd_mach_mips4650: |
4088 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
4089 | break; | |
c2d11a7d JM |
4090 | default: |
4091 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4092 | break; | |
4093 | } | |
4094 | else | |
4095 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
4096 | ||
4097 | /* MIPS version of register names. NOTE: At present the MIPS | |
4098 | register name management is part way between the old - | |
4099 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
4100 | Further work on it is required. */ | |
4101 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
4102 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); | |
4103 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
4104 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
4105 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); | |
4106 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); | |
4107 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4108 | ||
4109 | /* Initialize a frame */ | |
4110 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
4111 | ||
4112 | /* MIPS version of CALL_DUMMY */ | |
4113 | ||
4114 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4115 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
4116 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
4117 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
4118 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
4119 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
4120 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
4121 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4122 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
4123 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
4124 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
4125 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
4126 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
4127 | set_gdbarch_push_arguments (gdbarch, mips_push_arguments); | |
4128 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
b9a8e3bf | 4129 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 4130 | |
c4093a6a | 4131 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
47a8d4ba | 4132 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 4133 | |
4b9b3959 AC |
4134 | return gdbarch; |
4135 | } | |
4136 | ||
4137 | static void | |
4138 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4139 | { | |
4140 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4141 | if (tdep != NULL) | |
c2d11a7d | 4142 | { |
4b9b3959 AC |
4143 | fprintf_unfiltered (file, |
4144 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 4145 | tdep->elf_flags); |
4b9b3959 AC |
4146 | fprintf_unfiltered (file, |
4147 | "mips_dump_tdep: tdep->mips_abi = %d\n", | |
0dadbba0 | 4148 | tdep->mips_abi); |
c2d11a7d | 4149 | } |
4b9b3959 AC |
4150 | fprintf_unfiltered (file, |
4151 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4152 | FP_REGISTER_DOUBLE); | |
4153 | fprintf_unfiltered (file, | |
4154 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
4155 | MIPS_DEFAULT_FPU_TYPE, | |
4156 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4157 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4158 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4159 | : "???")); | |
4160 | fprintf_unfiltered (file, | |
4161 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
4162 | MIPS_EABI); | |
4163 | fprintf_unfiltered (file, | |
4164 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d\n", | |
4165 | MIPS_LAST_FP_ARG_REGNUM); | |
4b9b3959 AC |
4166 | fprintf_unfiltered (file, |
4167 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
4168 | MIPS_FPU_TYPE, | |
4169 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
4170 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
4171 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
4172 | : "???")); | |
4173 | fprintf_unfiltered (file, | |
4174 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
4175 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
4176 | fprintf_unfiltered (file, |
4177 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
4178 | FP_REGISTER_DOUBLE); | |
4179 | fprintf_unfiltered (file, | |
4180 | "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n", | |
4181 | MIPS_REGS_HAVE_HOME_P); | |
4182 | fprintf_unfiltered (file, | |
4183 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
4184 | MIPS_DEFAULT_STACK_ARGSIZE); | |
4185 | fprintf_unfiltered (file, | |
4186 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
4187 | MIPS_STACK_ARGSIZE); | |
4188 | fprintf_unfiltered (file, | |
4189 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
4190 | MIPS_REGSIZE); | |
2475bac3 AC |
4191 | fprintf_unfiltered (file, |
4192 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
4193 | A0_REGNUM); | |
4194 | fprintf_unfiltered (file, | |
4195 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
4196 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
4197 | fprintf_unfiltered (file, | |
4198 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
4199 | XSTRING (ATTACH_DETACH)); | |
4200 | fprintf_unfiltered (file, | |
4201 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
4202 | BADVADDR_REGNUM); | |
4203 | fprintf_unfiltered (file, | |
4204 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
4205 | fprintf_unfiltered (file, | |
4206 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
4207 | CAUSE_REGNUM); | |
4208 | fprintf_unfiltered (file, | |
4209 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
4210 | CPLUS_MARKER); | |
4211 | fprintf_unfiltered (file, | |
4212 | "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n", | |
4213 | DEFAULT_MIPS_TYPE); | |
4214 | fprintf_unfiltered (file, | |
4215 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
4216 | XSTRING (DO_REGISTERS_INFO)); | |
4217 | fprintf_unfiltered (file, | |
4218 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
4219 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
4220 | fprintf_unfiltered (file, | |
4221 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
4222 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
4223 | fprintf_unfiltered (file, | |
4224 | "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n", | |
4225 | XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM))); | |
4226 | fprintf_unfiltered (file, | |
4227 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
4228 | FCRCS_REGNUM); | |
4229 | fprintf_unfiltered (file, | |
4230 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
4231 | FCRIR_REGNUM); | |
4232 | fprintf_unfiltered (file, | |
4233 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
4234 | FIRST_EMBED_REGNUM); | |
4235 | fprintf_unfiltered (file, | |
4236 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
4237 | FPA0_REGNUM); | |
4238 | fprintf_unfiltered (file, | |
4239 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
4240 | GDB_TARGET_IS_MIPS64); | |
4241 | fprintf_unfiltered (file, | |
4242 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
4243 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
4244 | fprintf_unfiltered (file, | |
4245 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
4246 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
4247 | fprintf_unfiltered (file, | |
4248 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
4249 | GEN_REG_SAVE_MASK); | |
4250 | fprintf_unfiltered (file, | |
4251 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
4252 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
4253 | fprintf_unfiltered (file, | |
4254 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
4255 | HI_REGNUM); | |
4256 | fprintf_unfiltered (file, | |
4257 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
4258 | fprintf_unfiltered (file, | |
4259 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
4260 | fprintf_unfiltered (file, | |
4261 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
4262 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
4263 | fprintf_unfiltered (file, | |
4264 | "mips_dump_tdep: INIT_FRAME_PC # %s\n", | |
4265 | XSTRING (INIT_FRAME_PC (FROMLEAF, PREV))); | |
4266 | fprintf_unfiltered (file, | |
4267 | "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n", | |
4268 | XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF, PREV))); | |
4269 | fprintf_unfiltered (file, | |
4270 | "mips_dump_tdep: IN_SIGTRAMP # %s\n", | |
4271 | XSTRING (IN_SIGTRAMP (PC, NAME))); | |
4272 | fprintf_unfiltered (file, | |
4273 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
4274 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
4275 | fprintf_unfiltered (file, | |
4276 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
4277 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
4278 | fprintf_unfiltered (file, | |
4279 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
4280 | fprintf_unfiltered (file, | |
4281 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
4282 | LAST_EMBED_REGNUM); | |
4283 | fprintf_unfiltered (file, | |
4284 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
4285 | fprintf_unfiltered (file, | |
4286 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
4287 | LO_REGNUM); | |
4288 | #ifdef MACHINE_CPROC_FP_OFFSET | |
4289 | fprintf_unfiltered (file, | |
4290 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
4291 | MACHINE_CPROC_FP_OFFSET); | |
4292 | #endif | |
4293 | #ifdef MACHINE_CPROC_PC_OFFSET | |
4294 | fprintf_unfiltered (file, | |
4295 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
4296 | MACHINE_CPROC_PC_OFFSET); | |
4297 | #endif | |
4298 | #ifdef MACHINE_CPROC_SP_OFFSET | |
4299 | fprintf_unfiltered (file, | |
4300 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
4301 | MACHINE_CPROC_SP_OFFSET); | |
4302 | #endif | |
4303 | fprintf_unfiltered (file, | |
4304 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
4305 | fprintf_unfiltered (file, | |
4306 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
4307 | fprintf_unfiltered (file, | |
4308 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
4309 | MIPS16_INSTLEN); | |
4310 | fprintf_unfiltered (file, | |
4311 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
4312 | fprintf_unfiltered (file, | |
4313 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
4314 | fprintf_unfiltered (file, | |
4315 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
4316 | fprintf_unfiltered (file, | |
4317 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
4318 | MIPS_INSTLEN); | |
4319 | fprintf_unfiltered (file, | |
4320 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d\n", | |
4321 | MIPS_LAST_ARG_REGNUM); | |
4322 | fprintf_unfiltered (file, | |
4323 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
4324 | MIPS_NUMREGS); | |
4325 | fprintf_unfiltered (file, | |
4326 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
4327 | fprintf_unfiltered (file, | |
4328 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
4329 | MIPS_SAVED_REGSIZE); | |
4330 | fprintf_unfiltered (file, | |
4331 | "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n"); | |
4332 | fprintf_unfiltered (file, | |
4333 | "mips_dump_tdep: MSYMBOL_SIZE # %s\n", | |
4334 | XSTRING (MSYMBOL_SIZE (MSYM))); | |
4335 | fprintf_unfiltered (file, | |
4336 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
4337 | fprintf_unfiltered (file, | |
4338 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
4339 | fprintf_unfiltered (file, | |
4340 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
4341 | fprintf_unfiltered (file, | |
4342 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
4343 | fprintf_unfiltered (file, | |
4344 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
4345 | PRID_REGNUM); | |
4346 | fprintf_unfiltered (file, | |
4347 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
4348 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
4349 | fprintf_unfiltered (file, | |
4350 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
4351 | fprintf_unfiltered (file, | |
4352 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
4353 | fprintf_unfiltered (file, | |
4354 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
4355 | fprintf_unfiltered (file, | |
4356 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
4357 | fprintf_unfiltered (file, | |
4358 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
4359 | fprintf_unfiltered (file, | |
4360 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
4361 | fprintf_unfiltered (file, | |
4362 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
4363 | fprintf_unfiltered (file, | |
4364 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
4365 | fprintf_unfiltered (file, | |
4366 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
4367 | fprintf_unfiltered (file, | |
4368 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
4369 | fprintf_unfiltered (file, | |
4370 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
4371 | fprintf_unfiltered (file, | |
4372 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
4373 | fprintf_unfiltered (file, | |
4374 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
4375 | PS_REGNUM); | |
4376 | fprintf_unfiltered (file, | |
4377 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
4378 | PUSH_FP_REGNUM); | |
4379 | fprintf_unfiltered (file, | |
4380 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
4381 | RA_REGNUM); | |
4382 | fprintf_unfiltered (file, | |
4383 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
4384 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4385 | fprintf_unfiltered (file, | |
4386 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
4387 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
4388 | fprintf_unfiltered (file, | |
4389 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
4390 | fprintf_unfiltered (file, | |
4391 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
4392 | fprintf_unfiltered (file, | |
4393 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
4394 | #ifdef SAVED_BYTES | |
4395 | fprintf_unfiltered (file, | |
4396 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
4397 | SAVED_BYTES); | |
4398 | #endif | |
4399 | #ifdef SAVED_FP | |
4400 | fprintf_unfiltered (file, | |
4401 | "mips_dump_tdep: SAVED_FP = %d\n", | |
4402 | SAVED_FP); | |
4403 | #endif | |
4404 | #ifdef SAVED_PC | |
4405 | fprintf_unfiltered (file, | |
4406 | "mips_dump_tdep: SAVED_PC = %d\n", | |
4407 | SAVED_PC); | |
4408 | #endif | |
4409 | fprintf_unfiltered (file, | |
4410 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
4411 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
4412 | fprintf_unfiltered (file, | |
4413 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
4414 | fprintf_unfiltered (file, | |
4415 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
4416 | SIGFRAME_BASE); | |
4417 | fprintf_unfiltered (file, | |
4418 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
4419 | SIGFRAME_FPREGSAVE_OFF); | |
4420 | fprintf_unfiltered (file, | |
4421 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
4422 | SIGFRAME_PC_OFF); | |
4423 | fprintf_unfiltered (file, | |
4424 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
4425 | SIGFRAME_REGSAVE_OFF); | |
4426 | fprintf_unfiltered (file, | |
4427 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
4428 | SIGFRAME_REG_SIZE); | |
4429 | fprintf_unfiltered (file, | |
4430 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
4431 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
4432 | fprintf_unfiltered (file, | |
4433 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
4434 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
4435 | fprintf_unfiltered (file, | |
4436 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n", | |
4437 | SOFTWARE_SINGLE_STEP_P); | |
4438 | fprintf_unfiltered (file, | |
4439 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n", | |
4440 | SOFTWARE_SINGLE_STEP_P); | |
4441 | fprintf_unfiltered (file, | |
4442 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
4443 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
4444 | #ifdef STACK_END_ADDR | |
4445 | fprintf_unfiltered (file, | |
4446 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
4447 | STACK_END_ADDR); | |
4448 | #endif | |
4449 | fprintf_unfiltered (file, | |
4450 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
4451 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
4452 | fprintf_unfiltered (file, | |
4453 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
4454 | STEP_SKIPS_DELAY_P); | |
4455 | fprintf_unfiltered (file, | |
4456 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
4457 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
4458 | fprintf_unfiltered (file, | |
4459 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
4460 | T9_REGNUM); | |
4461 | fprintf_unfiltered (file, | |
4462 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
4463 | fprintf_unfiltered (file, | |
4464 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
4465 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
4466 | fprintf_unfiltered (file, | |
4467 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
4468 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
4469 | fprintf_unfiltered (file, | |
4470 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
4471 | fprintf_unfiltered (file, | |
4472 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
4473 | XSTRING (TM_PRINT_INSN_MACH)); | |
4474 | #ifdef TRACE_CLEAR | |
4475 | fprintf_unfiltered (file, | |
4476 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
4477 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
4478 | #endif | |
4479 | #ifdef TRACE_FLAVOR | |
4480 | fprintf_unfiltered (file, | |
4481 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
4482 | TRACE_FLAVOR); | |
4483 | #endif | |
4484 | #ifdef TRACE_FLAVOR_SIZE | |
4485 | fprintf_unfiltered (file, | |
4486 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
4487 | TRACE_FLAVOR_SIZE); | |
4488 | #endif | |
4489 | #ifdef TRACE_SET | |
4490 | fprintf_unfiltered (file, | |
4491 | "mips_dump_tdep: TRACE_SET # %s\n", | |
4492 | XSTRING (TRACE_SET (X,STATE))); | |
4493 | #endif | |
4494 | fprintf_unfiltered (file, | |
4495 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
4496 | #ifdef UNUSED_REGNUM | |
4497 | fprintf_unfiltered (file, | |
4498 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
4499 | UNUSED_REGNUM); | |
4500 | #endif | |
4501 | fprintf_unfiltered (file, | |
4502 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
4503 | V0_REGNUM); | |
4504 | fprintf_unfiltered (file, | |
4505 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
4506 | (long) VM_MIN_ADDRESS); | |
4507 | #ifdef VX_NUM_REGS | |
4508 | fprintf_unfiltered (file, | |
4509 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
4510 | VX_NUM_REGS); | |
4511 | #endif | |
4512 | fprintf_unfiltered (file, | |
4513 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
4514 | ZERO_REGNUM); | |
4515 | fprintf_unfiltered (file, | |
4516 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
4517 | _PROC_MAGIC_); | |
c2d11a7d JM |
4518 | } |
4519 | ||
c906108c SS |
4520 | void |
4521 | _initialize_mips_tdep () | |
4522 | { | |
4523 | static struct cmd_list_element *mipsfpulist = NULL; | |
4524 | struct cmd_list_element *c; | |
4525 | ||
4b9b3959 | 4526 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 4527 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
4528 | tm_print_insn = gdb_print_insn_mips; |
4529 | ||
a5ea2558 AC |
4530 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
4531 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
4532 | "Various MIPS specific commands.", | |
4533 | &setmipscmdlist, "set mips ", 0, &setlist); | |
4534 | ||
4535 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
4536 | "Various MIPS specific commands.", | |
4537 | &showmipscmdlist, "show mips ", 0, &showlist); | |
4538 | ||
4539 | /* Allow the user to override the saved register size. */ | |
4540 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
4541 | class_obscure, |
4542 | size_enums, | |
4543 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
4544 | Set size of general purpose registers saved on the stack.\n\ |
4545 | This option can be set to one of:\n\ | |
4546 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
4547 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
4548 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
4549 | saved GP register size from information contained in the executable.\n\ | |
4550 | (default: auto)", | |
1ed2a135 | 4551 | &setmipscmdlist), |
a5ea2558 AC |
4552 | &showmipscmdlist); |
4553 | ||
d929b26f AC |
4554 | /* Allow the user to override the argument stack size. */ |
4555 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
4556 | class_obscure, | |
4557 | size_enums, | |
1ed2a135 | 4558 | &mips_stack_argsize_string, "\ |
d929b26f AC |
4559 | Set the amount of stack space reserved for each argument.\n\ |
4560 | This option can be set to one of:\n\ | |
4561 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
4562 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
4563 | auto - Allow GDB to determine the correct setting from the current\n\ | |
4564 | target and executable (default)", | |
4565 | &setmipscmdlist), | |
4566 | &showmipscmdlist); | |
4567 | ||
c906108c SS |
4568 | /* Let the user turn off floating point and set the fence post for |
4569 | heuristic_proc_start. */ | |
4570 | ||
4571 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
4572 | "Set use of MIPS floating-point coprocessor.", | |
4573 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
4574 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
4575 | "Select single-precision MIPS floating-point coprocessor.", | |
4576 | &mipsfpulist); | |
4577 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
4578 | "Select double-precision MIPS floating-point coprocessor .", | |
4579 | &mipsfpulist); | |
4580 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
4581 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
4582 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
4583 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
4584 | "Select no MIPS floating-point coprocessor.", | |
4585 | &mipsfpulist); | |
4586 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
4587 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
4588 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
4589 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
4590 | "Select MIPS floating-point coprocessor automatically.", | |
4591 | &mipsfpulist); | |
4592 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
4593 | "Show current use of MIPS floating-point coprocessor target.", | |
4594 | &showlist); | |
4595 | ||
c2d11a7d | 4596 | #if !GDB_MULTI_ARCH |
c906108c SS |
4597 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
4598 | (char *) &tmp_mips_processor_type, | |
4599 | "Set the type of MIPS processor in use.\n\ | |
4600 | Set this to be able to access processor-type-specific registers.\n\ | |
4601 | ", | |
4602 | &setlist); | |
4603 | c->function.cfunc = mips_set_processor_type_command; | |
4604 | c = add_show_from_set (c, &showlist); | |
4605 | c->function.cfunc = mips_show_processor_type_command; | |
4606 | ||
4607 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); | |
4608 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); | |
c2d11a7d | 4609 | #endif |
c906108c SS |
4610 | |
4611 | /* We really would like to have both "0" and "unlimited" work, but | |
4612 | command.c doesn't deal with that. So make it a var_zinteger | |
4613 | because the user can always use "999999" or some such for unlimited. */ | |
4614 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
4615 | (char *) &heuristic_fence_post, | |
4616 | "\ | |
4617 | Set the distance searched for the start of a function.\n\ | |
4618 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
4619 | program for the start of a function. This command sets the distance of the\n\ | |
4620 | search. The only need to set it is when debugging a stripped executable.", | |
4621 | &setlist); | |
4622 | /* We need to throw away the frame cache when we set this, since it | |
4623 | might change our ability to get backtraces. */ | |
4624 | c->function.sfunc = reinit_frame_cache_sfunc; | |
4625 | add_show_from_set (c, &showlist); | |
4626 | ||
4627 | /* Allow the user to control whether the upper bits of 64-bit | |
4628 | addresses should be zeroed. */ | |
4629 | add_show_from_set | |
c5aa993b JM |
4630 | (add_set_cmd ("mask-address", no_class, var_boolean, (char *) &mask_address_p, |
4631 | "Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
c906108c SS |
4632 | Use \"on\" to enable the masking, and \"off\" to disable it.\n\ |
4633 | Without an argument, zeroing of upper address bits is enabled.", &setlist), | |
4634 | &showlist); | |
43e526b9 JM |
4635 | |
4636 | /* Allow the user to control the size of 32 bit registers within the | |
4637 | raw remote packet. */ | |
4638 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
4639 | class_obscure, | |
4640 | var_boolean, | |
4641 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
4642 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
4643 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
4644 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
4645 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
4646 | &setlist), | |
4647 | &showlist); | |
c906108c | 4648 | } |