Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
0fb0cc75 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
f8b73d13 DJ |
97 | /* The standard register names, and all the valid aliases for them. */ |
98 | struct register_alias | |
99 | { | |
100 | const char *name; | |
101 | int regnum; | |
102 | }; | |
103 | ||
104 | /* Aliases for o32 and most other ABIs. */ | |
105 | const struct register_alias mips_o32_aliases[] = { | |
106 | { "ta0", 12 }, | |
107 | { "ta1", 13 }, | |
108 | { "ta2", 14 }, | |
109 | { "ta3", 15 } | |
110 | }; | |
111 | ||
112 | /* Aliases for n32 and n64. */ | |
113 | const struct register_alias mips_n32_n64_aliases[] = { | |
114 | { "ta0", 8 }, | |
115 | { "ta1", 9 }, | |
116 | { "ta2", 10 }, | |
117 | { "ta3", 11 } | |
118 | }; | |
119 | ||
120 | /* Aliases for ABI-independent registers. */ | |
121 | const struct register_alias mips_register_aliases[] = { | |
122 | /* The architecture manuals specify these ABI-independent names for | |
123 | the GPRs. */ | |
124 | #define R(n) { "r" #n, n } | |
125 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
126 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
127 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
128 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
129 | #undef R | |
130 | ||
131 | /* k0 and k1 are sometimes called these instead (for "kernel | |
132 | temp"). */ | |
133 | { "kt0", 26 }, | |
134 | { "kt1", 27 }, | |
135 | ||
136 | /* This is the traditional GDB name for the CP0 status register. */ | |
137 | { "sr", MIPS_PS_REGNUM }, | |
138 | ||
139 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
140 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
141 | ||
142 | /* This is the traditional GDB name for the FCSR. */ | |
143 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
144 | }; | |
145 | ||
865093a3 AR |
146 | const struct register_alias mips_numeric_register_aliases[] = { |
147 | #define R(n) { #n, n } | |
148 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
149 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
150 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
151 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
152 | #undef R | |
153 | }; | |
154 | ||
c906108c SS |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
56cea623 AC |
171 | const struct mips_regnum * |
172 | mips_regnum (struct gdbarch *gdbarch) | |
173 | { | |
174 | return gdbarch_tdep (gdbarch)->regnum; | |
175 | } | |
176 | ||
177 | static int | |
178 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
179 | { | |
180 | return mips_regnum (gdbarch)->fp0 + 12; | |
181 | } | |
182 | ||
74ed0bb4 MD |
183 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
184 | == MIPS_ABI_EABI32 \ | |
185 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 186 | |
74ed0bb4 | 187 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 188 | |
74ed0bb4 | 189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 190 | |
74ed0bb4 | 191 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 192 | |
95404a3e AC |
193 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
194 | functions to test, set, or clear bit 0 of addresses. */ | |
195 | ||
196 | static CORE_ADDR | |
197 | is_mips16_addr (CORE_ADDR addr) | |
198 | { | |
199 | return ((addr) & 1); | |
200 | } | |
201 | ||
95404a3e AC |
202 | static CORE_ADDR |
203 | unmake_mips16_addr (CORE_ADDR addr) | |
204 | { | |
5b652102 | 205 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
206 | } |
207 | ||
d1973055 KB |
208 | /* Return the MIPS ABI associated with GDBARCH. */ |
209 | enum mips_abi | |
210 | mips_abi (struct gdbarch *gdbarch) | |
211 | { | |
212 | return gdbarch_tdep (gdbarch)->mips_abi; | |
213 | } | |
214 | ||
4246e332 | 215 | int |
1b13c4f6 | 216 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 217 | { |
29709017 DJ |
218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
219 | ||
220 | /* If we know how big the registers are, use that size. */ | |
221 | if (tdep->register_size_valid_p) | |
222 | return tdep->register_size; | |
223 | ||
224 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
225 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
226 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
227 | } | |
228 | ||
480d3dd2 AC |
229 | /* Return the currently configured (or set) saved register size. */ |
230 | ||
e6bc2e8a | 231 | unsigned int |
13326b4e | 232 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 233 | { |
1a69e1e4 DJ |
234 | switch (mips_abi (gdbarch)) |
235 | { | |
236 | case MIPS_ABI_EABI32: | |
237 | case MIPS_ABI_O32: | |
238 | return 4; | |
239 | case MIPS_ABI_N32: | |
240 | case MIPS_ABI_N64: | |
241 | case MIPS_ABI_O64: | |
242 | case MIPS_ABI_EABI64: | |
243 | return 8; | |
244 | case MIPS_ABI_UNKNOWN: | |
245 | case MIPS_ABI_LAST: | |
246 | default: | |
247 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
248 | } | |
d929b26f AC |
249 | } |
250 | ||
71b8ef93 | 251 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 252 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 253 | "info" field is used for this purpose. |
5a89d8aa | 254 | |
95f1da47 | 255 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
256 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
257 | minimal symbol to mark it as a 16-bit function | |
258 | ||
f594e5e9 | 259 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 260 | |
5a89d8aa | 261 | static void |
6d82d43b AC |
262 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
263 | { | |
264 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
265 | { | |
b887350f | 266 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b AC |
267 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
268 | } | |
5a89d8aa MS |
269 | } |
270 | ||
71b8ef93 MS |
271 | static int |
272 | msymbol_is_special (struct minimal_symbol *msym) | |
273 | { | |
b887350f | 274 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
275 | } |
276 | ||
88658117 AC |
277 | /* XFER a value from the big/little/left end of the register. |
278 | Depending on the size of the value it might occupy the entire | |
279 | register or just part of it. Make an allowance for this, aligning | |
280 | things accordingly. */ | |
281 | ||
282 | static void | |
ba32f989 DJ |
283 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
284 | int reg_num, int length, | |
870cd05e MK |
285 | enum bfd_endian endian, gdb_byte *in, |
286 | const gdb_byte *out, int buf_offset) | |
88658117 | 287 | { |
88658117 | 288 | int reg_offset = 0; |
72a155b4 UW |
289 | |
290 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
291 | /* Need to transfer the left or right part of the register, based on |
292 | the targets byte order. */ | |
88658117 AC |
293 | switch (endian) |
294 | { | |
295 | case BFD_ENDIAN_BIG: | |
72a155b4 | 296 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
297 | break; |
298 | case BFD_ENDIAN_LITTLE: | |
299 | reg_offset = 0; | |
300 | break; | |
6d82d43b | 301 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
302 | reg_offset = 0; |
303 | break; | |
304 | default: | |
e2e0b3e5 | 305 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
306 | } |
307 | if (mips_debug) | |
cb1d2653 AC |
308 | fprintf_unfiltered (gdb_stderr, |
309 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
310 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
311 | if (mips_debug && out != NULL) |
312 | { | |
313 | int i; | |
cb1d2653 | 314 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 315 | for (i = 0; i < length; i++) |
cb1d2653 | 316 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
317 | } |
318 | if (in != NULL) | |
6d82d43b AC |
319 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
320 | in + buf_offset); | |
88658117 | 321 | if (out != NULL) |
6d82d43b AC |
322 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
323 | out + buf_offset); | |
88658117 AC |
324 | if (mips_debug && in != NULL) |
325 | { | |
326 | int i; | |
cb1d2653 | 327 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 328 | for (i = 0; i < length; i++) |
cb1d2653 | 329 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
330 | } |
331 | if (mips_debug) | |
332 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
333 | } | |
334 | ||
dd824b04 DJ |
335 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
336 | compatiblity mode. A return value of 1 means that we have | |
337 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
338 | ||
339 | static int | |
9c9acae0 | 340 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 341 | { |
72a155b4 | 342 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
344 | meaningful. */ | |
72a155b4 | 345 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
346 | return 0; |
347 | ||
348 | #if 0 | |
349 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
350 | in all the places we deal with FP registers. PR gdb/413. */ | |
351 | /* Otherwise check the FR bit in the status register - it controls | |
352 | the FP compatiblity mode. If it is clear we are in compatibility | |
353 | mode. */ | |
9c9acae0 | 354 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
355 | return 1; |
356 | #endif | |
361d1df0 | 357 | |
dd824b04 DJ |
358 | return 0; |
359 | } | |
360 | ||
7a292a7a | 361 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 362 | |
74ed0bb4 | 363 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 364 | |
a14ed312 | 365 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 366 | |
acdb74a0 AC |
367 | /* The list of available "set mips " and "show mips " commands */ |
368 | ||
369 | static struct cmd_list_element *setmipscmdlist = NULL; | |
370 | static struct cmd_list_element *showmipscmdlist = NULL; | |
371 | ||
5e2e9765 KB |
372 | /* Integer registers 0 thru 31 are handled explicitly by |
373 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 374 | are listed in the following tables. */ |
691c0433 | 375 | |
6d82d43b AC |
376 | enum |
377 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
378 | |
379 | /* Generic MIPS. */ | |
380 | ||
381 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
382 | "sr", "lo", "hi", "bad", "cause", "pc", |
383 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
384 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
385 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
386 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
387 | "fsr", "fir", "" /*"fp" */ , "", | |
388 | "", "", "", "", "", "", "", "", | |
389 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
390 | }; |
391 | ||
392 | /* Names of IDT R3041 registers. */ | |
393 | ||
394 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
395 | "sr", "lo", "hi", "bad", "cause", "pc", |
396 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
397 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
398 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
399 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
400 | "fsr", "fir", "", /*"fp" */ "", | |
401 | "", "", "bus", "ccfg", "", "", "", "", | |
402 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
403 | }; |
404 | ||
405 | /* Names of tx39 registers. */ | |
406 | ||
407 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
408 | "sr", "lo", "hi", "bad", "cause", "pc", |
409 | "", "", "", "", "", "", "", "", | |
410 | "", "", "", "", "", "", "", "", | |
411 | "", "", "", "", "", "", "", "", | |
412 | "", "", "", "", "", "", "", "", | |
413 | "", "", "", "", | |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
416 | }; |
417 | ||
418 | /* Names of IRIX registers. */ | |
419 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
420 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
421 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
422 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
423 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
424 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
425 | }; |
426 | ||
cce74817 | 427 | |
5e2e9765 | 428 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 429 | static const char * |
d93859e2 | 430 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 431 | { |
d93859e2 | 432 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
433 | /* GPR names for all ABIs other than n32/n64. */ |
434 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
435 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
436 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
437 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
438 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
439 | }; |
440 | ||
441 | /* GPR names for n32 and n64 ABIs. */ | |
442 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
444 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
447 | }; |
448 | ||
d93859e2 | 449 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 450 | |
f57d151a UW |
451 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
452 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
453 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
454 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
455 | return ""; |
456 | ||
5e2e9765 KB |
457 | /* The MIPS integer registers are always mapped from 0 to 31. The |
458 | names of the registers (which reflects the conventions regarding | |
459 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 460 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
461 | { |
462 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 463 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 464 | else |
a4b8ebc8 | 465 | return mips_gpr_names[rawnum]; |
5e2e9765 | 466 | } |
d93859e2 UW |
467 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
468 | return tdesc_register_name (gdbarch, rawnum); | |
469 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
470 | { |
471 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
472 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
473 | } | |
5e2e9765 KB |
474 | else |
475 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 476 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 477 | } |
5e2e9765 | 478 | |
a4b8ebc8 | 479 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 480 | |
a4b8ebc8 AC |
481 | static int |
482 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
483 | struct reggroup *reggroup) | |
484 | { | |
485 | int vector_p; | |
486 | int float_p; | |
487 | int raw_p; | |
72a155b4 UW |
488 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
489 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
490 | if (reggroup == all_reggroup) |
491 | return pseudo; | |
492 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
493 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
494 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
495 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
496 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
497 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
498 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
499 | return 0; |
500 | if (reggroup == float_reggroup) | |
501 | return float_p && pseudo; | |
502 | if (reggroup == vector_reggroup) | |
503 | return vector_p && pseudo; | |
504 | if (reggroup == general_reggroup) | |
505 | return (!vector_p && !float_p) && pseudo; | |
506 | /* Save the pseudo registers. Need to make certain that any code | |
507 | extracting register values from a saved register cache also uses | |
508 | pseudo registers. */ | |
509 | if (reggroup == save_reggroup) | |
510 | return raw_p && pseudo; | |
511 | /* Restore the same pseudo register. */ | |
512 | if (reggroup == restore_reggroup) | |
513 | return raw_p && pseudo; | |
6d82d43b | 514 | return 0; |
a4b8ebc8 AC |
515 | } |
516 | ||
f8b73d13 DJ |
517 | /* Return the groups that a MIPS register can be categorised into. |
518 | This version is only used if we have a target description which | |
519 | describes real registers (and their groups). */ | |
520 | ||
521 | static int | |
522 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
523 | struct reggroup *reggroup) | |
524 | { | |
525 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
526 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
527 | int ret; | |
528 | ||
529 | /* Only save, restore, and display the pseudo registers. Need to | |
530 | make certain that any code extracting register values from a | |
531 | saved register cache also uses pseudo registers. | |
532 | ||
533 | Note: saving and restoring the pseudo registers is slightly | |
534 | strange; if we have 64 bits, we should save and restore all | |
535 | 64 bits. But this is hard and has little benefit. */ | |
536 | if (!pseudo) | |
537 | return 0; | |
538 | ||
539 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
540 | if (ret != -1) | |
541 | return ret; | |
542 | ||
543 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
544 | } | |
545 | ||
a4b8ebc8 | 546 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 547 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 548 | registers. Take care of alignment and size problems. */ |
c5aa993b | 549 | |
a4b8ebc8 AC |
550 | static void |
551 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 552 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 553 | { |
72a155b4 UW |
554 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
555 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
556 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 557 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 558 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
559 | else if (register_size (gdbarch, rawnum) > |
560 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
561 | { |
562 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 563 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
564 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
565 | else | |
566 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
567 | } | |
568 | else | |
e2e0b3e5 | 569 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
570 | } |
571 | ||
572 | static void | |
6d82d43b AC |
573 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
574 | struct regcache *regcache, int cookednum, | |
47a35522 | 575 | const gdb_byte *buf) |
a4b8ebc8 | 576 | { |
72a155b4 UW |
577 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
578 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
579 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 580 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 581 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
582 | else if (register_size (gdbarch, rawnum) > |
583 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
584 | { |
585 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
72a155b4 | 586 | || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
587 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
588 | else | |
589 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
590 | } | |
591 | else | |
e2e0b3e5 | 592 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 593 | } |
c5aa993b | 594 | |
c906108c | 595 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 596 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
597 | |
598 | /* Heuristic_proc_start may hunt through the text section for a long | |
599 | time across a 2400 baud serial line. Allows the user to limit this | |
600 | search. */ | |
601 | ||
602 | static unsigned int heuristic_fence_post = 0; | |
603 | ||
46cd78fb | 604 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
605 | register N. NOTE: This defines the pseudo register type so need to |
606 | rebuild the architecture vector. */ | |
43e526b9 JM |
607 | |
608 | static int mips64_transfers_32bit_regs_p = 0; | |
609 | ||
719ec221 AC |
610 | static void |
611 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
612 | struct cmd_list_element *c) | |
43e526b9 | 613 | { |
719ec221 AC |
614 | struct gdbarch_info info; |
615 | gdbarch_info_init (&info); | |
616 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
617 | instead of relying on globals. Doing that would let generic code | |
618 | handle the search for this specific architecture. */ | |
619 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 620 | { |
719ec221 | 621 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 622 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 623 | } |
a4b8ebc8 AC |
624 | } |
625 | ||
47ebcfbe | 626 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 627 | |
ff2e87ac | 628 | static int |
0abe36f5 | 629 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
ff2e87ac | 630 | { |
0abe36f5 MD |
631 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
632 | && register_size (gdbarch, regnum) == 4 | |
633 | && (regnum % gdbarch_num_regs (gdbarch)) | |
634 | >= mips_regnum (gdbarch)->fp0 | |
635 | && (regnum % gdbarch_num_regs (gdbarch)) | |
636 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 637 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
638 | } |
639 | ||
42c466d7 | 640 | static void |
ff2e87ac | 641 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 642 | struct type *type, gdb_byte *to) |
102182a9 | 643 | { |
47a35522 MK |
644 | get_frame_register (frame, regnum + 0, to + 4); |
645 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
646 | } |
647 | ||
42c466d7 | 648 | static void |
ff2e87ac | 649 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 650 | struct type *type, const gdb_byte *from) |
102182a9 | 651 | { |
47a35522 MK |
652 | put_frame_register (frame, regnum + 0, from + 4); |
653 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
654 | } |
655 | ||
a4b8ebc8 AC |
656 | /* Return the GDB type object for the "standard" data type of data in |
657 | register REG. */ | |
78fde5f8 KB |
658 | |
659 | static struct type * | |
a4b8ebc8 AC |
660 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
661 | { | |
72a155b4 UW |
662 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
663 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
664 | && (regnum % gdbarch_num_regs (gdbarch)) | |
665 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 666 | { |
5ef80fb0 | 667 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 668 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 669 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 670 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 671 | else |
27067745 | 672 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 673 | } |
72a155b4 | 674 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
675 | { |
676 | /* The raw or ISA registers. These are all sized according to | |
677 | the ISA regsize. */ | |
678 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 679 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 680 | else |
df4df182 | 681 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 682 | } |
78fde5f8 | 683 | else |
d5ac5a39 AC |
684 | { |
685 | /* The cooked or ABI registers. These are sized according to | |
686 | the ABI (with a few complications). */ | |
72a155b4 UW |
687 | if (regnum >= (gdbarch_num_regs (gdbarch) |
688 | + mips_regnum (gdbarch)->fp_control_status) | |
689 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
690 | /* The pseudo/cooked view of the embedded registers is always |
691 | 32-bit. The raw view is handled below. */ | |
df4df182 | 692 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
693 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
694 | /* The target, while possibly using a 64-bit register buffer, | |
695 | is only transfering 32-bits of each integer register. | |
696 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 697 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
698 | else if (mips_abi_regsize (gdbarch) == 4) |
699 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
700 | 32- or 64-bit). */ | |
df4df182 | 701 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
702 | else |
703 | /* 64-bit ABI. */ | |
df4df182 | 704 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 705 | } |
78fde5f8 KB |
706 | } |
707 | ||
f8b73d13 DJ |
708 | /* Return the GDB type for the pseudo register REGNUM, which is the |
709 | ABI-level view. This function is only called if there is a target | |
710 | description which includes registers, so we know precisely the | |
711 | types of hardware registers. */ | |
712 | ||
713 | static struct type * | |
714 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
715 | { | |
716 | const int num_regs = gdbarch_num_regs (gdbarch); | |
717 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
718 | int rawnum = regnum % num_regs; | |
719 | struct type *rawtype; | |
720 | ||
721 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
722 | ||
723 | /* Absent registers are still absent. */ | |
724 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
725 | if (TYPE_LENGTH (rawtype) == 0) | |
726 | return rawtype; | |
727 | ||
728 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
729 | /* Present the floating point registers however the hardware did; | |
730 | do not try to convert between FPU layouts. */ | |
731 | return rawtype; | |
732 | ||
733 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
734 | { | |
735 | /* The pseudo/cooked view of embedded registers is always | |
736 | 32-bit, even if the target transfers 64-bit values for them. | |
737 | New targets relying on XML descriptions should only transfer | |
738 | the necessary 32 bits, but older versions of GDB expected 64, | |
739 | so allow the target to provide 64 bits without interfering | |
740 | with the displayed type. */ | |
df4df182 | 741 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
742 | } |
743 | ||
744 | /* Use pointer types for registers if we can. For n32 we can not, | |
745 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
746 | if (mips_abi_regsize (gdbarch) |
747 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
748 | { |
749 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 750 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 751 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 752 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
753 | } |
754 | ||
755 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
756 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 757 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
758 | |
759 | /* For all other registers, pass through the hardware type. */ | |
760 | return rawtype; | |
761 | } | |
bcb0cc15 | 762 | |
c906108c | 763 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 764 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
765 | |
766 | static int | |
480d3dd2 | 767 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
768 | { |
769 | switch (mask_address_var) | |
770 | { | |
7f19b9a2 | 771 | case AUTO_BOOLEAN_TRUE: |
4014092b | 772 | return 1; |
7f19b9a2 | 773 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
774 | return 0; |
775 | break; | |
7f19b9a2 | 776 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 777 | return tdep->default_mask_address_p; |
4014092b | 778 | default: |
e2e0b3e5 | 779 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 780 | return -1; |
361d1df0 | 781 | } |
4014092b AC |
782 | } |
783 | ||
784 | static void | |
08546159 AC |
785 | show_mask_address (struct ui_file *file, int from_tty, |
786 | struct cmd_list_element *c, const char *value) | |
4014092b | 787 | { |
1cf3db46 | 788 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
789 | |
790 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
791 | switch (mask_address_var) |
792 | { | |
7f19b9a2 | 793 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
794 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
795 | break; | |
7f19b9a2 | 796 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
797 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
798 | break; | |
7f19b9a2 | 799 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
800 | printf_filtered |
801 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
802 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
803 | break; |
804 | default: | |
e2e0b3e5 | 805 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 806 | break; |
361d1df0 | 807 | } |
4014092b | 808 | } |
c906108c | 809 | |
c906108c SS |
810 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
811 | ||
0fe7e7c8 AC |
812 | int |
813 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
814 | { |
815 | struct minimal_symbol *sym; | |
816 | ||
817 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 818 | if (is_mips16_addr (memaddr)) |
c906108c SS |
819 | return 1; |
820 | ||
821 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
822 | the high bit of the info field. Use this to decide if the function is | |
823 | MIPS16 or normal MIPS. */ | |
824 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
825 | if (sym) | |
71b8ef93 | 826 | return msymbol_is_special (sym); |
c906108c SS |
827 | else |
828 | return 0; | |
829 | } | |
830 | ||
b2fa5097 | 831 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
832 | all registers should be sign extended for simplicity? */ |
833 | ||
834 | static CORE_ADDR | |
61a1198a | 835 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 836 | { |
61a1198a UW |
837 | ULONGEST pc; |
838 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
839 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
840 | return pc; | |
b6cb9035 AC |
841 | } |
842 | ||
58dfe9ff AC |
843 | static CORE_ADDR |
844 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
845 | { | |
72a155b4 UW |
846 | return frame_unwind_register_signed |
847 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
848 | } |
849 | ||
30244cd8 UW |
850 | static CORE_ADDR |
851 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
852 | { | |
72a155b4 UW |
853 | return frame_unwind_register_signed |
854 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
855 | } |
856 | ||
b8a22b94 | 857 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
858 | dummy frame. The frame ID's base needs to match the TOS value |
859 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
860 | breakpoint. */ | |
861 | ||
862 | static struct frame_id | |
b8a22b94 | 863 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 864 | { |
f57d151a | 865 | return frame_id_build |
b8a22b94 DJ |
866 | (get_frame_register_signed (this_frame, |
867 | gdbarch_num_regs (gdbarch) | |
868 | + MIPS_SP_REGNUM), | |
869 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
870 | } |
871 | ||
b6cb9035 | 872 | static void |
61a1198a | 873 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 874 | { |
61a1198a UW |
875 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
876 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 877 | } |
c906108c | 878 | |
c906108c SS |
879 | /* Fetch and return instruction from the specified location. If the PC |
880 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
881 | ||
d37cca3d | 882 | static ULONGEST |
acdb74a0 | 883 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 884 | { |
47a35522 | 885 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
886 | int instlen; |
887 | int status; | |
888 | ||
0fe7e7c8 | 889 | if (mips_pc_is_mips16 (addr)) |
c906108c | 890 | { |
95ac2dcf | 891 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 892 | addr = unmake_mips16_addr (addr); |
c906108c SS |
893 | } |
894 | else | |
95ac2dcf | 895 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 896 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
897 | if (status) |
898 | memory_error (status, addr); | |
899 | return extract_unsigned_integer (buf, instlen); | |
900 | } | |
901 | ||
c906108c | 902 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
903 | #define mips32_op(x) (x >> 26) |
904 | #define itype_op(x) (x >> 26) | |
905 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 906 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 907 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 908 | |
e135b889 DJ |
909 | #define jtype_op(x) (x >> 26) |
910 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 911 | |
e135b889 DJ |
912 | #define rtype_op(x) (x >> 26) |
913 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
914 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
915 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
916 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
917 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 918 | |
06987e64 MK |
919 | static LONGEST |
920 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 921 | { |
06987e64 | 922 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
923 | } |
924 | ||
f49e4e6d MS |
925 | /* Determine where to set a single step breakpoint while considering |
926 | branch prediction. */ | |
5a89d8aa | 927 | static CORE_ADDR |
0b1b3e42 | 928 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
929 | { |
930 | unsigned long inst; | |
931 | int op; | |
932 | inst = mips_fetch_instruction (pc); | |
e135b889 | 933 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 934 | { |
e135b889 | 935 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 936 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 937 | { |
e135b889 | 938 | op = (itype_op (inst) & 0x03); |
c906108c SS |
939 | switch (op) |
940 | { | |
e135b889 DJ |
941 | case 0: /* BEQL */ |
942 | goto equal_branch; | |
943 | case 1: /* BNEL */ | |
944 | goto neq_branch; | |
945 | case 2: /* BLEZL */ | |
946 | goto less_branch; | |
313628cc | 947 | case 3: /* BGTZL */ |
e135b889 | 948 | goto greater_branch; |
c5aa993b JM |
949 | default: |
950 | pc += 4; | |
c906108c SS |
951 | } |
952 | } | |
e135b889 | 953 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 954 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
955 | { |
956 | int tf = itype_rt (inst) & 0x01; | |
957 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 958 | int fcrcs = |
72a155b4 UW |
959 | get_frame_register_signed (frame, |
960 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 961 | fp_control_status); |
e135b889 DJ |
962 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
963 | ||
964 | if (((cond >> cnum) & 0x01) == tf) | |
965 | pc += mips32_relative_offset (inst) + 4; | |
966 | else | |
967 | pc += 8; | |
968 | } | |
c5aa993b JM |
969 | else |
970 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
971 | } |
972 | else | |
c5aa993b JM |
973 | { /* This gets way messy */ |
974 | ||
c906108c | 975 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 976 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 977 | { |
c5aa993b JM |
978 | case 0: /* SPECIAL */ |
979 | op = rtype_funct (inst); | |
980 | switch (op) | |
981 | { | |
982 | case 8: /* JR */ | |
983 | case 9: /* JALR */ | |
6c997a34 | 984 | /* Set PC to that address */ |
0b1b3e42 | 985 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 986 | break; |
e38d4e1a DJ |
987 | case 12: /* SYSCALL */ |
988 | { | |
989 | struct gdbarch_tdep *tdep; | |
990 | ||
991 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
992 | if (tdep->syscall_next_pc != NULL) | |
993 | pc = tdep->syscall_next_pc (frame); | |
994 | else | |
995 | pc += 4; | |
996 | } | |
997 | break; | |
c5aa993b JM |
998 | default: |
999 | pc += 4; | |
1000 | } | |
1001 | ||
6d82d43b | 1002 | break; /* end SPECIAL */ |
c5aa993b | 1003 | case 1: /* REGIMM */ |
c906108c | 1004 | { |
e135b889 DJ |
1005 | op = itype_rt (inst); /* branch condition */ |
1006 | switch (op) | |
c906108c | 1007 | { |
c5aa993b | 1008 | case 0: /* BLTZ */ |
e135b889 DJ |
1009 | case 2: /* BLTZL */ |
1010 | case 16: /* BLTZAL */ | |
c5aa993b | 1011 | case 18: /* BLTZALL */ |
c906108c | 1012 | less_branch: |
0b1b3e42 | 1013 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1014 | pc += mips32_relative_offset (inst) + 4; |
1015 | else | |
1016 | pc += 8; /* after the delay slot */ | |
1017 | break; | |
e135b889 | 1018 | case 1: /* BGEZ */ |
c5aa993b JM |
1019 | case 3: /* BGEZL */ |
1020 | case 17: /* BGEZAL */ | |
1021 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1022 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1023 | pc += mips32_relative_offset (inst) + 4; |
1024 | else | |
1025 | pc += 8; /* after the delay slot */ | |
1026 | break; | |
e135b889 | 1027 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1028 | default: |
1029 | pc += 4; | |
c906108c SS |
1030 | } |
1031 | } | |
6d82d43b | 1032 | break; /* end REGIMM */ |
c5aa993b JM |
1033 | case 2: /* J */ |
1034 | case 3: /* JAL */ | |
1035 | { | |
1036 | unsigned long reg; | |
1037 | reg = jtype_target (inst) << 2; | |
e135b889 | 1038 | /* Upper four bits get never changed... */ |
5b652102 | 1039 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1040 | } |
c5aa993b JM |
1041 | break; |
1042 | /* FIXME case JALX : */ | |
1043 | { | |
1044 | unsigned long reg; | |
1045 | reg = jtype_target (inst) << 2; | |
5b652102 | 1046 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1047 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1048 | } | |
c5aa993b | 1049 | break; /* The new PC will be alternate mode */ |
e135b889 | 1050 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1051 | equal_branch: |
0b1b3e42 UW |
1052 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1053 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1054 | pc += mips32_relative_offset (inst) + 4; |
1055 | else | |
1056 | pc += 8; | |
1057 | break; | |
e135b889 | 1058 | case 5: /* BNE, BNEL */ |
c5aa993b | 1059 | neq_branch: |
0b1b3e42 UW |
1060 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1061 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1062 | pc += mips32_relative_offset (inst) + 4; |
1063 | else | |
1064 | pc += 8; | |
1065 | break; | |
e135b889 | 1066 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1067 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1068 | pc += mips32_relative_offset (inst) + 4; |
1069 | else | |
1070 | pc += 8; | |
1071 | break; | |
1072 | case 7: | |
e135b889 DJ |
1073 | default: |
1074 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1075 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1076 | pc += mips32_relative_offset (inst) + 4; |
1077 | else | |
1078 | pc += 8; | |
1079 | break; | |
c5aa993b JM |
1080 | } /* switch */ |
1081 | } /* else */ | |
1082 | return pc; | |
1083 | } /* mips32_next_pc */ | |
c906108c SS |
1084 | |
1085 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1086 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1087 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1088 | We dont want to set a single step instruction on the extend instruction | |
1089 | either. | |
c5aa993b | 1090 | */ |
c906108c SS |
1091 | |
1092 | /* Lots of mips16 instruction formats */ | |
1093 | /* Predicting jumps requires itype,ritype,i8type | |
1094 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1095 | */ |
c906108c SS |
1096 | enum mips16_inst_fmts |
1097 | { | |
c5aa993b JM |
1098 | itype, /* 0 immediate 5,10 */ |
1099 | ritype, /* 1 5,3,8 */ | |
1100 | rrtype, /* 2 5,3,3,5 */ | |
1101 | rritype, /* 3 5,3,3,5 */ | |
1102 | rrrtype, /* 4 5,3,3,3,2 */ | |
1103 | rriatype, /* 5 5,3,3,1,4 */ | |
1104 | shifttype, /* 6 5,3,3,3,2 */ | |
1105 | i8type, /* 7 5,3,8 */ | |
1106 | i8movtype, /* 8 5,3,3,5 */ | |
1107 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1108 | i64type, /* 10 5,3,8 */ | |
1109 | ri64type, /* 11 5,3,3,5 */ | |
1110 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1111 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1112 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1113 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1114 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1115 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1116 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1117 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1118 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1119 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1120 | }; | |
12f02c2a AC |
1121 | /* I am heaping all the fields of the formats into one structure and |
1122 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1123 | struct upk_mips16 |
6d82d43b AC |
1124 | { |
1125 | CORE_ADDR offset; | |
1126 | unsigned int regx; /* Function in i8 type */ | |
1127 | unsigned int regy; | |
1128 | }; | |
c906108c SS |
1129 | |
1130 | ||
12f02c2a | 1131 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1132 | for the bits which make up the immediate extension. */ |
c906108c | 1133 | |
12f02c2a AC |
1134 | static CORE_ADDR |
1135 | extended_offset (unsigned int extension) | |
c906108c | 1136 | { |
12f02c2a | 1137 | CORE_ADDR value; |
c5aa993b JM |
1138 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1139 | value = value << 6; | |
1140 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1141 | value = value << 5; | |
1142 | value |= extension & 0x01f; /* extract 4:0 */ | |
1143 | return value; | |
c906108c SS |
1144 | } |
1145 | ||
1146 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1147 | instruction. It won't malfunction, but why make excess remote memory |
1148 | references? If the immediate operands get sign extended or something, | |
1149 | do it after the extension is performed. */ | |
c906108c | 1150 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1151 | when the offset is to be used in relative addressing. */ |
c906108c | 1152 | |
12f02c2a | 1153 | static unsigned int |
c5aa993b | 1154 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1155 | { |
47a35522 | 1156 | gdb_byte buf[8]; |
c5aa993b JM |
1157 | pc &= 0xfffffffe; /* clear the low order bit */ |
1158 | target_read_memory (pc, buf, 2); | |
1159 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1160 | } |
1161 | ||
1162 | static void | |
c5aa993b | 1163 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1164 | unsigned int extension, |
1165 | unsigned int inst, | |
6d82d43b | 1166 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1167 | { |
12f02c2a AC |
1168 | CORE_ADDR offset; |
1169 | int regx; | |
1170 | int regy; | |
1171 | switch (insn_format) | |
c906108c | 1172 | { |
c5aa993b | 1173 | case itype: |
c906108c | 1174 | { |
12f02c2a AC |
1175 | CORE_ADDR value; |
1176 | if (extension) | |
c5aa993b JM |
1177 | { |
1178 | value = extended_offset (extension); | |
1179 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1180 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1181 | } |
1182 | else | |
c5aa993b | 1183 | { |
12f02c2a | 1184 | value = inst & 0x7ff; |
c5aa993b | 1185 | /* FIXME : Consider sign extension */ |
c906108c | 1186 | } |
12f02c2a AC |
1187 | offset = value; |
1188 | regx = -1; | |
1189 | regy = -1; | |
c906108c | 1190 | } |
c5aa993b JM |
1191 | break; |
1192 | case ritype: | |
1193 | case i8type: | |
1194 | { /* A register identifier and an offset */ | |
c906108c SS |
1195 | /* Most of the fields are the same as I type but the |
1196 | immediate value is of a different length */ | |
12f02c2a AC |
1197 | CORE_ADDR value; |
1198 | if (extension) | |
c906108c | 1199 | { |
c5aa993b JM |
1200 | value = extended_offset (extension); |
1201 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1202 | value |= inst & 0xff; /* eleven bits from instruction */ |
1203 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1204 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1205 | { | |
1206 | value &= ~0x3fff; /* remove the sign bit */ | |
1207 | value = -value; | |
c906108c SS |
1208 | } |
1209 | } | |
c5aa993b JM |
1210 | else |
1211 | { | |
12f02c2a AC |
1212 | value = inst & 0xff; /* 8 bits */ |
1213 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1214 | /* FIXME: Do sign extension , this format needs it */ |
1215 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1216 | { | |
1217 | value &= 0xef; /* remove the sign bit */ | |
1218 | value = -value; | |
1219 | } | |
c5aa993b | 1220 | } |
12f02c2a AC |
1221 | offset = value; |
1222 | regy = -1; | |
c5aa993b | 1223 | break; |
c906108c | 1224 | } |
c5aa993b | 1225 | case jalxtype: |
c906108c | 1226 | { |
c5aa993b | 1227 | unsigned long value; |
12f02c2a AC |
1228 | unsigned int nexthalf; |
1229 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1230 | value = value << 16; |
1231 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1232 | value |= nexthalf; | |
12f02c2a AC |
1233 | offset = value; |
1234 | regx = -1; | |
1235 | regy = -1; | |
c5aa993b | 1236 | break; |
c906108c SS |
1237 | } |
1238 | default: | |
e2e0b3e5 | 1239 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1240 | } |
12f02c2a AC |
1241 | upk->offset = offset; |
1242 | upk->regx = regx; | |
1243 | upk->regy = regy; | |
c906108c SS |
1244 | } |
1245 | ||
1246 | ||
c5aa993b JM |
1247 | static CORE_ADDR |
1248 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1249 | { |
5b652102 | 1250 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1251 | } |
1252 | ||
12f02c2a | 1253 | static CORE_ADDR |
0b1b3e42 | 1254 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1255 | unsigned int extension, unsigned int insn) |
c906108c | 1256 | { |
12f02c2a AC |
1257 | int op = (insn >> 11); |
1258 | switch (op) | |
c906108c | 1259 | { |
6d82d43b | 1260 | case 2: /* Branch */ |
12f02c2a AC |
1261 | { |
1262 | CORE_ADDR offset; | |
1263 | struct upk_mips16 upk; | |
1264 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1265 | offset = upk.offset; | |
1266 | if (offset & 0x800) | |
1267 | { | |
1268 | offset &= 0xeff; | |
1269 | offset = -offset; | |
1270 | } | |
1271 | pc += (offset << 1) + 2; | |
1272 | break; | |
1273 | } | |
6d82d43b | 1274 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1275 | { |
1276 | struct upk_mips16 upk; | |
1277 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1278 | pc = add_offset_16 (pc, upk.offset); | |
1279 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1280 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1281 | else | |
1282 | pc |= 0x01; | |
1283 | break; | |
1284 | } | |
6d82d43b | 1285 | case 4: /* beqz */ |
12f02c2a AC |
1286 | { |
1287 | struct upk_mips16 upk; | |
1288 | int reg; | |
1289 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1290 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1291 | if (reg == 0) |
1292 | pc += (upk.offset << 1) + 2; | |
1293 | else | |
1294 | pc += 2; | |
1295 | break; | |
1296 | } | |
6d82d43b | 1297 | case 5: /* bnez */ |
12f02c2a AC |
1298 | { |
1299 | struct upk_mips16 upk; | |
1300 | int reg; | |
1301 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1302 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1303 | if (reg != 0) |
1304 | pc += (upk.offset << 1) + 2; | |
1305 | else | |
1306 | pc += 2; | |
1307 | break; | |
1308 | } | |
6d82d43b | 1309 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1310 | { |
1311 | struct upk_mips16 upk; | |
1312 | int reg; | |
1313 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1314 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1315 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1316 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1317 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1318 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1319 | pc += (upk.offset << 1) + 2; | |
1320 | else | |
1321 | pc += 2; | |
1322 | break; | |
1323 | } | |
6d82d43b | 1324 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1325 | { |
1326 | struct upk_mips16 upk; | |
1327 | /* upk.fmt = rrtype; */ | |
1328 | op = insn & 0x1f; | |
1329 | if (op == 0) | |
c5aa993b | 1330 | { |
12f02c2a AC |
1331 | int reg; |
1332 | upk.regx = (insn >> 8) & 0x07; | |
1333 | upk.regy = (insn >> 5) & 0x07; | |
1334 | switch (upk.regy) | |
c5aa993b | 1335 | { |
12f02c2a AC |
1336 | case 0: |
1337 | reg = upk.regx; | |
1338 | break; | |
1339 | case 1: | |
1340 | reg = 31; | |
6d82d43b | 1341 | break; /* Function return instruction */ |
12f02c2a AC |
1342 | case 2: |
1343 | reg = upk.regx; | |
1344 | break; | |
1345 | default: | |
1346 | reg = 31; | |
6d82d43b | 1347 | break; /* BOGUS Guess */ |
c906108c | 1348 | } |
0b1b3e42 | 1349 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1350 | } |
12f02c2a | 1351 | else |
c5aa993b | 1352 | pc += 2; |
12f02c2a AC |
1353 | break; |
1354 | } | |
1355 | case 30: | |
1356 | /* This is an instruction extension. Fetch the real instruction | |
1357 | (which follows the extension) and decode things based on | |
1358 | that. */ | |
1359 | { | |
1360 | pc += 2; | |
0b1b3e42 | 1361 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1362 | break; |
1363 | } | |
1364 | default: | |
1365 | { | |
1366 | pc += 2; | |
1367 | break; | |
1368 | } | |
c906108c | 1369 | } |
c5aa993b | 1370 | return pc; |
12f02c2a | 1371 | } |
c906108c | 1372 | |
5a89d8aa | 1373 | static CORE_ADDR |
0b1b3e42 | 1374 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1375 | { |
1376 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1377 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1378 | } |
1379 | ||
1380 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1381 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1382 | It works by decoding the current instruction and predicting where a |
1383 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1384 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1385 | static CORE_ADDR |
0b1b3e42 | 1386 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1387 | { |
ce1f96de | 1388 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1389 | return mips16_next_pc (frame, pc); |
c5aa993b | 1390 | else |
0b1b3e42 | 1391 | return mips32_next_pc (frame, pc); |
12f02c2a | 1392 | } |
c906108c | 1393 | |
edfae063 AC |
1394 | struct mips_frame_cache |
1395 | { | |
1396 | CORE_ADDR base; | |
1397 | struct trad_frame_saved_reg *saved_regs; | |
1398 | }; | |
1399 | ||
29639122 JB |
1400 | /* Set a register's saved stack address in temp_saved_regs. If an |
1401 | address has already been set for this register, do nothing; this | |
1402 | way we will only recognize the first save of a given register in a | |
1403 | function prologue. | |
eec63939 | 1404 | |
f57d151a UW |
1405 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1406 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1407 | Strictly speaking, only the second range is used as it is only second | |
1408 | range (the ABI instead of ISA registers) that comes into play when finding | |
1409 | saved registers in a frame. */ | |
eec63939 AC |
1410 | |
1411 | static void | |
74ed0bb4 MD |
1412 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1413 | int regnum, CORE_ADDR offset) | |
eec63939 | 1414 | { |
29639122 JB |
1415 | if (this_cache != NULL |
1416 | && this_cache->saved_regs[regnum].addr == -1) | |
1417 | { | |
74ed0bb4 MD |
1418 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1419 | = offset; | |
1420 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1421 | = offset; | |
29639122 | 1422 | } |
eec63939 AC |
1423 | } |
1424 | ||
eec63939 | 1425 | |
29639122 JB |
1426 | /* Fetch the immediate value from a MIPS16 instruction. |
1427 | If the previous instruction was an EXTEND, use it to extend | |
1428 | the upper bits of the immediate value. This is a helper function | |
1429 | for mips16_scan_prologue. */ | |
eec63939 | 1430 | |
29639122 JB |
1431 | static int |
1432 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1433 | unsigned short inst, /* current instruction */ | |
1434 | int nbits, /* number of bits in imm field */ | |
1435 | int scale, /* scale factor to be applied to imm */ | |
1436 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1437 | { |
29639122 | 1438 | int offset; |
eec63939 | 1439 | |
29639122 JB |
1440 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1441 | { | |
1442 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1443 | if (offset & 0x8000) /* check for negative extend */ | |
1444 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1445 | return offset | (inst & 0x1f); | |
1446 | } | |
eec63939 | 1447 | else |
29639122 JB |
1448 | { |
1449 | int max_imm = 1 << nbits; | |
1450 | int mask = max_imm - 1; | |
1451 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1452 | |
29639122 JB |
1453 | offset = inst & mask; |
1454 | if (is_signed && (offset & sign_bit)) | |
1455 | offset = 0 - (max_imm - offset); | |
1456 | return offset * scale; | |
1457 | } | |
1458 | } | |
eec63939 | 1459 | |
65596487 | 1460 | |
29639122 JB |
1461 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1462 | the associated FRAME_CACHE if not null. | |
1463 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1464 | |
29639122 JB |
1465 | static CORE_ADDR |
1466 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1467 | struct frame_info *this_frame, |
29639122 JB |
1468 | struct mips_frame_cache *this_cache) |
1469 | { | |
1470 | CORE_ADDR cur_pc; | |
1471 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1472 | CORE_ADDR sp; | |
1473 | long frame_offset = 0; /* Size of stack frame. */ | |
1474 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1475 | int frame_reg = MIPS_SP_REGNUM; | |
1476 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1477 | unsigned inst = 0; /* current instruction */ | |
1478 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1479 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1480 | int reg, offset; |
a343eb3c | 1481 | |
29639122 JB |
1482 | int extend_bytes = 0; |
1483 | int prev_extend_bytes; | |
1484 | CORE_ADDR end_prologue_addr = 0; | |
b8a22b94 | 1485 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
a343eb3c | 1486 | |
29639122 | 1487 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1488 | THIS_FRAME. */ |
1489 | if (this_frame != NULL) | |
1490 | sp = get_frame_register_signed (this_frame, | |
1491 | gdbarch_num_regs (gdbarch) | |
1492 | + MIPS_SP_REGNUM); | |
29639122 JB |
1493 | else |
1494 | sp = 0; | |
eec63939 | 1495 | |
29639122 JB |
1496 | if (limit_pc > start_pc + 200) |
1497 | limit_pc = start_pc + 200; | |
eec63939 | 1498 | |
95ac2dcf | 1499 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1500 | { |
1501 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1502 | the immediate offset extension from it in mips16_get_imm. */ | |
1503 | prev_inst = inst; | |
eec63939 | 1504 | |
29639122 JB |
1505 | /* Fetch and decode the instruction. */ |
1506 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1507 | |
29639122 JB |
1508 | /* Normally we ignore extend instructions. However, if it is |
1509 | not followed by a valid prologue instruction, then this | |
1510 | instruction is not part of the prologue either. We must | |
1511 | remember in this case to adjust the end_prologue_addr back | |
1512 | over the extend. */ | |
1513 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1514 | { | |
95ac2dcf | 1515 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1516 | continue; |
1517 | } | |
eec63939 | 1518 | |
29639122 JB |
1519 | prev_extend_bytes = extend_bytes; |
1520 | extend_bytes = 0; | |
eec63939 | 1521 | |
29639122 JB |
1522 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1523 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1524 | { | |
1525 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1526 | if (offset < 0) /* negative stack adjustment? */ | |
1527 | frame_offset -= offset; | |
1528 | else | |
1529 | /* Exit loop if a positive stack adjustment is found, which | |
1530 | usually means that the stack cleanup code in the function | |
1531 | epilogue is reached. */ | |
1532 | break; | |
1533 | } | |
1534 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1535 | { | |
1536 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1537 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1538 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1539 | } |
1540 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1541 | { | |
1542 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1543 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1544 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1545 | } |
1546 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1547 | { | |
1548 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1549 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1550 | } |
1551 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1552 | { | |
1553 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1554 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1555 | } |
1556 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1557 | { | |
1558 | frame_addr = sp; | |
1559 | frame_reg = 17; | |
1560 | } | |
1561 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1562 | { | |
1563 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1564 | frame_addr = sp + offset; | |
1565 | frame_reg = 17; | |
1566 | frame_adjust = offset; | |
1567 | } | |
1568 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1569 | { | |
1570 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1571 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1572 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1573 | } |
1574 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1575 | { | |
1576 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1577 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1578 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1579 | } |
1580 | else if ((inst & 0xf81f) == 0xe809 | |
1581 | && (inst & 0x700) != 0x700) /* entry */ | |
1582 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1583 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1584 | { | |
1585 | save_inst = inst; /* save for later processing */ | |
1586 | if (prev_extend_bytes) /* extend */ | |
1587 | save_inst |= prev_inst << 16; | |
1588 | } | |
29639122 | 1589 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1590 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1591 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1592 | { | |
1593 | /* This instruction is part of the prologue, but we don't | |
1594 | need to do anything special to handle it. */ | |
1595 | } | |
1596 | else | |
1597 | { | |
1598 | /* This instruction is not an instruction typically found | |
1599 | in a prologue, so we must have reached the end of the | |
1600 | prologue. */ | |
1601 | if (end_prologue_addr == 0) | |
1602 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1603 | } | |
1604 | } | |
eec63939 | 1605 | |
29639122 JB |
1606 | /* The entry instruction is typically the first instruction in a function, |
1607 | and it stores registers at offsets relative to the value of the old SP | |
1608 | (before the prologue). But the value of the sp parameter to this | |
1609 | function is the new SP (after the prologue has been executed). So we | |
1610 | can't calculate those offsets until we've seen the entire prologue, | |
1611 | and can calculate what the old SP must have been. */ | |
1612 | if (entry_inst != 0) | |
1613 | { | |
1614 | int areg_count = (entry_inst >> 8) & 7; | |
1615 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1616 | |
29639122 JB |
1617 | /* The entry instruction always subtracts 32 from the SP. */ |
1618 | frame_offset += 32; | |
1619 | ||
1620 | /* Now we can calculate what the SP must have been at the | |
1621 | start of the function prologue. */ | |
1622 | sp += frame_offset; | |
1623 | ||
1624 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1625 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1626 | { | |
74ed0bb4 | 1627 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1628 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1629 | } |
1630 | ||
1631 | /* Check if the ra register was pushed on the stack. */ | |
1632 | offset = -4; | |
1633 | if (entry_inst & 0x20) | |
1634 | { | |
74ed0bb4 | 1635 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1636 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1637 | } |
1638 | ||
1639 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1640 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1641 | { | |
74ed0bb4 | 1642 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1643 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1644 | } |
1645 | } | |
1646 | ||
2207132d MR |
1647 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1648 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1649 | size of the frame is specified as an immediate field of instruction | |
1650 | and an extended variation exists which lets additional registers and | |
1651 | frame space to be specified. The instruction always treats registers | |
1652 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1653 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1654 | { | |
1655 | static int args_table[16] = { | |
1656 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1657 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1658 | }; | |
1659 | static int astatic_table[16] = { | |
1660 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1661 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1662 | }; | |
1663 | int aregs = (save_inst >> 16) & 0xf; | |
1664 | int xsregs = (save_inst >> 24) & 0x7; | |
1665 | int args = args_table[aregs]; | |
1666 | int astatic = astatic_table[aregs]; | |
1667 | long frame_size; | |
1668 | ||
1669 | if (args < 0) | |
1670 | { | |
1671 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1672 | args = 0; | |
1673 | } | |
1674 | if (astatic < 0) | |
1675 | { | |
1676 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1677 | astatic = 0; | |
1678 | } | |
1679 | ||
1680 | /* For standard SAVE the frame size of 0 means 128. */ | |
1681 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1682 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1683 | frame_size = 16; | |
1684 | frame_size *= 8; | |
1685 | frame_offset += frame_size; | |
1686 | ||
1687 | /* Now we can calculate what the SP must have been at the | |
1688 | start of the function prologue. */ | |
1689 | sp += frame_offset; | |
1690 | ||
1691 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1692 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1693 | { | |
74ed0bb4 | 1694 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1695 | offset += mips_abi_regsize (gdbarch); |
1696 | } | |
1697 | ||
1698 | offset = -4; | |
1699 | ||
1700 | /* Check if the RA register was pushed on the stack. */ | |
1701 | if (save_inst & 0x40) | |
1702 | { | |
74ed0bb4 | 1703 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1704 | offset -= mips_abi_regsize (gdbarch); |
1705 | } | |
1706 | ||
1707 | /* Check if the S8 register was pushed on the stack. */ | |
1708 | if (xsregs > 6) | |
1709 | { | |
74ed0bb4 | 1710 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1711 | offset -= mips_abi_regsize (gdbarch); |
1712 | xsregs--; | |
1713 | } | |
1714 | /* Check if S2-S7 were pushed on the stack. */ | |
1715 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1716 | { | |
74ed0bb4 | 1717 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1718 | offset -= mips_abi_regsize (gdbarch); |
1719 | } | |
1720 | ||
1721 | /* Check if the S1 register was pushed on the stack. */ | |
1722 | if (save_inst & 0x10) | |
1723 | { | |
74ed0bb4 | 1724 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1725 | offset -= mips_abi_regsize (gdbarch); |
1726 | } | |
1727 | /* Check if the S0 register was pushed on the stack. */ | |
1728 | if (save_inst & 0x20) | |
1729 | { | |
74ed0bb4 | 1730 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1731 | offset -= mips_abi_regsize (gdbarch); |
1732 | } | |
1733 | ||
1734 | /* Check if A0-A3 were pushed on the stack. */ | |
1735 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1736 | { | |
74ed0bb4 | 1737 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1738 | offset -= mips_abi_regsize (gdbarch); |
1739 | } | |
1740 | } | |
1741 | ||
29639122 JB |
1742 | if (this_cache != NULL) |
1743 | { | |
1744 | this_cache->base = | |
b8a22b94 DJ |
1745 | (get_frame_register_signed (this_frame, |
1746 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1747 | + frame_offset - frame_adjust); |
1748 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1749 | be able to get rid of the assignment below, evetually. But it's | |
1750 | still needed for now. */ | |
72a155b4 UW |
1751 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1752 | + mips_regnum (gdbarch)->pc] | |
1753 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1754 | } |
1755 | ||
1756 | /* If we didn't reach the end of the prologue when scanning the function | |
1757 | instructions, then set end_prologue_addr to the address of the | |
1758 | instruction immediately after the last one we scanned. */ | |
1759 | if (end_prologue_addr == 0) | |
1760 | end_prologue_addr = cur_pc; | |
1761 | ||
1762 | return end_prologue_addr; | |
eec63939 AC |
1763 | } |
1764 | ||
29639122 JB |
1765 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1766 | Procedures that use the 32-bit instruction set are handled by the | |
1767 | mips_insn32 unwinder. */ | |
1768 | ||
1769 | static struct mips_frame_cache * | |
b8a22b94 | 1770 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1771 | { |
29639122 | 1772 | struct mips_frame_cache *cache; |
eec63939 AC |
1773 | |
1774 | if ((*this_cache) != NULL) | |
1775 | return (*this_cache); | |
29639122 JB |
1776 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1777 | (*this_cache) = cache; | |
b8a22b94 | 1778 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1779 | |
29639122 JB |
1780 | /* Analyze the function prologue. */ |
1781 | { | |
b8a22b94 | 1782 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1783 | CORE_ADDR start_addr; |
eec63939 | 1784 | |
29639122 JB |
1785 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1786 | if (start_addr == 0) | |
74ed0bb4 | 1787 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
1788 | /* We can't analyze the prologue if we couldn't find the begining |
1789 | of the function. */ | |
1790 | if (start_addr == 0) | |
1791 | return cache; | |
eec63939 | 1792 | |
b8a22b94 | 1793 | mips16_scan_prologue (start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1794 | } |
1795 | ||
3e8c568d | 1796 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1797 | trad_frame_set_value (cache->saved_regs, |
b8a22b94 DJ |
1798 | gdbarch_num_regs (get_frame_arch (this_frame)) |
1799 | + MIPS_SP_REGNUM, | |
72a155b4 | 1800 | cache->base); |
eec63939 | 1801 | |
29639122 | 1802 | return (*this_cache); |
eec63939 AC |
1803 | } |
1804 | ||
1805 | static void | |
b8a22b94 | 1806 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1807 | struct frame_id *this_id) |
eec63939 | 1808 | { |
b8a22b94 | 1809 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1810 | this_cache); |
b8a22b94 | 1811 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1812 | } |
1813 | ||
b8a22b94 DJ |
1814 | static struct value * |
1815 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1816 | void **this_cache, int regnum) | |
eec63939 | 1817 | { |
b8a22b94 | 1818 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1819 | this_cache); |
b8a22b94 DJ |
1820 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1821 | } | |
1822 | ||
1823 | static int | |
1824 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1825 | struct frame_info *this_frame, void **this_cache) | |
1826 | { | |
1827 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1828 | if (mips_pc_is_mips16 (pc)) | |
1829 | return 1; | |
1830 | return 0; | |
eec63939 AC |
1831 | } |
1832 | ||
29639122 | 1833 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1834 | { |
1835 | NORMAL_FRAME, | |
29639122 | 1836 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1837 | mips_insn16_frame_prev_register, |
1838 | NULL, | |
1839 | mips_insn16_frame_sniffer | |
eec63939 AC |
1840 | }; |
1841 | ||
eec63939 | 1842 | static CORE_ADDR |
b8a22b94 | 1843 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1844 | void **this_cache) |
eec63939 | 1845 | { |
b8a22b94 | 1846 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1847 | this_cache); |
1848 | return info->base; | |
eec63939 AC |
1849 | } |
1850 | ||
29639122 | 1851 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1852 | { |
29639122 JB |
1853 | &mips_insn16_frame_unwind, |
1854 | mips_insn16_frame_base_address, | |
1855 | mips_insn16_frame_base_address, | |
1856 | mips_insn16_frame_base_address | |
eec63939 AC |
1857 | }; |
1858 | ||
1859 | static const struct frame_base * | |
b8a22b94 | 1860 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1861 | { |
b8a22b94 DJ |
1862 | CORE_ADDR pc = get_frame_pc (this_frame); |
1863 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1864 | return &mips_insn16_frame_base; |
eec63939 AC |
1865 | else |
1866 | return NULL; | |
edfae063 AC |
1867 | } |
1868 | ||
29639122 JB |
1869 | /* Mark all the registers as unset in the saved_regs array |
1870 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1871 | ||
74ed0bb4 MD |
1872 | static void |
1873 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 1874 | { |
29639122 JB |
1875 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1876 | return; | |
1877 | ||
1878 | { | |
74ed0bb4 | 1879 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 1880 | int i; |
64159455 | 1881 | |
29639122 JB |
1882 | for (i = 0; i < num_regs; i++) |
1883 | { | |
1884 | this_cache->saved_regs[i].addr = -1; | |
1885 | } | |
1886 | } | |
c906108c SS |
1887 | } |
1888 | ||
29639122 JB |
1889 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1890 | the associated FRAME_CACHE if not null. | |
1891 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1892 | |
875e1767 | 1893 | static CORE_ADDR |
29639122 | 1894 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
b8a22b94 | 1895 | struct frame_info *this_frame, |
29639122 | 1896 | struct mips_frame_cache *this_cache) |
c906108c | 1897 | { |
29639122 JB |
1898 | CORE_ADDR cur_pc; |
1899 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1900 | CORE_ADDR sp; | |
1901 | long frame_offset; | |
1902 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1903 | |
29639122 JB |
1904 | CORE_ADDR end_prologue_addr = 0; |
1905 | int seen_sp_adjust = 0; | |
1906 | int load_immediate_bytes = 0; | |
db5f024e | 1907 | int in_delay_slot = 0; |
b8a22b94 | 1908 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
7d1e6fb8 | 1909 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 1910 | |
29639122 | 1911 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1912 | THIS_FRAME. */ |
1913 | if (this_frame != NULL) | |
1914 | sp = get_frame_register_signed (this_frame, | |
1915 | gdbarch_num_regs (gdbarch) | |
1916 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1917 | else |
29639122 | 1918 | sp = 0; |
9022177c | 1919 | |
29639122 JB |
1920 | if (limit_pc > start_pc + 200) |
1921 | limit_pc = start_pc + 200; | |
9022177c | 1922 | |
29639122 | 1923 | restart: |
9022177c | 1924 | |
29639122 | 1925 | frame_offset = 0; |
95ac2dcf | 1926 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1927 | { |
29639122 JB |
1928 | unsigned long inst, high_word, low_word; |
1929 | int reg; | |
9022177c | 1930 | |
29639122 JB |
1931 | /* Fetch the instruction. */ |
1932 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1933 | |
29639122 JB |
1934 | /* Save some code by pre-extracting some useful fields. */ |
1935 | high_word = (inst >> 16) & 0xffff; | |
1936 | low_word = inst & 0xffff; | |
1937 | reg = high_word & 0x1f; | |
fe29b929 | 1938 | |
29639122 JB |
1939 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1940 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1941 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1942 | { | |
1943 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1944 | frame_offset += 0x10000 - low_word; | |
1945 | else | |
1946 | /* Exit loop if a positive stack adjustment is found, which | |
1947 | usually means that the stack cleanup code in the function | |
1948 | epilogue is reached. */ | |
1949 | break; | |
1950 | seen_sp_adjust = 1; | |
1951 | } | |
7d1e6fb8 KB |
1952 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
1953 | && !regsize_is_64_bits) | |
29639122 | 1954 | { |
74ed0bb4 | 1955 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 1956 | } |
7d1e6fb8 KB |
1957 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
1958 | && regsize_is_64_bits) | |
29639122 JB |
1959 | { |
1960 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 1961 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
1962 | } |
1963 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1964 | { | |
1965 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1966 | if ((long) low_word != frame_offset) | |
1967 | frame_addr = sp + low_word; | |
b8a22b94 | 1968 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1969 | { |
1970 | unsigned alloca_adjust; | |
a4b8ebc8 | 1971 | |
29639122 | 1972 | frame_reg = 30; |
b8a22b94 DJ |
1973 | frame_addr = get_frame_register_signed |
1974 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1975 | |
29639122 JB |
1976 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1977 | if (alloca_adjust > 0) | |
1978 | { | |
1979 | /* FP > SP + frame_size. This may be because of | |
1980 | an alloca or somethings similar. Fix sp to | |
1981 | "pre-alloca" value, and try again. */ | |
1982 | sp += alloca_adjust; | |
1983 | /* Need to reset the status of all registers. Otherwise, | |
1984 | we will hit a guard that prevents the new address | |
1985 | for each register to be recomputed during the second | |
1986 | pass. */ | |
74ed0bb4 | 1987 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
1988 | goto restart; |
1989 | } | |
1990 | } | |
1991 | } | |
1992 | /* move $30,$sp. With different versions of gas this will be either | |
1993 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1994 | Accept any one of these. */ | |
1995 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1996 | { | |
1997 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 1998 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1999 | { |
2000 | unsigned alloca_adjust; | |
c906108c | 2001 | |
29639122 | 2002 | frame_reg = 30; |
b8a22b94 DJ |
2003 | frame_addr = get_frame_register_signed |
2004 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2005 | |
29639122 JB |
2006 | alloca_adjust = (unsigned) (frame_addr - sp); |
2007 | if (alloca_adjust > 0) | |
2008 | { | |
2009 | /* FP > SP + frame_size. This may be because of | |
2010 | an alloca or somethings similar. Fix sp to | |
2011 | "pre-alloca" value, and try again. */ | |
2012 | sp = frame_addr; | |
2013 | /* Need to reset the status of all registers. Otherwise, | |
2014 | we will hit a guard that prevents the new address | |
2015 | for each register to be recomputed during the second | |
2016 | pass. */ | |
74ed0bb4 | 2017 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2018 | goto restart; |
2019 | } | |
2020 | } | |
2021 | } | |
7d1e6fb8 KB |
2022 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2023 | && !regsize_is_64_bits) | |
29639122 | 2024 | { |
74ed0bb4 | 2025 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2026 | } |
2027 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2028 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2029 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2030 | || high_word == 0x3c1c /* lui $gp,n */ | |
2031 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2032 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2033 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2034 | ) | |
2035 | { | |
2036 | /* These instructions are part of the prologue, but we don't | |
2037 | need to do anything special to handle them. */ | |
2038 | } | |
2039 | /* The instructions below load $at or $t0 with an immediate | |
2040 | value in preparation for a stack adjustment via | |
2041 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2042 | initialize a local variable, so we accept them only before | |
2043 | a stack adjustment instruction was seen. */ | |
2044 | else if (!seen_sp_adjust | |
2045 | && (high_word == 0x3c01 /* lui $at,n */ | |
2046 | || high_word == 0x3c08 /* lui $t0,n */ | |
2047 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2048 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2049 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2050 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2051 | )) | |
2052 | { | |
95ac2dcf | 2053 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2054 | } |
2055 | else | |
2056 | { | |
2057 | /* This instruction is not an instruction typically found | |
2058 | in a prologue, so we must have reached the end of the | |
2059 | prologue. */ | |
2060 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2061 | loop now? Why would we need to continue scanning the function | |
2062 | instructions? */ | |
2063 | if (end_prologue_addr == 0) | |
2064 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2065 | |
2066 | /* Check for branches and jumps. For now, only jump to | |
2067 | register are caught (i.e. returns). */ | |
2068 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2069 | in_delay_slot = 1; | |
29639122 | 2070 | } |
db5f024e DJ |
2071 | |
2072 | /* If the previous instruction was a jump, we must have reached | |
2073 | the end of the prologue by now. Stop scanning so that we do | |
2074 | not go past the function return. */ | |
2075 | if (in_delay_slot) | |
2076 | break; | |
a4b8ebc8 | 2077 | } |
c906108c | 2078 | |
29639122 JB |
2079 | if (this_cache != NULL) |
2080 | { | |
2081 | this_cache->base = | |
b8a22b94 DJ |
2082 | (get_frame_register_signed (this_frame, |
2083 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2084 | + frame_offset); |
2085 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2086 | this assignment below, eventually. But it's still needed | |
2087 | for now. */ | |
72a155b4 UW |
2088 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2089 | + mips_regnum (gdbarch)->pc] | |
2090 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2091 | + MIPS_RA_REGNUM]; |
29639122 | 2092 | } |
c906108c | 2093 | |
29639122 JB |
2094 | /* If we didn't reach the end of the prologue when scanning the function |
2095 | instructions, then set end_prologue_addr to the address of the | |
2096 | instruction immediately after the last one we scanned. */ | |
2097 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2098 | we may as well be careful and do our best if we have a null | |
2099 | end_prologue_addr. */ | |
2100 | if (end_prologue_addr == 0) | |
2101 | end_prologue_addr = cur_pc; | |
2102 | ||
2103 | /* In a frameless function, we might have incorrectly | |
2104 | skipped some load immediate instructions. Undo the skipping | |
2105 | if the load immediate was not followed by a stack adjustment. */ | |
2106 | if (load_immediate_bytes && !seen_sp_adjust) | |
2107 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2108 | |
29639122 | 2109 | return end_prologue_addr; |
c906108c SS |
2110 | } |
2111 | ||
29639122 JB |
2112 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2113 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2114 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2115 | unwinder. */ | |
c906108c | 2116 | |
29639122 | 2117 | static struct mips_frame_cache * |
b8a22b94 | 2118 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2119 | { |
29639122 | 2120 | struct mips_frame_cache *cache; |
c906108c | 2121 | |
29639122 JB |
2122 | if ((*this_cache) != NULL) |
2123 | return (*this_cache); | |
c5aa993b | 2124 | |
29639122 JB |
2125 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2126 | (*this_cache) = cache; | |
b8a22b94 | 2127 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2128 | |
29639122 JB |
2129 | /* Analyze the function prologue. */ |
2130 | { | |
b8a22b94 | 2131 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2132 | CORE_ADDR start_addr; |
c906108c | 2133 | |
29639122 JB |
2134 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2135 | if (start_addr == 0) | |
74ed0bb4 | 2136 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
2137 | /* We can't analyze the prologue if we couldn't find the begining |
2138 | of the function. */ | |
2139 | if (start_addr == 0) | |
2140 | return cache; | |
c5aa993b | 2141 | |
b8a22b94 | 2142 | mips32_scan_prologue (start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2143 | } |
2144 | ||
3e8c568d | 2145 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2146 | trad_frame_set_value (cache->saved_regs, |
b8a22b94 DJ |
2147 | gdbarch_num_regs (get_frame_arch (this_frame)) |
2148 | + MIPS_SP_REGNUM, | |
f57d151a | 2149 | cache->base); |
c5aa993b | 2150 | |
29639122 | 2151 | return (*this_cache); |
c906108c SS |
2152 | } |
2153 | ||
29639122 | 2154 | static void |
b8a22b94 | 2155 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2156 | struct frame_id *this_id) |
c906108c | 2157 | { |
b8a22b94 | 2158 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2159 | this_cache); |
b8a22b94 | 2160 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2161 | } |
c906108c | 2162 | |
b8a22b94 DJ |
2163 | static struct value * |
2164 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2165 | void **this_cache, int regnum) | |
29639122 | 2166 | { |
b8a22b94 | 2167 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2168 | this_cache); |
b8a22b94 DJ |
2169 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2170 | } | |
2171 | ||
2172 | static int | |
2173 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2174 | struct frame_info *this_frame, void **this_cache) | |
2175 | { | |
2176 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2177 | if (! mips_pc_is_mips16 (pc)) | |
2178 | return 1; | |
2179 | return 0; | |
c906108c SS |
2180 | } |
2181 | ||
29639122 JB |
2182 | static const struct frame_unwind mips_insn32_frame_unwind = |
2183 | { | |
2184 | NORMAL_FRAME, | |
2185 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2186 | mips_insn32_frame_prev_register, |
2187 | NULL, | |
2188 | mips_insn32_frame_sniffer | |
29639122 | 2189 | }; |
c906108c | 2190 | |
1c645fec | 2191 | static CORE_ADDR |
b8a22b94 | 2192 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2193 | void **this_cache) |
c906108c | 2194 | { |
b8a22b94 | 2195 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2196 | this_cache); |
2197 | return info->base; | |
2198 | } | |
c906108c | 2199 | |
29639122 JB |
2200 | static const struct frame_base mips_insn32_frame_base = |
2201 | { | |
2202 | &mips_insn32_frame_unwind, | |
2203 | mips_insn32_frame_base_address, | |
2204 | mips_insn32_frame_base_address, | |
2205 | mips_insn32_frame_base_address | |
2206 | }; | |
1c645fec | 2207 | |
29639122 | 2208 | static const struct frame_base * |
b8a22b94 | 2209 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2210 | { |
b8a22b94 DJ |
2211 | CORE_ADDR pc = get_frame_pc (this_frame); |
2212 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2213 | return &mips_insn32_frame_base; |
a65bbe44 | 2214 | else |
29639122 JB |
2215 | return NULL; |
2216 | } | |
a65bbe44 | 2217 | |
29639122 | 2218 | static struct trad_frame_cache * |
b8a22b94 | 2219 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2220 | { |
2221 | CORE_ADDR pc; | |
2222 | CORE_ADDR start_addr; | |
2223 | CORE_ADDR stack_addr; | |
2224 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2225 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2226 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2227 | |
29639122 JB |
2228 | if ((*this_cache) != NULL) |
2229 | return (*this_cache); | |
b8a22b94 | 2230 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2231 | (*this_cache) = this_trad_cache; |
1c645fec | 2232 | |
29639122 | 2233 | /* The return address is in the link register. */ |
3e8c568d | 2234 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2235 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2236 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2237 | |
29639122 JB |
2238 | /* Frame ID, since it's a frameless / stackless function, no stack |
2239 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2240 | pc = get_frame_pc (this_frame); |
29639122 | 2241 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2242 | stack_addr = get_frame_register_signed (this_frame, |
2243 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2244 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2245 | |
29639122 JB |
2246 | /* Assume that the frame's base is the same as the |
2247 | stack-pointer. */ | |
2248 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2249 | |
29639122 JB |
2250 | return this_trad_cache; |
2251 | } | |
c906108c | 2252 | |
29639122 | 2253 | static void |
b8a22b94 | 2254 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2255 | struct frame_id *this_id) |
2256 | { | |
2257 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2258 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2259 | trad_frame_get_id (this_trad_cache, this_id); |
2260 | } | |
c906108c | 2261 | |
b8a22b94 DJ |
2262 | static struct value * |
2263 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2264 | void **this_cache, int regnum) | |
29639122 JB |
2265 | { |
2266 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2267 | = mips_stub_frame_cache (this_frame, this_cache); |
2268 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2269 | } |
c906108c | 2270 | |
b8a22b94 DJ |
2271 | static int |
2272 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2273 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2274 | { |
aa6c981f | 2275 | gdb_byte dummy[4]; |
979b38e0 | 2276 | struct obj_section *s; |
b8a22b94 | 2277 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2278 | struct minimal_symbol *msym; |
979b38e0 | 2279 | |
aa6c981f | 2280 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2281 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2282 | return 1; | |
aa6c981f | 2283 | |
29639122 | 2284 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2285 | return 1; |
979b38e0 DJ |
2286 | |
2287 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2288 | s = find_pc_section (pc); | |
2289 | ||
2290 | if (s != NULL | |
2291 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2292 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2293 | return 1; |
979b38e0 | 2294 | |
db5f024e DJ |
2295 | /* Calling a PIC function from a non-PIC function passes through a |
2296 | stub. The stub for foo is named ".pic.foo". */ | |
2297 | msym = lookup_minimal_symbol_by_pc (pc); | |
2298 | if (msym != NULL | |
2299 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2300 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2301 | return 1; | |
2302 | ||
b8a22b94 | 2303 | return 0; |
29639122 | 2304 | } |
c906108c | 2305 | |
b8a22b94 DJ |
2306 | static const struct frame_unwind mips_stub_frame_unwind = |
2307 | { | |
2308 | NORMAL_FRAME, | |
2309 | mips_stub_frame_this_id, | |
2310 | mips_stub_frame_prev_register, | |
2311 | NULL, | |
2312 | mips_stub_frame_sniffer | |
2313 | }; | |
2314 | ||
29639122 | 2315 | static CORE_ADDR |
b8a22b94 | 2316 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2317 | void **this_cache) |
2318 | { | |
2319 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2320 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2321 | return trad_frame_get_this_base (this_trad_cache); |
2322 | } | |
0fce0821 | 2323 | |
29639122 JB |
2324 | static const struct frame_base mips_stub_frame_base = |
2325 | { | |
2326 | &mips_stub_frame_unwind, | |
2327 | mips_stub_frame_base_address, | |
2328 | mips_stub_frame_base_address, | |
2329 | mips_stub_frame_base_address | |
2330 | }; | |
2331 | ||
2332 | static const struct frame_base * | |
b8a22b94 | 2333 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2334 | { |
b8a22b94 | 2335 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2336 | return &mips_stub_frame_base; |
2337 | else | |
2338 | return NULL; | |
2339 | } | |
2340 | ||
29639122 | 2341 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2342 | |
29639122 | 2343 | static CORE_ADDR |
24568a2c | 2344 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2345 | { |
24568a2c | 2346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29639122 JB |
2347 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2348 | /* This hack is a work-around for existing boards using PMON, the | |
2349 | simulator, and any other 64-bit targets that doesn't have true | |
2350 | 64-bit addressing. On these targets, the upper 32 bits of | |
2351 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2352 | likely to have been sign extended to all 1s by instruction | |
2353 | sequences that load 32-bit addresses. For example, a typical | |
2354 | piece of code that loads an address is this: | |
65596487 | 2355 | |
29639122 JB |
2356 | lui $r2, <upper 16 bits> |
2357 | ori $r2, <lower 16 bits> | |
65596487 | 2358 | |
29639122 JB |
2359 | But the lui sign-extends the value such that the upper 32 bits |
2360 | may be all 1s. The workaround is simply to mask off these | |
2361 | bits. In the future, gcc may be changed to support true 64-bit | |
2362 | addressing, and this masking will have to be disabled. */ | |
2363 | return addr &= 0xffffffffUL; | |
2364 | else | |
2365 | return addr; | |
65596487 JB |
2366 | } |
2367 | ||
3d5f6d12 DJ |
2368 | /* Instructions used during single-stepping of atomic sequences. */ |
2369 | #define LL_OPCODE 0x30 | |
2370 | #define LLD_OPCODE 0x34 | |
2371 | #define SC_OPCODE 0x38 | |
2372 | #define SCD_OPCODE 0x3c | |
2373 | ||
2374 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2375 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2376 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2377 | the sequence. */ | |
2378 | ||
2379 | static int | |
a6d9a66e | 2380 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 DJ |
2381 | { |
2382 | CORE_ADDR breaks[2] = {-1, -1}; | |
2383 | CORE_ADDR loc = pc; | |
2384 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2385 | unsigned long insn; | |
2386 | int insn_count; | |
2387 | int index; | |
2388 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2389 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2390 | ||
2391 | if (pc & 0x01) | |
2392 | return 0; | |
2393 | ||
2394 | insn = mips_fetch_instruction (loc); | |
2395 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
2396 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2397 | return 0; | |
2398 | ||
2399 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2400 | instructions. */ | |
2401 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2402 | { | |
2403 | int is_branch = 0; | |
2404 | loc += MIPS_INSN32_SIZE; | |
2405 | insn = mips_fetch_instruction (loc); | |
2406 | ||
2407 | /* Assume that there is at most one branch in the atomic | |
2408 | sequence. If a branch is found, put a breakpoint in its | |
2409 | destination address. */ | |
2410 | switch (itype_op (insn)) | |
2411 | { | |
2412 | case 0: /* SPECIAL */ | |
2413 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2414 | return 0; /* fallback to the standard single-step code. */ | |
2415 | break; | |
2416 | case 1: /* REGIMM */ | |
2417 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2418 | break; | |
2419 | case 2: /* J */ | |
2420 | case 3: /* JAL */ | |
2421 | return 0; /* fallback to the standard single-step code. */ | |
2422 | case 4: /* BEQ */ | |
2423 | case 5: /* BNE */ | |
2424 | case 6: /* BLEZ */ | |
2425 | case 7: /* BGTZ */ | |
2426 | case 20: /* BEQL */ | |
2427 | case 21: /* BNEL */ | |
2428 | case 22: /* BLEZL */ | |
2429 | case 23: /* BGTTL */ | |
2430 | is_branch = 1; | |
2431 | break; | |
2432 | case 17: /* COP1 */ | |
2433 | case 18: /* COP2 */ | |
2434 | case 19: /* COP3 */ | |
2435 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2436 | break; | |
2437 | } | |
2438 | if (is_branch) | |
2439 | { | |
2440 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2441 | if (last_breakpoint >= 1) | |
2442 | return 0; /* More than one branch found, fallback to the | |
2443 | standard single-step code. */ | |
2444 | breaks[1] = branch_bp; | |
2445 | last_breakpoint++; | |
2446 | } | |
2447 | ||
2448 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2449 | break; | |
2450 | } | |
2451 | ||
2452 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2453 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2454 | return 0; | |
2455 | ||
2456 | loc += MIPS_INSN32_SIZE; | |
2457 | ||
2458 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2459 | breaks[0] = loc; | |
2460 | ||
2461 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2462 | placed (branch instruction's destination) in the atomic sequence */ | |
2463 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2464 | last_breakpoint = 0; | |
2465 | ||
2466 | /* Effectively inserts the breakpoints. */ | |
2467 | for (index = 0; index <= last_breakpoint; index++) | |
a6d9a66e | 2468 | insert_single_step_breakpoint (gdbarch, breaks[index]); |
3d5f6d12 DJ |
2469 | |
2470 | return 1; | |
2471 | } | |
2472 | ||
29639122 JB |
2473 | /* mips_software_single_step() is called just before we want to resume |
2474 | the inferior, if we want to single-step it but there is no hardware | |
2475 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2476 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2477 | |
e6590a1b | 2478 | int |
0b1b3e42 | 2479 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2480 | { |
a6d9a66e | 2481 | struct gdbarch *gdbarch = get_frame_arch (frame); |
8181d85f | 2482 | CORE_ADDR pc, next_pc; |
65596487 | 2483 | |
0b1b3e42 | 2484 | pc = get_frame_pc (frame); |
a6d9a66e | 2485 | if (deal_with_atomic_sequence (gdbarch, pc)) |
3d5f6d12 DJ |
2486 | return 1; |
2487 | ||
0b1b3e42 | 2488 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2489 | |
a6d9a66e | 2490 | insert_single_step_breakpoint (gdbarch, next_pc); |
e6590a1b | 2491 | return 1; |
29639122 | 2492 | } |
a65bbe44 | 2493 | |
29639122 JB |
2494 | /* Test whether the PC points to the return instruction at the |
2495 | end of a function. */ | |
65596487 | 2496 | |
29639122 JB |
2497 | static int |
2498 | mips_about_to_return (CORE_ADDR pc) | |
2499 | { | |
0fe7e7c8 | 2500 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2501 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2502 | generates a "jr $ra"; other times it generates code to load | |
2503 | the return address from the stack to an accessible register (such | |
2504 | as $a3), then a "jr" using that register. This second case | |
2505 | is almost impossible to distinguish from an indirect jump | |
2506 | used for switch statements, so we don't even try. */ | |
2507 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2508 | else | |
2509 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2510 | } | |
c906108c | 2511 | |
c906108c | 2512 | |
29639122 JB |
2513 | /* This fencepost looks highly suspicious to me. Removing it also |
2514 | seems suspicious as it could affect remote debugging across serial | |
2515 | lines. */ | |
c906108c | 2516 | |
29639122 | 2517 | static CORE_ADDR |
74ed0bb4 | 2518 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2519 | { |
2520 | CORE_ADDR start_pc; | |
2521 | CORE_ADDR fence; | |
2522 | int instlen; | |
2523 | int seen_adjsp = 0; | |
d6b48e9c | 2524 | struct inferior *inf; |
65596487 | 2525 | |
74ed0bb4 | 2526 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2527 | start_pc = pc; |
2528 | fence = start_pc - heuristic_fence_post; | |
2529 | if (start_pc == 0) | |
2530 | return 0; | |
65596487 | 2531 | |
29639122 JB |
2532 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2533 | fence = VM_MIN_ADDRESS; | |
65596487 | 2534 | |
95ac2dcf | 2535 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2536 | |
d6b48e9c PA |
2537 | inf = current_inferior (); |
2538 | ||
29639122 JB |
2539 | /* search back for previous return */ |
2540 | for (start_pc -= instlen;; start_pc -= instlen) | |
2541 | if (start_pc < fence) | |
2542 | { | |
2543 | /* It's not clear to me why we reach this point when | |
2544 | stop_soon, but with this test, at least we | |
2545 | don't print out warnings for every child forked (eg, on | |
2546 | decstation). 22apr93 rich@cygnus.com. */ | |
d6b48e9c | 2547 | if (inf->stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2548 | { |
2549 | static int blurb_printed = 0; | |
98b4dd94 | 2550 | |
5af949e3 UW |
2551 | warning (_("GDB can't find the start of the function at %s."), |
2552 | paddress (gdbarch, pc)); | |
29639122 JB |
2553 | |
2554 | if (!blurb_printed) | |
2555 | { | |
2556 | /* This actually happens frequently in embedded | |
2557 | development, when you first connect to a board | |
2558 | and your stack pointer and pc are nowhere in | |
2559 | particular. This message needs to give people | |
2560 | in that situation enough information to | |
2561 | determine that it's no big deal. */ | |
2562 | printf_filtered ("\n\ | |
5af949e3 | 2563 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2564 | and thus can't determine the size of that function's stack frame.\n\ |
2565 | This means that GDB may be unable to access that stack frame, or\n\ | |
2566 | the frames below it.\n\ | |
2567 | This problem is most likely caused by an invalid program counter or\n\ | |
2568 | stack pointer.\n\ | |
2569 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2570 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2571 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2572 | heuristic-fence-post' command.\n", |
2573 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2574 | blurb_printed = 1; |
2575 | } | |
2576 | } | |
2577 | ||
2578 | return 0; | |
2579 | } | |
0fe7e7c8 | 2580 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2581 | { |
2582 | unsigned short inst; | |
2583 | ||
2584 | /* On MIPS16, any one of the following is likely to be the | |
2585 | start of a function: | |
193774b3 MR |
2586 | extend save |
2587 | save | |
29639122 JB |
2588 | entry |
2589 | addiu sp,-n | |
2590 | daddiu sp,-n | |
2591 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2592 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2593 | if ((inst & 0xff80) == 0x6480) /* save */ |
2594 | { | |
2595 | if (start_pc - instlen >= fence) | |
2596 | { | |
2597 | inst = mips_fetch_instruction (start_pc - instlen); | |
2598 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2599 | start_pc -= instlen; | |
2600 | } | |
2601 | break; | |
2602 | } | |
2603 | else if (((inst & 0xf81f) == 0xe809 | |
2604 | && (inst & 0x700) != 0x700) /* entry */ | |
2605 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2606 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2607 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2608 | break; |
2609 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2610 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2611 | seen_adjsp = 1; | |
2612 | else | |
2613 | seen_adjsp = 0; | |
2614 | } | |
2615 | else if (mips_about_to_return (start_pc)) | |
2616 | { | |
4c7d22cb | 2617 | /* Skip return and its delay slot. */ |
95ac2dcf | 2618 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2619 | break; |
2620 | } | |
2621 | ||
2622 | return start_pc; | |
c906108c SS |
2623 | } |
2624 | ||
6c0d6680 DJ |
2625 | struct mips_objfile_private |
2626 | { | |
2627 | bfd_size_type size; | |
2628 | char *contents; | |
2629 | }; | |
2630 | ||
f09ded24 AC |
2631 | /* According to the current ABI, should the type be passed in a |
2632 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2633 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2634 | FP registers and, consequently this returns false - forces FP |
2635 | arguments into integer registers. */ | |
2636 | ||
2637 | static int | |
74ed0bb4 MD |
2638 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2639 | struct type *arg_type) | |
f09ded24 AC |
2640 | { |
2641 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2642 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2643 | && (typecode == TYPE_CODE_STRUCT |
2644 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2645 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2646 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2647 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2648 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2649 | } |
2650 | ||
49e790b0 DJ |
2651 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2652 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2653 | ||
2654 | static int | |
2655 | mips_type_needs_double_align (struct type *type) | |
2656 | { | |
2657 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2658 | |
49e790b0 DJ |
2659 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2660 | return 1; | |
2661 | else if (typecode == TYPE_CODE_STRUCT) | |
2662 | { | |
2663 | if (TYPE_NFIELDS (type) < 1) | |
2664 | return 0; | |
2665 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2666 | } | |
2667 | else if (typecode == TYPE_CODE_UNION) | |
2668 | { | |
361d1df0 | 2669 | int i, n; |
49e790b0 DJ |
2670 | |
2671 | n = TYPE_NFIELDS (type); | |
2672 | for (i = 0; i < n; i++) | |
2673 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2674 | return 1; | |
2675 | return 0; | |
2676 | } | |
2677 | return 0; | |
2678 | } | |
2679 | ||
dc604539 AC |
2680 | /* Adjust the address downward (direction of stack growth) so that it |
2681 | is correctly aligned for a new stack frame. */ | |
2682 | static CORE_ADDR | |
2683 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2684 | { | |
5b03f266 | 2685 | return align_down (addr, 16); |
dc604539 AC |
2686 | } |
2687 | ||
f7ab6ec6 | 2688 | static CORE_ADDR |
7d9b040b | 2689 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2690 | struct regcache *regcache, CORE_ADDR bp_addr, |
2691 | int nargs, struct value **args, CORE_ADDR sp, | |
2692 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2693 | { |
2694 | int argreg; | |
2695 | int float_argreg; | |
2696 | int argnum; | |
2697 | int len = 0; | |
2698 | int stack_offset = 0; | |
480d3dd2 | 2699 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2700 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2701 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2702 | |
25ab4790 AC |
2703 | /* For shared libraries, "t9" needs to point at the function |
2704 | address. */ | |
4c7d22cb | 2705 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2706 | |
2707 | /* Set the return address register to point to the entry point of | |
2708 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2709 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2710 | |
c906108c | 2711 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2712 | are properly aligned. The stack has to be at least 64-bit |
2713 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2714 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2715 | aligned, so we round to this widest known alignment. */ | |
2716 | ||
5b03f266 AC |
2717 | sp = align_down (sp, 16); |
2718 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2719 | |
46e0f506 | 2720 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2721 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2722 | passed in registers, but that's OK. */ |
c906108c | 2723 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2724 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2725 | sp -= align_up (len, 16); |
c906108c | 2726 | |
9ace0497 | 2727 | if (mips_debug) |
6d82d43b | 2728 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2729 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2730 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2731 | |
c906108c | 2732 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2733 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2734 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2735 | |
46e0f506 | 2736 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2737 | if (struct_return) |
9ace0497 AC |
2738 | { |
2739 | if (mips_debug) | |
2740 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
2741 | "mips_eabi_push_dummy_call: struct_return reg=%d %s\n", |
2742 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 2743 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2744 | } |
c906108c SS |
2745 | |
2746 | /* Now load as many as possible of the first arguments into | |
2747 | registers, and push the rest onto the stack. Loop thru args | |
2748 | from first to last. */ | |
2749 | for (argnum = 0; argnum < nargs; argnum++) | |
2750 | { | |
47a35522 MK |
2751 | const gdb_byte *val; |
2752 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2753 | struct value *arg = args[argnum]; |
4991999e | 2754 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2755 | int len = TYPE_LENGTH (arg_type); |
2756 | enum type_code typecode = TYPE_CODE (arg_type); | |
2757 | ||
9ace0497 AC |
2758 | if (mips_debug) |
2759 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2760 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2761 | argnum + 1, len, (int) typecode); |
9ace0497 | 2762 | |
c906108c | 2763 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2764 | reference. */ |
1a69e1e4 | 2765 | if (len > regsize |
9ace0497 | 2766 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2767 | { |
42ae5230 | 2768 | store_unsigned_integer (valbuf, regsize, value_address (arg)); |
c906108c | 2769 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2770 | len = regsize; |
c906108c | 2771 | val = valbuf; |
9ace0497 AC |
2772 | if (mips_debug) |
2773 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2774 | } |
2775 | else | |
47a35522 | 2776 | val = value_contents (arg); |
c906108c SS |
2777 | |
2778 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2779 | even-numbered floating point register. Round the FP register |
2780 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2781 | left. Non MIPS_EABI targets also pass the FP in the integer |
2782 | registers so also round up normal registers. */ | |
74ed0bb4 | 2783 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2784 | { |
2785 | if ((float_argreg & 1)) | |
2786 | float_argreg++; | |
2787 | } | |
c906108c SS |
2788 | |
2789 | /* Floating point arguments passed in registers have to be | |
2790 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2791 | are passed in register pairs; the even register gets |
2792 | the low word, and the odd register gets the high word. | |
2793 | On non-EABI processors, the first two floating point arguments are | |
2794 | also copied to general registers, because MIPS16 functions | |
2795 | don't use float registers for arguments. This duplication of | |
2796 | arguments in general registers can't hurt non-MIPS16 functions | |
2797 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2798 | /* MIPS_EABI squeezes a struct that contains a single floating |
2799 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2800 | stack. */ |
74ed0bb4 MD |
2801 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2802 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2803 | { |
6da397e0 KB |
2804 | /* EABI32 will pass doubles in consecutive registers, even on |
2805 | 64-bit cores. At one time, we used to check the size of | |
2806 | `float_argreg' to determine whether or not to pass doubles | |
2807 | in consecutive registers, but this is not sufficient for | |
2808 | making the ABI determination. */ | |
2809 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2810 | { |
72a155b4 | 2811 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2812 | == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2813 | unsigned long regval; |
2814 | ||
2815 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2816 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2817 | if (mips_debug) |
acdb74a0 | 2818 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2819 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2820 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2821 | |
2822 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2823 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2824 | if (mips_debug) |
acdb74a0 | 2825 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2826 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2827 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2828 | } |
2829 | else | |
2830 | { | |
2831 | /* This is a floating point value that fits entirely | |
2832 | in a single register. */ | |
53a5351d | 2833 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2834 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2835 | LONGEST regval = extract_unsigned_integer (val, len); |
2836 | if (mips_debug) | |
acdb74a0 | 2837 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2838 | float_argreg, phex (regval, len)); |
9c9acae0 | 2839 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2840 | } |
2841 | } | |
2842 | else | |
2843 | { | |
2844 | /* Copy the argument to general registers or the stack in | |
2845 | register-sized pieces. Large arguments are split between | |
2846 | registers and stack. */ | |
1a69e1e4 DJ |
2847 | /* Note: structs whose size is not a multiple of regsize |
2848 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2849 | them in registers where gcc sometimes puts them on the |
2850 | stack. For maximum compatibility, we will put them in | |
2851 | both places. */ | |
1a69e1e4 | 2852 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2853 | |
f09ded24 | 2854 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2855 | register are only written to memory. */ |
c906108c SS |
2856 | while (len > 0) |
2857 | { | |
ebafbe83 | 2858 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2859 | int stack_used_p = 0; |
1a69e1e4 | 2860 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2861 | |
acdb74a0 AC |
2862 | if (mips_debug) |
2863 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2864 | partial_len); | |
2865 | ||
566f0f7a | 2866 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 2867 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 2868 | || odd_sized_struct |
74ed0bb4 | 2869 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 2870 | { |
c906108c SS |
2871 | /* Should shorter than int integer values be |
2872 | promoted to int before being stored? */ | |
c906108c | 2873 | int longword_offset = 0; |
9ace0497 | 2874 | CORE_ADDR addr; |
566f0f7a | 2875 | stack_used_p = 1; |
72a155b4 | 2876 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2877 | { |
1a69e1e4 | 2878 | if (regsize == 8 |
480d3dd2 AC |
2879 | && (typecode == TYPE_CODE_INT |
2880 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2881 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2882 | longword_offset = regsize - len; |
480d3dd2 AC |
2883 | else if ((typecode == TYPE_CODE_STRUCT |
2884 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2885 | && TYPE_LENGTH (arg_type) < regsize) |
2886 | longword_offset = regsize - len; | |
7a292a7a | 2887 | } |
c5aa993b | 2888 | |
9ace0497 AC |
2889 | if (mips_debug) |
2890 | { | |
5af949e3 UW |
2891 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
2892 | paddress (gdbarch, stack_offset)); | |
2893 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
2894 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 2895 | } |
361d1df0 | 2896 | |
9ace0497 AC |
2897 | addr = sp + stack_offset + longword_offset; |
2898 | ||
2899 | if (mips_debug) | |
2900 | { | |
2901 | int i; | |
5af949e3 UW |
2902 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
2903 | paddress (gdbarch, addr)); | |
9ace0497 AC |
2904 | for (i = 0; i < partial_len; i++) |
2905 | { | |
6d82d43b | 2906 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2907 | val[i] & 0xff); |
9ace0497 AC |
2908 | } |
2909 | } | |
2910 | write_memory (addr, val, partial_len); | |
c906108c SS |
2911 | } |
2912 | ||
f09ded24 AC |
2913 | /* Note!!! This is NOT an else clause. Odd sized |
2914 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2915 | arguments will not. */ |
566f0f7a | 2916 | /* Write this portion of the argument to a general |
6d82d43b | 2917 | purpose register. */ |
74ed0bb4 MD |
2918 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
2919 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 2920 | { |
6d82d43b AC |
2921 | LONGEST regval = |
2922 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2923 | |
9ace0497 | 2924 | if (mips_debug) |
acdb74a0 | 2925 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2926 | argreg, |
1a69e1e4 | 2927 | phex (regval, regsize)); |
9c9acae0 | 2928 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2929 | argreg++; |
c906108c | 2930 | } |
c5aa993b | 2931 | |
c906108c SS |
2932 | len -= partial_len; |
2933 | val += partial_len; | |
2934 | ||
566f0f7a | 2935 | /* Compute the the offset into the stack at which we |
6d82d43b | 2936 | will copy the next parameter. |
566f0f7a | 2937 | |
566f0f7a | 2938 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2939 | only needs to be adjusted when it has been used. */ |
c906108c | 2940 | |
46e0f506 | 2941 | if (stack_used_p) |
1a69e1e4 | 2942 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2943 | } |
2944 | } | |
9ace0497 AC |
2945 | if (mips_debug) |
2946 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2947 | } |
2948 | ||
f10683bb | 2949 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2950 | |
0f71a2f6 JM |
2951 | /* Return adjusted stack pointer. */ |
2952 | return sp; | |
2953 | } | |
2954 | ||
a1f5b845 | 2955 | /* Determine the return value convention being used. */ |
6d82d43b | 2956 | |
9c8fdbfa | 2957 | static enum return_value_convention |
c055b101 | 2958 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 2959 | struct type *type, struct regcache *regcache, |
47a35522 | 2960 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2961 | { |
609ba780 JM |
2962 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2963 | int fp_return_type = 0; | |
2964 | int offset, regnum, xfer; | |
2965 | ||
9c8fdbfa AC |
2966 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2967 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
2968 | |
2969 | /* Floating point type? */ | |
2970 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2971 | { | |
2972 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2973 | fp_return_type = 1; | |
2974 | /* Structs with a single field of float type | |
2975 | are returned in a floating point register. */ | |
2976 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2977 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2978 | && TYPE_NFIELDS (type) == 1) | |
2979 | { | |
2980 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
2981 | ||
2982 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
2983 | fp_return_type = 1; | |
2984 | } | |
2985 | } | |
2986 | ||
2987 | if (fp_return_type) | |
2988 | { | |
2989 | /* A floating-point value belongs in the least significant part | |
2990 | of FP0/FP1. */ | |
2991 | if (mips_debug) | |
2992 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
2993 | regnum = mips_regnum (gdbarch)->fp0; | |
2994 | } | |
2995 | else | |
2996 | { | |
2997 | /* An integer value goes in V0/V1. */ | |
2998 | if (mips_debug) | |
2999 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3000 | regnum = MIPS_V0_REGNUM; | |
3001 | } | |
3002 | for (offset = 0; | |
3003 | offset < TYPE_LENGTH (type); | |
3004 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3005 | { | |
3006 | xfer = mips_abi_regsize (gdbarch); | |
3007 | if (offset + xfer > TYPE_LENGTH (type)) | |
3008 | xfer = TYPE_LENGTH (type) - offset; | |
3009 | mips_xfer_register (gdbarch, regcache, | |
3010 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3011 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3012 | offset); | |
3013 | } | |
3014 | ||
9c8fdbfa | 3015 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3016 | } |
3017 | ||
6d82d43b AC |
3018 | |
3019 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3020 | |
8d26208a DJ |
3021 | /* Search for a naturally aligned double at OFFSET inside a struct |
3022 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3023 | registers. */ | |
3024 | ||
3025 | static int | |
74ed0bb4 MD |
3026 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3027 | int offset) | |
8d26208a DJ |
3028 | { |
3029 | int i; | |
3030 | ||
3031 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3032 | return 0; | |
3033 | ||
74ed0bb4 | 3034 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3035 | return 0; |
3036 | ||
3037 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3038 | return 0; | |
3039 | ||
3040 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3041 | { | |
3042 | int pos; | |
3043 | struct type *field_type; | |
3044 | ||
3045 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3046 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3047 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3048 | continue; | |
3049 | ||
3050 | /* If we have gone past the offset, there is no double to pass. */ | |
3051 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3052 | if (pos > offset) | |
3053 | return 0; | |
3054 | ||
3055 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3056 | ||
3057 | /* If this field is entirely before the requested offset, go | |
3058 | on to the next one. */ | |
3059 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3060 | continue; | |
3061 | ||
3062 | /* If this is our special aligned double, we can stop. */ | |
3063 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3064 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3065 | return 1; | |
3066 | ||
3067 | /* This field starts at or before the requested offset, and | |
3068 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3069 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3070 | } |
3071 | ||
3072 | return 0; | |
3073 | } | |
3074 | ||
f7ab6ec6 | 3075 | static CORE_ADDR |
7d9b040b | 3076 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3077 | struct regcache *regcache, CORE_ADDR bp_addr, |
3078 | int nargs, struct value **args, CORE_ADDR sp, | |
3079 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3080 | { |
3081 | int argreg; | |
3082 | int float_argreg; | |
3083 | int argnum; | |
3084 | int len = 0; | |
3085 | int stack_offset = 0; | |
480d3dd2 | 3086 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3087 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3088 | |
25ab4790 AC |
3089 | /* For shared libraries, "t9" needs to point at the function |
3090 | address. */ | |
4c7d22cb | 3091 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3092 | |
3093 | /* Set the return address register to point to the entry point of | |
3094 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3095 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3096 | |
cb3d25d1 MS |
3097 | /* First ensure that the stack and structure return address (if any) |
3098 | are properly aligned. The stack has to be at least 64-bit | |
3099 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3100 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3101 | aligned, so we round to this widest known alignment. */ | |
3102 | ||
5b03f266 AC |
3103 | sp = align_down (sp, 16); |
3104 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3105 | |
3106 | /* Now make space on the stack for the args. */ | |
3107 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3108 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3109 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3110 | |
3111 | if (mips_debug) | |
6d82d43b | 3112 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3113 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3114 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3115 | |
3116 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3117 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3118 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3119 | |
46e0f506 | 3120 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3121 | if (struct_return) |
3122 | { | |
3123 | if (mips_debug) | |
3124 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3125 | "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n", |
3126 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3127 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3128 | } |
3129 | ||
3130 | /* Now load as many as possible of the first arguments into | |
3131 | registers, and push the rest onto the stack. Loop thru args | |
3132 | from first to last. */ | |
3133 | for (argnum = 0; argnum < nargs; argnum++) | |
3134 | { | |
47a35522 | 3135 | const gdb_byte *val; |
cb3d25d1 | 3136 | struct value *arg = args[argnum]; |
4991999e | 3137 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3138 | int len = TYPE_LENGTH (arg_type); |
3139 | enum type_code typecode = TYPE_CODE (arg_type); | |
3140 | ||
3141 | if (mips_debug) | |
3142 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3143 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3144 | argnum + 1, len, (int) typecode); |
3145 | ||
47a35522 | 3146 | val = value_contents (arg); |
cb3d25d1 | 3147 | |
5b68030f JM |
3148 | /* A 128-bit long double value requires an even-odd pair of |
3149 | floating-point registers. */ | |
3150 | if (len == 16 | |
3151 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3152 | && (float_argreg & 1)) | |
3153 | { | |
3154 | float_argreg++; | |
3155 | argreg++; | |
3156 | } | |
3157 | ||
74ed0bb4 MD |
3158 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3159 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3160 | { |
3161 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3162 | in a single register or a pair of registers. */ |
3163 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
3164 | LONGEST regval = extract_unsigned_integer (val, reglen); | |
cb3d25d1 MS |
3165 | if (mips_debug) |
3166 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3167 | float_argreg, phex (regval, reglen)); |
8d26208a | 3168 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3169 | |
3170 | if (mips_debug) | |
3171 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3172 | argreg, phex (regval, reglen)); |
9c9acae0 | 3173 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3174 | float_argreg++; |
3175 | argreg++; | |
5b68030f JM |
3176 | if (len == 16) |
3177 | { | |
3178 | regval = extract_unsigned_integer (val + reglen, reglen); | |
3179 | if (mips_debug) | |
3180 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3181 | float_argreg, phex (regval, reglen)); | |
3182 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3183 | ||
3184 | if (mips_debug) | |
3185 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3186 | argreg, phex (regval, reglen)); | |
3187 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3188 | float_argreg++; | |
3189 | argreg++; | |
3190 | } | |
cb3d25d1 MS |
3191 | } |
3192 | else | |
3193 | { | |
3194 | /* Copy the argument to general registers or the stack in | |
3195 | register-sized pieces. Large arguments are split between | |
3196 | registers and stack. */ | |
ab2e1992 MR |
3197 | /* For N32/N64, structs, unions, or other composite types are |
3198 | treated as a sequence of doublewords, and are passed in integer | |
3199 | or floating point registers as though they were simple scalar | |
3200 | parameters to the extent that they fit, with any excess on the | |
3201 | stack packed according to the normal memory layout of the | |
3202 | object. | |
3203 | The caller does not reserve space for the register arguments; | |
3204 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3205 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3206 | register are only written to memory. */ |
cb3d25d1 MS |
3207 | while (len > 0) |
3208 | { | |
ad018eee | 3209 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3210 | int stack_used_p = 0; |
1a69e1e4 | 3211 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3212 | |
3213 | if (mips_debug) | |
3214 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3215 | partial_len); | |
3216 | ||
74ed0bb4 MD |
3217 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3218 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3219 | |
cb3d25d1 | 3220 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3221 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3222 | { |
3223 | /* Should shorter than int integer values be | |
3224 | promoted to int before being stored? */ | |
3225 | int longword_offset = 0; | |
3226 | CORE_ADDR addr; | |
3227 | stack_used_p = 1; | |
72a155b4 | 3228 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3229 | { |
1a69e1e4 | 3230 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3231 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3232 | && len <= 4) |
3233 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3234 | } |
3235 | ||
3236 | if (mips_debug) | |
3237 | { | |
5af949e3 UW |
3238 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3239 | paddress (gdbarch, stack_offset)); | |
3240 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3241 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3242 | } |
3243 | ||
3244 | addr = sp + stack_offset + longword_offset; | |
3245 | ||
3246 | if (mips_debug) | |
3247 | { | |
3248 | int i; | |
5af949e3 UW |
3249 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3250 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3251 | for (i = 0; i < partial_len; i++) |
3252 | { | |
6d82d43b | 3253 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3254 | val[i] & 0xff); |
3255 | } | |
3256 | } | |
3257 | write_memory (addr, val, partial_len); | |
3258 | } | |
3259 | ||
3260 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3261 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3262 | /* Write this portion of the argument to a general |
6d82d43b | 3263 | purpose register. */ |
74ed0bb4 | 3264 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3265 | { |
5863b5d5 MR |
3266 | LONGEST regval; |
3267 | ||
3268 | /* Sign extend pointers, 32-bit integers and signed | |
3269 | 16-bit and 8-bit integers; everything else is taken | |
3270 | as is. */ | |
3271 | ||
3272 | if ((partial_len == 4 | |
3273 | && (typecode == TYPE_CODE_PTR | |
3274 | || typecode == TYPE_CODE_INT)) | |
3275 | || (partial_len < 4 | |
3276 | && typecode == TYPE_CODE_INT | |
3277 | && !TYPE_UNSIGNED (arg_type))) | |
3278 | regval = extract_signed_integer (val, partial_len); | |
3279 | else | |
3280 | regval = extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3281 | |
3282 | /* A non-floating-point argument being passed in a | |
3283 | general register. If a struct or union, and if | |
3284 | the remaining length is smaller than the register | |
3285 | size, we have to adjust the register value on | |
3286 | big endian targets. | |
3287 | ||
3288 | It does not seem to be necessary to do the | |
1a69e1e4 | 3289 | same for integral types. */ |
cb3d25d1 | 3290 | |
72a155b4 | 3291 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3292 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3293 | && (typecode == TYPE_CODE_STRUCT |
3294 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3295 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3296 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3297 | |
3298 | if (mips_debug) | |
3299 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3300 | argreg, | |
1a69e1e4 | 3301 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3302 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3303 | |
74ed0bb4 | 3304 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3305 | TYPE_LENGTH (arg_type) - len)) |
3306 | { | |
3307 | if (mips_debug) | |
3308 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3309 | float_argreg, | |
3310 | phex (regval, MIPS64_REGSIZE)); | |
3311 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3312 | regval); | |
3313 | } | |
3314 | ||
3315 | float_argreg++; | |
cb3d25d1 MS |
3316 | argreg++; |
3317 | } | |
3318 | ||
3319 | len -= partial_len; | |
3320 | val += partial_len; | |
3321 | ||
3322 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3323 | will copy the next parameter. |
cb3d25d1 MS |
3324 | |
3325 | In N32 (N64?), the stack_offset only needs to be | |
3326 | adjusted when it has been used. */ | |
3327 | ||
3328 | if (stack_used_p) | |
1a69e1e4 | 3329 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3330 | } |
3331 | } | |
3332 | if (mips_debug) | |
3333 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3334 | } | |
3335 | ||
f10683bb | 3336 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3337 | |
cb3d25d1 MS |
3338 | /* Return adjusted stack pointer. */ |
3339 | return sp; | |
3340 | } | |
3341 | ||
6d82d43b | 3342 | static enum return_value_convention |
c055b101 | 3343 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3344 | struct type *type, struct regcache *regcache, |
47a35522 | 3345 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3346 | { |
72a155b4 | 3347 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3348 | |
3349 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3350 | ||
3351 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3352 | if needed), as appropriate for the type. Composite results (struct, | |
3353 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3354 | following rules: | |
3355 | ||
3356 | * A struct with only one or two floating point fields is returned in $f0 | |
3357 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3358 | case. | |
3359 | ||
3360 | * Any other struct or union results of at most 128 bits are returned in | |
3361 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3362 | ||
3363 | * Larger composite results are handled by converting the function to a | |
3364 | procedure with an implicit first parameter, which is a pointer to an area | |
3365 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3366 | that all composite results be handled by conversion to implicit first | |
3367 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3368 | specific exception to return COMPLEX results in the floating point | |
3369 | registers.] */ | |
3370 | ||
3371 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3372 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3373 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3374 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3375 | && TYPE_LENGTH (type) == 16 | |
3376 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3377 | { | |
3378 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3379 | two registers are used in the same as memory order, so the | |
3380 | eight bytes with the lower memory address are in $f0. */ | |
3381 | if (mips_debug) | |
3382 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3383 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3384 | gdbarch_num_regs (gdbarch) |
3385 | + mips_regnum (gdbarch)->fp0, | |
3386 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3387 | readbuf, writebuf, 0); |
ba32f989 | 3388 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3389 | gdbarch_num_regs (gdbarch) |
3390 | + mips_regnum (gdbarch)->fp0 + 2, | |
3391 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3392 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3393 | writebuf ? writebuf + 8 : writebuf, 0); |
3394 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3395 | } | |
6d82d43b AC |
3396 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3397 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3398 | { | |
59aa1faa | 3399 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3400 | if (mips_debug) |
3401 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3402 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3403 | gdbarch_num_regs (gdbarch) |
3404 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3405 | TYPE_LENGTH (type), |
72a155b4 | 3406 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3407 | readbuf, writebuf, 0); |
6d82d43b AC |
3408 | return RETURN_VALUE_REGISTER_CONVENTION; |
3409 | } | |
3410 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3411 | && TYPE_NFIELDS (type) <= 2 | |
3412 | && TYPE_NFIELDS (type) >= 1 | |
3413 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3414 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3415 | == TYPE_CODE_FLT)) |
3416 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3417 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3418 | == TYPE_CODE_FLT) |
b18bb924 | 3419 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3420 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3421 | { |
3422 | /* A struct that contains one or two floats. Each value is part | |
3423 | in the least significant part of their floating point | |
5b68030f | 3424 | register (or GPR, for soft float). */ |
6d82d43b AC |
3425 | int regnum; |
3426 | int field; | |
5b68030f JM |
3427 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3428 | ? mips_regnum (gdbarch)->fp0 | |
3429 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3430 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3431 | { | |
3432 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3433 | / TARGET_CHAR_BIT); | |
3434 | if (mips_debug) | |
3435 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3436 | offset); | |
5b68030f JM |
3437 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3438 | { | |
3439 | /* A 16-byte long double field goes in two consecutive | |
3440 | registers. */ | |
3441 | mips_xfer_register (gdbarch, regcache, | |
3442 | gdbarch_num_regs (gdbarch) + regnum, | |
3443 | 8, | |
3444 | gdbarch_byte_order (gdbarch), | |
3445 | readbuf, writebuf, offset); | |
3446 | mips_xfer_register (gdbarch, regcache, | |
3447 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3448 | 8, | |
3449 | gdbarch_byte_order (gdbarch), | |
3450 | readbuf, writebuf, offset + 8); | |
3451 | } | |
3452 | else | |
3453 | mips_xfer_register (gdbarch, regcache, | |
3454 | gdbarch_num_regs (gdbarch) + regnum, | |
3455 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3456 | gdbarch_byte_order (gdbarch), | |
3457 | readbuf, writebuf, offset); | |
6d82d43b AC |
3458 | } |
3459 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3460 | } | |
3461 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3462 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3463 | { | |
3464 | /* A structure or union. Extract the left justified value, | |
3465 | regardless of the byte order. I.e. DO NOT USE | |
3466 | mips_xfer_lower. */ | |
3467 | int offset; | |
3468 | int regnum; | |
4c7d22cb | 3469 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3470 | offset < TYPE_LENGTH (type); |
72a155b4 | 3471 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3472 | { |
72a155b4 | 3473 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3474 | if (offset + xfer > TYPE_LENGTH (type)) |
3475 | xfer = TYPE_LENGTH (type) - offset; | |
3476 | if (mips_debug) | |
3477 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3478 | offset, xfer, regnum); | |
ba32f989 DJ |
3479 | mips_xfer_register (gdbarch, regcache, |
3480 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3481 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3482 | offset); | |
6d82d43b AC |
3483 | } |
3484 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3485 | } | |
3486 | else | |
3487 | { | |
3488 | /* A scalar extract each part but least-significant-byte | |
3489 | justified. */ | |
3490 | int offset; | |
3491 | int regnum; | |
4c7d22cb | 3492 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3493 | offset < TYPE_LENGTH (type); |
72a155b4 | 3494 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3495 | { |
72a155b4 | 3496 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3497 | if (offset + xfer > TYPE_LENGTH (type)) |
3498 | xfer = TYPE_LENGTH (type) - offset; | |
3499 | if (mips_debug) | |
3500 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3501 | offset, xfer, regnum); | |
ba32f989 DJ |
3502 | mips_xfer_register (gdbarch, regcache, |
3503 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3504 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3505 | readbuf, writebuf, offset); |
6d82d43b AC |
3506 | } |
3507 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3508 | } | |
3509 | } | |
3510 | ||
3511 | /* O32 ABI stuff. */ | |
3512 | ||
3513 | static CORE_ADDR | |
7d9b040b | 3514 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3515 | struct regcache *regcache, CORE_ADDR bp_addr, |
3516 | int nargs, struct value **args, CORE_ADDR sp, | |
3517 | int struct_return, CORE_ADDR struct_addr) | |
3518 | { | |
3519 | int argreg; | |
3520 | int float_argreg; | |
3521 | int argnum; | |
3522 | int len = 0; | |
3523 | int stack_offset = 0; | |
3524 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3525 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3526 | |
3527 | /* For shared libraries, "t9" needs to point at the function | |
3528 | address. */ | |
4c7d22cb | 3529 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3530 | |
3531 | /* Set the return address register to point to the entry point of | |
3532 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3533 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3534 | |
3535 | /* First ensure that the stack and structure return address (if any) | |
3536 | are properly aligned. The stack has to be at least 64-bit | |
3537 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3538 | aligned. For n32 and n64, stack frames need to be 128-bit |
3539 | aligned, so we round to this widest known alignment. */ | |
3540 | ||
5b03f266 AC |
3541 | sp = align_down (sp, 16); |
3542 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3543 | |
3544 | /* Now make space on the stack for the args. */ | |
3545 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3546 | { |
3547 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3548 | int arglen = TYPE_LENGTH (arg_type); | |
3549 | ||
3550 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3551 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3552 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3553 | /* Allocate space on the stack. */ |
1a69e1e4 | 3554 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3555 | } |
5b03f266 | 3556 | sp -= align_up (len, 16); |
ebafbe83 MS |
3557 | |
3558 | if (mips_debug) | |
6d82d43b | 3559 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3560 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3561 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3562 | |
3563 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3564 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3565 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3566 | |
bcb0cc15 | 3567 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3568 | if (struct_return) |
3569 | { | |
3570 | if (mips_debug) | |
3571 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3572 | "mips_o32_push_dummy_call: struct_return reg=%d %s\n", |
3573 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3574 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3575 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3576 | } |
3577 | ||
3578 | /* Now load as many as possible of the first arguments into | |
3579 | registers, and push the rest onto the stack. Loop thru args | |
3580 | from first to last. */ | |
3581 | for (argnum = 0; argnum < nargs; argnum++) | |
3582 | { | |
47a35522 | 3583 | const gdb_byte *val; |
ebafbe83 | 3584 | struct value *arg = args[argnum]; |
4991999e | 3585 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3586 | int len = TYPE_LENGTH (arg_type); |
3587 | enum type_code typecode = TYPE_CODE (arg_type); | |
3588 | ||
3589 | if (mips_debug) | |
3590 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3591 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3592 | argnum + 1, len, (int) typecode); |
3593 | ||
47a35522 | 3594 | val = value_contents (arg); |
46cac009 AC |
3595 | |
3596 | /* 32-bit ABIs always start floating point arguments in an | |
3597 | even-numbered floating point register. Round the FP register | |
3598 | up before the check to see if there are any FP registers | |
3599 | left. O32/O64 targets also pass the FP in the integer | |
3600 | registers so also round up normal registers. */ | |
74ed0bb4 | 3601 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3602 | { |
3603 | if ((float_argreg & 1)) | |
3604 | float_argreg++; | |
3605 | } | |
3606 | ||
3607 | /* Floating point arguments passed in registers have to be | |
3608 | treated specially. On 32-bit architectures, doubles | |
3609 | are passed in register pairs; the even register gets | |
3610 | the low word, and the odd register gets the high word. | |
3611 | On O32/O64, the first two floating point arguments are | |
3612 | also copied to general registers, because MIPS16 functions | |
3613 | don't use float registers for arguments. This duplication of | |
3614 | arguments in general registers can't hurt non-MIPS16 functions | |
3615 | because those registers are normally skipped. */ | |
3616 | ||
74ed0bb4 MD |
3617 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3618 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3619 | { |
8b07f6d8 | 3620 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3621 | { |
72a155b4 | 3622 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3623 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3624 | unsigned long regval; |
3625 | ||
3626 | /* Write the low word of the double to the even register(s). */ | |
3627 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3628 | if (mips_debug) | |
3629 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3630 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3631 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3632 | if (mips_debug) |
3633 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3634 | argreg, phex (regval, 4)); | |
9c9acae0 | 3635 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3636 | |
3637 | /* Write the high word of the double to the odd register(s). */ | |
3638 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3639 | if (mips_debug) | |
3640 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3641 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3642 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3643 | |
3644 | if (mips_debug) | |
3645 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3646 | argreg, phex (regval, 4)); | |
9c9acae0 | 3647 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3648 | } |
3649 | else | |
3650 | { | |
3651 | /* This is a floating point value that fits entirely | |
3652 | in a single register. */ | |
3653 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3654 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3655 | LONGEST regval = extract_unsigned_integer (val, len); |
3656 | if (mips_debug) | |
3657 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3658 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3659 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3660 | /* Although two FP registers are reserved for each |
3661 | argument, only one corresponding integer register is | |
3662 | reserved. */ | |
46cac009 AC |
3663 | if (mips_debug) |
3664 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3665 | argreg, phex (regval, len)); | |
5b68030f | 3666 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3667 | } |
3668 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3669 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3670 | } |
3671 | else | |
3672 | { | |
3673 | /* Copy the argument to general registers or the stack in | |
3674 | register-sized pieces. Large arguments are split between | |
3675 | registers and stack. */ | |
1a69e1e4 DJ |
3676 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3677 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3678 | them in registers where gcc sometimes puts them on the |
3679 | stack. For maximum compatibility, we will put them in | |
3680 | both places. */ | |
1a69e1e4 DJ |
3681 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3682 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3683 | /* Structures should be aligned to eight bytes (even arg registers) |
3684 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3685 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3686 | { |
3687 | if ((argreg & 1)) | |
968b5391 MR |
3688 | { |
3689 | argreg++; | |
1a69e1e4 | 3690 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3691 | } |
46cac009 | 3692 | } |
46cac009 AC |
3693 | while (len > 0) |
3694 | { | |
3695 | /* Remember if the argument was written to the stack. */ | |
3696 | int stack_used_p = 0; | |
1a69e1e4 | 3697 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3698 | |
3699 | if (mips_debug) | |
3700 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3701 | partial_len); | |
3702 | ||
3703 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3704 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3705 | || odd_sized_struct) |
46cac009 AC |
3706 | { |
3707 | /* Should shorter than int integer values be | |
3708 | promoted to int before being stored? */ | |
3709 | int longword_offset = 0; | |
3710 | CORE_ADDR addr; | |
3711 | stack_used_p = 1; | |
46cac009 AC |
3712 | |
3713 | if (mips_debug) | |
3714 | { | |
5af949e3 UW |
3715 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3716 | paddress (gdbarch, stack_offset)); | |
3717 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3718 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3719 | } |
3720 | ||
3721 | addr = sp + stack_offset + longword_offset; | |
3722 | ||
3723 | if (mips_debug) | |
3724 | { | |
3725 | int i; | |
5af949e3 UW |
3726 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3727 | paddress (gdbarch, addr)); | |
46cac009 AC |
3728 | for (i = 0; i < partial_len; i++) |
3729 | { | |
6d82d43b | 3730 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3731 | val[i] & 0xff); |
3732 | } | |
3733 | } | |
3734 | write_memory (addr, val, partial_len); | |
3735 | } | |
3736 | ||
3737 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3738 | structs may go thru BOTH paths. */ |
46cac009 | 3739 | /* Write this portion of the argument to a general |
6d82d43b | 3740 | purpose register. */ |
74ed0bb4 | 3741 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 AC |
3742 | { |
3743 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3744 | /* Value may need to be sign extended, because |
1b13c4f6 | 3745 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3746 | |
3747 | /* A non-floating-point argument being passed in a | |
3748 | general register. If a struct or union, and if | |
3749 | the remaining length is smaller than the register | |
3750 | size, we have to adjust the register value on | |
3751 | big endian targets. | |
3752 | ||
3753 | It does not seem to be necessary to do the | |
3754 | same for integral types. | |
3755 | ||
3756 | Also don't do this adjustment on O64 binaries. | |
3757 | ||
3758 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3759 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3760 | mips_abi_regsize(), generates a left shift |
3761 | as part of storing the argument in a register | |
3762 | (the left shift isn't generated when | |
1b13c4f6 | 3763 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3764 | it is quite possible that this is GCC |
3765 | contradicting the LE/O32 ABI, GDB has not been | |
3766 | adjusted to accommodate this. Either someone | |
3767 | needs to demonstrate that the LE/O32 ABI | |
3768 | specifies such a left shift OR this new ABI gets | |
3769 | identified as such and GDB gets tweaked | |
3770 | accordingly. */ | |
3771 | ||
72a155b4 | 3772 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3773 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3774 | && (typecode == TYPE_CODE_STRUCT |
3775 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3776 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3777 | * TARGET_CHAR_BIT); |
46cac009 AC |
3778 | |
3779 | if (mips_debug) | |
3780 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3781 | argreg, | |
1a69e1e4 | 3782 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3783 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3784 | argreg++; |
3785 | ||
3786 | /* Prevent subsequent floating point arguments from | |
3787 | being passed in floating point registers. */ | |
74ed0bb4 | 3788 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3789 | } |
3790 | ||
3791 | len -= partial_len; | |
3792 | val += partial_len; | |
3793 | ||
3794 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3795 | will copy the next parameter. |
46cac009 | 3796 | |
6d82d43b AC |
3797 | In older ABIs, the caller reserved space for |
3798 | registers that contained arguments. This was loosely | |
3799 | refered to as their "home". Consequently, space is | |
3800 | always allocated. */ | |
46cac009 | 3801 | |
1a69e1e4 | 3802 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3803 | } |
3804 | } | |
3805 | if (mips_debug) | |
3806 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3807 | } | |
3808 | ||
f10683bb | 3809 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3810 | |
46cac009 AC |
3811 | /* Return adjusted stack pointer. */ |
3812 | return sp; | |
3813 | } | |
3814 | ||
6d82d43b | 3815 | static enum return_value_convention |
c055b101 CV |
3816 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3817 | struct type *type, struct regcache *regcache, | |
47a35522 | 3818 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3819 | { |
72a155b4 | 3820 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3821 | |
3822 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3823 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3824 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3825 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3826 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3827 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3828 | { | |
3829 | /* A single-precision floating-point value. It fits in the | |
3830 | least significant part of FP0. */ | |
3831 | if (mips_debug) | |
3832 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3833 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3834 | gdbarch_num_regs (gdbarch) |
3835 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3836 | TYPE_LENGTH (type), |
72a155b4 | 3837 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3838 | readbuf, writebuf, 0); |
6d82d43b AC |
3839 | return RETURN_VALUE_REGISTER_CONVENTION; |
3840 | } | |
3841 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3842 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3843 | { | |
3844 | /* A double-precision floating-point value. The most | |
3845 | significant part goes in FP1, and the least significant in | |
3846 | FP0. */ | |
3847 | if (mips_debug) | |
3848 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3849 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3850 | { |
3851 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3852 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3853 | gdbarch_num_regs (gdbarch) |
3854 | + mips_regnum (gdbarch)->fp0 + | |
3855 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3856 | readbuf, writebuf, 0); |
ba32f989 | 3857 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3858 | gdbarch_num_regs (gdbarch) |
3859 | + mips_regnum (gdbarch)->fp0 + 1, | |
3860 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3861 | readbuf, writebuf, 4); |
6d82d43b AC |
3862 | break; |
3863 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3864 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3865 | gdbarch_num_regs (gdbarch) |
3866 | + mips_regnum (gdbarch)->fp0 + 1, | |
3867 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3868 | readbuf, writebuf, 0); |
ba32f989 | 3869 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3870 | gdbarch_num_regs (gdbarch) |
3871 | + mips_regnum (gdbarch)->fp0 + 0, | |
3872 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3873 | readbuf, writebuf, 4); |
6d82d43b AC |
3874 | break; |
3875 | default: | |
e2e0b3e5 | 3876 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3877 | } |
3878 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3879 | } | |
3880 | #if 0 | |
3881 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3882 | && TYPE_NFIELDS (type) <= 2 | |
3883 | && TYPE_NFIELDS (type) >= 1 | |
3884 | && ((TYPE_NFIELDS (type) == 1 | |
3885 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3886 | == TYPE_CODE_FLT)) | |
3887 | || (TYPE_NFIELDS (type) == 2 | |
3888 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3889 | == TYPE_CODE_FLT) | |
3890 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3891 | == TYPE_CODE_FLT))) | |
3892 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3893 | { | |
3894 | /* A struct that contains one or two floats. Each value is part | |
3895 | in the least significant part of their floating point | |
3896 | register.. */ | |
870cd05e | 3897 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3898 | int regnum; |
3899 | int field; | |
72a155b4 | 3900 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3901 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3902 | { | |
3903 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3904 | / TARGET_CHAR_BIT); | |
3905 | if (mips_debug) | |
3906 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3907 | offset); | |
ba32f989 DJ |
3908 | mips_xfer_register (gdbarch, regcache, |
3909 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3910 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3911 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3912 | readbuf, writebuf, offset); |
6d82d43b AC |
3913 | } |
3914 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3915 | } | |
3916 | #endif | |
3917 | #if 0 | |
3918 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3919 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3920 | { | |
3921 | /* A structure or union. Extract the left justified value, | |
3922 | regardless of the byte order. I.e. DO NOT USE | |
3923 | mips_xfer_lower. */ | |
3924 | int offset; | |
3925 | int regnum; | |
4c7d22cb | 3926 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3927 | offset < TYPE_LENGTH (type); |
72a155b4 | 3928 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3929 | { |
72a155b4 | 3930 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3931 | if (offset + xfer > TYPE_LENGTH (type)) |
3932 | xfer = TYPE_LENGTH (type) - offset; | |
3933 | if (mips_debug) | |
3934 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3935 | offset, xfer, regnum); | |
ba32f989 DJ |
3936 | mips_xfer_register (gdbarch, regcache, |
3937 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
3938 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3939 | } | |
3940 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3941 | } | |
3942 | #endif | |
3943 | else | |
3944 | { | |
3945 | /* A scalar extract each part but least-significant-byte | |
3946 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3947 | the ISA. */ |
6d82d43b AC |
3948 | int offset; |
3949 | int regnum; | |
4c7d22cb | 3950 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3951 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3952 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3953 | { |
1a69e1e4 | 3954 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3955 | if (offset + xfer > TYPE_LENGTH (type)) |
3956 | xfer = TYPE_LENGTH (type) - offset; | |
3957 | if (mips_debug) | |
3958 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3959 | offset, xfer, regnum); | |
ba32f989 DJ |
3960 | mips_xfer_register (gdbarch, regcache, |
3961 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 3962 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3963 | readbuf, writebuf, offset); |
6d82d43b AC |
3964 | } |
3965 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3966 | } | |
3967 | } | |
3968 | ||
3969 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3970 | ABI. */ | |
46cac009 AC |
3971 | |
3972 | static CORE_ADDR | |
7d9b040b | 3973 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3974 | struct regcache *regcache, CORE_ADDR bp_addr, |
3975 | int nargs, | |
3976 | struct value **args, CORE_ADDR sp, | |
3977 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3978 | { |
3979 | int argreg; | |
3980 | int float_argreg; | |
3981 | int argnum; | |
3982 | int len = 0; | |
3983 | int stack_offset = 0; | |
480d3dd2 | 3984 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3985 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3986 | |
25ab4790 AC |
3987 | /* For shared libraries, "t9" needs to point at the function |
3988 | address. */ | |
4c7d22cb | 3989 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3990 | |
3991 | /* Set the return address register to point to the entry point of | |
3992 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3993 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3994 | |
46cac009 AC |
3995 | /* First ensure that the stack and structure return address (if any) |
3996 | are properly aligned. The stack has to be at least 64-bit | |
3997 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3998 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3999 | aligned, so we round to this widest known alignment. */ | |
4000 | ||
5b03f266 AC |
4001 | sp = align_down (sp, 16); |
4002 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4003 | |
4004 | /* Now make space on the stack for the args. */ | |
4005 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4006 | { |
4007 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4008 | int arglen = TYPE_LENGTH (arg_type); | |
4009 | ||
968b5391 | 4010 | /* Allocate space on the stack. */ |
1a69e1e4 | 4011 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4012 | } |
5b03f266 | 4013 | sp -= align_up (len, 16); |
46cac009 AC |
4014 | |
4015 | if (mips_debug) | |
6d82d43b | 4016 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4017 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4018 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4019 | |
4020 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4021 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4022 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4023 | |
4024 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4025 | if (struct_return) | |
4026 | { | |
4027 | if (mips_debug) | |
4028 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
4029 | "mips_o64_push_dummy_call: struct_return reg=%d %s\n", |
4030 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4031 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4032 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4033 | } |
4034 | ||
4035 | /* Now load as many as possible of the first arguments into | |
4036 | registers, and push the rest onto the stack. Loop thru args | |
4037 | from first to last. */ | |
4038 | for (argnum = 0; argnum < nargs; argnum++) | |
4039 | { | |
47a35522 | 4040 | const gdb_byte *val; |
46cac009 | 4041 | struct value *arg = args[argnum]; |
4991999e | 4042 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4043 | int len = TYPE_LENGTH (arg_type); |
4044 | enum type_code typecode = TYPE_CODE (arg_type); | |
4045 | ||
4046 | if (mips_debug) | |
4047 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4048 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4049 | argnum + 1, len, (int) typecode); |
4050 | ||
47a35522 | 4051 | val = value_contents (arg); |
ebafbe83 | 4052 | |
ebafbe83 MS |
4053 | /* Floating point arguments passed in registers have to be |
4054 | treated specially. On 32-bit architectures, doubles | |
4055 | are passed in register pairs; the even register gets | |
4056 | the low word, and the odd register gets the high word. | |
4057 | On O32/O64, the first two floating point arguments are | |
4058 | also copied to general registers, because MIPS16 functions | |
4059 | don't use float registers for arguments. This duplication of | |
4060 | arguments in general registers can't hurt non-MIPS16 functions | |
4061 | because those registers are normally skipped. */ | |
4062 | ||
74ed0bb4 MD |
4063 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4064 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4065 | { |
2afd3f0a MR |
4066 | LONGEST regval = extract_unsigned_integer (val, len); |
4067 | if (mips_debug) | |
4068 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4069 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4070 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4071 | if (mips_debug) |
4072 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4073 | argreg, phex (regval, len)); | |
9c9acae0 | 4074 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4075 | argreg++; |
ebafbe83 | 4076 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4077 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4078 | } |
4079 | else | |
4080 | { | |
4081 | /* Copy the argument to general registers or the stack in | |
4082 | register-sized pieces. Large arguments are split between | |
4083 | registers and stack. */ | |
1a69e1e4 | 4084 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4085 | are treated specially: Irix cc passes them in registers |
4086 | where gcc sometimes puts them on the stack. For maximum | |
4087 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4088 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4089 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4090 | while (len > 0) |
4091 | { | |
4092 | /* Remember if the argument was written to the stack. */ | |
4093 | int stack_used_p = 0; | |
1a69e1e4 | 4094 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4095 | |
4096 | if (mips_debug) | |
4097 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4098 | partial_len); | |
4099 | ||
4100 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4101 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4102 | || odd_sized_struct) |
ebafbe83 MS |
4103 | { |
4104 | /* Should shorter than int integer values be | |
4105 | promoted to int before being stored? */ | |
4106 | int longword_offset = 0; | |
4107 | CORE_ADDR addr; | |
4108 | stack_used_p = 1; | |
72a155b4 | 4109 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4110 | { |
1a69e1e4 DJ |
4111 | if ((typecode == TYPE_CODE_INT |
4112 | || typecode == TYPE_CODE_PTR | |
4113 | || typecode == TYPE_CODE_FLT) | |
4114 | && len <= 4) | |
4115 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4116 | } |
4117 | ||
4118 | if (mips_debug) | |
4119 | { | |
5af949e3 UW |
4120 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4121 | paddress (gdbarch, stack_offset)); | |
4122 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4123 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4124 | } |
4125 | ||
4126 | addr = sp + stack_offset + longword_offset; | |
4127 | ||
4128 | if (mips_debug) | |
4129 | { | |
4130 | int i; | |
5af949e3 UW |
4131 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4132 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4133 | for (i = 0; i < partial_len; i++) |
4134 | { | |
6d82d43b | 4135 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4136 | val[i] & 0xff); |
4137 | } | |
4138 | } | |
4139 | write_memory (addr, val, partial_len); | |
4140 | } | |
4141 | ||
4142 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4143 | structs may go thru BOTH paths. */ |
ebafbe83 | 4144 | /* Write this portion of the argument to a general |
6d82d43b | 4145 | purpose register. */ |
74ed0bb4 | 4146 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 MS |
4147 | { |
4148 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4149 | /* Value may need to be sign extended, because |
1b13c4f6 | 4150 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4151 | |
4152 | /* A non-floating-point argument being passed in a | |
4153 | general register. If a struct or union, and if | |
4154 | the remaining length is smaller than the register | |
4155 | size, we have to adjust the register value on | |
4156 | big endian targets. | |
4157 | ||
4158 | It does not seem to be necessary to do the | |
401835eb | 4159 | same for integral types. */ |
480d3dd2 | 4160 | |
72a155b4 | 4161 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4162 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4163 | && (typecode == TYPE_CODE_STRUCT |
4164 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4165 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4166 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4167 | |
4168 | if (mips_debug) | |
4169 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4170 | argreg, | |
1a69e1e4 | 4171 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4172 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4173 | argreg++; |
4174 | ||
4175 | /* Prevent subsequent floating point arguments from | |
4176 | being passed in floating point registers. */ | |
74ed0bb4 | 4177 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4178 | } |
4179 | ||
4180 | len -= partial_len; | |
4181 | val += partial_len; | |
4182 | ||
4183 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4184 | will copy the next parameter. |
ebafbe83 | 4185 | |
6d82d43b AC |
4186 | In older ABIs, the caller reserved space for |
4187 | registers that contained arguments. This was loosely | |
4188 | refered to as their "home". Consequently, space is | |
4189 | always allocated. */ | |
ebafbe83 | 4190 | |
1a69e1e4 | 4191 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4192 | } |
4193 | } | |
4194 | if (mips_debug) | |
4195 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4196 | } | |
4197 | ||
f10683bb | 4198 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4199 | |
ebafbe83 MS |
4200 | /* Return adjusted stack pointer. */ |
4201 | return sp; | |
4202 | } | |
4203 | ||
9c8fdbfa | 4204 | static enum return_value_convention |
c055b101 | 4205 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4206 | struct type *type, struct regcache *regcache, |
47a35522 | 4207 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4208 | { |
72a155b4 | 4209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4210 | |
4211 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4212 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4213 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4214 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4215 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4216 | { |
4217 | /* A floating-point value. It fits in the least significant | |
4218 | part of FP0. */ | |
4219 | if (mips_debug) | |
4220 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4221 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4222 | gdbarch_num_regs (gdbarch) |
4223 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4224 | TYPE_LENGTH (type), |
72a155b4 | 4225 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4226 | readbuf, writebuf, 0); |
7a076fd2 FF |
4227 | return RETURN_VALUE_REGISTER_CONVENTION; |
4228 | } | |
4229 | else | |
4230 | { | |
4231 | /* A scalar extract each part but least-significant-byte | |
4232 | justified. */ | |
4233 | int offset; | |
4234 | int regnum; | |
4235 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4236 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4237 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4238 | { |
1a69e1e4 | 4239 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4240 | if (offset + xfer > TYPE_LENGTH (type)) |
4241 | xfer = TYPE_LENGTH (type) - offset; | |
4242 | if (mips_debug) | |
4243 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4244 | offset, xfer, regnum); | |
ba32f989 DJ |
4245 | mips_xfer_register (gdbarch, regcache, |
4246 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4247 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4248 | readbuf, writebuf, offset); |
7a076fd2 FF |
4249 | } |
4250 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4251 | } | |
6d82d43b AC |
4252 | } |
4253 | ||
dd824b04 DJ |
4254 | /* Floating point register management. |
4255 | ||
4256 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4257 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4258 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4259 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4260 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4261 | double precision floats into two 32-bit chunks and store them in | |
4262 | consecutive fp regs. To display 64-bit floats stored in this | |
4263 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4264 | Throw in user-configurable endianness and you have a real mess. | |
4265 | ||
4266 | The way this works is: | |
4267 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4268 | double-precision value will be split across two logical registers. | |
4269 | The lower-numbered logical register will hold the low-order bits, | |
4270 | regardless of the processor's endianness. | |
4271 | - If we are on a 64-bit processor, and we are looking for a | |
4272 | single-precision value, it will be in the low ordered bits | |
4273 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4274 | save slot in memory. | |
4275 | - If we are in 64-bit mode, everything is straightforward. | |
4276 | ||
4277 | Note that this code only deals with "live" registers at the top of the | |
4278 | stack. We will attempt to deal with saved registers later, when | |
4279 | the raw/cooked register interface is in place. (We need a general | |
4280 | interface that can deal with dynamic saved register sizes -- fp | |
4281 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4282 | and below). */ | |
4283 | ||
4284 | /* Copy a 32-bit single-precision value from the current frame | |
4285 | into rare_buffer. */ | |
4286 | ||
4287 | static void | |
e11c53d2 | 4288 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4289 | gdb_byte *rare_buffer) |
dd824b04 | 4290 | { |
72a155b4 UW |
4291 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4292 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4293 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4294 | |
e11c53d2 | 4295 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4296 | error (_("can't read register %d (%s)"), |
72a155b4 | 4297 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4298 | if (raw_size == 8) |
4299 | { | |
4300 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4301 | 32 bits. */ |
dd824b04 DJ |
4302 | int offset; |
4303 | ||
72a155b4 | 4304 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4305 | offset = 4; |
4306 | else | |
4307 | offset = 0; | |
4308 | ||
4309 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4310 | } | |
4311 | else | |
4312 | { | |
4313 | memcpy (rare_buffer, raw_buffer, 4); | |
4314 | } | |
4315 | } | |
4316 | ||
4317 | /* Copy a 64-bit double-precision value from the current frame into | |
4318 | rare_buffer. This may include getting half of it from the next | |
4319 | register. */ | |
4320 | ||
4321 | static void | |
e11c53d2 | 4322 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4323 | gdb_byte *rare_buffer) |
dd824b04 | 4324 | { |
72a155b4 UW |
4325 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4326 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4327 | |
9c9acae0 | 4328 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4329 | { |
4330 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4331 | all 64 bits. */ |
e11c53d2 | 4332 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4333 | error (_("can't read register %d (%s)"), |
72a155b4 | 4334 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4335 | } |
4336 | else | |
4337 | { | |
72a155b4 | 4338 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4339 | |
72a155b4 | 4340 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4341 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4342 | _("mips_read_fp_register_double: bad access to " |
4343 | "odd-numbered FP register")); | |
dd824b04 DJ |
4344 | |
4345 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4346 | each register. */ |
72a155b4 | 4347 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4348 | { |
e11c53d2 AC |
4349 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4350 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4351 | } |
361d1df0 | 4352 | else |
dd824b04 | 4353 | { |
e11c53d2 AC |
4354 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4355 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4356 | } |
4357 | } | |
4358 | } | |
4359 | ||
c906108c | 4360 | static void |
e11c53d2 AC |
4361 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4362 | int regnum) | |
c5aa993b | 4363 | { /* do values for FP (float) regs */ |
72a155b4 | 4364 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4365 | gdb_byte *raw_buffer; |
3903d437 AC |
4366 | double doub, flt1; /* doubles extracted from raw hex data */ |
4367 | int inv1, inv2; | |
c5aa993b | 4368 | |
72a155b4 | 4369 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4370 | |
72a155b4 | 4371 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4372 | fprintf_filtered (file, "%*s", |
72a155b4 | 4373 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4374 | ""); |
f0ef6b29 | 4375 | |
72a155b4 | 4376 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4377 | { |
79a45b7d TT |
4378 | struct value_print_options opts; |
4379 | ||
f0ef6b29 KB |
4380 | /* 4-byte registers: Print hex and floating. Also print even |
4381 | numbered registers as doubles. */ | |
e11c53d2 | 4382 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 | 4383 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1); |
c5aa993b | 4384 | |
79a45b7d | 4385 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4386 | print_scalar_formatted (raw_buffer, |
4387 | builtin_type (gdbarch)->builtin_uint32, | |
4388 | &opts, 'w', file); | |
dd824b04 | 4389 | |
e11c53d2 | 4390 | fprintf_filtered (file, " flt: "); |
1adad886 | 4391 | if (inv1) |
e11c53d2 | 4392 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4393 | else |
e11c53d2 | 4394 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4395 | |
72a155b4 | 4396 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4397 | { |
e11c53d2 | 4398 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4399 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4400 | raw_buffer, &inv2); | |
1adad886 | 4401 | |
e11c53d2 | 4402 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4403 | if (inv2) |
e11c53d2 | 4404 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4405 | else |
e11c53d2 | 4406 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4407 | } |
c906108c SS |
4408 | } |
4409 | else | |
dd824b04 | 4410 | { |
79a45b7d TT |
4411 | struct value_print_options opts; |
4412 | ||
f0ef6b29 | 4413 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4414 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4415 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4416 | raw_buffer, &inv1); | |
c906108c | 4417 | |
e11c53d2 | 4418 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4419 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4420 | raw_buffer, &inv2); | |
f0ef6b29 | 4421 | |
79a45b7d | 4422 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4423 | print_scalar_formatted (raw_buffer, |
4424 | builtin_type (gdbarch)->builtin_uint64, | |
4425 | &opts, 'g', file); | |
f0ef6b29 | 4426 | |
e11c53d2 | 4427 | fprintf_filtered (file, " flt: "); |
1adad886 | 4428 | if (inv1) |
e11c53d2 | 4429 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4430 | else |
e11c53d2 | 4431 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4432 | |
e11c53d2 | 4433 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4434 | if (inv2) |
e11c53d2 | 4435 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4436 | else |
e11c53d2 | 4437 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4438 | } |
4439 | } | |
4440 | ||
4441 | static void | |
e11c53d2 | 4442 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4443 | int regnum) |
f0ef6b29 | 4444 | { |
a4b8ebc8 | 4445 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4446 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4447 | int offset; |
79a45b7d | 4448 | struct value_print_options opts; |
1adad886 | 4449 | |
7b9ee6a8 | 4450 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4451 | { |
e11c53d2 | 4452 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4453 | return; |
4454 | } | |
4455 | ||
4456 | /* Get the data in raw format. */ | |
e11c53d2 | 4457 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4458 | { |
c9f4d572 | 4459 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4460 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4461 | return; |
c906108c | 4462 | } |
f0ef6b29 | 4463 | |
72a155b4 | 4464 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4465 | |
4466 | /* The problem with printing numeric register names (r26, etc.) is that | |
4467 | the user can't use them on input. Probably the best solution is to | |
4468 | fix it so that either the numeric or the funky (a2, etc.) names | |
4469 | are accepted on input. */ | |
4470 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4471 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4472 | else |
e11c53d2 | 4473 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4474 | |
72a155b4 | 4475 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4476 | offset = |
72a155b4 | 4477 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4478 | else |
4479 | offset = 0; | |
4480 | ||
79a45b7d | 4481 | get_formatted_print_options (&opts, 'x'); |
6d82d43b | 4482 | print_scalar_formatted (raw_buffer + offset, |
79a45b7d | 4483 | register_type (gdbarch, regnum), &opts, 0, |
6d82d43b | 4484 | file); |
c906108c SS |
4485 | } |
4486 | ||
f0ef6b29 KB |
4487 | /* Replacement for generic do_registers_info. |
4488 | Print regs in pretty columns. */ | |
4489 | ||
4490 | static int | |
e11c53d2 AC |
4491 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4492 | int regnum) | |
f0ef6b29 | 4493 | { |
e11c53d2 AC |
4494 | fprintf_filtered (file, " "); |
4495 | mips_print_fp_register (file, frame, regnum); | |
4496 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4497 | return regnum + 1; |
4498 | } | |
4499 | ||
4500 | ||
c906108c SS |
4501 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4502 | ||
4503 | static int | |
e11c53d2 | 4504 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4505 | int start_regnum) |
c906108c | 4506 | { |
a4b8ebc8 | 4507 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4508 | /* do values for GP (int) regs */ |
47a35522 | 4509 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4510 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4511 | int col, byte; |
a4b8ebc8 | 4512 | int regnum; |
c906108c SS |
4513 | |
4514 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4515 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4516 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4517 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4518 | regnum++) |
c906108c | 4519 | { |
72a155b4 | 4520 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4521 | continue; /* unused register */ |
7b9ee6a8 | 4522 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4523 | TYPE_CODE_FLT) |
c5aa993b | 4524 | break; /* end the row: reached FP register */ |
0cc93a06 | 4525 | /* Large registers are handled separately. */ |
72a155b4 | 4526 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4527 | { |
4528 | if (col > 0) | |
4529 | break; /* End the row before this register. */ | |
4530 | ||
4531 | /* Print this register on a row by itself. */ | |
4532 | mips_print_register (file, frame, regnum); | |
4533 | fprintf_filtered (file, "\n"); | |
4534 | return regnum + 1; | |
4535 | } | |
d05f6826 DJ |
4536 | if (col == 0) |
4537 | fprintf_filtered (file, " "); | |
6d82d43b | 4538 | fprintf_filtered (file, |
72a155b4 UW |
4539 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4540 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4541 | col++; |
4542 | } | |
d05f6826 DJ |
4543 | |
4544 | if (col == 0) | |
4545 | return regnum; | |
4546 | ||
a4b8ebc8 | 4547 | /* print the R0 to R31 names */ |
72a155b4 | 4548 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4549 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4550 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4551 | else |
4552 | fprintf_filtered (file, "\n "); | |
c906108c | 4553 | |
c906108c | 4554 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4555 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4556 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4557 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4558 | regnum++) |
c906108c | 4559 | { |
72a155b4 | 4560 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4561 | continue; /* unused register */ |
7b9ee6a8 | 4562 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4563 | TYPE_CODE_FLT) |
c5aa993b | 4564 | break; /* end row: reached FP register */ |
72a155b4 | 4565 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4566 | break; /* End row: large register. */ |
4567 | ||
c906108c | 4568 | /* OK: get the data in raw format. */ |
e11c53d2 | 4569 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4570 | error (_("can't read register %d (%s)"), |
72a155b4 | 4571 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4572 | /* pad small registers */ |
4246e332 | 4573 | for (byte = 0; |
72a155b4 UW |
4574 | byte < (mips_abi_regsize (gdbarch) |
4575 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4576 | printf_filtered (" "); |
4577 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4578 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4579 | for (byte = |
72a155b4 UW |
4580 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4581 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4582 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4583 | else |
72a155b4 | 4584 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4585 | byte >= 0; byte--) |
47a35522 | 4586 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4587 | fprintf_filtered (file, " "); |
c906108c SS |
4588 | col++; |
4589 | } | |
c5aa993b | 4590 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4591 | fprintf_filtered (file, "\n"); |
c906108c SS |
4592 | |
4593 | return regnum; | |
4594 | } | |
4595 | ||
4596 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4597 | ||
bf1f5b4c | 4598 | static void |
e11c53d2 AC |
4599 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4600 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4601 | { |
c5aa993b | 4602 | if (regnum != -1) /* do one specified register */ |
c906108c | 4603 | { |
72a155b4 UW |
4604 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4605 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4606 | error (_("Not a valid register for the current processor type")); |
c906108c | 4607 | |
0cc93a06 | 4608 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4609 | fprintf_filtered (file, "\n"); |
c906108c | 4610 | } |
c5aa993b JM |
4611 | else |
4612 | /* do all (or most) registers */ | |
c906108c | 4613 | { |
72a155b4 UW |
4614 | regnum = gdbarch_num_regs (gdbarch); |
4615 | while (regnum < gdbarch_num_regs (gdbarch) | |
4616 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4617 | { |
7b9ee6a8 | 4618 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4619 | TYPE_CODE_FLT) |
e11c53d2 AC |
4620 | { |
4621 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4622 | regnum = print_fp_register_row (file, frame, regnum); | |
4623 | else | |
4624 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4625 | } | |
c906108c | 4626 | else |
e11c53d2 | 4627 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4628 | } |
4629 | } | |
4630 | } | |
4631 | ||
c906108c SS |
4632 | /* Is this a branch with a delay slot? */ |
4633 | ||
c906108c | 4634 | static int |
acdb74a0 | 4635 | is_delayed (unsigned long insn) |
c906108c SS |
4636 | { |
4637 | int i; | |
4638 | for (i = 0; i < NUMOPCODES; ++i) | |
4639 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4640 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4641 | break; | |
4642 | return (i < NUMOPCODES | |
4643 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4644 | | INSN_COND_BRANCH_DELAY | |
4645 | | INSN_COND_BRANCH_LIKELY))); | |
4646 | } | |
4647 | ||
63807e1d | 4648 | static int |
3352ef37 AC |
4649 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4650 | struct frame_info *frame) | |
c906108c | 4651 | { |
3352ef37 | 4652 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4653 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4654 | |
4655 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4656 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4657 | return 0; |
4658 | ||
06648491 MK |
4659 | if (!breakpoint_here_p (pc + 4)) |
4660 | return 0; | |
4661 | ||
3352ef37 AC |
4662 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4663 | /* If error reading memory, guess that it is not a delayed | |
4664 | branch. */ | |
c906108c | 4665 | return 0; |
4c7d22cb | 4666 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4667 | } |
4668 | ||
6d82d43b AC |
4669 | /* To skip prologues, I use this predicate. Returns either PC itself |
4670 | if the code at PC does not look like a function prologue; otherwise | |
4671 | returns an address that (if we're lucky) follows the prologue. If | |
4672 | LENIENT, then we must skip everything which is involved in setting | |
4673 | up the frame (it's OK to skip more, just so long as we don't skip | |
4674 | anything which might clobber the registers which are being saved. | |
4675 | We must skip more in the case where part of the prologue is in the | |
4676 | delay slot of a non-prologue instruction). */ | |
4677 | ||
4678 | static CORE_ADDR | |
6093d2eb | 4679 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4680 | { |
8b622e6a AC |
4681 | CORE_ADDR limit_pc; |
4682 | CORE_ADDR func_addr; | |
4683 | ||
6d82d43b AC |
4684 | /* See if we can determine the end of the prologue via the symbol table. |
4685 | If so, then return either PC, or the PC after the prologue, whichever | |
4686 | is greater. */ | |
8b622e6a AC |
4687 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4688 | { | |
d80b854b UW |
4689 | CORE_ADDR post_prologue_pc |
4690 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4691 | if (post_prologue_pc != 0) |
4692 | return max (pc, post_prologue_pc); | |
4693 | } | |
6d82d43b AC |
4694 | |
4695 | /* Can't determine prologue from the symbol table, need to examine | |
4696 | instructions. */ | |
4697 | ||
98b4dd94 JB |
4698 | /* Find an upper limit on the function prologue using the debug |
4699 | information. If the debug information could not be used to provide | |
4700 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4701 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4702 | if (limit_pc == 0) |
4703 | limit_pc = pc + 100; /* Magic. */ | |
4704 | ||
0fe7e7c8 | 4705 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4706 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4707 | else |
a65bbe44 | 4708 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4709 | } |
4710 | ||
97ab0fdd MR |
4711 | /* Check whether the PC is in a function epilogue (32-bit version). |
4712 | This is a helper function for mips_in_function_epilogue_p. */ | |
4713 | static int | |
4714 | mips32_in_function_epilogue_p (CORE_ADDR pc) | |
4715 | { | |
4716 | CORE_ADDR func_addr = 0, func_end = 0; | |
4717 | ||
4718 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4719 | { | |
4720 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4721 | CORE_ADDR addr = func_end - 12; | |
4722 | ||
4723 | if (addr < func_addr + 4) | |
4724 | addr = func_addr + 4; | |
4725 | if (pc < addr) | |
4726 | return 0; | |
4727 | ||
4728 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4729 | { | |
4730 | unsigned long high_word; | |
4731 | unsigned long inst; | |
4732 | ||
4733 | inst = mips_fetch_instruction (pc); | |
4734 | high_word = (inst >> 16) & 0xffff; | |
4735 | ||
4736 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4737 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4738 | && inst != 0x03e00008 /* jr $ra */ | |
4739 | && inst != 0x00000000) /* nop */ | |
4740 | return 0; | |
4741 | } | |
4742 | ||
4743 | return 1; | |
4744 | } | |
4745 | ||
4746 | return 0; | |
4747 | } | |
4748 | ||
4749 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4750 | This is a helper function for mips_in_function_epilogue_p. */ | |
4751 | static int | |
4752 | mips16_in_function_epilogue_p (CORE_ADDR pc) | |
4753 | { | |
4754 | CORE_ADDR func_addr = 0, func_end = 0; | |
4755 | ||
4756 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4757 | { | |
4758 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4759 | CORE_ADDR addr = func_end - 12; | |
4760 | ||
4761 | if (addr < func_addr + 4) | |
4762 | addr = func_addr + 4; | |
4763 | if (pc < addr) | |
4764 | return 0; | |
4765 | ||
4766 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4767 | { | |
4768 | unsigned short inst; | |
4769 | ||
4770 | inst = mips_fetch_instruction (pc); | |
4771 | ||
4772 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4773 | continue; | |
4774 | ||
4775 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4776 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4777 | && inst != 0xe820 /* jr $ra */ | |
4778 | && inst != 0xe8a0 /* jrc $ra */ | |
4779 | && inst != 0x6500) /* nop */ | |
4780 | return 0; | |
4781 | } | |
4782 | ||
4783 | return 1; | |
4784 | } | |
4785 | ||
4786 | return 0; | |
4787 | } | |
4788 | ||
4789 | /* The epilogue is defined here as the area at the end of a function, | |
4790 | after an instruction which destroys the function's stack frame. */ | |
4791 | static int | |
4792 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4793 | { | |
4794 | if (mips_pc_is_mips16 (pc)) | |
4795 | return mips16_in_function_epilogue_p (pc); | |
4796 | else | |
4797 | return mips32_in_function_epilogue_p (pc); | |
4798 | } | |
4799 | ||
a5ea2558 AC |
4800 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4801 | used for all MIPS-specific commands. */ | |
4802 | ||
a5ea2558 | 4803 | static void |
acdb74a0 | 4804 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4805 | { |
4806 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4807 | } | |
4808 | ||
a5ea2558 | 4809 | static void |
acdb74a0 | 4810 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4811 | { |
6d82d43b AC |
4812 | printf_unfiltered |
4813 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4814 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4815 | } | |
4816 | ||
c906108c SS |
4817 | /* Commands to show/set the MIPS FPU type. */ |
4818 | ||
c906108c | 4819 | static void |
acdb74a0 | 4820 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4821 | { |
c906108c | 4822 | char *fpu; |
6ca0852e | 4823 | |
1cf3db46 | 4824 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
4825 | { |
4826 | printf_unfiltered | |
4827 | ("The MIPS floating-point coprocessor is unknown " | |
4828 | "because the current architecture is not MIPS.\n"); | |
4829 | return; | |
4830 | } | |
4831 | ||
1cf3db46 | 4832 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
4833 | { |
4834 | case MIPS_FPU_SINGLE: | |
4835 | fpu = "single-precision"; | |
4836 | break; | |
4837 | case MIPS_FPU_DOUBLE: | |
4838 | fpu = "double-precision"; | |
4839 | break; | |
4840 | case MIPS_FPU_NONE: | |
4841 | fpu = "absent (none)"; | |
4842 | break; | |
93d56215 | 4843 | default: |
e2e0b3e5 | 4844 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4845 | } |
4846 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4847 | printf_unfiltered |
4848 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4849 | fpu); | |
c906108c | 4850 | else |
6d82d43b AC |
4851 | printf_unfiltered |
4852 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4853 | } |
4854 | ||
4855 | ||
c906108c | 4856 | static void |
acdb74a0 | 4857 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4858 | { |
6d82d43b AC |
4859 | printf_unfiltered |
4860 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4861 | show_mipsfpu_command (args, from_tty); |
4862 | } | |
4863 | ||
c906108c | 4864 | static void |
acdb74a0 | 4865 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4866 | { |
8d5838b5 AC |
4867 | struct gdbarch_info info; |
4868 | gdbarch_info_init (&info); | |
c906108c SS |
4869 | mips_fpu_type = MIPS_FPU_SINGLE; |
4870 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4871 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4872 | instead of relying on globals. Doing that would let generic code | |
4873 | handle the search for this specific architecture. */ | |
4874 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4875 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4876 | } |
4877 | ||
c906108c | 4878 | static void |
acdb74a0 | 4879 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4880 | { |
8d5838b5 AC |
4881 | struct gdbarch_info info; |
4882 | gdbarch_info_init (&info); | |
c906108c SS |
4883 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4884 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4885 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4886 | instead of relying on globals. Doing that would let generic code | |
4887 | handle the search for this specific architecture. */ | |
4888 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4889 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4890 | } |
4891 | ||
c906108c | 4892 | static void |
acdb74a0 | 4893 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4894 | { |
8d5838b5 AC |
4895 | struct gdbarch_info info; |
4896 | gdbarch_info_init (&info); | |
c906108c SS |
4897 | mips_fpu_type = MIPS_FPU_NONE; |
4898 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4899 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4900 | instead of relying on globals. Doing that would let generic code | |
4901 | handle the search for this specific architecture. */ | |
4902 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4903 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4904 | } |
4905 | ||
c906108c | 4906 | static void |
acdb74a0 | 4907 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4908 | { |
4909 | mips_fpu_type_auto = 1; | |
4910 | } | |
4911 | ||
c906108c | 4912 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4913 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4914 | the relevant processor still exists (it dates back to '94) and | |
4915 | secondly this is not the way to do this. The processor type should | |
4916 | be set by forcing an architecture change. */ | |
c906108c | 4917 | |
691c0433 AC |
4918 | void |
4919 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4920 | { |
bb486190 UW |
4921 | struct regcache *regcache = get_current_regcache (); |
4922 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
4923 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 4924 | ULONGEST prid; |
c906108c | 4925 | |
bb486190 | 4926 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 4927 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4928 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4929 | } |
4930 | ||
4931 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4932 | callable as an sfunc. */ | |
4933 | ||
4934 | static void | |
acdb74a0 AC |
4935 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4936 | struct cmd_list_element *c) | |
c906108c SS |
4937 | { |
4938 | reinit_frame_cache (); | |
4939 | } | |
4940 | ||
a89aa300 AC |
4941 | static int |
4942 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4943 | { |
d31431ed AC |
4944 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4945 | disassembler needs to be able to locally determine the ISA, and | |
4946 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4947 | work. */ | |
ec4045ea AC |
4948 | if (mips_pc_is_mips16 (memaddr)) |
4949 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4950 | |
4951 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4952 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4953 | |
e5ab0dce | 4954 | /* Set the disassembler options. */ |
9dae60cc | 4955 | if (!info->disassembler_options) |
e5ab0dce AC |
4956 | /* This string is not recognized explicitly by the disassembler, |
4957 | but it tells the disassembler to not try to guess the ABI from | |
4958 | the bfd elf headers, such that, if the user overrides the ABI | |
4959 | of a program linked as NewABI, the disassembly will follow the | |
4960 | register naming conventions specified by the user. */ | |
4961 | info->disassembler_options = "gpr-names=32"; | |
4962 | ||
c906108c | 4963 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 4964 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
4965 | return print_insn_big_mips (memaddr, info); |
4966 | else | |
4967 | return print_insn_little_mips (memaddr, info); | |
4968 | } | |
4969 | ||
9dae60cc UW |
4970 | static int |
4971 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
4972 | { | |
4973 | /* Set up the disassembler info, so that we get the right | |
4974 | register names from libopcodes. */ | |
4975 | info->disassembler_options = "gpr-names=n32"; | |
4976 | info->flavour = bfd_target_elf_flavour; | |
4977 | ||
4978 | return gdb_print_insn_mips (memaddr, info); | |
4979 | } | |
4980 | ||
4981 | static int | |
4982 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
4983 | { | |
4984 | /* Set up the disassembler info, so that we get the right | |
4985 | register names from libopcodes. */ | |
4986 | info->disassembler_options = "gpr-names=64"; | |
4987 | info->flavour = bfd_target_elf_flavour; | |
4988 | ||
4989 | return gdb_print_insn_mips (memaddr, info); | |
4990 | } | |
4991 | ||
3b3b875c UW |
4992 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4993 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4994 | It returns a pointer to a string of bytes that encode a breakpoint | |
4995 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4996 | necessary) to point to the actual memory location where the breakpoint | |
4997 | should be inserted. */ | |
c906108c | 4998 | |
47a35522 | 4999 | static const gdb_byte * |
67d57894 | 5000 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5001 | { |
67d57894 | 5002 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5003 | { |
0fe7e7c8 | 5004 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5005 | { |
47a35522 | 5006 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5007 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5008 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5009 | return mips16_big_breakpoint; |
5010 | } | |
5011 | else | |
5012 | { | |
aaab4dba AC |
5013 | /* The IDT board uses an unusual breakpoint value, and |
5014 | sometimes gets confused when it sees the usual MIPS | |
5015 | breakpoint instruction. */ | |
47a35522 MK |
5016 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5017 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5018 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5019 | |
c5aa993b | 5020 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5021 | |
5022 | if (strcmp (target_shortname, "mips") == 0) | |
5023 | return idt_big_breakpoint; | |
5024 | else if (strcmp (target_shortname, "ddb") == 0 | |
5025 | || strcmp (target_shortname, "pmon") == 0 | |
5026 | || strcmp (target_shortname, "lsi") == 0) | |
5027 | return pmon_big_breakpoint; | |
5028 | else | |
5029 | return big_breakpoint; | |
5030 | } | |
5031 | } | |
5032 | else | |
5033 | { | |
0fe7e7c8 | 5034 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5035 | { |
47a35522 | 5036 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5037 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5038 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5039 | return mips16_little_breakpoint; |
5040 | } | |
5041 | else | |
5042 | { | |
47a35522 MK |
5043 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5044 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5045 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5046 | |
c5aa993b | 5047 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5048 | |
5049 | if (strcmp (target_shortname, "mips") == 0) | |
5050 | return idt_little_breakpoint; | |
5051 | else if (strcmp (target_shortname, "ddb") == 0 | |
5052 | || strcmp (target_shortname, "pmon") == 0 | |
5053 | || strcmp (target_shortname, "lsi") == 0) | |
5054 | return pmon_little_breakpoint; | |
5055 | else | |
5056 | return little_breakpoint; | |
5057 | } | |
5058 | } | |
5059 | } | |
5060 | ||
5061 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5062 | PC, which is either the callee or the caller. There are several | |
5063 | cases which must be handled: | |
5064 | ||
5065 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5066 | target PC is in $31 ($ra). |
c906108c | 5067 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5068 | and the target PC is in $2. |
c906108c | 5069 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5070 | before the jal instruction, this is effectively a call stub |
5071 | and the the target PC is in $2. Otherwise this is effectively | |
5072 | a return stub and the target PC is in $18. | |
c906108c SS |
5073 | |
5074 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5075 | gory details. */ |
c906108c | 5076 | |
757a7cc6 | 5077 | static CORE_ADDR |
db5f024e | 5078 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
5079 | { |
5080 | char *name; | |
5081 | CORE_ADDR start_addr; | |
5082 | ||
5083 | /* Find the starting address and name of the function containing the PC. */ | |
5084 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5085 | return 0; | |
5086 | ||
5087 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5088 | target PC is in $31 ($ra). */ | |
5089 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5090 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5091 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5092 | |
5093 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5094 | { | |
5095 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5096 | and the target PC is in $2. */ | |
5097 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5098 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5099 | |
5100 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5101 | before the jal instruction, this is effectively a call stub |
5102 | and the the target PC is in $2. Otherwise this is effectively | |
5103 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5104 | else if (name[19] == 's' || name[19] == 'd') |
5105 | { | |
5106 | if (pc == start_addr) | |
5107 | { | |
5108 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5109 | stub. Such a stub for a function bar might have a name |
5110 | like __fn_stub_bar, and might look like this: | |
5111 | mfc1 $4,$f13 | |
5112 | mfc1 $5,$f12 | |
5113 | mfc1 $6,$f15 | |
5114 | mfc1 $7,$f14 | |
5115 | la $1,bar (becomes a lui/addiu pair) | |
5116 | jr $1 | |
5117 | So scan down to the lui/addi and extract the target | |
5118 | address from those two instructions. */ | |
c906108c | 5119 | |
52f729a7 | 5120 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5121 | ULONGEST inst; |
c906108c SS |
5122 | int i; |
5123 | ||
5124 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5125 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5126 | 0) | |
c906108c SS |
5127 | return target_pc; |
5128 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5129 | && strcmp (name, "etext") != 0 | |
5130 | && strcmp (name, "_etext") != 0) | |
5131 | return target_pc; | |
5132 | ||
5133 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5134 | The limit on the search is arbitrarily set to 20 |
5135 | instructions. FIXME. */ | |
95ac2dcf | 5136 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5137 | { |
c5aa993b JM |
5138 | inst = mips_fetch_instruction (target_pc); |
5139 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5140 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5141 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5142 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5143 | } |
5144 | ||
5145 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5146 | return target_pc; | |
5147 | } | |
5148 | else | |
5149 | /* This is the 'return' part of a call stub. The return | |
5150 | address is in $r18. */ | |
52f729a7 | 5151 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5152 | } |
5153 | } | |
c5aa993b | 5154 | return 0; /* not a stub */ |
c906108c SS |
5155 | } |
5156 | ||
db5f024e DJ |
5157 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5158 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5159 | so that $t9 has the correct value at function entry. */ | |
5160 | ||
5161 | static CORE_ADDR | |
5162 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5163 | { | |
5164 | struct minimal_symbol *msym; | |
5165 | int i; | |
5166 | gdb_byte stub_code[16]; | |
5167 | int32_t stub_words[4]; | |
5168 | ||
5169 | /* The stub for foo is named ".pic.foo", and is either two | |
5170 | instructions inserted before foo or a three instruction sequence | |
5171 | which jumps to foo. */ | |
5172 | msym = lookup_minimal_symbol_by_pc (pc); | |
5173 | if (msym == NULL | |
5174 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5175 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5176 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5177 | return 0; | |
5178 | ||
5179 | /* A two-instruction header. */ | |
5180 | if (MSYMBOL_SIZE (msym) == 8) | |
5181 | return pc + 8; | |
5182 | ||
5183 | /* A three-instruction (plus delay slot) trampoline. */ | |
5184 | if (MSYMBOL_SIZE (msym) == 16) | |
5185 | { | |
5186 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5187 | return 0; | |
5188 | for (i = 0; i < 4; i++) | |
5189 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 4); | |
5190 | ||
5191 | /* A stub contains these instructions: | |
5192 | lui t9, %hi(target) | |
5193 | j target | |
5194 | addiu t9, t9, %lo(target) | |
5195 | nop | |
5196 | ||
5197 | This works even for N64, since stubs are only generated with | |
5198 | -msym32. */ | |
5199 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5200 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5201 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5202 | && stub_words[3] == 0x00000000) | |
5203 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5204 | + (stub_words[2] & 0x0000ffff)); | |
5205 | } | |
5206 | ||
5207 | /* Not a recognized stub. */ | |
5208 | return 0; | |
5209 | } | |
5210 | ||
5211 | static CORE_ADDR | |
5212 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5213 | { | |
5214 | CORE_ADDR target_pc; | |
5215 | ||
5216 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5217 | if (target_pc) | |
5218 | return target_pc; | |
5219 | ||
5220 | target_pc = find_solib_trampoline_target (frame, pc); | |
5221 | if (target_pc) | |
5222 | return target_pc; | |
5223 | ||
5224 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5225 | if (target_pc) | |
5226 | return target_pc; | |
5227 | ||
5228 | return 0; | |
5229 | } | |
5230 | ||
a4b8ebc8 | 5231 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5232 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5233 | |
5234 | static int | |
d3f73121 | 5235 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5236 | { |
a4b8ebc8 | 5237 | int regnum; |
2f38ef89 | 5238 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5239 | regnum = num; |
2f38ef89 | 5240 | else if (num >= 38 && num < 70) |
d3f73121 | 5241 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5242 | else if (num == 70) |
d3f73121 | 5243 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5244 | else if (num == 71) |
d3f73121 | 5245 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5246 | else |
a4b8ebc8 AC |
5247 | /* This will hopefully (eventually) provoke a warning. Should |
5248 | we be calling complaint() here? */ | |
d3f73121 MD |
5249 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5250 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5251 | } |
5252 | ||
2f38ef89 | 5253 | |
a4b8ebc8 | 5254 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5255 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5256 | |
5257 | static int | |
d3f73121 | 5258 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5259 | { |
a4b8ebc8 | 5260 | int regnum; |
2f38ef89 | 5261 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5262 | regnum = num; |
2f38ef89 | 5263 | else if (num >= 32 && num < 64) |
d3f73121 | 5264 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5265 | else if (num == 64) |
d3f73121 | 5266 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5267 | else if (num == 65) |
d3f73121 | 5268 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5269 | else |
a4b8ebc8 AC |
5270 | /* This will hopefully (eventually) provoke a warning. Should we |
5271 | be calling complaint() here? */ | |
d3f73121 MD |
5272 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5273 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5274 | } |
5275 | ||
5276 | static int | |
e7faf938 | 5277 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5278 | { |
5279 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5280 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5281 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5282 | decide if it is valid. Should instead define a standard sim/gdb | |
5283 | register numbering scheme. */ | |
e7faf938 MD |
5284 | if (gdbarch_register_name (gdbarch, |
5285 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5286 | && gdbarch_register_name (gdbarch, | |
5287 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5288 | return regnum; |
5289 | else | |
6d82d43b | 5290 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5291 | } |
5292 | ||
2f38ef89 | 5293 | |
4844f454 CV |
5294 | /* Convert an integer into an address. Extracting the value signed |
5295 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5296 | |
5297 | static CORE_ADDR | |
79dd2d24 | 5298 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5299 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5300 | { |
4844f454 | 5301 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
5302 | } |
5303 | ||
82e91389 DJ |
5304 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5305 | than most other architectures; we just need to be explicit about it, | |
5306 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5307 | an assertion failure. */ | |
5308 | ||
5309 | static void | |
a54fba4c MD |
5310 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5311 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5312 | { |
5313 | *reg = MIPS_SP_REGNUM; | |
5314 | *offset = 0; | |
5315 | } | |
5316 | ||
caaa3122 DJ |
5317 | static void |
5318 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5319 | { | |
5320 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5321 | const char *name = bfd_get_section_name (abfd, sect); | |
5322 | ||
5323 | if (*abip != MIPS_ABI_UNKNOWN) | |
5324 | return; | |
5325 | ||
5326 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5327 | return; | |
5328 | ||
5329 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5330 | *abip = MIPS_ABI_O32; | |
5331 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5332 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5333 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5334 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5335 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5336 | *abip = MIPS_ABI_O64; | |
5337 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5338 | *abip = MIPS_ABI_EABI32; | |
5339 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5340 | *abip = MIPS_ABI_EABI64; | |
5341 | else | |
8a3fe4f8 | 5342 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5343 | } |
5344 | ||
22e47e37 FF |
5345 | static void |
5346 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5347 | { | |
5348 | int *lbp = (int *) obj; | |
5349 | const char *name = bfd_get_section_name (abfd, sect); | |
5350 | ||
5351 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5352 | *lbp = 32; | |
5353 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5354 | *lbp = 64; | |
5355 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5356 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5357 | } | |
5358 | ||
2e4ebe70 DJ |
5359 | static enum mips_abi |
5360 | global_mips_abi (void) | |
5361 | { | |
5362 | int i; | |
5363 | ||
5364 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5365 | if (mips_abi_strings[i] == mips_abi_string) | |
5366 | return (enum mips_abi) i; | |
5367 | ||
e2e0b3e5 | 5368 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5369 | } |
5370 | ||
29709017 DJ |
5371 | static void |
5372 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5373 | { | |
29709017 DJ |
5374 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5375 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5376 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5377 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5378 | |
5379 | /* If the size matches the full set of registers GDB traditionally | |
5380 | knows about, including floating point, for either 32-bit or | |
5381 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5382 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5383 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5384 | |
5385 | /* Otherwise we don't have a useful guess. */ | |
5386 | } | |
5387 | ||
f8b73d13 DJ |
5388 | static struct value * |
5389 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5390 | { | |
5391 | const int *reg_p = baton; | |
5392 | return value_of_register (*reg_p, frame); | |
5393 | } | |
5394 | ||
c2d11a7d | 5395 | static struct gdbarch * |
6d82d43b | 5396 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5397 | { |
c2d11a7d JM |
5398 | struct gdbarch *gdbarch; |
5399 | struct gdbarch_tdep *tdep; | |
5400 | int elf_flags; | |
2e4ebe70 | 5401 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5402 | int i, num_regs; |
8d5838b5 | 5403 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5404 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5405 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5406 | |
5407 | /* Check any target description for validity. */ | |
5408 | if (tdesc_has_registers (info.target_desc)) | |
5409 | { | |
5410 | static const char *const mips_gprs[] = { | |
5411 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5412 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5413 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5414 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5415 | }; | |
5416 | static const char *const mips_fprs[] = { | |
5417 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5418 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5419 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5420 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5421 | }; | |
5422 | ||
5423 | const struct tdesc_feature *feature; | |
5424 | int valid_p; | |
5425 | ||
5426 | feature = tdesc_find_feature (info.target_desc, | |
5427 | "org.gnu.gdb.mips.cpu"); | |
5428 | if (feature == NULL) | |
5429 | return NULL; | |
5430 | ||
5431 | tdesc_data = tdesc_data_alloc (); | |
5432 | ||
5433 | valid_p = 1; | |
5434 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5435 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5436 | mips_gprs[i]); | |
5437 | ||
5438 | ||
5439 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5440 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5441 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5442 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5443 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5444 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5445 | ||
5446 | if (!valid_p) | |
5447 | { | |
5448 | tdesc_data_cleanup (tdesc_data); | |
5449 | return NULL; | |
5450 | } | |
5451 | ||
5452 | feature = tdesc_find_feature (info.target_desc, | |
5453 | "org.gnu.gdb.mips.cp0"); | |
5454 | if (feature == NULL) | |
5455 | { | |
5456 | tdesc_data_cleanup (tdesc_data); | |
5457 | return NULL; | |
5458 | } | |
5459 | ||
5460 | valid_p = 1; | |
5461 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5462 | MIPS_EMBED_BADVADDR_REGNUM, | |
5463 | "badvaddr"); | |
5464 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5465 | MIPS_PS_REGNUM, "status"); | |
5466 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5467 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5468 | ||
5469 | if (!valid_p) | |
5470 | { | |
5471 | tdesc_data_cleanup (tdesc_data); | |
5472 | return NULL; | |
5473 | } | |
5474 | ||
5475 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5476 | backend is not prepared for that, though. */ | |
5477 | feature = tdesc_find_feature (info.target_desc, | |
5478 | "org.gnu.gdb.mips.fpu"); | |
5479 | if (feature == NULL) | |
5480 | { | |
5481 | tdesc_data_cleanup (tdesc_data); | |
5482 | return NULL; | |
5483 | } | |
5484 | ||
5485 | valid_p = 1; | |
5486 | for (i = 0; i < 32; i++) | |
5487 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5488 | i + MIPS_EMBED_FP0_REGNUM, | |
5489 | mips_fprs[i]); | |
5490 | ||
5491 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5492 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5493 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5494 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5495 | ||
5496 | if (!valid_p) | |
5497 | { | |
5498 | tdesc_data_cleanup (tdesc_data); | |
5499 | return NULL; | |
5500 | } | |
5501 | ||
5502 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5503 | when only 32-bit registers are provided. */ | |
5504 | } | |
c2d11a7d | 5505 | |
ec03c1ac AC |
5506 | /* First of all, extract the elf_flags, if available. */ |
5507 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5508 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5509 | else if (arches != NULL) |
5510 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5511 | else |
5512 | elf_flags = 0; | |
5513 | if (gdbarch_debug) | |
5514 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5515 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5516 | |
102182a9 | 5517 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5518 | switch ((elf_flags & EF_MIPS_ABI)) |
5519 | { | |
5520 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5521 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5522 | break; |
5523 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5524 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5525 | break; |
5526 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5527 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5528 | break; |
5529 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5530 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5531 | break; |
5532 | default: | |
acdb74a0 | 5533 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5534 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5535 | else |
ec03c1ac | 5536 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5537 | break; |
5538 | } | |
acdb74a0 | 5539 | |
caaa3122 | 5540 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5541 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5542 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5543 | |
dc305454 | 5544 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5545 | MIPS architecture (if there is one). */ |
5546 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5547 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5548 | |
32a6503c | 5549 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5550 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5551 | && info.bfd_arch_info != NULL |
5552 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5553 | { | |
5554 | switch (info.bfd_arch_info->mach) | |
5555 | { | |
5556 | case bfd_mach_mips3900: | |
ec03c1ac | 5557 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5558 | break; |
5559 | case bfd_mach_mips4100: | |
5560 | case bfd_mach_mips5000: | |
ec03c1ac | 5561 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5562 | break; |
1d06468c EZ |
5563 | case bfd_mach_mips8000: |
5564 | case bfd_mach_mips10000: | |
32a6503c KB |
5565 | /* On Irix, ELF64 executables use the N64 ABI. The |
5566 | pseudo-sections which describe the ABI aren't present | |
5567 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5568 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5569 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5570 | found_abi = MIPS_ABI_N64; |
28d169de | 5571 | else |
ec03c1ac | 5572 | found_abi = MIPS_ABI_N32; |
1d06468c | 5573 | break; |
bf64bfd6 AC |
5574 | } |
5575 | } | |
2e4ebe70 | 5576 | |
26c53e50 DJ |
5577 | /* Default 64-bit objects to N64 instead of O32. */ |
5578 | if (found_abi == MIPS_ABI_UNKNOWN | |
5579 | && info.abfd != NULL | |
5580 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5581 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5582 | found_abi = MIPS_ABI_N64; | |
5583 | ||
ec03c1ac AC |
5584 | if (gdbarch_debug) |
5585 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5586 | found_abi); | |
5587 | ||
5588 | /* What has the user specified from the command line? */ | |
5589 | wanted_abi = global_mips_abi (); | |
5590 | if (gdbarch_debug) | |
5591 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5592 | wanted_abi); | |
2e4ebe70 DJ |
5593 | |
5594 | /* Now that we have found what the ABI for this binary would be, | |
5595 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5596 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5597 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5598 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5599 | mips_abi = found_abi; | |
5600 | else | |
5601 | mips_abi = MIPS_ABI_O32; | |
5602 | if (gdbarch_debug) | |
5603 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5604 | mips_abi); | |
2e4ebe70 | 5605 | |
ec03c1ac | 5606 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5607 | if (gdbarch_debug) |
ec03c1ac AC |
5608 | fprintf_unfiltered (gdb_stdlog, |
5609 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5610 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5611 | |
8d5838b5 | 5612 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5613 | #ifdef HAVE_ELF |
5614 | if (info.abfd | |
5615 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5616 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5617 | Tag_GNU_MIPS_ABI_FP); | |
5618 | #endif /* HAVE_ELF */ | |
5619 | ||
8d5838b5 AC |
5620 | if (!mips_fpu_type_auto) |
5621 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5622 | else if (elf_fpu_type != 0) |
5623 | { | |
5624 | switch (elf_fpu_type) | |
5625 | { | |
5626 | case 1: | |
5627 | fpu_type = MIPS_FPU_DOUBLE; | |
5628 | break; | |
5629 | case 2: | |
5630 | fpu_type = MIPS_FPU_SINGLE; | |
5631 | break; | |
5632 | case 3: | |
5633 | default: | |
5634 | /* Soft float or unknown. */ | |
5635 | fpu_type = MIPS_FPU_NONE; | |
5636 | break; | |
5637 | } | |
5638 | } | |
8d5838b5 AC |
5639 | else if (info.bfd_arch_info != NULL |
5640 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5641 | switch (info.bfd_arch_info->mach) | |
5642 | { | |
5643 | case bfd_mach_mips3900: | |
5644 | case bfd_mach_mips4100: | |
5645 | case bfd_mach_mips4111: | |
a9d61c86 | 5646 | case bfd_mach_mips4120: |
8d5838b5 AC |
5647 | fpu_type = MIPS_FPU_NONE; |
5648 | break; | |
5649 | case bfd_mach_mips4650: | |
5650 | fpu_type = MIPS_FPU_SINGLE; | |
5651 | break; | |
5652 | default: | |
5653 | fpu_type = MIPS_FPU_DOUBLE; | |
5654 | break; | |
5655 | } | |
5656 | else if (arches != NULL) | |
5657 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5658 | else | |
5659 | fpu_type = MIPS_FPU_DOUBLE; | |
5660 | if (gdbarch_debug) | |
5661 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5662 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5663 | |
29709017 DJ |
5664 | /* Check for blatant incompatibilities. */ |
5665 | ||
5666 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5667 | ABI. */ | |
5668 | if (info.target_desc | |
5669 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5670 | && mips_abi != MIPS_ABI_EABI32 | |
5671 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5672 | { |
5673 | if (tdesc_data != NULL) | |
5674 | tdesc_data_cleanup (tdesc_data); | |
5675 | return NULL; | |
5676 | } | |
29709017 | 5677 | |
c2d11a7d JM |
5678 | /* try to find a pre-existing architecture */ |
5679 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5680 | arches != NULL; | |
5681 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5682 | { | |
5683 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5684 | using. */ |
9103eae0 | 5685 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5686 | continue; |
9103eae0 | 5687 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5688 | continue; |
719ec221 AC |
5689 | /* Need to be pedantic about which register virtual size is |
5690 | used. */ | |
5691 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5692 | != mips64_transfers_32bit_regs_p) | |
5693 | continue; | |
8d5838b5 AC |
5694 | /* Be pedantic about which FPU is selected. */ |
5695 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5696 | continue; | |
f8b73d13 DJ |
5697 | |
5698 | if (tdesc_data != NULL) | |
5699 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5700 | return arches->gdbarch; |
c2d11a7d JM |
5701 | } |
5702 | ||
102182a9 | 5703 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5704 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5705 | gdbarch = gdbarch_alloc (&info, tdep); | |
5706 | tdep->elf_flags = elf_flags; | |
719ec221 | 5707 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5708 | tdep->found_abi = found_abi; |
5709 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5710 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5711 | tdep->register_size_valid_p = 0; |
5712 | tdep->register_size = 0; | |
5713 | ||
5714 | if (info.target_desc) | |
5715 | { | |
5716 | /* Some useful properties can be inferred from the target. */ | |
5717 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5718 | { | |
5719 | tdep->register_size_valid_p = 1; | |
5720 | tdep->register_size = 4; | |
5721 | } | |
5722 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5723 | { | |
5724 | tdep->register_size_valid_p = 1; | |
5725 | tdep->register_size = 8; | |
5726 | } | |
5727 | } | |
c2d11a7d | 5728 | |
102182a9 | 5729 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5730 | set_gdbarch_short_bit (gdbarch, 16); |
5731 | set_gdbarch_int_bit (gdbarch, 32); | |
5732 | set_gdbarch_float_bit (gdbarch, 32); | |
5733 | set_gdbarch_double_bit (gdbarch, 64); | |
5734 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5735 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5736 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5737 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5738 | |
6d82d43b | 5739 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5740 | mips_elf_make_msymbol_special); |
5741 | ||
16e109ca | 5742 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5743 | { |
16e109ca | 5744 | const char **reg_names; |
56cea623 AC |
5745 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5746 | struct mips_regnum); | |
f8b73d13 DJ |
5747 | if (tdesc_has_registers (info.target_desc)) |
5748 | { | |
5749 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5750 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5751 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5752 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5753 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5754 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5755 | regnum->fp_control_status = 70; | |
5756 | regnum->fp_implementation_revision = 71; | |
5757 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5758 | reg_names = NULL; | |
5759 | } | |
5760 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5761 | { |
5762 | regnum->fp0 = 32; | |
5763 | regnum->pc = 64; | |
5764 | regnum->cause = 65; | |
5765 | regnum->badvaddr = 66; | |
5766 | regnum->hi = 67; | |
5767 | regnum->lo = 68; | |
5768 | regnum->fp_control_status = 69; | |
5769 | regnum->fp_implementation_revision = 70; | |
5770 | num_regs = 71; | |
16e109ca | 5771 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5772 | } |
5773 | else | |
5774 | { | |
5775 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5776 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5777 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5778 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5779 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5780 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5781 | regnum->fp_control_status = 70; | |
5782 | regnum->fp_implementation_revision = 71; | |
5783 | num_regs = 90; | |
16e109ca AC |
5784 | if (info.bfd_arch_info != NULL |
5785 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5786 | reg_names = mips_tx39_reg_names; | |
5787 | else | |
5788 | reg_names = mips_generic_reg_names; | |
56cea623 | 5789 | } |
3e8c568d | 5790 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 5791 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
5792 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5793 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5794 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5795 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5796 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5797 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5798 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5799 | tdep->mips_processor_reg_names = reg_names; |
5800 | tdep->regnum = regnum; | |
56cea623 | 5801 | } |
fe29b929 | 5802 | |
0dadbba0 | 5803 | switch (mips_abi) |
c2d11a7d | 5804 | { |
0dadbba0 | 5805 | case MIPS_ABI_O32: |
25ab4790 | 5806 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5807 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5808 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5809 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5810 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5811 | set_gdbarch_long_bit (gdbarch, 32); |
5812 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5813 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5814 | break; | |
0dadbba0 | 5815 | case MIPS_ABI_O64: |
25ab4790 | 5816 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5817 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5818 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5819 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5820 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5821 | set_gdbarch_long_bit (gdbarch, 32); |
5822 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5823 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5824 | break; | |
0dadbba0 | 5825 | case MIPS_ABI_EABI32: |
25ab4790 | 5826 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5827 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5828 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5829 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5830 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5831 | set_gdbarch_long_bit (gdbarch, 32); |
5832 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5833 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5834 | break; | |
0dadbba0 | 5835 | case MIPS_ABI_EABI64: |
25ab4790 | 5836 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5837 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5838 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5839 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5840 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5841 | set_gdbarch_long_bit (gdbarch, 64); |
5842 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5843 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5844 | break; | |
0dadbba0 | 5845 | case MIPS_ABI_N32: |
25ab4790 | 5846 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5847 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5848 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5849 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5850 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5851 | set_gdbarch_long_bit (gdbarch, 32); |
5852 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5853 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5854 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5855 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5856 | break; |
5857 | case MIPS_ABI_N64: | |
25ab4790 | 5858 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5859 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5860 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5861 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5862 | tdep->default_mask_address_p = 0; |
5863 | set_gdbarch_long_bit (gdbarch, 64); | |
5864 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5865 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5866 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5867 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 5868 | break; |
c2d11a7d | 5869 | default: |
e2e0b3e5 | 5870 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5871 | } |
5872 | ||
22e47e37 FF |
5873 | /* GCC creates a pseudo-section whose name specifies the size of |
5874 | longs, since -mlong32 or -mlong64 may be used independent of | |
5875 | other options. How those options affect pointer sizes is ABI and | |
5876 | architecture dependent, so use them to override the default sizes | |
5877 | set by the ABI. This table shows the relationship between ABI, | |
5878 | -mlongXX, and size of pointers: | |
5879 | ||
5880 | ABI -mlongXX ptr bits | |
5881 | --- -------- -------- | |
5882 | o32 32 32 | |
5883 | o32 64 32 | |
5884 | n32 32 32 | |
5885 | n32 64 64 | |
5886 | o64 32 32 | |
5887 | o64 64 64 | |
5888 | n64 32 32 | |
5889 | n64 64 64 | |
5890 | eabi32 32 32 | |
5891 | eabi32 64 32 | |
5892 | eabi64 32 32 | |
5893 | eabi64 64 64 | |
5894 | ||
5895 | Note that for o32 and eabi32, pointers are always 32 bits | |
5896 | regardless of any -mlongXX option. For all others, pointers and | |
5897 | longs are the same, as set by -mlongXX or set by defaults. | |
5898 | */ | |
5899 | ||
5900 | if (info.abfd != NULL) | |
5901 | { | |
5902 | int long_bit = 0; | |
5903 | ||
5904 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5905 | if (long_bit) | |
5906 | { | |
5907 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5908 | switch (mips_abi) | |
5909 | { | |
5910 | case MIPS_ABI_O32: | |
5911 | case MIPS_ABI_EABI32: | |
5912 | break; | |
5913 | case MIPS_ABI_N32: | |
5914 | case MIPS_ABI_O64: | |
5915 | case MIPS_ABI_N64: | |
5916 | case MIPS_ABI_EABI64: | |
5917 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5918 | break; | |
5919 | default: | |
5920 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5921 | } | |
5922 | } | |
5923 | } | |
5924 | ||
a5ea2558 AC |
5925 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5926 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5927 | comment: | |
5928 | ||
5929 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5930 | flag in object files because to do so would make it impossible to | |
102182a9 | 5931 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5932 | unnecessarily restrictive. |
361d1df0 | 5933 | |
a5ea2558 AC |
5934 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5935 | but to set this flag before gcc is built with such multilibs will | |
5936 | break too many systems.'' | |
5937 | ||
5938 | But even more unhelpfully, the default linker output target for | |
5939 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5940 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5941 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5942 | this flag to detect 32-bit mode would do the wrong thing given |
5943 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5944 | as 32-bit programs by default. */ |
a5ea2558 | 5945 | |
6c997a34 | 5946 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5947 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5948 | |
102182a9 MS |
5949 | /* Add/remove bits from an address. The MIPS needs be careful to |
5950 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5951 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5952 | ||
58dfe9ff AC |
5953 | /* Unwind the frame. */ |
5954 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5955 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 5956 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 5957 | |
102182a9 | 5958 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5959 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5960 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5961 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
5962 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
5963 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5964 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5965 | |
c2d11a7d JM |
5966 | /* MIPS version of CALL_DUMMY */ |
5967 | ||
9710e734 AC |
5968 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5969 | replaced by a command, and all targets will default to on stack | |
5970 | (regardless of the stack's execute status). */ | |
5971 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5972 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5973 | |
87783b8b AC |
5974 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5975 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5976 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5977 | ||
f7b9e9fc AC |
5978 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5979 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5980 | |
5981 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5982 | |
97ab0fdd MR |
5983 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
5984 | ||
fc0c74b1 AC |
5985 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5986 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5987 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5988 | |
a4b8ebc8 | 5989 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5990 | |
e11c53d2 | 5991 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5992 | |
9dae60cc UW |
5993 | if (mips_abi == MIPS_ABI_N32) |
5994 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
5995 | else if (mips_abi == MIPS_ABI_N64) | |
5996 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
5997 | else | |
5998 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 5999 | |
d92524f1 PM |
6000 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6001 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6002 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6003 | being used as guards for target_stopped_by_watchpoint, why not have |
6004 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6005 | is sitting on? */ |
6006 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6007 | ||
e7d6a6d2 | 6008 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6009 | |
3352ef37 AC |
6010 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
6011 | ||
0d5de010 DJ |
6012 | /* Virtual tables. */ |
6013 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6014 | ||
29709017 DJ |
6015 | mips_register_g_packet_guesses (gdbarch); |
6016 | ||
6de918a6 | 6017 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6018 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6019 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6020 | |
5792a79b | 6021 | /* Unwind the frame. */ |
b8a22b94 DJ |
6022 | dwarf2_append_unwinders (gdbarch); |
6023 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6024 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6025 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6026 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6027 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6028 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6029 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6030 | |
f8b73d13 DJ |
6031 | if (tdesc_data) |
6032 | { | |
6033 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6034 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6035 | |
6036 | /* Override the normal target description methods to handle our | |
6037 | dual real and pseudo registers. */ | |
6038 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6039 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
6040 | ||
6041 | num_regs = gdbarch_num_regs (gdbarch); | |
6042 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6043 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6044 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6045 | } | |
6046 | ||
6047 | /* Add ABI-specific aliases for the registers. */ | |
6048 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6049 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6050 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6051 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6052 | else | |
6053 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6054 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6055 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6056 | ||
6057 | /* Add some other standard aliases. */ | |
6058 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6059 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6060 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6061 | ||
865093a3 AR |
6062 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6063 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6064 | value_of_mips_user_reg, | |
6065 | &mips_numeric_register_aliases[i].regnum); | |
6066 | ||
4b9b3959 AC |
6067 | return gdbarch; |
6068 | } | |
6069 | ||
2e4ebe70 | 6070 | static void |
6d82d43b | 6071 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6072 | { |
6073 | struct gdbarch_info info; | |
6074 | ||
6075 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6076 | mips_gdbarch_init will take care of the rest. */ | |
6077 | gdbarch_info_init (&info); | |
6078 | gdbarch_update_p (info); | |
6079 | } | |
6080 | ||
ad188201 KB |
6081 | /* Print out which MIPS ABI is in use. */ |
6082 | ||
6083 | static void | |
1f8ca57c JB |
6084 | show_mips_abi (struct ui_file *file, |
6085 | int from_tty, | |
6086 | struct cmd_list_element *ignored_cmd, | |
6087 | const char *ignored_value) | |
ad188201 | 6088 | { |
1cf3db46 | 6089 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6090 | fprintf_filtered |
6091 | (file, | |
6092 | "The MIPS ABI is unknown because the current architecture " | |
6093 | "is not MIPS.\n"); | |
ad188201 KB |
6094 | else |
6095 | { | |
6096 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6097 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6098 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6099 | ||
6100 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6101 | fprintf_filtered |
6102 | (file, | |
6103 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6104 | actual_abi_str); |
ad188201 | 6105 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6106 | fprintf_filtered |
6107 | (file, | |
6108 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6109 | actual_abi_str); |
ad188201 KB |
6110 | else |
6111 | { | |
6112 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6113 | fprintf_filtered |
6114 | (file, | |
6115 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6116 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6117 | } |
6118 | } | |
6119 | } | |
6120 | ||
4b9b3959 | 6121 | static void |
72a155b4 | 6122 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6123 | { |
72a155b4 | 6124 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6125 | if (tdep != NULL) |
c2d11a7d | 6126 | { |
acdb74a0 AC |
6127 | int ef_mips_arch; |
6128 | int ef_mips_32bitmode; | |
f49e4e6d | 6129 | /* Determine the ISA. */ |
acdb74a0 AC |
6130 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6131 | { | |
6132 | case E_MIPS_ARCH_1: | |
6133 | ef_mips_arch = 1; | |
6134 | break; | |
6135 | case E_MIPS_ARCH_2: | |
6136 | ef_mips_arch = 2; | |
6137 | break; | |
6138 | case E_MIPS_ARCH_3: | |
6139 | ef_mips_arch = 3; | |
6140 | break; | |
6141 | case E_MIPS_ARCH_4: | |
93d56215 | 6142 | ef_mips_arch = 4; |
acdb74a0 AC |
6143 | break; |
6144 | default: | |
93d56215 | 6145 | ef_mips_arch = 0; |
acdb74a0 AC |
6146 | break; |
6147 | } | |
f49e4e6d | 6148 | /* Determine the size of a pointer. */ |
acdb74a0 | 6149 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6150 | fprintf_unfiltered (file, |
6151 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6152 | tdep->elf_flags); |
4b9b3959 | 6153 | fprintf_unfiltered (file, |
acdb74a0 AC |
6154 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6155 | ef_mips_32bitmode); | |
6156 | fprintf_unfiltered (file, | |
6157 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6158 | ef_mips_arch); | |
6159 | fprintf_unfiltered (file, | |
6160 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6161 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6162 | fprintf_unfiltered (file, |
6163 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6164 | mips_mask_address_p (tdep), |
4014092b | 6165 | tdep->default_mask_address_p); |
c2d11a7d | 6166 | } |
4b9b3959 AC |
6167 | fprintf_unfiltered (file, |
6168 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6169 | MIPS_DEFAULT_FPU_TYPE, | |
6170 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6171 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6172 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6173 | : "???")); | |
74ed0bb4 MD |
6174 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6175 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6176 | fprintf_unfiltered (file, |
6177 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6178 | MIPS_FPU_TYPE (gdbarch), |
6179 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6180 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6181 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6182 | : "???")); |
c2d11a7d JM |
6183 | } |
6184 | ||
6d82d43b | 6185 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6186 | |
c906108c | 6187 | void |
acdb74a0 | 6188 | _initialize_mips_tdep (void) |
c906108c SS |
6189 | { |
6190 | static struct cmd_list_element *mipsfpulist = NULL; | |
6191 | struct cmd_list_element *c; | |
6192 | ||
6d82d43b | 6193 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6194 | if (MIPS_ABI_LAST + 1 |
6195 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6196 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6197 | |
4b9b3959 | 6198 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6199 | |
8d5f9dcb DJ |
6200 | mips_pdr_data = register_objfile_data (); |
6201 | ||
4eb0ad19 DJ |
6202 | /* Create feature sets with the appropriate properties. The values |
6203 | are not important. */ | |
6204 | mips_tdesc_gp32 = allocate_target_description (); | |
6205 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6206 | ||
6207 | mips_tdesc_gp64 = allocate_target_description (); | |
6208 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6209 | ||
a5ea2558 AC |
6210 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6211 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6212 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6213 | &setmipscmdlist, "set mips ", 0, &setlist); |
6214 | ||
6215 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6216 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6217 | &showmipscmdlist, "show mips ", 0, &showlist); |
6218 | ||
2e4ebe70 | 6219 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6220 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6221 | &mips_abi_string, _("\ | |
6222 | Set the MIPS ABI used by this program."), _("\ | |
6223 | Show the MIPS ABI used by this program."), _("\ | |
6224 | This option can be set to one of:\n\ | |
6225 | auto - the default ABI associated with the current binary\n\ | |
6226 | o32\n\ | |
6227 | o64\n\ | |
6228 | n32\n\ | |
6229 | n64\n\ | |
6230 | eabi32\n\ | |
6231 | eabi64"), | |
6232 | mips_abi_update, | |
6233 | show_mips_abi, | |
6234 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6235 | |
c906108c SS |
6236 | /* Let the user turn off floating point and set the fence post for |
6237 | heuristic_proc_start. */ | |
6238 | ||
6239 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6240 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6241 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6242 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6243 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6244 | &mipsfpulist); |
6245 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6246 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6247 | &mipsfpulist); |
6248 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6249 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6250 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6251 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6252 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6253 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6254 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6255 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6256 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6257 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6258 | &mipsfpulist); |
6259 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6260 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6261 | &showlist); |
6262 | ||
c906108c SS |
6263 | /* We really would like to have both "0" and "unlimited" work, but |
6264 | command.c doesn't deal with that. So make it a var_zinteger | |
6265 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6266 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6267 | &heuristic_fence_post, _("\ |
6268 | Set the distance searched for the start of a function."), _("\ | |
6269 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6270 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6271 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6272 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6273 | reinit_frame_cache_sfunc, |
7915a72c | 6274 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6275 | &setlist, &showlist); |
c906108c SS |
6276 | |
6277 | /* Allow the user to control whether the upper bits of 64-bit | |
6278 | addresses should be zeroed. */ | |
7915a72c AC |
6279 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6280 | &mask_address_var, _("\ | |
6281 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6282 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 6283 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 6284 | allow GDB to determine the correct value."), |
08546159 AC |
6285 | NULL, show_mask_address, |
6286 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6287 | |
6288 | /* Allow the user to control the size of 32 bit registers within the | |
6289 | raw remote packet. */ | |
b3f42336 | 6290 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6291 | &mips64_transfers_32bit_regs_p, _("\ |
6292 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6293 | _("\ | |
6294 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6295 | _("\ | |
719ec221 AC |
6296 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6297 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6298 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6299 | set_mips64_transfers_32bit_regs, |
7915a72c | 6300 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6301 | &setlist, &showlist); |
9ace0497 AC |
6302 | |
6303 | /* Debug this files internals. */ | |
6bcadd06 | 6304 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6305 | &mips_debug, _("\ |
6306 | Set mips debugging."), _("\ | |
6307 | Show mips debugging."), _("\ | |
6308 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6309 | NULL, |
7915a72c | 6310 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6311 | &setdebuglist, &showdebuglist); |
c906108c | 6312 | } |