Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
1e698235 | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
5e2e9765 | 28 | #include "gdb_assert.h" |
c906108c SS |
29 | #include "frame.h" |
30 | #include "inferior.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "language.h" | |
35 | #include "gdbcore.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "target.h" | |
28d069e6 | 40 | #include "arch-utils.h" |
4e052eda | 41 | #include "regcache.h" |
70f80edf | 42 | #include "osabi.h" |
d1973055 | 43 | #include "mips-tdep.h" |
fe898f56 | 44 | #include "block.h" |
c906108c SS |
45 | |
46 | #include "opcode/mips.h" | |
c2d11a7d JM |
47 | #include "elf/mips.h" |
48 | #include "elf-bfd.h" | |
2475bac3 | 49 | #include "symcat.h" |
c906108c | 50 | |
e0f7ec59 AC |
51 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
52 | ||
dd824b04 DJ |
53 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
54 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
55 | #define ST0_FR (1 << 26) | |
56 | ||
b0069a17 AC |
57 | /* The sizes of floating point registers. */ |
58 | ||
59 | enum | |
60 | { | |
61 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
62 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
63 | }; | |
64 | ||
0dadbba0 | 65 | |
2e4ebe70 DJ |
66 | static const char *mips_abi_string; |
67 | ||
68 | static const char *mips_abi_strings[] = { | |
69 | "auto", | |
70 | "n32", | |
71 | "o32", | |
28d169de | 72 | "n64", |
2e4ebe70 DJ |
73 | "o64", |
74 | "eabi32", | |
75 | "eabi64", | |
76 | NULL | |
77 | }; | |
78 | ||
cce74817 | 79 | struct frame_extra_info |
c5aa993b JM |
80 | { |
81 | mips_extra_func_info_t proc_desc; | |
82 | int num_args; | |
83 | }; | |
cce74817 | 84 | |
d929b26f AC |
85 | /* Various MIPS ISA options (related to stack analysis) can be |
86 | overridden dynamically. Establish an enum/array for managing | |
87 | them. */ | |
88 | ||
53904c9e AC |
89 | static const char size_auto[] = "auto"; |
90 | static const char size_32[] = "32"; | |
91 | static const char size_64[] = "64"; | |
d929b26f | 92 | |
53904c9e | 93 | static const char *size_enums[] = { |
d929b26f AC |
94 | size_auto, |
95 | size_32, | |
96 | size_64, | |
a5ea2558 AC |
97 | 0 |
98 | }; | |
99 | ||
7a292a7a SS |
100 | /* Some MIPS boards don't support floating point while others only |
101 | support single-precision floating-point operations. See also | |
102 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
103 | |
104 | enum mips_fpu_type | |
c5aa993b JM |
105 | { |
106 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
107 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
108 | MIPS_FPU_NONE /* No floating point. */ | |
109 | }; | |
c906108c SS |
110 | |
111 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
112 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
113 | #endif | |
114 | static int mips_fpu_type_auto = 1; | |
115 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 116 | |
9ace0497 | 117 | static int mips_debug = 0; |
7a292a7a | 118 | |
c2d11a7d JM |
119 | /* MIPS specific per-architecture information */ |
120 | struct gdbarch_tdep | |
121 | { | |
122 | /* from the elf header */ | |
123 | int elf_flags; | |
70f80edf | 124 | |
c2d11a7d | 125 | /* mips options */ |
0dadbba0 | 126 | enum mips_abi mips_abi; |
2e4ebe70 | 127 | enum mips_abi found_abi; |
c2d11a7d JM |
128 | enum mips_fpu_type mips_fpu_type; |
129 | int mips_last_arg_regnum; | |
130 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 131 | int mips_default_saved_regsize; |
c2d11a7d | 132 | int mips_fp_register_double; |
d929b26f | 133 | int mips_default_stack_argsize; |
5213ab06 | 134 | int gdb_target_is_mips64; |
4014092b | 135 | int default_mask_address_p; |
c2d11a7d JM |
136 | }; |
137 | ||
0dadbba0 | 138 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 139 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 140 | |
c2d11a7d | 141 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 142 | |
c2d11a7d | 143 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 144 | |
c2d11a7d | 145 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 146 | |
d929b26f AC |
147 | /* Return the currently configured (or set) saved register size. */ |
148 | ||
a5ea2558 | 149 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 150 | |
53904c9e | 151 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
152 | |
153 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
154 | ||
22540ece AC |
155 | /* Return the contents of register REGNUM as a signed integer. */ |
156 | ||
157 | static LONGEST | |
158 | read_signed_register (int regnum) | |
159 | { | |
160 | void *buf = alloca (REGISTER_RAW_SIZE (regnum)); | |
161 | deprecated_read_register_gen (regnum, buf); | |
162 | return (extract_signed_integer (buf, REGISTER_RAW_SIZE (regnum))); | |
163 | } | |
164 | ||
165 | static LONGEST | |
166 | read_signed_register_pid (int regnum, ptid_t ptid) | |
167 | { | |
168 | ptid_t save_ptid; | |
169 | LONGEST retval; | |
170 | ||
171 | if (ptid_equal (ptid, inferior_ptid)) | |
172 | return read_signed_register (regnum); | |
173 | ||
174 | save_ptid = inferior_ptid; | |
175 | ||
176 | inferior_ptid = ptid; | |
177 | ||
178 | retval = read_signed_register (regnum); | |
179 | ||
180 | inferior_ptid = save_ptid; | |
181 | ||
182 | return retval; | |
183 | } | |
184 | ||
d1973055 KB |
185 | /* Return the MIPS ABI associated with GDBARCH. */ |
186 | enum mips_abi | |
187 | mips_abi (struct gdbarch *gdbarch) | |
188 | { | |
189 | return gdbarch_tdep (gdbarch)->mips_abi; | |
190 | } | |
191 | ||
d929b26f | 192 | static unsigned int |
acdb74a0 | 193 | mips_saved_regsize (void) |
d929b26f AC |
194 | { |
195 | if (mips_saved_regsize_string == size_auto) | |
196 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
197 | else if (mips_saved_regsize_string == size_64) | |
198 | return 8; | |
199 | else /* if (mips_saved_regsize_string == size_32) */ | |
200 | return 4; | |
201 | } | |
202 | ||
71b8ef93 | 203 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa MS |
204 | marks it as 16-bit function. The MSB of the minimal symbol's |
205 | "info" field is used for this purpose. This field is already | |
206 | being used to store the symbol size, so the assumption is | |
207 | that the symbol size cannot exceed 2^31. | |
208 | ||
209 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
210 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
211 | minimal symbol to mark it as a 16-bit function | |
212 | ||
213 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
214 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
215 | the "info" field with the "special" bit masked out */ | |
216 | ||
5a89d8aa MS |
217 | static void |
218 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
219 | { | |
220 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
221 | { | |
222 | MSYMBOL_INFO (msym) = (char *) | |
223 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
224 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
225 | } | |
226 | } | |
227 | ||
71b8ef93 MS |
228 | static int |
229 | msymbol_is_special (struct minimal_symbol *msym) | |
230 | { | |
231 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
232 | } | |
233 | ||
234 | static long | |
235 | msymbol_size (struct minimal_symbol *msym) | |
236 | { | |
237 | return ((long) MSYMBOL_INFO (msym) & 0x7fffffff); | |
238 | } | |
239 | ||
88658117 AC |
240 | /* XFER a value from the big/little/left end of the register. |
241 | Depending on the size of the value it might occupy the entire | |
242 | register or just part of it. Make an allowance for this, aligning | |
243 | things accordingly. */ | |
244 | ||
245 | static void | |
246 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
247 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
248 | int buf_offset) | |
249 | { | |
d9d9c31f | 250 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 251 | int reg_offset = 0; |
cb1d2653 AC |
252 | /* Need to transfer the left or right part of the register, based on |
253 | the targets byte order. */ | |
88658117 AC |
254 | switch (endian) |
255 | { | |
256 | case BFD_ENDIAN_BIG: | |
257 | reg_offset = REGISTER_RAW_SIZE (reg_num) - length; | |
258 | break; | |
259 | case BFD_ENDIAN_LITTLE: | |
260 | reg_offset = 0; | |
261 | break; | |
262 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
263 | reg_offset = 0; | |
264 | break; | |
265 | default: | |
266 | internal_error (__FILE__, __LINE__, "bad switch"); | |
267 | } | |
268 | if (mips_debug) | |
cb1d2653 AC |
269 | fprintf_unfiltered (gdb_stderr, |
270 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
271 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
272 | if (mips_debug && out != NULL) |
273 | { | |
274 | int i; | |
cb1d2653 | 275 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 276 | for (i = 0; i < length; i++) |
cb1d2653 | 277 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
278 | } |
279 | if (in != NULL) | |
280 | regcache_raw_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); | |
281 | if (out != NULL) | |
282 | regcache_raw_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); | |
283 | if (mips_debug && in != NULL) | |
284 | { | |
285 | int i; | |
cb1d2653 | 286 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 287 | for (i = 0; i < length; i++) |
cb1d2653 | 288 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
289 | } |
290 | if (mips_debug) | |
291 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
292 | } | |
293 | ||
dd824b04 DJ |
294 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
295 | compatiblity mode. A return value of 1 means that we have | |
296 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
297 | ||
298 | static int | |
299 | mips2_fp_compat (void) | |
300 | { | |
301 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
302 | meaningful. */ | |
303 | if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4) | |
304 | return 0; | |
305 | ||
306 | #if 0 | |
307 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
308 | in all the places we deal with FP registers. PR gdb/413. */ | |
309 | /* Otherwise check the FR bit in the status register - it controls | |
310 | the FP compatiblity mode. If it is clear we are in compatibility | |
311 | mode. */ | |
312 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
313 | return 1; | |
314 | #endif | |
361d1df0 | 315 | |
dd824b04 DJ |
316 | return 0; |
317 | } | |
318 | ||
c2d11a7d JM |
319 | /* Indicate that the ABI makes use of double-precision registers |
320 | provided by the FPU (rather than combining pairs of registers to | |
321 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
322 | determine if the ABI is using double-precision registers. See also | |
323 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 324 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 325 | |
d929b26f AC |
326 | /* The amount of space reserved on the stack for registers. This is |
327 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
328 | data allocated after the registers have run out. */ | |
329 | ||
0dadbba0 | 330 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
331 | |
332 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
333 | ||
53904c9e | 334 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
335 | |
336 | static unsigned int | |
337 | mips_stack_argsize (void) | |
338 | { | |
339 | if (mips_stack_argsize_string == size_auto) | |
340 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
341 | else if (mips_stack_argsize_string == size_64) | |
342 | return 8; | |
343 | else /* if (mips_stack_argsize_string == size_32) */ | |
344 | return 4; | |
345 | } | |
346 | ||
5213ab06 | 347 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 348 | |
92e1c15c | 349 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 350 | |
7a292a7a | 351 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 352 | |
a14ed312 | 353 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 354 | |
570b8f7c AC |
355 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
356 | struct frame_info *, int); | |
c906108c | 357 | |
a14ed312 | 358 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 359 | |
a14ed312 | 360 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 361 | |
5a89d8aa | 362 | static int mips_set_processor_type (char *); |
c906108c | 363 | |
a14ed312 | 364 | static void mips_show_processor_type_command (char *, int); |
c906108c | 365 | |
a14ed312 | 366 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 367 | |
570b8f7c AC |
368 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
369 | struct frame_info *next_frame, | |
370 | int cur_frame); | |
c906108c | 371 | |
a14ed312 KB |
372 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
373 | mips_extra_func_info_t proc_desc); | |
c906108c | 374 | |
67b2c998 DJ |
375 | static struct type *mips_float_register_type (void); |
376 | static struct type *mips_double_register_type (void); | |
377 | ||
c906108c SS |
378 | /* This value is the model of MIPS in use. It is derived from the value |
379 | of the PrID register. */ | |
380 | ||
381 | char *mips_processor_type; | |
382 | ||
383 | char *tmp_mips_processor_type; | |
384 | ||
acdb74a0 AC |
385 | /* The list of available "set mips " and "show mips " commands */ |
386 | ||
387 | static struct cmd_list_element *setmipscmdlist = NULL; | |
388 | static struct cmd_list_element *showmipscmdlist = NULL; | |
389 | ||
c906108c SS |
390 | /* A set of original names, to be used when restoring back to generic |
391 | registers from a specific set. */ | |
5e2e9765 | 392 | static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
c906108c | 393 | |
5e2e9765 KB |
394 | /* Integer registers 0 thru 31 are handled explicitly by |
395 | mips_register_name(). Processor specific registers 32 and above | |
396 | are listed in the sets of register names assigned to | |
397 | mips_processor_reg_names. */ | |
398 | static char **mips_processor_reg_names = mips_generic_reg_names; | |
cce74817 | 399 | |
5e2e9765 | 400 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 401 | static const char * |
5e2e9765 | 402 | mips_register_name (int regno) |
cce74817 | 403 | { |
5e2e9765 KB |
404 | /* GPR names for all ABIs other than n32/n64. */ |
405 | static char *mips_gpr_names[] = { | |
406 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
407 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
408 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
409 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
410 | }; | |
411 | ||
412 | /* GPR names for n32 and n64 ABIs. */ | |
413 | static char *mips_n32_n64_gpr_names[] = { | |
414 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
415 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
416 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
417 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
418 | }; | |
419 | ||
420 | enum mips_abi abi = mips_abi (current_gdbarch); | |
421 | ||
422 | /* The MIPS integer registers are always mapped from 0 to 31. The | |
423 | names of the registers (which reflects the conventions regarding | |
424 | register use) vary depending on the ABI. */ | |
425 | if (0 <= regno && regno < 32) | |
426 | { | |
427 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
428 | return mips_n32_n64_gpr_names[regno]; | |
429 | else | |
430 | return mips_gpr_names[regno]; | |
431 | } | |
b006a9e9 | 432 | else if (32 <= regno && regno < NUM_REGS) |
5e2e9765 KB |
433 | return mips_processor_reg_names[regno - 32]; |
434 | else | |
435 | internal_error (__FILE__, __LINE__, | |
436 | "mips_register_name: bad register number %d", regno); | |
cce74817 | 437 | } |
5e2e9765 | 438 | |
9846de1b | 439 | /* *INDENT-OFF* */ |
c906108c SS |
440 | /* Names of IDT R3041 registers. */ |
441 | ||
442 | char *mips_r3041_reg_names[] = { | |
c906108c SS |
443 | "sr", "lo", "hi", "bad", "cause","pc", |
444 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
445 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
446 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
447 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 448 | "fsr", "fir", "",/*"fp"*/ "", |
c906108c SS |
449 | "", "", "bus", "ccfg", "", "", "", "", |
450 | "", "", "port", "cmp", "", "", "epc", "prid", | |
451 | }; | |
452 | ||
453 | /* Names of IDT R3051 registers. */ | |
454 | ||
455 | char *mips_r3051_reg_names[] = { | |
c906108c SS |
456 | "sr", "lo", "hi", "bad", "cause","pc", |
457 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
458 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
459 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
460 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 461 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
462 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
463 | "", "", "ehi", "", "", "", "epc", "prid", | |
464 | }; | |
465 | ||
466 | /* Names of IDT R3081 registers. */ | |
467 | ||
468 | char *mips_r3081_reg_names[] = { | |
c906108c SS |
469 | "sr", "lo", "hi", "bad", "cause","pc", |
470 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
471 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
472 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
473 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
a094c6fb | 474 | "fsr", "fir", ""/*"fp"*/, "", |
c906108c SS |
475 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
476 | "", "", "ehi", "", "", "", "epc", "prid", | |
477 | }; | |
478 | ||
479 | /* Names of LSI 33k registers. */ | |
480 | ||
481 | char *mips_lsi33k_reg_names[] = { | |
c906108c SS |
482 | "epc", "hi", "lo", "sr", "cause","badvaddr", |
483 | "dcic", "bpc", "bda", "", "", "", "", "", | |
484 | "", "", "", "", "", "", "", "", | |
485 | "", "", "", "", "", "", "", "", | |
486 | "", "", "", "", "", "", "", "", | |
487 | "", "", "", "", | |
488 | "", "", "", "", "", "", "", "", | |
489 | "", "", "", "", "", "", "", "", | |
490 | }; | |
491 | ||
492 | struct { | |
493 | char *name; | |
494 | char **regnames; | |
495 | } mips_processor_type_table[] = { | |
496 | { "generic", mips_generic_reg_names }, | |
497 | { "r3041", mips_r3041_reg_names }, | |
498 | { "r3051", mips_r3051_reg_names }, | |
499 | { "r3071", mips_r3081_reg_names }, | |
500 | { "r3081", mips_r3081_reg_names }, | |
501 | { "lsi33k", mips_lsi33k_reg_names }, | |
502 | { NULL, NULL } | |
503 | }; | |
9846de1b | 504 | /* *INDENT-ON* */ |
c906108c | 505 | |
c5aa993b JM |
506 | |
507 | ||
508 | ||
c906108c | 509 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
510 | static int mips16_to_32_reg[8] = |
511 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
512 | |
513 | /* Heuristic_proc_start may hunt through the text section for a long | |
514 | time across a 2400 baud serial line. Allows the user to limit this | |
515 | search. */ | |
516 | ||
517 | static unsigned int heuristic_fence_post = 0; | |
518 | ||
c5aa993b JM |
519 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
520 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
521 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
522 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
523 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
524 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
525 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
526 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
527 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
528 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
529 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
530 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
531 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
532 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
533 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
534 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
535 | ||
536 | struct linked_proc_info | |
c5aa993b JM |
537 | { |
538 | struct mips_extra_func_info info; | |
539 | struct linked_proc_info *next; | |
540 | } | |
541 | *linked_proc_desc_table = NULL; | |
c906108c | 542 | |
cce74817 | 543 | void |
acdb74a0 | 544 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
545 | { |
546 | if (fi | |
da50a4b7 AC |
547 | && get_frame_extra_info (fi) |
548 | && get_frame_extra_info (fi)->proc_desc | |
549 | && get_frame_extra_info (fi)->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 550 | printf_filtered (" frame pointer is at %s+%s\n", |
da50a4b7 AC |
551 | REGISTER_NAME (get_frame_extra_info (fi)->proc_desc->pdr.framereg), |
552 | paddr_d (get_frame_extra_info (fi)->proc_desc->pdr.frameoffset)); | |
cce74817 | 553 | } |
c906108c | 554 | |
46cd78fb AC |
555 | /* Number of bytes of storage in the actual machine representation for |
556 | register N. NOTE: This indirectly defines the register size | |
557 | transfered by the GDB protocol. */ | |
43e526b9 JM |
558 | |
559 | static int mips64_transfers_32bit_regs_p = 0; | |
560 | ||
f7ab6ec6 | 561 | static int |
acdb74a0 | 562 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
563 | { |
564 | if (mips64_transfers_32bit_regs_p) | |
565 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
566 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
567 | && FP_REGISTER_DOUBLE) | |
568 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
569 | registers. */ | |
570 | return 8; | |
43e526b9 JM |
571 | else |
572 | return MIPS_REGSIZE; | |
573 | } | |
574 | ||
46cd78fb AC |
575 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
576 | defines the remote-gdb packet. */ | |
577 | ||
d05285fa | 578 | static int |
acdb74a0 | 579 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
580 | { |
581 | if (mips64_transfers_32bit_regs_p) | |
582 | return 0; | |
583 | else | |
584 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
585 | } | |
586 | ||
d05285fa | 587 | static void |
acdb74a0 AC |
588 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
589 | char *raw_buf, char *virt_buf) | |
43e526b9 | 590 | { |
d7449b42 | 591 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
592 | memcpy (virt_buf, |
593 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
594 | TYPE_LENGTH (virtual_type)); | |
595 | else | |
596 | memcpy (virt_buf, | |
597 | raw_buf, | |
598 | TYPE_LENGTH (virtual_type)); | |
599 | } | |
600 | ||
d05285fa | 601 | static void |
acdb74a0 AC |
602 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
603 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
604 | { |
605 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
d7449b42 | 606 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
607 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
608 | virt_buf, | |
609 | TYPE_LENGTH (virtual_type)); | |
610 | else | |
611 | memcpy (raw_buf, | |
612 | virt_buf, | |
613 | TYPE_LENGTH (virtual_type)); | |
614 | } | |
615 | ||
102182a9 MS |
616 | void |
617 | mips_register_convert_to_type (int regnum, struct type *type, char *buffer) | |
618 | { | |
619 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
620 | && REGISTER_RAW_SIZE (regnum) == 4 | |
621 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
622 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
623 | && TYPE_LENGTH(type) == 8) | |
624 | { | |
625 | char temp[4]; | |
626 | memcpy (temp, ((char *)(buffer))+4, 4); | |
627 | memcpy (((char *)(buffer))+4, (buffer), 4); | |
628 | memcpy (((char *)(buffer)), temp, 4); | |
629 | } | |
630 | } | |
631 | ||
632 | void | |
633 | mips_register_convert_from_type (int regnum, struct type *type, char *buffer) | |
634 | { | |
635 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
636 | && REGISTER_RAW_SIZE (regnum) == 4 | |
637 | && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32 | |
638 | && TYPE_CODE(type) == TYPE_CODE_FLT | |
639 | && TYPE_LENGTH(type) == 8) | |
640 | { | |
641 | char temp[4]; | |
642 | memcpy (temp, ((char *)(buffer))+4, 4); | |
643 | memcpy (((char *)(buffer))+4, (buffer), 4); | |
644 | memcpy (((char *)(buffer)), temp, 4); | |
645 | } | |
646 | } | |
647 | ||
78fde5f8 KB |
648 | /* Return the GDB type object for the "standard" data type |
649 | of data in register REG. | |
650 | ||
651 | Note: kevinb/2002-08-01: The definition below should faithfully | |
652 | reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE | |
0ba6dca9 AC |
653 | definitions found in config/mips/tm-*.h. I'm concerned about the |
654 | ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause though. | |
655 | In some cases DEPRECATED_FP_REGNUM is in this range, and I doubt | |
78fde5f8 KB |
656 | that this code is correct for the 64-bit case. */ |
657 | ||
658 | static struct type * | |
659 | mips_register_virtual_type (int reg) | |
660 | { | |
661 | if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32) | |
a6425924 KB |
662 | { |
663 | /* Floating point registers... */ | |
664 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
665 | return builtin_type_ieee_double_big; | |
666 | else | |
667 | return builtin_type_ieee_double_little; | |
668 | } | |
78fde5f8 KB |
669 | else if (reg == PS_REGNUM /* CR */) |
670 | return builtin_type_uint32; | |
671 | else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM) | |
672 | return builtin_type_uint32; | |
673 | else | |
674 | { | |
a6425924 KB |
675 | /* Everything else... |
676 | Return type appropriate for width of register. */ | |
677 | if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64)) | |
678 | return builtin_type_uint64; | |
78fde5f8 | 679 | else |
a6425924 | 680 | return builtin_type_uint32; |
78fde5f8 KB |
681 | } |
682 | } | |
683 | ||
bcb0cc15 MS |
684 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
685 | ||
686 | static CORE_ADDR | |
687 | mips_read_sp (void) | |
688 | { | |
e227b13c | 689 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
690 | } |
691 | ||
c906108c | 692 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 693 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
694 | |
695 | static int | |
696 | mips_mask_address_p (void) | |
697 | { | |
698 | switch (mask_address_var) | |
699 | { | |
7f19b9a2 | 700 | case AUTO_BOOLEAN_TRUE: |
4014092b | 701 | return 1; |
7f19b9a2 | 702 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
703 | return 0; |
704 | break; | |
7f19b9a2 | 705 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 706 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 707 | default: |
8e65ff28 AC |
708 | internal_error (__FILE__, __LINE__, |
709 | "mips_mask_address_p: bad switch"); | |
4014092b | 710 | return -1; |
361d1df0 | 711 | } |
4014092b AC |
712 | } |
713 | ||
714 | static void | |
e9e68a56 | 715 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
716 | { |
717 | switch (mask_address_var) | |
718 | { | |
7f19b9a2 | 719 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
720 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
721 | break; | |
7f19b9a2 | 722 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
723 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
724 | break; | |
7f19b9a2 | 725 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
726 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
727 | mips_mask_address_p () ? "enabled" : "disabled"); | |
728 | break; | |
729 | default: | |
8e65ff28 AC |
730 | internal_error (__FILE__, __LINE__, |
731 | "show_mask_address: bad switch"); | |
4014092b | 732 | break; |
361d1df0 | 733 | } |
4014092b | 734 | } |
c906108c SS |
735 | |
736 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 737 | |
f7ab6ec6 | 738 | static int |
cb811fe7 | 739 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 740 | { |
cb811fe7 MS |
741 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
742 | } | |
743 | ||
f7ab6ec6 | 744 | static int |
cb811fe7 MS |
745 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) |
746 | { | |
b78bcb18 | 747 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
748 | } |
749 | ||
f7ab6ec6 | 750 | static int |
cb811fe7 MS |
751 | mips_o32_use_struct_convention (int gcc_p, struct type *type) |
752 | { | |
753 | return 1; /* Structures are returned by ref in extra arg0. */ | |
c906108c SS |
754 | } |
755 | ||
8b389c40 MS |
756 | /* Should call_function pass struct by reference? |
757 | For each architecture, structs are passed either by | |
758 | value or by reference, depending on their size. */ | |
759 | ||
760 | static int | |
761 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
762 | { | |
763 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
764 | int len = TYPE_LENGTH (check_typedef (type)); | |
765 | ||
766 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
767 | return (len > MIPS_SAVED_REGSIZE); | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
772 | static int | |
773 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
774 | { | |
775 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
776 | } | |
777 | ||
f7ab6ec6 | 778 | static int |
8b389c40 MS |
779 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
780 | { | |
781 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
782 | } | |
783 | ||
c906108c SS |
784 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
785 | ||
786 | static int | |
787 | pc_is_mips16 (bfd_vma memaddr) | |
788 | { | |
789 | struct minimal_symbol *sym; | |
790 | ||
791 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
792 | if (IS_MIPS16_ADDR (memaddr)) | |
793 | return 1; | |
794 | ||
795 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
796 | the high bit of the info field. Use this to decide if the function is | |
797 | MIPS16 or normal MIPS. */ | |
798 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
799 | if (sym) | |
71b8ef93 | 800 | return msymbol_is_special (sym); |
c906108c SS |
801 | else |
802 | return 0; | |
803 | } | |
804 | ||
6c997a34 AC |
805 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
806 | all registers should be sign extended for simplicity? */ | |
807 | ||
808 | static CORE_ADDR | |
39f77062 | 809 | mips_read_pc (ptid_t ptid) |
6c997a34 | 810 | { |
39f77062 | 811 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 812 | } |
c906108c SS |
813 | |
814 | /* This returns the PC of the first inst after the prologue. If we can't | |
815 | find the prologue, then return 0. */ | |
816 | ||
817 | static CORE_ADDR | |
acdb74a0 AC |
818 | after_prologue (CORE_ADDR pc, |
819 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
820 | { |
821 | struct symtab_and_line sal; | |
822 | CORE_ADDR func_addr, func_end; | |
823 | ||
479412cd DJ |
824 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
825 | to read the stack pointer from the current machine state, because | |
826 | the current machine state has nothing to do with the information | |
827 | we need from the proc_desc; and the process may or may not exist | |
828 | right now. */ | |
c906108c | 829 | if (!proc_desc) |
479412cd | 830 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
831 | |
832 | if (proc_desc) | |
833 | { | |
834 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 835 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
836 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
837 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
838 | return 0; | |
839 | } | |
840 | ||
841 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
842 | return 0; /* Unknown */ | |
843 | ||
844 | sal = find_pc_line (func_addr, 0); | |
845 | ||
846 | if (sal.end < func_end) | |
847 | return sal.end; | |
848 | ||
849 | /* The line after the prologue is after the end of the function. In this | |
850 | case, tell the caller to find the prologue the hard way. */ | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
856 | set the appropriate bit in the general register mask or float register mask | |
857 | to indicate which register is saved. This is a helper function | |
858 | for mips_find_saved_regs. */ | |
859 | ||
860 | static void | |
acdb74a0 AC |
861 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
862 | unsigned long *float_mask) | |
c906108c SS |
863 | { |
864 | int reg; | |
865 | ||
866 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
867 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
868 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
869 | { | |
870 | /* It might be possible to use the instruction to | |
c5aa993b JM |
871 | find the offset, rather than the code below which |
872 | is based on things being in a certain order in the | |
873 | frame, but figuring out what the instruction's offset | |
874 | is relative to might be a little tricky. */ | |
c906108c SS |
875 | reg = (inst & 0x001f0000) >> 16; |
876 | *gen_mask |= (1 << reg); | |
877 | } | |
878 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
879 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
880 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
881 | |
882 | { | |
883 | reg = ((inst & 0x001f0000) >> 16); | |
884 | *float_mask |= (1 << reg); | |
885 | } | |
886 | } | |
887 | ||
888 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
889 | set the appropriate bit in the general register or float register mask | |
890 | to indicate which register is saved. This is a helper function | |
891 | for mips_find_saved_regs. */ | |
892 | ||
893 | static void | |
acdb74a0 | 894 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 895 | { |
c5aa993b | 896 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
897 | { |
898 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
899 | *gen_mask |= (1 << reg); | |
900 | } | |
c5aa993b | 901 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
902 | { |
903 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
904 | *gen_mask |= (1 << reg); | |
905 | } | |
c5aa993b | 906 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
907 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
908 | *gen_mask |= (1 << RA_REGNUM); | |
909 | } | |
910 | ||
911 | ||
912 | /* Fetch and return instruction from the specified location. If the PC | |
913 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
914 | ||
915 | static t_inst | |
acdb74a0 | 916 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
917 | { |
918 | char buf[MIPS_INSTLEN]; | |
919 | int instlen; | |
920 | int status; | |
921 | ||
922 | if (pc_is_mips16 (addr)) | |
923 | { | |
924 | instlen = MIPS16_INSTLEN; | |
925 | addr = UNMAKE_MIPS16_ADDR (addr); | |
926 | } | |
927 | else | |
c5aa993b | 928 | instlen = MIPS_INSTLEN; |
c906108c SS |
929 | status = read_memory_nobpt (addr, buf, instlen); |
930 | if (status) | |
931 | memory_error (status, addr); | |
932 | return extract_unsigned_integer (buf, instlen); | |
933 | } | |
934 | ||
935 | ||
936 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
937 | #define mips32_op(x) (x >> 26) |
938 | #define itype_op(x) (x >> 26) | |
939 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 940 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 941 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 942 | |
e135b889 DJ |
943 | #define jtype_op(x) (x >> 26) |
944 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 945 | |
e135b889 DJ |
946 | #define rtype_op(x) (x >> 26) |
947 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
948 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
949 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
950 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
951 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
952 | |
953 | static CORE_ADDR | |
c5aa993b JM |
954 | mips32_relative_offset (unsigned long inst) |
955 | { | |
956 | long x; | |
957 | x = itype_immediate (inst); | |
958 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 959 | { |
c5aa993b | 960 | x |= 0xffff0000; /* sign extension */ |
c906108c | 961 | } |
c5aa993b JM |
962 | x = x << 2; |
963 | return x; | |
c906108c SS |
964 | } |
965 | ||
966 | /* Determine whate to set a single step breakpoint while considering | |
967 | branch prediction */ | |
5a89d8aa | 968 | static CORE_ADDR |
c5aa993b JM |
969 | mips32_next_pc (CORE_ADDR pc) |
970 | { | |
971 | unsigned long inst; | |
972 | int op; | |
973 | inst = mips_fetch_instruction (pc); | |
e135b889 | 974 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 975 | { |
e135b889 DJ |
976 | if (itype_op (inst) >> 2 == 5) |
977 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 978 | { |
e135b889 | 979 | op = (itype_op (inst) & 0x03); |
c906108c SS |
980 | switch (op) |
981 | { | |
e135b889 DJ |
982 | case 0: /* BEQL */ |
983 | goto equal_branch; | |
984 | case 1: /* BNEL */ | |
985 | goto neq_branch; | |
986 | case 2: /* BLEZL */ | |
987 | goto less_branch; | |
988 | case 3: /* BGTZ */ | |
989 | goto greater_branch; | |
c5aa993b JM |
990 | default: |
991 | pc += 4; | |
c906108c SS |
992 | } |
993 | } | |
e135b889 DJ |
994 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
995 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
996 | { | |
997 | int tf = itype_rt (inst) & 0x01; | |
998 | int cnum = itype_rt (inst) >> 2; | |
999 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
1000 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
1001 | ||
1002 | if (((cond >> cnum) & 0x01) == tf) | |
1003 | pc += mips32_relative_offset (inst) + 4; | |
1004 | else | |
1005 | pc += 8; | |
1006 | } | |
c5aa993b JM |
1007 | else |
1008 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1009 | } |
1010 | else | |
c5aa993b JM |
1011 | { /* This gets way messy */ |
1012 | ||
c906108c | 1013 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1014 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1015 | { |
c5aa993b JM |
1016 | case 0: /* SPECIAL */ |
1017 | op = rtype_funct (inst); | |
1018 | switch (op) | |
1019 | { | |
1020 | case 8: /* JR */ | |
1021 | case 9: /* JALR */ | |
6c997a34 AC |
1022 | /* Set PC to that address */ |
1023 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1024 | break; |
1025 | default: | |
1026 | pc += 4; | |
1027 | } | |
1028 | ||
e135b889 | 1029 | break; /* end SPECIAL */ |
c5aa993b | 1030 | case 1: /* REGIMM */ |
c906108c | 1031 | { |
e135b889 DJ |
1032 | op = itype_rt (inst); /* branch condition */ |
1033 | switch (op) | |
c906108c | 1034 | { |
c5aa993b | 1035 | case 0: /* BLTZ */ |
e135b889 DJ |
1036 | case 2: /* BLTZL */ |
1037 | case 16: /* BLTZAL */ | |
c5aa993b | 1038 | case 18: /* BLTZALL */ |
c906108c | 1039 | less_branch: |
6c997a34 | 1040 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1041 | pc += mips32_relative_offset (inst) + 4; |
1042 | else | |
1043 | pc += 8; /* after the delay slot */ | |
1044 | break; | |
e135b889 | 1045 | case 1: /* BGEZ */ |
c5aa993b JM |
1046 | case 3: /* BGEZL */ |
1047 | case 17: /* BGEZAL */ | |
1048 | case 19: /* BGEZALL */ | |
c906108c | 1049 | greater_equal_branch: |
6c997a34 | 1050 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1051 | pc += mips32_relative_offset (inst) + 4; |
1052 | else | |
1053 | pc += 8; /* after the delay slot */ | |
1054 | break; | |
e135b889 | 1055 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1056 | default: |
1057 | pc += 4; | |
c906108c SS |
1058 | } |
1059 | } | |
e135b889 | 1060 | break; /* end REGIMM */ |
c5aa993b JM |
1061 | case 2: /* J */ |
1062 | case 3: /* JAL */ | |
1063 | { | |
1064 | unsigned long reg; | |
1065 | reg = jtype_target (inst) << 2; | |
e135b889 | 1066 | /* Upper four bits get never changed... */ |
c5aa993b | 1067 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1068 | } |
c5aa993b JM |
1069 | break; |
1070 | /* FIXME case JALX : */ | |
1071 | { | |
1072 | unsigned long reg; | |
1073 | reg = jtype_target (inst) << 2; | |
1074 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1075 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1076 | } | |
c5aa993b | 1077 | break; /* The new PC will be alternate mode */ |
e135b889 | 1078 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1079 | equal_branch: |
6c997a34 AC |
1080 | if (read_signed_register (itype_rs (inst)) == |
1081 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1082 | pc += mips32_relative_offset (inst) + 4; |
1083 | else | |
1084 | pc += 8; | |
1085 | break; | |
e135b889 | 1086 | case 5: /* BNE, BNEL */ |
c5aa993b | 1087 | neq_branch: |
6c997a34 | 1088 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1089 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1090 | pc += mips32_relative_offset (inst) + 4; |
1091 | else | |
1092 | pc += 8; | |
1093 | break; | |
e135b889 | 1094 | case 6: /* BLEZ, BLEZL */ |
c906108c | 1095 | less_zero_branch: |
6c997a34 | 1096 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1097 | pc += mips32_relative_offset (inst) + 4; |
1098 | else | |
1099 | pc += 8; | |
1100 | break; | |
1101 | case 7: | |
e135b889 DJ |
1102 | default: |
1103 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1104 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1105 | pc += mips32_relative_offset (inst) + 4; |
1106 | else | |
1107 | pc += 8; | |
1108 | break; | |
c5aa993b JM |
1109 | } /* switch */ |
1110 | } /* else */ | |
1111 | return pc; | |
1112 | } /* mips32_next_pc */ | |
c906108c SS |
1113 | |
1114 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1115 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1116 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1117 | We dont want to set a single step instruction on the extend instruction | |
1118 | either. | |
c5aa993b | 1119 | */ |
c906108c SS |
1120 | |
1121 | /* Lots of mips16 instruction formats */ | |
1122 | /* Predicting jumps requires itype,ritype,i8type | |
1123 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1124 | */ |
c906108c SS |
1125 | enum mips16_inst_fmts |
1126 | { | |
c5aa993b JM |
1127 | itype, /* 0 immediate 5,10 */ |
1128 | ritype, /* 1 5,3,8 */ | |
1129 | rrtype, /* 2 5,3,3,5 */ | |
1130 | rritype, /* 3 5,3,3,5 */ | |
1131 | rrrtype, /* 4 5,3,3,3,2 */ | |
1132 | rriatype, /* 5 5,3,3,1,4 */ | |
1133 | shifttype, /* 6 5,3,3,3,2 */ | |
1134 | i8type, /* 7 5,3,8 */ | |
1135 | i8movtype, /* 8 5,3,3,5 */ | |
1136 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1137 | i64type, /* 10 5,3,8 */ | |
1138 | ri64type, /* 11 5,3,3,5 */ | |
1139 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1140 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1141 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1142 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1143 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1144 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1145 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1146 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1147 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1148 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1149 | }; | |
12f02c2a AC |
1150 | /* I am heaping all the fields of the formats into one structure and |
1151 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1152 | struct upk_mips16 |
c5aa993b | 1153 | { |
12f02c2a | 1154 | CORE_ADDR offset; |
c5aa993b JM |
1155 | unsigned int regx; /* Function in i8 type */ |
1156 | unsigned int regy; | |
1157 | }; | |
c906108c SS |
1158 | |
1159 | ||
12f02c2a AC |
1160 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1161 | for the bits which make up the immediatate extension. */ | |
c906108c | 1162 | |
12f02c2a AC |
1163 | static CORE_ADDR |
1164 | extended_offset (unsigned int extension) | |
c906108c | 1165 | { |
12f02c2a | 1166 | CORE_ADDR value; |
c5aa993b JM |
1167 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1168 | value = value << 6; | |
1169 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1170 | value = value << 5; | |
1171 | value |= extension & 0x01f; /* extract 4:0 */ | |
1172 | return value; | |
c906108c SS |
1173 | } |
1174 | ||
1175 | /* Only call this function if you know that this is an extendable | |
1176 | instruction, It wont malfunction, but why make excess remote memory references? | |
1177 | If the immediate operands get sign extended or somthing, do it after | |
1178 | the extension is performed. | |
c5aa993b | 1179 | */ |
c906108c SS |
1180 | /* FIXME: Every one of these cases needs to worry about sign extension |
1181 | when the offset is to be used in relative addressing */ | |
1182 | ||
1183 | ||
12f02c2a | 1184 | static unsigned int |
c5aa993b | 1185 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1186 | { |
c5aa993b JM |
1187 | char buf[8]; |
1188 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1189 | target_read_memory (pc, buf, 2); | |
1190 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1191 | } |
1192 | ||
1193 | static void | |
c5aa993b | 1194 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1195 | unsigned int extension, |
1196 | unsigned int inst, | |
1197 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1198 | struct upk_mips16 *upk) |
c906108c | 1199 | { |
12f02c2a AC |
1200 | CORE_ADDR offset; |
1201 | int regx; | |
1202 | int regy; | |
1203 | switch (insn_format) | |
c906108c | 1204 | { |
c5aa993b | 1205 | case itype: |
c906108c | 1206 | { |
12f02c2a AC |
1207 | CORE_ADDR value; |
1208 | if (extension) | |
c5aa993b JM |
1209 | { |
1210 | value = extended_offset (extension); | |
1211 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1212 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1213 | } |
1214 | else | |
c5aa993b | 1215 | { |
12f02c2a | 1216 | value = inst & 0x7ff; |
c5aa993b | 1217 | /* FIXME : Consider sign extension */ |
c906108c | 1218 | } |
12f02c2a AC |
1219 | offset = value; |
1220 | regx = -1; | |
1221 | regy = -1; | |
c906108c | 1222 | } |
c5aa993b JM |
1223 | break; |
1224 | case ritype: | |
1225 | case i8type: | |
1226 | { /* A register identifier and an offset */ | |
c906108c SS |
1227 | /* Most of the fields are the same as I type but the |
1228 | immediate value is of a different length */ | |
12f02c2a AC |
1229 | CORE_ADDR value; |
1230 | if (extension) | |
c906108c | 1231 | { |
c5aa993b JM |
1232 | value = extended_offset (extension); |
1233 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1234 | value |= inst & 0xff; /* eleven bits from instruction */ |
1235 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1236 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1237 | { | |
1238 | value &= ~0x3fff; /* remove the sign bit */ | |
1239 | value = -value; | |
c906108c SS |
1240 | } |
1241 | } | |
c5aa993b JM |
1242 | else |
1243 | { | |
12f02c2a AC |
1244 | value = inst & 0xff; /* 8 bits */ |
1245 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1246 | /* FIXME: Do sign extension , this format needs it */ |
1247 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1248 | { | |
1249 | value &= 0xef; /* remove the sign bit */ | |
1250 | value = -value; | |
1251 | } | |
c5aa993b | 1252 | } |
12f02c2a AC |
1253 | offset = value; |
1254 | regy = -1; | |
c5aa993b | 1255 | break; |
c906108c | 1256 | } |
c5aa993b | 1257 | case jalxtype: |
c906108c | 1258 | { |
c5aa993b | 1259 | unsigned long value; |
12f02c2a AC |
1260 | unsigned int nexthalf; |
1261 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1262 | value = value << 16; |
1263 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1264 | value |= nexthalf; | |
12f02c2a AC |
1265 | offset = value; |
1266 | regx = -1; | |
1267 | regy = -1; | |
c5aa993b | 1268 | break; |
c906108c SS |
1269 | } |
1270 | default: | |
8e65ff28 AC |
1271 | internal_error (__FILE__, __LINE__, |
1272 | "bad switch"); | |
c906108c | 1273 | } |
12f02c2a AC |
1274 | upk->offset = offset; |
1275 | upk->regx = regx; | |
1276 | upk->regy = regy; | |
c906108c SS |
1277 | } |
1278 | ||
1279 | ||
c5aa993b JM |
1280 | static CORE_ADDR |
1281 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1282 | { |
c5aa993b | 1283 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1284 | } |
1285 | ||
12f02c2a AC |
1286 | static CORE_ADDR |
1287 | extended_mips16_next_pc (CORE_ADDR pc, | |
1288 | unsigned int extension, | |
1289 | unsigned int insn) | |
c906108c | 1290 | { |
12f02c2a AC |
1291 | int op = (insn >> 11); |
1292 | switch (op) | |
c906108c | 1293 | { |
12f02c2a AC |
1294 | case 2: /* Branch */ |
1295 | { | |
1296 | CORE_ADDR offset; | |
1297 | struct upk_mips16 upk; | |
1298 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1299 | offset = upk.offset; | |
1300 | if (offset & 0x800) | |
1301 | { | |
1302 | offset &= 0xeff; | |
1303 | offset = -offset; | |
1304 | } | |
1305 | pc += (offset << 1) + 2; | |
1306 | break; | |
1307 | } | |
1308 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1309 | { | |
1310 | struct upk_mips16 upk; | |
1311 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1312 | pc = add_offset_16 (pc, upk.offset); | |
1313 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1314 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1315 | else | |
1316 | pc |= 0x01; | |
1317 | break; | |
1318 | } | |
1319 | case 4: /* beqz */ | |
1320 | { | |
1321 | struct upk_mips16 upk; | |
1322 | int reg; | |
1323 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1324 | reg = read_signed_register (upk.regx); | |
1325 | if (reg == 0) | |
1326 | pc += (upk.offset << 1) + 2; | |
1327 | else | |
1328 | pc += 2; | |
1329 | break; | |
1330 | } | |
1331 | case 5: /* bnez */ | |
1332 | { | |
1333 | struct upk_mips16 upk; | |
1334 | int reg; | |
1335 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1336 | reg = read_signed_register (upk.regx); | |
1337 | if (reg != 0) | |
1338 | pc += (upk.offset << 1) + 2; | |
1339 | else | |
1340 | pc += 2; | |
1341 | break; | |
1342 | } | |
1343 | case 12: /* I8 Formats btez btnez */ | |
1344 | { | |
1345 | struct upk_mips16 upk; | |
1346 | int reg; | |
1347 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1348 | /* upk.regx contains the opcode */ | |
1349 | reg = read_signed_register (24); /* Test register is 24 */ | |
1350 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1351 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1352 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1353 | pc += (upk.offset << 1) + 2; | |
1354 | else | |
1355 | pc += 2; | |
1356 | break; | |
1357 | } | |
1358 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1359 | { | |
1360 | struct upk_mips16 upk; | |
1361 | /* upk.fmt = rrtype; */ | |
1362 | op = insn & 0x1f; | |
1363 | if (op == 0) | |
c5aa993b | 1364 | { |
12f02c2a AC |
1365 | int reg; |
1366 | upk.regx = (insn >> 8) & 0x07; | |
1367 | upk.regy = (insn >> 5) & 0x07; | |
1368 | switch (upk.regy) | |
c5aa993b | 1369 | { |
12f02c2a AC |
1370 | case 0: |
1371 | reg = upk.regx; | |
1372 | break; | |
1373 | case 1: | |
1374 | reg = 31; | |
1375 | break; /* Function return instruction */ | |
1376 | case 2: | |
1377 | reg = upk.regx; | |
1378 | break; | |
1379 | default: | |
1380 | reg = 31; | |
1381 | break; /* BOGUS Guess */ | |
c906108c | 1382 | } |
12f02c2a | 1383 | pc = read_signed_register (reg); |
c906108c | 1384 | } |
12f02c2a | 1385 | else |
c5aa993b | 1386 | pc += 2; |
12f02c2a AC |
1387 | break; |
1388 | } | |
1389 | case 30: | |
1390 | /* This is an instruction extension. Fetch the real instruction | |
1391 | (which follows the extension) and decode things based on | |
1392 | that. */ | |
1393 | { | |
1394 | pc += 2; | |
1395 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1396 | break; | |
1397 | } | |
1398 | default: | |
1399 | { | |
1400 | pc += 2; | |
1401 | break; | |
1402 | } | |
c906108c | 1403 | } |
c5aa993b | 1404 | return pc; |
12f02c2a | 1405 | } |
c906108c | 1406 | |
5a89d8aa | 1407 | static CORE_ADDR |
12f02c2a AC |
1408 | mips16_next_pc (CORE_ADDR pc) |
1409 | { | |
1410 | unsigned int insn = fetch_mips_16 (pc); | |
1411 | return extended_mips16_next_pc (pc, 0, insn); | |
1412 | } | |
1413 | ||
1414 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1415 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1416 | It works by decoding the current instruction and predicting where a |
1417 | branch will go. This isnt hard because all the data is available. | |
1418 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1419 | CORE_ADDR |
1420 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1421 | { |
c5aa993b JM |
1422 | if (pc & 0x01) |
1423 | return mips16_next_pc (pc); | |
1424 | else | |
1425 | return mips32_next_pc (pc); | |
12f02c2a | 1426 | } |
c906108c | 1427 | |
e0f7ec59 AC |
1428 | /* Set up the 'saved_regs' array. This is a data structure containing |
1429 | the addresses on the stack where each register has been saved, for | |
1430 | each stack frame. Registers that have not been saved will have | |
1431 | zero here. The stack pointer register is special: rather than the | |
1432 | address where the stack register has been saved, | |
1433 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1434 | frame's stack register. */ | |
c906108c | 1435 | |
d28e01f4 | 1436 | static void |
acdb74a0 | 1437 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1438 | { |
1439 | int ireg; | |
c906108c SS |
1440 | /* r0 bit means kernel trap */ |
1441 | int kernel_trap; | |
1442 | /* What registers have been saved? Bitmasks. */ | |
1443 | unsigned long gen_mask, float_mask; | |
1444 | mips_extra_func_info_t proc_desc; | |
1445 | t_inst inst; | |
e0f7ec59 | 1446 | CORE_ADDR *saved_regs; |
c906108c | 1447 | |
e0f7ec59 AC |
1448 | if (get_frame_saved_regs (fci) != NULL) |
1449 | return; | |
1450 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1451 | |
1452 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1453 | in a sigcontext structure somewhere on the stack. If the stack |
1454 | layout for sigtramp changes we might have to change these | |
1455 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1456 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1457 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1458 | above the sigtramp frame. */ | |
c906108c SS |
1459 | #define SIGFRAME_BASE MIPS_REGSIZE |
1460 | /* FIXME! Are these correct?? */ | |
1461 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1462 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1463 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1464 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1465 | #endif | |
1466 | #ifndef SIGFRAME_REG_SIZE | |
e0f7ec59 | 1467 | /* FIXME! Is this correct?? */ |
c906108c SS |
1468 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE |
1469 | #endif | |
5a203e44 | 1470 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1471 | { |
1472 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1473 | { | |
e0f7ec59 AC |
1474 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
1475 | + ireg * SIGFRAME_REG_SIZE); | |
1476 | set_reg_offset (saved_regs, ireg, reg_position); | |
c906108c SS |
1477 | } |
1478 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1479 | { | |
e0f7ec59 AC |
1480 | CORE_ADDR reg_position = (get_frame_base (fci) |
1481 | + SIGFRAME_FPREGSAVE_OFF | |
1482 | + ireg * SIGFRAME_REG_SIZE); | |
1483 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position); | |
c906108c | 1484 | } |
e0f7ec59 AC |
1485 | |
1486 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1487 | /* SP_REGNUM, contains the value and not the address. */ | |
1488 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1489 | return; |
1490 | } | |
1491 | ||
da50a4b7 | 1492 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1493 | if (proc_desc == NULL) |
e0f7ec59 AC |
1494 | /* I'm not sure how/whether this can happen. Normally when we |
1495 | can't find a proc_desc, we "synthesize" one using | |
1496 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1497 | return; |
1498 | ||
c5aa993b JM |
1499 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1500 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1501 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1502 | |
e0f7ec59 AC |
1503 | if (/* In any frame other than the innermost or a frame interrupted |
1504 | by a signal, we assume that all registers have been saved. | |
1505 | This assumes that all register saves in a function happen | |
1506 | before the first function call. */ | |
11c02a10 AC |
1507 | (get_next_frame (fci) == NULL |
1508 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1509 | |
e0f7ec59 | 1510 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1511 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1512 | |
e0f7ec59 AC |
1513 | /* Don't bother unless we are inside a function prologue. |
1514 | Outside the prologue, we know where everything is. */ | |
c906108c | 1515 | |
50abf9e5 | 1516 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1517 | |
e0f7ec59 AC |
1518 | /* Not sure exactly what kernel_trap means, but if it means the |
1519 | kernel saves the registers without a prologue doing it, we | |
1520 | better not examine the prologue to see whether registers | |
1521 | have been saved yet. */ | |
c5aa993b | 1522 | && !kernel_trap) |
c906108c | 1523 | { |
e0f7ec59 AC |
1524 | /* We need to figure out whether the registers that the |
1525 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1526 | |
1527 | CORE_ADDR addr; | |
1528 | ||
1529 | /* Bitmasks; set if we have found a save for the register. */ | |
1530 | unsigned long gen_save_found = 0; | |
1531 | unsigned long float_save_found = 0; | |
1532 | int instlen; | |
1533 | ||
1534 | /* If the address is odd, assume this is MIPS16 code. */ | |
1535 | addr = PROC_LOW_ADDR (proc_desc); | |
1536 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1537 | ||
e0f7ec59 AC |
1538 | /* Scan through this function's instructions preceding the |
1539 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1540 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1541 | { |
1542 | inst = mips_fetch_instruction (addr); | |
1543 | if (pc_is_mips16 (addr)) | |
1544 | mips16_decode_reg_save (inst, &gen_save_found); | |
1545 | else | |
1546 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1547 | addr += instlen; | |
1548 | } | |
1549 | gen_mask = gen_save_found; | |
1550 | float_mask = float_save_found; | |
1551 | } | |
1552 | ||
e0f7ec59 AC |
1553 | /* Fill in the offsets for the registers which gen_mask says were |
1554 | saved. */ | |
1555 | { | |
1556 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1557 | + PROC_REG_OFFSET (proc_desc)); | |
1558 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1559 | if (gen_mask & 0x80000000) | |
1560 | { | |
1561 | set_reg_offset (saved_regs, ireg, reg_position); | |
1562 | reg_position -= MIPS_SAVED_REGSIZE; | |
1563 | } | |
1564 | } | |
c906108c | 1565 | |
e0f7ec59 AC |
1566 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1567 | order of that normally used by gcc. Therefore, we have to fetch | |
1568 | the first instruction of the function, and if it's an entry | |
1569 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1570 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1571 | { | |
1572 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1573 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1574 | /* entry */ | |
c906108c SS |
1575 | { |
1576 | int reg; | |
1577 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1578 | |
c906108c | 1579 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1580 | CORE_ADDR reg_position = (get_frame_base (fci) |
1581 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1582 | if (inst & 0x20) |
7a292a7a | 1583 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1584 | |
e0f7ec59 AC |
1585 | /* Check if the s0 and s1 registers were pushed on the |
1586 | stack. */ | |
c5aa993b | 1587 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1588 | { |
e0f7ec59 | 1589 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1590 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1591 | } |
1592 | } | |
1593 | } | |
1594 | ||
e0f7ec59 AC |
1595 | /* Fill in the offsets for the registers which float_mask says were |
1596 | saved. */ | |
1597 | { | |
1598 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1599 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1600 | |
e0f7ec59 AC |
1601 | /* Apparently, the freg_offset gives the offset to the first 64 |
1602 | bit saved. | |
6acdf5c7 | 1603 | |
e0f7ec59 AC |
1604 | When the ABI specifies 64 bit saved registers, the FREG_OFFSET |
1605 | designates the first saved 64 bit register. | |
6acdf5c7 | 1606 | |
e0f7ec59 AC |
1607 | When the ABI specifies 32 bit saved registers, the ``64 bit |
1608 | saved DOUBLE'' consists of two adjacent 32 bit registers, Hence | |
1609 | FREG_OFFSET, designates the address of the lower register of | |
1610 | the register pair. Adjust the offset so that it designates the | |
1611 | upper register of the pair -- i.e., the address of the first | |
1612 | saved 32 bit register. */ | |
c906108c | 1613 | |
e0f7ec59 AC |
1614 | if (MIPS_SAVED_REGSIZE == 4) |
1615 | reg_position += MIPS_SAVED_REGSIZE; | |
c906108c | 1616 | |
e0f7ec59 AC |
1617 | /* Fill in the offsets for the float registers which float_mask |
1618 | says were saved. */ | |
1619 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1620 | if (float_mask & 0x80000000) | |
1621 | { | |
1622 | set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position); | |
1623 | reg_position -= MIPS_SAVED_REGSIZE; | |
1624 | } | |
c906108c | 1625 | |
e0f7ec59 AC |
1626 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1627 | } | |
d28e01f4 | 1628 | |
e0f7ec59 AC |
1629 | /* SP_REGNUM, contains the value and not the address. */ |
1630 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1631 | } |
1632 | ||
c906108c | 1633 | static CORE_ADDR |
acdb74a0 | 1634 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1635 | { |
64159455 AC |
1636 | int optimized; |
1637 | CORE_ADDR addr; | |
1638 | int realnum; | |
1639 | enum lval_type lval; | |
d9d9c31f | 1640 | char raw_buffer[MAX_REGISTER_SIZE]; |
f796e4be KB |
1641 | |
1642 | if (fi == NULL) | |
c906108c | 1643 | { |
f796e4be KB |
1644 | regcache_cooked_read (current_regcache, regno, raw_buffer); |
1645 | } | |
1646 | else | |
1647 | { | |
1648 | frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum, | |
1649 | raw_buffer); | |
1650 | /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS | |
1651 | should have a pseudo register range that correspons to the ABI's, | |
1652 | rather than the ISA's, view of registers. These registers would | |
1653 | then implicitly describe their size and hence could be used | |
1654 | without the below munging. */ | |
1655 | if (lval == lval_memory) | |
c906108c | 1656 | { |
f796e4be KB |
1657 | if (regno < 32) |
1658 | { | |
1659 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
1660 | saved. */ | |
1661 | return read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
1662 | } | |
c906108c SS |
1663 | } |
1664 | } | |
64159455 AC |
1665 | |
1666 | return extract_signed_integer (raw_buffer, REGISTER_VIRTUAL_SIZE (regno)); | |
c906108c SS |
1667 | } |
1668 | ||
1669 | /* mips_addr_bits_remove - remove useless address bits */ | |
1670 | ||
875e1767 | 1671 | static CORE_ADDR |
acdb74a0 | 1672 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1673 | { |
5213ab06 AC |
1674 | if (GDB_TARGET_IS_MIPS64) |
1675 | { | |
4014092b | 1676 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1677 | { |
1678 | /* This hack is a work-around for existing boards using | |
1679 | PMON, the simulator, and any other 64-bit targets that | |
1680 | doesn't have true 64-bit addressing. On these targets, | |
1681 | the upper 32 bits of addresses are ignored by the | |
1682 | hardware. Thus, the PC or SP are likely to have been | |
1683 | sign extended to all 1s by instruction sequences that | |
1684 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1685 | code that loads an address is this: |
1686 | lui $r2, <upper 16 bits> | |
1687 | ori $r2, <lower 16 bits> | |
1688 | But the lui sign-extends the value such that the upper 32 | |
1689 | bits may be all 1s. The workaround is simply to mask off | |
1690 | these bits. In the future, gcc may be changed to support | |
1691 | true 64-bit addressing, and this masking will have to be | |
1692 | disabled. */ | |
5213ab06 AC |
1693 | addr &= (CORE_ADDR) 0xffffffff; |
1694 | } | |
1695 | } | |
4014092b | 1696 | else if (mips_mask_address_p ()) |
5213ab06 | 1697 | { |
4014092b AC |
1698 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1699 | masking off bits, instead, the actual target should be asking | |
1700 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1701 | /* Even when GDB is configured for some 32-bit targets |
1702 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1703 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1704 | useless bits from addresses. */ | |
c5aa993b | 1705 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1706 | } |
c906108c SS |
1707 | return addr; |
1708 | } | |
1709 | ||
9022177c DJ |
1710 | /* mips_software_single_step() is called just before we want to resume |
1711 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1712 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1713 | the target of the coming instruction and breakpoint it. |
1714 | ||
1715 | single_step is also called just after the inferior stops. If we had | |
1716 | set up a simulated single-step, we undo our damage. */ | |
1717 | ||
1718 | void | |
1719 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1720 | { | |
1721 | static CORE_ADDR next_pc; | |
1722 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1723 | static binsn_quantum break_mem; | |
1724 | CORE_ADDR pc; | |
1725 | ||
1726 | if (insert_breakpoints_p) | |
1727 | { | |
1728 | pc = read_register (PC_REGNUM); | |
1729 | next_pc = mips_next_pc (pc); | |
1730 | ||
1731 | target_insert_breakpoint (next_pc, break_mem); | |
1732 | } | |
1733 | else | |
1734 | target_remove_breakpoint (next_pc, break_mem); | |
1735 | } | |
1736 | ||
97f46953 | 1737 | static CORE_ADDR |
acdb74a0 | 1738 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1739 | { |
1740 | CORE_ADDR pc, tmp; | |
1741 | ||
11c02a10 | 1742 | pc = ((fromleaf) |
6913c89a | 1743 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1744 | : get_next_frame (prev) |
8bedc050 | 1745 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1746 | : read_pc ()); |
5a89d8aa | 1747 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1748 | return tmp ? tmp : pc; |
c906108c SS |
1749 | } |
1750 | ||
1751 | ||
f7ab6ec6 | 1752 | static CORE_ADDR |
acdb74a0 | 1753 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1754 | { |
1755 | CORE_ADDR saved_pc; | |
da50a4b7 | 1756 | mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc; |
c906108c SS |
1757 | /* We have to get the saved pc from the sigcontext |
1758 | if it is a signal handler frame. */ | |
5a203e44 | 1759 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME) ? PC_REGNUM |
c5aa993b | 1760 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1761 | |
50abf9e5 | 1762 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
1763 | { |
1764 | LONGEST tmp; | |
1765 | frame_unwind_signed_register (frame, PC_REGNUM, &tmp); | |
1766 | saved_pc = tmp; | |
1767 | } | |
1768 | else if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1e2330ba | 1769 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1770 | else |
7a292a7a | 1771 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1772 | |
1773 | return ADDR_BITS_REMOVE (saved_pc); | |
1774 | } | |
1775 | ||
1776 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1777 | |
1778 | /* This hack will go away once the get_prev_frame() code has been | |
1779 | modified to set the frame's type first. That is BEFORE init extra | |
1780 | frame info et.al. is called. This is because it will become | |
1781 | possible to skip the init extra info call for sigtramp and dummy | |
1782 | frames. */ | |
1783 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1784 | |
e0f7ec59 AC |
1785 | /* Set a register's saved stack address in temp_saved_regs. If an |
1786 | address has already been set for this register, do nothing; this | |
1787 | way we will only recognize the first save of a given register in a | |
1788 | function prologue. */ | |
c906108c SS |
1789 | |
1790 | static void | |
e0f7ec59 | 1791 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1792 | { |
e0f7ec59 AC |
1793 | if (saved_regs[regno] == 0) |
1794 | saved_regs[regno] = offset; | |
c906108c SS |
1795 | } |
1796 | ||
1797 | ||
1798 | /* Test whether the PC points to the return instruction at the | |
1799 | end of a function. */ | |
1800 | ||
c5aa993b | 1801 | static int |
acdb74a0 | 1802 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1803 | { |
1804 | if (pc_is_mips16 (pc)) | |
1805 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1806 | generates a "jr $ra"; other times it generates code to load | |
1807 | the return address from the stack to an accessible register (such | |
1808 | as $a3), then a "jr" using that register. This second case | |
1809 | is almost impossible to distinguish from an indirect jump | |
1810 | used for switch statements, so we don't even try. */ | |
1811 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1812 | else | |
1813 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1814 | } | |
1815 | ||
1816 | ||
1817 | /* This fencepost looks highly suspicious to me. Removing it also | |
1818 | seems suspicious as it could affect remote debugging across serial | |
1819 | lines. */ | |
1820 | ||
1821 | static CORE_ADDR | |
acdb74a0 | 1822 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1823 | { |
c5aa993b JM |
1824 | CORE_ADDR start_pc; |
1825 | CORE_ADDR fence; | |
1826 | int instlen; | |
1827 | int seen_adjsp = 0; | |
c906108c | 1828 | |
c5aa993b JM |
1829 | pc = ADDR_BITS_REMOVE (pc); |
1830 | start_pc = pc; | |
1831 | fence = start_pc - heuristic_fence_post; | |
1832 | if (start_pc == 0) | |
1833 | return 0; | |
c906108c | 1834 | |
c5aa993b JM |
1835 | if (heuristic_fence_post == UINT_MAX |
1836 | || fence < VM_MIN_ADDRESS) | |
1837 | fence = VM_MIN_ADDRESS; | |
c906108c | 1838 | |
c5aa993b | 1839 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1840 | |
c5aa993b JM |
1841 | /* search back for previous return */ |
1842 | for (start_pc -= instlen;; start_pc -= instlen) | |
1843 | if (start_pc < fence) | |
1844 | { | |
1845 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1846 | stop_soon, but with this test, at least we |
c5aa993b JM |
1847 | don't print out warnings for every child forked (eg, on |
1848 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1849 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1850 | { |
c5aa993b JM |
1851 | static int blurb_printed = 0; |
1852 | ||
1853 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1854 | paddr_nz (pc)); | |
1855 | ||
1856 | if (!blurb_printed) | |
c906108c | 1857 | { |
c5aa993b JM |
1858 | /* This actually happens frequently in embedded |
1859 | development, when you first connect to a board | |
1860 | and your stack pointer and pc are nowhere in | |
1861 | particular. This message needs to give people | |
1862 | in that situation enough information to | |
1863 | determine that it's no big deal. */ | |
1864 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1865 | GDB is unable to find the start of the function at 0x%s\n\ |
1866 | and thus can't determine the size of that function's stack frame.\n\ | |
1867 | This means that GDB may be unable to access that stack frame, or\n\ | |
1868 | the frames below it.\n\ | |
1869 | This problem is most likely caused by an invalid program counter or\n\ | |
1870 | stack pointer.\n\ | |
1871 | However, if you think GDB should simply search farther back\n\ | |
1872 | from 0x%s for code which looks like the beginning of a\n\ | |
1873 | function, you can increase the range of the search using the `set\n\ | |
1874 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1875 | paddr_nz (pc), paddr_nz (pc)); |
1876 | blurb_printed = 1; | |
c906108c | 1877 | } |
c906108c SS |
1878 | } |
1879 | ||
c5aa993b JM |
1880 | return 0; |
1881 | } | |
1882 | else if (pc_is_mips16 (start_pc)) | |
1883 | { | |
1884 | unsigned short inst; | |
1885 | ||
1886 | /* On MIPS16, any one of the following is likely to be the | |
1887 | start of a function: | |
1888 | entry | |
1889 | addiu sp,-n | |
1890 | daddiu sp,-n | |
1891 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1892 | inst = mips_fetch_instruction (start_pc); | |
1893 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1894 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1895 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1896 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1897 | break; | |
1898 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1899 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1900 | seen_adjsp = 1; | |
1901 | else | |
1902 | seen_adjsp = 0; | |
1903 | } | |
1904 | else if (mips_about_to_return (start_pc)) | |
1905 | { | |
1906 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1907 | break; | |
1908 | } | |
1909 | ||
c5aa993b | 1910 | return start_pc; |
c906108c SS |
1911 | } |
1912 | ||
1913 | /* Fetch the immediate value from a MIPS16 instruction. | |
1914 | If the previous instruction was an EXTEND, use it to extend | |
1915 | the upper bits of the immediate value. This is a helper function | |
1916 | for mips16_heuristic_proc_desc. */ | |
1917 | ||
1918 | static int | |
acdb74a0 AC |
1919 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1920 | unsigned short inst, /* current instruction */ | |
1921 | int nbits, /* number of bits in imm field */ | |
1922 | int scale, /* scale factor to be applied to imm */ | |
1923 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1924 | { |
1925 | int offset; | |
1926 | ||
1927 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1928 | { | |
1929 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1930 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1931 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1932 | return offset | (inst & 0x1f); | |
1933 | } | |
1934 | else | |
1935 | { | |
1936 | int max_imm = 1 << nbits; | |
1937 | int mask = max_imm - 1; | |
1938 | int sign_bit = max_imm >> 1; | |
1939 | ||
1940 | offset = inst & mask; | |
1941 | if (is_signed && (offset & sign_bit)) | |
1942 | offset = 0 - (max_imm - offset); | |
1943 | return offset * scale; | |
1944 | } | |
1945 | } | |
1946 | ||
1947 | ||
1948 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1949 | stream from start_pc to limit_pc. */ | |
1950 | ||
1951 | static void | |
acdb74a0 AC |
1952 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1953 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1954 | { |
1955 | CORE_ADDR cur_pc; | |
1956 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1957 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1958 | unsigned inst = 0; /* current instruction */ | |
1959 | unsigned entry_inst = 0; /* the entry instruction */ | |
1960 | int reg, offset; | |
1961 | ||
c5aa993b JM |
1962 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1963 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1964 | |
1965 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1966 | { | |
1967 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1968 | the immediate offset extension from it in mips16_get_imm. */ | |
1969 | prev_inst = inst; | |
1970 | ||
1971 | /* Fetch and decode the instruction. */ | |
1972 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1973 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1974 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1975 | { | |
1976 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1977 | if (offset < 0) /* negative stack adjustment? */ |
1978 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1979 | else |
1980 | /* Exit loop if a positive stack adjustment is found, which | |
1981 | usually means that the stack cleanup code in the function | |
1982 | epilogue is reached. */ | |
1983 | break; | |
1984 | } | |
1985 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1986 | { | |
1987 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1988 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1989 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 1990 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
1991 | } |
1992 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1993 | { | |
1994 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1995 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1996 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 1997 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
1998 | } |
1999 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2000 | { | |
2001 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2002 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2003 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2004 | } |
2005 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2006 | { | |
2007 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2008 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2009 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2010 | } |
c5aa993b | 2011 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2012 | { |
2013 | frame_addr = sp; | |
2014 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2015 | } | |
2016 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2017 | { | |
2018 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2019 | frame_addr = sp + offset; | |
2020 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2021 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2022 | } | |
2023 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2024 | { | |
2025 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2026 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2027 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2028 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2029 | } |
2030 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2031 | { | |
2032 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2033 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2034 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2035 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2036 | } |
c5aa993b JM |
2037 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2038 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2039 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2040 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2041 | } |
2042 | ||
c5aa993b JM |
2043 | /* The entry instruction is typically the first instruction in a function, |
2044 | and it stores registers at offsets relative to the value of the old SP | |
2045 | (before the prologue). But the value of the sp parameter to this | |
2046 | function is the new SP (after the prologue has been executed). So we | |
2047 | can't calculate those offsets until we've seen the entire prologue, | |
2048 | and can calculate what the old SP must have been. */ | |
2049 | if (entry_inst != 0) | |
2050 | { | |
2051 | int areg_count = (entry_inst >> 8) & 7; | |
2052 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2053 | |
c5aa993b JM |
2054 | /* The entry instruction always subtracts 32 from the SP. */ |
2055 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2056 | |
c5aa993b JM |
2057 | /* Now we can calculate what the SP must have been at the |
2058 | start of the function prologue. */ | |
2059 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2060 | |
c5aa993b JM |
2061 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2062 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2063 | { | |
2064 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2065 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2066 | offset += MIPS_SAVED_REGSIZE; |
2067 | } | |
c906108c | 2068 | |
c5aa993b JM |
2069 | /* Check if the ra register was pushed on the stack. */ |
2070 | offset = -4; | |
2071 | if (entry_inst & 0x20) | |
2072 | { | |
2073 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2074 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2075 | offset -= MIPS_SAVED_REGSIZE; |
2076 | } | |
c906108c | 2077 | |
c5aa993b JM |
2078 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2079 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2080 | { | |
2081 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2082 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2083 | offset -= MIPS_SAVED_REGSIZE; |
2084 | } | |
2085 | } | |
c906108c SS |
2086 | } |
2087 | ||
2088 | static void | |
fba45db2 KB |
2089 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2090 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2091 | { |
2092 | CORE_ADDR cur_pc; | |
c5aa993b | 2093 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2094 | restart: |
fe29b929 | 2095 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2096 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2097 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2098 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2099 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2100 | { | |
2101 | unsigned long inst, high_word, low_word; | |
2102 | int reg; | |
2103 | ||
2104 | /* Fetch the instruction. */ | |
2105 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2106 | ||
2107 | /* Save some code by pre-extracting some useful fields. */ | |
2108 | high_word = (inst >> 16) & 0xffff; | |
2109 | low_word = inst & 0xffff; | |
2110 | reg = high_word & 0x1f; | |
2111 | ||
c5aa993b | 2112 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2113 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2114 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2115 | { | |
2116 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2117 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2118 | else |
2119 | /* Exit loop if a positive stack adjustment is found, which | |
2120 | usually means that the stack cleanup code in the function | |
2121 | epilogue is reached. */ | |
2122 | break; | |
2123 | } | |
2124 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2125 | { | |
c5aa993b | 2126 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2127 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2128 | } |
2129 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2130 | { | |
2131 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2132 | but the register size used is only 32 bits. Make the address | |
2133 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2134 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2135 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - MIPS_REGSIZE); |
c906108c | 2136 | } |
c5aa993b | 2137 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2138 | { |
2139 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2140 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2141 | frame_addr = sp + low_word; | |
c906108c SS |
2142 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2143 | { | |
2144 | unsigned alloca_adjust; | |
2145 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2146 | frame_addr = read_next_frame_reg (next_frame, 30); |
2147 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
2148 | if (alloca_adjust > 0) |
2149 | { | |
2150 | /* FP > SP + frame_size. This may be because | |
2151 | * of an alloca or somethings similar. | |
2152 | * Fix sp to "pre-alloca" value, and try again. | |
2153 | */ | |
2154 | sp += alloca_adjust; | |
2155 | goto restart; | |
2156 | } | |
2157 | } | |
2158 | } | |
c5aa993b JM |
2159 | /* move $30,$sp. With different versions of gas this will be either |
2160 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2161 | Accept any one of these. */ | |
c906108c SS |
2162 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2163 | { | |
2164 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2165 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2166 | { | |
2167 | unsigned alloca_adjust; | |
2168 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
2169 | frame_addr = read_next_frame_reg (next_frame, 30); |
2170 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
2171 | if (alloca_adjust > 0) |
2172 | { | |
2173 | /* FP > SP + frame_size. This may be because | |
2174 | * of an alloca or somethings similar. | |
2175 | * Fix sp to "pre-alloca" value, and try again. | |
2176 | */ | |
2177 | sp += alloca_adjust; | |
2178 | goto restart; | |
2179 | } | |
2180 | } | |
2181 | } | |
c5aa993b | 2182 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2183 | { |
c5aa993b | 2184 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2185 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2186 | } |
2187 | } | |
2188 | } | |
2189 | ||
2190 | static mips_extra_func_info_t | |
acdb74a0 | 2191 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2192 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2193 | { |
479412cd DJ |
2194 | CORE_ADDR sp; |
2195 | ||
2196 | if (cur_frame) | |
2197 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
2198 | else | |
2199 | sp = 0; | |
c906108c | 2200 | |
c5aa993b JM |
2201 | if (start_pc == 0) |
2202 | return NULL; | |
2203 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2204 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2205 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2206 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2207 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2208 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2209 | ||
2210 | if (start_pc + 200 < limit_pc) | |
2211 | limit_pc = start_pc + 200; | |
2212 | if (pc_is_mips16 (start_pc)) | |
2213 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2214 | else | |
2215 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2216 | return &temp_proc_desc; | |
2217 | } | |
2218 | ||
6c0d6680 DJ |
2219 | struct mips_objfile_private |
2220 | { | |
2221 | bfd_size_type size; | |
2222 | char *contents; | |
2223 | }; | |
2224 | ||
2225 | /* Global used to communicate between non_heuristic_proc_desc and | |
2226 | compare_pdr_entries within qsort (). */ | |
2227 | static bfd *the_bfd; | |
2228 | ||
2229 | static int | |
2230 | compare_pdr_entries (const void *a, const void *b) | |
2231 | { | |
2232 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2233 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2234 | ||
2235 | if (lhs < rhs) | |
2236 | return -1; | |
2237 | else if (lhs == rhs) | |
2238 | return 0; | |
2239 | else | |
2240 | return 1; | |
2241 | } | |
2242 | ||
c906108c | 2243 | static mips_extra_func_info_t |
acdb74a0 | 2244 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2245 | { |
2246 | CORE_ADDR startaddr; | |
2247 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2248 | struct block *b = block_for_pc (pc); |
c906108c | 2249 | struct symbol *sym; |
6c0d6680 DJ |
2250 | struct obj_section *sec; |
2251 | struct mips_objfile_private *priv; | |
2252 | ||
ae45cd16 | 2253 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2254 | return NULL; |
c906108c SS |
2255 | |
2256 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2257 | if (addrptr) | |
2258 | *addrptr = startaddr; | |
6c0d6680 DJ |
2259 | |
2260 | priv = NULL; | |
2261 | ||
2262 | sec = find_pc_section (pc); | |
2263 | if (sec != NULL) | |
c906108c | 2264 | { |
6c0d6680 DJ |
2265 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2266 | ||
2267 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2268 | the information normally found in ECOFF PDRs. */ | |
2269 | ||
2270 | the_bfd = sec->objfile->obfd; | |
2271 | if (priv == NULL | |
2272 | && (the_bfd->format == bfd_object | |
2273 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2274 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2275 | { | |
2276 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2277 | This means that we should not bother with this method on 64-bit | |
2278 | targets (until that is fixed). */ | |
2279 | ||
2280 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2281 | sizeof (struct mips_objfile_private)); | |
2282 | priv->size = 0; | |
2283 | sec->objfile->obj_private = priv; | |
2284 | } | |
2285 | else if (priv == NULL) | |
2286 | { | |
2287 | asection *bfdsec; | |
2288 | ||
2289 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2290 | sizeof (struct mips_objfile_private)); | |
2291 | ||
2292 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2293 | if (bfdsec != NULL) | |
2294 | { | |
2295 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2296 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2297 | priv->size); | |
2298 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2299 | priv->contents, 0, priv->size); | |
2300 | ||
2301 | /* In general, the .pdr section is sorted. However, in the | |
2302 | presence of multiple code sections (and other corner cases) | |
2303 | it can become unsorted. Sort it so that we can use a faster | |
2304 | binary search. */ | |
2305 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2306 | } | |
2307 | else | |
2308 | priv->size = 0; | |
2309 | ||
2310 | sec->objfile->obj_private = priv; | |
2311 | } | |
2312 | the_bfd = NULL; | |
2313 | ||
2314 | if (priv->size != 0) | |
2315 | { | |
2316 | int low, mid, high; | |
2317 | char *ptr; | |
2318 | ||
2319 | low = 0; | |
2320 | high = priv->size / 32; | |
2321 | ||
2322 | do | |
2323 | { | |
2324 | CORE_ADDR pdr_pc; | |
2325 | ||
2326 | mid = (low + high) / 2; | |
2327 | ||
2328 | ptr = priv->contents + mid * 32; | |
2329 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2330 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2331 | SECT_OFF_TEXT (sec->objfile)); | |
2332 | if (pdr_pc == startaddr) | |
2333 | break; | |
2334 | if (pdr_pc > startaddr) | |
2335 | high = mid; | |
2336 | else | |
2337 | low = mid + 1; | |
2338 | } | |
2339 | while (low != high); | |
2340 | ||
2341 | if (low != high) | |
2342 | { | |
2343 | struct symbol *sym = find_pc_function (pc); | |
2344 | ||
2345 | /* Fill in what we need of the proc_desc. */ | |
2346 | proc_desc = (mips_extra_func_info_t) | |
2347 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2348 | sizeof (struct mips_extra_func_info)); | |
2349 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2350 | ||
2351 | /* Only used for dummy frames. */ | |
2352 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2353 | ||
2354 | PROC_FRAME_OFFSET (proc_desc) | |
2355 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2356 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2357 | ptr + 24); | |
2358 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2359 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2360 | ptr + 4); | |
2361 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2362 | ptr + 12); | |
2363 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2364 | ptr + 8); | |
2365 | PROC_FREG_OFFSET (proc_desc) | |
2366 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2367 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2368 | ptr + 28); | |
2369 | proc_desc->pdr.isym = (long) sym; | |
2370 | ||
2371 | return proc_desc; | |
2372 | } | |
2373 | } | |
c906108c SS |
2374 | } |
2375 | ||
6c0d6680 DJ |
2376 | if (b == NULL) |
2377 | return NULL; | |
2378 | ||
2379 | if (startaddr > BLOCK_START (b)) | |
2380 | { | |
2381 | /* This is the "pathological" case referred to in a comment in | |
2382 | print_frame_info. It might be better to move this check into | |
2383 | symbol reading. */ | |
2384 | return NULL; | |
2385 | } | |
2386 | ||
176620f1 | 2387 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2388 | |
c906108c SS |
2389 | /* If we never found a PDR for this function in symbol reading, then |
2390 | examine prologues to find the information. */ | |
2391 | if (sym) | |
2392 | { | |
2393 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2394 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2395 | return NULL; | |
2396 | else | |
2397 | return proc_desc; | |
2398 | } | |
2399 | else | |
2400 | return NULL; | |
2401 | } | |
2402 | ||
2403 | ||
2404 | static mips_extra_func_info_t | |
479412cd | 2405 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2406 | { |
2407 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2408 | CORE_ADDR startaddr = 0; |
c906108c SS |
2409 | |
2410 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2411 | ||
2412 | if (proc_desc) | |
2413 | { | |
2414 | /* IF this is the topmost frame AND | |
2415 | * (this proc does not have debugging information OR | |
2416 | * the PC is in the procedure prologue) | |
2417 | * THEN create a "heuristic" proc_desc (by analyzing | |
2418 | * the actual code) to replace the "official" proc_desc. | |
2419 | */ | |
2420 | if (next_frame == NULL) | |
2421 | { | |
2422 | struct symtab_and_line val; | |
2423 | struct symbol *proc_symbol = | |
c86b5b38 | 2424 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2425 | |
2426 | if (proc_symbol) | |
2427 | { | |
2428 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2429 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2430 | 0); |
2431 | val.pc = val.end ? val.end : pc; | |
2432 | } | |
2433 | if (!proc_symbol || pc < val.pc) | |
2434 | { | |
2435 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2436 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2437 | pc, next_frame, cur_frame); | |
c906108c SS |
2438 | if (found_heuristic) |
2439 | proc_desc = found_heuristic; | |
2440 | } | |
2441 | } | |
2442 | } | |
2443 | else | |
2444 | { | |
2445 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2446 | by procedure call dummys. However, the procedures being called ought |
2447 | to have their own proc_descs, and even if they don't, | |
2448 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
2449 | |
2450 | register struct linked_proc_info *link; | |
2451 | ||
2452 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2453 | if (PROC_LOW_ADDR (&link->info) <= pc |
2454 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2455 | return &link->info; |
2456 | ||
2457 | if (startaddr == 0) | |
2458 | startaddr = heuristic_proc_start (pc); | |
2459 | ||
2460 | proc_desc = | |
479412cd | 2461 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2462 | } |
2463 | return proc_desc; | |
2464 | } | |
2465 | ||
2466 | static CORE_ADDR | |
acdb74a0 AC |
2467 | get_frame_pointer (struct frame_info *frame, |
2468 | mips_extra_func_info_t proc_desc) | |
c906108c | 2469 | { |
e227b13c AC |
2470 | return (read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) |
2471 | + PROC_FRAME_OFFSET (proc_desc) | |
2472 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2473 | } |
2474 | ||
5a89d8aa | 2475 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2476 | |
f7ab6ec6 | 2477 | static CORE_ADDR |
acdb74a0 | 2478 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2479 | { |
2480 | mips_extra_func_info_t proc_desc; | |
2481 | CORE_ADDR tmp; | |
8bedc050 | 2482 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c SS |
2483 | |
2484 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2485 | return 0; | |
2486 | ||
2487 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2488 | PC of the caller of that stub. */ | |
5a89d8aa | 2489 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2490 | saved_pc = tmp; |
2491 | ||
ae45cd16 | 2492 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2493 | { |
2494 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2495 | is well, frame->frame the bottom of the current frame will | |
2496 | contain that value. */ | |
1e2330ba | 2497 | return get_frame_base (frame); |
cedea778 AC |
2498 | } |
2499 | ||
c906108c | 2500 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2501 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2502 | if (!proc_desc) |
2503 | return 0; | |
2504 | ||
2505 | cached_proc_desc = proc_desc; | |
2506 | ||
2507 | /* If no frame pointer and frame size is zero, we must be at end | |
2508 | of stack (or otherwise hosed). If we don't check frame size, | |
2509 | we loop forever if we see a zero size frame. */ | |
2510 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2511 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2512 | /* The previous frame from a sigtramp frame might be frameless |
2513 | and have frame size zero. */ | |
5a203e44 | 2514 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2515 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2516 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2517 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2518 | return 0; |
2519 | else | |
2520 | return get_frame_pointer (frame, proc_desc); | |
2521 | } | |
2522 | ||
f7ab6ec6 | 2523 | static void |
acdb74a0 | 2524 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2525 | { |
2526 | int regnum; | |
f2c16bd6 KB |
2527 | mips_extra_func_info_t proc_desc; |
2528 | ||
2529 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2530 | return; | |
c906108c | 2531 | |
f796e4be KB |
2532 | /* Use proc_desc calculated in frame_chain. When there is no |
2533 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2534 | find_proc_desc () to calculate it, passing an explicit | |
2535 | NULL as the frame parameter. */ | |
f2c16bd6 | 2536 | proc_desc = |
11c02a10 AC |
2537 | get_next_frame (fci) |
2538 | ? cached_proc_desc | |
f796e4be KB |
2539 | : find_proc_desc (get_frame_pc (fci), |
2540 | NULL /* i.e, get_next_frame (fci) */, | |
2541 | 1); | |
c906108c | 2542 | |
a00a19e9 | 2543 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2544 | |
7b5849cc | 2545 | deprecated_set_frame_saved_regs_hack (fci, NULL); |
da50a4b7 | 2546 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2547 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2548 | if (proc_desc) | |
2549 | { | |
2550 | /* Fixup frame-pointer - only needed for top frame */ | |
2551 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2552 | Get the value of the frame relative sp, procedure might have been |
2553 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2554 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2555 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
11c02a10 | 2556 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), SP_REGNUM)); |
50abf9e5 | 2557 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2558 | /* Do not ``fix'' fci->frame. It will have the value of the |
2559 | generic dummy frame's top-of-stack (since the draft | |
2560 | fci->frame is obtained by returning the unwound stack | |
2561 | pointer) and that is what we want. That way the fci->frame | |
2562 | value will match the top-of-stack value that was saved as | |
2563 | part of the dummy frames data. */ | |
2564 | /* Do nothing. */; | |
c906108c | 2565 | else |
11c02a10 | 2566 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2567 | |
2568 | if (proc_desc == &temp_proc_desc) | |
2569 | { | |
2570 | char *name; | |
2571 | ||
2572 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2573 | mips_find_saved_registers will do that for us. We can't |
2574 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2575 | yet set. */ | |
2576 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2577 | frame.c:get_prev_frame() is modified to set the frame's | |
2578 | type before calling functions like this. */ | |
50abf9e5 | 2579 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2580 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2581 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2582 | { |
c5aa993b | 2583 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2584 | /* Set value of previous frame's stack pointer. |
2585 | Remember that saved_regs[SP_REGNUM] is special in | |
2586 | that it contains the value of the stack pointer | |
2587 | register. The other saved_regs values are addresses | |
2588 | (in the inferior) at which a given register's value | |
2589 | may be found. */ | |
2590 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2591 | get_frame_base (fci)); | |
2592 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2593 | temp_saved_regs[RA_REGNUM]); | |
2594 | memcpy (get_frame_saved_regs (fci), temp_saved_regs, | |
2595 | SIZEOF_FRAME_SAVED_REGS); | |
c906108c SS |
2596 | } |
2597 | } | |
2598 | ||
2599 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2600 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2601 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2602 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2603 | { | |
c5aa993b | 2604 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2605 | { |
da50a4b7 | 2606 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2607 | break; |
2608 | } | |
c5aa993b | 2609 | } |
c906108c SS |
2610 | } |
2611 | } | |
2612 | ||
2613 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2614 | we basically have to look at symbol information for the function | |
2615 | that we stopped in, which tells us *which* register (if any) is | |
2616 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2617 | the frame itself is at. |
c906108c SS |
2618 | |
2619 | This presents a problem when trying to examine a stack in memory | |
2620 | (that isn't executing at the moment), using the "frame" command. We | |
2621 | don't have a PC, nor do we have any registers except SP. | |
2622 | ||
2623 | This routine takes two arguments, SP and PC, and tries to make the | |
2624 | cached frames look as if these two arguments defined a frame on the | |
2625 | cache. This allows the rest of info frame to extract the important | |
2626 | arguments without difficulty. */ | |
2627 | ||
2628 | struct frame_info * | |
acdb74a0 | 2629 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2630 | { |
2631 | if (argc != 2) | |
2632 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2633 | ||
2634 | return create_new_frame (argv[0], argv[1]); | |
2635 | } | |
2636 | ||
f09ded24 AC |
2637 | /* According to the current ABI, should the type be passed in a |
2638 | floating-point register (assuming that there is space)? When there | |
2639 | is no FPU, FP are not even considered as possibile candidates for | |
2640 | FP registers and, consequently this returns false - forces FP | |
2641 | arguments into integer registers. */ | |
2642 | ||
2643 | static int | |
2644 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2645 | { | |
2646 | return ((typecode == TYPE_CODE_FLT | |
2647 | || (MIPS_EABI | |
2648 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2649 | && TYPE_NFIELDS (arg_type) == 1 | |
2650 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2651 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2652 | } |
2653 | ||
49e790b0 DJ |
2654 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2655 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2656 | ||
2657 | static int | |
2658 | mips_type_needs_double_align (struct type *type) | |
2659 | { | |
2660 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2661 | |
49e790b0 DJ |
2662 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2663 | return 1; | |
2664 | else if (typecode == TYPE_CODE_STRUCT) | |
2665 | { | |
2666 | if (TYPE_NFIELDS (type) < 1) | |
2667 | return 0; | |
2668 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2669 | } | |
2670 | else if (typecode == TYPE_CODE_UNION) | |
2671 | { | |
361d1df0 | 2672 | int i, n; |
49e790b0 DJ |
2673 | |
2674 | n = TYPE_NFIELDS (type); | |
2675 | for (i = 0; i < n; i++) | |
2676 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2677 | return 1; | |
2678 | return 0; | |
2679 | } | |
2680 | return 0; | |
2681 | } | |
2682 | ||
cb3d25d1 MS |
2683 | /* Macros to round N up or down to the next A boundary; |
2684 | A must be a power of two. */ | |
2685 | ||
2686 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2687 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
2688 | ||
dc604539 AC |
2689 | /* Adjust the address downward (direction of stack growth) so that it |
2690 | is correctly aligned for a new stack frame. */ | |
2691 | static CORE_ADDR | |
2692 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2693 | { | |
2694 | return ROUND_DOWN (addr, 16); | |
2695 | } | |
2696 | ||
f7ab6ec6 | 2697 | static CORE_ADDR |
25ab4790 AC |
2698 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2699 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2700 | struct value **args, CORE_ADDR sp, int struct_return, | |
2701 | CORE_ADDR struct_addr) | |
c906108c SS |
2702 | { |
2703 | int argreg; | |
2704 | int float_argreg; | |
2705 | int argnum; | |
2706 | int len = 0; | |
2707 | int stack_offset = 0; | |
2708 | ||
25ab4790 AC |
2709 | /* For shared libraries, "t9" needs to point at the function |
2710 | address. */ | |
2711 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2712 | ||
2713 | /* Set the return address register to point to the entry point of | |
2714 | the program, where a breakpoint lies in wait. */ | |
2715 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2716 | ||
c906108c | 2717 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2718 | are properly aligned. The stack has to be at least 64-bit |
2719 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2720 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2721 | aligned, so we round to this widest known alignment. */ | |
2722 | ||
c906108c | 2723 | sp = ROUND_DOWN (sp, 16); |
cce41527 | 2724 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2725 | |
46e0f506 | 2726 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2727 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2728 | passed in registers, but that's OK. */ |
c906108c | 2729 | for (argnum = 0; argnum < nargs; argnum++) |
46e0f506 MS |
2730 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
2731 | MIPS_STACK_ARGSIZE); | |
c906108c SS |
2732 | sp -= ROUND_UP (len, 16); |
2733 | ||
9ace0497 | 2734 | if (mips_debug) |
46e0f506 | 2735 | fprintf_unfiltered (gdb_stdlog, |
25ab4790 | 2736 | "mips_eabi_push_dummy_call: sp=0x%s allocated %d\n", |
cb3d25d1 | 2737 | paddr_nz (sp), ROUND_UP (len, 16)); |
9ace0497 | 2738 | |
c906108c SS |
2739 | /* Initialize the integer and float register pointers. */ |
2740 | argreg = A0_REGNUM; | |
2741 | float_argreg = FPA0_REGNUM; | |
2742 | ||
46e0f506 | 2743 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2744 | if (struct_return) |
9ace0497 AC |
2745 | { |
2746 | if (mips_debug) | |
2747 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2748 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2749 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2750 | write_register (argreg++, struct_addr); |
2751 | } | |
c906108c SS |
2752 | |
2753 | /* Now load as many as possible of the first arguments into | |
2754 | registers, and push the rest onto the stack. Loop thru args | |
2755 | from first to last. */ | |
2756 | for (argnum = 0; argnum < nargs; argnum++) | |
2757 | { | |
2758 | char *val; | |
d9d9c31f | 2759 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2760 | struct value *arg = args[argnum]; |
c906108c SS |
2761 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2762 | int len = TYPE_LENGTH (arg_type); | |
2763 | enum type_code typecode = TYPE_CODE (arg_type); | |
2764 | ||
9ace0497 AC |
2765 | if (mips_debug) |
2766 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2767 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2768 | argnum + 1, len, (int) typecode); |
9ace0497 | 2769 | |
c906108c | 2770 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2771 | reference. */ |
2772 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2773 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2774 | { |
fbd9dcd3 | 2775 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2776 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2777 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2778 | val = valbuf; |
9ace0497 AC |
2779 | if (mips_debug) |
2780 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2781 | } |
2782 | else | |
c5aa993b | 2783 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2784 | |
2785 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2786 | even-numbered floating point register. Round the FP register |
2787 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2788 | left. Non MIPS_EABI targets also pass the FP in the integer |
2789 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2790 | if (!FP_REGISTER_DOUBLE |
2791 | && fp_register_arg_p (typecode, arg_type)) | |
2792 | { | |
2793 | if ((float_argreg & 1)) | |
2794 | float_argreg++; | |
2795 | } | |
c906108c SS |
2796 | |
2797 | /* Floating point arguments passed in registers have to be | |
2798 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2799 | are passed in register pairs; the even register gets |
2800 | the low word, and the odd register gets the high word. | |
2801 | On non-EABI processors, the first two floating point arguments are | |
2802 | also copied to general registers, because MIPS16 functions | |
2803 | don't use float registers for arguments. This duplication of | |
2804 | arguments in general registers can't hurt non-MIPS16 functions | |
2805 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2806 | /* MIPS_EABI squeezes a struct that contains a single floating |
2807 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2808 | stack. */ |
f09ded24 AC |
2809 | if (fp_register_arg_p (typecode, arg_type) |
2810 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2811 | { |
2812 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2813 | { | |
d7449b42 | 2814 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2815 | unsigned long regval; |
2816 | ||
2817 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2818 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2819 | if (mips_debug) |
acdb74a0 | 2820 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2821 | float_argreg, phex (regval, 4)); |
c906108c | 2822 | write_register (float_argreg++, regval); |
c906108c SS |
2823 | |
2824 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2825 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2826 | if (mips_debug) |
acdb74a0 | 2827 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2828 | float_argreg, phex (regval, 4)); |
c906108c | 2829 | write_register (float_argreg++, regval); |
c906108c SS |
2830 | } |
2831 | else | |
2832 | { | |
2833 | /* This is a floating point value that fits entirely | |
2834 | in a single register. */ | |
53a5351d | 2835 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2836 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2837 | LONGEST regval = extract_unsigned_integer (val, len); |
2838 | if (mips_debug) | |
acdb74a0 | 2839 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2840 | float_argreg, phex (regval, len)); |
c906108c | 2841 | write_register (float_argreg++, regval); |
c906108c SS |
2842 | } |
2843 | } | |
2844 | else | |
2845 | { | |
2846 | /* Copy the argument to general registers or the stack in | |
2847 | register-sized pieces. Large arguments are split between | |
2848 | registers and stack. */ | |
2849 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2850 | are treated specially: Irix cc passes them in registers | |
2851 | where gcc sometimes puts them on the stack. For maximum | |
2852 | compatibility, we will put them in both places. */ | |
c5aa993b | 2853 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2854 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2855 | |
f09ded24 | 2856 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2857 | register are only written to memory. */ |
c906108c SS |
2858 | while (len > 0) |
2859 | { | |
ebafbe83 | 2860 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2861 | int stack_used_p = 0; |
46e0f506 MS |
2862 | int partial_len = |
2863 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2864 | |
acdb74a0 AC |
2865 | if (mips_debug) |
2866 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2867 | partial_len); | |
2868 | ||
566f0f7a | 2869 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2870 | if (argreg > MIPS_LAST_ARG_REGNUM |
2871 | || odd_sized_struct | |
2872 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2873 | { |
c906108c SS |
2874 | /* Should shorter than int integer values be |
2875 | promoted to int before being stored? */ | |
c906108c | 2876 | int longword_offset = 0; |
9ace0497 | 2877 | CORE_ADDR addr; |
566f0f7a | 2878 | stack_used_p = 1; |
d7449b42 | 2879 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2880 | { |
d929b26f | 2881 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2882 | (typecode == TYPE_CODE_INT || |
2883 | typecode == TYPE_CODE_PTR || | |
2884 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2885 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2886 | else if ((typecode == TYPE_CODE_STRUCT || |
2887 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2888 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2889 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2890 | } |
c5aa993b | 2891 | |
9ace0497 AC |
2892 | if (mips_debug) |
2893 | { | |
cb3d25d1 MS |
2894 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2895 | paddr_nz (stack_offset)); | |
2896 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2897 | paddr_nz (longword_offset)); | |
9ace0497 | 2898 | } |
361d1df0 | 2899 | |
9ace0497 AC |
2900 | addr = sp + stack_offset + longword_offset; |
2901 | ||
2902 | if (mips_debug) | |
2903 | { | |
2904 | int i; | |
cb3d25d1 MS |
2905 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2906 | paddr_nz (addr)); | |
9ace0497 AC |
2907 | for (i = 0; i < partial_len; i++) |
2908 | { | |
cb3d25d1 MS |
2909 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2910 | val[i] & 0xff); | |
9ace0497 AC |
2911 | } |
2912 | } | |
2913 | write_memory (addr, val, partial_len); | |
c906108c SS |
2914 | } |
2915 | ||
f09ded24 AC |
2916 | /* Note!!! This is NOT an else clause. Odd sized |
2917 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2918 | arguments will not. */ |
566f0f7a | 2919 | /* Write this portion of the argument to a general |
46e0f506 | 2920 | purpose register. */ |
f09ded24 AC |
2921 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2922 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2923 | { |
9ace0497 | 2924 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2925 | |
9ace0497 | 2926 | if (mips_debug) |
acdb74a0 | 2927 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2928 | argreg, |
2929 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2930 | write_register (argreg, regval); |
2931 | argreg++; | |
c906108c | 2932 | } |
c5aa993b | 2933 | |
c906108c SS |
2934 | len -= partial_len; |
2935 | val += partial_len; | |
2936 | ||
566f0f7a AC |
2937 | /* Compute the the offset into the stack at which we |
2938 | will copy the next parameter. | |
2939 | ||
566f0f7a | 2940 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2941 | only needs to be adjusted when it has been used. */ |
c906108c | 2942 | |
46e0f506 | 2943 | if (stack_used_p) |
d929b26f | 2944 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2945 | } |
2946 | } | |
9ace0497 AC |
2947 | if (mips_debug) |
2948 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2949 | } |
2950 | ||
0f71a2f6 JM |
2951 | /* Return adjusted stack pointer. */ |
2952 | return sp; | |
2953 | } | |
2954 | ||
25ab4790 | 2955 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 2956 | |
f7ab6ec6 | 2957 | static CORE_ADDR |
25ab4790 AC |
2958 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2959 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2960 | struct value **args, CORE_ADDR sp, int struct_return, | |
2961 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2962 | { |
2963 | int argreg; | |
2964 | int float_argreg; | |
2965 | int argnum; | |
2966 | int len = 0; | |
2967 | int stack_offset = 0; | |
2968 | ||
25ab4790 AC |
2969 | /* For shared libraries, "t9" needs to point at the function |
2970 | address. */ | |
2971 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2972 | ||
2973 | /* Set the return address register to point to the entry point of | |
2974 | the program, where a breakpoint lies in wait. */ | |
2975 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2976 | ||
cb3d25d1 MS |
2977 | /* First ensure that the stack and structure return address (if any) |
2978 | are properly aligned. The stack has to be at least 64-bit | |
2979 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2980 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2981 | aligned, so we round to this widest known alignment. */ | |
2982 | ||
2983 | sp = ROUND_DOWN (sp, 16); | |
2984 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
2985 | ||
2986 | /* Now make space on the stack for the args. */ | |
2987 | for (argnum = 0; argnum < nargs; argnum++) | |
2988 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
2989 | MIPS_STACK_ARGSIZE); | |
2990 | sp -= ROUND_UP (len, 16); | |
2991 | ||
2992 | if (mips_debug) | |
2993 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2994 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %d\n", |
cb3d25d1 MS |
2995 | paddr_nz (sp), ROUND_UP (len, 16)); |
2996 | ||
2997 | /* Initialize the integer and float register pointers. */ | |
2998 | argreg = A0_REGNUM; | |
2999 | float_argreg = FPA0_REGNUM; | |
3000 | ||
46e0f506 | 3001 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3002 | if (struct_return) |
3003 | { | |
3004 | if (mips_debug) | |
3005 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3006 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3007 | argreg, paddr_nz (struct_addr)); |
3008 | write_register (argreg++, struct_addr); | |
3009 | } | |
3010 | ||
3011 | /* Now load as many as possible of the first arguments into | |
3012 | registers, and push the rest onto the stack. Loop thru args | |
3013 | from first to last. */ | |
3014 | for (argnum = 0; argnum < nargs; argnum++) | |
3015 | { | |
3016 | char *val; | |
d9d9c31f | 3017 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3018 | struct value *arg = args[argnum]; |
3019 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3020 | int len = TYPE_LENGTH (arg_type); | |
3021 | enum type_code typecode = TYPE_CODE (arg_type); | |
3022 | ||
3023 | if (mips_debug) | |
3024 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3025 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3026 | argnum + 1, len, (int) typecode); |
3027 | ||
3028 | val = (char *) VALUE_CONTENTS (arg); | |
3029 | ||
3030 | if (fp_register_arg_p (typecode, arg_type) | |
3031 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3032 | { | |
3033 | /* This is a floating point value that fits entirely | |
3034 | in a single register. */ | |
3035 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3036 | above to ensure that it is even register aligned. */ | |
3037 | LONGEST regval = extract_unsigned_integer (val, len); | |
3038 | if (mips_debug) | |
3039 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3040 | float_argreg, phex (regval, len)); | |
3041 | write_register (float_argreg++, regval); | |
3042 | ||
3043 | if (mips_debug) | |
3044 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3045 | argreg, phex (regval, len)); | |
3046 | write_register (argreg, regval); | |
3047 | argreg += 1; | |
3048 | } | |
3049 | else | |
3050 | { | |
3051 | /* Copy the argument to general registers or the stack in | |
3052 | register-sized pieces. Large arguments are split between | |
3053 | registers and stack. */ | |
3054 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3055 | are treated specially: Irix cc passes them in registers | |
3056 | where gcc sometimes puts them on the stack. For maximum | |
3057 | compatibility, we will put them in both places. */ | |
3058 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3059 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3060 | /* Note: Floating-point values that didn't fit into an FP | |
3061 | register are only written to memory. */ | |
3062 | while (len > 0) | |
3063 | { | |
3064 | /* Rememer if the argument was written to the stack. */ | |
3065 | int stack_used_p = 0; | |
3066 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3067 | len : MIPS_SAVED_REGSIZE; | |
3068 | ||
3069 | if (mips_debug) | |
3070 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3071 | partial_len); | |
3072 | ||
3073 | /* Write this portion of the argument to the stack. */ | |
3074 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3075 | || odd_sized_struct | |
3076 | || fp_register_arg_p (typecode, arg_type)) | |
3077 | { | |
3078 | /* Should shorter than int integer values be | |
3079 | promoted to int before being stored? */ | |
3080 | int longword_offset = 0; | |
3081 | CORE_ADDR addr; | |
3082 | stack_used_p = 1; | |
3083 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3084 | { | |
3085 | if (MIPS_STACK_ARGSIZE == 8 && | |
3086 | (typecode == TYPE_CODE_INT || | |
3087 | typecode == TYPE_CODE_PTR || | |
3088 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3089 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3090 | } |
3091 | ||
3092 | if (mips_debug) | |
3093 | { | |
3094 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3095 | paddr_nz (stack_offset)); | |
3096 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3097 | paddr_nz (longword_offset)); | |
3098 | } | |
3099 | ||
3100 | addr = sp + stack_offset + longword_offset; | |
3101 | ||
3102 | if (mips_debug) | |
3103 | { | |
3104 | int i; | |
3105 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3106 | paddr_nz (addr)); | |
3107 | for (i = 0; i < partial_len; i++) | |
3108 | { | |
3109 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3110 | val[i] & 0xff); | |
3111 | } | |
3112 | } | |
3113 | write_memory (addr, val, partial_len); | |
3114 | } | |
3115 | ||
3116 | /* Note!!! This is NOT an else clause. Odd sized | |
3117 | structs may go thru BOTH paths. Floating point | |
3118 | arguments will not. */ | |
3119 | /* Write this portion of the argument to a general | |
3120 | purpose register. */ | |
3121 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3122 | && !fp_register_arg_p (typecode, arg_type)) | |
3123 | { | |
3124 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3125 | ||
3126 | /* A non-floating-point argument being passed in a | |
3127 | general register. If a struct or union, and if | |
3128 | the remaining length is smaller than the register | |
3129 | size, we have to adjust the register value on | |
3130 | big endian targets. | |
3131 | ||
3132 | It does not seem to be necessary to do the | |
3133 | same for integral types. | |
3134 | ||
3135 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3136 | outputting LE O32 with sizeof (struct) < | |
3137 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3138 | part of storing the argument in a register a | |
3139 | register (the left shift isn't generated when | |
3140 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3141 | is quite possible that this is GCC contradicting | |
3142 | the LE/O32 ABI, GDB has not been adjusted to | |
3143 | accommodate this. Either someone needs to | |
3144 | demonstrate that the LE/O32 ABI specifies such a | |
3145 | left shift OR this new ABI gets identified as | |
3146 | such and GDB gets tweaked accordingly. */ | |
3147 | ||
3148 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3149 | && partial_len < MIPS_SAVED_REGSIZE | |
3150 | && (typecode == TYPE_CODE_STRUCT || | |
3151 | typecode == TYPE_CODE_UNION)) | |
3152 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3153 | TARGET_CHAR_BIT); | |
3154 | ||
3155 | if (mips_debug) | |
3156 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3157 | argreg, | |
3158 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3159 | write_register (argreg, regval); | |
3160 | argreg++; | |
3161 | } | |
3162 | ||
3163 | len -= partial_len; | |
3164 | val += partial_len; | |
3165 | ||
3166 | /* Compute the the offset into the stack at which we | |
3167 | will copy the next parameter. | |
3168 | ||
3169 | In N32 (N64?), the stack_offset only needs to be | |
3170 | adjusted when it has been used. */ | |
3171 | ||
3172 | if (stack_used_p) | |
3173 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3174 | } | |
3175 | } | |
3176 | if (mips_debug) | |
3177 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3178 | } | |
3179 | ||
3180 | /* Return adjusted stack pointer. */ | |
3181 | return sp; | |
3182 | } | |
3183 | ||
25ab4790 | 3184 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3185 | |
46cac009 | 3186 | static CORE_ADDR |
25ab4790 AC |
3187 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3188 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3189 | struct value **args, CORE_ADDR sp, int struct_return, | |
3190 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3191 | { |
3192 | int argreg; | |
3193 | int float_argreg; | |
3194 | int argnum; | |
3195 | int len = 0; | |
3196 | int stack_offset = 0; | |
ebafbe83 | 3197 | |
25ab4790 AC |
3198 | /* For shared libraries, "t9" needs to point at the function |
3199 | address. */ | |
3200 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3201 | ||
3202 | /* Set the return address register to point to the entry point of | |
3203 | the program, where a breakpoint lies in wait. */ | |
3204 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3205 | ||
ebafbe83 MS |
3206 | /* First ensure that the stack and structure return address (if any) |
3207 | are properly aligned. The stack has to be at least 64-bit | |
3208 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3209 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3210 | aligned, so we round to this widest known alignment. */ | |
3211 | ||
3212 | sp = ROUND_DOWN (sp, 16); | |
3213 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3214 | ||
3215 | /* Now make space on the stack for the args. */ | |
3216 | for (argnum = 0; argnum < nargs; argnum++) | |
3217 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3218 | MIPS_STACK_ARGSIZE); | |
3219 | sp -= ROUND_UP (len, 16); | |
3220 | ||
3221 | if (mips_debug) | |
3222 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3223 | "mips_o32_push_dummy_call: sp=0x%s allocated %d\n", |
ebafbe83 MS |
3224 | paddr_nz (sp), ROUND_UP (len, 16)); |
3225 | ||
3226 | /* Initialize the integer and float register pointers. */ | |
3227 | argreg = A0_REGNUM; | |
3228 | float_argreg = FPA0_REGNUM; | |
3229 | ||
bcb0cc15 | 3230 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3231 | if (struct_return) |
3232 | { | |
3233 | if (mips_debug) | |
3234 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3235 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3236 | argreg, paddr_nz (struct_addr)); |
3237 | write_register (argreg++, struct_addr); | |
3238 | stack_offset += MIPS_STACK_ARGSIZE; | |
3239 | } | |
3240 | ||
3241 | /* Now load as many as possible of the first arguments into | |
3242 | registers, and push the rest onto the stack. Loop thru args | |
3243 | from first to last. */ | |
3244 | for (argnum = 0; argnum < nargs; argnum++) | |
3245 | { | |
3246 | char *val; | |
d9d9c31f | 3247 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3248 | struct value *arg = args[argnum]; |
3249 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3250 | int len = TYPE_LENGTH (arg_type); | |
3251 | enum type_code typecode = TYPE_CODE (arg_type); | |
3252 | ||
3253 | if (mips_debug) | |
3254 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3255 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3256 | argnum + 1, len, (int) typecode); |
3257 | ||
3258 | val = (char *) VALUE_CONTENTS (arg); | |
3259 | ||
3260 | /* 32-bit ABIs always start floating point arguments in an | |
3261 | even-numbered floating point register. Round the FP register | |
3262 | up before the check to see if there are any FP registers | |
3263 | left. O32/O64 targets also pass the FP in the integer | |
3264 | registers so also round up normal registers. */ | |
3265 | if (!FP_REGISTER_DOUBLE | |
3266 | && fp_register_arg_p (typecode, arg_type)) | |
3267 | { | |
3268 | if ((float_argreg & 1)) | |
3269 | float_argreg++; | |
3270 | } | |
3271 | ||
3272 | /* Floating point arguments passed in registers have to be | |
3273 | treated specially. On 32-bit architectures, doubles | |
3274 | are passed in register pairs; the even register gets | |
3275 | the low word, and the odd register gets the high word. | |
3276 | On O32/O64, the first two floating point arguments are | |
3277 | also copied to general registers, because MIPS16 functions | |
3278 | don't use float registers for arguments. This duplication of | |
3279 | arguments in general registers can't hurt non-MIPS16 functions | |
3280 | because those registers are normally skipped. */ | |
3281 | ||
3282 | if (fp_register_arg_p (typecode, arg_type) | |
3283 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3284 | { | |
3285 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3286 | { | |
3287 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3288 | unsigned long regval; | |
3289 | ||
3290 | /* Write the low word of the double to the even register(s). */ | |
3291 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3292 | if (mips_debug) | |
3293 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3294 | float_argreg, phex (regval, 4)); | |
3295 | write_register (float_argreg++, regval); | |
3296 | if (mips_debug) | |
3297 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3298 | argreg, phex (regval, 4)); | |
3299 | write_register (argreg++, regval); | |
3300 | ||
3301 | /* Write the high word of the double to the odd register(s). */ | |
3302 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3303 | if (mips_debug) | |
3304 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3305 | float_argreg, phex (regval, 4)); | |
3306 | write_register (float_argreg++, regval); | |
3307 | ||
3308 | if (mips_debug) | |
3309 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3310 | argreg, phex (regval, 4)); | |
3311 | write_register (argreg++, regval); | |
3312 | } | |
3313 | else | |
3314 | { | |
3315 | /* This is a floating point value that fits entirely | |
3316 | in a single register. */ | |
3317 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3318 | above to ensure that it is even register aligned. */ | |
3319 | LONGEST regval = extract_unsigned_integer (val, len); | |
3320 | if (mips_debug) | |
3321 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3322 | float_argreg, phex (regval, len)); | |
3323 | write_register (float_argreg++, regval); | |
3324 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3325 | registers for each argument. The below is (my | |
3326 | guess) to ensure that the corresponding integer | |
3327 | register has reserved the same space. */ | |
3328 | if (mips_debug) | |
3329 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3330 | argreg, phex (regval, len)); | |
3331 | write_register (argreg, regval); | |
3332 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3333 | } | |
3334 | /* Reserve space for the FP register. */ | |
3335 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3336 | } | |
3337 | else | |
3338 | { | |
3339 | /* Copy the argument to general registers or the stack in | |
3340 | register-sized pieces. Large arguments are split between | |
3341 | registers and stack. */ | |
3342 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3343 | are treated specially: Irix cc passes them in registers | |
3344 | where gcc sometimes puts them on the stack. For maximum | |
3345 | compatibility, we will put them in both places. */ | |
3346 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3347 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3348 | /* Structures should be aligned to eight bytes (even arg registers) | |
3349 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3350 | if (MIPS_SAVED_REGSIZE < 8 | |
3351 | && mips_type_needs_double_align (arg_type)) | |
3352 | { | |
3353 | if ((argreg & 1)) | |
3354 | argreg++; | |
3355 | } | |
3356 | /* Note: Floating-point values that didn't fit into an FP | |
3357 | register are only written to memory. */ | |
3358 | while (len > 0) | |
3359 | { | |
3360 | /* Remember if the argument was written to the stack. */ | |
3361 | int stack_used_p = 0; | |
3362 | int partial_len = | |
3363 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3364 | ||
3365 | if (mips_debug) | |
3366 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3367 | partial_len); | |
3368 | ||
3369 | /* Write this portion of the argument to the stack. */ | |
3370 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3371 | || odd_sized_struct | |
3372 | || fp_register_arg_p (typecode, arg_type)) | |
3373 | { | |
3374 | /* Should shorter than int integer values be | |
3375 | promoted to int before being stored? */ | |
3376 | int longword_offset = 0; | |
3377 | CORE_ADDR addr; | |
3378 | stack_used_p = 1; | |
3379 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3380 | { | |
3381 | if (MIPS_STACK_ARGSIZE == 8 && | |
3382 | (typecode == TYPE_CODE_INT || | |
3383 | typecode == TYPE_CODE_PTR || | |
3384 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3385 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3386 | } | |
3387 | ||
3388 | if (mips_debug) | |
3389 | { | |
3390 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3391 | paddr_nz (stack_offset)); | |
3392 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3393 | paddr_nz (longword_offset)); | |
3394 | } | |
3395 | ||
3396 | addr = sp + stack_offset + longword_offset; | |
3397 | ||
3398 | if (mips_debug) | |
3399 | { | |
3400 | int i; | |
3401 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3402 | paddr_nz (addr)); | |
3403 | for (i = 0; i < partial_len; i++) | |
3404 | { | |
3405 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3406 | val[i] & 0xff); | |
3407 | } | |
3408 | } | |
3409 | write_memory (addr, val, partial_len); | |
3410 | } | |
3411 | ||
3412 | /* Note!!! This is NOT an else clause. Odd sized | |
3413 | structs may go thru BOTH paths. Floating point | |
3414 | arguments will not. */ | |
3415 | /* Write this portion of the argument to a general | |
3416 | purpose register. */ | |
3417 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3418 | && !fp_register_arg_p (typecode, arg_type)) | |
3419 | { | |
3420 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3421 | /* Value may need to be sign extended, because | |
3422 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3423 | ||
3424 | /* A non-floating-point argument being passed in a | |
3425 | general register. If a struct or union, and if | |
3426 | the remaining length is smaller than the register | |
3427 | size, we have to adjust the register value on | |
3428 | big endian targets. | |
3429 | ||
3430 | It does not seem to be necessary to do the | |
3431 | same for integral types. | |
3432 | ||
3433 | Also don't do this adjustment on O64 binaries. | |
3434 | ||
3435 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3436 | outputting LE O32 with sizeof (struct) < | |
3437 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3438 | part of storing the argument in a register a | |
3439 | register (the left shift isn't generated when | |
3440 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3441 | is quite possible that this is GCC contradicting | |
3442 | the LE/O32 ABI, GDB has not been adjusted to | |
3443 | accommodate this. Either someone needs to | |
3444 | demonstrate that the LE/O32 ABI specifies such a | |
3445 | left shift OR this new ABI gets identified as | |
3446 | such and GDB gets tweaked accordingly. */ | |
3447 | ||
3448 | if (MIPS_SAVED_REGSIZE < 8 | |
3449 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3450 | && partial_len < MIPS_SAVED_REGSIZE | |
3451 | && (typecode == TYPE_CODE_STRUCT || | |
3452 | typecode == TYPE_CODE_UNION)) | |
3453 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3454 | TARGET_CHAR_BIT); | |
3455 | ||
3456 | if (mips_debug) | |
3457 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3458 | argreg, | |
3459 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3460 | write_register (argreg, regval); | |
3461 | argreg++; | |
3462 | ||
3463 | /* Prevent subsequent floating point arguments from | |
3464 | being passed in floating point registers. */ | |
3465 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3466 | } | |
3467 | ||
3468 | len -= partial_len; | |
3469 | val += partial_len; | |
3470 | ||
3471 | /* Compute the the offset into the stack at which we | |
3472 | will copy the next parameter. | |
3473 | ||
3474 | In older ABIs, the caller reserved space for | |
3475 | registers that contained arguments. This was loosely | |
3476 | refered to as their "home". Consequently, space is | |
3477 | always allocated. */ | |
3478 | ||
3479 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3480 | } | |
3481 | } | |
3482 | if (mips_debug) | |
3483 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3484 | } | |
3485 | ||
3486 | /* Return adjusted stack pointer. */ | |
3487 | return sp; | |
3488 | } | |
3489 | ||
25ab4790 | 3490 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3491 | |
3492 | static CORE_ADDR | |
25ab4790 AC |
3493 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3494 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3495 | struct value **args, CORE_ADDR sp, int struct_return, | |
3496 | CORE_ADDR struct_addr) | |
46cac009 AC |
3497 | { |
3498 | int argreg; | |
3499 | int float_argreg; | |
3500 | int argnum; | |
3501 | int len = 0; | |
3502 | int stack_offset = 0; | |
3503 | ||
25ab4790 AC |
3504 | /* For shared libraries, "t9" needs to point at the function |
3505 | address. */ | |
3506 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3507 | ||
3508 | /* Set the return address register to point to the entry point of | |
3509 | the program, where a breakpoint lies in wait. */ | |
3510 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3511 | ||
46cac009 AC |
3512 | /* First ensure that the stack and structure return address (if any) |
3513 | are properly aligned. The stack has to be at least 64-bit | |
3514 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3515 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3516 | aligned, so we round to this widest known alignment. */ | |
3517 | ||
3518 | sp = ROUND_DOWN (sp, 16); | |
3519 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
3520 | ||
3521 | /* Now make space on the stack for the args. */ | |
3522 | for (argnum = 0; argnum < nargs; argnum++) | |
3523 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
3524 | MIPS_STACK_ARGSIZE); | |
3525 | sp -= ROUND_UP (len, 16); | |
3526 | ||
3527 | if (mips_debug) | |
3528 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3529 | "mips_o64_push_dummy_call: sp=0x%s allocated %d\n", |
46cac009 AC |
3530 | paddr_nz (sp), ROUND_UP (len, 16)); |
3531 | ||
3532 | /* Initialize the integer and float register pointers. */ | |
3533 | argreg = A0_REGNUM; | |
3534 | float_argreg = FPA0_REGNUM; | |
3535 | ||
3536 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3537 | if (struct_return) | |
3538 | { | |
3539 | if (mips_debug) | |
3540 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3541 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3542 | argreg, paddr_nz (struct_addr)); |
3543 | write_register (argreg++, struct_addr); | |
3544 | stack_offset += MIPS_STACK_ARGSIZE; | |
3545 | } | |
3546 | ||
3547 | /* Now load as many as possible of the first arguments into | |
3548 | registers, and push the rest onto the stack. Loop thru args | |
3549 | from first to last. */ | |
3550 | for (argnum = 0; argnum < nargs; argnum++) | |
3551 | { | |
3552 | char *val; | |
d9d9c31f | 3553 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3554 | struct value *arg = args[argnum]; |
3555 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3556 | int len = TYPE_LENGTH (arg_type); | |
3557 | enum type_code typecode = TYPE_CODE (arg_type); | |
3558 | ||
3559 | if (mips_debug) | |
3560 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3561 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3562 | argnum + 1, len, (int) typecode); |
3563 | ||
3564 | val = (char *) VALUE_CONTENTS (arg); | |
3565 | ||
3566 | /* 32-bit ABIs always start floating point arguments in an | |
3567 | even-numbered floating point register. Round the FP register | |
3568 | up before the check to see if there are any FP registers | |
3569 | left. O32/O64 targets also pass the FP in the integer | |
3570 | registers so also round up normal registers. */ | |
3571 | if (!FP_REGISTER_DOUBLE | |
3572 | && fp_register_arg_p (typecode, arg_type)) | |
3573 | { | |
3574 | if ((float_argreg & 1)) | |
3575 | float_argreg++; | |
3576 | } | |
3577 | ||
3578 | /* Floating point arguments passed in registers have to be | |
3579 | treated specially. On 32-bit architectures, doubles | |
3580 | are passed in register pairs; the even register gets | |
3581 | the low word, and the odd register gets the high word. | |
3582 | On O32/O64, the first two floating point arguments are | |
3583 | also copied to general registers, because MIPS16 functions | |
3584 | don't use float registers for arguments. This duplication of | |
3585 | arguments in general registers can't hurt non-MIPS16 functions | |
3586 | because those registers are normally skipped. */ | |
3587 | ||
3588 | if (fp_register_arg_p (typecode, arg_type) | |
3589 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3590 | { | |
3591 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3592 | { | |
3593 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3594 | unsigned long regval; | |
3595 | ||
3596 | /* Write the low word of the double to the even register(s). */ | |
3597 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3598 | if (mips_debug) | |
3599 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3600 | float_argreg, phex (regval, 4)); | |
3601 | write_register (float_argreg++, regval); | |
3602 | if (mips_debug) | |
3603 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3604 | argreg, phex (regval, 4)); | |
3605 | write_register (argreg++, regval); | |
3606 | ||
3607 | /* Write the high word of the double to the odd register(s). */ | |
3608 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3609 | if (mips_debug) | |
3610 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3611 | float_argreg, phex (regval, 4)); | |
3612 | write_register (float_argreg++, regval); | |
3613 | ||
3614 | if (mips_debug) | |
3615 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3616 | argreg, phex (regval, 4)); | |
3617 | write_register (argreg++, regval); | |
3618 | } | |
3619 | else | |
3620 | { | |
3621 | /* This is a floating point value that fits entirely | |
3622 | in a single register. */ | |
3623 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3624 | above to ensure that it is even register aligned. */ | |
3625 | LONGEST regval = extract_unsigned_integer (val, len); | |
3626 | if (mips_debug) | |
3627 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3628 | float_argreg, phex (regval, len)); | |
3629 | write_register (float_argreg++, regval); | |
3630 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3631 | registers for each argument. The below is (my | |
3632 | guess) to ensure that the corresponding integer | |
3633 | register has reserved the same space. */ | |
3634 | if (mips_debug) | |
3635 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3636 | argreg, phex (regval, len)); | |
3637 | write_register (argreg, regval); | |
3638 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3639 | } | |
3640 | /* Reserve space for the FP register. */ | |
3641 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3642 | } | |
3643 | else | |
3644 | { | |
3645 | /* Copy the argument to general registers or the stack in | |
3646 | register-sized pieces. Large arguments are split between | |
3647 | registers and stack. */ | |
3648 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3649 | are treated specially: Irix cc passes them in registers | |
3650 | where gcc sometimes puts them on the stack. For maximum | |
3651 | compatibility, we will put them in both places. */ | |
3652 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3653 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3654 | /* Structures should be aligned to eight bytes (even arg registers) | |
3655 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3656 | if (MIPS_SAVED_REGSIZE < 8 | |
3657 | && mips_type_needs_double_align (arg_type)) | |
3658 | { | |
3659 | if ((argreg & 1)) | |
3660 | argreg++; | |
3661 | } | |
3662 | /* Note: Floating-point values that didn't fit into an FP | |
3663 | register are only written to memory. */ | |
3664 | while (len > 0) | |
3665 | { | |
3666 | /* Remember if the argument was written to the stack. */ | |
3667 | int stack_used_p = 0; | |
3668 | int partial_len = | |
3669 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3670 | ||
3671 | if (mips_debug) | |
3672 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3673 | partial_len); | |
3674 | ||
3675 | /* Write this portion of the argument to the stack. */ | |
3676 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3677 | || odd_sized_struct | |
3678 | || fp_register_arg_p (typecode, arg_type)) | |
3679 | { | |
3680 | /* Should shorter than int integer values be | |
3681 | promoted to int before being stored? */ | |
3682 | int longword_offset = 0; | |
3683 | CORE_ADDR addr; | |
3684 | stack_used_p = 1; | |
3685 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3686 | { | |
3687 | if (MIPS_STACK_ARGSIZE == 8 && | |
3688 | (typecode == TYPE_CODE_INT || | |
3689 | typecode == TYPE_CODE_PTR || | |
3690 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3691 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3692 | } | |
3693 | ||
3694 | if (mips_debug) | |
3695 | { | |
3696 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3697 | paddr_nz (stack_offset)); | |
3698 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3699 | paddr_nz (longword_offset)); | |
3700 | } | |
3701 | ||
3702 | addr = sp + stack_offset + longword_offset; | |
3703 | ||
3704 | if (mips_debug) | |
3705 | { | |
3706 | int i; | |
3707 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3708 | paddr_nz (addr)); | |
3709 | for (i = 0; i < partial_len; i++) | |
3710 | { | |
3711 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3712 | val[i] & 0xff); | |
3713 | } | |
3714 | } | |
3715 | write_memory (addr, val, partial_len); | |
3716 | } | |
3717 | ||
3718 | /* Note!!! This is NOT an else clause. Odd sized | |
3719 | structs may go thru BOTH paths. Floating point | |
3720 | arguments will not. */ | |
3721 | /* Write this portion of the argument to a general | |
3722 | purpose register. */ | |
3723 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3724 | && !fp_register_arg_p (typecode, arg_type)) | |
3725 | { | |
3726 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3727 | /* Value may need to be sign extended, because | |
3728 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3729 | ||
3730 | /* A non-floating-point argument being passed in a | |
3731 | general register. If a struct or union, and if | |
3732 | the remaining length is smaller than the register | |
3733 | size, we have to adjust the register value on | |
3734 | big endian targets. | |
3735 | ||
3736 | It does not seem to be necessary to do the | |
3737 | same for integral types. | |
3738 | ||
3739 | Also don't do this adjustment on O64 binaries. | |
3740 | ||
3741 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3742 | outputting LE O32 with sizeof (struct) < | |
3743 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3744 | part of storing the argument in a register a | |
3745 | register (the left shift isn't generated when | |
3746 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3747 | is quite possible that this is GCC contradicting | |
3748 | the LE/O32 ABI, GDB has not been adjusted to | |
3749 | accommodate this. Either someone needs to | |
3750 | demonstrate that the LE/O32 ABI specifies such a | |
3751 | left shift OR this new ABI gets identified as | |
3752 | such and GDB gets tweaked accordingly. */ | |
3753 | ||
3754 | if (MIPS_SAVED_REGSIZE < 8 | |
3755 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3756 | && partial_len < MIPS_SAVED_REGSIZE | |
3757 | && (typecode == TYPE_CODE_STRUCT || | |
3758 | typecode == TYPE_CODE_UNION)) | |
3759 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3760 | TARGET_CHAR_BIT); | |
3761 | ||
3762 | if (mips_debug) | |
3763 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3764 | argreg, | |
3765 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3766 | write_register (argreg, regval); | |
3767 | argreg++; | |
3768 | ||
3769 | /* Prevent subsequent floating point arguments from | |
3770 | being passed in floating point registers. */ | |
3771 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3772 | } | |
3773 | ||
3774 | len -= partial_len; | |
3775 | val += partial_len; | |
3776 | ||
3777 | /* Compute the the offset into the stack at which we | |
3778 | will copy the next parameter. | |
3779 | ||
3780 | In older ABIs, the caller reserved space for | |
3781 | registers that contained arguments. This was loosely | |
3782 | refered to as their "home". Consequently, space is | |
3783 | always allocated. */ | |
3784 | ||
3785 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3786 | } | |
3787 | } | |
3788 | if (mips_debug) | |
3789 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3790 | } | |
3791 | ||
3792 | /* Return adjusted stack pointer. */ | |
3793 | return sp; | |
3794 | } | |
3795 | ||
f7ab6ec6 | 3796 | static void |
acdb74a0 | 3797 | mips_pop_frame (void) |
c906108c SS |
3798 | { |
3799 | register int regnum; | |
3800 | struct frame_info *frame = get_current_frame (); | |
c193f6ac | 3801 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3802 | mips_extra_func_info_t proc_desc; |
c906108c | 3803 | |
50abf9e5 | 3804 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3805 | { |
3806 | generic_pop_dummy_frame (); | |
3807 | flush_cached_frames (); | |
3808 | return; | |
3809 | } | |
3810 | ||
e227b13c | 3811 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3812 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3813 | mips_find_saved_regs (frame); |
c906108c | 3814 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3815 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
b2fb4676 | 3816 | && get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3817 | { |
3818 | /* Floating point registers must not be sign extended, | |
3819 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3820 | ||
3821 | if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32) | |
3822 | write_register (regnum, | |
b2fb4676 | 3823 | read_memory_unsigned_integer (get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3824 | MIPS_SAVED_REGSIZE)); |
3825 | else | |
3826 | write_register (regnum, | |
b2fb4676 | 3827 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3828 | MIPS_SAVED_REGSIZE)); |
3829 | } | |
757a7cc6 | 3830 | |
c906108c SS |
3831 | write_register (SP_REGNUM, new_sp); |
3832 | flush_cached_frames (); | |
3833 | ||
c5aa993b | 3834 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3835 | { |
3836 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3837 | ||
3838 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3839 | pi_ptr != NULL; | |
3840 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3841 | { | |
3842 | if (&pi_ptr->info == proc_desc) | |
3843 | break; | |
3844 | } | |
3845 | ||
3846 | if (pi_ptr == NULL) | |
3847 | error ("Can't locate dummy extra frame info\n"); | |
3848 | ||
3849 | if (prev_ptr != NULL) | |
3850 | prev_ptr->next = pi_ptr->next; | |
3851 | else | |
3852 | linked_proc_desc_table = pi_ptr->next; | |
3853 | ||
b8c9b27d | 3854 | xfree (pi_ptr); |
c906108c SS |
3855 | |
3856 | write_register (HI_REGNUM, | |
c5aa993b | 3857 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3858 | MIPS_SAVED_REGSIZE)); |
c906108c | 3859 | write_register (LO_REGNUM, |
c5aa993b | 3860 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3861 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3862 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
3863 | write_register (FCRCS_REGNUM, | |
c5aa993b | 3864 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3865 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3866 | } |
3867 | } | |
3868 | ||
dd824b04 DJ |
3869 | /* Floating point register management. |
3870 | ||
3871 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3872 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3873 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3874 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3875 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3876 | double precision floats into two 32-bit chunks and store them in | |
3877 | consecutive fp regs. To display 64-bit floats stored in this | |
3878 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3879 | Throw in user-configurable endianness and you have a real mess. | |
3880 | ||
3881 | The way this works is: | |
3882 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3883 | double-precision value will be split across two logical registers. | |
3884 | The lower-numbered logical register will hold the low-order bits, | |
3885 | regardless of the processor's endianness. | |
3886 | - If we are on a 64-bit processor, and we are looking for a | |
3887 | single-precision value, it will be in the low ordered bits | |
3888 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3889 | save slot in memory. | |
3890 | - If we are in 64-bit mode, everything is straightforward. | |
3891 | ||
3892 | Note that this code only deals with "live" registers at the top of the | |
3893 | stack. We will attempt to deal with saved registers later, when | |
3894 | the raw/cooked register interface is in place. (We need a general | |
3895 | interface that can deal with dynamic saved register sizes -- fp | |
3896 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3897 | and below). */ | |
3898 | ||
67b2c998 DJ |
3899 | static struct type * |
3900 | mips_float_register_type (void) | |
3901 | { | |
361d1df0 | 3902 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3903 | return builtin_type_ieee_single_big; |
3904 | else | |
3905 | return builtin_type_ieee_single_little; | |
3906 | } | |
3907 | ||
3908 | static struct type * | |
3909 | mips_double_register_type (void) | |
3910 | { | |
361d1df0 | 3911 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3912 | return builtin_type_ieee_double_big; |
3913 | else | |
3914 | return builtin_type_ieee_double_little; | |
3915 | } | |
3916 | ||
dd824b04 DJ |
3917 | /* Copy a 32-bit single-precision value from the current frame |
3918 | into rare_buffer. */ | |
3919 | ||
3920 | static void | |
e11c53d2 AC |
3921 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3922 | char *rare_buffer) | |
dd824b04 DJ |
3923 | { |
3924 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3925 | char *raw_buffer = alloca (raw_size); | |
3926 | ||
e11c53d2 | 3927 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3928 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3929 | if (raw_size == 8) | |
3930 | { | |
3931 | /* We have a 64-bit value for this register. Find the low-order | |
3932 | 32 bits. */ | |
3933 | int offset; | |
3934 | ||
3935 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3936 | offset = 4; | |
3937 | else | |
3938 | offset = 0; | |
3939 | ||
3940 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3941 | } | |
3942 | else | |
3943 | { | |
3944 | memcpy (rare_buffer, raw_buffer, 4); | |
3945 | } | |
3946 | } | |
3947 | ||
3948 | /* Copy a 64-bit double-precision value from the current frame into | |
3949 | rare_buffer. This may include getting half of it from the next | |
3950 | register. */ | |
3951 | ||
3952 | static void | |
e11c53d2 AC |
3953 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3954 | char *rare_buffer) | |
dd824b04 DJ |
3955 | { |
3956 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3957 | ||
3958 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3959 | { | |
3960 | /* We have a 64-bit value for this register, and we should use | |
3961 | all 64 bits. */ | |
e11c53d2 | 3962 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
3963 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3964 | } | |
3965 | else | |
3966 | { | |
3967 | if ((regno - FP0_REGNUM) & 1) | |
3968 | internal_error (__FILE__, __LINE__, | |
3969 | "mips_read_fp_register_double: bad access to " | |
3970 | "odd-numbered FP register"); | |
3971 | ||
3972 | /* mips_read_fp_register_single will find the correct 32 bits from | |
3973 | each register. */ | |
3974 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3975 | { | |
e11c53d2 AC |
3976 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3977 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3978 | } |
361d1df0 | 3979 | else |
dd824b04 | 3980 | { |
e11c53d2 AC |
3981 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3982 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
3983 | } |
3984 | } | |
3985 | } | |
3986 | ||
c906108c | 3987 | static void |
e11c53d2 AC |
3988 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
3989 | int regnum) | |
c5aa993b | 3990 | { /* do values for FP (float) regs */ |
dd824b04 | 3991 | char *raw_buffer; |
c906108c | 3992 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 3993 | int inv1, inv2, namelen; |
c5aa993b | 3994 | |
dd824b04 | 3995 | raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 3996 | |
e11c53d2 AC |
3997 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
3998 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
3999 | ""); | |
f0ef6b29 | 4000 | |
dd824b04 | 4001 | if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4002 | { |
f0ef6b29 KB |
4003 | /* 4-byte registers: Print hex and floating. Also print even |
4004 | numbered registers as doubles. */ | |
e11c53d2 | 4005 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4006 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4007 | |
e11c53d2 | 4008 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4009 | |
e11c53d2 | 4010 | fprintf_filtered (file, " flt: "); |
1adad886 | 4011 | if (inv1) |
e11c53d2 | 4012 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4013 | else |
e11c53d2 | 4014 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4015 | |
f0ef6b29 KB |
4016 | if (regnum % 2 == 0) |
4017 | { | |
e11c53d2 | 4018 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4019 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4020 | &inv2); | |
1adad886 | 4021 | |
e11c53d2 | 4022 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4023 | if (inv2) |
e11c53d2 | 4024 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4025 | else |
e11c53d2 | 4026 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4027 | } |
c906108c SS |
4028 | } |
4029 | else | |
dd824b04 | 4030 | { |
f0ef6b29 | 4031 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4032 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4033 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4034 | |
e11c53d2 | 4035 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4036 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4037 | ||
361d1df0 | 4038 | |
e11c53d2 | 4039 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4040 | |
e11c53d2 | 4041 | fprintf_filtered (file, " flt: "); |
1adad886 | 4042 | if (inv1) |
e11c53d2 | 4043 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4044 | else |
e11c53d2 | 4045 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4046 | |
e11c53d2 | 4047 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4048 | if (inv2) |
e11c53d2 | 4049 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4050 | else |
e11c53d2 | 4051 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4052 | } |
4053 | } | |
4054 | ||
4055 | static void | |
e11c53d2 AC |
4056 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4057 | int regnum, int all) | |
f0ef6b29 | 4058 | { |
d9d9c31f | 4059 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4060 | int offset; |
1adad886 | 4061 | |
f0ef6b29 KB |
4062 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
4063 | { | |
e11c53d2 | 4064 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4065 | return; |
4066 | } | |
4067 | ||
4068 | /* Get the data in raw format. */ | |
e11c53d2 | 4069 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4070 | { |
e11c53d2 | 4071 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4072 | return; |
c906108c | 4073 | } |
f0ef6b29 | 4074 | |
e11c53d2 | 4075 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4076 | |
4077 | /* The problem with printing numeric register names (r26, etc.) is that | |
4078 | the user can't use them on input. Probably the best solution is to | |
4079 | fix it so that either the numeric or the funky (a2, etc.) names | |
4080 | are accepted on input. */ | |
4081 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4082 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4083 | else |
e11c53d2 | 4084 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4085 | |
4086 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4087 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); | |
4088 | else | |
4089 | offset = 0; | |
4090 | ||
4091 | print_scalar_formatted (raw_buffer + offset, | |
4092 | REGISTER_VIRTUAL_TYPE (regnum), | |
e11c53d2 | 4093 | 'x', 0, file); |
c906108c SS |
4094 | } |
4095 | ||
f0ef6b29 KB |
4096 | /* Replacement for generic do_registers_info. |
4097 | Print regs in pretty columns. */ | |
4098 | ||
4099 | static int | |
e11c53d2 AC |
4100 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4101 | int regnum) | |
f0ef6b29 | 4102 | { |
e11c53d2 AC |
4103 | fprintf_filtered (file, " "); |
4104 | mips_print_fp_register (file, frame, regnum); | |
4105 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4106 | return regnum + 1; |
4107 | } | |
4108 | ||
4109 | ||
c906108c SS |
4110 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4111 | ||
4112 | static int | |
e11c53d2 AC |
4113 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
4114 | int regnum) | |
c906108c SS |
4115 | { |
4116 | /* do values for GP (int) regs */ | |
d9d9c31f | 4117 | char raw_buffer[MAX_REGISTER_SIZE]; |
c906108c SS |
4118 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
4119 | int col, byte; | |
4120 | int start_regnum = regnum; | |
4121 | int numregs = NUM_REGS; | |
4122 | ||
4123 | ||
4124 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4125 | fprintf_filtered (file, " "); |
c906108c SS |
4126 | for (col = 0; col < ncols && regnum < numregs; regnum++) |
4127 | { | |
4128 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4129 | continue; /* unused register */ |
c906108c | 4130 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4131 | break; /* end the row: reached FP register */ |
e11c53d2 AC |
4132 | fprintf_filtered (file, MIPS_REGSIZE == 8 ? "%17s" : "%9s", |
4133 | REGISTER_NAME (regnum)); | |
c906108c SS |
4134 | col++; |
4135 | } | |
e11c53d2 AC |
4136 | fprintf_filtered (file, |
4137 | start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", | |
4138 | start_regnum); /* print the R0 to R31 names */ | |
c906108c SS |
4139 | |
4140 | regnum = start_regnum; /* go back to start of row */ | |
4141 | /* now print the values in hex, 4 or 8 to the row */ | |
4142 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
4143 | { | |
4144 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4145 | continue; /* unused register */ |
c906108c | 4146 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4147 | break; /* end row: reached FP register */ |
c906108c | 4148 | /* OK: get the data in raw format. */ |
e11c53d2 | 4149 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4150 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4151 | /* pad small registers */ | |
43e526b9 | 4152 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
4153 | printf_filtered (" "); |
4154 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4155 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
4156 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
4157 | byte < REGISTER_RAW_SIZE (regnum); | |
4158 | byte++) | |
e11c53d2 | 4159 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4160 | else |
43e526b9 JM |
4161 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
4162 | byte >= 0; | |
4163 | byte--) | |
e11c53d2 AC |
4164 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4165 | fprintf_filtered (file, " "); | |
c906108c SS |
4166 | col++; |
4167 | } | |
c5aa993b | 4168 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4169 | fprintf_filtered (file, "\n"); |
c906108c SS |
4170 | |
4171 | return regnum; | |
4172 | } | |
4173 | ||
4174 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4175 | ||
bf1f5b4c | 4176 | static void |
e11c53d2 AC |
4177 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4178 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4179 | { |
c5aa993b | 4180 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
4181 | { |
4182 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4183 | error ("Not a valid register for the current processor type"); | |
4184 | ||
e11c53d2 AC |
4185 | mips_print_register (file, frame, regnum, 0); |
4186 | fprintf_filtered (file, "\n"); | |
c906108c | 4187 | } |
c5aa993b JM |
4188 | else |
4189 | /* do all (or most) registers */ | |
c906108c SS |
4190 | { |
4191 | regnum = 0; | |
4192 | while (regnum < NUM_REGS) | |
4193 | { | |
c5aa993b | 4194 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4195 | { |
4196 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4197 | regnum = print_fp_register_row (file, frame, regnum); | |
4198 | else | |
4199 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4200 | } | |
c906108c | 4201 | else |
e11c53d2 | 4202 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4203 | } |
4204 | } | |
4205 | } | |
4206 | ||
c906108c SS |
4207 | /* Is this a branch with a delay slot? */ |
4208 | ||
a14ed312 | 4209 | static int is_delayed (unsigned long); |
c906108c SS |
4210 | |
4211 | static int | |
acdb74a0 | 4212 | is_delayed (unsigned long insn) |
c906108c SS |
4213 | { |
4214 | int i; | |
4215 | for (i = 0; i < NUMOPCODES; ++i) | |
4216 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4217 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4218 | break; | |
4219 | return (i < NUMOPCODES | |
4220 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4221 | | INSN_COND_BRANCH_DELAY | |
4222 | | INSN_COND_BRANCH_LIKELY))); | |
4223 | } | |
4224 | ||
4225 | int | |
acdb74a0 | 4226 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4227 | { |
4228 | char buf[MIPS_INSTLEN]; | |
4229 | ||
4230 | /* There is no branch delay slot on MIPS16. */ | |
4231 | if (pc_is_mips16 (pc)) | |
4232 | return 0; | |
4233 | ||
4234 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4235 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4236 | return 0; | |
c5aa993b | 4237 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4238 | } |
4239 | ||
4240 | ||
4241 | /* Skip the PC past function prologue instructions (32-bit version). | |
4242 | This is a helper function for mips_skip_prologue. */ | |
4243 | ||
4244 | static CORE_ADDR | |
f7b9e9fc | 4245 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4246 | { |
c5aa993b JM |
4247 | t_inst inst; |
4248 | CORE_ADDR end_pc; | |
4249 | int seen_sp_adjust = 0; | |
4250 | int load_immediate_bytes = 0; | |
4251 | ||
4252 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4253 | instruction and the instructions that save registers on the stack | |
4254 | or in the gcc frame. */ | |
4255 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
4256 | { | |
4257 | unsigned long high_word; | |
c906108c | 4258 | |
c5aa993b JM |
4259 | inst = mips_fetch_instruction (pc); |
4260 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4261 | |
c5aa993b JM |
4262 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4263 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4264 | seen_sp_adjust = 1; | |
4265 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4266 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4267 | seen_sp_adjust = 1; | |
4268 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4269 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4270 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4271 | continue; | |
4272 | ||
4273 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4274 | continue; | |
4275 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4276 | /* sx reg,n($s8) */ | |
4277 | continue; /* reg != $zero */ | |
4278 | ||
4279 | /* move $s8,$sp. With different versions of gas this will be either | |
4280 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4281 | Accept any one of these. */ | |
4282 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4283 | continue; | |
4284 | ||
4285 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4286 | continue; | |
4287 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4288 | continue; | |
4289 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4290 | continue; | |
4291 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4292 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4293 | continue; | |
4294 | /* The following instructions load $at or $t0 with an immediate | |
4295 | value in preparation for a stack adjustment via | |
4296 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4297 | a local variable, so we accept them only before a stack adjustment | |
4298 | instruction was seen. */ | |
4299 | else if (!seen_sp_adjust) | |
4300 | { | |
4301 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4302 | high_word == 0x3c08) /* lui $t0,n */ | |
4303 | { | |
4304 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4305 | continue; | |
4306 | } | |
4307 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4308 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4309 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4310 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4311 | { | |
4312 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4313 | continue; | |
4314 | } | |
4315 | else | |
4316 | break; | |
4317 | } | |
4318 | else | |
4319 | break; | |
c906108c SS |
4320 | } |
4321 | ||
c5aa993b JM |
4322 | /* In a frameless function, we might have incorrectly |
4323 | skipped some load immediate instructions. Undo the skipping | |
4324 | if the load immediate was not followed by a stack adjustment. */ | |
4325 | if (load_immediate_bytes && !seen_sp_adjust) | |
4326 | pc -= load_immediate_bytes; | |
4327 | return pc; | |
c906108c SS |
4328 | } |
4329 | ||
4330 | /* Skip the PC past function prologue instructions (16-bit version). | |
4331 | This is a helper function for mips_skip_prologue. */ | |
4332 | ||
4333 | static CORE_ADDR | |
f7b9e9fc | 4334 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4335 | { |
c5aa993b JM |
4336 | CORE_ADDR end_pc; |
4337 | int extend_bytes = 0; | |
4338 | int prev_extend_bytes; | |
c906108c | 4339 | |
c5aa993b JM |
4340 | /* Table of instructions likely to be found in a function prologue. */ |
4341 | static struct | |
c906108c SS |
4342 | { |
4343 | unsigned short inst; | |
4344 | unsigned short mask; | |
c5aa993b JM |
4345 | } |
4346 | table[] = | |
4347 | { | |
c906108c | 4348 | { |
c5aa993b JM |
4349 | 0x6300, 0xff00 |
4350 | } | |
4351 | , /* addiu $sp,offset */ | |
4352 | { | |
4353 | 0xfb00, 0xff00 | |
4354 | } | |
4355 | , /* daddiu $sp,offset */ | |
4356 | { | |
4357 | 0xd000, 0xf800 | |
4358 | } | |
4359 | , /* sw reg,n($sp) */ | |
4360 | { | |
4361 | 0xf900, 0xff00 | |
4362 | } | |
4363 | , /* sd reg,n($sp) */ | |
4364 | { | |
4365 | 0x6200, 0xff00 | |
4366 | } | |
4367 | , /* sw $ra,n($sp) */ | |
4368 | { | |
4369 | 0xfa00, 0xff00 | |
4370 | } | |
4371 | , /* sd $ra,n($sp) */ | |
4372 | { | |
4373 | 0x673d, 0xffff | |
4374 | } | |
4375 | , /* move $s1,sp */ | |
4376 | { | |
4377 | 0xd980, 0xff80 | |
4378 | } | |
4379 | , /* sw $a0-$a3,n($s1) */ | |
4380 | { | |
4381 | 0x6704, 0xff1c | |
4382 | } | |
4383 | , /* move reg,$a0-$a3 */ | |
4384 | { | |
4385 | 0xe809, 0xf81f | |
4386 | } | |
4387 | , /* entry pseudo-op */ | |
4388 | { | |
4389 | 0x0100, 0xff00 | |
4390 | } | |
4391 | , /* addiu $s1,$sp,n */ | |
4392 | { | |
4393 | 0, 0 | |
4394 | } /* end of table marker */ | |
4395 | }; | |
4396 | ||
4397 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4398 | instruction and the instructions that save registers on the stack | |
4399 | or in the gcc frame. */ | |
4400 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
4401 | { | |
4402 | unsigned short inst; | |
4403 | int i; | |
c906108c | 4404 | |
c5aa993b | 4405 | inst = mips_fetch_instruction (pc); |
c906108c | 4406 | |
c5aa993b JM |
4407 | /* Normally we ignore an extend instruction. However, if it is |
4408 | not followed by a valid prologue instruction, we must adjust | |
4409 | the pc back over the extend so that it won't be considered | |
4410 | part of the prologue. */ | |
4411 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4412 | { | |
4413 | extend_bytes = MIPS16_INSTLEN; | |
4414 | continue; | |
4415 | } | |
4416 | prev_extend_bytes = extend_bytes; | |
4417 | extend_bytes = 0; | |
c906108c | 4418 | |
c5aa993b JM |
4419 | /* Check for other valid prologue instructions besides extend. */ |
4420 | for (i = 0; table[i].mask != 0; i++) | |
4421 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4422 | break; | |
4423 | if (table[i].mask != 0) /* it was in table? */ | |
4424 | continue; /* ignore it */ | |
4425 | else | |
4426 | /* non-prologue */ | |
4427 | { | |
4428 | /* Return the current pc, adjusted backwards by 2 if | |
4429 | the previous instruction was an extend. */ | |
4430 | return pc - prev_extend_bytes; | |
4431 | } | |
c906108c SS |
4432 | } |
4433 | return pc; | |
4434 | } | |
4435 | ||
4436 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4437 | if the code at PC does not look like a function prologue; otherwise | |
4438 | returns an address that (if we're lucky) follows the prologue. If | |
4439 | LENIENT, then we must skip everything which is involved in setting | |
4440 | up the frame (it's OK to skip more, just so long as we don't skip | |
4441 | anything which might clobber the registers which are being saved. | |
4442 | We must skip more in the case where part of the prologue is in the | |
4443 | delay slot of a non-prologue instruction). */ | |
4444 | ||
f7ab6ec6 | 4445 | static CORE_ADDR |
f7b9e9fc | 4446 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4447 | { |
4448 | /* See if we can determine the end of the prologue via the symbol table. | |
4449 | If so, then return either PC, or the PC after the prologue, whichever | |
4450 | is greater. */ | |
4451 | ||
4452 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4453 | ||
4454 | if (post_prologue_pc != 0) | |
4455 | return max (pc, post_prologue_pc); | |
4456 | ||
4457 | /* Can't determine prologue from the symbol table, need to examine | |
4458 | instructions. */ | |
4459 | ||
4460 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4461 | return mips16_skip_prologue (pc); |
c906108c | 4462 | else |
f7b9e9fc | 4463 | return mips32_skip_prologue (pc); |
c906108c | 4464 | } |
c906108c | 4465 | |
7a292a7a SS |
4466 | /* Determine how a return value is stored within the MIPS register |
4467 | file, given the return type `valtype'. */ | |
4468 | ||
4469 | struct return_value_word | |
4470 | { | |
4471 | int len; | |
4472 | int reg; | |
4473 | int reg_offset; | |
4474 | int buf_offset; | |
4475 | }; | |
4476 | ||
7a292a7a | 4477 | static void |
acdb74a0 AC |
4478 | return_value_location (struct type *valtype, |
4479 | struct return_value_word *hi, | |
4480 | struct return_value_word *lo) | |
7a292a7a SS |
4481 | { |
4482 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4483 | |
7a292a7a SS |
4484 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4485 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4486 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4487 | { | |
4488 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4489 | { | |
4490 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4491 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4492 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4493 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4494 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
7a292a7a SS |
4495 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
4496 | ? 4 : 0); | |
4497 | hi->reg_offset = lo->reg_offset; | |
4498 | lo->reg = FP0_REGNUM + 0; | |
4499 | hi->reg = FP0_REGNUM + 1; | |
4500 | lo->len = 4; | |
4501 | hi->len = 4; | |
4502 | } | |
4503 | else | |
4504 | { | |
4505 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4506 | register. */ |
d7449b42 | 4507 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4508 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
4509 | && len == 4) | |
4510 | ? 4 : 0); | |
4511 | lo->reg = FP0_REGNUM; | |
4512 | lo->len = len; | |
4513 | lo->buf_offset = 0; | |
4514 | hi->len = 0; | |
4515 | hi->reg_offset = 0; | |
4516 | hi->buf_offset = 0; | |
4517 | hi->reg = 0; | |
4518 | } | |
4519 | } | |
4520 | else | |
4521 | { | |
4522 | /* Locate a result possibly spread across two registers. */ | |
4523 | int regnum = 2; | |
4524 | lo->reg = regnum + 0; | |
4525 | hi->reg = regnum + 1; | |
d7449b42 | 4526 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4527 | && len < MIPS_SAVED_REGSIZE) |
4528 | { | |
bf1f5b4c MS |
4529 | /* "un-left-justify" the value in the low register */ |
4530 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4531 | lo->len = len; |
bf1f5b4c | 4532 | hi->reg_offset = 0; |
7a292a7a SS |
4533 | hi->len = 0; |
4534 | } | |
d7449b42 | 4535 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4536 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4537 | && len < MIPS_SAVED_REGSIZE * 2 | |
4538 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4539 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4540 | { | |
4541 | /* "un-left-justify" the value spread across two registers. */ | |
4542 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4543 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4544 | hi->reg_offset = 0; | |
4545 | hi->len = len - lo->len; | |
4546 | } | |
4547 | else | |
4548 | { | |
4549 | /* Only perform a partial copy of the second register. */ | |
4550 | lo->reg_offset = 0; | |
4551 | hi->reg_offset = 0; | |
4552 | if (len > MIPS_SAVED_REGSIZE) | |
4553 | { | |
4554 | lo->len = MIPS_SAVED_REGSIZE; | |
4555 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4556 | } | |
4557 | else | |
4558 | { | |
4559 | lo->len = len; | |
4560 | hi->len = 0; | |
4561 | } | |
4562 | } | |
d7449b42 | 4563 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4564 | && REGISTER_RAW_SIZE (regnum) == 8 |
4565 | && MIPS_SAVED_REGSIZE == 4) | |
4566 | { | |
4567 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4568 | of the register is being used */ |
7a292a7a SS |
4569 | lo->reg_offset += 4; |
4570 | hi->reg_offset += 4; | |
4571 | } | |
4572 | lo->buf_offset = 0; | |
4573 | hi->buf_offset = lo->len; | |
4574 | } | |
4575 | } | |
4576 | ||
4577 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4578 | copy its value into `valbuf'. */ | |
4579 | ||
46cac009 AC |
4580 | static void |
4581 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4582 | char regbuf[], |
46cac009 AC |
4583 | char *valbuf) |
4584 | { | |
4585 | struct return_value_word lo; | |
4586 | struct return_value_word hi; | |
4587 | return_value_location (valtype, &hi, &lo); | |
4588 | ||
4589 | memcpy (valbuf + lo.buf_offset, | |
4590 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4591 | lo.len); | |
4592 | ||
4593 | if (hi.len > 0) | |
4594 | memcpy (valbuf + hi.buf_offset, | |
4595 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4596 | hi.len); | |
4597 | } | |
4598 | ||
46cac009 AC |
4599 | static void |
4600 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4601 | char regbuf[], |
46cac009 AC |
4602 | char *valbuf) |
4603 | { | |
4604 | struct return_value_word lo; | |
4605 | struct return_value_word hi; | |
4606 | return_value_location (valtype, &hi, &lo); | |
4607 | ||
4608 | memcpy (valbuf + lo.buf_offset, | |
4609 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4610 | lo.len); | |
4611 | ||
4612 | if (hi.len > 0) | |
4613 | memcpy (valbuf + hi.buf_offset, | |
4614 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4615 | hi.len); | |
4616 | } | |
4617 | ||
7a292a7a SS |
4618 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4619 | value into the appropriate register. */ | |
4620 | ||
46cac009 AC |
4621 | static void |
4622 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4623 | { | |
d9d9c31f | 4624 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4625 | struct return_value_word lo; |
4626 | struct return_value_word hi; | |
4627 | return_value_location (valtype, &hi, &lo); | |
4628 | ||
4629 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4630 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
73937e03 AC |
4631 | deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer, |
4632 | REGISTER_RAW_SIZE (lo.reg)); | |
46cac009 AC |
4633 | |
4634 | if (hi.len > 0) | |
4635 | { | |
4636 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4637 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
73937e03 AC |
4638 | deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer, |
4639 | REGISTER_RAW_SIZE (hi.reg)); | |
46cac009 AC |
4640 | } |
4641 | } | |
4642 | ||
4643 | static void | |
cb1d2653 | 4644 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4645 | { |
d9d9c31f | 4646 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4647 | struct return_value_word lo; |
4648 | struct return_value_word hi; | |
4649 | return_value_location (valtype, &hi, &lo); | |
4650 | ||
4651 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4652 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
73937e03 AC |
4653 | deprecated_write_register_bytes (REGISTER_BYTE (lo.reg), raw_buffer, |
4654 | REGISTER_RAW_SIZE (lo.reg)); | |
46cac009 AC |
4655 | |
4656 | if (hi.len > 0) | |
4657 | { | |
4658 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4659 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
73937e03 AC |
4660 | deprecated_write_register_bytes (REGISTER_BYTE (hi.reg), raw_buffer, |
4661 | REGISTER_RAW_SIZE (hi.reg)); | |
46cac009 AC |
4662 | } |
4663 | } | |
4664 | ||
cb1d2653 AC |
4665 | /* O32 ABI stuff. */ |
4666 | ||
46cac009 | 4667 | static void |
cb1d2653 AC |
4668 | mips_o32_xfer_return_value (struct type *type, |
4669 | struct regcache *regcache, | |
4670 | bfd_byte *in, const bfd_byte *out) | |
46cac009 | 4671 | { |
cb1d2653 AC |
4672 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4673 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4674 | && TYPE_LENGTH (type) == 4 | |
4675 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4676 | { |
cb1d2653 AC |
4677 | /* A single-precision floating-point value. It fits in the |
4678 | least significant part of FP0. */ | |
4679 | if (mips_debug) | |
4680 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4681 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4682 | TARGET_BYTE_ORDER, in, out, 0); | |
4683 | } | |
4684 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4685 | && TYPE_LENGTH (type) == 8 | |
4686 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4687 | { | |
4688 | /* A double-precision floating-point value. It fits in the | |
4689 | least significant part of FP0/FP1 but with byte ordering | |
4690 | based on the target (???). */ | |
4691 | if (mips_debug) | |
4692 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0/$fp1\n"); | |
4693 | switch (TARGET_BYTE_ORDER) | |
4694 | { | |
4695 | case BFD_ENDIAN_LITTLE: | |
4696 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4697 | TARGET_BYTE_ORDER, in, out, 0); | |
4698 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4699 | TARGET_BYTE_ORDER, in, out, 4); | |
4700 | break; | |
4701 | case BFD_ENDIAN_BIG: | |
4702 | mips_xfer_register (regcache, FP0_REGNUM + 1, 4, | |
4703 | TARGET_BYTE_ORDER, in, out, 0); | |
4704 | mips_xfer_register (regcache, FP0_REGNUM + 0, 4, | |
4705 | TARGET_BYTE_ORDER, in, out, 4); | |
4706 | break; | |
4707 | default: | |
4708 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4709 | } | |
4710 | } | |
4711 | #if 0 | |
4712 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4713 | && TYPE_NFIELDS (type) <= 2 | |
4714 | && TYPE_NFIELDS (type) >= 1 | |
4715 | && ((TYPE_NFIELDS (type) == 1 | |
4716 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4717 | == TYPE_CODE_FLT)) | |
4718 | || (TYPE_NFIELDS (type) == 2 | |
4719 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4720 | == TYPE_CODE_FLT) | |
4721 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4722 | == TYPE_CODE_FLT))) | |
4723 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4724 | { | |
4725 | /* A struct that contains one or two floats. Each value is part | |
4726 | in the least significant part of their floating point | |
4727 | register.. */ | |
d9d9c31f | 4728 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4729 | int regnum; |
4730 | int field; | |
4731 | for (field = 0, regnum = FP0_REGNUM; | |
4732 | field < TYPE_NFIELDS (type); | |
4733 | field++, regnum += 2) | |
4734 | { | |
4735 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4736 | / TARGET_CHAR_BIT); | |
4737 | if (mips_debug) | |
4738 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4739 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4740 | TARGET_BYTE_ORDER, in, out, offset); | |
4741 | } | |
4742 | } | |
4743 | #endif | |
4744 | #if 0 | |
4745 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4746 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4747 | { | |
4748 | /* A structure or union. Extract the left justified value, | |
4749 | regardless of the byte order. I.e. DO NOT USE | |
4750 | mips_xfer_lower. */ | |
4751 | int offset; | |
4752 | int regnum; | |
4753 | for (offset = 0, regnum = V0_REGNUM; | |
4754 | offset < TYPE_LENGTH (type); | |
4755 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4756 | { | |
4757 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4758 | if (offset + xfer > TYPE_LENGTH (type)) | |
4759 | xfer = TYPE_LENGTH (type) - offset; | |
4760 | if (mips_debug) | |
4761 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4762 | offset, xfer, regnum); | |
4763 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4764 | in, out, offset); | |
4765 | } | |
4766 | } | |
4767 | #endif | |
4768 | else | |
4769 | { | |
4770 | /* A scalar extract each part but least-significant-byte | |
4771 | justified. o32 thinks registers are 4 byte, regardless of | |
4772 | the ISA. mips_stack_argsize controls this. */ | |
4773 | int offset; | |
4774 | int regnum; | |
4775 | for (offset = 0, regnum = V0_REGNUM; | |
4776 | offset < TYPE_LENGTH (type); | |
4777 | offset += mips_stack_argsize (), regnum++) | |
4778 | { | |
4779 | int xfer = mips_stack_argsize (); | |
4780 | int pos = 0; | |
4781 | if (offset + xfer > TYPE_LENGTH (type)) | |
4782 | xfer = TYPE_LENGTH (type) - offset; | |
4783 | if (mips_debug) | |
4784 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4785 | offset, xfer, regnum); | |
4786 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4787 | in, out, offset); | |
4788 | } | |
46cac009 AC |
4789 | } |
4790 | } | |
4791 | ||
cb1d2653 AC |
4792 | static void |
4793 | mips_o32_extract_return_value (struct type *type, | |
4794 | struct regcache *regcache, | |
ebba8386 | 4795 | void *valbuf) |
cb1d2653 AC |
4796 | { |
4797 | mips_o32_xfer_return_value (type, regcache, valbuf, NULL); | |
4798 | } | |
4799 | ||
4800 | static void | |
4801 | mips_o32_store_return_value (struct type *type, char *valbuf) | |
4802 | { | |
4803 | mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf); | |
4804 | } | |
4805 | ||
4806 | /* N32/N44 ABI stuff. */ | |
4807 | ||
46cac009 | 4808 | static void |
88658117 AC |
4809 | mips_n32n64_xfer_return_value (struct type *type, |
4810 | struct regcache *regcache, | |
4811 | bfd_byte *in, const bfd_byte *out) | |
c906108c | 4812 | { |
88658117 AC |
4813 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4814 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4815 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4816 | { |
88658117 AC |
4817 | /* A floating-point value belongs in the least significant part |
4818 | of FP0. */ | |
4819 | if (mips_debug) | |
4820 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4821 | mips_xfer_register (regcache, FP0_REGNUM, TYPE_LENGTH (type), | |
4822 | TARGET_BYTE_ORDER, in, out, 0); | |
4823 | } | |
4824 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4825 | && TYPE_NFIELDS (type) <= 2 | |
4826 | && TYPE_NFIELDS (type) >= 1 | |
4827 | && ((TYPE_NFIELDS (type) == 1 | |
4828 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4829 | == TYPE_CODE_FLT)) | |
4830 | || (TYPE_NFIELDS (type) == 2 | |
4831 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4832 | == TYPE_CODE_FLT) | |
4833 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4834 | == TYPE_CODE_FLT))) | |
4835 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4836 | { | |
4837 | /* A struct that contains one or two floats. Each value is part | |
4838 | in the least significant part of their floating point | |
4839 | register.. */ | |
d9d9c31f | 4840 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4841 | int regnum; |
4842 | int field; | |
4843 | for (field = 0, regnum = FP0_REGNUM; | |
4844 | field < TYPE_NFIELDS (type); | |
4845 | field++, regnum += 2) | |
4846 | { | |
4847 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4848 | / TARGET_CHAR_BIT); | |
4849 | if (mips_debug) | |
4850 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
4851 | mips_xfer_register (regcache, regnum, TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4852 | TARGET_BYTE_ORDER, in, out, offset); | |
4853 | } | |
7a292a7a | 4854 | } |
88658117 AC |
4855 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4856 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4857 | { | |
4858 | /* A structure or union. Extract the left justified value, | |
4859 | regardless of the byte order. I.e. DO NOT USE | |
4860 | mips_xfer_lower. */ | |
4861 | int offset; | |
4862 | int regnum; | |
4863 | for (offset = 0, regnum = V0_REGNUM; | |
4864 | offset < TYPE_LENGTH (type); | |
4865 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4866 | { | |
4867 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4868 | if (offset + xfer > TYPE_LENGTH (type)) | |
4869 | xfer = TYPE_LENGTH (type) - offset; | |
4870 | if (mips_debug) | |
4871 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4872 | offset, xfer, regnum); | |
4873 | mips_xfer_register (regcache, regnum, xfer, BFD_ENDIAN_UNKNOWN, | |
4874 | in, out, offset); | |
4875 | } | |
4876 | } | |
4877 | else | |
4878 | { | |
4879 | /* A scalar extract each part but least-significant-byte | |
4880 | justified. */ | |
4881 | int offset; | |
4882 | int regnum; | |
4883 | for (offset = 0, regnum = V0_REGNUM; | |
4884 | offset < TYPE_LENGTH (type); | |
4885 | offset += REGISTER_RAW_SIZE (regnum), regnum++) | |
4886 | { | |
4887 | int xfer = REGISTER_RAW_SIZE (regnum); | |
4888 | int pos = 0; | |
4889 | if (offset + xfer > TYPE_LENGTH (type)) | |
4890 | xfer = TYPE_LENGTH (type) - offset; | |
4891 | if (mips_debug) | |
4892 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4893 | offset, xfer, regnum); | |
4894 | mips_xfer_register (regcache, regnum, xfer, TARGET_BYTE_ORDER, | |
4895 | in, out, offset); | |
4896 | } | |
4897 | } | |
4898 | } | |
4899 | ||
4900 | static void | |
4901 | mips_n32n64_extract_return_value (struct type *type, | |
4902 | struct regcache *regcache, | |
ebba8386 | 4903 | void *valbuf) |
88658117 AC |
4904 | { |
4905 | mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); | |
4906 | } | |
4907 | ||
4908 | static void | |
4909 | mips_n32n64_store_return_value (struct type *type, char *valbuf) | |
4910 | { | |
4911 | mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); | |
c906108c SS |
4912 | } |
4913 | ||
2f1488ce | 4914 | static CORE_ADDR |
6672060b | 4915 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
4916 | { |
4917 | /* FIXME: This will only work at random. The caller passes the | |
4918 | struct_return address in V0, but it is not preserved. It may | |
4919 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
4920 | LONGEST val; |
4921 | ||
4922 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 4923 | return val; |
2f1488ce MS |
4924 | } |
4925 | ||
c906108c SS |
4926 | /* Exported procedure: Is PC in the signal trampoline code */ |
4927 | ||
102182a9 MS |
4928 | static int |
4929 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
4930 | { |
4931 | if (sigtramp_address == 0) | |
4932 | fixup_sigtramp (); | |
4933 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
4934 | } | |
4935 | ||
a5ea2558 AC |
4936 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4937 | used for all MIPS-specific commands. */ | |
4938 | ||
a5ea2558 | 4939 | static void |
acdb74a0 | 4940 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4941 | { |
4942 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4943 | } | |
4944 | ||
a5ea2558 | 4945 | static void |
acdb74a0 | 4946 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4947 | { |
4948 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
4949 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
4950 | } | |
4951 | ||
c906108c SS |
4952 | /* Commands to show/set the MIPS FPU type. */ |
4953 | ||
c906108c | 4954 | static void |
acdb74a0 | 4955 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4956 | { |
c906108c SS |
4957 | char *fpu; |
4958 | switch (MIPS_FPU_TYPE) | |
4959 | { | |
4960 | case MIPS_FPU_SINGLE: | |
4961 | fpu = "single-precision"; | |
4962 | break; | |
4963 | case MIPS_FPU_DOUBLE: | |
4964 | fpu = "double-precision"; | |
4965 | break; | |
4966 | case MIPS_FPU_NONE: | |
4967 | fpu = "absent (none)"; | |
4968 | break; | |
93d56215 AC |
4969 | default: |
4970 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4971 | } |
4972 | if (mips_fpu_type_auto) | |
4973 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4974 | fpu); | |
4975 | else | |
4976 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
4977 | fpu); | |
4978 | } | |
4979 | ||
4980 | ||
c906108c | 4981 | static void |
acdb74a0 | 4982 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
4983 | { |
4984 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
4985 | show_mipsfpu_command (args, from_tty); | |
4986 | } | |
4987 | ||
c906108c | 4988 | static void |
acdb74a0 | 4989 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
4990 | { |
4991 | mips_fpu_type = MIPS_FPU_SINGLE; | |
4992 | mips_fpu_type_auto = 0; | |
9e364162 | 4993 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
4994 | } |
4995 | ||
c906108c | 4996 | static void |
acdb74a0 | 4997 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
4998 | { |
4999 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5000 | mips_fpu_type_auto = 0; | |
9e364162 | 5001 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5002 | } |
5003 | ||
c906108c | 5004 | static void |
acdb74a0 | 5005 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5006 | { |
5007 | mips_fpu_type = MIPS_FPU_NONE; | |
5008 | mips_fpu_type_auto = 0; | |
9e364162 | 5009 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5010 | } |
5011 | ||
c906108c | 5012 | static void |
acdb74a0 | 5013 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5014 | { |
5015 | mips_fpu_type_auto = 1; | |
5016 | } | |
5017 | ||
5018 | /* Command to set the processor type. */ | |
5019 | ||
5020 | void | |
acdb74a0 | 5021 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
5022 | { |
5023 | int i; | |
5024 | ||
5025 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
5026 | { | |
5027 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
5028 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5029 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
5030 | ||
5031 | /* Restore the value. */ | |
4fcf66da | 5032 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5033 | |
5034 | return; | |
5035 | } | |
c5aa993b | 5036 | |
c906108c SS |
5037 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
5038 | { | |
5039 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
5040 | /* Restore its value. */ | |
4fcf66da | 5041 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
5042 | } |
5043 | } | |
5044 | ||
5045 | static void | |
acdb74a0 | 5046 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
5047 | { |
5048 | } | |
5049 | ||
5050 | /* Modify the actual processor type. */ | |
5051 | ||
5a89d8aa | 5052 | static int |
acdb74a0 | 5053 | mips_set_processor_type (char *str) |
c906108c | 5054 | { |
1012bd0e | 5055 | int i; |
c906108c SS |
5056 | |
5057 | if (str == NULL) | |
5058 | return 0; | |
5059 | ||
5060 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
5061 | { | |
5062 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
5063 | { | |
5064 | mips_processor_type = str; | |
cce74817 | 5065 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 5066 | return 1; |
c906108c SS |
5067 | /* FIXME tweak fpu flag too */ |
5068 | } | |
5069 | } | |
5070 | ||
5071 | return 0; | |
5072 | } | |
5073 | ||
5074 | /* Attempt to identify the particular processor model by reading the | |
5075 | processor id. */ | |
5076 | ||
5077 | char * | |
acdb74a0 | 5078 | mips_read_processor_type (void) |
c906108c SS |
5079 | { |
5080 | CORE_ADDR prid; | |
5081 | ||
5082 | prid = read_register (PRID_REGNUM); | |
5083 | ||
5084 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 5085 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
5086 | |
5087 | return NULL; | |
5088 | } | |
5089 | ||
5090 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5091 | callable as an sfunc. */ | |
5092 | ||
5093 | static void | |
acdb74a0 AC |
5094 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5095 | struct cmd_list_element *c) | |
c906108c SS |
5096 | { |
5097 | reinit_frame_cache (); | |
5098 | } | |
5099 | ||
5100 | int | |
acdb74a0 | 5101 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
5102 | { |
5103 | mips_extra_func_info_t proc_desc; | |
5104 | ||
5105 | /* Search for the function containing this address. Set the low bit | |
5106 | of the address when searching, in case we were given an even address | |
5107 | that is the start of a 16-bit function. If we didn't do this, | |
5108 | the search would fail because the symbol table says the function | |
5109 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5110 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
5111 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
5112 | ||
5113 | /* Make an attempt to determine if this is a 16-bit function. If | |
5114 | the procedure descriptor exists and the address therein is odd, | |
5115 | it's definitely a 16-bit function. Otherwise, we have to just | |
5116 | guess that if the address passed in is odd, it's 16-bits. */ | |
5117 | if (proc_desc) | |
361d1df0 | 5118 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
65c11066 | 5119 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c | 5120 | else |
361d1df0 | 5121 | info->mach = pc_is_mips16 (memaddr) ? |
65c11066 | 5122 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c SS |
5123 | |
5124 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5125 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5126 | |
c906108c | 5127 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5128 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5129 | return print_insn_big_mips (memaddr, info); |
5130 | else | |
5131 | return print_insn_little_mips (memaddr, info); | |
5132 | } | |
5133 | ||
c906108c SS |
5134 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5135 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5136 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5137 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5138 | (if necessary) to point to the actual memory location where the | |
5139 | breakpoint should be inserted. */ | |
5140 | ||
f7ab6ec6 | 5141 | static const unsigned char * |
acdb74a0 | 5142 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5143 | { |
d7449b42 | 5144 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5145 | { |
5146 | if (pc_is_mips16 (*pcptr)) | |
5147 | { | |
aaab4dba | 5148 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
c906108c | 5149 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 5150 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5151 | return mips16_big_breakpoint; |
5152 | } | |
5153 | else | |
5154 | { | |
aaab4dba AC |
5155 | /* The IDT board uses an unusual breakpoint value, and |
5156 | sometimes gets confused when it sees the usual MIPS | |
5157 | breakpoint instruction. */ | |
5158 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5159 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5160 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5161 | |
c5aa993b | 5162 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5163 | |
5164 | if (strcmp (target_shortname, "mips") == 0) | |
5165 | return idt_big_breakpoint; | |
5166 | else if (strcmp (target_shortname, "ddb") == 0 | |
5167 | || strcmp (target_shortname, "pmon") == 0 | |
5168 | || strcmp (target_shortname, "lsi") == 0) | |
5169 | return pmon_big_breakpoint; | |
5170 | else | |
5171 | return big_breakpoint; | |
5172 | } | |
5173 | } | |
5174 | else | |
5175 | { | |
5176 | if (pc_is_mips16 (*pcptr)) | |
5177 | { | |
aaab4dba | 5178 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
c906108c | 5179 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 5180 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5181 | return mips16_little_breakpoint; |
5182 | } | |
5183 | else | |
5184 | { | |
aaab4dba AC |
5185 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5186 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5187 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5188 | |
c5aa993b | 5189 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5190 | |
5191 | if (strcmp (target_shortname, "mips") == 0) | |
5192 | return idt_little_breakpoint; | |
5193 | else if (strcmp (target_shortname, "ddb") == 0 | |
5194 | || strcmp (target_shortname, "pmon") == 0 | |
5195 | || strcmp (target_shortname, "lsi") == 0) | |
5196 | return pmon_little_breakpoint; | |
5197 | else | |
5198 | return little_breakpoint; | |
5199 | } | |
5200 | } | |
5201 | } | |
5202 | ||
5203 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5204 | PC, which is either the callee or the caller. There are several | |
5205 | cases which must be handled: | |
5206 | ||
5207 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5208 | target PC is in $31 ($ra). |
c906108c | 5209 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5210 | and the target PC is in $2. |
c906108c | 5211 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5212 | before the jal instruction, this is effectively a call stub |
5213 | and the the target PC is in $2. Otherwise this is effectively | |
5214 | a return stub and the target PC is in $18. | |
c906108c SS |
5215 | |
5216 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5217 | gory details. | |
5218 | ||
5219 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5220 | */ |
c906108c | 5221 | |
757a7cc6 | 5222 | static CORE_ADDR |
acdb74a0 | 5223 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5224 | { |
5225 | char *name; | |
5226 | CORE_ADDR start_addr; | |
5227 | ||
5228 | /* Find the starting address and name of the function containing the PC. */ | |
5229 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5230 | return 0; | |
5231 | ||
5232 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5233 | target PC is in $31 ($ra). */ | |
5234 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5235 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5236 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5237 | |
5238 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5239 | { | |
5240 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5241 | and the target PC is in $2. */ | |
5242 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5243 | return read_signed_register (2); |
c906108c SS |
5244 | |
5245 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5246 | before the jal instruction, this is effectively a call stub |
5247 | and the the target PC is in $2. Otherwise this is effectively | |
5248 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5249 | else if (name[19] == 's' || name[19] == 'd') |
5250 | { | |
5251 | if (pc == start_addr) | |
5252 | { | |
5253 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5254 | stub. Such a stub for a function bar might have a name |
5255 | like __fn_stub_bar, and might look like this: | |
5256 | mfc1 $4,$f13 | |
5257 | mfc1 $5,$f12 | |
5258 | mfc1 $6,$f15 | |
5259 | mfc1 $7,$f14 | |
5260 | la $1,bar (becomes a lui/addiu pair) | |
5261 | jr $1 | |
5262 | So scan down to the lui/addi and extract the target | |
5263 | address from those two instructions. */ | |
c906108c | 5264 | |
6c997a34 | 5265 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5266 | t_inst inst; |
5267 | int i; | |
5268 | ||
5269 | /* See if the name of the target function is __fn_stub_*. */ | |
5270 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5271 | return target_pc; | |
5272 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5273 | && strcmp (name, "etext") != 0 | |
5274 | && strcmp (name, "_etext") != 0) | |
5275 | return target_pc; | |
5276 | ||
5277 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5278 | The limit on the search is arbitrarily set to 20 |
5279 | instructions. FIXME. */ | |
c906108c SS |
5280 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5281 | { | |
c5aa993b JM |
5282 | inst = mips_fetch_instruction (target_pc); |
5283 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5284 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5285 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5286 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5287 | } |
5288 | ||
5289 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5290 | return target_pc; | |
5291 | } | |
5292 | else | |
5293 | /* This is the 'return' part of a call stub. The return | |
5294 | address is in $r18. */ | |
6c997a34 | 5295 | return read_signed_register (18); |
c906108c SS |
5296 | } |
5297 | } | |
c5aa993b | 5298 | return 0; /* not a stub */ |
c906108c SS |
5299 | } |
5300 | ||
5301 | ||
5302 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5303 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5304 | ||
757a7cc6 | 5305 | static int |
acdb74a0 | 5306 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5307 | { |
5308 | CORE_ADDR start_addr; | |
5309 | ||
5310 | /* Find the starting address of the function containing the PC. If the | |
5311 | caller didn't give us a name, look it up at the same time. */ | |
5312 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5313 | return 0; | |
5314 | ||
5315 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5316 | { | |
5317 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5318 | if (name[19] >= '0' && name[19] <= '9') | |
5319 | return 1; | |
5320 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5321 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5322 | else if (name[19] == 's' || name[19] == 'd') |
5323 | return pc == start_addr; | |
5324 | } | |
5325 | ||
c5aa993b | 5326 | return 0; /* not a stub */ |
c906108c SS |
5327 | } |
5328 | ||
5329 | ||
5330 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5331 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5332 | ||
e41b17f0 | 5333 | static int |
acdb74a0 | 5334 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5335 | { |
5336 | CORE_ADDR start_addr; | |
5337 | ||
5338 | /* Find the starting address of the function containing the PC. */ | |
5339 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5340 | return 0; | |
5341 | ||
5342 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5343 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5344 | || strcmp (name, "__mips16_ret_df") == 0) | |
5345 | return 1; | |
5346 | ||
5347 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5348 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5349 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5350 | && (name[19] == 's' || name[19] == 'd') | |
5351 | && pc != start_addr) | |
5352 | return 1; | |
5353 | ||
c5aa993b | 5354 | return 0; /* not a stub */ |
c906108c SS |
5355 | } |
5356 | ||
5357 | ||
5358 | /* Return non-zero if the PC is in a library helper function that should | |
5359 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5360 | ||
5361 | int | |
acdb74a0 | 5362 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5363 | { |
5364 | char *name; | |
5365 | ||
5366 | /* Find the starting address and name of the function containing the PC. */ | |
5367 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5368 | return 0; | |
5369 | ||
5370 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5371 | that we want to ignore. */ | |
5372 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5373 | || strcmp (name, "__mips16_ret_df") == 0); | |
5374 | } | |
5375 | ||
5376 | ||
5377 | /* Return a location where we can set a breakpoint that will be hit | |
5378 | when an inferior function call returns. This is normally the | |
5379 | program's entry point. Executables that don't have an entry | |
5380 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
5381 | whose address is the location where the breakpoint should be placed. */ | |
5382 | ||
f7ab6ec6 | 5383 | static CORE_ADDR |
acdb74a0 | 5384 | mips_call_dummy_address (void) |
c906108c SS |
5385 | { |
5386 | struct minimal_symbol *sym; | |
5387 | ||
5388 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
5389 | if (sym) | |
5390 | return SYMBOL_VALUE_ADDRESS (sym); | |
5391 | else | |
5392 | return entry_point_address (); | |
5393 | } | |
5394 | ||
5395 | ||
47a8d4ba AC |
5396 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5397 | the register stored on the stack (32) is different to its real raw | |
5398 | size (64). The below ensures that registers are fetched from the | |
5399 | stack using their ABI size and then stored into the RAW_BUFFER | |
5400 | using their raw size. | |
5401 | ||
5402 | The alternative to adding this function would be to add an ABI | |
5403 | macro - REGISTER_STACK_SIZE(). */ | |
5404 | ||
5405 | static void | |
acdb74a0 | 5406 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5407 | int *optimizedp, |
acdb74a0 AC |
5408 | CORE_ADDR *addrp, |
5409 | struct frame_info *frame, | |
5410 | int regnum, | |
795e1e11 | 5411 | enum lval_type *lvalp) |
47a8d4ba | 5412 | { |
795e1e11 AC |
5413 | CORE_ADDR addrx; |
5414 | enum lval_type lvalx; | |
5415 | int optimizedx; | |
47a8d4ba AC |
5416 | |
5417 | if (!target_has_registers) | |
5418 | error ("No registers."); | |
5419 | ||
795e1e11 AC |
5420 | /* Make certain that all needed parameters are present. */ |
5421 | if (addrp == NULL) | |
5422 | addrp = &addrx; | |
5423 | if (lvalp == NULL) | |
5424 | lvalp = &lvalx; | |
5425 | if (optimizedp == NULL) | |
5426 | optimizedp = &optimizedx; | |
f796e4be KB |
5427 | generic_unwind_get_saved_register (raw_buffer, optimizedp, addrp, frame, |
5428 | regnum, lvalp); | |
795e1e11 AC |
5429 | /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should |
5430 | have a pseudo register range that correspons to the ABI's, rather | |
5431 | than the ISA's, view of registers. These registers would then | |
5432 | implicitly describe their size and hence could be used without | |
5433 | the below munging. */ | |
5434 | if ((*lvalp) == lval_memory) | |
47a8d4ba | 5435 | { |
47a8d4ba AC |
5436 | if (raw_buffer != NULL) |
5437 | { | |
47a8d4ba | 5438 | if (regnum < 32) |
795e1e11 AC |
5439 | { |
5440 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
5441 | saved. */ | |
5442 | LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE); | |
fbd9dcd3 | 5443 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), val); |
795e1e11 | 5444 | } |
47a8d4ba AC |
5445 | } |
5446 | } | |
47a8d4ba | 5447 | } |
2acceee2 | 5448 | |
f7b9e9fc AC |
5449 | /* Immediately after a function call, return the saved pc. |
5450 | Can't always go through the frames for this because on some machines | |
5451 | the new frame is not set up until the new function executes | |
5452 | some instructions. */ | |
5453 | ||
5454 | static CORE_ADDR | |
5455 | mips_saved_pc_after_call (struct frame_info *frame) | |
5456 | { | |
6c997a34 | 5457 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5458 | } |
5459 | ||
5460 | ||
88c72b7d AC |
5461 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
5462 | REGNUM */ | |
5463 | ||
5464 | static int | |
5465 | mips_stab_reg_to_regnum (int num) | |
5466 | { | |
2f38ef89 | 5467 | if (num >= 0 && num < 32) |
88c72b7d | 5468 | return num; |
2f38ef89 | 5469 | else if (num >= 38 && num < 70) |
88c72b7d | 5470 | return num + FP0_REGNUM - 38; |
040b99fd KB |
5471 | else if (num == 70) |
5472 | return HI_REGNUM; | |
5473 | else if (num == 71) | |
5474 | return LO_REGNUM; | |
2f38ef89 KB |
5475 | else |
5476 | { | |
5477 | /* This will hopefully (eventually) provoke a warning. Should | |
5478 | we be calling complaint() here? */ | |
5479 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5480 | } | |
88c72b7d AC |
5481 | } |
5482 | ||
2f38ef89 KB |
5483 | |
5484 | /* Convert a dwarf, dwarf2, or ecoff register number to a gdb REGNUM */ | |
88c72b7d AC |
5485 | |
5486 | static int | |
2f38ef89 | 5487 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5488 | { |
2f38ef89 | 5489 | if (num >= 0 && num < 32) |
88c72b7d | 5490 | return num; |
2f38ef89 | 5491 | else if (num >= 32 && num < 64) |
88c72b7d | 5492 | return num + FP0_REGNUM - 32; |
040b99fd KB |
5493 | else if (num == 64) |
5494 | return HI_REGNUM; | |
5495 | else if (num == 65) | |
5496 | return LO_REGNUM; | |
2f38ef89 KB |
5497 | else |
5498 | { | |
5499 | /* This will hopefully (eventually) provoke a warning. Should | |
5500 | we be calling complaint() here? */ | |
5501 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5502 | } | |
88c72b7d AC |
5503 | } |
5504 | ||
2f38ef89 | 5505 | |
fc0c74b1 AC |
5506 | /* Convert an integer into an address. By first converting the value |
5507 | into a pointer and then extracting it signed, the address is | |
5508 | guarenteed to be correctly sign extended. */ | |
5509 | ||
5510 | static CORE_ADDR | |
5511 | mips_integer_to_address (struct type *type, void *buf) | |
5512 | { | |
5513 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5514 | LONGEST val = unpack_long (type, buf); | |
5515 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5516 | return extract_signed_integer (tmp, | |
5517 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5518 | } | |
5519 | ||
caaa3122 DJ |
5520 | static void |
5521 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5522 | { | |
5523 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5524 | const char *name = bfd_get_section_name (abfd, sect); | |
5525 | ||
5526 | if (*abip != MIPS_ABI_UNKNOWN) | |
5527 | return; | |
5528 | ||
5529 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5530 | return; | |
5531 | ||
5532 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5533 | *abip = MIPS_ABI_O32; | |
5534 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5535 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5536 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5537 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5538 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5539 | *abip = MIPS_ABI_O64; | |
5540 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5541 | *abip = MIPS_ABI_EABI32; | |
5542 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5543 | *abip = MIPS_ABI_EABI64; | |
5544 | else | |
5545 | warning ("unsupported ABI %s.", name + 8); | |
5546 | } | |
5547 | ||
2e4ebe70 DJ |
5548 | static enum mips_abi |
5549 | global_mips_abi (void) | |
5550 | { | |
5551 | int i; | |
5552 | ||
5553 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5554 | if (mips_abi_strings[i] == mips_abi_string) | |
5555 | return (enum mips_abi) i; | |
5556 | ||
5557 | internal_error (__FILE__, __LINE__, | |
5558 | "unknown ABI string"); | |
5559 | } | |
5560 | ||
c2d11a7d | 5561 | static struct gdbarch * |
acdb74a0 AC |
5562 | mips_gdbarch_init (struct gdbarch_info info, |
5563 | struct gdbarch_list *arches) | |
c2d11a7d | 5564 | { |
c2d11a7d JM |
5565 | struct gdbarch *gdbarch; |
5566 | struct gdbarch_tdep *tdep; | |
5567 | int elf_flags; | |
2e4ebe70 | 5568 | enum mips_abi mips_abi, found_abi, wanted_abi; |
c2d11a7d | 5569 | |
1d06468c EZ |
5570 | /* Reset the disassembly info, in case it was set to something |
5571 | non-default. */ | |
810ecf9f AC |
5572 | deprecated_tm_print_insn_info.flavour = bfd_target_unknown_flavour; |
5573 | deprecated_tm_print_insn_info.arch = bfd_arch_unknown; | |
5574 | deprecated_tm_print_insn_info.mach = 0; | |
1d06468c | 5575 | |
70f80edf JT |
5576 | elf_flags = 0; |
5577 | ||
5578 | if (info.abfd) | |
5579 | { | |
5580 | /* First of all, extract the elf_flags, if available. */ | |
5581 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5582 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5583 | } |
c2d11a7d | 5584 | |
102182a9 | 5585 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5586 | switch ((elf_flags & EF_MIPS_ABI)) |
5587 | { | |
5588 | case E_MIPS_ABI_O32: | |
5589 | mips_abi = MIPS_ABI_O32; | |
5590 | break; | |
5591 | case E_MIPS_ABI_O64: | |
5592 | mips_abi = MIPS_ABI_O64; | |
5593 | break; | |
5594 | case E_MIPS_ABI_EABI32: | |
5595 | mips_abi = MIPS_ABI_EABI32; | |
5596 | break; | |
5597 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5598 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5599 | break; |
5600 | default: | |
acdb74a0 AC |
5601 | if ((elf_flags & EF_MIPS_ABI2)) |
5602 | mips_abi = MIPS_ABI_N32; | |
5603 | else | |
5604 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5605 | break; |
5606 | } | |
acdb74a0 | 5607 | |
caaa3122 DJ |
5608 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5609 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5610 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5611 | ||
2e4ebe70 DJ |
5612 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5613 | Use the ABI from the last architecture if there is one. */ | |
5614 | if (info.abfd == NULL && arches != NULL) | |
5615 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5616 | ||
32a6503c | 5617 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5618 | if (mips_abi == MIPS_ABI_UNKNOWN |
5619 | && info.bfd_arch_info != NULL | |
5620 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5621 | { | |
5622 | switch (info.bfd_arch_info->mach) | |
5623 | { | |
5624 | case bfd_mach_mips3900: | |
5625 | mips_abi = MIPS_ABI_EABI32; | |
5626 | break; | |
5627 | case bfd_mach_mips4100: | |
5628 | case bfd_mach_mips5000: | |
5629 | mips_abi = MIPS_ABI_EABI64; | |
5630 | break; | |
1d06468c EZ |
5631 | case bfd_mach_mips8000: |
5632 | case bfd_mach_mips10000: | |
32a6503c KB |
5633 | /* On Irix, ELF64 executables use the N64 ABI. The |
5634 | pseudo-sections which describe the ABI aren't present | |
5635 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5636 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5637 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5638 | mips_abi = MIPS_ABI_N64; | |
5639 | else | |
5640 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5641 | break; |
bf64bfd6 AC |
5642 | } |
5643 | } | |
2e4ebe70 | 5644 | |
2e4ebe70 DJ |
5645 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5646 | mips_abi = MIPS_ABI_O32; | |
5647 | ||
5648 | /* Now that we have found what the ABI for this binary would be, | |
5649 | check whether the user is overriding it. */ | |
5650 | found_abi = mips_abi; | |
5651 | wanted_abi = global_mips_abi (); | |
5652 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5653 | mips_abi = wanted_abi; | |
5654 | ||
810ecf9f | 5655 | /* We have to set deprecated_tm_print_insn_info before looking for a |
2252e863 AO |
5656 | pre-existing architecture, otherwise we may return before we get |
5657 | a chance to set it up. */ | |
5658 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5659 | { | |
5660 | /* Set up the disassembler info, so that we get the right | |
5661 | register names from libopcodes. */ | |
5662 | if (mips_abi == MIPS_ABI_N32) | |
810ecf9f | 5663 | deprecated_tm_print_insn_info.disassembler_options = "gpr-names=n32"; |
2252e863 | 5664 | else |
810ecf9f AC |
5665 | deprecated_tm_print_insn_info.disassembler_options = "gpr-names=64"; |
5666 | deprecated_tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5667 | deprecated_tm_print_insn_info.arch = bfd_arch_mips; | |
2252e863 AO |
5668 | if (info.bfd_arch_info != NULL |
5669 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5670 | && info.bfd_arch_info->mach) | |
810ecf9f | 5671 | deprecated_tm_print_insn_info.mach = info.bfd_arch_info->mach; |
2252e863 | 5672 | else |
810ecf9f | 5673 | deprecated_tm_print_insn_info.mach = bfd_mach_mips8000; |
2252e863 AO |
5674 | } |
5675 | else | |
5676 | /* This string is not recognized explicitly by the disassembler, | |
5677 | but it tells the disassembler to not try to guess the ABI from | |
5678 | the bfd elf headers, such that, if the user overrides the ABI | |
5679 | of a program linked as NewABI, the disassembly will follow the | |
5680 | register naming conventions specified by the user. */ | |
810ecf9f | 5681 | deprecated_tm_print_insn_info.disassembler_options = "gpr-names=32"; |
2252e863 | 5682 | |
4b9b3959 AC |
5683 | if (gdbarch_debug) |
5684 | { | |
5685 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5686 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5687 | elf_flags); |
4b9b3959 AC |
5688 | fprintf_unfiltered (gdb_stdlog, |
5689 | "mips_gdbarch_init: mips_abi = %d\n", | |
5690 | mips_abi); | |
2e4ebe70 DJ |
5691 | fprintf_unfiltered (gdb_stdlog, |
5692 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5693 | found_abi); | |
4b9b3959 | 5694 | } |
0dadbba0 | 5695 | |
c2d11a7d JM |
5696 | /* try to find a pre-existing architecture */ |
5697 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5698 | arches != NULL; | |
5699 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5700 | { | |
5701 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5702 | using. */ |
9103eae0 | 5703 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5704 | continue; |
9103eae0 | 5705 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5706 | continue; |
4be87837 | 5707 | return arches->gdbarch; |
c2d11a7d JM |
5708 | } |
5709 | ||
102182a9 | 5710 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5711 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5712 | gdbarch = gdbarch_alloc (&info, tdep); | |
5713 | tdep->elf_flags = elf_flags; | |
5714 | ||
102182a9 | 5715 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5716 | set_gdbarch_short_bit (gdbarch, 16); |
5717 | set_gdbarch_int_bit (gdbarch, 32); | |
5718 | set_gdbarch_float_bit (gdbarch, 32); | |
5719 | set_gdbarch_double_bit (gdbarch, 64); | |
5720 | set_gdbarch_long_double_bit (gdbarch, 64); | |
46cd78fb | 5721 | set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); |
2e4ebe70 | 5722 | tdep->found_abi = found_abi; |
0dadbba0 | 5723 | tdep->mips_abi = mips_abi; |
1d06468c | 5724 | |
f7ab6ec6 MS |
5725 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5726 | mips_elf_make_msymbol_special); | |
5727 | ||
4be87837 | 5728 | if (info.osabi == GDB_OSABI_IRIX) |
fe29b929 KB |
5729 | set_gdbarch_num_regs (gdbarch, 71); |
5730 | else | |
5731 | set_gdbarch_num_regs (gdbarch, 90); | |
5732 | ||
0dadbba0 | 5733 | switch (mips_abi) |
c2d11a7d | 5734 | { |
0dadbba0 | 5735 | case MIPS_ABI_O32: |
25ab4790 | 5736 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
ebba8386 | 5737 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); |
cb1d2653 | 5738 | set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); |
a5ea2558 | 5739 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5740 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5741 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5742 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5743 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5744 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5745 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5746 | set_gdbarch_long_bit (gdbarch, 32); |
5747 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5748 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5749 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5750 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5751 | set_gdbarch_use_struct_convention (gdbarch, |
5752 | mips_o32_use_struct_convention); | |
c2d11a7d | 5753 | break; |
0dadbba0 | 5754 | case MIPS_ABI_O64: |
25ab4790 | 5755 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5756 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5757 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5758 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5759 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5760 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5761 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5762 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5763 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 5764 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5765 | set_gdbarch_long_bit (gdbarch, 32); |
5766 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5767 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5768 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5769 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5770 | set_gdbarch_use_struct_convention (gdbarch, |
5771 | mips_o32_use_struct_convention); | |
c2d11a7d | 5772 | break; |
0dadbba0 | 5773 | case MIPS_ABI_EABI32: |
25ab4790 | 5774 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5775 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5776 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5777 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5778 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5779 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5780 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5781 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5782 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5783 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5784 | set_gdbarch_long_bit (gdbarch, 32); |
5785 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5786 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5787 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5788 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5789 | set_gdbarch_use_struct_convention (gdbarch, |
5790 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5791 | break; |
0dadbba0 | 5792 | case MIPS_ABI_EABI64: |
25ab4790 | 5793 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5794 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5795 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5796 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5797 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5798 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5799 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5800 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5801 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5802 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5803 | set_gdbarch_long_bit (gdbarch, 64); |
5804 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5805 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5806 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5807 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5808 | set_gdbarch_use_struct_convention (gdbarch, |
5809 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5810 | break; |
0dadbba0 | 5811 | case MIPS_ABI_N32: |
25ab4790 | 5812 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5813 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5814 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
63db5580 | 5815 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5816 | tdep->mips_default_stack_argsize = 8; |
5817 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
5818 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5819 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
6acdf5c7 | 5820 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5821 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5822 | set_gdbarch_long_bit (gdbarch, 32); |
5823 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5824 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5825 | set_gdbarch_use_struct_convention (gdbarch, |
5826 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5827 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5828 | mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5829 | break; |
5830 | case MIPS_ABI_N64: | |
25ab4790 | 5831 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
ebba8386 | 5832 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); |
88658117 | 5833 | set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); |
28d169de KB |
5834 | tdep->mips_default_saved_regsize = 8; |
5835 | tdep->mips_default_stack_argsize = 8; | |
5836 | tdep->mips_fp_register_double = 1; | |
5837 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
5838 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
28d169de KB |
5839 | tdep->gdb_target_is_mips64 = 1; |
5840 | tdep->default_mask_address_p = 0; | |
5841 | set_gdbarch_long_bit (gdbarch, 64); | |
5842 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5843 | set_gdbarch_long_long_bit (gdbarch, 64); | |
cb811fe7 MS |
5844 | set_gdbarch_use_struct_convention (gdbarch, |
5845 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5846 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5847 | mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5848 | break; |
c2d11a7d | 5849 | default: |
2e4ebe70 DJ |
5850 | internal_error (__FILE__, __LINE__, |
5851 | "unknown ABI in switch"); | |
c2d11a7d JM |
5852 | } |
5853 | ||
a5ea2558 AC |
5854 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5855 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5856 | comment: | |
5857 | ||
5858 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5859 | flag in object files because to do so would make it impossible to | |
102182a9 | 5860 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5861 | unnecessarily restrictive. |
361d1df0 | 5862 | |
a5ea2558 AC |
5863 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5864 | but to set this flag before gcc is built with such multilibs will | |
5865 | break too many systems.'' | |
5866 | ||
5867 | But even more unhelpfully, the default linker output target for | |
5868 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5869 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5870 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5871 | this flag to detect 32-bit mode would do the wrong thing given |
5872 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5873 | as 32-bit programs by default. */ |
a5ea2558 | 5874 | |
c2d11a7d JM |
5875 | /* enable/disable the MIPS FPU */ |
5876 | if (!mips_fpu_type_auto) | |
5877 | tdep->mips_fpu_type = mips_fpu_type; | |
5878 | else if (info.bfd_arch_info != NULL | |
5879 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5880 | switch (info.bfd_arch_info->mach) | |
5881 | { | |
b0069a17 | 5882 | case bfd_mach_mips3900: |
c2d11a7d | 5883 | case bfd_mach_mips4100: |
ed9a39eb | 5884 | case bfd_mach_mips4111: |
c2d11a7d JM |
5885 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5886 | break; | |
bf64bfd6 AC |
5887 | case bfd_mach_mips4650: |
5888 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5889 | break; | |
c2d11a7d JM |
5890 | default: |
5891 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5892 | break; | |
5893 | } | |
5894 | else | |
5895 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5896 | ||
5897 | /* MIPS version of register names. NOTE: At present the MIPS | |
5898 | register name management is part way between the old - | |
5899 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
102182a9 | 5900 | Further work on it is required. */ |
18f81521 MS |
5901 | /* NOTE: many targets (esp. embedded) do not go thru the |
5902 | gdbarch_register_name vector at all, instead bypassing it | |
5903 | by defining REGISTER_NAMES. */ | |
c2d11a7d | 5904 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6c997a34 | 5905 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 5906 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 5907 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 5908 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
6c0e89ed | 5909 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, generic_target_write_sp); |
c2d11a7d | 5910 | |
102182a9 MS |
5911 | /* Add/remove bits from an address. The MIPS needs be careful to |
5912 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5913 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5914 | ||
10312cc4 | 5915 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
5916 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
5917 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
a5afb99f | 5918 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 5919 | |
102182a9 | 5920 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5921 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
5922 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
5923 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5924 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
88c72b7d | 5925 | |
c2d11a7d | 5926 | /* Initialize a frame */ |
e0f7ec59 | 5927 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 5928 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
5929 | |
5930 | /* MIPS version of CALL_DUMMY */ | |
5931 | ||
c2d11a7d | 5932 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); |
749b82f6 | 5933 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 5934 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
cedea778 | 5935 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
bf1f5b4c | 5936 | set_gdbarch_register_convertible (gdbarch, mips_register_convertible); |
d05285fa MS |
5937 | set_gdbarch_register_convert_to_virtual (gdbarch, |
5938 | mips_register_convert_to_virtual); | |
5939 | set_gdbarch_register_convert_to_raw (gdbarch, | |
5940 | mips_register_convert_to_raw); | |
5941 | ||
618ce49f | 5942 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
5943 | set_gdbarch_frameless_function_invocation (gdbarch, |
5944 | generic_frameless_function_invocation_not); | |
8bedc050 | 5945 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
5946 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
5947 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
5948 | ||
129c1cd6 | 5949 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 5950 | |
f7b9e9fc AC |
5951 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5952 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
5953 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
5954 | |
5955 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 5956 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 5957 | |
fc0c74b1 AC |
5958 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5959 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5960 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5961 | |
102182a9 MS |
5962 | set_gdbarch_function_start_offset (gdbarch, 0); |
5963 | ||
32a6503c KB |
5964 | /* There are MIPS targets which do not yet use this since they still |
5965 | define REGISTER_VIRTUAL_TYPE. */ | |
78fde5f8 KB |
5966 | set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type); |
5967 | ||
e11c53d2 | 5968 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 5969 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 5970 | |
70f80edf | 5971 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 5972 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 5973 | |
2f1488ce MS |
5974 | set_gdbarch_extract_struct_value_address (gdbarch, |
5975 | mips_extract_struct_value_address); | |
757a7cc6 MS |
5976 | |
5977 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
5978 | ||
5979 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 5980 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 5981 | |
4b9b3959 AC |
5982 | return gdbarch; |
5983 | } | |
5984 | ||
2e4ebe70 DJ |
5985 | static void |
5986 | mips_abi_update (char *ignore_args, int from_tty, | |
5987 | struct cmd_list_element *c) | |
5988 | { | |
5989 | struct gdbarch_info info; | |
5990 | ||
5991 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5992 | mips_gdbarch_init will take care of the rest. */ | |
5993 | gdbarch_info_init (&info); | |
5994 | gdbarch_update_p (info); | |
5995 | } | |
5996 | ||
ad188201 KB |
5997 | /* Print out which MIPS ABI is in use. */ |
5998 | ||
5999 | static void | |
6000 | show_mips_abi (char *ignore_args, int from_tty) | |
6001 | { | |
6002 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6003 | printf_filtered ( | |
6004 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6005 | else | |
6006 | { | |
6007 | enum mips_abi global_abi = global_mips_abi (); | |
6008 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6009 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6010 | ||
6011 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6012 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6013 | actual_abi_str); | |
6014 | else if (global_abi == actual_abi) | |
6015 | printf_filtered ( | |
6016 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6017 | actual_abi_str); | |
6018 | else | |
6019 | { | |
6020 | /* Probably shouldn't happen... */ | |
6021 | printf_filtered ( | |
6022 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6023 | actual_abi_str, | |
6024 | mips_abi_strings[global_abi]); | |
6025 | } | |
6026 | } | |
6027 | } | |
6028 | ||
4b9b3959 AC |
6029 | static void |
6030 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6031 | { | |
6032 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6033 | if (tdep != NULL) | |
c2d11a7d | 6034 | { |
acdb74a0 AC |
6035 | int ef_mips_arch; |
6036 | int ef_mips_32bitmode; | |
6037 | /* determine the ISA */ | |
6038 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6039 | { | |
6040 | case E_MIPS_ARCH_1: | |
6041 | ef_mips_arch = 1; | |
6042 | break; | |
6043 | case E_MIPS_ARCH_2: | |
6044 | ef_mips_arch = 2; | |
6045 | break; | |
6046 | case E_MIPS_ARCH_3: | |
6047 | ef_mips_arch = 3; | |
6048 | break; | |
6049 | case E_MIPS_ARCH_4: | |
93d56215 | 6050 | ef_mips_arch = 4; |
acdb74a0 AC |
6051 | break; |
6052 | default: | |
93d56215 | 6053 | ef_mips_arch = 0; |
acdb74a0 AC |
6054 | break; |
6055 | } | |
6056 | /* determine the size of a pointer */ | |
6057 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6058 | fprintf_unfiltered (file, |
6059 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6060 | tdep->elf_flags); |
4b9b3959 | 6061 | fprintf_unfiltered (file, |
acdb74a0 AC |
6062 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6063 | ef_mips_32bitmode); | |
6064 | fprintf_unfiltered (file, | |
6065 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6066 | ef_mips_arch); | |
6067 | fprintf_unfiltered (file, | |
6068 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6069 | tdep->mips_abi, | |
2e4ebe70 | 6070 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6071 | fprintf_unfiltered (file, |
6072 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6073 | mips_mask_address_p (), | |
6074 | tdep->default_mask_address_p); | |
c2d11a7d | 6075 | } |
4b9b3959 AC |
6076 | fprintf_unfiltered (file, |
6077 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6078 | FP_REGISTER_DOUBLE); | |
6079 | fprintf_unfiltered (file, | |
6080 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6081 | MIPS_DEFAULT_FPU_TYPE, | |
6082 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6083 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6084 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6085 | : "???")); | |
6086 | fprintf_unfiltered (file, | |
6087 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6088 | MIPS_EABI); | |
6089 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6090 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
6091 | MIPS_LAST_FP_ARG_REGNUM, | |
6092 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
6093 | fprintf_unfiltered (file, |
6094 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6095 | MIPS_FPU_TYPE, | |
6096 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6097 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6098 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6099 | : "???")); | |
6100 | fprintf_unfiltered (file, | |
6101 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6102 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6103 | fprintf_unfiltered (file, |
6104 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6105 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6106 | fprintf_unfiltered (file, |
6107 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6108 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6109 | fprintf_unfiltered (file, | |
6110 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6111 | MIPS_STACK_ARGSIZE); | |
6112 | fprintf_unfiltered (file, | |
6113 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
6114 | MIPS_REGSIZE); | |
2475bac3 AC |
6115 | fprintf_unfiltered (file, |
6116 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6117 | A0_REGNUM); | |
6118 | fprintf_unfiltered (file, | |
6119 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6120 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6121 | fprintf_unfiltered (file, | |
6122 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6123 | XSTRING (ATTACH_DETACH)); | |
6124 | fprintf_unfiltered (file, | |
6125 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
6126 | BADVADDR_REGNUM); | |
2475bac3 AC |
6127 | fprintf_unfiltered (file, |
6128 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
6129 | CAUSE_REGNUM); | |
2475bac3 AC |
6130 | fprintf_unfiltered (file, |
6131 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6132 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6133 | fprintf_unfiltered (file, | |
6134 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6135 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6136 | fprintf_unfiltered (file, |
6137 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
6138 | FCRCS_REGNUM); | |
6139 | fprintf_unfiltered (file, | |
6140 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
6141 | FCRIR_REGNUM); | |
6142 | fprintf_unfiltered (file, | |
6143 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6144 | FIRST_EMBED_REGNUM); | |
6145 | fprintf_unfiltered (file, | |
6146 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
6147 | FPA0_REGNUM); | |
6148 | fprintf_unfiltered (file, | |
6149 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
6150 | GDB_TARGET_IS_MIPS64); | |
2475bac3 AC |
6151 | fprintf_unfiltered (file, |
6152 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
6153 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
6154 | fprintf_unfiltered (file, | |
6155 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
6156 | HI_REGNUM); | |
2475bac3 AC |
6157 | fprintf_unfiltered (file, |
6158 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6159 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6160 | fprintf_unfiltered (file, |
6161 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6162 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6163 | fprintf_unfiltered (file, | |
6164 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6165 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
6166 | fprintf_unfiltered (file, | |
6167 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
6168 | fprintf_unfiltered (file, | |
6169 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6170 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6171 | fprintf_unfiltered (file, |
6172 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
6173 | LO_REGNUM); | |
6174 | #ifdef MACHINE_CPROC_FP_OFFSET | |
6175 | fprintf_unfiltered (file, | |
6176 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6177 | MACHINE_CPROC_FP_OFFSET); | |
6178 | #endif | |
6179 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6180 | fprintf_unfiltered (file, | |
6181 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6182 | MACHINE_CPROC_PC_OFFSET); | |
6183 | #endif | |
6184 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6185 | fprintf_unfiltered (file, | |
6186 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6187 | MACHINE_CPROC_SP_OFFSET); | |
6188 | #endif | |
6189 | fprintf_unfiltered (file, | |
6190 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
2475bac3 AC |
6191 | fprintf_unfiltered (file, |
6192 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6193 | MIPS16_INSTLEN); | |
2475bac3 AC |
6194 | fprintf_unfiltered (file, |
6195 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6196 | fprintf_unfiltered (file, | |
6197 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6198 | fprintf_unfiltered (file, | |
6199 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6200 | MIPS_INSTLEN); | |
6201 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6202 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6203 | MIPS_LAST_ARG_REGNUM, | |
6204 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6205 | fprintf_unfiltered (file, |
6206 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6207 | MIPS_NUMREGS); | |
6208 | fprintf_unfiltered (file, | |
6209 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
6210 | fprintf_unfiltered (file, | |
6211 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6212 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6213 | fprintf_unfiltered (file, |
6214 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
6215 | fprintf_unfiltered (file, | |
6216 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
2475bac3 AC |
6217 | fprintf_unfiltered (file, |
6218 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6219 | PRID_REGNUM); | |
6220 | fprintf_unfiltered (file, | |
6221 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
6222 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
6223 | fprintf_unfiltered (file, | |
6224 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6225 | fprintf_unfiltered (file, | |
6226 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6227 | fprintf_unfiltered (file, | |
6228 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6229 | fprintf_unfiltered (file, | |
6230 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6231 | fprintf_unfiltered (file, | |
6232 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6233 | fprintf_unfiltered (file, | |
6234 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6235 | fprintf_unfiltered (file, | |
6236 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6237 | fprintf_unfiltered (file, | |
6238 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6239 | fprintf_unfiltered (file, | |
6240 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6241 | fprintf_unfiltered (file, | |
6242 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6243 | fprintf_unfiltered (file, | |
6244 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6245 | fprintf_unfiltered (file, | |
6246 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6247 | fprintf_unfiltered (file, | |
6248 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6249 | PS_REGNUM); | |
2475bac3 AC |
6250 | fprintf_unfiltered (file, |
6251 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6252 | RA_REGNUM); | |
6253 | fprintf_unfiltered (file, | |
6254 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
6255 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6256 | fprintf_unfiltered (file, | |
6257 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
6258 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
6259 | fprintf_unfiltered (file, | |
6260 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
6261 | fprintf_unfiltered (file, | |
6262 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
6263 | fprintf_unfiltered (file, | |
6264 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
6265 | #ifdef SAVED_BYTES | |
6266 | fprintf_unfiltered (file, | |
6267 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6268 | SAVED_BYTES); | |
6269 | #endif | |
6270 | #ifdef SAVED_FP | |
6271 | fprintf_unfiltered (file, | |
6272 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6273 | SAVED_FP); | |
6274 | #endif | |
6275 | #ifdef SAVED_PC | |
6276 | fprintf_unfiltered (file, | |
6277 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6278 | SAVED_PC); | |
6279 | #endif | |
6280 | fprintf_unfiltered (file, | |
6281 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6282 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6283 | fprintf_unfiltered (file, | |
6284 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6285 | fprintf_unfiltered (file, | |
6286 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6287 | SIGFRAME_BASE); | |
6288 | fprintf_unfiltered (file, | |
6289 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6290 | SIGFRAME_FPREGSAVE_OFF); | |
6291 | fprintf_unfiltered (file, | |
6292 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6293 | SIGFRAME_PC_OFF); | |
6294 | fprintf_unfiltered (file, | |
6295 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6296 | SIGFRAME_REGSAVE_OFF); | |
6297 | fprintf_unfiltered (file, | |
6298 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
6299 | SIGFRAME_REG_SIZE); | |
6300 | fprintf_unfiltered (file, | |
6301 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6302 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6303 | fprintf_unfiltered (file, | |
6304 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6305 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6306 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6307 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6308 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6309 | fprintf_unfiltered (file, |
6310 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6311 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6312 | #ifdef STACK_END_ADDR | |
6313 | fprintf_unfiltered (file, | |
6314 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6315 | STACK_END_ADDR); | |
6316 | #endif | |
6317 | fprintf_unfiltered (file, | |
6318 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6319 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6320 | fprintf_unfiltered (file, | |
6321 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6322 | STEP_SKIPS_DELAY_P); | |
6323 | fprintf_unfiltered (file, | |
6324 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6325 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6326 | fprintf_unfiltered (file, | |
6327 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6328 | T9_REGNUM); | |
6329 | fprintf_unfiltered (file, | |
6330 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6331 | fprintf_unfiltered (file, | |
6332 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6333 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6334 | fprintf_unfiltered (file, | |
6335 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6336 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
6337 | fprintf_unfiltered (file, | |
6338 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
6341 | XSTRING (TM_PRINT_INSN_MACH)); | |
6342 | #ifdef TRACE_CLEAR | |
6343 | fprintf_unfiltered (file, | |
6344 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6345 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6346 | #endif | |
6347 | #ifdef TRACE_FLAVOR | |
6348 | fprintf_unfiltered (file, | |
6349 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6350 | TRACE_FLAVOR); | |
6351 | #endif | |
6352 | #ifdef TRACE_FLAVOR_SIZE | |
6353 | fprintf_unfiltered (file, | |
6354 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6355 | TRACE_FLAVOR_SIZE); | |
6356 | #endif | |
6357 | #ifdef TRACE_SET | |
6358 | fprintf_unfiltered (file, | |
6359 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6360 | XSTRING (TRACE_SET (X,STATE))); | |
6361 | #endif | |
6362 | fprintf_unfiltered (file, | |
6363 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
6364 | #ifdef UNUSED_REGNUM | |
6365 | fprintf_unfiltered (file, | |
6366 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6367 | UNUSED_REGNUM); | |
6368 | #endif | |
6369 | fprintf_unfiltered (file, | |
6370 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6371 | V0_REGNUM); | |
6372 | fprintf_unfiltered (file, | |
6373 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6374 | (long) VM_MIN_ADDRESS); | |
6375 | #ifdef VX_NUM_REGS | |
6376 | fprintf_unfiltered (file, | |
6377 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
6378 | VX_NUM_REGS); | |
6379 | #endif | |
6380 | fprintf_unfiltered (file, | |
6381 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6382 | ZERO_REGNUM); | |
6383 | fprintf_unfiltered (file, | |
6384 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6385 | _PROC_MAGIC_); | |
c2d11a7d JM |
6386 | } |
6387 | ||
c906108c | 6388 | void |
acdb74a0 | 6389 | _initialize_mips_tdep (void) |
c906108c SS |
6390 | { |
6391 | static struct cmd_list_element *mipsfpulist = NULL; | |
6392 | struct cmd_list_element *c; | |
6393 | ||
2e4ebe70 DJ |
6394 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6395 | if (MIPS_ABI_LAST + 1 | |
6396 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6397 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6398 | ||
4b9b3959 | 6399 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
d7a27068 AC |
6400 | if (!deprecated_tm_print_insn) /* Someone may have already set it */ |
6401 | deprecated_tm_print_insn = gdb_print_insn_mips; | |
c906108c | 6402 | |
a5ea2558 AC |
6403 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6404 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6405 | "Various MIPS specific commands.", | |
6406 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6407 | ||
6408 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6409 | "Various MIPS specific commands.", | |
6410 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6411 | ||
6412 | /* Allow the user to override the saved register size. */ | |
6413 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6414 | class_obscure, |
6415 | size_enums, | |
6416 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6417 | Set size of general purpose registers saved on the stack.\n\ |
6418 | This option can be set to one of:\n\ | |
6419 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6420 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6421 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6422 | saved GP register size from information contained in the executable.\n\ | |
6423 | (default: auto)", | |
1ed2a135 | 6424 | &setmipscmdlist), |
a5ea2558 AC |
6425 | &showmipscmdlist); |
6426 | ||
d929b26f AC |
6427 | /* Allow the user to override the argument stack size. */ |
6428 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6429 | class_obscure, | |
6430 | size_enums, | |
1ed2a135 | 6431 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6432 | Set the amount of stack space reserved for each argument.\n\ |
6433 | This option can be set to one of:\n\ | |
6434 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6435 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6436 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6437 | target and executable (default)", | |
6438 | &setmipscmdlist), | |
6439 | &showmipscmdlist); | |
6440 | ||
2e4ebe70 DJ |
6441 | /* Allow the user to override the ABI. */ |
6442 | c = add_set_enum_cmd | |
6443 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6444 | "Set the ABI used by this program.\n" | |
6445 | "This option can be set to one of:\n" | |
6446 | " auto - the default ABI associated with the current binary\n" | |
6447 | " o32\n" | |
6448 | " o64\n" | |
6449 | " n32\n" | |
f3a7b3a5 | 6450 | " n64\n" |
2e4ebe70 DJ |
6451 | " eabi32\n" |
6452 | " eabi64", | |
6453 | &setmipscmdlist); | |
2e4ebe70 | 6454 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6455 | add_cmd ("abi", class_obscure, show_mips_abi, |
6456 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6457 | |
c906108c SS |
6458 | /* Let the user turn off floating point and set the fence post for |
6459 | heuristic_proc_start. */ | |
6460 | ||
6461 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6462 | "Set use of MIPS floating-point coprocessor.", | |
6463 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6464 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6465 | "Select single-precision MIPS floating-point coprocessor.", | |
6466 | &mipsfpulist); | |
6467 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6468 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6469 | &mipsfpulist); |
6470 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6471 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6472 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6473 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6474 | "Select no MIPS floating-point coprocessor.", | |
6475 | &mipsfpulist); | |
6476 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6477 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6478 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6479 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6480 | "Select MIPS floating-point coprocessor automatically.", | |
6481 | &mipsfpulist); | |
6482 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6483 | "Show current use of MIPS floating-point coprocessor target.", | |
6484 | &showlist); | |
6485 | ||
c906108c SS |
6486 | /* We really would like to have both "0" and "unlimited" work, but |
6487 | command.c doesn't deal with that. So make it a var_zinteger | |
6488 | because the user can always use "999999" or some such for unlimited. */ | |
6489 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6490 | (char *) &heuristic_fence_post, | |
6491 | "\ | |
6492 | Set the distance searched for the start of a function.\n\ | |
6493 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6494 | program for the start of a function. This command sets the distance of the\n\ | |
6495 | search. The only need to set it is when debugging a stripped executable.", | |
6496 | &setlist); | |
6497 | /* We need to throw away the frame cache when we set this, since it | |
6498 | might change our ability to get backtraces. */ | |
9f60d481 | 6499 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6500 | add_show_from_set (c, &showlist); |
6501 | ||
6502 | /* Allow the user to control whether the upper bits of 64-bit | |
6503 | addresses should be zeroed. */ | |
e9e68a56 AC |
6504 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6505 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6506 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6507 | allow GDB to determine the correct value.\n", "\ | |
6508 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6509 | NULL, show_mask_address, | |
6510 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6511 | |
6512 | /* Allow the user to control the size of 32 bit registers within the | |
6513 | raw remote packet. */ | |
6514 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
6515 | class_obscure, | |
6516 | var_boolean, | |
6517 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
6518 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
6519 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6520 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6521 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
6522 | &setlist), | |
6523 | &showlist); | |
9ace0497 AC |
6524 | |
6525 | /* Debug this files internals. */ | |
6526 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6527 | &mips_debug, "Set mips debugging.\n\ | |
6528 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6529 | &showdebuglist); | |
c906108c | 6530 | } |