Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
c906108c | 53 | |
e0f7ec59 | 54 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 55 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 56 | |
dd824b04 DJ |
57 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
58 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
59 | #define ST0_FR (1 << 26) | |
60 | ||
b0069a17 AC |
61 | /* The sizes of floating point registers. */ |
62 | ||
63 | enum | |
64 | { | |
65 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
66 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
67 | }; | |
68 | ||
0dadbba0 | 69 | |
2e4ebe70 DJ |
70 | static const char *mips_abi_string; |
71 | ||
72 | static const char *mips_abi_strings[] = { | |
73 | "auto", | |
74 | "n32", | |
75 | "o32", | |
28d169de | 76 | "n64", |
2e4ebe70 DJ |
77 | "o64", |
78 | "eabi32", | |
79 | "eabi64", | |
80 | NULL | |
81 | }; | |
82 | ||
cce74817 | 83 | struct frame_extra_info |
6d82d43b AC |
84 | { |
85 | mips_extra_func_info_t proc_desc; | |
86 | int num_args; | |
87 | }; | |
cce74817 | 88 | |
d929b26f AC |
89 | /* Various MIPS ISA options (related to stack analysis) can be |
90 | overridden dynamically. Establish an enum/array for managing | |
91 | them. */ | |
92 | ||
53904c9e AC |
93 | static const char size_auto[] = "auto"; |
94 | static const char size_32[] = "32"; | |
95 | static const char size_64[] = "64"; | |
d929b26f | 96 | |
53904c9e | 97 | static const char *size_enums[] = { |
d929b26f AC |
98 | size_auto, |
99 | size_32, | |
100 | size_64, | |
a5ea2558 AC |
101 | 0 |
102 | }; | |
103 | ||
7a292a7a SS |
104 | /* Some MIPS boards don't support floating point while others only |
105 | support single-precision floating-point operations. See also | |
106 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
107 | |
108 | enum mips_fpu_type | |
6d82d43b AC |
109 | { |
110 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
111 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
112 | MIPS_FPU_NONE /* No floating point. */ | |
113 | }; | |
c906108c SS |
114 | |
115 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
116 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
117 | #endif | |
118 | static int mips_fpu_type_auto = 1; | |
119 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 120 | |
9ace0497 | 121 | static int mips_debug = 0; |
7a292a7a | 122 | |
c2d11a7d JM |
123 | /* MIPS specific per-architecture information */ |
124 | struct gdbarch_tdep | |
6d82d43b AC |
125 | { |
126 | /* from the elf header */ | |
127 | int elf_flags; | |
128 | ||
129 | /* mips options */ | |
130 | enum mips_abi mips_abi; | |
131 | enum mips_abi found_abi; | |
132 | enum mips_fpu_type mips_fpu_type; | |
133 | int mips_last_arg_regnum; | |
134 | int mips_last_fp_arg_regnum; | |
135 | int mips_default_saved_regsize; | |
136 | int mips_fp_register_double; | |
137 | int mips_default_stack_argsize; | |
138 | int default_mask_address_p; | |
139 | /* Is the target using 64-bit raw integer registers but only | |
140 | storing a left-aligned 32-bit value in each? */ | |
141 | int mips64_transfers_32bit_regs_p; | |
142 | /* Indexes for various registers. IRIX and embedded have | |
143 | different values. This contains the "public" fields. Don't | |
144 | add any that do not need to be public. */ | |
145 | const struct mips_regnum *regnum; | |
146 | /* Register names table for the current register set. */ | |
147 | const char **mips_processor_reg_names; | |
148 | }; | |
c2d11a7d | 149 | |
56cea623 AC |
150 | const struct mips_regnum * |
151 | mips_regnum (struct gdbarch *gdbarch) | |
152 | { | |
153 | return gdbarch_tdep (gdbarch)->regnum; | |
154 | } | |
155 | ||
156 | static int | |
157 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
158 | { | |
159 | return mips_regnum (gdbarch)->fp0 + 12; | |
160 | } | |
161 | ||
0dadbba0 | 162 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 163 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 164 | |
c2d11a7d | 165 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 166 | |
c2d11a7d | 167 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 168 | |
c2d11a7d | 169 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 170 | |
95404a3e AC |
171 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
172 | functions to test, set, or clear bit 0 of addresses. */ | |
173 | ||
174 | static CORE_ADDR | |
175 | is_mips16_addr (CORE_ADDR addr) | |
176 | { | |
177 | return ((addr) & 1); | |
178 | } | |
179 | ||
180 | static CORE_ADDR | |
181 | make_mips16_addr (CORE_ADDR addr) | |
182 | { | |
183 | return ((addr) | 1); | |
184 | } | |
185 | ||
186 | static CORE_ADDR | |
187 | unmake_mips16_addr (CORE_ADDR addr) | |
188 | { | |
189 | return ((addr) & ~1); | |
190 | } | |
191 | ||
22540ece AC |
192 | /* Return the contents of register REGNUM as a signed integer. */ |
193 | ||
194 | static LONGEST | |
195 | read_signed_register (int regnum) | |
196 | { | |
719ec221 | 197 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 198 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
199 | return (extract_signed_integer |
200 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
201 | } |
202 | ||
203 | static LONGEST | |
204 | read_signed_register_pid (int regnum, ptid_t ptid) | |
205 | { | |
206 | ptid_t save_ptid; | |
207 | LONGEST retval; | |
208 | ||
209 | if (ptid_equal (ptid, inferior_ptid)) | |
210 | return read_signed_register (regnum); | |
211 | ||
212 | save_ptid = inferior_ptid; | |
213 | ||
214 | inferior_ptid = ptid; | |
215 | ||
216 | retval = read_signed_register (regnum); | |
217 | ||
218 | inferior_ptid = save_ptid; | |
219 | ||
220 | return retval; | |
221 | } | |
222 | ||
d1973055 KB |
223 | /* Return the MIPS ABI associated with GDBARCH. */ |
224 | enum mips_abi | |
225 | mips_abi (struct gdbarch *gdbarch) | |
226 | { | |
227 | return gdbarch_tdep (gdbarch)->mips_abi; | |
228 | } | |
229 | ||
4246e332 AC |
230 | int |
231 | mips_regsize (struct gdbarch *gdbarch) | |
232 | { | |
233 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
234 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
235 | } | |
236 | ||
480d3dd2 AC |
237 | /* Return the currently configured (or set) saved register size. */ |
238 | ||
239 | static const char *mips_saved_regsize_string = size_auto; | |
240 | ||
d929b26f | 241 | static unsigned int |
480d3dd2 | 242 | mips_saved_regsize (struct gdbarch_tdep *tdep) |
d929b26f AC |
243 | { |
244 | if (mips_saved_regsize_string == size_auto) | |
480d3dd2 | 245 | return tdep->mips_default_saved_regsize; |
d929b26f AC |
246 | else if (mips_saved_regsize_string == size_64) |
247 | return 8; | |
6d82d43b | 248 | else /* if (mips_saved_regsize_string == size_32) */ |
d929b26f AC |
249 | return 4; |
250 | } | |
251 | ||
71b8ef93 | 252 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 253 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 254 | "info" field is used for this purpose. |
5a89d8aa MS |
255 | |
256 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
257 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
258 | minimal symbol to mark it as a 16-bit function | |
259 | ||
f594e5e9 | 260 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 261 | |
5a89d8aa | 262 | static void |
6d82d43b AC |
263 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
264 | { | |
265 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
266 | { | |
267 | MSYMBOL_INFO (msym) = (char *) | |
268 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
269 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
270 | } | |
5a89d8aa MS |
271 | } |
272 | ||
71b8ef93 MS |
273 | static int |
274 | msymbol_is_special (struct minimal_symbol *msym) | |
275 | { | |
276 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
277 | } | |
278 | ||
88658117 AC |
279 | /* XFER a value from the big/little/left end of the register. |
280 | Depending on the size of the value it might occupy the entire | |
281 | register or just part of it. Make an allowance for this, aligning | |
282 | things accordingly. */ | |
283 | ||
284 | static void | |
285 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
286 | enum bfd_endian endian, bfd_byte * in, |
287 | const bfd_byte * out, int buf_offset) | |
88658117 | 288 | { |
d9d9c31f | 289 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 290 | int reg_offset = 0; |
a4b8ebc8 | 291 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
292 | /* Need to transfer the left or right part of the register, based on |
293 | the targets byte order. */ | |
88658117 AC |
294 | switch (endian) |
295 | { | |
296 | case BFD_ENDIAN_BIG: | |
719ec221 | 297 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
298 | break; |
299 | case BFD_ENDIAN_LITTLE: | |
300 | reg_offset = 0; | |
301 | break; | |
6d82d43b | 302 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
303 | reg_offset = 0; |
304 | break; | |
305 | default: | |
306 | internal_error (__FILE__, __LINE__, "bad switch"); | |
307 | } | |
308 | if (mips_debug) | |
cb1d2653 AC |
309 | fprintf_unfiltered (gdb_stderr, |
310 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
311 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
312 | if (mips_debug && out != NULL) |
313 | { | |
314 | int i; | |
cb1d2653 | 315 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 316 | for (i = 0; i < length; i++) |
cb1d2653 | 317 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
318 | } |
319 | if (in != NULL) | |
6d82d43b AC |
320 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
321 | in + buf_offset); | |
88658117 | 322 | if (out != NULL) |
6d82d43b AC |
323 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
324 | out + buf_offset); | |
88658117 AC |
325 | if (mips_debug && in != NULL) |
326 | { | |
327 | int i; | |
cb1d2653 | 328 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 329 | for (i = 0; i < length; i++) |
cb1d2653 | 330 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
331 | } |
332 | if (mips_debug) | |
333 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
334 | } | |
335 | ||
dd824b04 DJ |
336 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
337 | compatiblity mode. A return value of 1 means that we have | |
338 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
339 | ||
340 | static int | |
341 | mips2_fp_compat (void) | |
342 | { | |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
344 | meaningful. */ | |
6d82d43b AC |
345 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
346 | 4) | |
dd824b04 DJ |
347 | return 0; |
348 | ||
349 | #if 0 | |
350 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
351 | in all the places we deal with FP registers. PR gdb/413. */ | |
352 | /* Otherwise check the FR bit in the status register - it controls | |
353 | the FP compatiblity mode. If it is clear we are in compatibility | |
354 | mode. */ | |
355 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
356 | return 1; | |
357 | #endif | |
361d1df0 | 358 | |
dd824b04 DJ |
359 | return 0; |
360 | } | |
361 | ||
c2d11a7d JM |
362 | /* Indicate that the ABI makes use of double-precision registers |
363 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 364 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 365 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 366 | |
d929b26f AC |
367 | /* The amount of space reserved on the stack for registers. This is |
368 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
369 | data allocated after the registers have run out. */ | |
370 | ||
53904c9e | 371 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
372 | |
373 | static unsigned int | |
480d3dd2 | 374 | mips_stack_argsize (struct gdbarch_tdep *tdep) |
d929b26f AC |
375 | { |
376 | if (mips_stack_argsize_string == size_auto) | |
480d3dd2 | 377 | return tdep->mips_default_stack_argsize; |
d929b26f AC |
378 | else if (mips_stack_argsize_string == size_64) |
379 | return 8; | |
6d82d43b | 380 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
381 | return 4; |
382 | } | |
383 | ||
7a292a7a | 384 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 385 | |
570b8f7c AC |
386 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
387 | struct frame_info *, int); | |
c906108c | 388 | |
a14ed312 | 389 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 390 | |
a14ed312 | 391 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 392 | |
a14ed312 | 393 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 394 | |
570b8f7c AC |
395 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
396 | struct frame_info *next_frame, | |
397 | int cur_frame); | |
c906108c | 398 | |
a14ed312 KB |
399 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
400 | mips_extra_func_info_t proc_desc); | |
c906108c | 401 | |
67b2c998 DJ |
402 | static struct type *mips_float_register_type (void); |
403 | static struct type *mips_double_register_type (void); | |
404 | ||
acdb74a0 AC |
405 | /* The list of available "set mips " and "show mips " commands */ |
406 | ||
407 | static struct cmd_list_element *setmipscmdlist = NULL; | |
408 | static struct cmd_list_element *showmipscmdlist = NULL; | |
409 | ||
5e2e9765 KB |
410 | /* Integer registers 0 thru 31 are handled explicitly by |
411 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
412 | are listed in the followign tables. */ |
413 | ||
6d82d43b AC |
414 | enum |
415 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
416 | |
417 | /* Generic MIPS. */ | |
418 | ||
419 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
420 | "sr", "lo", "hi", "bad", "cause", "pc", |
421 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
422 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
423 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
424 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
425 | "fsr", "fir", "" /*"fp" */ , "", | |
426 | "", "", "", "", "", "", "", "", | |
427 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
428 | }; |
429 | ||
430 | /* Names of IDT R3041 registers. */ | |
431 | ||
432 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
433 | "sr", "lo", "hi", "bad", "cause", "pc", |
434 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
435 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
436 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
437 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
438 | "fsr", "fir", "", /*"fp" */ "", | |
439 | "", "", "bus", "ccfg", "", "", "", "", | |
440 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
441 | }; |
442 | ||
443 | /* Names of tx39 registers. */ | |
444 | ||
445 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
446 | "sr", "lo", "hi", "bad", "cause", "pc", |
447 | "", "", "", "", "", "", "", "", | |
448 | "", "", "", "", "", "", "", "", | |
449 | "", "", "", "", "", "", "", "", | |
450 | "", "", "", "", "", "", "", "", | |
451 | "", "", "", "", | |
452 | "", "", "", "", "", "", "", "", | |
453 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
454 | }; |
455 | ||
456 | /* Names of IRIX registers. */ | |
457 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
458 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
459 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
460 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
461 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
462 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
463 | }; |
464 | ||
cce74817 | 465 | |
5e2e9765 | 466 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 467 | static const char * |
5e2e9765 | 468 | mips_register_name (int regno) |
cce74817 | 469 | { |
691c0433 | 470 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
471 | /* GPR names for all ABIs other than n32/n64. */ |
472 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
473 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
474 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
475 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
476 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
477 | }; |
478 | ||
479 | /* GPR names for n32 and n64 ABIs. */ | |
480 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
481 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
482 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
483 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
484 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
485 | }; |
486 | ||
487 | enum mips_abi abi = mips_abi (current_gdbarch); | |
488 | ||
a4b8ebc8 AC |
489 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
490 | don't make the raw register names visible. */ | |
491 | int rawnum = regno % NUM_REGS; | |
492 | if (regno < NUM_REGS) | |
493 | return ""; | |
494 | ||
5e2e9765 KB |
495 | /* The MIPS integer registers are always mapped from 0 to 31. The |
496 | names of the registers (which reflects the conventions regarding | |
497 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 498 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
499 | { |
500 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 501 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 502 | else |
a4b8ebc8 | 503 | return mips_gpr_names[rawnum]; |
5e2e9765 | 504 | } |
a4b8ebc8 | 505 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
506 | { |
507 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
508 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
509 | } | |
5e2e9765 KB |
510 | else |
511 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 512 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 513 | } |
5e2e9765 | 514 | |
a4b8ebc8 | 515 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 516 | |
a4b8ebc8 AC |
517 | static int |
518 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
519 | struct reggroup *reggroup) | |
520 | { | |
521 | int vector_p; | |
522 | int float_p; | |
523 | int raw_p; | |
524 | int rawnum = regnum % NUM_REGS; | |
525 | int pseudo = regnum / NUM_REGS; | |
526 | if (reggroup == all_reggroup) | |
527 | return pseudo; | |
528 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
529 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
530 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
531 | (gdbarch), as not all architectures are multi-arch. */ | |
532 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 533 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
534 | return 0; |
535 | if (reggroup == float_reggroup) | |
536 | return float_p && pseudo; | |
537 | if (reggroup == vector_reggroup) | |
538 | return vector_p && pseudo; | |
539 | if (reggroup == general_reggroup) | |
540 | return (!vector_p && !float_p) && pseudo; | |
541 | /* Save the pseudo registers. Need to make certain that any code | |
542 | extracting register values from a saved register cache also uses | |
543 | pseudo registers. */ | |
544 | if (reggroup == save_reggroup) | |
545 | return raw_p && pseudo; | |
546 | /* Restore the same pseudo register. */ | |
547 | if (reggroup == restore_reggroup) | |
548 | return raw_p && pseudo; | |
6d82d43b | 549 | return 0; |
a4b8ebc8 AC |
550 | } |
551 | ||
552 | /* Map the symbol table registers which live in the range [1 * | |
553 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 554 | registers. Take care of alignment and size problems. */ |
c5aa993b | 555 | |
a4b8ebc8 AC |
556 | static void |
557 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
558 | int cookednum, void *buf) | |
559 | { | |
47ebcfbe | 560 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 561 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 562 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 563 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
564 | else if (register_size (gdbarch, rawnum) > |
565 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
566 | { |
567 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
568 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
569 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
570 | else | |
571 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
572 | } | |
573 | else | |
574 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
575 | } |
576 | ||
577 | static void | |
6d82d43b AC |
578 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
579 | struct regcache *regcache, int cookednum, | |
580 | const void *buf) | |
a4b8ebc8 | 581 | { |
47ebcfbe | 582 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 583 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 584 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 585 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
586 | else if (register_size (gdbarch, rawnum) > |
587 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
588 | { |
589 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
590 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
591 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
592 | else | |
593 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
594 | } | |
595 | else | |
596 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 597 | } |
c5aa993b | 598 | |
c906108c | 599 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 600 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
601 | |
602 | /* Heuristic_proc_start may hunt through the text section for a long | |
603 | time across a 2400 baud serial line. Allows the user to limit this | |
604 | search. */ | |
605 | ||
606 | static unsigned int heuristic_fence_post = 0; | |
607 | ||
c5aa993b JM |
608 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
609 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
610 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
611 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
612 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
613 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
614 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
615 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
616 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
617 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
618 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
619 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
620 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
621 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
622 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
623 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
624 | ||
625 | struct linked_proc_info | |
6d82d43b AC |
626 | { |
627 | struct mips_extra_func_info info; | |
628 | struct linked_proc_info *next; | |
629 | } | |
c5aa993b | 630 | *linked_proc_desc_table = NULL; |
c906108c | 631 | |
46cd78fb | 632 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
633 | register N. NOTE: This defines the pseudo register type so need to |
634 | rebuild the architecture vector. */ | |
43e526b9 JM |
635 | |
636 | static int mips64_transfers_32bit_regs_p = 0; | |
637 | ||
719ec221 AC |
638 | static void |
639 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
640 | struct cmd_list_element *c) | |
43e526b9 | 641 | { |
719ec221 AC |
642 | struct gdbarch_info info; |
643 | gdbarch_info_init (&info); | |
644 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
645 | instead of relying on globals. Doing that would let generic code | |
646 | handle the search for this specific architecture. */ | |
647 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 648 | { |
719ec221 AC |
649 | mips64_transfers_32bit_regs_p = 0; |
650 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 651 | } |
a4b8ebc8 AC |
652 | } |
653 | ||
47ebcfbe | 654 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 655 | |
ff2e87ac AC |
656 | static int |
657 | mips_convert_register_p (int regnum, struct type *type) | |
658 | { | |
659 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 660 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
661 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
662 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 663 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
664 | } |
665 | ||
42c466d7 | 666 | static void |
ff2e87ac AC |
667 | mips_register_to_value (struct frame_info *frame, int regnum, |
668 | struct type *type, void *to) | |
102182a9 | 669 | { |
7f5f525d AC |
670 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
671 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
672 | } |
673 | ||
42c466d7 | 674 | static void |
ff2e87ac AC |
675 | mips_value_to_register (struct frame_info *frame, int regnum, |
676 | struct type *type, const void *from) | |
102182a9 | 677 | { |
ff2e87ac AC |
678 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
679 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
680 | } |
681 | ||
a4b8ebc8 AC |
682 | /* Return the GDB type object for the "standard" data type of data in |
683 | register REG. */ | |
78fde5f8 KB |
684 | |
685 | static struct type * | |
a4b8ebc8 AC |
686 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
687 | { | |
5ef80fb0 | 688 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
689 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
690 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 691 | { |
5ef80fb0 AC |
692 | /* The floating-point registers raw, or cooked, always match |
693 | mips_regsize(), and also map 1:1, byte for byte. */ | |
694 | switch (gdbarch_byte_order (gdbarch)) | |
695 | { | |
696 | case BFD_ENDIAN_BIG: | |
697 | if (mips_regsize (gdbarch) == 4) | |
698 | return builtin_type_ieee_single_big; | |
699 | else | |
700 | return builtin_type_ieee_double_big; | |
701 | case BFD_ENDIAN_LITTLE: | |
702 | if (mips_regsize (gdbarch) == 4) | |
703 | return builtin_type_ieee_single_little; | |
704 | else | |
705 | return builtin_type_ieee_double_little; | |
706 | case BFD_ENDIAN_UNKNOWN: | |
707 | default: | |
708 | internal_error (__FILE__, __LINE__, "bad switch"); | |
709 | } | |
a6425924 | 710 | } |
6d82d43b AC |
711 | else if (regnum >= |
712 | (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) | |
5ef80fb0 AC |
713 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
714 | /* The pseudo/cooked view of the embedded registers is always | |
715 | 32-bit. The raw view is handled below. */ | |
716 | return builtin_type_int32; | |
719ec221 AC |
717 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
718 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
719 | /* The target, while using a 64-bit register buffer, is only | |
720 | transfering 32-bits of each integer register. Reflect this in | |
721 | the cooked/pseudo register value. */ | |
722 | return builtin_type_int32; | |
5ef80fb0 AC |
723 | else if (mips_regsize (gdbarch) == 8) |
724 | /* 64-bit ISA. */ | |
725 | return builtin_type_int64; | |
78fde5f8 | 726 | else |
5ef80fb0 AC |
727 | /* 32-bit ISA. */ |
728 | return builtin_type_int32; | |
78fde5f8 KB |
729 | } |
730 | ||
bcb0cc15 MS |
731 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
732 | ||
733 | static CORE_ADDR | |
734 | mips_read_sp (void) | |
735 | { | |
e227b13c | 736 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
737 | } |
738 | ||
c906108c | 739 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 740 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
741 | |
742 | static int | |
480d3dd2 | 743 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
744 | { |
745 | switch (mask_address_var) | |
746 | { | |
7f19b9a2 | 747 | case AUTO_BOOLEAN_TRUE: |
4014092b | 748 | return 1; |
7f19b9a2 | 749 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
750 | return 0; |
751 | break; | |
7f19b9a2 | 752 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 753 | return tdep->default_mask_address_p; |
4014092b | 754 | default: |
6d82d43b | 755 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 756 | return -1; |
361d1df0 | 757 | } |
4014092b AC |
758 | } |
759 | ||
760 | static void | |
e9e68a56 | 761 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 762 | { |
480d3dd2 | 763 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
764 | switch (mask_address_var) |
765 | { | |
7f19b9a2 | 766 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
767 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
768 | break; | |
7f19b9a2 | 769 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
770 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
771 | break; | |
7f19b9a2 | 772 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
773 | printf_filtered |
774 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
775 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
776 | break; |
777 | default: | |
6d82d43b | 778 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 779 | break; |
361d1df0 | 780 | } |
4014092b | 781 | } |
c906108c | 782 | |
c906108c SS |
783 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
784 | ||
785 | static int | |
786 | pc_is_mips16 (bfd_vma memaddr) | |
787 | { | |
788 | struct minimal_symbol *sym; | |
789 | ||
790 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 791 | if (is_mips16_addr (memaddr)) |
c906108c SS |
792 | return 1; |
793 | ||
794 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
795 | the high bit of the info field. Use this to decide if the function is | |
796 | MIPS16 or normal MIPS. */ | |
797 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
798 | if (sym) | |
71b8ef93 | 799 | return msymbol_is_special (sym); |
c906108c SS |
800 | else |
801 | return 0; | |
802 | } | |
803 | ||
6c997a34 AC |
804 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
805 | all registers should be sign extended for simplicity? */ | |
806 | ||
807 | static CORE_ADDR | |
39f77062 | 808 | mips_read_pc (ptid_t ptid) |
6c997a34 | 809 | { |
b6cb9035 AC |
810 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
811 | } | |
812 | ||
58dfe9ff AC |
813 | static CORE_ADDR |
814 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
815 | { | |
816 | return frame_unwind_register_signed (next_frame, mips_regnum (gdbarch)->pc); | |
817 | } | |
818 | ||
b6cb9035 AC |
819 | static void |
820 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
821 | { | |
822 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 823 | } |
c906108c SS |
824 | |
825 | /* This returns the PC of the first inst after the prologue. If we can't | |
826 | find the prologue, then return 0. */ | |
827 | ||
828 | static CORE_ADDR | |
6d82d43b | 829 | after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc) |
c906108c SS |
830 | { |
831 | struct symtab_and_line sal; | |
832 | CORE_ADDR func_addr, func_end; | |
833 | ||
479412cd DJ |
834 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
835 | to read the stack pointer from the current machine state, because | |
836 | the current machine state has nothing to do with the information | |
837 | we need from the proc_desc; and the process may or may not exist | |
838 | right now. */ | |
c906108c | 839 | if (!proc_desc) |
479412cd | 840 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
841 | |
842 | if (proc_desc) | |
843 | { | |
844 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 845 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
846 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
847 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
848 | return 0; | |
849 | } | |
850 | ||
851 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
852 | return 0; /* Unknown */ | |
853 | ||
854 | sal = find_pc_line (func_addr, 0); | |
855 | ||
856 | if (sal.end < func_end) | |
857 | return sal.end; | |
858 | ||
859 | /* The line after the prologue is after the end of the function. In this | |
860 | case, tell the caller to find the prologue the hard way. */ | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
865 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
866 | set the appropriate bit in the general register mask or float register mask | |
867 | to indicate which register is saved. This is a helper function | |
868 | for mips_find_saved_regs. */ | |
869 | ||
870 | static void | |
acdb74a0 AC |
871 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
872 | unsigned long *float_mask) | |
c906108c SS |
873 | { |
874 | int reg; | |
875 | ||
6d82d43b | 876 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
c906108c SS |
877 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
878 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
879 | { | |
880 | /* It might be possible to use the instruction to | |
c5aa993b JM |
881 | find the offset, rather than the code below which |
882 | is based on things being in a certain order in the | |
883 | frame, but figuring out what the instruction's offset | |
884 | is relative to might be a little tricky. */ | |
c906108c SS |
885 | reg = (inst & 0x001f0000) >> 16; |
886 | *gen_mask |= (1 << reg); | |
887 | } | |
888 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
6d82d43b | 889 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
c5aa993b | 890 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
c906108c SS |
891 | |
892 | { | |
893 | reg = ((inst & 0x001f0000) >> 16); | |
894 | *float_mask |= (1 << reg); | |
895 | } | |
896 | } | |
897 | ||
898 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
899 | set the appropriate bit in the general register or float register mask | |
900 | to indicate which register is saved. This is a helper function | |
901 | for mips_find_saved_regs. */ | |
902 | ||
903 | static void | |
acdb74a0 | 904 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 905 | { |
c5aa993b | 906 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
907 | { |
908 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
909 | *gen_mask |= (1 << reg); | |
910 | } | |
c5aa993b | 911 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
912 | { |
913 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
914 | *gen_mask |= (1 << reg); | |
915 | } | |
c5aa993b | 916 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
917 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
918 | *gen_mask |= (1 << RA_REGNUM); | |
919 | } | |
920 | ||
921 | ||
922 | /* Fetch and return instruction from the specified location. If the PC | |
923 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
924 | ||
925 | static t_inst | |
acdb74a0 | 926 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
927 | { |
928 | char buf[MIPS_INSTLEN]; | |
929 | int instlen; | |
930 | int status; | |
931 | ||
932 | if (pc_is_mips16 (addr)) | |
933 | { | |
934 | instlen = MIPS16_INSTLEN; | |
95404a3e | 935 | addr = unmake_mips16_addr (addr); |
c906108c SS |
936 | } |
937 | else | |
c5aa993b | 938 | instlen = MIPS_INSTLEN; |
c906108c SS |
939 | status = read_memory_nobpt (addr, buf, instlen); |
940 | if (status) | |
941 | memory_error (status, addr); | |
942 | return extract_unsigned_integer (buf, instlen); | |
943 | } | |
944 | ||
945 | ||
946 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
947 | #define mips32_op(x) (x >> 26) |
948 | #define itype_op(x) (x >> 26) | |
949 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 950 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 951 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 952 | |
e135b889 DJ |
953 | #define jtype_op(x) (x >> 26) |
954 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 955 | |
e135b889 DJ |
956 | #define rtype_op(x) (x >> 26) |
957 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
958 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
959 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
960 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
961 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
962 | |
963 | static CORE_ADDR | |
c5aa993b JM |
964 | mips32_relative_offset (unsigned long inst) |
965 | { | |
966 | long x; | |
967 | x = itype_immediate (inst); | |
968 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 969 | { |
c5aa993b | 970 | x |= 0xffff0000; /* sign extension */ |
c906108c | 971 | } |
c5aa993b JM |
972 | x = x << 2; |
973 | return x; | |
c906108c SS |
974 | } |
975 | ||
976 | /* Determine whate to set a single step breakpoint while considering | |
977 | branch prediction */ | |
5a89d8aa | 978 | static CORE_ADDR |
c5aa993b JM |
979 | mips32_next_pc (CORE_ADDR pc) |
980 | { | |
981 | unsigned long inst; | |
982 | int op; | |
983 | inst = mips_fetch_instruction (pc); | |
e135b889 | 984 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 985 | { |
e135b889 | 986 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 987 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 988 | { |
e135b889 | 989 | op = (itype_op (inst) & 0x03); |
c906108c SS |
990 | switch (op) |
991 | { | |
e135b889 DJ |
992 | case 0: /* BEQL */ |
993 | goto equal_branch; | |
994 | case 1: /* BNEL */ | |
995 | goto neq_branch; | |
996 | case 2: /* BLEZL */ | |
997 | goto less_branch; | |
998 | case 3: /* BGTZ */ | |
999 | goto greater_branch; | |
c5aa993b JM |
1000 | default: |
1001 | pc += 4; | |
c906108c SS |
1002 | } |
1003 | } | |
e135b889 | 1004 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1005 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1006 | { |
1007 | int tf = itype_rt (inst) & 0x01; | |
1008 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1009 | int fcrcs = |
1010 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1011 | fp_control_status); | |
e135b889 DJ |
1012 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1013 | ||
1014 | if (((cond >> cnum) & 0x01) == tf) | |
1015 | pc += mips32_relative_offset (inst) + 4; | |
1016 | else | |
1017 | pc += 8; | |
1018 | } | |
c5aa993b JM |
1019 | else |
1020 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1021 | } |
1022 | else | |
c5aa993b JM |
1023 | { /* This gets way messy */ |
1024 | ||
c906108c | 1025 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1026 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1027 | { |
c5aa993b JM |
1028 | case 0: /* SPECIAL */ |
1029 | op = rtype_funct (inst); | |
1030 | switch (op) | |
1031 | { | |
1032 | case 8: /* JR */ | |
1033 | case 9: /* JALR */ | |
6c997a34 AC |
1034 | /* Set PC to that address */ |
1035 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1036 | break; |
1037 | default: | |
1038 | pc += 4; | |
1039 | } | |
1040 | ||
6d82d43b | 1041 | break; /* end SPECIAL */ |
c5aa993b | 1042 | case 1: /* REGIMM */ |
c906108c | 1043 | { |
e135b889 DJ |
1044 | op = itype_rt (inst); /* branch condition */ |
1045 | switch (op) | |
c906108c | 1046 | { |
c5aa993b | 1047 | case 0: /* BLTZ */ |
e135b889 DJ |
1048 | case 2: /* BLTZL */ |
1049 | case 16: /* BLTZAL */ | |
c5aa993b | 1050 | case 18: /* BLTZALL */ |
c906108c | 1051 | less_branch: |
6c997a34 | 1052 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1053 | pc += mips32_relative_offset (inst) + 4; |
1054 | else | |
1055 | pc += 8; /* after the delay slot */ | |
1056 | break; | |
e135b889 | 1057 | case 1: /* BGEZ */ |
c5aa993b JM |
1058 | case 3: /* BGEZL */ |
1059 | case 17: /* BGEZAL */ | |
1060 | case 19: /* BGEZALL */ | |
6c997a34 | 1061 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1062 | pc += mips32_relative_offset (inst) + 4; |
1063 | else | |
1064 | pc += 8; /* after the delay slot */ | |
1065 | break; | |
e135b889 | 1066 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1067 | default: |
1068 | pc += 4; | |
c906108c SS |
1069 | } |
1070 | } | |
6d82d43b | 1071 | break; /* end REGIMM */ |
c5aa993b JM |
1072 | case 2: /* J */ |
1073 | case 3: /* JAL */ | |
1074 | { | |
1075 | unsigned long reg; | |
1076 | reg = jtype_target (inst) << 2; | |
e135b889 | 1077 | /* Upper four bits get never changed... */ |
c5aa993b | 1078 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1079 | } |
c5aa993b JM |
1080 | break; |
1081 | /* FIXME case JALX : */ | |
1082 | { | |
1083 | unsigned long reg; | |
1084 | reg = jtype_target (inst) << 2; | |
1085 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1086 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1087 | } | |
c5aa993b | 1088 | break; /* The new PC will be alternate mode */ |
e135b889 | 1089 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1090 | equal_branch: |
6c997a34 AC |
1091 | if (read_signed_register (itype_rs (inst)) == |
1092 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1093 | pc += mips32_relative_offset (inst) + 4; |
1094 | else | |
1095 | pc += 8; | |
1096 | break; | |
e135b889 | 1097 | case 5: /* BNE, BNEL */ |
c5aa993b | 1098 | neq_branch: |
6c997a34 | 1099 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1100 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1101 | pc += mips32_relative_offset (inst) + 4; |
1102 | else | |
1103 | pc += 8; | |
1104 | break; | |
e135b889 | 1105 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1106 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1107 | pc += mips32_relative_offset (inst) + 4; |
1108 | else | |
1109 | pc += 8; | |
1110 | break; | |
1111 | case 7: | |
e135b889 DJ |
1112 | default: |
1113 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1114 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1115 | pc += mips32_relative_offset (inst) + 4; |
1116 | else | |
1117 | pc += 8; | |
1118 | break; | |
c5aa993b JM |
1119 | } /* switch */ |
1120 | } /* else */ | |
1121 | return pc; | |
1122 | } /* mips32_next_pc */ | |
c906108c SS |
1123 | |
1124 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1125 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1126 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1127 | We dont want to set a single step instruction on the extend instruction | |
1128 | either. | |
c5aa993b | 1129 | */ |
c906108c SS |
1130 | |
1131 | /* Lots of mips16 instruction formats */ | |
1132 | /* Predicting jumps requires itype,ritype,i8type | |
1133 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1134 | */ |
c906108c SS |
1135 | enum mips16_inst_fmts |
1136 | { | |
c5aa993b JM |
1137 | itype, /* 0 immediate 5,10 */ |
1138 | ritype, /* 1 5,3,8 */ | |
1139 | rrtype, /* 2 5,3,3,5 */ | |
1140 | rritype, /* 3 5,3,3,5 */ | |
1141 | rrrtype, /* 4 5,3,3,3,2 */ | |
1142 | rriatype, /* 5 5,3,3,1,4 */ | |
1143 | shifttype, /* 6 5,3,3,3,2 */ | |
1144 | i8type, /* 7 5,3,8 */ | |
1145 | i8movtype, /* 8 5,3,3,5 */ | |
1146 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1147 | i64type, /* 10 5,3,8 */ | |
1148 | ri64type, /* 11 5,3,3,5 */ | |
1149 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1150 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1151 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1152 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1153 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1154 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1155 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1156 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1157 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1158 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1159 | }; | |
12f02c2a AC |
1160 | /* I am heaping all the fields of the formats into one structure and |
1161 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1162 | struct upk_mips16 |
6d82d43b AC |
1163 | { |
1164 | CORE_ADDR offset; | |
1165 | unsigned int regx; /* Function in i8 type */ | |
1166 | unsigned int regy; | |
1167 | }; | |
c906108c SS |
1168 | |
1169 | ||
12f02c2a AC |
1170 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1171 | for the bits which make up the immediatate extension. */ | |
c906108c | 1172 | |
12f02c2a AC |
1173 | static CORE_ADDR |
1174 | extended_offset (unsigned int extension) | |
c906108c | 1175 | { |
12f02c2a | 1176 | CORE_ADDR value; |
c5aa993b JM |
1177 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1178 | value = value << 6; | |
1179 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1180 | value = value << 5; | |
1181 | value |= extension & 0x01f; /* extract 4:0 */ | |
1182 | return value; | |
c906108c SS |
1183 | } |
1184 | ||
1185 | /* Only call this function if you know that this is an extendable | |
1186 | instruction, It wont malfunction, but why make excess remote memory references? | |
1187 | If the immediate operands get sign extended or somthing, do it after | |
1188 | the extension is performed. | |
c5aa993b | 1189 | */ |
c906108c SS |
1190 | /* FIXME: Every one of these cases needs to worry about sign extension |
1191 | when the offset is to be used in relative addressing */ | |
1192 | ||
1193 | ||
12f02c2a | 1194 | static unsigned int |
c5aa993b | 1195 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1196 | { |
c5aa993b JM |
1197 | char buf[8]; |
1198 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1199 | target_read_memory (pc, buf, 2); | |
1200 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1201 | } |
1202 | ||
1203 | static void | |
c5aa993b | 1204 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1205 | unsigned int extension, |
1206 | unsigned int inst, | |
6d82d43b | 1207 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1208 | { |
12f02c2a AC |
1209 | CORE_ADDR offset; |
1210 | int regx; | |
1211 | int regy; | |
1212 | switch (insn_format) | |
c906108c | 1213 | { |
c5aa993b | 1214 | case itype: |
c906108c | 1215 | { |
12f02c2a AC |
1216 | CORE_ADDR value; |
1217 | if (extension) | |
c5aa993b JM |
1218 | { |
1219 | value = extended_offset (extension); | |
1220 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1221 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1222 | } |
1223 | else | |
c5aa993b | 1224 | { |
12f02c2a | 1225 | value = inst & 0x7ff; |
c5aa993b | 1226 | /* FIXME : Consider sign extension */ |
c906108c | 1227 | } |
12f02c2a AC |
1228 | offset = value; |
1229 | regx = -1; | |
1230 | regy = -1; | |
c906108c | 1231 | } |
c5aa993b JM |
1232 | break; |
1233 | case ritype: | |
1234 | case i8type: | |
1235 | { /* A register identifier and an offset */ | |
c906108c SS |
1236 | /* Most of the fields are the same as I type but the |
1237 | immediate value is of a different length */ | |
12f02c2a AC |
1238 | CORE_ADDR value; |
1239 | if (extension) | |
c906108c | 1240 | { |
c5aa993b JM |
1241 | value = extended_offset (extension); |
1242 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1243 | value |= inst & 0xff; /* eleven bits from instruction */ |
1244 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1245 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1246 | { | |
1247 | value &= ~0x3fff; /* remove the sign bit */ | |
1248 | value = -value; | |
c906108c SS |
1249 | } |
1250 | } | |
c5aa993b JM |
1251 | else |
1252 | { | |
12f02c2a AC |
1253 | value = inst & 0xff; /* 8 bits */ |
1254 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1255 | /* FIXME: Do sign extension , this format needs it */ |
1256 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1257 | { | |
1258 | value &= 0xef; /* remove the sign bit */ | |
1259 | value = -value; | |
1260 | } | |
c5aa993b | 1261 | } |
12f02c2a AC |
1262 | offset = value; |
1263 | regy = -1; | |
c5aa993b | 1264 | break; |
c906108c | 1265 | } |
c5aa993b | 1266 | case jalxtype: |
c906108c | 1267 | { |
c5aa993b | 1268 | unsigned long value; |
12f02c2a AC |
1269 | unsigned int nexthalf; |
1270 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1271 | value = value << 16; |
1272 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1273 | value |= nexthalf; | |
12f02c2a AC |
1274 | offset = value; |
1275 | regx = -1; | |
1276 | regy = -1; | |
c5aa993b | 1277 | break; |
c906108c SS |
1278 | } |
1279 | default: | |
6d82d43b | 1280 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1281 | } |
12f02c2a AC |
1282 | upk->offset = offset; |
1283 | upk->regx = regx; | |
1284 | upk->regy = regy; | |
c906108c SS |
1285 | } |
1286 | ||
1287 | ||
c5aa993b JM |
1288 | static CORE_ADDR |
1289 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1290 | { |
c5aa993b | 1291 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1292 | } |
1293 | ||
12f02c2a AC |
1294 | static CORE_ADDR |
1295 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1296 | unsigned int extension, unsigned int insn) |
c906108c | 1297 | { |
12f02c2a AC |
1298 | int op = (insn >> 11); |
1299 | switch (op) | |
c906108c | 1300 | { |
6d82d43b | 1301 | case 2: /* Branch */ |
12f02c2a AC |
1302 | { |
1303 | CORE_ADDR offset; | |
1304 | struct upk_mips16 upk; | |
1305 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1306 | offset = upk.offset; | |
1307 | if (offset & 0x800) | |
1308 | { | |
1309 | offset &= 0xeff; | |
1310 | offset = -offset; | |
1311 | } | |
1312 | pc += (offset << 1) + 2; | |
1313 | break; | |
1314 | } | |
6d82d43b | 1315 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1316 | { |
1317 | struct upk_mips16 upk; | |
1318 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1319 | pc = add_offset_16 (pc, upk.offset); | |
1320 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1321 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1322 | else | |
1323 | pc |= 0x01; | |
1324 | break; | |
1325 | } | |
6d82d43b | 1326 | case 4: /* beqz */ |
12f02c2a AC |
1327 | { |
1328 | struct upk_mips16 upk; | |
1329 | int reg; | |
1330 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1331 | reg = read_signed_register (upk.regx); | |
1332 | if (reg == 0) | |
1333 | pc += (upk.offset << 1) + 2; | |
1334 | else | |
1335 | pc += 2; | |
1336 | break; | |
1337 | } | |
6d82d43b | 1338 | case 5: /* bnez */ |
12f02c2a AC |
1339 | { |
1340 | struct upk_mips16 upk; | |
1341 | int reg; | |
1342 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1343 | reg = read_signed_register (upk.regx); | |
1344 | if (reg != 0) | |
1345 | pc += (upk.offset << 1) + 2; | |
1346 | else | |
1347 | pc += 2; | |
1348 | break; | |
1349 | } | |
6d82d43b | 1350 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1351 | { |
1352 | struct upk_mips16 upk; | |
1353 | int reg; | |
1354 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1355 | /* upk.regx contains the opcode */ | |
1356 | reg = read_signed_register (24); /* Test register is 24 */ | |
1357 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1358 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1359 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1360 | pc += (upk.offset << 1) + 2; | |
1361 | else | |
1362 | pc += 2; | |
1363 | break; | |
1364 | } | |
6d82d43b | 1365 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1366 | { |
1367 | struct upk_mips16 upk; | |
1368 | /* upk.fmt = rrtype; */ | |
1369 | op = insn & 0x1f; | |
1370 | if (op == 0) | |
c5aa993b | 1371 | { |
12f02c2a AC |
1372 | int reg; |
1373 | upk.regx = (insn >> 8) & 0x07; | |
1374 | upk.regy = (insn >> 5) & 0x07; | |
1375 | switch (upk.regy) | |
c5aa993b | 1376 | { |
12f02c2a AC |
1377 | case 0: |
1378 | reg = upk.regx; | |
1379 | break; | |
1380 | case 1: | |
1381 | reg = 31; | |
6d82d43b | 1382 | break; /* Function return instruction */ |
12f02c2a AC |
1383 | case 2: |
1384 | reg = upk.regx; | |
1385 | break; | |
1386 | default: | |
1387 | reg = 31; | |
6d82d43b | 1388 | break; /* BOGUS Guess */ |
c906108c | 1389 | } |
12f02c2a | 1390 | pc = read_signed_register (reg); |
c906108c | 1391 | } |
12f02c2a | 1392 | else |
c5aa993b | 1393 | pc += 2; |
12f02c2a AC |
1394 | break; |
1395 | } | |
1396 | case 30: | |
1397 | /* This is an instruction extension. Fetch the real instruction | |
1398 | (which follows the extension) and decode things based on | |
1399 | that. */ | |
1400 | { | |
1401 | pc += 2; | |
1402 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1403 | break; | |
1404 | } | |
1405 | default: | |
1406 | { | |
1407 | pc += 2; | |
1408 | break; | |
1409 | } | |
c906108c | 1410 | } |
c5aa993b | 1411 | return pc; |
12f02c2a | 1412 | } |
c906108c | 1413 | |
5a89d8aa | 1414 | static CORE_ADDR |
12f02c2a AC |
1415 | mips16_next_pc (CORE_ADDR pc) |
1416 | { | |
1417 | unsigned int insn = fetch_mips_16 (pc); | |
1418 | return extended_mips16_next_pc (pc, 0, insn); | |
1419 | } | |
1420 | ||
1421 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1422 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1423 | It works by decoding the current instruction and predicting where a |
1424 | branch will go. This isnt hard because all the data is available. | |
1425 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1426 | CORE_ADDR |
1427 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1428 | { |
c5aa993b JM |
1429 | if (pc & 0x01) |
1430 | return mips16_next_pc (pc); | |
1431 | else | |
1432 | return mips32_next_pc (pc); | |
12f02c2a | 1433 | } |
c906108c | 1434 | |
e0f7ec59 AC |
1435 | /* Set up the 'saved_regs' array. This is a data structure containing |
1436 | the addresses on the stack where each register has been saved, for | |
1437 | each stack frame. Registers that have not been saved will have | |
1438 | zero here. The stack pointer register is special: rather than the | |
1439 | address where the stack register has been saved, | |
1440 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1441 | frame's stack register. */ | |
c906108c | 1442 | |
d28e01f4 | 1443 | static void |
acdb74a0 | 1444 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1445 | { |
1446 | int ireg; | |
c906108c SS |
1447 | /* r0 bit means kernel trap */ |
1448 | int kernel_trap; | |
1449 | /* What registers have been saved? Bitmasks. */ | |
1450 | unsigned long gen_mask, float_mask; | |
1451 | mips_extra_func_info_t proc_desc; | |
1452 | t_inst inst; | |
e0f7ec59 | 1453 | CORE_ADDR *saved_regs; |
480d3dd2 | 1454 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1455 | |
1b1d3794 | 1456 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1457 | return; |
1458 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1459 | |
1460 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1461 | in a sigcontext structure somewhere on the stack. If the stack |
1462 | layout for sigtramp changes we might have to change these | |
1463 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1464 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1465 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1466 | above the sigtramp frame. */ | |
4246e332 | 1467 | #define SIGFRAME_BASE mips_regsize (current_gdbarch) |
c906108c | 1468 | /* FIXME! Are these correct?? */ |
4246e332 AC |
1469 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch)) |
1470 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch)) | |
c906108c | 1471 | #define SIGFRAME_FPREGSAVE_OFF \ |
4246e332 | 1472 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch)) |
c906108c | 1473 | #endif |
5a203e44 | 1474 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1475 | { |
1476 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1477 | { | |
6d82d43b AC |
1478 | CORE_ADDR reg_position = |
1479 | (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF + | |
1480 | ireg * mips_regsize (current_gdbarch)); | |
e0f7ec59 | 1481 | set_reg_offset (saved_regs, ireg, reg_position); |
c906108c SS |
1482 | } |
1483 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1484 | { | |
e0f7ec59 AC |
1485 | CORE_ADDR reg_position = (get_frame_base (fci) |
1486 | + SIGFRAME_FPREGSAVE_OFF | |
10a08821 | 1487 | + ireg * mips_regsize (current_gdbarch)); |
6d82d43b AC |
1488 | set_reg_offset (saved_regs, |
1489 | mips_regnum (current_gdbarch)->fp0 + ireg, | |
1490 | reg_position); | |
c906108c | 1491 | } |
e0f7ec59 | 1492 | |
b6cb9035 | 1493 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->pc, |
6d82d43b | 1494 | get_frame_base (fci) + SIGFRAME_PC_OFF); |
e0f7ec59 AC |
1495 | /* SP_REGNUM, contains the value and not the address. */ |
1496 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1497 | return; |
1498 | } | |
1499 | ||
da50a4b7 | 1500 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1501 | if (proc_desc == NULL) |
e0f7ec59 AC |
1502 | /* I'm not sure how/whether this can happen. Normally when we |
1503 | can't find a proc_desc, we "synthesize" one using | |
1504 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1505 | return; |
1506 | ||
c5aa993b JM |
1507 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1508 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1509 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1510 | |
6d82d43b AC |
1511 | if ( /* In any frame other than the innermost or a frame interrupted |
1512 | by a signal, we assume that all registers have been saved. | |
1513 | This assumes that all register saves in a function happen | |
1514 | before the first function call. */ | |
11c02a10 AC |
1515 | (get_next_frame (fci) == NULL |
1516 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
e0f7ec59 | 1517 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1518 | && !PROC_DESC_IS_DUMMY (proc_desc) |
e0f7ec59 | 1519 | /* Don't bother unless we are inside a function prologue. |
6d82d43b | 1520 | Outside the prologue, we know where everything is. */ |
50abf9e5 | 1521 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
e0f7ec59 | 1522 | /* Not sure exactly what kernel_trap means, but if it means the |
6d82d43b AC |
1523 | kernel saves the registers without a prologue doing it, we |
1524 | better not examine the prologue to see whether registers | |
1525 | have been saved yet. */ | |
c5aa993b | 1526 | && !kernel_trap) |
c906108c | 1527 | { |
e0f7ec59 AC |
1528 | /* We need to figure out whether the registers that the |
1529 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1530 | |
1531 | CORE_ADDR addr; | |
1532 | ||
1533 | /* Bitmasks; set if we have found a save for the register. */ | |
1534 | unsigned long gen_save_found = 0; | |
1535 | unsigned long float_save_found = 0; | |
1536 | int instlen; | |
1537 | ||
1538 | /* If the address is odd, assume this is MIPS16 code. */ | |
1539 | addr = PROC_LOW_ADDR (proc_desc); | |
1540 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1541 | ||
e0f7ec59 AC |
1542 | /* Scan through this function's instructions preceding the |
1543 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1544 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1545 | { |
1546 | inst = mips_fetch_instruction (addr); | |
1547 | if (pc_is_mips16 (addr)) | |
1548 | mips16_decode_reg_save (inst, &gen_save_found); | |
1549 | else | |
1550 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1551 | addr += instlen; | |
1552 | } | |
1553 | gen_mask = gen_save_found; | |
1554 | float_mask = float_save_found; | |
1555 | } | |
1556 | ||
e0f7ec59 AC |
1557 | /* Fill in the offsets for the registers which gen_mask says were |
1558 | saved. */ | |
1559 | { | |
1560 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1561 | + PROC_REG_OFFSET (proc_desc)); | |
1562 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1563 | if (gen_mask & 0x80000000) | |
1564 | { | |
1565 | set_reg_offset (saved_regs, ireg, reg_position); | |
480d3dd2 | 1566 | reg_position -= mips_saved_regsize (tdep); |
e0f7ec59 AC |
1567 | } |
1568 | } | |
c906108c | 1569 | |
e0f7ec59 AC |
1570 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1571 | order of that normally used by gcc. Therefore, we have to fetch | |
1572 | the first instruction of the function, and if it's an entry | |
1573 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1574 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1575 | { | |
1576 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1577 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1578 | /* entry */ | |
c906108c SS |
1579 | { |
1580 | int reg; | |
1581 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1582 | |
c906108c | 1583 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1584 | CORE_ADDR reg_position = (get_frame_base (fci) |
1585 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1586 | if (inst & 0x20) |
480d3dd2 | 1587 | reg_position -= mips_saved_regsize (tdep); |
c906108c | 1588 | |
e0f7ec59 | 1589 | /* Check if the s0 and s1 registers were pushed on the |
6d82d43b | 1590 | stack. */ |
c5aa993b | 1591 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1592 | { |
e0f7ec59 | 1593 | set_reg_offset (saved_regs, reg, reg_position); |
480d3dd2 | 1594 | reg_position -= mips_saved_regsize (tdep); |
c906108c SS |
1595 | } |
1596 | } | |
1597 | } | |
1598 | ||
e0f7ec59 AC |
1599 | /* Fill in the offsets for the registers which float_mask says were |
1600 | saved. */ | |
1601 | { | |
1602 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1603 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1604 | |
e0f7ec59 AC |
1605 | /* Fill in the offsets for the float registers which float_mask |
1606 | says were saved. */ | |
1607 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1608 | if (float_mask & 0x80000000) | |
1609 | { | |
480d3dd2 AC |
1610 | if (mips_saved_regsize (tdep) == 4 |
1611 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
c57bb9fa AC |
1612 | { |
1613 | /* On a big endian 32 bit ABI, floating point registers | |
6d82d43b AC |
1614 | are paired to form doubles such that the most |
1615 | significant part is in $f[N+1] and the least | |
1616 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1617 | registers are also spilled as a pair and stored as a | |
1618 | double. | |
c57bb9fa AC |
1619 | |
1620 | When little-endian the least significant part is | |
1621 | stored first leading to the memory order $f[N] and | |
1622 | then $f[N+1]. | |
1623 | ||
6d82d43b AC |
1624 | Unfortunately, when big-endian the most significant |
1625 | part of the double is stored first, and the least | |
1626 | significant is stored second. This leads to the | |
1627 | registers being ordered in memory as firt $f[N+1] and | |
1628 | then $f[N]. | |
1629 | ||
1630 | For the big-endian case make certain that the | |
1631 | addresses point at the correct (swapped) locations | |
1632 | $f[N] and $f[N+1] pair (keep in mind that | |
1633 | reg_position is decremented each time through the | |
1634 | loop). */ | |
c57bb9fa | 1635 | if ((ireg & 1)) |
6d82d43b AC |
1636 | set_reg_offset (saved_regs, |
1637 | mips_regnum (current_gdbarch)->fp0 + ireg, | |
480d3dd2 | 1638 | reg_position - mips_saved_regsize (tdep)); |
c57bb9fa | 1639 | else |
6d82d43b AC |
1640 | set_reg_offset (saved_regs, |
1641 | mips_regnum (current_gdbarch)->fp0 + ireg, | |
480d3dd2 | 1642 | reg_position + mips_saved_regsize (tdep)); |
c57bb9fa AC |
1643 | } |
1644 | else | |
6d82d43b AC |
1645 | set_reg_offset (saved_regs, |
1646 | mips_regnum (current_gdbarch)->fp0 + ireg, | |
1647 | reg_position); | |
480d3dd2 | 1648 | reg_position -= mips_saved_regsize (tdep); |
e0f7ec59 | 1649 | } |
c906108c | 1650 | |
b6cb9035 AC |
1651 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->pc, |
1652 | saved_regs[RA_REGNUM]); | |
e0f7ec59 | 1653 | } |
d28e01f4 | 1654 | |
e0f7ec59 AC |
1655 | /* SP_REGNUM, contains the value and not the address. */ |
1656 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1657 | } |
1658 | ||
c906108c | 1659 | static CORE_ADDR |
acdb74a0 | 1660 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1661 | { |
a4b8ebc8 AC |
1662 | /* Always a pseudo. */ |
1663 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1664 | if (fi == NULL) |
c906108c | 1665 | { |
a4b8ebc8 AC |
1666 | LONGEST val; |
1667 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1668 | return val; | |
f796e4be | 1669 | } |
a4b8ebc8 AC |
1670 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1671 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1672 | In fact, it is so special that it can even only be fetched | |
1673 | using a raw register number! Once this code as been converted | |
1674 | to frame-unwind the problem goes away. */ | |
1675 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1676 | else |
a4b8ebc8 | 1677 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1678 | |
c906108c SS |
1679 | } |
1680 | ||
1681 | /* mips_addr_bits_remove - remove useless address bits */ | |
1682 | ||
875e1767 | 1683 | static CORE_ADDR |
acdb74a0 | 1684 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1685 | { |
480d3dd2 | 1686 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 1687 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
1688 | /* This hack is a work-around for existing boards using PMON, the |
1689 | simulator, and any other 64-bit targets that doesn't have true | |
1690 | 64-bit addressing. On these targets, the upper 32 bits of | |
1691 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1692 | likely to have been sign extended to all 1s by instruction | |
1693 | sequences that load 32-bit addresses. For example, a typical | |
1694 | piece of code that loads an address is this: | |
1695 | ||
1696 | lui $r2, <upper 16 bits> | |
1697 | ori $r2, <lower 16 bits> | |
1698 | ||
1699 | But the lui sign-extends the value such that the upper 32 bits | |
1700 | may be all 1s. The workaround is simply to mask off these | |
1701 | bits. In the future, gcc may be changed to support true 64-bit | |
1702 | addressing, and this masking will have to be disabled. */ | |
1703 | return addr &= 0xffffffffUL; | |
1704 | else | |
1705 | return addr; | |
c906108c SS |
1706 | } |
1707 | ||
9022177c DJ |
1708 | /* mips_software_single_step() is called just before we want to resume |
1709 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1710 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1711 | the target of the coming instruction and breakpoint it. |
1712 | ||
1713 | single_step is also called just after the inferior stops. If we had | |
1714 | set up a simulated single-step, we undo our damage. */ | |
1715 | ||
1716 | void | |
1717 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1718 | { | |
1719 | static CORE_ADDR next_pc; | |
1720 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1721 | static binsn_quantum break_mem; | |
1722 | CORE_ADDR pc; | |
1723 | ||
1724 | if (insert_breakpoints_p) | |
1725 | { | |
b6cb9035 | 1726 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
1727 | next_pc = mips_next_pc (pc); |
1728 | ||
1729 | target_insert_breakpoint (next_pc, break_mem); | |
1730 | } | |
1731 | else | |
1732 | target_remove_breakpoint (next_pc, break_mem); | |
1733 | } | |
1734 | ||
97f46953 | 1735 | static CORE_ADDR |
acdb74a0 | 1736 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1737 | { |
1738 | CORE_ADDR pc, tmp; | |
1739 | ||
11c02a10 | 1740 | pc = ((fromleaf) |
6913c89a | 1741 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1742 | : get_next_frame (prev) |
6d82d43b | 1743 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) : read_pc ()); |
5a89d8aa | 1744 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1745 | return tmp ? tmp : pc; |
c906108c SS |
1746 | } |
1747 | ||
1748 | ||
f7ab6ec6 | 1749 | static CORE_ADDR |
acdb74a0 | 1750 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1751 | { |
1752 | CORE_ADDR saved_pc; | |
480d3dd2 | 1753 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1754 | |
50abf9e5 | 1755 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 | 1756 | { |
a4b8ebc8 | 1757 | /* Always unwind the cooked PC register value. */ |
b6cb9035 | 1758 | saved_pc = frame_unwind_register_signed (frame, NUM_REGS + mips_regnum (current_gdbarch)->pc); |
cedea778 | 1759 | } |
c906108c | 1760 | else |
a4b8ebc8 AC |
1761 | { |
1762 | mips_extra_func_info_t proc_desc | |
1763 | = get_frame_extra_info (frame)->proc_desc; | |
1764 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
480d3dd2 | 1765 | saved_pc = read_memory_integer ((get_frame_base (frame) |
6d82d43b AC |
1766 | - mips_saved_regsize (tdep)), |
1767 | mips_saved_regsize (tdep)); | |
a4b8ebc8 AC |
1768 | else |
1769 | { | |
1770 | /* We have to get the saved pc from the sigcontext if it is | |
1771 | a signal handler frame. */ | |
b6cb9035 AC |
1772 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME |
1773 | ? mips_regnum (current_gdbarch)->pc | |
a4b8ebc8 AC |
1774 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
1775 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1776 | } | |
1777 | } | |
c906108c SS |
1778 | return ADDR_BITS_REMOVE (saved_pc); |
1779 | } | |
1780 | ||
1781 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1782 | |
1783 | /* This hack will go away once the get_prev_frame() code has been | |
1784 | modified to set the frame's type first. That is BEFORE init extra | |
1785 | frame info et.al. is called. This is because it will become | |
1786 | possible to skip the init extra info call for sigtramp and dummy | |
1787 | frames. */ | |
1788 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1789 | |
e0f7ec59 AC |
1790 | /* Set a register's saved stack address in temp_saved_regs. If an |
1791 | address has already been set for this register, do nothing; this | |
1792 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1793 | function prologue. |
1794 | ||
1795 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1796 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1797 | is used as it is only second range (the ABI instead of ISA | |
1798 | registers) that comes into play when finding saved registers in a | |
1799 | frame. */ | |
c906108c SS |
1800 | |
1801 | static void | |
e0f7ec59 | 1802 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1803 | { |
e0f7ec59 | 1804 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1805 | { |
1806 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1807 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1808 | } | |
c906108c SS |
1809 | } |
1810 | ||
1811 | ||
1812 | /* Test whether the PC points to the return instruction at the | |
1813 | end of a function. */ | |
1814 | ||
c5aa993b | 1815 | static int |
acdb74a0 | 1816 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1817 | { |
1818 | if (pc_is_mips16 (pc)) | |
1819 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1820 | generates a "jr $ra"; other times it generates code to load | |
1821 | the return address from the stack to an accessible register (such | |
1822 | as $a3), then a "jr" using that register. This second case | |
1823 | is almost impossible to distinguish from an indirect jump | |
1824 | used for switch statements, so we don't even try. */ | |
1825 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1826 | else | |
1827 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1828 | } | |
1829 | ||
1830 | ||
1831 | /* This fencepost looks highly suspicious to me. Removing it also | |
1832 | seems suspicious as it could affect remote debugging across serial | |
1833 | lines. */ | |
1834 | ||
1835 | static CORE_ADDR | |
acdb74a0 | 1836 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1837 | { |
c5aa993b JM |
1838 | CORE_ADDR start_pc; |
1839 | CORE_ADDR fence; | |
1840 | int instlen; | |
1841 | int seen_adjsp = 0; | |
c906108c | 1842 | |
c5aa993b JM |
1843 | pc = ADDR_BITS_REMOVE (pc); |
1844 | start_pc = pc; | |
1845 | fence = start_pc - heuristic_fence_post; | |
1846 | if (start_pc == 0) | |
1847 | return 0; | |
c906108c | 1848 | |
6d82d43b | 1849 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 1850 | fence = VM_MIN_ADDRESS; |
c906108c | 1851 | |
c5aa993b | 1852 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1853 | |
c5aa993b JM |
1854 | /* search back for previous return */ |
1855 | for (start_pc -= instlen;; start_pc -= instlen) | |
1856 | if (start_pc < fence) | |
1857 | { | |
1858 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1859 | stop_soon, but with this test, at least we |
c5aa993b JM |
1860 | don't print out warnings for every child forked (eg, on |
1861 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1862 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1863 | { |
c5aa993b JM |
1864 | static int blurb_printed = 0; |
1865 | ||
6d82d43b AC |
1866 | warning |
1867 | ("Warning: GDB can't find the start of the function at 0x%s.", | |
1868 | paddr_nz (pc)); | |
c5aa993b JM |
1869 | |
1870 | if (!blurb_printed) | |
c906108c | 1871 | { |
c5aa993b JM |
1872 | /* This actually happens frequently in embedded |
1873 | development, when you first connect to a board | |
1874 | and your stack pointer and pc are nowhere in | |
1875 | particular. This message needs to give people | |
1876 | in that situation enough information to | |
1877 | determine that it's no big deal. */ | |
1878 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1879 | GDB is unable to find the start of the function at 0x%s\n\ |
1880 | and thus can't determine the size of that function's stack frame.\n\ | |
1881 | This means that GDB may be unable to access that stack frame, or\n\ | |
1882 | the frames below it.\n\ | |
1883 | This problem is most likely caused by an invalid program counter or\n\ | |
1884 | stack pointer.\n\ | |
1885 | However, if you think GDB should simply search farther back\n\ | |
1886 | from 0x%s for code which looks like the beginning of a\n\ | |
1887 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 1888 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 1889 | blurb_printed = 1; |
c906108c | 1890 | } |
c906108c SS |
1891 | } |
1892 | ||
c5aa993b JM |
1893 | return 0; |
1894 | } | |
1895 | else if (pc_is_mips16 (start_pc)) | |
1896 | { | |
1897 | unsigned short inst; | |
1898 | ||
1899 | /* On MIPS16, any one of the following is likely to be the | |
1900 | start of a function: | |
1901 | entry | |
1902 | addiu sp,-n | |
1903 | daddiu sp,-n | |
1904 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1905 | inst = mips_fetch_instruction (start_pc); | |
1906 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1907 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1908 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1909 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1910 | break; | |
1911 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1912 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1913 | seen_adjsp = 1; | |
1914 | else | |
1915 | seen_adjsp = 0; | |
1916 | } | |
1917 | else if (mips_about_to_return (start_pc)) | |
1918 | { | |
1919 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1920 | break; | |
1921 | } | |
1922 | ||
c5aa993b | 1923 | return start_pc; |
c906108c SS |
1924 | } |
1925 | ||
1926 | /* Fetch the immediate value from a MIPS16 instruction. | |
1927 | If the previous instruction was an EXTEND, use it to extend | |
1928 | the upper bits of the immediate value. This is a helper function | |
1929 | for mips16_heuristic_proc_desc. */ | |
1930 | ||
1931 | static int | |
acdb74a0 AC |
1932 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1933 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
1934 | int nbits, /* number of bits in imm field */ |
1935 | int scale, /* scale factor to be applied to imm */ | |
1936 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1937 | { |
1938 | int offset; | |
1939 | ||
1940 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1941 | { | |
1942 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1943 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1944 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1945 | return offset | (inst & 0x1f); | |
1946 | } | |
1947 | else | |
1948 | { | |
1949 | int max_imm = 1 << nbits; | |
1950 | int mask = max_imm - 1; | |
1951 | int sign_bit = max_imm >> 1; | |
1952 | ||
1953 | offset = inst & mask; | |
1954 | if (is_signed && (offset & sign_bit)) | |
1955 | offset = 0 - (max_imm - offset); | |
1956 | return offset * scale; | |
1957 | } | |
1958 | } | |
1959 | ||
1960 | ||
1961 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1962 | stream from start_pc to limit_pc. */ | |
1963 | ||
1964 | static void | |
acdb74a0 AC |
1965 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1966 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1967 | { |
1968 | CORE_ADDR cur_pc; | |
1969 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1970 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1971 | unsigned inst = 0; /* current instruction */ | |
1972 | unsigned entry_inst = 0; /* the entry instruction */ | |
1973 | int reg, offset; | |
480d3dd2 | 1974 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1975 | |
c5aa993b JM |
1976 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1977 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1978 | |
1979 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1980 | { | |
1981 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1982 | the immediate offset extension from it in mips16_get_imm. */ | |
1983 | prev_inst = inst; | |
1984 | ||
1985 | /* Fetch and decode the instruction. */ | |
1986 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1987 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 1988 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
1989 | { |
1990 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1991 | if (offset < 0) /* negative stack adjustment? */ |
1992 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1993 | else |
1994 | /* Exit loop if a positive stack adjustment is found, which | |
1995 | usually means that the stack cleanup code in the function | |
1996 | epilogue is reached. */ | |
1997 | break; | |
1998 | } | |
1999 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2000 | { | |
2001 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2002 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2003 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2004 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2005 | } |
2006 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2007 | { | |
2008 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2009 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2010 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2011 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2012 | } |
2013 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2014 | { | |
2015 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2016 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2017 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2018 | } |
2019 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2020 | { | |
2021 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2022 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2023 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2024 | } |
c5aa993b | 2025 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2026 | { |
2027 | frame_addr = sp; | |
2028 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2029 | } | |
2030 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2031 | { | |
2032 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2033 | frame_addr = sp + offset; | |
2034 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2035 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2036 | } | |
2037 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2038 | { | |
2039 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2040 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2041 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2042 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2043 | } |
2044 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2045 | { | |
2046 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2047 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2048 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2049 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2050 | } |
c5aa993b JM |
2051 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2052 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2053 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2054 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2055 | } |
2056 | ||
c5aa993b JM |
2057 | /* The entry instruction is typically the first instruction in a function, |
2058 | and it stores registers at offsets relative to the value of the old SP | |
2059 | (before the prologue). But the value of the sp parameter to this | |
2060 | function is the new SP (after the prologue has been executed). So we | |
2061 | can't calculate those offsets until we've seen the entire prologue, | |
2062 | and can calculate what the old SP must have been. */ | |
2063 | if (entry_inst != 0) | |
2064 | { | |
2065 | int areg_count = (entry_inst >> 8) & 7; | |
2066 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2067 | |
c5aa993b JM |
2068 | /* The entry instruction always subtracts 32 from the SP. */ |
2069 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2070 | |
c5aa993b JM |
2071 | /* Now we can calculate what the SP must have been at the |
2072 | start of the function prologue. */ | |
2073 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2074 | |
c5aa993b JM |
2075 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2076 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2077 | { | |
2078 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2079 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
480d3dd2 | 2080 | offset += mips_saved_regsize (tdep); |
c5aa993b | 2081 | } |
c906108c | 2082 | |
c5aa993b JM |
2083 | /* Check if the ra register was pushed on the stack. */ |
2084 | offset = -4; | |
2085 | if (entry_inst & 0x20) | |
2086 | { | |
2087 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2088 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
480d3dd2 | 2089 | offset -= mips_saved_regsize (tdep); |
c5aa993b | 2090 | } |
c906108c | 2091 | |
c5aa993b JM |
2092 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2093 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2094 | { | |
2095 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2096 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
480d3dd2 | 2097 | offset -= mips_saved_regsize (tdep); |
c5aa993b JM |
2098 | } |
2099 | } | |
c906108c SS |
2100 | } |
2101 | ||
2102 | static void | |
fba45db2 KB |
2103 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2104 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2105 | { |
2106 | CORE_ADDR cur_pc; | |
c5aa993b | 2107 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2108 | restart: |
fe29b929 | 2109 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2110 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2111 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2112 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2113 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2114 | { | |
2115 | unsigned long inst, high_word, low_word; | |
2116 | int reg; | |
2117 | ||
2118 | /* Fetch the instruction. */ | |
2119 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2120 | ||
2121 | /* Save some code by pre-extracting some useful fields. */ | |
2122 | high_word = (inst >> 16) & 0xffff; | |
2123 | low_word = inst & 0xffff; | |
2124 | reg = high_word & 0x1f; | |
2125 | ||
c5aa993b | 2126 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2127 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2128 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2129 | { | |
2130 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2131 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2132 | else |
2133 | /* Exit loop if a positive stack adjustment is found, which | |
2134 | usually means that the stack cleanup code in the function | |
2135 | epilogue is reached. */ | |
2136 | break; | |
2137 | } | |
2138 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2139 | { | |
c5aa993b | 2140 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2141 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2142 | } |
2143 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2144 | { | |
2145 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2146 | but the register size used is only 32 bits. Make the address | |
2147 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2148 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
6d82d43b AC |
2149 | set_reg_offset (temp_saved_regs, reg, |
2150 | sp + low_word + 8 - mips_regsize (current_gdbarch)); | |
c906108c | 2151 | } |
c5aa993b | 2152 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2153 | { |
2154 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2155 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2156 | frame_addr = sp + low_word; | |
c906108c SS |
2157 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2158 | { | |
2159 | unsigned alloca_adjust; | |
2160 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2161 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2162 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2163 | if (alloca_adjust > 0) |
2164 | { | |
2165 | /* FP > SP + frame_size. This may be because | |
2166 | * of an alloca or somethings similar. | |
2167 | * Fix sp to "pre-alloca" value, and try again. | |
2168 | */ | |
2169 | sp += alloca_adjust; | |
2170 | goto restart; | |
2171 | } | |
2172 | } | |
2173 | } | |
c5aa993b JM |
2174 | /* move $30,$sp. With different versions of gas this will be either |
2175 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2176 | Accept any one of these. */ | |
c906108c SS |
2177 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2178 | { | |
2179 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2180 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2181 | { | |
2182 | unsigned alloca_adjust; | |
2183 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2184 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2185 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2186 | if (alloca_adjust > 0) |
2187 | { | |
2188 | /* FP > SP + frame_size. This may be because | |
2189 | * of an alloca or somethings similar. | |
2190 | * Fix sp to "pre-alloca" value, and try again. | |
2191 | */ | |
2192 | sp += alloca_adjust; | |
2193 | goto restart; | |
2194 | } | |
2195 | } | |
2196 | } | |
c5aa993b | 2197 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2198 | { |
c5aa993b | 2199 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2200 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2201 | } |
2202 | } | |
2203 | } | |
2204 | ||
2205 | static mips_extra_func_info_t | |
acdb74a0 | 2206 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2207 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2208 | { |
479412cd DJ |
2209 | CORE_ADDR sp; |
2210 | ||
2211 | if (cur_frame) | |
a4b8ebc8 | 2212 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2213 | else |
2214 | sp = 0; | |
c906108c | 2215 | |
c5aa993b JM |
2216 | if (start_pc == 0) |
2217 | return NULL; | |
2218 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2219 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2220 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2221 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2222 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2223 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2224 | ||
2225 | if (start_pc + 200 < limit_pc) | |
2226 | limit_pc = start_pc + 200; | |
2227 | if (pc_is_mips16 (start_pc)) | |
2228 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2229 | else | |
2230 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2231 | return &temp_proc_desc; | |
2232 | } | |
2233 | ||
6c0d6680 DJ |
2234 | struct mips_objfile_private |
2235 | { | |
2236 | bfd_size_type size; | |
2237 | char *contents; | |
2238 | }; | |
2239 | ||
2240 | /* Global used to communicate between non_heuristic_proc_desc and | |
2241 | compare_pdr_entries within qsort (). */ | |
2242 | static bfd *the_bfd; | |
2243 | ||
2244 | static int | |
2245 | compare_pdr_entries (const void *a, const void *b) | |
2246 | { | |
2247 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2248 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2249 | ||
2250 | if (lhs < rhs) | |
2251 | return -1; | |
2252 | else if (lhs == rhs) | |
2253 | return 0; | |
2254 | else | |
2255 | return 1; | |
2256 | } | |
2257 | ||
c906108c | 2258 | static mips_extra_func_info_t |
acdb74a0 | 2259 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2260 | { |
2261 | CORE_ADDR startaddr; | |
2262 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2263 | struct block *b = block_for_pc (pc); |
c906108c | 2264 | struct symbol *sym; |
6c0d6680 DJ |
2265 | struct obj_section *sec; |
2266 | struct mips_objfile_private *priv; | |
2267 | ||
ae45cd16 | 2268 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2269 | return NULL; |
c906108c SS |
2270 | |
2271 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2272 | if (addrptr) | |
2273 | *addrptr = startaddr; | |
6c0d6680 DJ |
2274 | |
2275 | priv = NULL; | |
2276 | ||
2277 | sec = find_pc_section (pc); | |
2278 | if (sec != NULL) | |
c906108c | 2279 | { |
6c0d6680 DJ |
2280 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2281 | ||
2282 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2283 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2284 | |
2285 | the_bfd = sec->objfile->obfd; | |
2286 | if (priv == NULL | |
2287 | && (the_bfd->format == bfd_object | |
2288 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2289 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2290 | { | |
2291 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2292 | This means that we should not bother with this method on 64-bit | |
2293 | targets (until that is fixed). */ | |
2294 | ||
8b92e4d5 | 2295 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2296 | sizeof (struct mips_objfile_private)); |
2297 | priv->size = 0; | |
2298 | sec->objfile->obj_private = priv; | |
2299 | } | |
2300 | else if (priv == NULL) | |
2301 | { | |
2302 | asection *bfdsec; | |
2303 | ||
8b92e4d5 | 2304 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2305 | sizeof (struct mips_objfile_private)); |
2306 | ||
2307 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2308 | if (bfdsec != NULL) | |
2309 | { | |
2310 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2311 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2312 | priv->size); |
2313 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2314 | priv->contents, 0, priv->size); | |
2315 | ||
2316 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2317 | presence of multiple code sections (and other corner cases) |
2318 | it can become unsorted. Sort it so that we can use a faster | |
2319 | binary search. */ | |
2320 | qsort (priv->contents, priv->size / 32, 32, | |
2321 | compare_pdr_entries); | |
6c0d6680 DJ |
2322 | } |
2323 | else | |
2324 | priv->size = 0; | |
2325 | ||
2326 | sec->objfile->obj_private = priv; | |
2327 | } | |
2328 | the_bfd = NULL; | |
2329 | ||
2330 | if (priv->size != 0) | |
2331 | { | |
2332 | int low, mid, high; | |
2333 | char *ptr; | |
2334 | ||
2335 | low = 0; | |
2336 | high = priv->size / 32; | |
2337 | ||
2338 | do | |
2339 | { | |
2340 | CORE_ADDR pdr_pc; | |
2341 | ||
2342 | mid = (low + high) / 2; | |
2343 | ||
2344 | ptr = priv->contents + mid * 32; | |
2345 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2346 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2347 | SECT_OFF_TEXT (sec->objfile)); | |
2348 | if (pdr_pc == startaddr) | |
2349 | break; | |
2350 | if (pdr_pc > startaddr) | |
2351 | high = mid; | |
2352 | else | |
2353 | low = mid + 1; | |
2354 | } | |
2355 | while (low != high); | |
2356 | ||
2357 | if (low != high) | |
2358 | { | |
2359 | struct symbol *sym = find_pc_function (pc); | |
2360 | ||
2361 | /* Fill in what we need of the proc_desc. */ | |
2362 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 2363 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2364 | sizeof (struct mips_extra_func_info)); |
2365 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2366 | ||
2367 | /* Only used for dummy frames. */ | |
2368 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2369 | ||
2370 | PROC_FRAME_OFFSET (proc_desc) | |
2371 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2372 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2373 | ptr + 24); | |
2374 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2375 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2376 | ptr + 4); | |
2377 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2378 | ptr + 12); | |
2379 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2380 | ptr + 8); | |
2381 | PROC_FREG_OFFSET (proc_desc) | |
2382 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2383 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2384 | ptr + 28); | |
2385 | proc_desc->pdr.isym = (long) sym; | |
2386 | ||
2387 | return proc_desc; | |
2388 | } | |
2389 | } | |
c906108c SS |
2390 | } |
2391 | ||
6c0d6680 DJ |
2392 | if (b == NULL) |
2393 | return NULL; | |
2394 | ||
2395 | if (startaddr > BLOCK_START (b)) | |
2396 | { | |
2397 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
2398 | print_frame_info. It might be better to move this check into |
2399 | symbol reading. */ | |
6c0d6680 DJ |
2400 | return NULL; |
2401 | } | |
2402 | ||
176620f1 | 2403 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2404 | |
c906108c SS |
2405 | /* If we never found a PDR for this function in symbol reading, then |
2406 | examine prologues to find the information. */ | |
2407 | if (sym) | |
2408 | { | |
2409 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2410 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2411 | return NULL; | |
2412 | else | |
2413 | return proc_desc; | |
2414 | } | |
2415 | else | |
2416 | return NULL; | |
2417 | } | |
2418 | ||
2419 | ||
2420 | static mips_extra_func_info_t | |
479412cd | 2421 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2422 | { |
2423 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2424 | CORE_ADDR startaddr = 0; |
c906108c SS |
2425 | |
2426 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2427 | ||
2428 | if (proc_desc) | |
2429 | { | |
2430 | /* IF this is the topmost frame AND | |
2431 | * (this proc does not have debugging information OR | |
2432 | * the PC is in the procedure prologue) | |
2433 | * THEN create a "heuristic" proc_desc (by analyzing | |
2434 | * the actual code) to replace the "official" proc_desc. | |
2435 | */ | |
2436 | if (next_frame == NULL) | |
2437 | { | |
2438 | struct symtab_and_line val; | |
2439 | struct symbol *proc_symbol = | |
c86b5b38 | 2440 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2441 | |
2442 | if (proc_symbol) | |
2443 | { | |
2444 | val = find_pc_line (BLOCK_START | |
6d82d43b | 2445 | (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); |
c906108c SS |
2446 | val.pc = val.end ? val.end : pc; |
2447 | } | |
2448 | if (!proc_symbol || pc < val.pc) | |
2449 | { | |
2450 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2451 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2452 | pc, next_frame, cur_frame); | |
c906108c SS |
2453 | if (found_heuristic) |
2454 | proc_desc = found_heuristic; | |
2455 | } | |
2456 | } | |
2457 | } | |
2458 | else | |
2459 | { | |
2460 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2461 | by procedure call dummys. However, the procedures being called ought |
2462 | to have their own proc_descs, and even if they don't, | |
2463 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2464 | |
aa1ee363 | 2465 | struct linked_proc_info *link; |
c906108c SS |
2466 | |
2467 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2468 | if (PROC_LOW_ADDR (&link->info) <= pc |
2469 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2470 | return &link->info; |
2471 | ||
2472 | if (startaddr == 0) | |
2473 | startaddr = heuristic_proc_start (pc); | |
2474 | ||
6d82d43b | 2475 | proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2476 | } |
2477 | return proc_desc; | |
2478 | } | |
2479 | ||
2480 | static CORE_ADDR | |
6d82d43b | 2481 | get_frame_pointer (struct frame_info *frame, mips_extra_func_info_t proc_desc) |
c906108c | 2482 | { |
a4b8ebc8 | 2483 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
6d82d43b | 2484 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); |
c906108c SS |
2485 | } |
2486 | ||
5a89d8aa | 2487 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2488 | |
f7ab6ec6 | 2489 | static CORE_ADDR |
acdb74a0 | 2490 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2491 | { |
2492 | mips_extra_func_info_t proc_desc; | |
2493 | CORE_ADDR tmp; | |
8bedc050 | 2494 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2495 | |
c906108c SS |
2496 | /* Check if the PC is inside a call stub. If it is, fetch the |
2497 | PC of the caller of that stub. */ | |
5a89d8aa | 2498 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2499 | saved_pc = tmp; |
2500 | ||
ae45cd16 | 2501 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2502 | { |
2503 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2504 | is well, frame->frame the bottom of the current frame will | |
2505 | contain that value. */ | |
1e2330ba | 2506 | return get_frame_base (frame); |
cedea778 AC |
2507 | } |
2508 | ||
c906108c | 2509 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2510 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2511 | if (!proc_desc) |
2512 | return 0; | |
2513 | ||
2514 | cached_proc_desc = proc_desc; | |
2515 | ||
2516 | /* If no frame pointer and frame size is zero, we must be at end | |
2517 | of stack (or otherwise hosed). If we don't check frame size, | |
2518 | we loop forever if we see a zero size frame. */ | |
2519 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2520 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 | 2521 | /* The previous frame from a sigtramp frame might be frameless |
6d82d43b | 2522 | and have frame size zero. */ |
5a203e44 | 2523 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2524 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2525 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2526 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2527 | return 0; |
2528 | else | |
2529 | return get_frame_pointer (frame, proc_desc); | |
2530 | } | |
2531 | ||
f7ab6ec6 | 2532 | static void |
acdb74a0 | 2533 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2534 | { |
2535 | int regnum; | |
f2c16bd6 KB |
2536 | mips_extra_func_info_t proc_desc; |
2537 | ||
2538 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2539 | return; | |
c906108c | 2540 | |
f796e4be KB |
2541 | /* Use proc_desc calculated in frame_chain. When there is no |
2542 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2543 | find_proc_desc () to calculate it, passing an explicit | |
2544 | NULL as the frame parameter. */ | |
f2c16bd6 | 2545 | proc_desc = |
11c02a10 AC |
2546 | get_next_frame (fci) |
2547 | ? cached_proc_desc | |
f796e4be | 2548 | : find_proc_desc (get_frame_pc (fci), |
6d82d43b | 2549 | NULL /* i.e, get_next_frame (fci) */ , |
f796e4be | 2550 | 1); |
c906108c | 2551 | |
a00a19e9 | 2552 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2553 | |
da50a4b7 | 2554 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2555 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2556 | if (proc_desc) | |
2557 | { | |
2558 | /* Fixup frame-pointer - only needed for top frame */ | |
2559 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2560 | Get the value of the frame relative sp, procedure might have been |
2561 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2562 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2563 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
6d82d43b AC |
2564 | deprecated_update_frame_base_hack (fci, |
2565 | read_next_frame_reg (get_next_frame | |
2566 | (fci), | |
2567 | NUM_REGS + | |
2568 | SP_REGNUM)); | |
50abf9e5 | 2569 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 | 2570 | /* Do not ``fix'' fci->frame. It will have the value of the |
6d82d43b AC |
2571 | generic dummy frame's top-of-stack (since the draft |
2572 | fci->frame is obtained by returning the unwound stack | |
2573 | pointer) and that is what we want. That way the fci->frame | |
2574 | value will match the top-of-stack value that was saved as | |
2575 | part of the dummy frames data. */ | |
2576 | /* Do nothing. */ ; | |
c906108c | 2577 | else |
6d82d43b AC |
2578 | deprecated_update_frame_base_hack (fci, |
2579 | get_frame_pointer (get_next_frame | |
2580 | (fci), | |
2581 | proc_desc)); | |
c906108c SS |
2582 | |
2583 | if (proc_desc == &temp_proc_desc) | |
2584 | { | |
2585 | char *name; | |
2586 | ||
2587 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2588 | mips_find_saved_registers will do that for us. We can't |
2589 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2590 | yet set. */ | |
2591 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
6d82d43b AC |
2592 | frame.c:get_prev_frame() is modified to set the frame's |
2593 | type before calling functions like this. */ | |
50abf9e5 | 2594 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2595 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2596 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2597 | { |
c5aa993b | 2598 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2599 | /* Set value of previous frame's stack pointer. |
2600 | Remember that saved_regs[SP_REGNUM] is special in | |
2601 | that it contains the value of the stack pointer | |
2602 | register. The other saved_regs values are addresses | |
2603 | (in the inferior) at which a given register's value | |
2604 | may be found. */ | |
2605 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2606 | get_frame_base (fci)); | |
b6cb9035 | 2607 | set_reg_offset (temp_saved_regs, mips_regnum (current_gdbarch)->pc, |
e0f7ec59 | 2608 | temp_saved_regs[RA_REGNUM]); |
1b1d3794 | 2609 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2610 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2611 | } |
2612 | } | |
2613 | ||
2614 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2615 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2616 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2617 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2618 | { | |
c5aa993b | 2619 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2620 | { |
da50a4b7 | 2621 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2622 | break; |
2623 | } | |
c5aa993b | 2624 | } |
c906108c SS |
2625 | } |
2626 | } | |
2627 | ||
2628 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2629 | we basically have to look at symbol information for the function | |
2630 | that we stopped in, which tells us *which* register (if any) is | |
2631 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2632 | the frame itself is at. |
c906108c SS |
2633 | |
2634 | This presents a problem when trying to examine a stack in memory | |
2635 | (that isn't executing at the moment), using the "frame" command. We | |
2636 | don't have a PC, nor do we have any registers except SP. | |
2637 | ||
2638 | This routine takes two arguments, SP and PC, and tries to make the | |
2639 | cached frames look as if these two arguments defined a frame on the | |
2640 | cache. This allows the rest of info frame to extract the important | |
2641 | arguments without difficulty. */ | |
2642 | ||
2643 | struct frame_info * | |
acdb74a0 | 2644 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2645 | { |
2646 | if (argc != 2) | |
2647 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2648 | ||
2649 | return create_new_frame (argv[0], argv[1]); | |
2650 | } | |
2651 | ||
f09ded24 AC |
2652 | /* According to the current ABI, should the type be passed in a |
2653 | floating-point register (assuming that there is space)? When there | |
2654 | is no FPU, FP are not even considered as possibile candidates for | |
2655 | FP registers and, consequently this returns false - forces FP | |
2656 | arguments into integer registers. */ | |
2657 | ||
2658 | static int | |
2659 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2660 | { | |
2661 | return ((typecode == TYPE_CODE_FLT | |
2662 | || (MIPS_EABI | |
6d82d43b AC |
2663 | && (typecode == TYPE_CODE_STRUCT |
2664 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2665 | && TYPE_NFIELDS (arg_type) == 1 |
2666 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2667 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2668 | } |
2669 | ||
49e790b0 DJ |
2670 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2671 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2672 | ||
2673 | static int | |
2674 | mips_type_needs_double_align (struct type *type) | |
2675 | { | |
2676 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2677 | |
49e790b0 DJ |
2678 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2679 | return 1; | |
2680 | else if (typecode == TYPE_CODE_STRUCT) | |
2681 | { | |
2682 | if (TYPE_NFIELDS (type) < 1) | |
2683 | return 0; | |
2684 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2685 | } | |
2686 | else if (typecode == TYPE_CODE_UNION) | |
2687 | { | |
361d1df0 | 2688 | int i, n; |
49e790b0 DJ |
2689 | |
2690 | n = TYPE_NFIELDS (type); | |
2691 | for (i = 0; i < n; i++) | |
2692 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2693 | return 1; | |
2694 | return 0; | |
2695 | } | |
2696 | return 0; | |
2697 | } | |
2698 | ||
dc604539 AC |
2699 | /* Adjust the address downward (direction of stack growth) so that it |
2700 | is correctly aligned for a new stack frame. */ | |
2701 | static CORE_ADDR | |
2702 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2703 | { | |
5b03f266 | 2704 | return align_down (addr, 16); |
dc604539 AC |
2705 | } |
2706 | ||
6d82d43b AC |
2707 | /* Determine how a return value is stored within the MIPS register |
2708 | file, given the return type `valtype'. */ | |
2709 | ||
2710 | struct return_value_word | |
2711 | { | |
2712 | int len; | |
2713 | int reg; | |
2714 | int reg_offset; | |
2715 | int buf_offset; | |
2716 | }; | |
2717 | ||
2718 | static void | |
2719 | return_value_location (struct type *valtype, | |
2720 | struct return_value_word *hi, | |
2721 | struct return_value_word *lo) | |
2722 | { | |
2723 | int len = TYPE_LENGTH (valtype); | |
2724 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2725 | ||
2726 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
2727 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
2728 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
2729 | { | |
2730 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2731 | { | |
2732 | /* We need to break a 64bit float in two 32 bit halves and | |
2733 | spread them across a floating-point register pair. */ | |
2734 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
2735 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
2736 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2737 | && register_size (current_gdbarch, | |
2738 | mips_regnum (current_gdbarch)-> | |
2739 | fp0) == 8) ? 4 : 0); | |
2740 | hi->reg_offset = lo->reg_offset; | |
2741 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
2742 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
2743 | lo->len = 4; | |
2744 | hi->len = 4; | |
2745 | } | |
2746 | else | |
2747 | { | |
2748 | /* The floating point value fits in a single floating-point | |
2749 | register. */ | |
2750 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2751 | && register_size (current_gdbarch, | |
2752 | mips_regnum (current_gdbarch)-> | |
2753 | fp0) == 8 | |
2754 | && len == 4) ? 4 : 0); | |
2755 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
2756 | lo->len = len; | |
2757 | lo->buf_offset = 0; | |
2758 | hi->len = 0; | |
2759 | hi->reg_offset = 0; | |
2760 | hi->buf_offset = 0; | |
2761 | hi->reg = 0; | |
2762 | } | |
2763 | } | |
2764 | else | |
2765 | { | |
2766 | /* Locate a result possibly spread across two registers. */ | |
2767 | int regnum = 2; | |
2768 | lo->reg = regnum + 0; | |
2769 | hi->reg = regnum + 1; | |
2770 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2771 | && len < mips_saved_regsize (tdep)) | |
2772 | { | |
2773 | /* "un-left-justify" the value in the low register */ | |
2774 | lo->reg_offset = mips_saved_regsize (tdep) - len; | |
2775 | lo->len = len; | |
2776 | hi->reg_offset = 0; | |
2777 | hi->len = 0; | |
2778 | } | |
2779 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_saved_regsize (tdep) /* odd-size structs */ | |
2780 | && len < mips_saved_regsize (tdep) * 2 | |
2781 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
2782 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
2783 | { | |
2784 | /* "un-left-justify" the value spread across two registers. */ | |
2785 | lo->reg_offset = 2 * mips_saved_regsize (tdep) - len; | |
2786 | lo->len = mips_saved_regsize (tdep) - lo->reg_offset; | |
2787 | hi->reg_offset = 0; | |
2788 | hi->len = len - lo->len; | |
2789 | } | |
2790 | else | |
2791 | { | |
2792 | /* Only perform a partial copy of the second register. */ | |
2793 | lo->reg_offset = 0; | |
2794 | hi->reg_offset = 0; | |
2795 | if (len > mips_saved_regsize (tdep)) | |
2796 | { | |
2797 | lo->len = mips_saved_regsize (tdep); | |
2798 | hi->len = len - mips_saved_regsize (tdep); | |
2799 | } | |
2800 | else | |
2801 | { | |
2802 | lo->len = len; | |
2803 | hi->len = 0; | |
2804 | } | |
2805 | } | |
2806 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2807 | && register_size (current_gdbarch, regnum) == 8 | |
2808 | && mips_saved_regsize (tdep) == 4) | |
2809 | { | |
2810 | /* Account for the fact that only the least-signficant part | |
2811 | of the register is being used */ | |
2812 | lo->reg_offset += 4; | |
2813 | hi->reg_offset += 4; | |
2814 | } | |
2815 | lo->buf_offset = 0; | |
2816 | hi->buf_offset = lo->len; | |
2817 | } | |
2818 | } | |
2819 | ||
2820 | /* Should call_function allocate stack space for a struct return? */ | |
2821 | ||
2822 | static int | |
2823 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
2824 | { | |
2825 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2826 | return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)); | |
2827 | } | |
2828 | ||
2829 | /* Should call_function pass struct by reference? | |
2830 | For each architecture, structs are passed either by | |
2831 | value or by reference, depending on their size. */ | |
2832 | ||
2833 | static int | |
2834 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
2835 | { | |
2836 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
2837 | int len = TYPE_LENGTH (check_typedef (type)); | |
2838 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2839 | ||
2840 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2841 | return (len > mips_saved_regsize (tdep)); | |
2842 | ||
2843 | return 0; | |
2844 | } | |
2845 | ||
f7ab6ec6 | 2846 | static CORE_ADDR |
25ab4790 | 2847 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
2848 | struct regcache *regcache, CORE_ADDR bp_addr, |
2849 | int nargs, struct value **args, CORE_ADDR sp, | |
2850 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2851 | { |
2852 | int argreg; | |
2853 | int float_argreg; | |
2854 | int argnum; | |
2855 | int len = 0; | |
2856 | int stack_offset = 0; | |
480d3dd2 | 2857 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c906108c | 2858 | |
25ab4790 AC |
2859 | /* For shared libraries, "t9" needs to point at the function |
2860 | address. */ | |
2861 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2862 | ||
2863 | /* Set the return address register to point to the entry point of | |
2864 | the program, where a breakpoint lies in wait. */ | |
2865 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2866 | ||
c906108c | 2867 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2868 | are properly aligned. The stack has to be at least 64-bit |
2869 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2870 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2871 | aligned, so we round to this widest known alignment. */ | |
2872 | ||
5b03f266 AC |
2873 | sp = align_down (sp, 16); |
2874 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2875 | |
46e0f506 | 2876 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2877 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2878 | passed in registers, but that's OK. */ |
c906108c | 2879 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 2880 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 2881 | mips_stack_argsize (tdep)); |
5b03f266 | 2882 | sp -= align_up (len, 16); |
c906108c | 2883 | |
9ace0497 | 2884 | if (mips_debug) |
6d82d43b | 2885 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2886 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2887 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2888 | |
c906108c SS |
2889 | /* Initialize the integer and float register pointers. */ |
2890 | argreg = A0_REGNUM; | |
56cea623 | 2891 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2892 | |
46e0f506 | 2893 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2894 | if (struct_return) |
9ace0497 AC |
2895 | { |
2896 | if (mips_debug) | |
2897 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2898 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2899 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2900 | write_register (argreg++, struct_addr); |
2901 | } | |
c906108c SS |
2902 | |
2903 | /* Now load as many as possible of the first arguments into | |
2904 | registers, and push the rest onto the stack. Loop thru args | |
2905 | from first to last. */ | |
2906 | for (argnum = 0; argnum < nargs; argnum++) | |
2907 | { | |
2908 | char *val; | |
d9d9c31f | 2909 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2910 | struct value *arg = args[argnum]; |
c906108c SS |
2911 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2912 | int len = TYPE_LENGTH (arg_type); | |
2913 | enum type_code typecode = TYPE_CODE (arg_type); | |
2914 | ||
9ace0497 AC |
2915 | if (mips_debug) |
2916 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2917 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2918 | argnum + 1, len, (int) typecode); |
9ace0497 | 2919 | |
c906108c | 2920 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2921 | reference. */ |
480d3dd2 | 2922 | if (len > mips_saved_regsize (tdep) |
9ace0497 | 2923 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2924 | { |
480d3dd2 AC |
2925 | store_unsigned_integer (valbuf, mips_saved_regsize (tdep), |
2926 | VALUE_ADDRESS (arg)); | |
c906108c | 2927 | typecode = TYPE_CODE_PTR; |
480d3dd2 | 2928 | len = mips_saved_regsize (tdep); |
c906108c | 2929 | val = valbuf; |
9ace0497 AC |
2930 | if (mips_debug) |
2931 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2932 | } |
2933 | else | |
c5aa993b | 2934 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2935 | |
2936 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2937 | even-numbered floating point register. Round the FP register |
2938 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2939 | left. Non MIPS_EABI targets also pass the FP in the integer |
2940 | registers so also round up normal registers. */ | |
6d82d43b | 2941 | if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2942 | { |
2943 | if ((float_argreg & 1)) | |
2944 | float_argreg++; | |
2945 | } | |
c906108c SS |
2946 | |
2947 | /* Floating point arguments passed in registers have to be | |
2948 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2949 | are passed in register pairs; the even register gets |
2950 | the low word, and the odd register gets the high word. | |
2951 | On non-EABI processors, the first two floating point arguments are | |
2952 | also copied to general registers, because MIPS16 functions | |
2953 | don't use float registers for arguments. This duplication of | |
2954 | arguments in general registers can't hurt non-MIPS16 functions | |
2955 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2956 | /* MIPS_EABI squeezes a struct that contains a single floating |
2957 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2958 | stack. */ |
f09ded24 AC |
2959 | if (fp_register_arg_p (typecode, arg_type) |
2960 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2961 | { |
2962 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2963 | { | |
d7449b42 | 2964 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2965 | unsigned long regval; |
2966 | ||
2967 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2968 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2969 | if (mips_debug) |
acdb74a0 | 2970 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2971 | float_argreg, phex (regval, 4)); |
c906108c | 2972 | write_register (float_argreg++, regval); |
c906108c SS |
2973 | |
2974 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2975 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2976 | if (mips_debug) |
acdb74a0 | 2977 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2978 | float_argreg, phex (regval, 4)); |
c906108c | 2979 | write_register (float_argreg++, regval); |
c906108c SS |
2980 | } |
2981 | else | |
2982 | { | |
2983 | /* This is a floating point value that fits entirely | |
2984 | in a single register. */ | |
53a5351d | 2985 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2986 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2987 | LONGEST regval = extract_unsigned_integer (val, len); |
2988 | if (mips_debug) | |
acdb74a0 | 2989 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2990 | float_argreg, phex (regval, len)); |
c906108c | 2991 | write_register (float_argreg++, regval); |
c906108c SS |
2992 | } |
2993 | } | |
2994 | else | |
2995 | { | |
2996 | /* Copy the argument to general registers or the stack in | |
2997 | register-sized pieces. Large arguments are split between | |
2998 | registers and stack. */ | |
4246e332 AC |
2999 | /* Note: structs whose size is not a multiple of |
3000 | mips_regsize() are treated specially: Irix cc passes them | |
3001 | in registers where gcc sometimes puts them on the stack. | |
3002 | For maximum compatibility, we will put them in both | |
3003 | places. */ | |
480d3dd2 AC |
3004 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3005 | && (len % mips_saved_regsize (tdep) != 0)); | |
46e0f506 | 3006 | |
f09ded24 | 3007 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3008 | register are only written to memory. */ |
c906108c SS |
3009 | while (len > 0) |
3010 | { | |
ebafbe83 | 3011 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3012 | int stack_used_p = 0; |
480d3dd2 AC |
3013 | int partial_len = (len < mips_saved_regsize (tdep) |
3014 | ? len : mips_saved_regsize (tdep)); | |
c906108c | 3015 | |
acdb74a0 AC |
3016 | if (mips_debug) |
3017 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3018 | partial_len); | |
3019 | ||
566f0f7a | 3020 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3021 | if (argreg > MIPS_LAST_ARG_REGNUM |
3022 | || odd_sized_struct | |
3023 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3024 | { |
c906108c SS |
3025 | /* Should shorter than int integer values be |
3026 | promoted to int before being stored? */ | |
c906108c | 3027 | int longword_offset = 0; |
9ace0497 | 3028 | CORE_ADDR addr; |
566f0f7a | 3029 | stack_used_p = 1; |
d7449b42 | 3030 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3031 | { |
480d3dd2 AC |
3032 | if (mips_stack_argsize (tdep) == 8 |
3033 | && (typecode == TYPE_CODE_INT | |
3034 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3035 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 AC |
3036 | longword_offset = mips_stack_argsize (tdep) - len; |
3037 | else if ((typecode == TYPE_CODE_STRUCT | |
3038 | || typecode == TYPE_CODE_UNION) | |
3039 | && (TYPE_LENGTH (arg_type) | |
3040 | < mips_stack_argsize (tdep))) | |
3041 | longword_offset = mips_stack_argsize (tdep) - len; | |
7a292a7a | 3042 | } |
c5aa993b | 3043 | |
9ace0497 AC |
3044 | if (mips_debug) |
3045 | { | |
cb3d25d1 MS |
3046 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3047 | paddr_nz (stack_offset)); | |
3048 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3049 | paddr_nz (longword_offset)); | |
9ace0497 | 3050 | } |
361d1df0 | 3051 | |
9ace0497 AC |
3052 | addr = sp + stack_offset + longword_offset; |
3053 | ||
3054 | if (mips_debug) | |
3055 | { | |
3056 | int i; | |
6d82d43b | 3057 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3058 | paddr_nz (addr)); |
9ace0497 AC |
3059 | for (i = 0; i < partial_len; i++) |
3060 | { | |
6d82d43b | 3061 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3062 | val[i] & 0xff); |
9ace0497 AC |
3063 | } |
3064 | } | |
3065 | write_memory (addr, val, partial_len); | |
c906108c SS |
3066 | } |
3067 | ||
f09ded24 AC |
3068 | /* Note!!! This is NOT an else clause. Odd sized |
3069 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3070 | arguments will not. */ |
566f0f7a | 3071 | /* Write this portion of the argument to a general |
6d82d43b | 3072 | purpose register. */ |
f09ded24 AC |
3073 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3074 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3075 | { |
6d82d43b AC |
3076 | LONGEST regval = |
3077 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3078 | |
9ace0497 | 3079 | if (mips_debug) |
acdb74a0 | 3080 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3081 | argreg, |
6d82d43b AC |
3082 | phex (regval, |
3083 | mips_saved_regsize (tdep))); | |
c906108c SS |
3084 | write_register (argreg, regval); |
3085 | argreg++; | |
c906108c | 3086 | } |
c5aa993b | 3087 | |
c906108c SS |
3088 | len -= partial_len; |
3089 | val += partial_len; | |
3090 | ||
566f0f7a | 3091 | /* Compute the the offset into the stack at which we |
6d82d43b | 3092 | will copy the next parameter. |
566f0f7a | 3093 | |
566f0f7a | 3094 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3095 | only needs to be adjusted when it has been used. */ |
c906108c | 3096 | |
46e0f506 | 3097 | if (stack_used_p) |
480d3dd2 AC |
3098 | stack_offset += align_up (partial_len, |
3099 | mips_stack_argsize (tdep)); | |
c906108c SS |
3100 | } |
3101 | } | |
9ace0497 AC |
3102 | if (mips_debug) |
3103 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3104 | } |
3105 | ||
310e9b6a AC |
3106 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3107 | ||
0f71a2f6 JM |
3108 | /* Return adjusted stack pointer. */ |
3109 | return sp; | |
3110 | } | |
3111 | ||
6d82d43b AC |
3112 | /* Given a return value in `regbuf' with a type `valtype', extract and |
3113 | copy its value into `valbuf'. */ | |
3114 | ||
3115 | static void | |
3116 | mips_eabi_extract_return_value (struct type *valtype, | |
3117 | char regbuf[], char *valbuf) | |
3118 | { | |
3119 | struct return_value_word lo; | |
3120 | struct return_value_word hi; | |
3121 | return_value_location (valtype, &hi, &lo); | |
3122 | ||
3123 | memcpy (valbuf + lo.buf_offset, | |
3124 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
3125 | lo.reg_offset, lo.len); | |
3126 | ||
3127 | if (hi.len > 0) | |
3128 | memcpy (valbuf + hi.buf_offset, | |
3129 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3130 | hi.reg_offset, hi.len); | |
3131 | } | |
3132 | ||
3133 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3134 | value into the appropriate register. */ | |
3135 | ||
3136 | static void | |
3137 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3138 | { | |
3139 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3140 | struct return_value_word lo; | |
3141 | struct return_value_word hi; | |
3142 | return_value_location (valtype, &hi, &lo); | |
3143 | ||
3144 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3145 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3146 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3147 | raw_buffer, register_size (current_gdbarch, | |
3148 | lo.reg)); | |
3149 | ||
3150 | if (hi.len > 0) | |
3151 | { | |
3152 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3153 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3154 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3155 | raw_buffer, | |
3156 | register_size (current_gdbarch, | |
3157 | hi.reg)); | |
3158 | } | |
3159 | } | |
3160 | ||
3161 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3162 | |
f7ab6ec6 | 3163 | static CORE_ADDR |
25ab4790 | 3164 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
3165 | struct regcache *regcache, CORE_ADDR bp_addr, |
3166 | int nargs, struct value **args, CORE_ADDR sp, | |
3167 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3168 | { |
3169 | int argreg; | |
3170 | int float_argreg; | |
3171 | int argnum; | |
3172 | int len = 0; | |
3173 | int stack_offset = 0; | |
480d3dd2 | 3174 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cb3d25d1 | 3175 | |
25ab4790 AC |
3176 | /* For shared libraries, "t9" needs to point at the function |
3177 | address. */ | |
3178 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3179 | ||
3180 | /* Set the return address register to point to the entry point of | |
3181 | the program, where a breakpoint lies in wait. */ | |
3182 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3183 | ||
cb3d25d1 MS |
3184 | /* First ensure that the stack and structure return address (if any) |
3185 | are properly aligned. The stack has to be at least 64-bit | |
3186 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3187 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3188 | aligned, so we round to this widest known alignment. */ | |
3189 | ||
5b03f266 AC |
3190 | sp = align_down (sp, 16); |
3191 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3192 | |
3193 | /* Now make space on the stack for the args. */ | |
3194 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3195 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3196 | mips_stack_argsize (tdep)); |
5b03f266 | 3197 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3198 | |
3199 | if (mips_debug) | |
6d82d43b | 3200 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3201 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3202 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3203 | |
3204 | /* Initialize the integer and float register pointers. */ | |
3205 | argreg = A0_REGNUM; | |
56cea623 | 3206 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3207 | |
46e0f506 | 3208 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3209 | if (struct_return) |
3210 | { | |
3211 | if (mips_debug) | |
3212 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3213 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3214 | argreg, paddr_nz (struct_addr)); |
3215 | write_register (argreg++, struct_addr); | |
3216 | } | |
3217 | ||
3218 | /* Now load as many as possible of the first arguments into | |
3219 | registers, and push the rest onto the stack. Loop thru args | |
3220 | from first to last. */ | |
3221 | for (argnum = 0; argnum < nargs; argnum++) | |
3222 | { | |
3223 | char *val; | |
d9d9c31f | 3224 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3225 | struct value *arg = args[argnum]; |
3226 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3227 | int len = TYPE_LENGTH (arg_type); | |
3228 | enum type_code typecode = TYPE_CODE (arg_type); | |
3229 | ||
3230 | if (mips_debug) | |
3231 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3232 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3233 | argnum + 1, len, (int) typecode); |
3234 | ||
3235 | val = (char *) VALUE_CONTENTS (arg); | |
3236 | ||
3237 | if (fp_register_arg_p (typecode, arg_type) | |
3238 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3239 | { | |
3240 | /* This is a floating point value that fits entirely | |
3241 | in a single register. */ | |
3242 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3243 | above to ensure that it is even register aligned. */ | |
3244 | LONGEST regval = extract_unsigned_integer (val, len); | |
3245 | if (mips_debug) | |
3246 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3247 | float_argreg, phex (regval, len)); | |
3248 | write_register (float_argreg++, regval); | |
3249 | ||
3250 | if (mips_debug) | |
3251 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3252 | argreg, phex (regval, len)); | |
3253 | write_register (argreg, regval); | |
3254 | argreg += 1; | |
3255 | } | |
3256 | else | |
3257 | { | |
3258 | /* Copy the argument to general registers or the stack in | |
3259 | register-sized pieces. Large arguments are split between | |
3260 | registers and stack. */ | |
4246e332 AC |
3261 | /* Note: structs whose size is not a multiple of |
3262 | mips_regsize() are treated specially: Irix cc passes them | |
3263 | in registers where gcc sometimes puts them on the stack. | |
3264 | For maximum compatibility, we will put them in both | |
3265 | places. */ | |
480d3dd2 AC |
3266 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3267 | && (len % mips_saved_regsize (tdep) != 0)); | |
cb3d25d1 | 3268 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3269 | register are only written to memory. */ |
cb3d25d1 MS |
3270 | while (len > 0) |
3271 | { | |
3272 | /* Rememer if the argument was written to the stack. */ | |
3273 | int stack_used_p = 0; | |
480d3dd2 AC |
3274 | int partial_len = (len < mips_saved_regsize (tdep) |
3275 | ? len : mips_saved_regsize (tdep)); | |
cb3d25d1 MS |
3276 | |
3277 | if (mips_debug) | |
3278 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3279 | partial_len); | |
3280 | ||
3281 | /* Write this portion of the argument to the stack. */ | |
3282 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3283 | || odd_sized_struct | |
3284 | || fp_register_arg_p (typecode, arg_type)) | |
3285 | { | |
3286 | /* Should shorter than int integer values be | |
3287 | promoted to int before being stored? */ | |
3288 | int longword_offset = 0; | |
3289 | CORE_ADDR addr; | |
3290 | stack_used_p = 1; | |
3291 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3292 | { | |
480d3dd2 AC |
3293 | if (mips_stack_argsize (tdep) == 8 |
3294 | && (typecode == TYPE_CODE_INT | |
3295 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3296 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 | 3297 | longword_offset = mips_stack_argsize (tdep) - len; |
cb3d25d1 MS |
3298 | } |
3299 | ||
3300 | if (mips_debug) | |
3301 | { | |
3302 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3303 | paddr_nz (stack_offset)); | |
3304 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3305 | paddr_nz (longword_offset)); | |
3306 | } | |
3307 | ||
3308 | addr = sp + stack_offset + longword_offset; | |
3309 | ||
3310 | if (mips_debug) | |
3311 | { | |
3312 | int i; | |
6d82d43b | 3313 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3314 | paddr_nz (addr)); |
3315 | for (i = 0; i < partial_len; i++) | |
3316 | { | |
6d82d43b | 3317 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3318 | val[i] & 0xff); |
3319 | } | |
3320 | } | |
3321 | write_memory (addr, val, partial_len); | |
3322 | } | |
3323 | ||
3324 | /* Note!!! This is NOT an else clause. Odd sized | |
3325 | structs may go thru BOTH paths. Floating point | |
3326 | arguments will not. */ | |
3327 | /* Write this portion of the argument to a general | |
6d82d43b | 3328 | purpose register. */ |
cb3d25d1 MS |
3329 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3330 | && !fp_register_arg_p (typecode, arg_type)) | |
3331 | { | |
6d82d43b AC |
3332 | LONGEST regval = |
3333 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3334 | |
3335 | /* A non-floating-point argument being passed in a | |
3336 | general register. If a struct or union, and if | |
3337 | the remaining length is smaller than the register | |
3338 | size, we have to adjust the register value on | |
3339 | big endian targets. | |
3340 | ||
3341 | It does not seem to be necessary to do the | |
3342 | same for integral types. | |
3343 | ||
3344 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3345 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3346 | mips_saved_regsize(), generates a left shift as |
cb3d25d1 MS |
3347 | part of storing the argument in a register a |
3348 | register (the left shift isn't generated when | |
480d3dd2 AC |
3349 | sizeof (struct) >= mips_saved_regsize()). Since |
3350 | it is quite possible that this is GCC | |
3351 | contradicting the LE/O32 ABI, GDB has not been | |
3352 | adjusted to accommodate this. Either someone | |
3353 | needs to demonstrate that the LE/O32 ABI | |
3354 | specifies such a left shift OR this new ABI gets | |
3355 | identified as such and GDB gets tweaked | |
3356 | accordingly. */ | |
cb3d25d1 MS |
3357 | |
3358 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
480d3dd2 | 3359 | && partial_len < mips_saved_regsize (tdep) |
cb3d25d1 MS |
3360 | && (typecode == TYPE_CODE_STRUCT || |
3361 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3362 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
cb3d25d1 MS |
3363 | TARGET_CHAR_BIT); |
3364 | ||
3365 | if (mips_debug) | |
3366 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3367 | argreg, | |
6d82d43b AC |
3368 | phex (regval, |
3369 | mips_saved_regsize (tdep))); | |
cb3d25d1 MS |
3370 | write_register (argreg, regval); |
3371 | argreg++; | |
3372 | } | |
3373 | ||
3374 | len -= partial_len; | |
3375 | val += partial_len; | |
3376 | ||
3377 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3378 | will copy the next parameter. |
cb3d25d1 MS |
3379 | |
3380 | In N32 (N64?), the stack_offset only needs to be | |
3381 | adjusted when it has been used. */ | |
3382 | ||
3383 | if (stack_used_p) | |
480d3dd2 AC |
3384 | stack_offset += align_up (partial_len, |
3385 | mips_stack_argsize (tdep)); | |
cb3d25d1 MS |
3386 | } |
3387 | } | |
3388 | if (mips_debug) | |
3389 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3390 | } | |
3391 | ||
310e9b6a AC |
3392 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3393 | ||
cb3d25d1 MS |
3394 | /* Return adjusted stack pointer. */ |
3395 | return sp; | |
3396 | } | |
3397 | ||
6d82d43b AC |
3398 | static enum return_value_convention |
3399 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3400 | struct type *type, struct regcache *regcache, | |
3401 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3402 | { |
6d82d43b AC |
3403 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3404 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3405 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3406 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
3407 | || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)) | |
3408 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3409 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3410 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3411 | { | |
3412 | /* A floating-point value belongs in the least significant part | |
3413 | of FP0. */ | |
3414 | if (mips_debug) | |
3415 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3416 | mips_xfer_register (regcache, | |
3417 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3418 | TYPE_LENGTH (type), | |
3419 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3420 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3421 | } | |
3422 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3423 | && TYPE_NFIELDS (type) <= 2 | |
3424 | && TYPE_NFIELDS (type) >= 1 | |
3425 | && ((TYPE_NFIELDS (type) == 1 | |
3426 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3427 | == TYPE_CODE_FLT)) | |
3428 | || (TYPE_NFIELDS (type) == 2 | |
3429 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3430 | == TYPE_CODE_FLT) | |
3431 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3432 | == TYPE_CODE_FLT))) | |
3433 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3434 | { | |
3435 | /* A struct that contains one or two floats. Each value is part | |
3436 | in the least significant part of their floating point | |
3437 | register.. */ | |
3438 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3439 | int regnum; | |
3440 | int field; | |
3441 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3442 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3443 | { | |
3444 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3445 | / TARGET_CHAR_BIT); | |
3446 | if (mips_debug) | |
3447 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3448 | offset); | |
3449 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3450 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3451 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3452 | } | |
3453 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3454 | } | |
3455 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3456 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3457 | { | |
3458 | /* A structure or union. Extract the left justified value, | |
3459 | regardless of the byte order. I.e. DO NOT USE | |
3460 | mips_xfer_lower. */ | |
3461 | int offset; | |
3462 | int regnum; | |
3463 | for (offset = 0, regnum = V0_REGNUM; | |
3464 | offset < TYPE_LENGTH (type); | |
3465 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3466 | { | |
3467 | int xfer = register_size (current_gdbarch, regnum); | |
3468 | if (offset + xfer > TYPE_LENGTH (type)) | |
3469 | xfer = TYPE_LENGTH (type) - offset; | |
3470 | if (mips_debug) | |
3471 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3472 | offset, xfer, regnum); | |
3473 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3474 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3475 | } | |
3476 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | /* A scalar extract each part but least-significant-byte | |
3481 | justified. */ | |
3482 | int offset; | |
3483 | int regnum; | |
3484 | for (offset = 0, regnum = V0_REGNUM; | |
3485 | offset < TYPE_LENGTH (type); | |
3486 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3487 | { | |
3488 | int xfer = register_size (current_gdbarch, regnum); | |
3489 | int pos = 0; | |
3490 | if (offset + xfer > TYPE_LENGTH (type)) | |
3491 | xfer = TYPE_LENGTH (type) - offset; | |
3492 | if (mips_debug) | |
3493 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3494 | offset, xfer, regnum); | |
3495 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3496 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3497 | } | |
3498 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3499 | } | |
3500 | } | |
3501 | ||
3502 | /* O32 ABI stuff. */ | |
3503 | ||
3504 | static CORE_ADDR | |
3505 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
3506 | struct regcache *regcache, CORE_ADDR bp_addr, | |
3507 | int nargs, struct value **args, CORE_ADDR sp, | |
3508 | int struct_return, CORE_ADDR struct_addr) | |
3509 | { | |
3510 | int argreg; | |
3511 | int float_argreg; | |
3512 | int argnum; | |
3513 | int len = 0; | |
3514 | int stack_offset = 0; | |
3515 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3516 | ||
3517 | /* For shared libraries, "t9" needs to point at the function | |
3518 | address. */ | |
3519 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3520 | ||
3521 | /* Set the return address register to point to the entry point of | |
3522 | the program, where a breakpoint lies in wait. */ | |
3523 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3524 | ||
3525 | /* First ensure that the stack and structure return address (if any) | |
3526 | are properly aligned. The stack has to be at least 64-bit | |
3527 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3528 | aligned. For n32 and n64, stack frames need to be 128-bit |
3529 | aligned, so we round to this widest known alignment. */ | |
3530 | ||
5b03f266 AC |
3531 | sp = align_down (sp, 16); |
3532 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3533 | |
3534 | /* Now make space on the stack for the args. */ | |
3535 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3536 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3537 | mips_stack_argsize (tdep)); |
5b03f266 | 3538 | sp -= align_up (len, 16); |
ebafbe83 MS |
3539 | |
3540 | if (mips_debug) | |
6d82d43b | 3541 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3542 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3543 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3544 | |
3545 | /* Initialize the integer and float register pointers. */ | |
3546 | argreg = A0_REGNUM; | |
56cea623 | 3547 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3548 | |
bcb0cc15 | 3549 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3550 | if (struct_return) |
3551 | { | |
3552 | if (mips_debug) | |
3553 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3554 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3555 | argreg, paddr_nz (struct_addr)); |
3556 | write_register (argreg++, struct_addr); | |
480d3dd2 | 3557 | stack_offset += mips_stack_argsize (tdep); |
ebafbe83 MS |
3558 | } |
3559 | ||
3560 | /* Now load as many as possible of the first arguments into | |
3561 | registers, and push the rest onto the stack. Loop thru args | |
3562 | from first to last. */ | |
3563 | for (argnum = 0; argnum < nargs; argnum++) | |
3564 | { | |
3565 | char *val; | |
d9d9c31f | 3566 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3567 | struct value *arg = args[argnum]; |
3568 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3569 | int len = TYPE_LENGTH (arg_type); | |
3570 | enum type_code typecode = TYPE_CODE (arg_type); | |
3571 | ||
3572 | if (mips_debug) | |
3573 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3574 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3575 | argnum + 1, len, (int) typecode); |
3576 | ||
3577 | val = (char *) VALUE_CONTENTS (arg); | |
3578 | ||
3579 | /* 32-bit ABIs always start floating point arguments in an | |
3580 | even-numbered floating point register. Round the FP register | |
3581 | up before the check to see if there are any FP registers | |
3582 | left. O32/O64 targets also pass the FP in the integer | |
3583 | registers so also round up normal registers. */ | |
6d82d43b | 3584 | if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3585 | { |
3586 | if ((float_argreg & 1)) | |
3587 | float_argreg++; | |
3588 | } | |
3589 | ||
3590 | /* Floating point arguments passed in registers have to be | |
3591 | treated specially. On 32-bit architectures, doubles | |
3592 | are passed in register pairs; the even register gets | |
3593 | the low word, and the odd register gets the high word. | |
3594 | On O32/O64, the first two floating point arguments are | |
3595 | also copied to general registers, because MIPS16 functions | |
3596 | don't use float registers for arguments. This duplication of | |
3597 | arguments in general registers can't hurt non-MIPS16 functions | |
3598 | because those registers are normally skipped. */ | |
3599 | ||
3600 | if (fp_register_arg_p (typecode, arg_type) | |
3601 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3602 | { | |
3603 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3604 | { | |
3605 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3606 | unsigned long regval; | |
3607 | ||
3608 | /* Write the low word of the double to the even register(s). */ | |
3609 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3610 | if (mips_debug) | |
3611 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3612 | float_argreg, phex (regval, 4)); | |
3613 | write_register (float_argreg++, regval); | |
3614 | if (mips_debug) | |
3615 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3616 | argreg, phex (regval, 4)); | |
3617 | write_register (argreg++, regval); | |
3618 | ||
3619 | /* Write the high word of the double to the odd register(s). */ | |
3620 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3621 | if (mips_debug) | |
3622 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3623 | float_argreg, phex (regval, 4)); | |
3624 | write_register (float_argreg++, regval); | |
3625 | ||
3626 | if (mips_debug) | |
3627 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3628 | argreg, phex (regval, 4)); | |
3629 | write_register (argreg++, regval); | |
3630 | } | |
3631 | else | |
3632 | { | |
3633 | /* This is a floating point value that fits entirely | |
3634 | in a single register. */ | |
3635 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3636 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3637 | LONGEST regval = extract_unsigned_integer (val, len); |
3638 | if (mips_debug) | |
3639 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3640 | float_argreg, phex (regval, len)); | |
3641 | write_register (float_argreg++, regval); | |
3642 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3643 | registers for each argument. The below is (my |
3644 | guess) to ensure that the corresponding integer | |
3645 | register has reserved the same space. */ | |
46cac009 AC |
3646 | if (mips_debug) |
3647 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3648 | argreg, phex (regval, len)); | |
3649 | write_register (argreg, regval); | |
3650 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3651 | } | |
3652 | /* Reserve space for the FP register. */ | |
480d3dd2 | 3653 | stack_offset += align_up (len, mips_stack_argsize (tdep)); |
46cac009 AC |
3654 | } |
3655 | else | |
3656 | { | |
3657 | /* Copy the argument to general registers or the stack in | |
3658 | register-sized pieces. Large arguments are split between | |
3659 | registers and stack. */ | |
4246e332 AC |
3660 | /* Note: structs whose size is not a multiple of |
3661 | mips_regsize() are treated specially: Irix cc passes them | |
3662 | in registers where gcc sometimes puts them on the stack. | |
3663 | For maximum compatibility, we will put them in both | |
3664 | places. */ | |
480d3dd2 AC |
3665 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
3666 | && (len % mips_saved_regsize (tdep) != 0)); | |
46cac009 AC |
3667 | /* Structures should be aligned to eight bytes (even arg registers) |
3668 | on MIPS_ABI_O32, if their first member has double precision. */ | |
480d3dd2 | 3669 | if (mips_saved_regsize (tdep) < 8 |
46cac009 AC |
3670 | && mips_type_needs_double_align (arg_type)) |
3671 | { | |
3672 | if ((argreg & 1)) | |
6d82d43b | 3673 | argreg++; |
46cac009 AC |
3674 | } |
3675 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3676 | register are only written to memory. */ |
46cac009 AC |
3677 | while (len > 0) |
3678 | { | |
3679 | /* Remember if the argument was written to the stack. */ | |
3680 | int stack_used_p = 0; | |
480d3dd2 AC |
3681 | int partial_len = (len < mips_saved_regsize (tdep) |
3682 | ? len : mips_saved_regsize (tdep)); | |
46cac009 AC |
3683 | |
3684 | if (mips_debug) | |
3685 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3686 | partial_len); | |
3687 | ||
3688 | /* Write this portion of the argument to the stack. */ | |
3689 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3690 | || odd_sized_struct | |
3691 | || fp_register_arg_p (typecode, arg_type)) | |
3692 | { | |
3693 | /* Should shorter than int integer values be | |
3694 | promoted to int before being stored? */ | |
3695 | int longword_offset = 0; | |
3696 | CORE_ADDR addr; | |
3697 | stack_used_p = 1; | |
3698 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3699 | { | |
480d3dd2 AC |
3700 | if (mips_stack_argsize (tdep) == 8 |
3701 | && (typecode == TYPE_CODE_INT | |
3702 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3703 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 | 3704 | longword_offset = mips_stack_argsize (tdep) - len; |
46cac009 AC |
3705 | } |
3706 | ||
3707 | if (mips_debug) | |
3708 | { | |
3709 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3710 | paddr_nz (stack_offset)); | |
3711 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3712 | paddr_nz (longword_offset)); | |
3713 | } | |
3714 | ||
3715 | addr = sp + stack_offset + longword_offset; | |
3716 | ||
3717 | if (mips_debug) | |
3718 | { | |
3719 | int i; | |
6d82d43b | 3720 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3721 | paddr_nz (addr)); |
3722 | for (i = 0; i < partial_len; i++) | |
3723 | { | |
6d82d43b | 3724 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3725 | val[i] & 0xff); |
3726 | } | |
3727 | } | |
3728 | write_memory (addr, val, partial_len); | |
3729 | } | |
3730 | ||
3731 | /* Note!!! This is NOT an else clause. Odd sized | |
3732 | structs may go thru BOTH paths. Floating point | |
3733 | arguments will not. */ | |
3734 | /* Write this portion of the argument to a general | |
6d82d43b | 3735 | purpose register. */ |
46cac009 AC |
3736 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3737 | && !fp_register_arg_p (typecode, arg_type)) | |
3738 | { | |
3739 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3740 | /* Value may need to be sign extended, because |
480d3dd2 | 3741 | mips_regsize() != mips_saved_regsize(). */ |
46cac009 AC |
3742 | |
3743 | /* A non-floating-point argument being passed in a | |
3744 | general register. If a struct or union, and if | |
3745 | the remaining length is smaller than the register | |
3746 | size, we have to adjust the register value on | |
3747 | big endian targets. | |
3748 | ||
3749 | It does not seem to be necessary to do the | |
3750 | same for integral types. | |
3751 | ||
3752 | Also don't do this adjustment on O64 binaries. | |
3753 | ||
3754 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3755 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 3756 | mips_saved_regsize(), generates a left shift as |
46cac009 AC |
3757 | part of storing the argument in a register a |
3758 | register (the left shift isn't generated when | |
480d3dd2 AC |
3759 | sizeof (struct) >= mips_saved_regsize()). Since |
3760 | it is quite possible that this is GCC | |
3761 | contradicting the LE/O32 ABI, GDB has not been | |
3762 | adjusted to accommodate this. Either someone | |
3763 | needs to demonstrate that the LE/O32 ABI | |
3764 | specifies such a left shift OR this new ABI gets | |
3765 | identified as such and GDB gets tweaked | |
3766 | accordingly. */ | |
3767 | ||
3768 | if (mips_saved_regsize (tdep) < 8 | |
46cac009 | 3769 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 3770 | && partial_len < mips_saved_regsize (tdep) |
46cac009 AC |
3771 | && (typecode == TYPE_CODE_STRUCT || |
3772 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 3773 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
46cac009 AC |
3774 | TARGET_CHAR_BIT); |
3775 | ||
3776 | if (mips_debug) | |
3777 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3778 | argreg, | |
6d82d43b AC |
3779 | phex (regval, |
3780 | mips_saved_regsize (tdep))); | |
46cac009 AC |
3781 | write_register (argreg, regval); |
3782 | argreg++; | |
3783 | ||
3784 | /* Prevent subsequent floating point arguments from | |
3785 | being passed in floating point registers. */ | |
3786 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3787 | } | |
3788 | ||
3789 | len -= partial_len; | |
3790 | val += partial_len; | |
3791 | ||
3792 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3793 | will copy the next parameter. |
46cac009 | 3794 | |
6d82d43b AC |
3795 | In older ABIs, the caller reserved space for |
3796 | registers that contained arguments. This was loosely | |
3797 | refered to as their "home". Consequently, space is | |
3798 | always allocated. */ | |
46cac009 | 3799 | |
480d3dd2 AC |
3800 | stack_offset += align_up (partial_len, |
3801 | mips_stack_argsize (tdep)); | |
46cac009 AC |
3802 | } |
3803 | } | |
3804 | if (mips_debug) | |
3805 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3806 | } | |
3807 | ||
310e9b6a AC |
3808 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3809 | ||
46cac009 AC |
3810 | /* Return adjusted stack pointer. */ |
3811 | return sp; | |
3812 | } | |
3813 | ||
6d82d43b AC |
3814 | static enum return_value_convention |
3815 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3816 | struct regcache *regcache, | |
3817 | void *readbuf, const void *writebuf) | |
3818 | { | |
3819 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3820 | ||
3821 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3822 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3823 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3824 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3825 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3826 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3827 | { | |
3828 | /* A single-precision floating-point value. It fits in the | |
3829 | least significant part of FP0. */ | |
3830 | if (mips_debug) | |
3831 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3832 | mips_xfer_register (regcache, | |
3833 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3834 | TYPE_LENGTH (type), | |
3835 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3836 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3837 | } | |
3838 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3839 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3840 | { | |
3841 | /* A double-precision floating-point value. The most | |
3842 | significant part goes in FP1, and the least significant in | |
3843 | FP0. */ | |
3844 | if (mips_debug) | |
3845 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3846 | switch (TARGET_BYTE_ORDER) | |
3847 | { | |
3848 | case BFD_ENDIAN_LITTLE: | |
3849 | mips_xfer_register (regcache, | |
3850 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3851 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3852 | mips_xfer_register (regcache, | |
3853 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3854 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3855 | break; | |
3856 | case BFD_ENDIAN_BIG: | |
3857 | mips_xfer_register (regcache, | |
3858 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3859 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3860 | mips_xfer_register (regcache, | |
3861 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3862 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3863 | break; | |
3864 | default: | |
3865 | internal_error (__FILE__, __LINE__, "bad switch"); | |
3866 | } | |
3867 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3868 | } | |
3869 | #if 0 | |
3870 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3871 | && TYPE_NFIELDS (type) <= 2 | |
3872 | && TYPE_NFIELDS (type) >= 1 | |
3873 | && ((TYPE_NFIELDS (type) == 1 | |
3874 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3875 | == TYPE_CODE_FLT)) | |
3876 | || (TYPE_NFIELDS (type) == 2 | |
3877 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3878 | == TYPE_CODE_FLT) | |
3879 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3880 | == TYPE_CODE_FLT))) | |
3881 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3882 | { | |
3883 | /* A struct that contains one or two floats. Each value is part | |
3884 | in the least significant part of their floating point | |
3885 | register.. */ | |
3886 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3887 | int regnum; | |
3888 | int field; | |
3889 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3890 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3891 | { | |
3892 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3893 | / TARGET_CHAR_BIT); | |
3894 | if (mips_debug) | |
3895 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3896 | offset); | |
3897 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3898 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3899 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3900 | } | |
3901 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3902 | } | |
3903 | #endif | |
3904 | #if 0 | |
3905 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3906 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3907 | { | |
3908 | /* A structure or union. Extract the left justified value, | |
3909 | regardless of the byte order. I.e. DO NOT USE | |
3910 | mips_xfer_lower. */ | |
3911 | int offset; | |
3912 | int regnum; | |
3913 | for (offset = 0, regnum = V0_REGNUM; | |
3914 | offset < TYPE_LENGTH (type); | |
3915 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3916 | { | |
3917 | int xfer = register_size (current_gdbarch, regnum); | |
3918 | if (offset + xfer > TYPE_LENGTH (type)) | |
3919 | xfer = TYPE_LENGTH (type) - offset; | |
3920 | if (mips_debug) | |
3921 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3922 | offset, xfer, regnum); | |
3923 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3924 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3925 | } | |
3926 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3927 | } | |
3928 | #endif | |
3929 | else | |
3930 | { | |
3931 | /* A scalar extract each part but least-significant-byte | |
3932 | justified. o32 thinks registers are 4 byte, regardless of | |
3933 | the ISA. mips_stack_argsize controls this. */ | |
3934 | int offset; | |
3935 | int regnum; | |
3936 | for (offset = 0, regnum = V0_REGNUM; | |
3937 | offset < TYPE_LENGTH (type); | |
3938 | offset += mips_stack_argsize (tdep), regnum++) | |
3939 | { | |
3940 | int xfer = mips_stack_argsize (tdep); | |
3941 | int pos = 0; | |
3942 | if (offset + xfer > TYPE_LENGTH (type)) | |
3943 | xfer = TYPE_LENGTH (type) - offset; | |
3944 | if (mips_debug) | |
3945 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3946 | offset, xfer, regnum); | |
3947 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3948 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3949 | } | |
3950 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3951 | } | |
3952 | } | |
3953 | ||
3954 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3955 | ABI. */ | |
46cac009 AC |
3956 | |
3957 | static CORE_ADDR | |
25ab4790 | 3958 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
6d82d43b AC |
3959 | struct regcache *regcache, CORE_ADDR bp_addr, |
3960 | int nargs, | |
3961 | struct value **args, CORE_ADDR sp, | |
3962 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3963 | { |
3964 | int argreg; | |
3965 | int float_argreg; | |
3966 | int argnum; | |
3967 | int len = 0; | |
3968 | int stack_offset = 0; | |
480d3dd2 | 3969 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
46cac009 | 3970 | |
25ab4790 AC |
3971 | /* For shared libraries, "t9" needs to point at the function |
3972 | address. */ | |
3973 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3974 | ||
3975 | /* Set the return address register to point to the entry point of | |
3976 | the program, where a breakpoint lies in wait. */ | |
3977 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3978 | ||
46cac009 AC |
3979 | /* First ensure that the stack and structure return address (if any) |
3980 | are properly aligned. The stack has to be at least 64-bit | |
3981 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3982 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3983 | aligned, so we round to this widest known alignment. */ | |
3984 | ||
5b03f266 AC |
3985 | sp = align_down (sp, 16); |
3986 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3987 | |
3988 | /* Now make space on the stack for the args. */ | |
3989 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3990 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
480d3dd2 | 3991 | mips_stack_argsize (tdep)); |
5b03f266 | 3992 | sp -= align_up (len, 16); |
46cac009 AC |
3993 | |
3994 | if (mips_debug) | |
6d82d43b | 3995 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3996 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3997 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3998 | |
3999 | /* Initialize the integer and float register pointers. */ | |
4000 | argreg = A0_REGNUM; | |
56cea623 | 4001 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4002 | |
4003 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4004 | if (struct_return) | |
4005 | { | |
4006 | if (mips_debug) | |
4007 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4008 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4009 | argreg, paddr_nz (struct_addr)); |
4010 | write_register (argreg++, struct_addr); | |
480d3dd2 | 4011 | stack_offset += mips_stack_argsize (tdep); |
46cac009 AC |
4012 | } |
4013 | ||
4014 | /* Now load as many as possible of the first arguments into | |
4015 | registers, and push the rest onto the stack. Loop thru args | |
4016 | from first to last. */ | |
4017 | for (argnum = 0; argnum < nargs; argnum++) | |
4018 | { | |
4019 | char *val; | |
d9d9c31f | 4020 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
4021 | struct value *arg = args[argnum]; |
4022 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4023 | int len = TYPE_LENGTH (arg_type); | |
4024 | enum type_code typecode = TYPE_CODE (arg_type); | |
4025 | ||
4026 | if (mips_debug) | |
4027 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4028 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4029 | argnum + 1, len, (int) typecode); |
4030 | ||
4031 | val = (char *) VALUE_CONTENTS (arg); | |
4032 | ||
4033 | /* 32-bit ABIs always start floating point arguments in an | |
4034 | even-numbered floating point register. Round the FP register | |
4035 | up before the check to see if there are any FP registers | |
4036 | left. O32/O64 targets also pass the FP in the integer | |
4037 | registers so also round up normal registers. */ | |
6d82d43b | 4038 | if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) |
ebafbe83 MS |
4039 | { |
4040 | if ((float_argreg & 1)) | |
4041 | float_argreg++; | |
4042 | } | |
4043 | ||
4044 | /* Floating point arguments passed in registers have to be | |
4045 | treated specially. On 32-bit architectures, doubles | |
4046 | are passed in register pairs; the even register gets | |
4047 | the low word, and the odd register gets the high word. | |
4048 | On O32/O64, the first two floating point arguments are | |
4049 | also copied to general registers, because MIPS16 functions | |
4050 | don't use float registers for arguments. This duplication of | |
4051 | arguments in general registers can't hurt non-MIPS16 functions | |
4052 | because those registers are normally skipped. */ | |
4053 | ||
4054 | if (fp_register_arg_p (typecode, arg_type) | |
4055 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4056 | { | |
4057 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4058 | { | |
4059 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4060 | unsigned long regval; | |
4061 | ||
4062 | /* Write the low word of the double to the even register(s). */ | |
4063 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4064 | if (mips_debug) | |
4065 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4066 | float_argreg, phex (regval, 4)); | |
4067 | write_register (float_argreg++, regval); | |
4068 | if (mips_debug) | |
4069 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4070 | argreg, phex (regval, 4)); | |
4071 | write_register (argreg++, regval); | |
4072 | ||
4073 | /* Write the high word of the double to the odd register(s). */ | |
4074 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4075 | if (mips_debug) | |
4076 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4077 | float_argreg, phex (regval, 4)); | |
4078 | write_register (float_argreg++, regval); | |
4079 | ||
4080 | if (mips_debug) | |
4081 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4082 | argreg, phex (regval, 4)); | |
4083 | write_register (argreg++, regval); | |
4084 | } | |
4085 | else | |
4086 | { | |
4087 | /* This is a floating point value that fits entirely | |
4088 | in a single register. */ | |
4089 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4090 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4091 | LONGEST regval = extract_unsigned_integer (val, len); |
4092 | if (mips_debug) | |
4093 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4094 | float_argreg, phex (regval, len)); | |
4095 | write_register (float_argreg++, regval); | |
4096 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4097 | registers for each argument. The below is (my |
4098 | guess) to ensure that the corresponding integer | |
4099 | register has reserved the same space. */ | |
ebafbe83 MS |
4100 | if (mips_debug) |
4101 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4102 | argreg, phex (regval, len)); | |
4103 | write_register (argreg, regval); | |
4104 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
4105 | } | |
4106 | /* Reserve space for the FP register. */ | |
480d3dd2 | 4107 | stack_offset += align_up (len, mips_stack_argsize (tdep)); |
ebafbe83 MS |
4108 | } |
4109 | else | |
4110 | { | |
4111 | /* Copy the argument to general registers or the stack in | |
4112 | register-sized pieces. Large arguments are split between | |
4113 | registers and stack. */ | |
4246e332 AC |
4114 | /* Note: structs whose size is not a multiple of |
4115 | mips_regsize() are treated specially: Irix cc passes them | |
4116 | in registers where gcc sometimes puts them on the stack. | |
4117 | For maximum compatibility, we will put them in both | |
4118 | places. */ | |
480d3dd2 AC |
4119 | int odd_sized_struct = ((len > mips_saved_regsize (tdep)) |
4120 | && (len % mips_saved_regsize (tdep) != 0)); | |
ebafbe83 MS |
4121 | /* Structures should be aligned to eight bytes (even arg registers) |
4122 | on MIPS_ABI_O32, if their first member has double precision. */ | |
480d3dd2 | 4123 | if (mips_saved_regsize (tdep) < 8 |
ebafbe83 MS |
4124 | && mips_type_needs_double_align (arg_type)) |
4125 | { | |
4126 | if ((argreg & 1)) | |
6d82d43b | 4127 | argreg++; |
ebafbe83 MS |
4128 | } |
4129 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4130 | register are only written to memory. */ |
ebafbe83 MS |
4131 | while (len > 0) |
4132 | { | |
4133 | /* Remember if the argument was written to the stack. */ | |
4134 | int stack_used_p = 0; | |
480d3dd2 AC |
4135 | int partial_len = (len < mips_saved_regsize (tdep) |
4136 | ? len : mips_saved_regsize (tdep)); | |
ebafbe83 MS |
4137 | |
4138 | if (mips_debug) | |
4139 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4140 | partial_len); | |
4141 | ||
4142 | /* Write this portion of the argument to the stack. */ | |
4143 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4144 | || odd_sized_struct | |
4145 | || fp_register_arg_p (typecode, arg_type)) | |
4146 | { | |
4147 | /* Should shorter than int integer values be | |
4148 | promoted to int before being stored? */ | |
4149 | int longword_offset = 0; | |
4150 | CORE_ADDR addr; | |
4151 | stack_used_p = 1; | |
4152 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4153 | { | |
480d3dd2 AC |
4154 | if (mips_stack_argsize (tdep) == 8 |
4155 | && (typecode == TYPE_CODE_INT | |
4156 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4157 | || typecode == TYPE_CODE_FLT) && len <= 4) |
480d3dd2 | 4158 | longword_offset = mips_stack_argsize (tdep) - len; |
ebafbe83 MS |
4159 | } |
4160 | ||
4161 | if (mips_debug) | |
4162 | { | |
4163 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4164 | paddr_nz (stack_offset)); | |
4165 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4166 | paddr_nz (longword_offset)); | |
4167 | } | |
4168 | ||
4169 | addr = sp + stack_offset + longword_offset; | |
4170 | ||
4171 | if (mips_debug) | |
4172 | { | |
4173 | int i; | |
6d82d43b | 4174 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4175 | paddr_nz (addr)); |
4176 | for (i = 0; i < partial_len; i++) | |
4177 | { | |
6d82d43b | 4178 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4179 | val[i] & 0xff); |
4180 | } | |
4181 | } | |
4182 | write_memory (addr, val, partial_len); | |
4183 | } | |
4184 | ||
4185 | /* Note!!! This is NOT an else clause. Odd sized | |
4186 | structs may go thru BOTH paths. Floating point | |
4187 | arguments will not. */ | |
4188 | /* Write this portion of the argument to a general | |
6d82d43b | 4189 | purpose register. */ |
ebafbe83 MS |
4190 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4191 | && !fp_register_arg_p (typecode, arg_type)) | |
4192 | { | |
4193 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4194 | /* Value may need to be sign extended, because |
480d3dd2 | 4195 | mips_regsize() != mips_saved_regsize(). */ |
ebafbe83 MS |
4196 | |
4197 | /* A non-floating-point argument being passed in a | |
4198 | general register. If a struct or union, and if | |
4199 | the remaining length is smaller than the register | |
4200 | size, we have to adjust the register value on | |
4201 | big endian targets. | |
4202 | ||
4203 | It does not seem to be necessary to do the | |
4204 | same for integral types. | |
4205 | ||
4206 | Also don't do this adjustment on O64 binaries. | |
4207 | ||
4208 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4209 | outputting LE O32 with sizeof (struct) < | |
480d3dd2 | 4210 | mips_saved_regsize(), generates a left shift as |
ebafbe83 MS |
4211 | part of storing the argument in a register a |
4212 | register (the left shift isn't generated when | |
480d3dd2 AC |
4213 | sizeof (struct) >= mips_saved_regsize()). Since |
4214 | it is quite possible that this is GCC | |
4215 | contradicting the LE/O32 ABI, GDB has not been | |
4216 | adjusted to accommodate this. Either someone | |
4217 | needs to demonstrate that the LE/O32 ABI | |
4218 | specifies such a left shift OR this new ABI gets | |
4219 | identified as such and GDB gets tweaked | |
4220 | accordingly. */ | |
4221 | ||
4222 | if (mips_saved_regsize (tdep) < 8 | |
ebafbe83 | 4223 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
480d3dd2 | 4224 | && partial_len < mips_saved_regsize (tdep) |
ebafbe83 MS |
4225 | && (typecode == TYPE_CODE_STRUCT || |
4226 | typecode == TYPE_CODE_UNION)) | |
480d3dd2 | 4227 | regval <<= ((mips_saved_regsize (tdep) - partial_len) * |
ebafbe83 MS |
4228 | TARGET_CHAR_BIT); |
4229 | ||
4230 | if (mips_debug) | |
4231 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4232 | argreg, | |
6d82d43b AC |
4233 | phex (regval, |
4234 | mips_saved_regsize (tdep))); | |
ebafbe83 MS |
4235 | write_register (argreg, regval); |
4236 | argreg++; | |
4237 | ||
4238 | /* Prevent subsequent floating point arguments from | |
4239 | being passed in floating point registers. */ | |
4240 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4241 | } | |
4242 | ||
4243 | len -= partial_len; | |
4244 | val += partial_len; | |
4245 | ||
4246 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4247 | will copy the next parameter. |
ebafbe83 | 4248 | |
6d82d43b AC |
4249 | In older ABIs, the caller reserved space for |
4250 | registers that contained arguments. This was loosely | |
4251 | refered to as their "home". Consequently, space is | |
4252 | always allocated. */ | |
ebafbe83 | 4253 | |
480d3dd2 AC |
4254 | stack_offset += align_up (partial_len, |
4255 | mips_stack_argsize (tdep)); | |
ebafbe83 MS |
4256 | } |
4257 | } | |
4258 | if (mips_debug) | |
4259 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4260 | } | |
4261 | ||
310e9b6a AC |
4262 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
4263 | ||
ebafbe83 MS |
4264 | /* Return adjusted stack pointer. */ |
4265 | return sp; | |
4266 | } | |
4267 | ||
f7ab6ec6 | 4268 | static void |
6d82d43b AC |
4269 | mips_o64_extract_return_value (struct type *valtype, |
4270 | char regbuf[], char *valbuf) | |
c906108c | 4271 | { |
6d82d43b AC |
4272 | struct return_value_word lo; |
4273 | struct return_value_word hi; | |
4274 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4275 | |
6d82d43b AC |
4276 | memcpy (valbuf + lo.buf_offset, |
4277 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4278 | lo.reg_offset, lo.len); | |
4279 | ||
4280 | if (hi.len > 0) | |
4281 | memcpy (valbuf + hi.buf_offset, | |
4282 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4283 | hi.reg_offset, hi.len); | |
4284 | } | |
4285 | ||
4286 | static void | |
4287 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4288 | { | |
4289 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4290 | struct return_value_word lo; | |
4291 | struct return_value_word hi; | |
4292 | return_value_location (valtype, &hi, &lo); | |
4293 | ||
4294 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4295 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4296 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4297 | raw_buffer, register_size (current_gdbarch, | |
4298 | lo.reg)); | |
4299 | ||
4300 | if (hi.len > 0) | |
4301 | { | |
4302 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4303 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4304 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4305 | raw_buffer, | |
4306 | register_size (current_gdbarch, | |
4307 | hi.reg)); | |
4308 | } | |
4309 | } | |
4310 | ||
4311 | static void | |
4312 | mips_pop_frame (void) | |
4313 | { | |
4314 | int regnum; | |
4315 | struct frame_info *frame = get_current_frame (); | |
4316 | CORE_ADDR new_sp = get_frame_base (frame); | |
4317 | mips_extra_func_info_t proc_desc; | |
4318 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4319 | ||
4320 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) | |
4321 | { | |
4322 | generic_pop_dummy_frame (); | |
4323 | flush_cached_frames (); | |
cedea778 AC |
4324 | return; |
4325 | } | |
4326 | ||
e227b13c | 4327 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
b6cb9035 AC |
4328 | write_register (mips_regnum (current_gdbarch)->pc, |
4329 | DEPRECATED_FRAME_SAVED_PC (frame)); | |
e0f7ec59 | 4330 | mips_find_saved_regs (frame); |
c906108c | 4331 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
b6cb9035 | 4332 | if (regnum != SP_REGNUM && regnum != mips_regnum (current_gdbarch)->pc |
1b1d3794 | 4333 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 | 4334 | { |
480d3dd2 AC |
4335 | /* Floating point registers must not be sign extended, in case |
4336 | mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */ | |
21f87145 | 4337 | |
6d82d43b AC |
4338 | if (mips_regnum (current_gdbarch)->fp0 <= regnum |
4339 | && regnum < mips_regnum (current_gdbarch)->fp0 + 32) | |
21f87145 | 4340 | write_register (regnum, |
6d82d43b AC |
4341 | read_memory_unsigned_integer |
4342 | (deprecated_get_frame_saved_regs (frame)[regnum], | |
4343 | mips_saved_regsize (tdep))); | |
21f87145 MS |
4344 | else |
4345 | write_register (regnum, | |
6d82d43b AC |
4346 | read_memory_integer (deprecated_get_frame_saved_regs |
4347 | (frame)[regnum], | |
480d3dd2 | 4348 | mips_saved_regsize (tdep))); |
21f87145 | 4349 | } |
757a7cc6 | 4350 | |
c906108c SS |
4351 | write_register (SP_REGNUM, new_sp); |
4352 | flush_cached_frames (); | |
4353 | ||
c5aa993b | 4354 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
4355 | { |
4356 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
4357 | ||
4358 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
6d82d43b | 4359 | pi_ptr != NULL; prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) |
c906108c SS |
4360 | { |
4361 | if (&pi_ptr->info == proc_desc) | |
4362 | break; | |
4363 | } | |
4364 | ||
4365 | if (pi_ptr == NULL) | |
4366 | error ("Can't locate dummy extra frame info\n"); | |
4367 | ||
4368 | if (prev_ptr != NULL) | |
4369 | prev_ptr->next = pi_ptr->next; | |
4370 | else | |
4371 | linked_proc_desc_table = pi_ptr->next; | |
4372 | ||
b8c9b27d | 4373 | xfree (pi_ptr); |
c906108c | 4374 | |
56cea623 | 4375 | write_register (mips_regnum (current_gdbarch)->hi, |
480d3dd2 AC |
4376 | read_memory_integer ((new_sp |
4377 | - 2 * mips_saved_regsize (tdep)), | |
4378 | mips_saved_regsize (tdep))); | |
56cea623 | 4379 | write_register (mips_regnum (current_gdbarch)->lo, |
480d3dd2 AC |
4380 | read_memory_integer ((new_sp |
4381 | - 3 * mips_saved_regsize (tdep)), | |
4382 | mips_saved_regsize (tdep))); | |
c906108c | 4383 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
56cea623 | 4384 | write_register (mips_regnum (current_gdbarch)->fp_control_status, |
480d3dd2 | 4385 | read_memory_integer ((new_sp |
6d82d43b AC |
4386 | - |
4387 | 4 * mips_saved_regsize (tdep)), | |
480d3dd2 | 4388 | mips_saved_regsize (tdep))); |
c906108c SS |
4389 | } |
4390 | } | |
4391 | ||
dd824b04 DJ |
4392 | /* Floating point register management. |
4393 | ||
4394 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4395 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4396 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4397 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4398 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4399 | double precision floats into two 32-bit chunks and store them in | |
4400 | consecutive fp regs. To display 64-bit floats stored in this | |
4401 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4402 | Throw in user-configurable endianness and you have a real mess. | |
4403 | ||
4404 | The way this works is: | |
4405 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4406 | double-precision value will be split across two logical registers. | |
4407 | The lower-numbered logical register will hold the low-order bits, | |
4408 | regardless of the processor's endianness. | |
4409 | - If we are on a 64-bit processor, and we are looking for a | |
4410 | single-precision value, it will be in the low ordered bits | |
4411 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4412 | save slot in memory. | |
4413 | - If we are in 64-bit mode, everything is straightforward. | |
4414 | ||
4415 | Note that this code only deals with "live" registers at the top of the | |
4416 | stack. We will attempt to deal with saved registers later, when | |
4417 | the raw/cooked register interface is in place. (We need a general | |
4418 | interface that can deal with dynamic saved register sizes -- fp | |
4419 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4420 | and below). */ | |
4421 | ||
67b2c998 DJ |
4422 | static struct type * |
4423 | mips_float_register_type (void) | |
4424 | { | |
361d1df0 | 4425 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4426 | return builtin_type_ieee_single_big; |
4427 | else | |
4428 | return builtin_type_ieee_single_little; | |
4429 | } | |
4430 | ||
4431 | static struct type * | |
4432 | mips_double_register_type (void) | |
4433 | { | |
361d1df0 | 4434 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4435 | return builtin_type_ieee_double_big; |
4436 | else | |
4437 | return builtin_type_ieee_double_little; | |
4438 | } | |
4439 | ||
dd824b04 DJ |
4440 | /* Copy a 32-bit single-precision value from the current frame |
4441 | into rare_buffer. */ | |
4442 | ||
4443 | static void | |
e11c53d2 AC |
4444 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4445 | char *rare_buffer) | |
dd824b04 | 4446 | { |
719ec221 | 4447 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4448 | char *raw_buffer = alloca (raw_size); |
4449 | ||
e11c53d2 | 4450 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4451 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4452 | if (raw_size == 8) | |
4453 | { | |
4454 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4455 | 32 bits. */ |
dd824b04 DJ |
4456 | int offset; |
4457 | ||
4458 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4459 | offset = 4; | |
4460 | else | |
4461 | offset = 0; | |
4462 | ||
4463 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4464 | } | |
4465 | else | |
4466 | { | |
4467 | memcpy (rare_buffer, raw_buffer, 4); | |
4468 | } | |
4469 | } | |
4470 | ||
4471 | /* Copy a 64-bit double-precision value from the current frame into | |
4472 | rare_buffer. This may include getting half of it from the next | |
4473 | register. */ | |
4474 | ||
4475 | static void | |
e11c53d2 AC |
4476 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4477 | char *rare_buffer) | |
dd824b04 | 4478 | { |
719ec221 | 4479 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4480 | |
4481 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4482 | { | |
4483 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4484 | all 64 bits. */ |
e11c53d2 | 4485 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4486 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4487 | } | |
4488 | else | |
4489 | { | |
56cea623 | 4490 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4491 | internal_error (__FILE__, __LINE__, |
4492 | "mips_read_fp_register_double: bad access to " | |
4493 | "odd-numbered FP register"); | |
4494 | ||
4495 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4496 | each register. */ |
dd824b04 DJ |
4497 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4498 | { | |
e11c53d2 AC |
4499 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4500 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4501 | } |
361d1df0 | 4502 | else |
dd824b04 | 4503 | { |
e11c53d2 AC |
4504 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4505 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4506 | } |
4507 | } | |
4508 | } | |
4509 | ||
c906108c | 4510 | static void |
e11c53d2 AC |
4511 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4512 | int regnum) | |
c5aa993b | 4513 | { /* do values for FP (float) regs */ |
dd824b04 | 4514 | char *raw_buffer; |
c906108c | 4515 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4516 | int inv1, inv2, namelen; |
c5aa993b | 4517 | |
6d82d43b AC |
4518 | raw_buffer = |
4519 | (char *) alloca (2 * | |
4520 | register_size (current_gdbarch, | |
4521 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4522 | |
e11c53d2 AC |
4523 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4524 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4525 | ""); | |
f0ef6b29 | 4526 | |
719ec221 | 4527 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4528 | { |
f0ef6b29 KB |
4529 | /* 4-byte registers: Print hex and floating. Also print even |
4530 | numbered registers as doubles. */ | |
e11c53d2 | 4531 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4532 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4533 | |
6d82d43b AC |
4534 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4535 | file); | |
dd824b04 | 4536 | |
e11c53d2 | 4537 | fprintf_filtered (file, " flt: "); |
1adad886 | 4538 | if (inv1) |
e11c53d2 | 4539 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4540 | else |
e11c53d2 | 4541 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4542 | |
f0ef6b29 KB |
4543 | if (regnum % 2 == 0) |
4544 | { | |
e11c53d2 | 4545 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4546 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4547 | &inv2); |
1adad886 | 4548 | |
e11c53d2 | 4549 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4550 | if (inv2) |
e11c53d2 | 4551 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4552 | else |
e11c53d2 | 4553 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4554 | } |
c906108c SS |
4555 | } |
4556 | else | |
dd824b04 | 4557 | { |
f0ef6b29 | 4558 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4559 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4560 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4561 | |
e11c53d2 | 4562 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4563 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4564 | ||
361d1df0 | 4565 | |
6d82d43b AC |
4566 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4567 | file); | |
f0ef6b29 | 4568 | |
e11c53d2 | 4569 | fprintf_filtered (file, " flt: "); |
1adad886 | 4570 | if (inv1) |
e11c53d2 | 4571 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4572 | else |
e11c53d2 | 4573 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4574 | |
e11c53d2 | 4575 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4576 | if (inv2) |
e11c53d2 | 4577 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4578 | else |
e11c53d2 | 4579 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4580 | } |
4581 | } | |
4582 | ||
4583 | static void | |
e11c53d2 AC |
4584 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4585 | int regnum, int all) | |
f0ef6b29 | 4586 | { |
a4b8ebc8 | 4587 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4588 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4589 | int offset; |
1adad886 | 4590 | |
a4b8ebc8 | 4591 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4592 | { |
e11c53d2 | 4593 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4594 | return; |
4595 | } | |
4596 | ||
4597 | /* Get the data in raw format. */ | |
e11c53d2 | 4598 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4599 | { |
e11c53d2 | 4600 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4601 | return; |
c906108c | 4602 | } |
f0ef6b29 | 4603 | |
e11c53d2 | 4604 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4605 | |
4606 | /* The problem with printing numeric register names (r26, etc.) is that | |
4607 | the user can't use them on input. Probably the best solution is to | |
4608 | fix it so that either the numeric or the funky (a2, etc.) names | |
4609 | are accepted on input. */ | |
4610 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4611 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4612 | else |
e11c53d2 | 4613 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4614 | |
4615 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4616 | offset = |
4617 | register_size (current_gdbarch, | |
4618 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4619 | else |
4620 | offset = 0; | |
4621 | ||
6d82d43b AC |
4622 | print_scalar_formatted (raw_buffer + offset, |
4623 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4624 | file); | |
c906108c SS |
4625 | } |
4626 | ||
f0ef6b29 KB |
4627 | /* Replacement for generic do_registers_info. |
4628 | Print regs in pretty columns. */ | |
4629 | ||
4630 | static int | |
e11c53d2 AC |
4631 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4632 | int regnum) | |
f0ef6b29 | 4633 | { |
e11c53d2 AC |
4634 | fprintf_filtered (file, " "); |
4635 | mips_print_fp_register (file, frame, regnum); | |
4636 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4637 | return regnum + 1; |
4638 | } | |
4639 | ||
4640 | ||
c906108c SS |
4641 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4642 | ||
4643 | static int | |
e11c53d2 | 4644 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4645 | int start_regnum) |
c906108c | 4646 | { |
a4b8ebc8 | 4647 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4648 | /* do values for GP (int) regs */ |
d9d9c31f | 4649 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4650 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4651 | int col, byte; |
a4b8ebc8 | 4652 | int regnum; |
c906108c SS |
4653 | |
4654 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4655 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4656 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4657 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4658 | { |
4659 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4660 | continue; /* unused register */ |
6d82d43b AC |
4661 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4662 | TYPE_CODE_FLT) | |
c5aa993b | 4663 | break; /* end the row: reached FP register */ |
6d82d43b AC |
4664 | fprintf_filtered (file, |
4665 | mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", | |
e11c53d2 | 4666 | REGISTER_NAME (regnum)); |
c906108c SS |
4667 | col++; |
4668 | } | |
a4b8ebc8 | 4669 | /* print the R0 to R31 names */ |
20e6603c AC |
4670 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4671 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4672 | else | |
4673 | fprintf_filtered (file, "\n "); | |
c906108c | 4674 | |
c906108c | 4675 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4676 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4677 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4678 | { |
4679 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4680 | continue; /* unused register */ |
6d82d43b AC |
4681 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4682 | TYPE_CODE_FLT) | |
c5aa993b | 4683 | break; /* end row: reached FP register */ |
c906108c | 4684 | /* OK: get the data in raw format. */ |
e11c53d2 | 4685 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4686 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4687 | /* pad small registers */ | |
4246e332 AC |
4688 | for (byte = 0; |
4689 | byte < (mips_regsize (current_gdbarch) | |
6d82d43b | 4690 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4691 | printf_filtered (" "); |
4692 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4693 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4694 | for (byte = |
4695 | register_size (current_gdbarch, | |
4696 | regnum) - register_size (current_gdbarch, regnum); | |
4697 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4698 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4699 | else |
c73e8f27 | 4700 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4701 | byte >= 0; byte--) |
e11c53d2 AC |
4702 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4703 | fprintf_filtered (file, " "); | |
c906108c SS |
4704 | col++; |
4705 | } | |
c5aa993b | 4706 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4707 | fprintf_filtered (file, "\n"); |
c906108c SS |
4708 | |
4709 | return regnum; | |
4710 | } | |
4711 | ||
4712 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4713 | ||
bf1f5b4c | 4714 | static void |
e11c53d2 AC |
4715 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4716 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4717 | { |
c5aa993b | 4718 | if (regnum != -1) /* do one specified register */ |
c906108c | 4719 | { |
a4b8ebc8 | 4720 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4721 | if (*(REGISTER_NAME (regnum)) == '\0') |
4722 | error ("Not a valid register for the current processor type"); | |
4723 | ||
e11c53d2 AC |
4724 | mips_print_register (file, frame, regnum, 0); |
4725 | fprintf_filtered (file, "\n"); | |
c906108c | 4726 | } |
c5aa993b JM |
4727 | else |
4728 | /* do all (or most) registers */ | |
c906108c | 4729 | { |
a4b8ebc8 AC |
4730 | regnum = NUM_REGS; |
4731 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4732 | { |
6d82d43b AC |
4733 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4734 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4735 | { |
4736 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4737 | regnum = print_fp_register_row (file, frame, regnum); | |
4738 | else | |
4739 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4740 | } | |
c906108c | 4741 | else |
e11c53d2 | 4742 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4743 | } |
4744 | } | |
4745 | } | |
4746 | ||
c906108c SS |
4747 | /* Is this a branch with a delay slot? */ |
4748 | ||
a14ed312 | 4749 | static int is_delayed (unsigned long); |
c906108c SS |
4750 | |
4751 | static int | |
acdb74a0 | 4752 | is_delayed (unsigned long insn) |
c906108c SS |
4753 | { |
4754 | int i; | |
4755 | for (i = 0; i < NUMOPCODES; ++i) | |
4756 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4757 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4758 | break; | |
4759 | return (i < NUMOPCODES | |
4760 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4761 | | INSN_COND_BRANCH_DELAY | |
4762 | | INSN_COND_BRANCH_LIKELY))); | |
4763 | } | |
4764 | ||
4765 | int | |
acdb74a0 | 4766 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4767 | { |
4768 | char buf[MIPS_INSTLEN]; | |
4769 | ||
4770 | /* There is no branch delay slot on MIPS16. */ | |
4771 | if (pc_is_mips16 (pc)) | |
4772 | return 0; | |
4773 | ||
4774 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4775 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4776 | return 0; | |
6d82d43b AC |
4777 | return is_delayed ((unsigned long) |
4778 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
4779 | } |
4780 | ||
4781 | ||
74da7425 AC |
4782 | /* Given PC at the function's start address, attempt to find the |
4783 | prologue end using SAL information. Return zero if the skip fails. | |
4784 | ||
4785 | A non-optimized prologue traditionally has one SAL for the function | |
4786 | and a second for the function body. A single line function has | |
4787 | them both pointing at the same line. | |
4788 | ||
4789 | An optimized prologue is similar but the prologue may contain | |
4790 | instructions (SALs) from the instruction body. Need to skip those | |
4791 | while not getting into the function body. | |
4792 | ||
4793 | The functions end point and an increasing SAL line are used as | |
4794 | indicators of the prologue's endpoint. | |
4795 | ||
4796 | This code is based on the function refine_prologue_limit (versions | |
4797 | found in both ia64 and ppc). */ | |
4798 | ||
4799 | static CORE_ADDR | |
4800 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
4801 | { | |
4802 | struct symtab_and_line prologue_sal; | |
4803 | CORE_ADDR start_pc; | |
4804 | CORE_ADDR end_pc; | |
4805 | ||
4806 | /* Get an initial range for the function. */ | |
4807 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
4808 | start_pc += FUNCTION_START_OFFSET; | |
4809 | ||
4810 | prologue_sal = find_pc_line (start_pc, 0); | |
4811 | if (prologue_sal.line != 0) | |
4812 | { | |
4813 | while (prologue_sal.end < end_pc) | |
4814 | { | |
4815 | struct symtab_and_line sal; | |
4816 | ||
4817 | sal = find_pc_line (prologue_sal.end, 0); | |
4818 | if (sal.line == 0) | |
4819 | break; | |
4820 | /* Assume that a consecutive SAL for the same (or larger) | |
6d82d43b | 4821 | line mark the prologue -> body transition. */ |
74da7425 AC |
4822 | if (sal.line >= prologue_sal.line) |
4823 | break; | |
4824 | /* The case in which compiler's optimizer/scheduler has | |
4825 | moved instructions into the prologue. We look ahead in | |
4826 | the function looking for address ranges whose | |
4827 | corresponding line number is less the first one that we | |
4828 | found for the function. This is more conservative then | |
4829 | refine_prologue_limit which scans a large number of SALs | |
4830 | looking for any in the prologue */ | |
4831 | prologue_sal = sal; | |
4832 | } | |
4833 | } | |
4834 | return prologue_sal.end; | |
4835 | } | |
4836 | ||
c906108c SS |
4837 | /* Skip the PC past function prologue instructions (32-bit version). |
4838 | This is a helper function for mips_skip_prologue. */ | |
4839 | ||
4840 | static CORE_ADDR | |
f7b9e9fc | 4841 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4842 | { |
c5aa993b JM |
4843 | t_inst inst; |
4844 | CORE_ADDR end_pc; | |
4845 | int seen_sp_adjust = 0; | |
4846 | int load_immediate_bytes = 0; | |
4847 | ||
74da7425 AC |
4848 | /* Find an upper bound on the prologue. */ |
4849 | end_pc = skip_prologue_using_sal (pc); | |
4850 | if (end_pc == 0) | |
6d82d43b | 4851 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 4852 | |
c5aa993b JM |
4853 | /* Skip the typical prologue instructions. These are the stack adjustment |
4854 | instruction and the instructions that save registers on the stack | |
4855 | or in the gcc frame. */ | |
74da7425 | 4856 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4857 | { |
4858 | unsigned long high_word; | |
c906108c | 4859 | |
c5aa993b JM |
4860 | inst = mips_fetch_instruction (pc); |
4861 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4862 | |
c5aa993b JM |
4863 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4864 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4865 | seen_sp_adjust = 1; | |
4866 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4867 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4868 | seen_sp_adjust = 1; | |
4869 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4870 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4871 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4872 | continue; | |
4873 | ||
4874 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4875 | continue; | |
4876 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4877 | /* sx reg,n($s8) */ | |
4878 | continue; /* reg != $zero */ | |
4879 | ||
4880 | /* move $s8,$sp. With different versions of gas this will be either | |
4881 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4882 | Accept any one of these. */ | |
4883 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4884 | continue; | |
4885 | ||
4886 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4887 | continue; | |
6d82d43b AC |
4888 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
4889 | continue; | |
4890 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4891 | continue; | |
4892 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4893 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4894 | continue; | |
4895 | /* The following instructions load $at or $t0 with an immediate | |
4896 | value in preparation for a stack adjustment via | |
4897 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4898 | a local variable, so we accept them only before a stack adjustment | |
4899 | instruction was seen. */ | |
4900 | else if (!seen_sp_adjust) | |
cb1d2653 | 4901 | { |
6d82d43b AC |
4902 | if (high_word == 0x3c01 || /* lui $at,n */ |
4903 | high_word == 0x3c08) /* lui $t0,n */ | |
4904 | { | |
4905 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4906 | continue; | |
4907 | } | |
4908 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4909 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4910 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4911 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4912 | { | |
4913 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4914 | continue; | |
4915 | } | |
4916 | else | |
4917 | break; | |
cb1d2653 | 4918 | } |
6d82d43b AC |
4919 | else |
4920 | break; | |
46cac009 | 4921 | } |
6d82d43b AC |
4922 | |
4923 | /* In a frameless function, we might have incorrectly | |
4924 | skipped some load immediate instructions. Undo the skipping | |
4925 | if the load immediate was not followed by a stack adjustment. */ | |
4926 | if (load_immediate_bytes && !seen_sp_adjust) | |
4927 | pc -= load_immediate_bytes; | |
4928 | return pc; | |
46cac009 AC |
4929 | } |
4930 | ||
6d82d43b AC |
4931 | /* Skip the PC past function prologue instructions (16-bit version). |
4932 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 4933 | |
6d82d43b AC |
4934 | static CORE_ADDR |
4935 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 4936 | { |
6d82d43b AC |
4937 | CORE_ADDR end_pc; |
4938 | int extend_bytes = 0; | |
4939 | int prev_extend_bytes; | |
4940 | ||
4941 | /* Table of instructions likely to be found in a function prologue. */ | |
4942 | static struct | |
4943 | { | |
4944 | unsigned short inst; | |
4945 | unsigned short mask; | |
4946 | } | |
4947 | table[] = | |
4948 | { | |
7a292a7a | 4949 | { |
6d82d43b AC |
4950 | 0x6300, 0xff00} |
4951 | , /* addiu $sp,offset */ | |
88658117 | 4952 | { |
6d82d43b AC |
4953 | 0xfb00, 0xff00} |
4954 | , /* daddiu $sp,offset */ | |
88658117 | 4955 | { |
6d82d43b AC |
4956 | 0xd000, 0xf800} |
4957 | , /* sw reg,n($sp) */ | |
4958 | { | |
4959 | 0xf900, 0xff00} | |
4960 | , /* sd reg,n($sp) */ | |
4961 | { | |
4962 | 0x6200, 0xff00} | |
4963 | , /* sw $ra,n($sp) */ | |
4964 | { | |
4965 | 0xfa00, 0xff00} | |
4966 | , /* sd $ra,n($sp) */ | |
4967 | { | |
4968 | 0x673d, 0xffff} | |
4969 | , /* move $s1,sp */ | |
4970 | { | |
4971 | 0xd980, 0xff80} | |
4972 | , /* sw $a0-$a3,n($s1) */ | |
4973 | { | |
4974 | 0x6704, 0xff1c} | |
4975 | , /* move reg,$a0-$a3 */ | |
4976 | { | |
4977 | 0xe809, 0xf81f} | |
4978 | , /* entry pseudo-op */ | |
4979 | { | |
4980 | 0x0100, 0xff00} | |
4981 | , /* addiu $s1,$sp,n */ | |
4982 | { | |
4983 | 0, 0} /* end of table marker */ | |
4984 | }; | |
4985 | ||
4986 | /* Find an upper bound on the prologue. */ | |
4987 | end_pc = skip_prologue_using_sal (pc); | |
4988 | if (end_pc == 0) | |
4989 | end_pc = pc + 100; /* Magic. */ | |
4990 | ||
4991 | /* Skip the typical prologue instructions. These are the stack adjustment | |
4992 | instruction and the instructions that save registers on the stack | |
4993 | or in the gcc frame. */ | |
4994 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
4995 | { | |
4996 | unsigned short inst; | |
4997 | int i; | |
4998 | ||
4999 | inst = mips_fetch_instruction (pc); | |
5000 | ||
5001 | /* Normally we ignore an extend instruction. However, if it is | |
5002 | not followed by a valid prologue instruction, we must adjust | |
5003 | the pc back over the extend so that it won't be considered | |
5004 | part of the prologue. */ | |
5005 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 5006 | { |
6d82d43b AC |
5007 | extend_bytes = MIPS16_INSTLEN; |
5008 | continue; | |
88658117 | 5009 | } |
6d82d43b AC |
5010 | prev_extend_bytes = extend_bytes; |
5011 | extend_bytes = 0; | |
5012 | ||
5013 | /* Check for other valid prologue instructions besides extend. */ | |
5014 | for (i = 0; table[i].mask != 0; i++) | |
5015 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
5016 | break; | |
5017 | if (table[i].mask != 0) /* it was in table? */ | |
5018 | continue; /* ignore it */ | |
5019 | else | |
5020 | /* non-prologue */ | |
88658117 | 5021 | { |
6d82d43b AC |
5022 | /* Return the current pc, adjusted backwards by 2 if |
5023 | the previous instruction was an extend. */ | |
5024 | return pc - prev_extend_bytes; | |
88658117 AC |
5025 | } |
5026 | } | |
6d82d43b AC |
5027 | return pc; |
5028 | } | |
5029 | ||
5030 | /* To skip prologues, I use this predicate. Returns either PC itself | |
5031 | if the code at PC does not look like a function prologue; otherwise | |
5032 | returns an address that (if we're lucky) follows the prologue. If | |
5033 | LENIENT, then we must skip everything which is involved in setting | |
5034 | up the frame (it's OK to skip more, just so long as we don't skip | |
5035 | anything which might clobber the registers which are being saved. | |
5036 | We must skip more in the case where part of the prologue is in the | |
5037 | delay slot of a non-prologue instruction). */ | |
5038 | ||
5039 | static CORE_ADDR | |
5040 | mips_skip_prologue (CORE_ADDR pc) | |
5041 | { | |
5042 | /* See if we can determine the end of the prologue via the symbol table. | |
5043 | If so, then return either PC, or the PC after the prologue, whichever | |
5044 | is greater. */ | |
5045 | ||
5046 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
5047 | ||
5048 | if (post_prologue_pc != 0) | |
5049 | return max (pc, post_prologue_pc); | |
5050 | ||
5051 | /* Can't determine prologue from the symbol table, need to examine | |
5052 | instructions. */ | |
5053 | ||
5054 | if (pc_is_mips16 (pc)) | |
5055 | return mips16_skip_prologue (pc); | |
5056 | else | |
5057 | return mips32_skip_prologue (pc); | |
88658117 AC |
5058 | } |
5059 | ||
c906108c SS |
5060 | /* Exported procedure: Is PC in the signal trampoline code */ |
5061 | ||
102182a9 MS |
5062 | static int |
5063 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5064 | { |
5065 | if (sigtramp_address == 0) | |
5066 | fixup_sigtramp (); | |
5067 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5068 | } | |
5069 | ||
a5ea2558 AC |
5070 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5071 | used for all MIPS-specific commands. */ | |
5072 | ||
a5ea2558 | 5073 | static void |
acdb74a0 | 5074 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5075 | { |
5076 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5077 | } | |
5078 | ||
a5ea2558 | 5079 | static void |
acdb74a0 | 5080 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5081 | { |
6d82d43b AC |
5082 | printf_unfiltered |
5083 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5084 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5085 | } | |
5086 | ||
c906108c SS |
5087 | /* Commands to show/set the MIPS FPU type. */ |
5088 | ||
c906108c | 5089 | static void |
acdb74a0 | 5090 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5091 | { |
c906108c SS |
5092 | char *fpu; |
5093 | switch (MIPS_FPU_TYPE) | |
5094 | { | |
5095 | case MIPS_FPU_SINGLE: | |
5096 | fpu = "single-precision"; | |
5097 | break; | |
5098 | case MIPS_FPU_DOUBLE: | |
5099 | fpu = "double-precision"; | |
5100 | break; | |
5101 | case MIPS_FPU_NONE: | |
5102 | fpu = "absent (none)"; | |
5103 | break; | |
93d56215 AC |
5104 | default: |
5105 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5106 | } |
5107 | if (mips_fpu_type_auto) | |
6d82d43b AC |
5108 | printf_unfiltered |
5109 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5110 | fpu); | |
c906108c | 5111 | else |
6d82d43b AC |
5112 | printf_unfiltered |
5113 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5114 | } |
5115 | ||
5116 | ||
c906108c | 5117 | static void |
acdb74a0 | 5118 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5119 | { |
6d82d43b AC |
5120 | printf_unfiltered |
5121 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5122 | show_mipsfpu_command (args, from_tty); |
5123 | } | |
5124 | ||
c906108c | 5125 | static void |
acdb74a0 | 5126 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5127 | { |
8d5838b5 AC |
5128 | struct gdbarch_info info; |
5129 | gdbarch_info_init (&info); | |
c906108c SS |
5130 | mips_fpu_type = MIPS_FPU_SINGLE; |
5131 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5132 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5133 | instead of relying on globals. Doing that would let generic code | |
5134 | handle the search for this specific architecture. */ | |
5135 | if (!gdbarch_update_p (info)) | |
5136 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5137 | } |
5138 | ||
c906108c | 5139 | static void |
acdb74a0 | 5140 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5141 | { |
8d5838b5 AC |
5142 | struct gdbarch_info info; |
5143 | gdbarch_info_init (&info); | |
c906108c SS |
5144 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5145 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5146 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5147 | instead of relying on globals. Doing that would let generic code | |
5148 | handle the search for this specific architecture. */ | |
5149 | if (!gdbarch_update_p (info)) | |
5150 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5151 | } |
5152 | ||
c906108c | 5153 | static void |
acdb74a0 | 5154 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5155 | { |
8d5838b5 AC |
5156 | struct gdbarch_info info; |
5157 | gdbarch_info_init (&info); | |
c906108c SS |
5158 | mips_fpu_type = MIPS_FPU_NONE; |
5159 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5160 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5161 | instead of relying on globals. Doing that would let generic code | |
5162 | handle the search for this specific architecture. */ | |
5163 | if (!gdbarch_update_p (info)) | |
5164 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5165 | } |
5166 | ||
c906108c | 5167 | static void |
acdb74a0 | 5168 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5169 | { |
5170 | mips_fpu_type_auto = 1; | |
5171 | } | |
5172 | ||
c906108c | 5173 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5174 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5175 | the relevant processor still exists (it dates back to '94) and | |
5176 | secondly this is not the way to do this. The processor type should | |
5177 | be set by forcing an architecture change. */ | |
c906108c | 5178 | |
691c0433 AC |
5179 | void |
5180 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5181 | { |
691c0433 | 5182 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5183 | CORE_ADDR prid; |
5184 | ||
5185 | prid = read_register (PRID_REGNUM); | |
5186 | ||
5187 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5188 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5189 | } |
5190 | ||
5191 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5192 | callable as an sfunc. */ | |
5193 | ||
5194 | static void | |
acdb74a0 AC |
5195 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5196 | struct cmd_list_element *c) | |
c906108c SS |
5197 | { |
5198 | reinit_frame_cache (); | |
5199 | } | |
5200 | ||
a89aa300 AC |
5201 | static int |
5202 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5203 | { |
e5ab0dce | 5204 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5205 | mips_extra_func_info_t proc_desc; |
5206 | ||
5207 | /* Search for the function containing this address. Set the low bit | |
5208 | of the address when searching, in case we were given an even address | |
5209 | that is the start of a 16-bit function. If we didn't do this, | |
5210 | the search would fail because the symbol table says the function | |
5211 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5212 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5213 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5214 | |
5215 | /* Make an attempt to determine if this is a 16-bit function. If | |
5216 | the procedure descriptor exists and the address therein is odd, | |
5217 | it's definitely a 16-bit function. Otherwise, we have to just | |
5218 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5219 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5220 | disassembler needs to be able to locally determine the ISA, and | |
5221 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5222 | work. */ | |
c906108c | 5223 | if (proc_desc) |
d31431ed AC |
5224 | { |
5225 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 5226 | info->mach = bfd_mach_mips16; |
d31431ed | 5227 | } |
c906108c | 5228 | else |
d31431ed AC |
5229 | { |
5230 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5231 | info->mach = bfd_mach_mips16; |
5232 | } | |
c906108c SS |
5233 | |
5234 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5235 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5236 | |
e5ab0dce | 5237 | /* Set the disassembler options. */ |
6d82d43b | 5238 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5239 | { |
5240 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5241 | register names from libopcodes. */ |
e5ab0dce AC |
5242 | if (tdep->mips_abi == MIPS_ABI_N32) |
5243 | info->disassembler_options = "gpr-names=n32"; | |
5244 | else | |
5245 | info->disassembler_options = "gpr-names=64"; | |
5246 | info->flavour = bfd_target_elf_flavour; | |
5247 | } | |
5248 | else | |
5249 | /* This string is not recognized explicitly by the disassembler, | |
5250 | but it tells the disassembler to not try to guess the ABI from | |
5251 | the bfd elf headers, such that, if the user overrides the ABI | |
5252 | of a program linked as NewABI, the disassembly will follow the | |
5253 | register naming conventions specified by the user. */ | |
5254 | info->disassembler_options = "gpr-names=32"; | |
5255 | ||
c906108c | 5256 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5257 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5258 | return print_insn_big_mips (memaddr, info); |
5259 | else | |
5260 | return print_insn_little_mips (memaddr, info); | |
5261 | } | |
5262 | ||
c906108c SS |
5263 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5264 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5265 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5266 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5267 | (if necessary) to point to the actual memory location where the | |
5268 | breakpoint should be inserted. */ | |
5269 | ||
f7ab6ec6 | 5270 | static const unsigned char * |
6d82d43b | 5271 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5272 | { |
d7449b42 | 5273 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5274 | { |
5275 | if (pc_is_mips16 (*pcptr)) | |
5276 | { | |
6d82d43b | 5277 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5278 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5279 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5280 | return mips16_big_breakpoint; |
5281 | } | |
5282 | else | |
5283 | { | |
aaab4dba AC |
5284 | /* The IDT board uses an unusual breakpoint value, and |
5285 | sometimes gets confused when it sees the usual MIPS | |
5286 | breakpoint instruction. */ | |
6d82d43b AC |
5287 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5288 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5289 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5290 | |
c5aa993b | 5291 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5292 | |
5293 | if (strcmp (target_shortname, "mips") == 0) | |
5294 | return idt_big_breakpoint; | |
5295 | else if (strcmp (target_shortname, "ddb") == 0 | |
5296 | || strcmp (target_shortname, "pmon") == 0 | |
5297 | || strcmp (target_shortname, "lsi") == 0) | |
5298 | return pmon_big_breakpoint; | |
5299 | else | |
5300 | return big_breakpoint; | |
5301 | } | |
5302 | } | |
5303 | else | |
5304 | { | |
5305 | if (pc_is_mips16 (*pcptr)) | |
5306 | { | |
6d82d43b | 5307 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5308 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5309 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5310 | return mips16_little_breakpoint; |
5311 | } | |
5312 | else | |
5313 | { | |
6d82d43b AC |
5314 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5315 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5316 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5317 | |
c5aa993b | 5318 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5319 | |
5320 | if (strcmp (target_shortname, "mips") == 0) | |
5321 | return idt_little_breakpoint; | |
5322 | else if (strcmp (target_shortname, "ddb") == 0 | |
5323 | || strcmp (target_shortname, "pmon") == 0 | |
5324 | || strcmp (target_shortname, "lsi") == 0) | |
5325 | return pmon_little_breakpoint; | |
5326 | else | |
5327 | return little_breakpoint; | |
5328 | } | |
5329 | } | |
5330 | } | |
5331 | ||
5332 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5333 | PC, which is either the callee or the caller. There are several | |
5334 | cases which must be handled: | |
5335 | ||
5336 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5337 | target PC is in $31 ($ra). |
c906108c | 5338 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5339 | and the target PC is in $2. |
c906108c | 5340 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5341 | before the jal instruction, this is effectively a call stub |
5342 | and the the target PC is in $2. Otherwise this is effectively | |
5343 | a return stub and the target PC is in $18. | |
c906108c SS |
5344 | |
5345 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5346 | gory details. | |
5347 | ||
5348 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5349 | */ |
c906108c | 5350 | |
757a7cc6 | 5351 | static CORE_ADDR |
acdb74a0 | 5352 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5353 | { |
5354 | char *name; | |
5355 | CORE_ADDR start_addr; | |
5356 | ||
5357 | /* Find the starting address and name of the function containing the PC. */ | |
5358 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5359 | return 0; | |
5360 | ||
5361 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5362 | target PC is in $31 ($ra). */ | |
5363 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5364 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5365 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5366 | |
5367 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5368 | { | |
5369 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5370 | and the target PC is in $2. */ | |
5371 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5372 | return read_signed_register (2); |
c906108c SS |
5373 | |
5374 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5375 | before the jal instruction, this is effectively a call stub |
5376 | and the the target PC is in $2. Otherwise this is effectively | |
5377 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5378 | else if (name[19] == 's' || name[19] == 'd') |
5379 | { | |
5380 | if (pc == start_addr) | |
5381 | { | |
5382 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5383 | stub. Such a stub for a function bar might have a name |
5384 | like __fn_stub_bar, and might look like this: | |
5385 | mfc1 $4,$f13 | |
5386 | mfc1 $5,$f12 | |
5387 | mfc1 $6,$f15 | |
5388 | mfc1 $7,$f14 | |
5389 | la $1,bar (becomes a lui/addiu pair) | |
5390 | jr $1 | |
5391 | So scan down to the lui/addi and extract the target | |
5392 | address from those two instructions. */ | |
c906108c | 5393 | |
6c997a34 | 5394 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5395 | t_inst inst; |
5396 | int i; | |
5397 | ||
5398 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5399 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5400 | 0) | |
c906108c SS |
5401 | return target_pc; |
5402 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5403 | && strcmp (name, "etext") != 0 | |
5404 | && strcmp (name, "_etext") != 0) | |
5405 | return target_pc; | |
5406 | ||
5407 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5408 | The limit on the search is arbitrarily set to 20 |
5409 | instructions. FIXME. */ | |
c906108c SS |
5410 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5411 | { | |
c5aa993b JM |
5412 | inst = mips_fetch_instruction (target_pc); |
5413 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5414 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5415 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5416 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5417 | } |
5418 | ||
5419 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5420 | return target_pc; | |
5421 | } | |
5422 | else | |
5423 | /* This is the 'return' part of a call stub. The return | |
5424 | address is in $r18. */ | |
6c997a34 | 5425 | return read_signed_register (18); |
c906108c SS |
5426 | } |
5427 | } | |
c5aa993b | 5428 | return 0; /* not a stub */ |
c906108c SS |
5429 | } |
5430 | ||
5431 | ||
5432 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5433 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5434 | ||
757a7cc6 | 5435 | static int |
acdb74a0 | 5436 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5437 | { |
5438 | CORE_ADDR start_addr; | |
5439 | ||
5440 | /* Find the starting address of the function containing the PC. If the | |
5441 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5442 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5443 | 0) | |
c906108c SS |
5444 | return 0; |
5445 | ||
5446 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5447 | { | |
5448 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5449 | if (name[19] >= '0' && name[19] <= '9') | |
5450 | return 1; | |
5451 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5452 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5453 | else if (name[19] == 's' || name[19] == 'd') |
5454 | return pc == start_addr; | |
5455 | } | |
5456 | ||
c5aa993b | 5457 | return 0; /* not a stub */ |
c906108c SS |
5458 | } |
5459 | ||
5460 | ||
5461 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5462 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5463 | ||
e41b17f0 | 5464 | static int |
acdb74a0 | 5465 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5466 | { |
5467 | CORE_ADDR start_addr; | |
5468 | ||
5469 | /* Find the starting address of the function containing the PC. */ | |
5470 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5471 | return 0; | |
5472 | ||
5473 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5474 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5475 | || strcmp (name, "__mips16_ret_df") == 0) | |
5476 | return 1; | |
5477 | ||
5478 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5479 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5480 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5481 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5482 | return 1; |
5483 | ||
c5aa993b | 5484 | return 0; /* not a stub */ |
c906108c SS |
5485 | } |
5486 | ||
5487 | ||
5488 | /* Return non-zero if the PC is in a library helper function that should | |
5489 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5490 | ||
5491 | int | |
acdb74a0 | 5492 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5493 | { |
5494 | char *name; | |
5495 | ||
5496 | /* Find the starting address and name of the function containing the PC. */ | |
5497 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5498 | return 0; | |
5499 | ||
5500 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5501 | that we want to ignore. */ | |
5502 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5503 | || strcmp (name, "__mips16_ret_df") == 0); | |
5504 | } | |
5505 | ||
5506 | ||
47a8d4ba AC |
5507 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5508 | the register stored on the stack (32) is different to its real raw | |
5509 | size (64). The below ensures that registers are fetched from the | |
5510 | stack using their ABI size and then stored into the RAW_BUFFER | |
5511 | using their raw size. | |
5512 | ||
5513 | The alternative to adding this function would be to add an ABI | |
5514 | macro - REGISTER_STACK_SIZE(). */ | |
5515 | ||
5516 | static void | |
acdb74a0 | 5517 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5518 | int *optimizedp, |
acdb74a0 AC |
5519 | CORE_ADDR *addrp, |
5520 | struct frame_info *frame, | |
6d82d43b | 5521 | int regnum, enum lval_type *lvalp) |
47a8d4ba | 5522 | { |
795e1e11 AC |
5523 | CORE_ADDR addrx; |
5524 | enum lval_type lvalx; | |
5525 | int optimizedx; | |
6e51443a | 5526 | int realnumx; |
47a8d4ba | 5527 | |
a4b8ebc8 AC |
5528 | /* Always a pseudo. */ |
5529 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5530 | |
795e1e11 AC |
5531 | /* Make certain that all needed parameters are present. */ |
5532 | if (addrp == NULL) | |
5533 | addrp = &addrx; | |
5534 | if (lvalp == NULL) | |
5535 | lvalp = &lvalx; | |
5536 | if (optimizedp == NULL) | |
5537 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5538 | |
5539 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5540 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5541 | In fact, it is so special that it can even only be fetched | |
5542 | using a raw register number! Once this code as been converted | |
5543 | to frame-unwind the problem goes away. */ | |
5544 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5545 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5546 | &realnumx, raw_buffer); | |
5547 | else | |
5548 | /* Get it from the next frame. */ | |
5549 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5550 | regnum, optimizedp, lvalp, addrp, | |
5551 | &realnumx, raw_buffer); | |
47a8d4ba | 5552 | } |
2acceee2 | 5553 | |
f7b9e9fc AC |
5554 | /* Immediately after a function call, return the saved pc. |
5555 | Can't always go through the frames for this because on some machines | |
5556 | the new frame is not set up until the new function executes | |
5557 | some instructions. */ | |
5558 | ||
5559 | static CORE_ADDR | |
5560 | mips_saved_pc_after_call (struct frame_info *frame) | |
5561 | { | |
6c997a34 | 5562 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5563 | } |
5564 | ||
5565 | ||
a4b8ebc8 AC |
5566 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5567 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5568 | |
5569 | static int | |
5570 | mips_stab_reg_to_regnum (int num) | |
5571 | { | |
a4b8ebc8 | 5572 | int regnum; |
2f38ef89 | 5573 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5574 | regnum = num; |
2f38ef89 | 5575 | else if (num >= 38 && num < 70) |
56cea623 | 5576 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5577 | else if (num == 70) |
56cea623 | 5578 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5579 | else if (num == 71) |
56cea623 | 5580 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5581 | else |
a4b8ebc8 AC |
5582 | /* This will hopefully (eventually) provoke a warning. Should |
5583 | we be calling complaint() here? */ | |
5584 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5585 | return NUM_REGS + regnum; | |
88c72b7d AC |
5586 | } |
5587 | ||
2f38ef89 | 5588 | |
a4b8ebc8 AC |
5589 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5590 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5591 | |
5592 | static int | |
2f38ef89 | 5593 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5594 | { |
a4b8ebc8 | 5595 | int regnum; |
2f38ef89 | 5596 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5597 | regnum = num; |
2f38ef89 | 5598 | else if (num >= 32 && num < 64) |
56cea623 | 5599 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5600 | else if (num == 64) |
56cea623 | 5601 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5602 | else if (num == 65) |
56cea623 | 5603 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5604 | else |
a4b8ebc8 AC |
5605 | /* This will hopefully (eventually) provoke a warning. Should we |
5606 | be calling complaint() here? */ | |
5607 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5608 | return NUM_REGS + regnum; | |
5609 | } | |
5610 | ||
5611 | static int | |
5612 | mips_register_sim_regno (int regnum) | |
5613 | { | |
5614 | /* Only makes sense to supply raw registers. */ | |
5615 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5616 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5617 | decide if it is valid. Should instead define a standard sim/gdb | |
5618 | register numbering scheme. */ | |
5619 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5620 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5621 | return regnum; | |
5622 | else | |
6d82d43b | 5623 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5624 | } |
5625 | ||
2f38ef89 | 5626 | |
fc0c74b1 AC |
5627 | /* Convert an integer into an address. By first converting the value |
5628 | into a pointer and then extracting it signed, the address is | |
5629 | guarenteed to be correctly sign extended. */ | |
5630 | ||
5631 | static CORE_ADDR | |
5632 | mips_integer_to_address (struct type *type, void *buf) | |
5633 | { | |
5634 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5635 | LONGEST val = unpack_long (type, buf); | |
5636 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5637 | return extract_signed_integer (tmp, | |
5638 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5639 | } | |
5640 | ||
caaa3122 DJ |
5641 | static void |
5642 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5643 | { | |
5644 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5645 | const char *name = bfd_get_section_name (abfd, sect); | |
5646 | ||
5647 | if (*abip != MIPS_ABI_UNKNOWN) | |
5648 | return; | |
5649 | ||
5650 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5651 | return; | |
5652 | ||
5653 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5654 | *abip = MIPS_ABI_O32; | |
5655 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5656 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5657 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5658 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5659 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5660 | *abip = MIPS_ABI_O64; | |
5661 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5662 | *abip = MIPS_ABI_EABI32; | |
5663 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5664 | *abip = MIPS_ABI_EABI64; | |
5665 | else | |
5666 | warning ("unsupported ABI %s.", name + 8); | |
5667 | } | |
5668 | ||
2e4ebe70 DJ |
5669 | static enum mips_abi |
5670 | global_mips_abi (void) | |
5671 | { | |
5672 | int i; | |
5673 | ||
5674 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5675 | if (mips_abi_strings[i] == mips_abi_string) | |
5676 | return (enum mips_abi) i; | |
5677 | ||
6d82d43b | 5678 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5679 | } |
5680 | ||
c2d11a7d | 5681 | static struct gdbarch * |
6d82d43b | 5682 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5683 | { |
c2d11a7d JM |
5684 | struct gdbarch *gdbarch; |
5685 | struct gdbarch_tdep *tdep; | |
5686 | int elf_flags; | |
2e4ebe70 | 5687 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5688 | int num_regs; |
8d5838b5 | 5689 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5690 | |
ec03c1ac AC |
5691 | /* First of all, extract the elf_flags, if available. */ |
5692 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5693 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5694 | else if (arches != NULL) |
5695 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5696 | else |
5697 | elf_flags = 0; | |
5698 | if (gdbarch_debug) | |
5699 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5700 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5701 | |
102182a9 | 5702 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5703 | switch ((elf_flags & EF_MIPS_ABI)) |
5704 | { | |
5705 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5706 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5707 | break; |
5708 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5709 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5710 | break; |
5711 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5712 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5713 | break; |
5714 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5715 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5716 | break; |
5717 | default: | |
acdb74a0 | 5718 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5719 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5720 | else |
ec03c1ac | 5721 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5722 | break; |
5723 | } | |
acdb74a0 | 5724 | |
caaa3122 | 5725 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5726 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5727 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5728 | |
ec03c1ac AC |
5729 | /* If we have no usefu BFD information, use the ABI from the last |
5730 | MIPS architecture (if there is one). */ | |
5731 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5732 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5733 | |
32a6503c | 5734 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5735 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5736 | && info.bfd_arch_info != NULL |
5737 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5738 | { | |
5739 | switch (info.bfd_arch_info->mach) | |
5740 | { | |
5741 | case bfd_mach_mips3900: | |
ec03c1ac | 5742 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5743 | break; |
5744 | case bfd_mach_mips4100: | |
5745 | case bfd_mach_mips5000: | |
ec03c1ac | 5746 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5747 | break; |
1d06468c EZ |
5748 | case bfd_mach_mips8000: |
5749 | case bfd_mach_mips10000: | |
32a6503c KB |
5750 | /* On Irix, ELF64 executables use the N64 ABI. The |
5751 | pseudo-sections which describe the ABI aren't present | |
5752 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5753 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5754 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5755 | found_abi = MIPS_ABI_N64; |
28d169de | 5756 | else |
ec03c1ac | 5757 | found_abi = MIPS_ABI_N32; |
1d06468c | 5758 | break; |
bf64bfd6 AC |
5759 | } |
5760 | } | |
2e4ebe70 | 5761 | |
ec03c1ac AC |
5762 | if (gdbarch_debug) |
5763 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5764 | found_abi); | |
5765 | ||
5766 | /* What has the user specified from the command line? */ | |
5767 | wanted_abi = global_mips_abi (); | |
5768 | if (gdbarch_debug) | |
5769 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5770 | wanted_abi); | |
2e4ebe70 DJ |
5771 | |
5772 | /* Now that we have found what the ABI for this binary would be, | |
5773 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5774 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5775 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5776 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5777 | mips_abi = found_abi; | |
5778 | else | |
5779 | mips_abi = MIPS_ABI_O32; | |
5780 | if (gdbarch_debug) | |
5781 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5782 | mips_abi); | |
2e4ebe70 | 5783 | |
ec03c1ac | 5784 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5785 | if (gdbarch_debug) |
ec03c1ac AC |
5786 | fprintf_unfiltered (gdb_stdlog, |
5787 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5788 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5789 | |
8d5838b5 AC |
5790 | /* Determine the MIPS FPU type. */ |
5791 | if (!mips_fpu_type_auto) | |
5792 | fpu_type = mips_fpu_type; | |
5793 | else if (info.bfd_arch_info != NULL | |
5794 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5795 | switch (info.bfd_arch_info->mach) | |
5796 | { | |
5797 | case bfd_mach_mips3900: | |
5798 | case bfd_mach_mips4100: | |
5799 | case bfd_mach_mips4111: | |
5800 | fpu_type = MIPS_FPU_NONE; | |
5801 | break; | |
5802 | case bfd_mach_mips4650: | |
5803 | fpu_type = MIPS_FPU_SINGLE; | |
5804 | break; | |
5805 | default: | |
5806 | fpu_type = MIPS_FPU_DOUBLE; | |
5807 | break; | |
5808 | } | |
5809 | else if (arches != NULL) | |
5810 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5811 | else | |
5812 | fpu_type = MIPS_FPU_DOUBLE; | |
5813 | if (gdbarch_debug) | |
5814 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5815 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5816 | |
c2d11a7d JM |
5817 | /* try to find a pre-existing architecture */ |
5818 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5819 | arches != NULL; | |
5820 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5821 | { | |
5822 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5823 | using. */ |
9103eae0 | 5824 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5825 | continue; |
9103eae0 | 5826 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5827 | continue; |
719ec221 AC |
5828 | /* Need to be pedantic about which register virtual size is |
5829 | used. */ | |
5830 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5831 | != mips64_transfers_32bit_regs_p) | |
5832 | continue; | |
8d5838b5 AC |
5833 | /* Be pedantic about which FPU is selected. */ |
5834 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5835 | continue; | |
4be87837 | 5836 | return arches->gdbarch; |
c2d11a7d JM |
5837 | } |
5838 | ||
102182a9 | 5839 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5840 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5841 | gdbarch = gdbarch_alloc (&info, tdep); | |
5842 | tdep->elf_flags = elf_flags; | |
719ec221 | 5843 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5844 | tdep->found_abi = found_abi; |
5845 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5846 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5847 | |
102182a9 | 5848 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5849 | set_gdbarch_short_bit (gdbarch, 16); |
5850 | set_gdbarch_int_bit (gdbarch, 32); | |
5851 | set_gdbarch_float_bit (gdbarch, 32); | |
5852 | set_gdbarch_double_bit (gdbarch, 64); | |
5853 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5854 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5855 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5856 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5857 | |
6d82d43b | 5858 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5859 | mips_elf_make_msymbol_special); |
5860 | ||
16e109ca | 5861 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5862 | { |
16e109ca | 5863 | const char **reg_names; |
56cea623 AC |
5864 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5865 | struct mips_regnum); | |
56cea623 AC |
5866 | if (info.osabi == GDB_OSABI_IRIX) |
5867 | { | |
5868 | regnum->fp0 = 32; | |
5869 | regnum->pc = 64; | |
5870 | regnum->cause = 65; | |
5871 | regnum->badvaddr = 66; | |
5872 | regnum->hi = 67; | |
5873 | regnum->lo = 68; | |
5874 | regnum->fp_control_status = 69; | |
5875 | regnum->fp_implementation_revision = 70; | |
5876 | num_regs = 71; | |
16e109ca | 5877 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5878 | } |
5879 | else | |
5880 | { | |
5881 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5882 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5883 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5884 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5885 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5886 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5887 | regnum->fp_control_status = 70; | |
5888 | regnum->fp_implementation_revision = 71; | |
5889 | num_regs = 90; | |
16e109ca AC |
5890 | if (info.bfd_arch_info != NULL |
5891 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5892 | reg_names = mips_tx39_reg_names; | |
5893 | else | |
5894 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5895 | } |
5896 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5897 | replaced by read_pc? */ | |
5898 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5899 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5900 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5901 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5902 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5903 | tdep->mips_processor_reg_names = reg_names; | |
5904 | tdep->regnum = regnum; | |
56cea623 | 5905 | } |
fe29b929 | 5906 | |
0dadbba0 | 5907 | switch (mips_abi) |
c2d11a7d | 5908 | { |
0dadbba0 | 5909 | case MIPS_ABI_O32: |
25ab4790 | 5910 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5911 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
a5ea2558 | 5912 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5913 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5914 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5915 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5916 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5917 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5918 | set_gdbarch_long_bit (gdbarch, 32); |
5919 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5920 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5921 | break; | |
0dadbba0 | 5922 | case MIPS_ABI_O64: |
25ab4790 | 5923 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
5924 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5925 | mips_o64_store_return_value); | |
5926 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5927 | mips_o64_extract_return_value); | |
a5ea2558 | 5928 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5929 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5930 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5931 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5932 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5933 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5934 | set_gdbarch_long_bit (gdbarch, 32); |
5935 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5936 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6d82d43b AC |
5937 | set_gdbarch_use_struct_convention (gdbarch, |
5938 | always_use_struct_convention); | |
c2d11a7d | 5939 | break; |
0dadbba0 | 5940 | case MIPS_ABI_EABI32: |
25ab4790 | 5941 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5942 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5943 | mips_eabi_store_return_value); | |
5944 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5945 | mips_eabi_extract_return_value); | |
a5ea2558 | 5946 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5947 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5948 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5949 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5950 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5951 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5952 | set_gdbarch_long_bit (gdbarch, 32); |
5953 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5954 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5955 | set_gdbarch_deprecated_reg_struct_has_addr |
5956 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
6d82d43b | 5957 | set_gdbarch_use_struct_convention (gdbarch, |
cb811fe7 | 5958 | mips_eabi_use_struct_convention); |
c2d11a7d | 5959 | break; |
0dadbba0 | 5960 | case MIPS_ABI_EABI64: |
25ab4790 | 5961 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
5962 | set_gdbarch_deprecated_store_return_value (gdbarch, |
5963 | mips_eabi_store_return_value); | |
5964 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
5965 | mips_eabi_extract_return_value); | |
a5ea2558 | 5966 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5967 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5968 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5969 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5970 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5971 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5972 | set_gdbarch_long_bit (gdbarch, 64); |
5973 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5974 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5975 | set_gdbarch_deprecated_reg_struct_has_addr |
5976 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
6d82d43b | 5977 | set_gdbarch_use_struct_convention (gdbarch, |
cb811fe7 | 5978 | mips_eabi_use_struct_convention); |
c2d11a7d | 5979 | break; |
0dadbba0 | 5980 | case MIPS_ABI_N32: |
25ab4790 | 5981 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5982 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
63db5580 | 5983 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5984 | tdep->mips_default_stack_argsize = 8; |
5985 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5986 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5987 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5988 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5989 | set_gdbarch_long_bit (gdbarch, 32); |
5990 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5991 | set_gdbarch_long_long_bit (gdbarch, 64); | |
28d169de KB |
5992 | break; |
5993 | case MIPS_ABI_N64: | |
25ab4790 | 5994 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5995 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de KB |
5996 | tdep->mips_default_saved_regsize = 8; |
5997 | tdep->mips_default_stack_argsize = 8; | |
5998 | tdep->mips_fp_register_double = 1; | |
5999 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 6000 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6001 | tdep->default_mask_address_p = 0; |
6002 | set_gdbarch_long_bit (gdbarch, 64); | |
6003 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6004 | set_gdbarch_long_long_bit (gdbarch, 64); | |
0dadbba0 | 6005 | break; |
c2d11a7d | 6006 | default: |
6d82d43b | 6007 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
6008 | } |
6009 | ||
a5ea2558 AC |
6010 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6011 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6012 | comment: | |
6013 | ||
6014 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6015 | flag in object files because to do so would make it impossible to | |
102182a9 | 6016 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6017 | unnecessarily restrictive. |
361d1df0 | 6018 | |
a5ea2558 AC |
6019 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6020 | but to set this flag before gcc is built with such multilibs will | |
6021 | break too many systems.'' | |
6022 | ||
6023 | But even more unhelpfully, the default linker output target for | |
6024 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6025 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6026 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6027 | this flag to detect 32-bit mode would do the wrong thing given |
6028 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6029 | as 32-bit programs by default. */ |
a5ea2558 | 6030 | |
6c997a34 | 6031 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6032 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 6033 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6034 | |
102182a9 MS |
6035 | /* Add/remove bits from an address. The MIPS needs be careful to |
6036 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6037 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6038 | ||
58dfe9ff AC |
6039 | /* Unwind the frame. */ |
6040 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
23e3c3fc AC |
6041 | #if 0 |
6042 | #else | |
6043 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ | |
6044 | /* Initialize a frame */ | |
6045 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, | |
6046 | mips_find_saved_regs); | |
6047 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, | |
6048 | mips_init_extra_frame_info); | |
10312cc4 | 6049 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 | 6050 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
6d82d43b AC |
6051 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, |
6052 | mips_init_frame_pc_first); | |
23e3c3fc AC |
6053 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
6054 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, | |
6055 | generic_save_dummy_frame_tos); | |
6056 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); | |
6057 | set_gdbarch_frameless_function_invocation (gdbarch, | |
6058 | generic_frameless_function_invocation_not); | |
6059 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); | |
6060 | set_gdbarch_deprecated_get_saved_register (gdbarch, | |
6061 | mips_get_saved_register); | |
6062 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, | |
6063 | mips_saved_pc_after_call); | |
6064 | #endif | |
10312cc4 | 6065 | |
102182a9 | 6066 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6067 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6068 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6069 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6070 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
6071 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6072 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
6073 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6074 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6075 | |
c2d11a7d JM |
6076 | /* MIPS version of CALL_DUMMY */ |
6077 | ||
9710e734 AC |
6078 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6079 | replaced by a command, and all targets will default to on stack | |
6080 | (regardless of the stack's execute status). */ | |
6081 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6082 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6083 | |
87783b8b AC |
6084 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6085 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6086 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6087 | ||
b5d1566e MS |
6088 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6089 | ||
f7b9e9fc AC |
6090 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6091 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6092 | |
6093 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6094 | |
fc0c74b1 AC |
6095 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6096 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6097 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6098 | |
a4b8ebc8 | 6099 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6100 | |
e11c53d2 | 6101 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6102 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6103 | |
e5ab0dce AC |
6104 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6105 | ||
3a3bc038 AC |
6106 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6107 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6108 | need to all be folded into the target vector. Since they are | |
6109 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6110 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6111 | is sitting on? */ | |
6112 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6113 | ||
70f80edf | 6114 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6115 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6116 | |
757a7cc6 MS |
6117 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
6118 | ||
6119 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6120 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6121 | |
4b9b3959 AC |
6122 | return gdbarch; |
6123 | } | |
6124 | ||
2e4ebe70 | 6125 | static void |
6d82d43b | 6126 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6127 | { |
6128 | struct gdbarch_info info; | |
6129 | ||
6130 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6131 | mips_gdbarch_init will take care of the rest. */ | |
6132 | gdbarch_info_init (&info); | |
6133 | gdbarch_update_p (info); | |
6134 | } | |
6135 | ||
ad188201 KB |
6136 | /* Print out which MIPS ABI is in use. */ |
6137 | ||
6138 | static void | |
6139 | show_mips_abi (char *ignore_args, int from_tty) | |
6140 | { | |
6141 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
6142 | printf_filtered |
6143 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
6144 | else |
6145 | { | |
6146 | enum mips_abi global_abi = global_mips_abi (); | |
6147 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6148 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6149 | ||
6150 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
6151 | printf_filtered |
6152 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6153 | actual_abi_str); | |
ad188201 | 6154 | else if (global_abi == actual_abi) |
6d82d43b AC |
6155 | printf_filtered |
6156 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6157 | actual_abi_str); | |
ad188201 KB |
6158 | else |
6159 | { | |
6160 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
6161 | printf_filtered |
6162 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6163 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
6164 | } |
6165 | } | |
6166 | } | |
6167 | ||
4b9b3959 AC |
6168 | static void |
6169 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6170 | { | |
6171 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6172 | if (tdep != NULL) | |
c2d11a7d | 6173 | { |
acdb74a0 AC |
6174 | int ef_mips_arch; |
6175 | int ef_mips_32bitmode; | |
6176 | /* determine the ISA */ | |
6177 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6178 | { | |
6179 | case E_MIPS_ARCH_1: | |
6180 | ef_mips_arch = 1; | |
6181 | break; | |
6182 | case E_MIPS_ARCH_2: | |
6183 | ef_mips_arch = 2; | |
6184 | break; | |
6185 | case E_MIPS_ARCH_3: | |
6186 | ef_mips_arch = 3; | |
6187 | break; | |
6188 | case E_MIPS_ARCH_4: | |
93d56215 | 6189 | ef_mips_arch = 4; |
acdb74a0 AC |
6190 | break; |
6191 | default: | |
93d56215 | 6192 | ef_mips_arch = 0; |
acdb74a0 AC |
6193 | break; |
6194 | } | |
6195 | /* determine the size of a pointer */ | |
6196 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6197 | fprintf_unfiltered (file, |
6198 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6199 | tdep->elf_flags); |
4b9b3959 | 6200 | fprintf_unfiltered (file, |
acdb74a0 AC |
6201 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6202 | ef_mips_32bitmode); | |
6203 | fprintf_unfiltered (file, | |
6204 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6205 | ef_mips_arch); | |
6206 | fprintf_unfiltered (file, | |
6207 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6208 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6209 | fprintf_unfiltered (file, |
6210 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6211 | mips_mask_address_p (tdep), |
4014092b | 6212 | tdep->default_mask_address_p); |
c2d11a7d | 6213 | } |
4b9b3959 AC |
6214 | fprintf_unfiltered (file, |
6215 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6216 | FP_REGISTER_DOUBLE); | |
6217 | fprintf_unfiltered (file, | |
6218 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6219 | MIPS_DEFAULT_FPU_TYPE, | |
6220 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6221 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6222 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6223 | : "???")); | |
6d82d43b | 6224 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
6225 | fprintf_unfiltered (file, |
6226 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6227 | MIPS_FPU_TYPE, | |
6228 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6229 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6230 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6231 | : "???")); | |
4b9b3959 AC |
6232 | fprintf_unfiltered (file, |
6233 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6234 | FP_REGISTER_DOUBLE); | |
4b9b3959 | 6235 | fprintf_unfiltered (file, |
480d3dd2 AC |
6236 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
6237 | mips_stack_argsize (tdep)); | |
6d82d43b | 6238 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
6239 | fprintf_unfiltered (file, |
6240 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 6241 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
6242 | fprintf_unfiltered (file, |
6243 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6244 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6245 | fprintf_unfiltered (file, |
6246 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6247 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6248 | fprintf_unfiltered (file, | |
6249 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6250 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6251 | fprintf_unfiltered (file, |
6252 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6253 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
6254 | fprintf_unfiltered (file, |
6255 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6256 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6257 | fprintf_unfiltered (file, |
6258 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6259 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6260 | fprintf_unfiltered (file, | |
6261 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6262 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6263 | fprintf_unfiltered (file, |
6264 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6265 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6266 | #ifdef MACHINE_CPROC_FP_OFFSET |
6267 | fprintf_unfiltered (file, | |
6268 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6269 | MACHINE_CPROC_FP_OFFSET); | |
6270 | #endif | |
6271 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6272 | fprintf_unfiltered (file, | |
6273 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6274 | MACHINE_CPROC_PC_OFFSET); | |
6275 | #endif | |
6276 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6277 | fprintf_unfiltered (file, | |
6278 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6279 | MACHINE_CPROC_SP_OFFSET); | |
6280 | #endif | |
2475bac3 AC |
6281 | fprintf_unfiltered (file, |
6282 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6283 | MIPS16_INSTLEN); | |
6d82d43b | 6284 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
6285 | fprintf_unfiltered (file, |
6286 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6287 | fprintf_unfiltered (file, | |
6d82d43b | 6288 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 6289 | fprintf_unfiltered (file, |
acdb74a0 AC |
6290 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6291 | MIPS_LAST_ARG_REGNUM, | |
6292 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 6293 | fprintf_unfiltered (file, |
6d82d43b | 6294 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 6295 | fprintf_unfiltered (file, |
480d3dd2 AC |
6296 | "mips_dump_tdep: mips_saved_regsize() = %d\n", |
6297 | mips_saved_regsize (tdep)); | |
2475bac3 | 6298 | fprintf_unfiltered (file, |
6d82d43b | 6299 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
6300 | fprintf_unfiltered (file, |
6301 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6302 | fprintf_unfiltered (file, | |
6303 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6304 | fprintf_unfiltered (file, | |
6305 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
6306 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
6307 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6308 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6309 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6310 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6311 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6312 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6313 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6314 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6315 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
6316 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
6317 | #ifdef SAVED_BYTES |
6318 | fprintf_unfiltered (file, | |
6d82d43b | 6319 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
6320 | #endif |
6321 | #ifdef SAVED_FP | |
6d82d43b | 6322 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6323 | #endif |
6324 | #ifdef SAVED_PC | |
6d82d43b | 6325 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6326 | #endif |
6327 | fprintf_unfiltered (file, | |
6328 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6329 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6330 | fprintf_unfiltered (file, | |
6331 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6332 | fprintf_unfiltered (file, | |
6d82d43b | 6333 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", SIGFRAME_BASE); |
2475bac3 AC |
6334 | fprintf_unfiltered (file, |
6335 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6336 | SIGFRAME_FPREGSAVE_OFF); | |
6337 | fprintf_unfiltered (file, | |
6338 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6339 | SIGFRAME_PC_OFF); | |
6340 | fprintf_unfiltered (file, | |
6341 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6342 | SIGFRAME_REGSAVE_OFF); | |
2475bac3 AC |
6343 | fprintf_unfiltered (file, |
6344 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6345 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6346 | fprintf_unfiltered (file, | |
6347 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6348 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6349 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6350 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6351 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6352 | fprintf_unfiltered (file, |
6353 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6354 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6355 | #ifdef STACK_END_ADDR | |
6356 | fprintf_unfiltered (file, | |
6357 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6358 | STACK_END_ADDR); | |
6359 | #endif | |
6360 | fprintf_unfiltered (file, | |
6361 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6362 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6363 | fprintf_unfiltered (file, | |
6364 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6365 | STEP_SKIPS_DELAY_P); | |
6366 | fprintf_unfiltered (file, | |
6367 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6368 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6369 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6370 | fprintf_unfiltered (file, |
6371 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6372 | fprintf_unfiltered (file, | |
6373 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6374 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6375 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6376 | fprintf_unfiltered (file, |
6377 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6378 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6379 | #ifdef TRACE_CLEAR |
6380 | fprintf_unfiltered (file, | |
6381 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6382 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6383 | #endif | |
6384 | #ifdef TRACE_FLAVOR | |
6385 | fprintf_unfiltered (file, | |
6d82d43b | 6386 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6387 | #endif |
6388 | #ifdef TRACE_FLAVOR_SIZE | |
6389 | fprintf_unfiltered (file, | |
6390 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6391 | TRACE_FLAVOR_SIZE); | |
6392 | #endif | |
6393 | #ifdef TRACE_SET | |
6394 | fprintf_unfiltered (file, | |
6395 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6396 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6397 | #endif |
2475bac3 AC |
6398 | #ifdef UNUSED_REGNUM |
6399 | fprintf_unfiltered (file, | |
6d82d43b | 6400 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6401 | #endif |
6d82d43b | 6402 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6403 | fprintf_unfiltered (file, |
6404 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6405 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6406 | fprintf_unfiltered (file, |
6d82d43b | 6407 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
2475bac3 | 6408 | fprintf_unfiltered (file, |
6d82d43b | 6409 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); |
c2d11a7d JM |
6410 | } |
6411 | ||
6d82d43b | 6412 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6413 | |
c906108c | 6414 | void |
acdb74a0 | 6415 | _initialize_mips_tdep (void) |
c906108c SS |
6416 | { |
6417 | static struct cmd_list_element *mipsfpulist = NULL; | |
6418 | struct cmd_list_element *c; | |
6419 | ||
6d82d43b | 6420 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6421 | if (MIPS_ABI_LAST + 1 |
6422 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6423 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6424 | ||
4b9b3959 | 6425 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6426 | |
a5ea2558 AC |
6427 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6428 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6429 | "Various MIPS specific commands.", | |
6430 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6431 | ||
6432 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6433 | "Various MIPS specific commands.", | |
6434 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6435 | ||
6436 | /* Allow the user to override the saved register size. */ | |
6437 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6438 | class_obscure, |
6439 | size_enums, | |
6440 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6441 | Set size of general purpose registers saved on the stack.\n\ |
6442 | This option can be set to one of:\n\ | |
6443 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6444 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6445 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6446 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6447 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6448 | |
d929b26f AC |
6449 | /* Allow the user to override the argument stack size. */ |
6450 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6451 | class_obscure, | |
6452 | size_enums, | |
1ed2a135 | 6453 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6454 | Set the amount of stack space reserved for each argument.\n\ |
6455 | This option can be set to one of:\n\ | |
6456 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6457 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6458 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6d82d43b | 6459 | target and executable (default)", &setmipscmdlist), &showmipscmdlist); |
d929b26f | 6460 | |
2e4ebe70 DJ |
6461 | /* Allow the user to override the ABI. */ |
6462 | c = add_set_enum_cmd | |
6463 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6464 | "Set the ABI used by this program.\n" | |
6465 | "This option can be set to one of:\n" | |
6466 | " auto - the default ABI associated with the current binary\n" | |
6467 | " o32\n" | |
6d82d43b | 6468 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6469 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6470 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6471 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6472 | |
c906108c SS |
6473 | /* Let the user turn off floating point and set the fence post for |
6474 | heuristic_proc_start. */ | |
6475 | ||
6476 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6477 | "Set use of MIPS floating-point coprocessor.", | |
6478 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6479 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6480 | "Select single-precision MIPS floating-point coprocessor.", | |
6481 | &mipsfpulist); | |
6482 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6483 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6484 | &mipsfpulist); |
6485 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6486 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6487 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6488 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6489 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6490 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6491 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6492 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6493 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6494 | "Select MIPS floating-point coprocessor automatically.", | |
6495 | &mipsfpulist); | |
6496 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6497 | "Show current use of MIPS floating-point coprocessor target.", | |
6498 | &showlist); | |
6499 | ||
c906108c SS |
6500 | /* We really would like to have both "0" and "unlimited" work, but |
6501 | command.c doesn't deal with that. So make it a var_zinteger | |
6502 | because the user can always use "999999" or some such for unlimited. */ | |
6503 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6504 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6505 | Set the distance searched for the start of a function.\n\ |
6506 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6507 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6508 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6509 | /* We need to throw away the frame cache when we set this, since it |
6510 | might change our ability to get backtraces. */ | |
9f60d481 | 6511 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6512 | add_show_from_set (c, &showlist); |
6513 | ||
6514 | /* Allow the user to control whether the upper bits of 64-bit | |
6515 | addresses should be zeroed. */ | |
e9e68a56 AC |
6516 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6517 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6518 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6519 | allow GDB to determine the correct value.\n", "\ | |
6520 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6d82d43b | 6521 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6522 | |
6523 | /* Allow the user to control the size of 32 bit registers within the | |
6524 | raw remote packet. */ | |
719ec221 AC |
6525 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6526 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6527 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6528 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6529 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6530 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
719ec221 | 6531 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ |
43e526b9 JM |
6532 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6533 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6534 | 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); |
9ace0497 AC |
6535 | |
6536 | /* Debug this files internals. */ | |
6537 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6538 | &mips_debug, "Set mips debugging.\n\ | |
6d82d43b | 6539 | When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist); |
c906108c | 6540 | } |