Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
dd824b04 DJ |
63 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
64 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
65 | #define ST0_FR (1 << 26) | |
66 | ||
b0069a17 AC |
67 | /* The sizes of floating point registers. */ |
68 | ||
69 | enum | |
70 | { | |
71 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
72 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
73 | }; | |
74 | ||
0dadbba0 | 75 | |
2e4ebe70 DJ |
76 | static const char *mips_abi_string; |
77 | ||
78 | static const char *mips_abi_strings[] = { | |
79 | "auto", | |
80 | "n32", | |
81 | "o32", | |
28d169de | 82 | "n64", |
2e4ebe70 DJ |
83 | "o64", |
84 | "eabi32", | |
85 | "eabi64", | |
86 | NULL | |
87 | }; | |
88 | ||
cce74817 | 89 | struct frame_extra_info |
6d82d43b AC |
90 | { |
91 | mips_extra_func_info_t proc_desc; | |
92 | int num_args; | |
93 | }; | |
cce74817 | 94 | |
d929b26f AC |
95 | /* Various MIPS ISA options (related to stack analysis) can be |
96 | overridden dynamically. Establish an enum/array for managing | |
97 | them. */ | |
98 | ||
53904c9e AC |
99 | static const char size_auto[] = "auto"; |
100 | static const char size_32[] = "32"; | |
101 | static const char size_64[] = "64"; | |
d929b26f | 102 | |
53904c9e | 103 | static const char *size_enums[] = { |
d929b26f AC |
104 | size_auto, |
105 | size_32, | |
106 | size_64, | |
a5ea2558 AC |
107 | 0 |
108 | }; | |
109 | ||
7a292a7a | 110 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 111 | support single-precision floating-point operations. */ |
c906108c SS |
112 | |
113 | enum mips_fpu_type | |
6d82d43b AC |
114 | { |
115 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
116 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
117 | MIPS_FPU_NONE /* No floating point. */ | |
118 | }; | |
c906108c SS |
119 | |
120 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
121 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
122 | #endif | |
123 | static int mips_fpu_type_auto = 1; | |
124 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 125 | |
9ace0497 | 126 | static int mips_debug = 0; |
7a292a7a | 127 | |
c2d11a7d JM |
128 | /* MIPS specific per-architecture information */ |
129 | struct gdbarch_tdep | |
6d82d43b AC |
130 | { |
131 | /* from the elf header */ | |
132 | int elf_flags; | |
133 | ||
134 | /* mips options */ | |
135 | enum mips_abi mips_abi; | |
136 | enum mips_abi found_abi; | |
137 | enum mips_fpu_type mips_fpu_type; | |
138 | int mips_last_arg_regnum; | |
139 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
140 | int default_mask_address_p; |
141 | /* Is the target using 64-bit raw integer registers but only | |
142 | storing a left-aligned 32-bit value in each? */ | |
143 | int mips64_transfers_32bit_regs_p; | |
144 | /* Indexes for various registers. IRIX and embedded have | |
145 | different values. This contains the "public" fields. Don't | |
146 | add any that do not need to be public. */ | |
147 | const struct mips_regnum *regnum; | |
148 | /* Register names table for the current register set. */ | |
149 | const char **mips_processor_reg_names; | |
150 | }; | |
c2d11a7d | 151 | |
fed7ba43 JB |
152 | static int |
153 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
154 | const char *from) | |
155 | { | |
156 | return 1; | |
157 | } | |
158 | ||
159 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
160 | They are implemented as a pair of 64bit doubles where the high | |
161 | part holds the result of the operation rounded to double, and | |
162 | the low double holds the difference between the exact result and | |
163 | the rounded result. So "high" + "low" contains the result with | |
164 | added precision. Unfortunately, the floatformat structure used | |
165 | by GDB is not powerful enough to describe this format. As a temporary | |
166 | measure, we define a 128bit floatformat that only uses the high part. | |
167 | We lose a bit of precision but that's probably the best we can do | |
168 | for now with the current infrastructure. */ | |
169 | ||
170 | static const struct floatformat floatformat_n32n64_long_double_big = | |
171 | { | |
172 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
173 | floatformat_intbit_no, | |
174 | "floatformat_ieee_double_big", | |
175 | n32n64_floatformat_always_valid | |
176 | }; | |
177 | ||
56cea623 AC |
178 | const struct mips_regnum * |
179 | mips_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return gdbarch_tdep (gdbarch)->regnum; | |
182 | } | |
183 | ||
184 | static int | |
185 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
186 | { | |
187 | return mips_regnum (gdbarch)->fp0 + 12; | |
188 | } | |
189 | ||
0dadbba0 | 190 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 191 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 192 | |
c2d11a7d | 193 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 194 | |
c2d11a7d | 195 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 196 | |
c2d11a7d | 197 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 198 | |
95404a3e AC |
199 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
200 | functions to test, set, or clear bit 0 of addresses. */ | |
201 | ||
202 | static CORE_ADDR | |
203 | is_mips16_addr (CORE_ADDR addr) | |
204 | { | |
205 | return ((addr) & 1); | |
206 | } | |
207 | ||
208 | static CORE_ADDR | |
209 | make_mips16_addr (CORE_ADDR addr) | |
210 | { | |
211 | return ((addr) | 1); | |
212 | } | |
213 | ||
214 | static CORE_ADDR | |
215 | unmake_mips16_addr (CORE_ADDR addr) | |
216 | { | |
217 | return ((addr) & ~1); | |
218 | } | |
219 | ||
22540ece AC |
220 | /* Return the contents of register REGNUM as a signed integer. */ |
221 | ||
222 | static LONGEST | |
223 | read_signed_register (int regnum) | |
224 | { | |
719ec221 | 225 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 226 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
227 | return (extract_signed_integer |
228 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
229 | } |
230 | ||
231 | static LONGEST | |
232 | read_signed_register_pid (int regnum, ptid_t ptid) | |
233 | { | |
234 | ptid_t save_ptid; | |
235 | LONGEST retval; | |
236 | ||
237 | if (ptid_equal (ptid, inferior_ptid)) | |
238 | return read_signed_register (regnum); | |
239 | ||
240 | save_ptid = inferior_ptid; | |
241 | ||
242 | inferior_ptid = ptid; | |
243 | ||
244 | retval = read_signed_register (regnum); | |
245 | ||
246 | inferior_ptid = save_ptid; | |
247 | ||
248 | return retval; | |
249 | } | |
250 | ||
d1973055 KB |
251 | /* Return the MIPS ABI associated with GDBARCH. */ |
252 | enum mips_abi | |
253 | mips_abi (struct gdbarch *gdbarch) | |
254 | { | |
255 | return gdbarch_tdep (gdbarch)->mips_abi; | |
256 | } | |
257 | ||
4246e332 | 258 | int |
1b13c4f6 | 259 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
260 | { |
261 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
262 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
263 | } | |
264 | ||
480d3dd2 AC |
265 | /* Return the currently configured (or set) saved register size. */ |
266 | ||
1b13c4f6 | 267 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 268 | |
d929b26f | 269 | static unsigned int |
13326b4e | 270 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 271 | { |
1b13c4f6 | 272 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
273 | switch (mips_abi (gdbarch)) |
274 | { | |
275 | case MIPS_ABI_EABI32: | |
276 | case MIPS_ABI_O32: | |
277 | return 4; | |
278 | case MIPS_ABI_N32: | |
279 | case MIPS_ABI_N64: | |
280 | case MIPS_ABI_O64: | |
281 | case MIPS_ABI_EABI64: | |
282 | return 8; | |
283 | case MIPS_ABI_UNKNOWN: | |
284 | case MIPS_ABI_LAST: | |
285 | default: | |
286 | internal_error (__FILE__, __LINE__, "bad switch"); | |
287 | } | |
1b13c4f6 | 288 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 289 | return 8; |
1b13c4f6 | 290 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
291 | return 4; |
292 | } | |
293 | ||
71b8ef93 | 294 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 295 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 296 | "info" field is used for this purpose. |
5a89d8aa MS |
297 | |
298 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
299 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
300 | minimal symbol to mark it as a 16-bit function | |
301 | ||
f594e5e9 | 302 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 303 | |
5a89d8aa | 304 | static void |
6d82d43b AC |
305 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
306 | { | |
307 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
308 | { | |
309 | MSYMBOL_INFO (msym) = (char *) | |
310 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
311 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
312 | } | |
5a89d8aa MS |
313 | } |
314 | ||
71b8ef93 MS |
315 | static int |
316 | msymbol_is_special (struct minimal_symbol *msym) | |
317 | { | |
318 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
319 | } | |
320 | ||
88658117 AC |
321 | /* XFER a value from the big/little/left end of the register. |
322 | Depending on the size of the value it might occupy the entire | |
323 | register or just part of it. Make an allowance for this, aligning | |
324 | things accordingly. */ | |
325 | ||
326 | static void | |
327 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
328 | enum bfd_endian endian, bfd_byte * in, |
329 | const bfd_byte * out, int buf_offset) | |
88658117 | 330 | { |
88658117 | 331 | int reg_offset = 0; |
a4b8ebc8 | 332 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
333 | /* Need to transfer the left or right part of the register, based on |
334 | the targets byte order. */ | |
88658117 AC |
335 | switch (endian) |
336 | { | |
337 | case BFD_ENDIAN_BIG: | |
719ec221 | 338 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
339 | break; |
340 | case BFD_ENDIAN_LITTLE: | |
341 | reg_offset = 0; | |
342 | break; | |
6d82d43b | 343 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
344 | reg_offset = 0; |
345 | break; | |
346 | default: | |
347 | internal_error (__FILE__, __LINE__, "bad switch"); | |
348 | } | |
349 | if (mips_debug) | |
cb1d2653 AC |
350 | fprintf_unfiltered (gdb_stderr, |
351 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
352 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
353 | if (mips_debug && out != NULL) |
354 | { | |
355 | int i; | |
cb1d2653 | 356 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 357 | for (i = 0; i < length; i++) |
cb1d2653 | 358 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
359 | } |
360 | if (in != NULL) | |
6d82d43b AC |
361 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
362 | in + buf_offset); | |
88658117 | 363 | if (out != NULL) |
6d82d43b AC |
364 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
365 | out + buf_offset); | |
88658117 AC |
366 | if (mips_debug && in != NULL) |
367 | { | |
368 | int i; | |
cb1d2653 | 369 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 370 | for (i = 0; i < length; i++) |
cb1d2653 | 371 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
372 | } |
373 | if (mips_debug) | |
374 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
375 | } | |
376 | ||
dd824b04 DJ |
377 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
378 | compatiblity mode. A return value of 1 means that we have | |
379 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
380 | ||
381 | static int | |
382 | mips2_fp_compat (void) | |
383 | { | |
384 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
385 | meaningful. */ | |
6d82d43b AC |
386 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
387 | 4) | |
dd824b04 DJ |
388 | return 0; |
389 | ||
390 | #if 0 | |
391 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
392 | in all the places we deal with FP registers. PR gdb/413. */ | |
393 | /* Otherwise check the FR bit in the status register - it controls | |
394 | the FP compatiblity mode. If it is clear we are in compatibility | |
395 | mode. */ | |
396 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
397 | return 1; | |
398 | #endif | |
361d1df0 | 399 | |
dd824b04 DJ |
400 | return 0; |
401 | } | |
402 | ||
d929b26f | 403 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 404 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
405 | data allocated after the registers have run out. */ |
406 | ||
53904c9e | 407 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
408 | |
409 | static unsigned int | |
13326b4e | 410 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
411 | { |
412 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 413 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
414 | else if (mips_stack_argsize_string == size_64) |
415 | return 8; | |
6d82d43b | 416 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
417 | return 4; |
418 | } | |
419 | ||
7a292a7a | 420 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 421 | |
c9343fd1 | 422 | struct mips_frame_cache; |
570b8f7c | 423 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
c9343fd1 AC |
424 | struct frame_info *, |
425 | struct mips_frame_cache *); | |
eec63939 AC |
426 | static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc, |
427 | CORE_ADDR *addrptr); | |
c906108c | 428 | |
a14ed312 | 429 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 430 | |
a14ed312 | 431 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 432 | |
a14ed312 | 433 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 434 | |
177f84a3 | 435 | static CORE_ADDR after_prologue (CORE_ADDR pc); |
c906108c | 436 | |
67b2c998 DJ |
437 | static struct type *mips_float_register_type (void); |
438 | static struct type *mips_double_register_type (void); | |
439 | ||
acdb74a0 AC |
440 | /* The list of available "set mips " and "show mips " commands */ |
441 | ||
442 | static struct cmd_list_element *setmipscmdlist = NULL; | |
443 | static struct cmd_list_element *showmipscmdlist = NULL; | |
444 | ||
5e2e9765 KB |
445 | /* Integer registers 0 thru 31 are handled explicitly by |
446 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
447 | are listed in the followign tables. */ |
448 | ||
6d82d43b AC |
449 | enum |
450 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
451 | |
452 | /* Generic MIPS. */ | |
453 | ||
454 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
455 | "sr", "lo", "hi", "bad", "cause", "pc", |
456 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
457 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
458 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
459 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
460 | "fsr", "fir", "" /*"fp" */ , "", | |
461 | "", "", "", "", "", "", "", "", | |
462 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
463 | }; |
464 | ||
465 | /* Names of IDT R3041 registers. */ | |
466 | ||
467 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
468 | "sr", "lo", "hi", "bad", "cause", "pc", |
469 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
470 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
471 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
472 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
473 | "fsr", "fir", "", /*"fp" */ "", | |
474 | "", "", "bus", "ccfg", "", "", "", "", | |
475 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
476 | }; |
477 | ||
478 | /* Names of tx39 registers. */ | |
479 | ||
480 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
481 | "sr", "lo", "hi", "bad", "cause", "pc", |
482 | "", "", "", "", "", "", "", "", | |
483 | "", "", "", "", "", "", "", "", | |
484 | "", "", "", "", "", "", "", "", | |
485 | "", "", "", "", "", "", "", "", | |
486 | "", "", "", "", | |
487 | "", "", "", "", "", "", "", "", | |
488 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
489 | }; |
490 | ||
491 | /* Names of IRIX registers. */ | |
492 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
493 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
494 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
495 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
496 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
497 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
498 | }; |
499 | ||
cce74817 | 500 | |
5e2e9765 | 501 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 502 | static const char * |
5e2e9765 | 503 | mips_register_name (int regno) |
cce74817 | 504 | { |
691c0433 | 505 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
506 | /* GPR names for all ABIs other than n32/n64. */ |
507 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
508 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
509 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
510 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
511 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
512 | }; |
513 | ||
514 | /* GPR names for n32 and n64 ABIs. */ | |
515 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
516 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
517 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
518 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
519 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
520 | }; |
521 | ||
522 | enum mips_abi abi = mips_abi (current_gdbarch); | |
523 | ||
a4b8ebc8 AC |
524 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
525 | don't make the raw register names visible. */ | |
526 | int rawnum = regno % NUM_REGS; | |
527 | if (regno < NUM_REGS) | |
528 | return ""; | |
529 | ||
5e2e9765 KB |
530 | /* The MIPS integer registers are always mapped from 0 to 31. The |
531 | names of the registers (which reflects the conventions regarding | |
532 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 533 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
534 | { |
535 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 536 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 537 | else |
a4b8ebc8 | 538 | return mips_gpr_names[rawnum]; |
5e2e9765 | 539 | } |
a4b8ebc8 | 540 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
541 | { |
542 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
543 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
544 | } | |
5e2e9765 KB |
545 | else |
546 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 547 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 548 | } |
5e2e9765 | 549 | |
a4b8ebc8 | 550 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 551 | |
a4b8ebc8 AC |
552 | static int |
553 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
554 | struct reggroup *reggroup) | |
555 | { | |
556 | int vector_p; | |
557 | int float_p; | |
558 | int raw_p; | |
559 | int rawnum = regnum % NUM_REGS; | |
560 | int pseudo = regnum / NUM_REGS; | |
561 | if (reggroup == all_reggroup) | |
562 | return pseudo; | |
563 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
564 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
565 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
566 | (gdbarch), as not all architectures are multi-arch. */ | |
567 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 568 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
569 | return 0; |
570 | if (reggroup == float_reggroup) | |
571 | return float_p && pseudo; | |
572 | if (reggroup == vector_reggroup) | |
573 | return vector_p && pseudo; | |
574 | if (reggroup == general_reggroup) | |
575 | return (!vector_p && !float_p) && pseudo; | |
576 | /* Save the pseudo registers. Need to make certain that any code | |
577 | extracting register values from a saved register cache also uses | |
578 | pseudo registers. */ | |
579 | if (reggroup == save_reggroup) | |
580 | return raw_p && pseudo; | |
581 | /* Restore the same pseudo register. */ | |
582 | if (reggroup == restore_reggroup) | |
583 | return raw_p && pseudo; | |
6d82d43b | 584 | return 0; |
a4b8ebc8 AC |
585 | } |
586 | ||
587 | /* Map the symbol table registers which live in the range [1 * | |
588 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 589 | registers. Take care of alignment and size problems. */ |
c5aa993b | 590 | |
a4b8ebc8 AC |
591 | static void |
592 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
593 | int cookednum, void *buf) | |
594 | { | |
47ebcfbe | 595 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 596 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 597 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 598 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
599 | else if (register_size (gdbarch, rawnum) > |
600 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
601 | { |
602 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
603 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
604 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
605 | else | |
606 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
607 | } | |
608 | else | |
609 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
610 | } |
611 | ||
612 | static void | |
6d82d43b AC |
613 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
614 | struct regcache *regcache, int cookednum, | |
615 | const void *buf) | |
a4b8ebc8 | 616 | { |
47ebcfbe | 617 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 618 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 619 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 620 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
621 | else if (register_size (gdbarch, rawnum) > |
622 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
623 | { |
624 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
625 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
626 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
627 | else | |
628 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
629 | } | |
630 | else | |
631 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 632 | } |
c5aa993b | 633 | |
c906108c | 634 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 635 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
636 | |
637 | /* Heuristic_proc_start may hunt through the text section for a long | |
638 | time across a 2400 baud serial line. Allows the user to limit this | |
639 | search. */ | |
640 | ||
641 | static unsigned int heuristic_fence_post = 0; | |
642 | ||
c5aa993b JM |
643 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
644 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
645 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
646 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
647 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
648 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
649 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
650 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
651 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
652 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
653 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
654 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
655 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
656 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
657 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
658 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
659 | ||
46cd78fb | 660 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
661 | register N. NOTE: This defines the pseudo register type so need to |
662 | rebuild the architecture vector. */ | |
43e526b9 JM |
663 | |
664 | static int mips64_transfers_32bit_regs_p = 0; | |
665 | ||
719ec221 AC |
666 | static void |
667 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
668 | struct cmd_list_element *c) | |
43e526b9 | 669 | { |
719ec221 AC |
670 | struct gdbarch_info info; |
671 | gdbarch_info_init (&info); | |
672 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
673 | instead of relying on globals. Doing that would let generic code | |
674 | handle the search for this specific architecture. */ | |
675 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 676 | { |
719ec221 AC |
677 | mips64_transfers_32bit_regs_p = 0; |
678 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 679 | } |
a4b8ebc8 AC |
680 | } |
681 | ||
47ebcfbe | 682 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 683 | |
ff2e87ac AC |
684 | static int |
685 | mips_convert_register_p (int regnum, struct type *type) | |
686 | { | |
687 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 688 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
689 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
690 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 691 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
692 | } |
693 | ||
42c466d7 | 694 | static void |
ff2e87ac AC |
695 | mips_register_to_value (struct frame_info *frame, int regnum, |
696 | struct type *type, void *to) | |
102182a9 | 697 | { |
7f5f525d AC |
698 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
699 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
700 | } |
701 | ||
42c466d7 | 702 | static void |
ff2e87ac AC |
703 | mips_value_to_register (struct frame_info *frame, int regnum, |
704 | struct type *type, const void *from) | |
102182a9 | 705 | { |
ff2e87ac AC |
706 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
707 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
708 | } |
709 | ||
a4b8ebc8 AC |
710 | /* Return the GDB type object for the "standard" data type of data in |
711 | register REG. */ | |
78fde5f8 KB |
712 | |
713 | static struct type * | |
a4b8ebc8 AC |
714 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
715 | { | |
5ef80fb0 | 716 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
717 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
718 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 719 | { |
5ef80fb0 | 720 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 721 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
722 | switch (gdbarch_byte_order (gdbarch)) |
723 | { | |
724 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 725 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
726 | return builtin_type_ieee_single_big; |
727 | else | |
728 | return builtin_type_ieee_double_big; | |
729 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 730 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
731 | return builtin_type_ieee_single_little; |
732 | else | |
733 | return builtin_type_ieee_double_little; | |
734 | case BFD_ENDIAN_UNKNOWN: | |
735 | default: | |
736 | internal_error (__FILE__, __LINE__, "bad switch"); | |
737 | } | |
a6425924 | 738 | } |
d5ac5a39 AC |
739 | else if (regnum < NUM_REGS) |
740 | { | |
741 | /* The raw or ISA registers. These are all sized according to | |
742 | the ISA regsize. */ | |
743 | if (mips_isa_regsize (gdbarch) == 4) | |
744 | return builtin_type_int32; | |
745 | else | |
746 | return builtin_type_int64; | |
747 | } | |
78fde5f8 | 748 | else |
d5ac5a39 AC |
749 | { |
750 | /* The cooked or ABI registers. These are sized according to | |
751 | the ABI (with a few complications). */ | |
752 | if (regnum >= (NUM_REGS | |
753 | + mips_regnum (current_gdbarch)->fp_control_status) | |
754 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
755 | /* The pseudo/cooked view of the embedded registers is always | |
756 | 32-bit. The raw view is handled below. */ | |
757 | return builtin_type_int32; | |
758 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
759 | /* The target, while possibly using a 64-bit register buffer, | |
760 | is only transfering 32-bits of each integer register. | |
761 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
762 | return builtin_type_int32; | |
763 | else if (mips_abi_regsize (gdbarch) == 4) | |
764 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
765 | 32- or 64-bit). */ | |
766 | return builtin_type_int32; | |
767 | else | |
768 | /* 64-bit ABI. */ | |
769 | return builtin_type_int64; | |
770 | } | |
78fde5f8 KB |
771 | } |
772 | ||
bcb0cc15 MS |
773 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
774 | ||
775 | static CORE_ADDR | |
776 | mips_read_sp (void) | |
777 | { | |
f10683bb | 778 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
779 | } |
780 | ||
c906108c | 781 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 782 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
783 | |
784 | static int | |
480d3dd2 | 785 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
786 | { |
787 | switch (mask_address_var) | |
788 | { | |
7f19b9a2 | 789 | case AUTO_BOOLEAN_TRUE: |
4014092b | 790 | return 1; |
7f19b9a2 | 791 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
792 | return 0; |
793 | break; | |
7f19b9a2 | 794 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 795 | return tdep->default_mask_address_p; |
4014092b | 796 | default: |
6d82d43b | 797 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 798 | return -1; |
361d1df0 | 799 | } |
4014092b AC |
800 | } |
801 | ||
802 | static void | |
e9e68a56 | 803 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 804 | { |
480d3dd2 | 805 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
806 | switch (mask_address_var) |
807 | { | |
7f19b9a2 | 808 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
809 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
810 | break; | |
7f19b9a2 | 811 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
812 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
813 | break; | |
7f19b9a2 | 814 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
815 | printf_filtered |
816 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
817 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
818 | break; |
819 | default: | |
6d82d43b | 820 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 821 | break; |
361d1df0 | 822 | } |
4014092b | 823 | } |
c906108c | 824 | |
c906108c SS |
825 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
826 | ||
827 | static int | |
828 | pc_is_mips16 (bfd_vma memaddr) | |
829 | { | |
830 | struct minimal_symbol *sym; | |
831 | ||
832 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 833 | if (is_mips16_addr (memaddr)) |
c906108c SS |
834 | return 1; |
835 | ||
836 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
837 | the high bit of the info field. Use this to decide if the function is | |
838 | MIPS16 or normal MIPS. */ | |
839 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
840 | if (sym) | |
71b8ef93 | 841 | return msymbol_is_special (sym); |
c906108c SS |
842 | else |
843 | return 0; | |
844 | } | |
845 | ||
b2fa5097 | 846 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
847 | all registers should be sign extended for simplicity? */ |
848 | ||
849 | static CORE_ADDR | |
39f77062 | 850 | mips_read_pc (ptid_t ptid) |
6c997a34 | 851 | { |
b6cb9035 AC |
852 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
853 | } | |
854 | ||
58dfe9ff AC |
855 | static CORE_ADDR |
856 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
857 | { | |
edfae063 AC |
858 | return frame_unwind_register_signed (next_frame, |
859 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
860 | } | |
861 | ||
862 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
863 | dummy frame. The frame ID's base needs to match the TOS value | |
864 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
865 | breakpoint. */ | |
866 | ||
867 | static struct frame_id | |
868 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
869 | { | |
f10683bb | 870 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 871 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
872 | } |
873 | ||
b6cb9035 AC |
874 | static void |
875 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
876 | { | |
877 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 878 | } |
c906108c SS |
879 | |
880 | /* This returns the PC of the first inst after the prologue. If we can't | |
881 | find the prologue, then return 0. */ | |
882 | ||
883 | static CORE_ADDR | |
177f84a3 | 884 | after_prologue (CORE_ADDR pc) |
c906108c | 885 | { |
177f84a3 | 886 | mips_extra_func_info_t proc_desc; |
c906108c SS |
887 | struct symtab_and_line sal; |
888 | CORE_ADDR func_addr, func_end; | |
283be873 AC |
889 | CORE_ADDR startaddr = 0; |
890 | ||
891 | /* Pass a NULL next_frame to heuristic_proc_desc. We should not | |
892 | attempt to read the stack pointer from the current machine state, | |
893 | because the current machine state has nothing to do with the | |
894 | information we need from the proc_desc; and the process may or | |
895 | may not exist right now. */ | |
896 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
897 | if (proc_desc) | |
898 | { | |
899 | /* IF this is the topmost frame AND (this proc does not have | |
900 | debugging information OR the PC is in the procedure prologue) | |
901 | THEN create a "heuristic" proc_desc (by analyzing the actual | |
902 | code) to replace the "official" proc_desc. */ | |
903 | struct symtab_and_line val; | |
904 | struct symbol *proc_symbol = | |
905 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); | |
906 | ||
907 | if (proc_symbol) | |
908 | { | |
909 | val = find_pc_line (BLOCK_START | |
910 | (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); | |
911 | val.pc = val.end ? val.end : pc; | |
912 | } | |
913 | if (!proc_symbol || pc < val.pc) | |
914 | { | |
915 | mips_extra_func_info_t found_heuristic = | |
c9343fd1 | 916 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), pc, NULL, NULL); |
283be873 AC |
917 | if (found_heuristic) |
918 | proc_desc = found_heuristic; | |
919 | } | |
920 | } | |
921 | else | |
922 | { | |
923 | if (startaddr == 0) | |
924 | startaddr = heuristic_proc_start (pc); | |
c906108c | 925 | |
c9343fd1 | 926 | proc_desc = heuristic_proc_desc (startaddr, pc, NULL, NULL); |
283be873 | 927 | } |
c906108c SS |
928 | |
929 | if (proc_desc) | |
930 | { | |
931 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 932 | strongly suspect that frameless always means prologueless... */ |
f10683bb | 933 | if (PROC_FRAME_REG (proc_desc) == MIPS_SP_REGNUM |
c906108c SS |
934 | && PROC_FRAME_OFFSET (proc_desc) == 0) |
935 | return 0; | |
936 | } | |
937 | ||
938 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
939 | return 0; /* Unknown */ | |
940 | ||
941 | sal = find_pc_line (func_addr, 0); | |
942 | ||
943 | if (sal.end < func_end) | |
944 | return sal.end; | |
945 | ||
946 | /* The line after the prologue is after the end of the function. In this | |
947 | case, tell the caller to find the prologue the hard way. */ | |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
952 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
953 | set the appropriate bit in the general register mask or float register mask | |
954 | to indicate which register is saved. This is a helper function | |
955 | for mips_find_saved_regs. */ | |
956 | ||
957 | static void | |
acdb74a0 AC |
958 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
959 | unsigned long *float_mask) | |
c906108c SS |
960 | { |
961 | int reg; | |
962 | ||
6d82d43b | 963 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
c906108c SS |
964 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
965 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
966 | { | |
967 | /* It might be possible to use the instruction to | |
c5aa993b JM |
968 | find the offset, rather than the code below which |
969 | is based on things being in a certain order in the | |
970 | frame, but figuring out what the instruction's offset | |
971 | is relative to might be a little tricky. */ | |
c906108c SS |
972 | reg = (inst & 0x001f0000) >> 16; |
973 | *gen_mask |= (1 << reg); | |
974 | } | |
975 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
6d82d43b | 976 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
c5aa993b | 977 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
c906108c SS |
978 | |
979 | { | |
980 | reg = ((inst & 0x001f0000) >> 16); | |
981 | *float_mask |= (1 << reg); | |
982 | } | |
983 | } | |
984 | ||
985 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
986 | set the appropriate bit in the general register or float register mask | |
987 | to indicate which register is saved. This is a helper function | |
988 | for mips_find_saved_regs. */ | |
989 | ||
990 | static void | |
acdb74a0 | 991 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 992 | { |
c5aa993b | 993 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
994 | { |
995 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
996 | *gen_mask |= (1 << reg); | |
997 | } | |
c5aa993b | 998 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
999 | { |
1000 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1001 | *gen_mask |= (1 << reg); | |
1002 | } | |
c5aa993b | 1003 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
1004 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
1005 | *gen_mask |= (1 << RA_REGNUM); | |
1006 | } | |
1007 | ||
1008 | ||
1009 | /* Fetch and return instruction from the specified location. If the PC | |
1010 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1011 | ||
1012 | static t_inst | |
acdb74a0 | 1013 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
1014 | { |
1015 | char buf[MIPS_INSTLEN]; | |
1016 | int instlen; | |
1017 | int status; | |
1018 | ||
1019 | if (pc_is_mips16 (addr)) | |
1020 | { | |
1021 | instlen = MIPS16_INSTLEN; | |
95404a3e | 1022 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1023 | } |
1024 | else | |
c5aa993b | 1025 | instlen = MIPS_INSTLEN; |
1f602b35 | 1026 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
1027 | if (status) |
1028 | memory_error (status, addr); | |
1029 | return extract_unsigned_integer (buf, instlen); | |
1030 | } | |
1031 | ||
edfae063 AC |
1032 | static ULONGEST |
1033 | mips16_fetch_instruction (CORE_ADDR addr) | |
1034 | { | |
1035 | char buf[MIPS_INSTLEN]; | |
1036 | int instlen; | |
1037 | int status; | |
1038 | ||
1039 | instlen = MIPS16_INSTLEN; | |
1040 | addr = unmake_mips16_addr (addr); | |
1f602b35 | 1041 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
1042 | if (status) |
1043 | memory_error (status, addr); | |
1044 | return extract_unsigned_integer (buf, instlen); | |
1045 | } | |
1046 | ||
1047 | static ULONGEST | |
1048 | mips32_fetch_instruction (CORE_ADDR addr) | |
1049 | { | |
1050 | char buf[MIPS_INSTLEN]; | |
1051 | int instlen; | |
1052 | int status; | |
1053 | instlen = MIPS_INSTLEN; | |
1f602b35 | 1054 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
1055 | if (status) |
1056 | memory_error (status, addr); | |
1057 | return extract_unsigned_integer (buf, instlen); | |
1058 | } | |
1059 | ||
c906108c SS |
1060 | |
1061 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
1062 | #define mips32_op(x) (x >> 26) |
1063 | #define itype_op(x) (x >> 26) | |
1064 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1065 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1066 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1067 | |
e135b889 DJ |
1068 | #define jtype_op(x) (x >> 26) |
1069 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1070 | |
e135b889 DJ |
1071 | #define rtype_op(x) (x >> 26) |
1072 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1073 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1074 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1075 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1076 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1077 | |
1078 | static CORE_ADDR | |
c5aa993b JM |
1079 | mips32_relative_offset (unsigned long inst) |
1080 | { | |
1081 | long x; | |
1082 | x = itype_immediate (inst); | |
1083 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1084 | { |
c5aa993b | 1085 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1086 | } |
c5aa993b JM |
1087 | x = x << 2; |
1088 | return x; | |
c906108c SS |
1089 | } |
1090 | ||
1091 | /* Determine whate to set a single step breakpoint while considering | |
1092 | branch prediction */ | |
5a89d8aa | 1093 | static CORE_ADDR |
c5aa993b JM |
1094 | mips32_next_pc (CORE_ADDR pc) |
1095 | { | |
1096 | unsigned long inst; | |
1097 | int op; | |
1098 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1099 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1100 | { |
e135b889 | 1101 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1102 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1103 | { |
e135b889 | 1104 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1105 | switch (op) |
1106 | { | |
e135b889 DJ |
1107 | case 0: /* BEQL */ |
1108 | goto equal_branch; | |
1109 | case 1: /* BNEL */ | |
1110 | goto neq_branch; | |
1111 | case 2: /* BLEZL */ | |
1112 | goto less_branch; | |
1113 | case 3: /* BGTZ */ | |
1114 | goto greater_branch; | |
c5aa993b JM |
1115 | default: |
1116 | pc += 4; | |
c906108c SS |
1117 | } |
1118 | } | |
e135b889 | 1119 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1120 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1121 | { |
1122 | int tf = itype_rt (inst) & 0x01; | |
1123 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1124 | int fcrcs = |
1125 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1126 | fp_control_status); | |
e135b889 DJ |
1127 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1128 | ||
1129 | if (((cond >> cnum) & 0x01) == tf) | |
1130 | pc += mips32_relative_offset (inst) + 4; | |
1131 | else | |
1132 | pc += 8; | |
1133 | } | |
c5aa993b JM |
1134 | else |
1135 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1136 | } |
1137 | else | |
c5aa993b JM |
1138 | { /* This gets way messy */ |
1139 | ||
c906108c | 1140 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1141 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1142 | { |
c5aa993b JM |
1143 | case 0: /* SPECIAL */ |
1144 | op = rtype_funct (inst); | |
1145 | switch (op) | |
1146 | { | |
1147 | case 8: /* JR */ | |
1148 | case 9: /* JALR */ | |
6c997a34 AC |
1149 | /* Set PC to that address */ |
1150 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1151 | break; |
1152 | default: | |
1153 | pc += 4; | |
1154 | } | |
1155 | ||
6d82d43b | 1156 | break; /* end SPECIAL */ |
c5aa993b | 1157 | case 1: /* REGIMM */ |
c906108c | 1158 | { |
e135b889 DJ |
1159 | op = itype_rt (inst); /* branch condition */ |
1160 | switch (op) | |
c906108c | 1161 | { |
c5aa993b | 1162 | case 0: /* BLTZ */ |
e135b889 DJ |
1163 | case 2: /* BLTZL */ |
1164 | case 16: /* BLTZAL */ | |
c5aa993b | 1165 | case 18: /* BLTZALL */ |
c906108c | 1166 | less_branch: |
6c997a34 | 1167 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1168 | pc += mips32_relative_offset (inst) + 4; |
1169 | else | |
1170 | pc += 8; /* after the delay slot */ | |
1171 | break; | |
e135b889 | 1172 | case 1: /* BGEZ */ |
c5aa993b JM |
1173 | case 3: /* BGEZL */ |
1174 | case 17: /* BGEZAL */ | |
1175 | case 19: /* BGEZALL */ | |
6c997a34 | 1176 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1177 | pc += mips32_relative_offset (inst) + 4; |
1178 | else | |
1179 | pc += 8; /* after the delay slot */ | |
1180 | break; | |
e135b889 | 1181 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1182 | default: |
1183 | pc += 4; | |
c906108c SS |
1184 | } |
1185 | } | |
6d82d43b | 1186 | break; /* end REGIMM */ |
c5aa993b JM |
1187 | case 2: /* J */ |
1188 | case 3: /* JAL */ | |
1189 | { | |
1190 | unsigned long reg; | |
1191 | reg = jtype_target (inst) << 2; | |
e135b889 | 1192 | /* Upper four bits get never changed... */ |
c5aa993b | 1193 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1194 | } |
c5aa993b JM |
1195 | break; |
1196 | /* FIXME case JALX : */ | |
1197 | { | |
1198 | unsigned long reg; | |
1199 | reg = jtype_target (inst) << 2; | |
1200 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1201 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1202 | } | |
c5aa993b | 1203 | break; /* The new PC will be alternate mode */ |
e135b889 | 1204 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1205 | equal_branch: |
6c997a34 AC |
1206 | if (read_signed_register (itype_rs (inst)) == |
1207 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1208 | pc += mips32_relative_offset (inst) + 4; |
1209 | else | |
1210 | pc += 8; | |
1211 | break; | |
e135b889 | 1212 | case 5: /* BNE, BNEL */ |
c5aa993b | 1213 | neq_branch: |
6c997a34 | 1214 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1215 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1216 | pc += mips32_relative_offset (inst) + 4; |
1217 | else | |
1218 | pc += 8; | |
1219 | break; | |
e135b889 | 1220 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1221 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1222 | pc += mips32_relative_offset (inst) + 4; |
1223 | else | |
1224 | pc += 8; | |
1225 | break; | |
1226 | case 7: | |
e135b889 DJ |
1227 | default: |
1228 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1229 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1230 | pc += mips32_relative_offset (inst) + 4; |
1231 | else | |
1232 | pc += 8; | |
1233 | break; | |
c5aa993b JM |
1234 | } /* switch */ |
1235 | } /* else */ | |
1236 | return pc; | |
1237 | } /* mips32_next_pc */ | |
c906108c SS |
1238 | |
1239 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1240 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1241 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1242 | We dont want to set a single step instruction on the extend instruction | |
1243 | either. | |
c5aa993b | 1244 | */ |
c906108c SS |
1245 | |
1246 | /* Lots of mips16 instruction formats */ | |
1247 | /* Predicting jumps requires itype,ritype,i8type | |
1248 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1249 | */ |
c906108c SS |
1250 | enum mips16_inst_fmts |
1251 | { | |
c5aa993b JM |
1252 | itype, /* 0 immediate 5,10 */ |
1253 | ritype, /* 1 5,3,8 */ | |
1254 | rrtype, /* 2 5,3,3,5 */ | |
1255 | rritype, /* 3 5,3,3,5 */ | |
1256 | rrrtype, /* 4 5,3,3,3,2 */ | |
1257 | rriatype, /* 5 5,3,3,1,4 */ | |
1258 | shifttype, /* 6 5,3,3,3,2 */ | |
1259 | i8type, /* 7 5,3,8 */ | |
1260 | i8movtype, /* 8 5,3,3,5 */ | |
1261 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1262 | i64type, /* 10 5,3,8 */ | |
1263 | ri64type, /* 11 5,3,3,5 */ | |
1264 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1265 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1266 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1267 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1268 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1269 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1270 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1271 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1272 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1273 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1274 | }; | |
12f02c2a AC |
1275 | /* I am heaping all the fields of the formats into one structure and |
1276 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1277 | struct upk_mips16 |
6d82d43b AC |
1278 | { |
1279 | CORE_ADDR offset; | |
1280 | unsigned int regx; /* Function in i8 type */ | |
1281 | unsigned int regy; | |
1282 | }; | |
c906108c SS |
1283 | |
1284 | ||
12f02c2a AC |
1285 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1286 | for the bits which make up the immediatate extension. */ | |
c906108c | 1287 | |
12f02c2a AC |
1288 | static CORE_ADDR |
1289 | extended_offset (unsigned int extension) | |
c906108c | 1290 | { |
12f02c2a | 1291 | CORE_ADDR value; |
c5aa993b JM |
1292 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1293 | value = value << 6; | |
1294 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1295 | value = value << 5; | |
1296 | value |= extension & 0x01f; /* extract 4:0 */ | |
1297 | return value; | |
c906108c SS |
1298 | } |
1299 | ||
1300 | /* Only call this function if you know that this is an extendable | |
1301 | instruction, It wont malfunction, but why make excess remote memory references? | |
1302 | If the immediate operands get sign extended or somthing, do it after | |
1303 | the extension is performed. | |
c5aa993b | 1304 | */ |
c906108c SS |
1305 | /* FIXME: Every one of these cases needs to worry about sign extension |
1306 | when the offset is to be used in relative addressing */ | |
1307 | ||
1308 | ||
12f02c2a | 1309 | static unsigned int |
c5aa993b | 1310 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1311 | { |
c5aa993b JM |
1312 | char buf[8]; |
1313 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1314 | target_read_memory (pc, buf, 2); | |
1315 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1316 | } |
1317 | ||
1318 | static void | |
c5aa993b | 1319 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1320 | unsigned int extension, |
1321 | unsigned int inst, | |
6d82d43b | 1322 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1323 | { |
12f02c2a AC |
1324 | CORE_ADDR offset; |
1325 | int regx; | |
1326 | int regy; | |
1327 | switch (insn_format) | |
c906108c | 1328 | { |
c5aa993b | 1329 | case itype: |
c906108c | 1330 | { |
12f02c2a AC |
1331 | CORE_ADDR value; |
1332 | if (extension) | |
c5aa993b JM |
1333 | { |
1334 | value = extended_offset (extension); | |
1335 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1336 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1337 | } |
1338 | else | |
c5aa993b | 1339 | { |
12f02c2a | 1340 | value = inst & 0x7ff; |
c5aa993b | 1341 | /* FIXME : Consider sign extension */ |
c906108c | 1342 | } |
12f02c2a AC |
1343 | offset = value; |
1344 | regx = -1; | |
1345 | regy = -1; | |
c906108c | 1346 | } |
c5aa993b JM |
1347 | break; |
1348 | case ritype: | |
1349 | case i8type: | |
1350 | { /* A register identifier and an offset */ | |
c906108c SS |
1351 | /* Most of the fields are the same as I type but the |
1352 | immediate value is of a different length */ | |
12f02c2a AC |
1353 | CORE_ADDR value; |
1354 | if (extension) | |
c906108c | 1355 | { |
c5aa993b JM |
1356 | value = extended_offset (extension); |
1357 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1358 | value |= inst & 0xff; /* eleven bits from instruction */ |
1359 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1360 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1361 | { | |
1362 | value &= ~0x3fff; /* remove the sign bit */ | |
1363 | value = -value; | |
c906108c SS |
1364 | } |
1365 | } | |
c5aa993b JM |
1366 | else |
1367 | { | |
12f02c2a AC |
1368 | value = inst & 0xff; /* 8 bits */ |
1369 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1370 | /* FIXME: Do sign extension , this format needs it */ |
1371 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1372 | { | |
1373 | value &= 0xef; /* remove the sign bit */ | |
1374 | value = -value; | |
1375 | } | |
c5aa993b | 1376 | } |
12f02c2a AC |
1377 | offset = value; |
1378 | regy = -1; | |
c5aa993b | 1379 | break; |
c906108c | 1380 | } |
c5aa993b | 1381 | case jalxtype: |
c906108c | 1382 | { |
c5aa993b | 1383 | unsigned long value; |
12f02c2a AC |
1384 | unsigned int nexthalf; |
1385 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1386 | value = value << 16; |
1387 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1388 | value |= nexthalf; | |
12f02c2a AC |
1389 | offset = value; |
1390 | regx = -1; | |
1391 | regy = -1; | |
c5aa993b | 1392 | break; |
c906108c SS |
1393 | } |
1394 | default: | |
6d82d43b | 1395 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1396 | } |
12f02c2a AC |
1397 | upk->offset = offset; |
1398 | upk->regx = regx; | |
1399 | upk->regy = regy; | |
c906108c SS |
1400 | } |
1401 | ||
1402 | ||
c5aa993b JM |
1403 | static CORE_ADDR |
1404 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1405 | { |
c5aa993b | 1406 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1407 | } |
1408 | ||
12f02c2a AC |
1409 | static CORE_ADDR |
1410 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1411 | unsigned int extension, unsigned int insn) |
c906108c | 1412 | { |
12f02c2a AC |
1413 | int op = (insn >> 11); |
1414 | switch (op) | |
c906108c | 1415 | { |
6d82d43b | 1416 | case 2: /* Branch */ |
12f02c2a AC |
1417 | { |
1418 | CORE_ADDR offset; | |
1419 | struct upk_mips16 upk; | |
1420 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1421 | offset = upk.offset; | |
1422 | if (offset & 0x800) | |
1423 | { | |
1424 | offset &= 0xeff; | |
1425 | offset = -offset; | |
1426 | } | |
1427 | pc += (offset << 1) + 2; | |
1428 | break; | |
1429 | } | |
6d82d43b | 1430 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1431 | { |
1432 | struct upk_mips16 upk; | |
1433 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1434 | pc = add_offset_16 (pc, upk.offset); | |
1435 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1436 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1437 | else | |
1438 | pc |= 0x01; | |
1439 | break; | |
1440 | } | |
6d82d43b | 1441 | case 4: /* beqz */ |
12f02c2a AC |
1442 | { |
1443 | struct upk_mips16 upk; | |
1444 | int reg; | |
1445 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1446 | reg = read_signed_register (upk.regx); | |
1447 | if (reg == 0) | |
1448 | pc += (upk.offset << 1) + 2; | |
1449 | else | |
1450 | pc += 2; | |
1451 | break; | |
1452 | } | |
6d82d43b | 1453 | case 5: /* bnez */ |
12f02c2a AC |
1454 | { |
1455 | struct upk_mips16 upk; | |
1456 | int reg; | |
1457 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1458 | reg = read_signed_register (upk.regx); | |
1459 | if (reg != 0) | |
1460 | pc += (upk.offset << 1) + 2; | |
1461 | else | |
1462 | pc += 2; | |
1463 | break; | |
1464 | } | |
6d82d43b | 1465 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1466 | { |
1467 | struct upk_mips16 upk; | |
1468 | int reg; | |
1469 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1470 | /* upk.regx contains the opcode */ | |
1471 | reg = read_signed_register (24); /* Test register is 24 */ | |
1472 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1473 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1474 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1475 | pc += (upk.offset << 1) + 2; | |
1476 | else | |
1477 | pc += 2; | |
1478 | break; | |
1479 | } | |
6d82d43b | 1480 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1481 | { |
1482 | struct upk_mips16 upk; | |
1483 | /* upk.fmt = rrtype; */ | |
1484 | op = insn & 0x1f; | |
1485 | if (op == 0) | |
c5aa993b | 1486 | { |
12f02c2a AC |
1487 | int reg; |
1488 | upk.regx = (insn >> 8) & 0x07; | |
1489 | upk.regy = (insn >> 5) & 0x07; | |
1490 | switch (upk.regy) | |
c5aa993b | 1491 | { |
12f02c2a AC |
1492 | case 0: |
1493 | reg = upk.regx; | |
1494 | break; | |
1495 | case 1: | |
1496 | reg = 31; | |
6d82d43b | 1497 | break; /* Function return instruction */ |
12f02c2a AC |
1498 | case 2: |
1499 | reg = upk.regx; | |
1500 | break; | |
1501 | default: | |
1502 | reg = 31; | |
6d82d43b | 1503 | break; /* BOGUS Guess */ |
c906108c | 1504 | } |
12f02c2a | 1505 | pc = read_signed_register (reg); |
c906108c | 1506 | } |
12f02c2a | 1507 | else |
c5aa993b | 1508 | pc += 2; |
12f02c2a AC |
1509 | break; |
1510 | } | |
1511 | case 30: | |
1512 | /* This is an instruction extension. Fetch the real instruction | |
1513 | (which follows the extension) and decode things based on | |
1514 | that. */ | |
1515 | { | |
1516 | pc += 2; | |
1517 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1518 | break; | |
1519 | } | |
1520 | default: | |
1521 | { | |
1522 | pc += 2; | |
1523 | break; | |
1524 | } | |
c906108c | 1525 | } |
c5aa993b | 1526 | return pc; |
12f02c2a | 1527 | } |
c906108c | 1528 | |
5a89d8aa | 1529 | static CORE_ADDR |
12f02c2a AC |
1530 | mips16_next_pc (CORE_ADDR pc) |
1531 | { | |
1532 | unsigned int insn = fetch_mips_16 (pc); | |
1533 | return extended_mips16_next_pc (pc, 0, insn); | |
1534 | } | |
1535 | ||
1536 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1537 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1538 | It works by decoding the current instruction and predicting where a |
1539 | branch will go. This isnt hard because all the data is available. | |
1540 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1541 | CORE_ADDR |
1542 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1543 | { |
c5aa993b JM |
1544 | if (pc & 0x01) |
1545 | return mips16_next_pc (pc); | |
1546 | else | |
1547 | return mips32_next_pc (pc); | |
12f02c2a | 1548 | } |
c906108c | 1549 | |
edfae063 AC |
1550 | struct mips_frame_cache |
1551 | { | |
1552 | CORE_ADDR base; | |
1553 | struct trad_frame_saved_reg *saved_regs; | |
1554 | }; | |
1555 | ||
1556 | ||
1557 | static struct mips_frame_cache * | |
1558 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1559 | { | |
0d5febcc | 1560 | CORE_ADDR startaddr = 0; |
edfae063 AC |
1561 | mips_extra_func_info_t proc_desc; |
1562 | struct mips_frame_cache *cache; | |
1563 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1564 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1565 | /* r0 bit means kernel trap */ | |
1566 | int kernel_trap; | |
1567 | /* What registers have been saved? Bitmasks. */ | |
1568 | unsigned long gen_mask, float_mask; | |
1569 | ||
1570 | if ((*this_cache) != NULL) | |
1571 | return (*this_cache); | |
1572 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1573 | (*this_cache) = cache; | |
1574 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1575 | ||
1576 | /* Get the mdebug proc descriptor. */ | |
0d5febcc AC |
1577 | proc_desc = non_heuristic_proc_desc (frame_pc_unwind (next_frame), |
1578 | &startaddr); | |
1579 | /* Must be true. This is only called when the sniffer detected a | |
1580 | proc descriptor. */ | |
1581 | gdb_assert (proc_desc != NULL); | |
edfae063 AC |
1582 | |
1583 | /* Extract the frame's base. */ | |
1584 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1585 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1586 | ||
1587 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1588 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1589 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1590 | ||
9733cfe1 AC |
1591 | /* Must be true. The in_prologue case is left for the heuristic |
1592 | unwinder. This is always used on kernel traps. */ | |
1593 | gdb_assert (!in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1594 | || kernel_trap); | |
edfae063 AC |
1595 | |
1596 | /* Fill in the offsets for the registers which gen_mask says were | |
1597 | saved. */ | |
1598 | { | |
4fbbbd07 | 1599 | CORE_ADDR reg_position = (cache->base + PROC_REG_OFFSET (proc_desc)); |
edfae063 | 1600 | int ireg; |
4fbbbd07 | 1601 | |
edfae063 AC |
1602 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
1603 | if (gen_mask & 0x80000000) | |
1604 | { | |
1605 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1606 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1607 | } |
1608 | } | |
1609 | ||
1610 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1611 | order of that normally used by gcc. Therefore, we have to fetch | |
1612 | the first instruction of the function, and if it's an entry | |
1613 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1614 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1615 | { | |
1616 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1617 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1618 | /* entry */ | |
1619 | { | |
1620 | int reg; | |
1621 | int sreg_count = (inst >> 6) & 3; | |
1622 | ||
1623 | /* Check if the ra register was pushed on the stack. */ | |
1624 | CORE_ADDR reg_position = (cache->base | |
1625 | + PROC_REG_OFFSET (proc_desc)); | |
1626 | if (inst & 0x20) | |
13326b4e | 1627 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1628 | |
1629 | /* Check if the s0 and s1 registers were pushed on the | |
1630 | stack. */ | |
1631 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1632 | check. */ | |
1633 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1634 | { | |
1635 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1636 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1637 | } |
1638 | } | |
1639 | } | |
1640 | ||
1641 | /* Fill in the offsets for the registers which float_mask says were | |
1642 | saved. */ | |
1643 | { | |
1644 | CORE_ADDR reg_position = (cache->base | |
1645 | + PROC_FREG_OFFSET (proc_desc)); | |
1646 | int ireg; | |
1647 | /* Fill in the offsets for the float registers which float_mask | |
1648 | says were saved. */ | |
1649 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1650 | if (float_mask & 0x80000000) | |
1651 | { | |
13326b4e | 1652 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1653 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1654 | { | |
1655 | /* On a big endian 32 bit ABI, floating point registers | |
1656 | are paired to form doubles such that the most | |
1657 | significant part is in $f[N+1] and the least | |
1658 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1659 | registers are also spilled as a pair and stored as a | |
1660 | double. | |
1661 | ||
1662 | When little-endian the least significant part is | |
1663 | stored first leading to the memory order $f[N] and | |
1664 | then $f[N+1]. | |
1665 | ||
1666 | Unfortunately, when big-endian the most significant | |
1667 | part of the double is stored first, and the least | |
1668 | significant is stored second. This leads to the | |
1669 | registers being ordered in memory as firt $f[N+1] and | |
1670 | then $f[N]. | |
1671 | ||
1672 | For the big-endian case make certain that the | |
1673 | addresses point at the correct (swapped) locations | |
1674 | $f[N] and $f[N+1] pair (keep in mind that | |
1675 | reg_position is decremented each time through the | |
1676 | loop). */ | |
1677 | if ((ireg & 1)) | |
1678 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1679 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1680 | else |
1681 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1682 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1683 | } |
1684 | else | |
1685 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1686 | .addr = reg_position; | |
13326b4e | 1687 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1688 | } |
1689 | ||
1690 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1691 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1692 | } | |
1693 | ||
1694 | /* SP_REGNUM, contains the value and not the address. */ | |
f10683bb | 1695 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); |
edfae063 AC |
1696 | |
1697 | return (*this_cache); | |
1698 | } | |
1699 | ||
1700 | static void | |
1701 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1702 | struct frame_id *this_id) | |
1703 | { | |
1704 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1705 | this_cache); | |
1706 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1707 | } | |
1708 | ||
1709 | static void | |
1710 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1711 | void **this_cache, | |
1712 | int regnum, int *optimizedp, | |
1713 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1714 | int *realnump, void *valuep) | |
1715 | { | |
1716 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1717 | this_cache); | |
1f67027d AC |
1718 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
1719 | optimizedp, lvalp, addrp, realnump, valuep); | |
edfae063 AC |
1720 | } |
1721 | ||
1722 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1723 | { | |
1724 | NORMAL_FRAME, | |
1725 | mips_mdebug_frame_this_id, | |
1726 | mips_mdebug_frame_prev_register | |
1727 | }; | |
1728 | ||
1729 | static const struct frame_unwind * | |
1730 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1731 | { | |
eec63939 AC |
1732 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1733 | CORE_ADDR startaddr = 0; | |
1734 | mips_extra_func_info_t proc_desc; | |
1735 | int kernel_trap; | |
1736 | ||
1737 | /* Only use the mdebug frame unwinder on mdebug frames where all the | |
1738 | registers have been saved. Leave hard cases such as no mdebug or | |
1739 | in prologue for the heuristic unwinders. */ | |
1740 | ||
1741 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1742 | if (proc_desc == NULL) | |
1743 | return NULL; | |
1744 | ||
1745 | /* Not sure exactly what kernel_trap means, but if it means the | |
1746 | kernel saves the registers without a prologue doing it, we better | |
1747 | not examine the prologue to see whether registers have been saved | |
1748 | yet. */ | |
1749 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1750 | if (kernel_trap) | |
1751 | return &mips_mdebug_frame_unwind; | |
1752 | ||
1753 | /* In any frame other than the innermost or a frame interrupted by a | |
1754 | signal, we assume that all registers have been saved. This | |
1755 | assumes that all register saves in a function happen before the | |
1756 | first function call. */ | |
1757 | if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc))) | |
1758 | return &mips_mdebug_frame_unwind; | |
1759 | ||
1760 | return NULL; | |
edfae063 AC |
1761 | } |
1762 | ||
1763 | static CORE_ADDR | |
1764 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1765 | void **this_cache) | |
1766 | { | |
1767 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1768 | this_cache); | |
1769 | return info->base; | |
1770 | } | |
1771 | ||
1772 | static const struct frame_base mips_mdebug_frame_base = { | |
1773 | &mips_mdebug_frame_unwind, | |
1774 | mips_mdebug_frame_base_address, | |
1775 | mips_mdebug_frame_base_address, | |
1776 | mips_mdebug_frame_base_address | |
1777 | }; | |
1778 | ||
1779 | static const struct frame_base * | |
1780 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1781 | { | |
eec63939 AC |
1782 | if (mips_mdebug_frame_sniffer (next_frame) != NULL) |
1783 | return &mips_mdebug_frame_base; | |
1784 | else | |
1785 | return NULL; | |
1786 | } | |
1787 | ||
45c9dd44 AC |
1788 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1789 | Procedures that use the 32-bit instruction set are handled by the | |
1790 | mips_insn32 unwinder. */ | |
1791 | ||
eec63939 | 1792 | static struct mips_frame_cache * |
45c9dd44 | 1793 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 AC |
1794 | { |
1795 | mips_extra_func_info_t proc_desc; | |
1796 | struct mips_frame_cache *cache; | |
1797 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1798 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1799 | /* r0 bit means kernel trap */ | |
1800 | int kernel_trap; | |
1801 | /* What registers have been saved? Bitmasks. */ | |
1802 | unsigned long gen_mask, float_mask; | |
1803 | ||
1804 | if ((*this_cache) != NULL) | |
1805 | return (*this_cache); | |
1806 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1807 | (*this_cache) = cache; | |
1808 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1809 | ||
0d5febcc AC |
1810 | /* Synthesize a proc descriptor. */ |
1811 | { | |
1812 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1813 | CORE_ADDR start_addr; | |
eec63939 | 1814 | |
0d5febcc AC |
1815 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1816 | if (start_addr == 0) | |
1817 | start_addr = heuristic_proc_start (pc); | |
1818 | ||
c9343fd1 AC |
1819 | #ifdef NOT_YET |
1820 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, this_cache); | |
1821 | #else | |
1822 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, NULL); | |
1823 | #endif | |
0d5febcc AC |
1824 | } |
1825 | ||
eec63939 AC |
1826 | /* Extract the frame's base. */ |
1827 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1828 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1829 | ||
1830 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1831 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1832 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1833 | ||
1834 | /* In any frame other than the innermost or a frame interrupted by a | |
1835 | signal, we assume that all registers have been saved. This | |
1836 | assumes that all register saves in a function happen before the | |
1837 | first function call. */ | |
1838 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1839 | /* Not sure exactly what kernel_trap means, but if it means the | |
1840 | kernel saves the registers without a prologue doing it, we | |
1841 | better not examine the prologue to see whether registers | |
1842 | have been saved yet. */ | |
1843 | && !kernel_trap) | |
1844 | { | |
1845 | /* We need to figure out whether the registers that the | |
1846 | proc_desc claims are saved have been saved yet. */ | |
1847 | ||
1848 | CORE_ADDR addr; | |
1849 | ||
1850 | /* Bitmasks; set if we have found a save for the register. */ | |
1851 | unsigned long gen_save_found = 0; | |
1852 | unsigned long float_save_found = 0; | |
1853 | int mips16; | |
1854 | ||
1855 | /* If the address is odd, assume this is MIPS16 code. */ | |
1856 | addr = PROC_LOW_ADDR (proc_desc); | |
1857 | mips16 = pc_is_mips16 (addr); | |
1858 | ||
1859 | /* Scan through this function's instructions preceding the | |
1860 | current PC, and look for those that save registers. */ | |
1861 | while (addr < frame_pc_unwind (next_frame)) | |
1862 | { | |
1863 | if (mips16) | |
1864 | { | |
1865 | mips16_decode_reg_save (mips16_fetch_instruction (addr), | |
1866 | &gen_save_found); | |
1867 | addr += MIPS16_INSTLEN; | |
1868 | } | |
1869 | else | |
1870 | { | |
1871 | mips32_decode_reg_save (mips32_fetch_instruction (addr), | |
1872 | &gen_save_found, &float_save_found); | |
1873 | addr += MIPS_INSTLEN; | |
1874 | } | |
1875 | } | |
1876 | gen_mask = gen_save_found; | |
1877 | float_mask = float_save_found; | |
1878 | } | |
1879 | ||
1880 | /* Fill in the offsets for the registers which gen_mask says were | |
1881 | saved. */ | |
1882 | { | |
1883 | CORE_ADDR reg_position = (cache->base | |
1884 | + PROC_REG_OFFSET (proc_desc)); | |
1885 | int ireg; | |
1886 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1887 | if (gen_mask & 0x80000000) | |
1888 | { | |
1889 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
1890 | reg_position -= mips_abi_regsize (gdbarch); | |
1891 | } | |
1892 | } | |
1893 | ||
1894 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1895 | order of that normally used by gcc. Therefore, we have to fetch | |
1896 | the first instruction of the function, and if it's an entry | |
1897 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1898 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1899 | { | |
1900 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1901 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1902 | /* entry */ | |
1903 | { | |
1904 | int reg; | |
1905 | int sreg_count = (inst >> 6) & 3; | |
1906 | ||
1907 | /* Check if the ra register was pushed on the stack. */ | |
1908 | CORE_ADDR reg_position = (cache->base | |
1909 | + PROC_REG_OFFSET (proc_desc)); | |
1910 | if (inst & 0x20) | |
1911 | reg_position -= mips_abi_regsize (gdbarch); | |
1912 | ||
1913 | /* Check if the s0 and s1 registers were pushed on the | |
1914 | stack. */ | |
1915 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1916 | check. */ | |
1917 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1918 | { | |
1919 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
1920 | reg_position -= mips_abi_regsize (gdbarch); | |
1921 | } | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | /* Fill in the offsets for the registers which float_mask says were | |
1926 | saved. */ | |
1927 | { | |
1928 | CORE_ADDR reg_position = (cache->base | |
1929 | + PROC_FREG_OFFSET (proc_desc)); | |
1930 | int ireg; | |
1931 | /* Fill in the offsets for the float registers which float_mask | |
1932 | says were saved. */ | |
1933 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1934 | if (float_mask & 0x80000000) | |
1935 | { | |
1936 | if (mips_abi_regsize (gdbarch) == 4 | |
1937 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1938 | { | |
1939 | /* On a big endian 32 bit ABI, floating point registers | |
1940 | are paired to form doubles such that the most | |
1941 | significant part is in $f[N+1] and the least | |
1942 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1943 | registers are also spilled as a pair and stored as a | |
1944 | double. | |
1945 | ||
1946 | When little-endian the least significant part is | |
1947 | stored first leading to the memory order $f[N] and | |
1948 | then $f[N+1]. | |
1949 | ||
1950 | Unfortunately, when big-endian the most significant | |
1951 | part of the double is stored first, and the least | |
1952 | significant is stored second. This leads to the | |
1953 | registers being ordered in memory as firt $f[N+1] and | |
1954 | then $f[N]. | |
1955 | ||
1956 | For the big-endian case make certain that the | |
1957 | addresses point at the correct (swapped) locations | |
1958 | $f[N] and $f[N+1] pair (keep in mind that | |
1959 | reg_position is decremented each time through the | |
1960 | loop). */ | |
1961 | if ((ireg & 1)) | |
1962 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1963 | .addr = reg_position - mips_abi_regsize (gdbarch); | |
1964 | else | |
1965 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1966 | .addr = reg_position + mips_abi_regsize (gdbarch); | |
1967 | } | |
1968 | else | |
1969 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1970 | .addr = reg_position; | |
1971 | reg_position -= mips_abi_regsize (gdbarch); | |
1972 | } | |
1973 | ||
1974 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1975 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1976 | } | |
1977 | ||
1978 | /* SP_REGNUM, contains the value and not the address. */ | |
1979 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
1980 | ||
1981 | return (*this_cache); | |
1982 | } | |
1983 | ||
1984 | static void | |
45c9dd44 | 1985 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
1986 | struct frame_id *this_id) |
1987 | { | |
45c9dd44 | 1988 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1989 | this_cache); |
1990 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1991 | } | |
1992 | ||
1993 | static void | |
45c9dd44 | 1994 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1995 | void **this_cache, |
1996 | int regnum, int *optimizedp, | |
1997 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1998 | int *realnump, void *valuep) | |
1999 | { | |
45c9dd44 | 2000 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
2001 | this_cache); |
2002 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2003 | optimizedp, lvalp, addrp, realnump, valuep); | |
2004 | } | |
2005 | ||
45c9dd44 | 2006 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2007 | { |
2008 | NORMAL_FRAME, | |
45c9dd44 AC |
2009 | mips_insn16_frame_this_id, |
2010 | mips_insn16_frame_prev_register | |
eec63939 AC |
2011 | }; |
2012 | ||
2013 | static const struct frame_unwind * | |
45c9dd44 | 2014 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2015 | { |
2016 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2017 | if (pc_is_mips16 (pc)) | |
45c9dd44 | 2018 | return &mips_insn16_frame_unwind; |
eec63939 AC |
2019 | return NULL; |
2020 | } | |
2021 | ||
2022 | static CORE_ADDR | |
45c9dd44 | 2023 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
2024 | void **this_cache) |
2025 | { | |
45c9dd44 | 2026 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
2027 | this_cache); |
2028 | return info->base; | |
2029 | } | |
2030 | ||
45c9dd44 | 2031 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2032 | { |
45c9dd44 AC |
2033 | &mips_insn16_frame_unwind, |
2034 | mips_insn16_frame_base_address, | |
2035 | mips_insn16_frame_base_address, | |
2036 | mips_insn16_frame_base_address | |
eec63939 AC |
2037 | }; |
2038 | ||
2039 | static const struct frame_base * | |
45c9dd44 | 2040 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2041 | { |
45c9dd44 AC |
2042 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
2043 | return &mips_insn16_frame_base; | |
eec63939 AC |
2044 | else |
2045 | return NULL; | |
2046 | } | |
2047 | ||
45c9dd44 AC |
2048 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2049 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2050 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2051 | unwinder. */ | |
2052 | ||
eec63939 | 2053 | static struct mips_frame_cache * |
45c9dd44 | 2054 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 AC |
2055 | { |
2056 | mips_extra_func_info_t proc_desc; | |
2057 | struct mips_frame_cache *cache; | |
2058 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2059 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2060 | /* r0 bit means kernel trap */ | |
2061 | int kernel_trap; | |
2062 | /* What registers have been saved? Bitmasks. */ | |
2063 | unsigned long gen_mask, float_mask; | |
2064 | ||
2065 | if ((*this_cache) != NULL) | |
2066 | return (*this_cache); | |
2067 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2068 | (*this_cache) = cache; | |
2069 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2070 | ||
a343eb3c JB |
2071 | /* Synthesize a proc descriptor. */ |
2072 | { | |
2073 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2074 | CORE_ADDR start_addr; | |
2075 | ||
2076 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2077 | if (start_addr == 0) | |
2078 | start_addr = heuristic_proc_start (pc); | |
2079 | ||
c9343fd1 AC |
2080 | #ifdef NOT_YET |
2081 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, this_cache); | |
2082 | #else | |
2083 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame, NULL); | |
2084 | #endif | |
a343eb3c JB |
2085 | } |
2086 | ||
eec63939 AC |
2087 | if (proc_desc == NULL) |
2088 | /* I'm not sure how/whether this can happen. Normally when we | |
2089 | can't find a proc_desc, we "synthesize" one using | |
2090 | heuristic_proc_desc and set the saved_regs right away. */ | |
2091 | return cache; | |
2092 | ||
2093 | /* Extract the frame's base. */ | |
2094 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
2095 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
2096 | ||
2097 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
2098 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
2099 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
2100 | ||
2101 | /* In any frame other than the innermost or a frame interrupted by a | |
2102 | signal, we assume that all registers have been saved. This | |
2103 | assumes that all register saves in a function happen before the | |
2104 | first function call. */ | |
2105 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
2106 | /* Not sure exactly what kernel_trap means, but if it means the | |
2107 | kernel saves the registers without a prologue doing it, we | |
2108 | better not examine the prologue to see whether registers | |
2109 | have been saved yet. */ | |
2110 | && !kernel_trap) | |
2111 | { | |
2112 | /* We need to figure out whether the registers that the | |
2113 | proc_desc claims are saved have been saved yet. */ | |
2114 | ||
2115 | CORE_ADDR addr; | |
2116 | ||
2117 | /* Bitmasks; set if we have found a save for the register. */ | |
2118 | unsigned long gen_save_found = 0; | |
2119 | unsigned long float_save_found = 0; | |
eec63939 | 2120 | |
eec63939 | 2121 | addr = PROC_LOW_ADDR (proc_desc); |
eec63939 AC |
2122 | |
2123 | /* Scan through this function's instructions preceding the | |
2124 | current PC, and look for those that save registers. */ | |
2125 | while (addr < frame_pc_unwind (next_frame)) | |
2126 | { | |
8ac2e020 JB |
2127 | mips32_decode_reg_save (mips32_fetch_instruction (addr), |
2128 | &gen_save_found, &float_save_found); | |
2129 | addr += MIPS_INSTLEN; | |
eec63939 AC |
2130 | } |
2131 | gen_mask = gen_save_found; | |
2132 | float_mask = float_save_found; | |
2133 | } | |
2134 | ||
2135 | /* Fill in the offsets for the registers which gen_mask says were | |
2136 | saved. */ | |
2137 | { | |
2138 | CORE_ADDR reg_position = (cache->base | |
2139 | + PROC_REG_OFFSET (proc_desc)); | |
2140 | int ireg; | |
2141 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
2142 | if (gen_mask & 0x80000000) | |
2143 | { | |
2144 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
2145 | reg_position -= mips_abi_regsize (gdbarch); | |
2146 | } | |
2147 | } | |
2148 | ||
eec63939 AC |
2149 | /* Fill in the offsets for the registers which float_mask says were |
2150 | saved. */ | |
2151 | { | |
8ac2e020 | 2152 | CORE_ADDR reg_position = (cache->base + PROC_FREG_OFFSET (proc_desc)); |
eec63939 | 2153 | int ireg; |
8ac2e020 | 2154 | |
eec63939 AC |
2155 | /* Fill in the offsets for the float registers which float_mask |
2156 | says were saved. */ | |
2157 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
2158 | if (float_mask & 0x80000000) | |
2159 | { | |
8ac2e020 JB |
2160 | const int regno = |
2161 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg; | |
2162 | ||
eec63939 AC |
2163 | if (mips_abi_regsize (gdbarch) == 4 |
2164 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2165 | { | |
2166 | /* On a big endian 32 bit ABI, floating point registers | |
2167 | are paired to form doubles such that the most | |
2168 | significant part is in $f[N+1] and the least | |
2169 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
2170 | registers are also spilled as a pair and stored as a | |
2171 | double. | |
2172 | ||
2173 | When little-endian the least significant part is | |
2174 | stored first leading to the memory order $f[N] and | |
2175 | then $f[N+1]. | |
2176 | ||
2177 | Unfortunately, when big-endian the most significant | |
2178 | part of the double is stored first, and the least | |
2179 | significant is stored second. This leads to the | |
2180 | registers being ordered in memory as firt $f[N+1] and | |
2181 | then $f[N]. | |
2182 | ||
2183 | For the big-endian case make certain that the | |
2184 | addresses point at the correct (swapped) locations | |
2185 | $f[N] and $f[N+1] pair (keep in mind that | |
2186 | reg_position is decremented each time through the | |
2187 | loop). */ | |
2188 | if ((ireg & 1)) | |
8ac2e020 JB |
2189 | cache->saved_regs[regno].addr = |
2190 | reg_position - mips_abi_regsize (gdbarch); | |
eec63939 | 2191 | else |
8ac2e020 JB |
2192 | cache->saved_regs[regno].addr = |
2193 | reg_position + mips_abi_regsize (gdbarch); | |
eec63939 AC |
2194 | } |
2195 | else | |
8ac2e020 | 2196 | cache->saved_regs[regno].addr = reg_position; |
eec63939 AC |
2197 | reg_position -= mips_abi_regsize (gdbarch); |
2198 | } | |
2199 | ||
2200 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
2201 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
2202 | } | |
2203 | ||
2204 | /* SP_REGNUM, contains the value and not the address. */ | |
2205 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
2206 | ||
2207 | return (*this_cache); | |
2208 | } | |
2209 | ||
2210 | static void | |
45c9dd44 | 2211 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
2212 | struct frame_id *this_id) |
2213 | { | |
45c9dd44 | 2214 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2215 | this_cache); |
2216 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2217 | } | |
2218 | ||
2219 | static void | |
45c9dd44 | 2220 | mips_insn32_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
2221 | void **this_cache, |
2222 | int regnum, int *optimizedp, | |
2223 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2224 | int *realnump, void *valuep) | |
2225 | { | |
45c9dd44 | 2226 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2227 | this_cache); |
2228 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2229 | optimizedp, lvalp, addrp, realnump, valuep); | |
2230 | } | |
2231 | ||
45c9dd44 | 2232 | static const struct frame_unwind mips_insn32_frame_unwind = |
eec63939 AC |
2233 | { |
2234 | NORMAL_FRAME, | |
45c9dd44 AC |
2235 | mips_insn32_frame_this_id, |
2236 | mips_insn32_frame_prev_register | |
eec63939 AC |
2237 | }; |
2238 | ||
2239 | static const struct frame_unwind * | |
45c9dd44 | 2240 | mips_insn32_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2241 | { |
2242 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2243 | if (! pc_is_mips16 (pc)) | |
45c9dd44 | 2244 | return &mips_insn32_frame_unwind; |
eec63939 AC |
2245 | return NULL; |
2246 | } | |
2247 | ||
2248 | static CORE_ADDR | |
45c9dd44 | 2249 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
2250 | void **this_cache) |
2251 | { | |
45c9dd44 | 2252 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2253 | this_cache); |
2254 | return info->base; | |
2255 | } | |
2256 | ||
45c9dd44 | 2257 | static const struct frame_base mips_insn32_frame_base = |
eec63939 | 2258 | { |
45c9dd44 AC |
2259 | &mips_insn32_frame_unwind, |
2260 | mips_insn32_frame_base_address, | |
2261 | mips_insn32_frame_base_address, | |
2262 | mips_insn32_frame_base_address | |
eec63939 AC |
2263 | }; |
2264 | ||
2265 | static const struct frame_base * | |
45c9dd44 | 2266 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2267 | { |
45c9dd44 AC |
2268 | if (mips_insn32_frame_sniffer (next_frame) != NULL) |
2269 | return &mips_insn32_frame_base; | |
eec63939 AC |
2270 | else |
2271 | return NULL; | |
2272 | } | |
2273 | ||
2274 | static struct trad_frame_cache * | |
2275 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2276 | { | |
2277 | CORE_ADDR pc; | |
2278 | CORE_ADDR start_addr; | |
2279 | CORE_ADDR stack_addr; | |
2280 | struct trad_frame_cache *this_trad_cache; | |
2281 | ||
2282 | if ((*this_cache) != NULL) | |
2283 | return (*this_cache); | |
2284 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2285 | (*this_cache) = this_trad_cache; | |
2286 | ||
2287 | /* The return address is in the link register. */ | |
2288 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, RA_REGNUM); | |
2289 | ||
2290 | /* Frame ID, since it's a frameless / stackless function, no stack | |
2291 | space is allocated and SP on entry is the current SP. */ | |
2292 | pc = frame_pc_unwind (next_frame); | |
2293 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2294 | stack_addr = frame_unwind_register_signed (next_frame, SP_REGNUM); | |
2295 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); | |
2296 | ||
2297 | /* Assume that the frame's base is the same as the | |
2298 | stack-pointer. */ | |
2299 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
2300 | ||
2301 | return this_trad_cache; | |
2302 | } | |
2303 | ||
2304 | static void | |
2305 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2306 | struct frame_id *this_id) | |
2307 | { | |
2308 | struct trad_frame_cache *this_trad_cache | |
2309 | = mips_stub_frame_cache (next_frame, this_cache); | |
2310 | trad_frame_get_id (this_trad_cache, this_id); | |
2311 | } | |
2312 | ||
2313 | static void | |
2314 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2315 | void **this_cache, | |
2316 | int regnum, int *optimizedp, | |
2317 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2318 | int *realnump, void *valuep) | |
2319 | { | |
2320 | struct trad_frame_cache *this_trad_cache | |
2321 | = mips_stub_frame_cache (next_frame, this_cache); | |
2322 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2323 | lvalp, addrp, realnump, valuep); | |
2324 | } | |
2325 | ||
2326 | static const struct frame_unwind mips_stub_frame_unwind = | |
2327 | { | |
2328 | NORMAL_FRAME, | |
2329 | mips_stub_frame_this_id, | |
2330 | mips_stub_frame_prev_register | |
2331 | }; | |
2332 | ||
2333 | static const struct frame_unwind * | |
2334 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2335 | { | |
2336 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2337 | if (in_plt_section (pc, NULL)) | |
2338 | return &mips_stub_frame_unwind; | |
2339 | else | |
2340 | return NULL; | |
2341 | } | |
2342 | ||
2343 | static CORE_ADDR | |
2344 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2345 | void **this_cache) | |
2346 | { | |
2347 | struct trad_frame_cache *this_trad_cache | |
2348 | = mips_stub_frame_cache (next_frame, this_cache); | |
2349 | return trad_frame_get_this_base (this_trad_cache); | |
2350 | } | |
2351 | ||
2352 | static const struct frame_base mips_stub_frame_base = | |
2353 | { | |
2354 | &mips_stub_frame_unwind, | |
2355 | mips_stub_frame_base_address, | |
2356 | mips_stub_frame_base_address, | |
2357 | mips_stub_frame_base_address | |
2358 | }; | |
2359 | ||
2360 | static const struct frame_base * | |
2361 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2362 | { | |
2363 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2364 | return &mips_stub_frame_base; | |
2365 | else | |
2366 | return NULL; | |
edfae063 AC |
2367 | } |
2368 | ||
c906108c | 2369 | static CORE_ADDR |
acdb74a0 | 2370 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 2371 | { |
a4b8ebc8 AC |
2372 | /* Always a pseudo. */ |
2373 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 2374 | if (fi == NULL) |
c906108c | 2375 | { |
a4b8ebc8 AC |
2376 | LONGEST val; |
2377 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2378 | return val; | |
f796e4be | 2379 | } |
f10683bb MH |
2380 | else if ((regno % NUM_REGS) == MIPS_SP_REGNUM) |
2381 | /* MIPS_SP_REGNUM is special, its value is stored in saved_regs. | |
a4b8ebc8 AC |
2382 | In fact, it is so special that it can even only be fetched |
2383 | using a raw register number! Once this code as been converted | |
2384 | to frame-unwind the problem goes away. */ | |
2385 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 2386 | else |
a4b8ebc8 | 2387 | return frame_unwind_register_signed (fi, regno); |
64159455 | 2388 | |
c906108c SS |
2389 | } |
2390 | ||
2391 | /* mips_addr_bits_remove - remove useless address bits */ | |
2392 | ||
875e1767 | 2393 | static CORE_ADDR |
acdb74a0 | 2394 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 2395 | { |
480d3dd2 | 2396 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 2397 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
2398 | /* This hack is a work-around for existing boards using PMON, the |
2399 | simulator, and any other 64-bit targets that doesn't have true | |
2400 | 64-bit addressing. On these targets, the upper 32 bits of | |
2401 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2402 | likely to have been sign extended to all 1s by instruction | |
2403 | sequences that load 32-bit addresses. For example, a typical | |
2404 | piece of code that loads an address is this: | |
2405 | ||
2406 | lui $r2, <upper 16 bits> | |
2407 | ori $r2, <lower 16 bits> | |
2408 | ||
2409 | But the lui sign-extends the value such that the upper 32 bits | |
2410 | may be all 1s. The workaround is simply to mask off these | |
2411 | bits. In the future, gcc may be changed to support true 64-bit | |
2412 | addressing, and this masking will have to be disabled. */ | |
2413 | return addr &= 0xffffffffUL; | |
2414 | else | |
2415 | return addr; | |
c906108c SS |
2416 | } |
2417 | ||
9022177c DJ |
2418 | /* mips_software_single_step() is called just before we want to resume |
2419 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 2420 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
2421 | the target of the coming instruction and breakpoint it. |
2422 | ||
2423 | single_step is also called just after the inferior stops. If we had | |
2424 | set up a simulated single-step, we undo our damage. */ | |
2425 | ||
2426 | void | |
2427 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
2428 | { | |
2429 | static CORE_ADDR next_pc; | |
2430 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2431 | static binsn_quantum break_mem; | |
2432 | CORE_ADDR pc; | |
2433 | ||
2434 | if (insert_breakpoints_p) | |
2435 | { | |
b6cb9035 | 2436 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
2437 | next_pc = mips_next_pc (pc); |
2438 | ||
2439 | target_insert_breakpoint (next_pc, break_mem); | |
2440 | } | |
2441 | else | |
2442 | target_remove_breakpoint (next_pc, break_mem); | |
2443 | } | |
2444 | ||
c906108c | 2445 | static struct mips_extra_func_info temp_proc_desc; |
fe29b929 | 2446 | |
e0f7ec59 AC |
2447 | /* Set a register's saved stack address in temp_saved_regs. If an |
2448 | address has already been set for this register, do nothing; this | |
2449 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
2450 | function prologue. |
2451 | ||
2452 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
2453 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
2454 | is used as it is only second range (the ABI instead of ISA | |
2455 | registers) that comes into play when finding saved registers in a | |
2456 | frame. */ | |
c906108c SS |
2457 | |
2458 | static void | |
c9343fd1 AC |
2459 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
2460 | CORE_ADDR offset) | |
c906108c | 2461 | { |
c9343fd1 AC |
2462 | if (this_cache != NULL |
2463 | && this_cache->saved_regs[regnum].addr == 0) | |
a4b8ebc8 | 2464 | { |
c9343fd1 AC |
2465 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; |
2466 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
a4b8ebc8 | 2467 | } |
c906108c SS |
2468 | } |
2469 | ||
2470 | ||
2471 | /* Test whether the PC points to the return instruction at the | |
2472 | end of a function. */ | |
2473 | ||
c5aa993b | 2474 | static int |
acdb74a0 | 2475 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
2476 | { |
2477 | if (pc_is_mips16 (pc)) | |
2478 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
2479 | generates a "jr $ra"; other times it generates code to load | |
2480 | the return address from the stack to an accessible register (such | |
2481 | as $a3), then a "jr" using that register. This second case | |
2482 | is almost impossible to distinguish from an indirect jump | |
2483 | used for switch statements, so we don't even try. */ | |
2484 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2485 | else | |
2486 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2487 | } | |
2488 | ||
2489 | ||
2490 | /* This fencepost looks highly suspicious to me. Removing it also | |
2491 | seems suspicious as it could affect remote debugging across serial | |
2492 | lines. */ | |
2493 | ||
2494 | static CORE_ADDR | |
acdb74a0 | 2495 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 2496 | { |
c5aa993b JM |
2497 | CORE_ADDR start_pc; |
2498 | CORE_ADDR fence; | |
2499 | int instlen; | |
2500 | int seen_adjsp = 0; | |
c906108c | 2501 | |
c5aa993b JM |
2502 | pc = ADDR_BITS_REMOVE (pc); |
2503 | start_pc = pc; | |
2504 | fence = start_pc - heuristic_fence_post; | |
2505 | if (start_pc == 0) | |
2506 | return 0; | |
c906108c | 2507 | |
6d82d43b | 2508 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 2509 | fence = VM_MIN_ADDRESS; |
c906108c | 2510 | |
c5aa993b | 2511 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 2512 | |
c5aa993b JM |
2513 | /* search back for previous return */ |
2514 | for (start_pc -= instlen;; start_pc -= instlen) | |
2515 | if (start_pc < fence) | |
2516 | { | |
2517 | /* It's not clear to me why we reach this point when | |
c0236d92 | 2518 | stop_soon, but with this test, at least we |
c5aa993b JM |
2519 | don't print out warnings for every child forked (eg, on |
2520 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 2521 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 2522 | { |
c5aa993b JM |
2523 | static int blurb_printed = 0; |
2524 | ||
dc305454 MS |
2525 | warning ("GDB can't find the start of the function at 0x%s.", |
2526 | paddr_nz (pc)); | |
c5aa993b JM |
2527 | |
2528 | if (!blurb_printed) | |
c906108c | 2529 | { |
c5aa993b JM |
2530 | /* This actually happens frequently in embedded |
2531 | development, when you first connect to a board | |
2532 | and your stack pointer and pc are nowhere in | |
2533 | particular. This message needs to give people | |
2534 | in that situation enough information to | |
2535 | determine that it's no big deal. */ | |
2536 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
2537 | GDB is unable to find the start of the function at 0x%s\n\ |
2538 | and thus can't determine the size of that function's stack frame.\n\ | |
2539 | This means that GDB may be unable to access that stack frame, or\n\ | |
2540 | the frames below it.\n\ | |
2541 | This problem is most likely caused by an invalid program counter or\n\ | |
2542 | stack pointer.\n\ | |
2543 | However, if you think GDB should simply search farther back\n\ | |
2544 | from 0x%s for code which looks like the beginning of a\n\ | |
2545 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 2546 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 2547 | blurb_printed = 1; |
c906108c | 2548 | } |
c906108c SS |
2549 | } |
2550 | ||
c5aa993b JM |
2551 | return 0; |
2552 | } | |
2553 | else if (pc_is_mips16 (start_pc)) | |
2554 | { | |
2555 | unsigned short inst; | |
2556 | ||
2557 | /* On MIPS16, any one of the following is likely to be the | |
2558 | start of a function: | |
2559 | entry | |
2560 | addiu sp,-n | |
2561 | daddiu sp,-n | |
2562 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2563 | inst = mips_fetch_instruction (start_pc); | |
2564 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2565 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2566 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2567 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2568 | break; | |
2569 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2570 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2571 | seen_adjsp = 1; | |
2572 | else | |
2573 | seen_adjsp = 0; | |
2574 | } | |
2575 | else if (mips_about_to_return (start_pc)) | |
2576 | { | |
2577 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
2578 | break; | |
2579 | } | |
2580 | ||
c5aa993b | 2581 | return start_pc; |
c906108c SS |
2582 | } |
2583 | ||
2584 | /* Fetch the immediate value from a MIPS16 instruction. | |
2585 | If the previous instruction was an EXTEND, use it to extend | |
2586 | the upper bits of the immediate value. This is a helper function | |
2587 | for mips16_heuristic_proc_desc. */ | |
2588 | ||
2589 | static int | |
acdb74a0 AC |
2590 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
2591 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
2592 | int nbits, /* number of bits in imm field */ |
2593 | int scale, /* scale factor to be applied to imm */ | |
2594 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
2595 | { |
2596 | int offset; | |
2597 | ||
2598 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
2599 | { | |
2600 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 2601 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
2602 | offset = 0 - (0x10000 - (offset & 0xffff)); |
2603 | return offset | (inst & 0x1f); | |
2604 | } | |
2605 | else | |
2606 | { | |
2607 | int max_imm = 1 << nbits; | |
2608 | int mask = max_imm - 1; | |
2609 | int sign_bit = max_imm >> 1; | |
2610 | ||
2611 | offset = inst & mask; | |
2612 | if (is_signed && (offset & sign_bit)) | |
2613 | offset = 0 - (max_imm - offset); | |
2614 | return offset * scale; | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | ||
2619 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
2620 | stream from start_pc to limit_pc. */ | |
2621 | ||
2622 | static void | |
acdb74a0 | 2623 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
c9343fd1 AC |
2624 | CORE_ADDR sp, |
2625 | struct frame_info *next_frame, | |
2626 | struct mips_frame_cache *this_cache) | |
c906108c SS |
2627 | { |
2628 | CORE_ADDR cur_pc; | |
2629 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
2630 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
2631 | unsigned inst = 0; /* current instruction */ | |
2632 | unsigned entry_inst = 0; /* the entry instruction */ | |
2633 | int reg, offset; | |
480d3dd2 | 2634 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 2635 | |
c5aa993b JM |
2636 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
2637 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2638 | |
2639 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2640 | { | |
2641 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2642 | the immediate offset extension from it in mips16_get_imm. */ | |
2643 | prev_inst = inst; | |
2644 | ||
2645 | /* Fetch and decode the instruction. */ | |
2646 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2647 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 2648 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
2649 | { |
2650 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2651 | if (offset < 0) /* negative stack adjustment? */ |
2652 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2653 | else |
2654 | /* Exit loop if a positive stack adjustment is found, which | |
2655 | usually means that the stack cleanup code in the function | |
2656 | epilogue is reached. */ | |
2657 | break; | |
2658 | } | |
2659 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2660 | { | |
2661 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2662 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2663 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c9343fd1 | 2664 | set_reg_offset (this_cache, reg, sp + offset); |
c906108c SS |
2665 | } |
2666 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2667 | { | |
2668 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2669 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2670 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c9343fd1 | 2671 | set_reg_offset (this_cache, reg, sp + offset); |
c906108c SS |
2672 | } |
2673 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2674 | { | |
2675 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2676 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c9343fd1 | 2677 | set_reg_offset (this_cache, RA_REGNUM, sp + offset); |
c906108c SS |
2678 | } |
2679 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2680 | { | |
2681 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2682 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c9343fd1 | 2683 | set_reg_offset (this_cache, RA_REGNUM, sp + offset); |
c906108c | 2684 | } |
c5aa993b | 2685 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2686 | { |
2687 | frame_addr = sp; | |
2688 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2689 | } | |
2690 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2691 | { | |
2692 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2693 | frame_addr = sp + offset; | |
2694 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2695 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2696 | } | |
2697 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2698 | { | |
2699 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2700 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2701 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c9343fd1 | 2702 | set_reg_offset (this_cache, reg, frame_addr + offset); |
c906108c SS |
2703 | } |
2704 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2705 | { | |
2706 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2707 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2708 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c9343fd1 | 2709 | set_reg_offset (this_cache, reg, frame_addr + offset); |
c906108c | 2710 | } |
c5aa993b JM |
2711 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2712 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2713 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2714 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2715 | } |
2716 | ||
c5aa993b JM |
2717 | /* The entry instruction is typically the first instruction in a function, |
2718 | and it stores registers at offsets relative to the value of the old SP | |
2719 | (before the prologue). But the value of the sp parameter to this | |
2720 | function is the new SP (after the prologue has been executed). So we | |
2721 | can't calculate those offsets until we've seen the entire prologue, | |
2722 | and can calculate what the old SP must have been. */ | |
2723 | if (entry_inst != 0) | |
2724 | { | |
2725 | int areg_count = (entry_inst >> 8) & 7; | |
2726 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2727 | |
c5aa993b JM |
2728 | /* The entry instruction always subtracts 32 from the SP. */ |
2729 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2730 | |
c5aa993b JM |
2731 | /* Now we can calculate what the SP must have been at the |
2732 | start of the function prologue. */ | |
2733 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2734 | |
c5aa993b JM |
2735 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2736 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2737 | { | |
2738 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
c9343fd1 | 2739 | set_reg_offset (this_cache, reg, sp + offset); |
13326b4e | 2740 | offset += mips_abi_regsize (current_gdbarch); |
c5aa993b | 2741 | } |
c906108c | 2742 | |
c5aa993b JM |
2743 | /* Check if the ra register was pushed on the stack. */ |
2744 | offset = -4; | |
2745 | if (entry_inst & 0x20) | |
2746 | { | |
2747 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
c9343fd1 | 2748 | set_reg_offset (this_cache, RA_REGNUM, sp + offset); |
13326b4e | 2749 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b | 2750 | } |
c906108c | 2751 | |
c5aa993b JM |
2752 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2753 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2754 | { | |
2755 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
c9343fd1 | 2756 | set_reg_offset (this_cache, reg, sp + offset); |
13326b4e | 2757 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b JM |
2758 | } |
2759 | } | |
c906108c SS |
2760 | } |
2761 | ||
2762 | static void | |
fba45db2 | 2763 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
c9343fd1 AC |
2764 | CORE_ADDR sp, struct frame_info *next_frame, |
2765 | struct mips_frame_cache *this_cache) | |
c906108c SS |
2766 | { |
2767 | CORE_ADDR cur_pc; | |
c5aa993b | 2768 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2769 | restart: |
c9343fd1 AC |
2770 | this_cache = xrealloc (this_cache, SIZEOF_FRAME_SAVED_REGS); |
2771 | memset (this_cache, '\0', SIZEOF_FRAME_SAVED_REGS); | |
c5aa993b | 2772 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2773 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2774 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2775 | { | |
2776 | unsigned long inst, high_word, low_word; | |
2777 | int reg; | |
2778 | ||
2779 | /* Fetch the instruction. */ | |
2780 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2781 | ||
2782 | /* Save some code by pre-extracting some useful fields. */ | |
2783 | high_word = (inst >> 16) & 0xffff; | |
2784 | low_word = inst & 0xffff; | |
2785 | reg = high_word & 0x1f; | |
2786 | ||
c5aa993b | 2787 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2788 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2789 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2790 | { | |
2791 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2792 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2793 | else |
2794 | /* Exit loop if a positive stack adjustment is found, which | |
2795 | usually means that the stack cleanup code in the function | |
2796 | epilogue is reached. */ | |
2797 | break; | |
2798 | } | |
2799 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2800 | { | |
c5aa993b | 2801 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c9343fd1 | 2802 | set_reg_offset (this_cache, reg, sp + low_word); |
c906108c SS |
2803 | } |
2804 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2805 | { | |
d5ac5a39 AC |
2806 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and |
2807 | $ra. */ | |
c5aa993b | 2808 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c9343fd1 | 2809 | set_reg_offset (this_cache, reg, sp + low_word); |
c906108c | 2810 | } |
c5aa993b | 2811 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2812 | { |
2813 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2814 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2815 | frame_addr = sp + low_word; | |
f10683bb | 2816 | else if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM) |
c906108c SS |
2817 | { |
2818 | unsigned alloca_adjust; | |
2819 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2820 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2821 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2822 | if (alloca_adjust > 0) |
2823 | { | |
2824 | /* FP > SP + frame_size. This may be because | |
2825 | * of an alloca or somethings similar. | |
2826 | * Fix sp to "pre-alloca" value, and try again. | |
2827 | */ | |
2828 | sp += alloca_adjust; | |
2829 | goto restart; | |
2830 | } | |
2831 | } | |
2832 | } | |
c5aa993b JM |
2833 | /* move $30,$sp. With different versions of gas this will be either |
2834 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2835 | Accept any one of these. */ | |
c906108c SS |
2836 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2837 | { | |
2838 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
f10683bb | 2839 | if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM) |
c906108c SS |
2840 | { |
2841 | unsigned alloca_adjust; | |
2842 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2843 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2844 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2845 | if (alloca_adjust > 0) |
2846 | { | |
2847 | /* FP > SP + frame_size. This may be because | |
2848 | * of an alloca or somethings similar. | |
2849 | * Fix sp to "pre-alloca" value, and try again. | |
2850 | */ | |
2851 | sp += alloca_adjust; | |
2852 | goto restart; | |
2853 | } | |
2854 | } | |
2855 | } | |
c5aa993b | 2856 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2857 | { |
c5aa993b | 2858 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c9343fd1 | 2859 | set_reg_offset (this_cache, reg, frame_addr + low_word); |
c906108c SS |
2860 | } |
2861 | } | |
2862 | } | |
2863 | ||
2864 | static mips_extra_func_info_t | |
acdb74a0 | 2865 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
c9343fd1 AC |
2866 | struct frame_info *next_frame, |
2867 | struct mips_frame_cache *this_cache) | |
c906108c | 2868 | { |
479412cd DJ |
2869 | CORE_ADDR sp; |
2870 | ||
465f7520 AC |
2871 | /* Can be called when there's no process, and hence when there's no |
2872 | NEXT_FRAME. */ | |
2873 | if (next_frame != NULL) | |
f10683bb | 2874 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); |
479412cd DJ |
2875 | else |
2876 | sp = 0; | |
c906108c | 2877 | |
c5aa993b JM |
2878 | if (start_pc == 0) |
2879 | return NULL; | |
2880 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
c906108c | 2881 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
f10683bb | 2882 | PROC_FRAME_REG (&temp_proc_desc) = MIPS_SP_REGNUM; |
c906108c SS |
2883 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; |
2884 | ||
2885 | if (start_pc + 200 < limit_pc) | |
2886 | limit_pc = start_pc + 200; | |
2887 | if (pc_is_mips16 (start_pc)) | |
c9343fd1 AC |
2888 | mips16_heuristic_proc_desc (start_pc, limit_pc, sp, |
2889 | next_frame, this_cache); | |
c906108c | 2890 | else |
c9343fd1 AC |
2891 | mips32_heuristic_proc_desc (start_pc, limit_pc, sp, |
2892 | next_frame, this_cache); | |
c906108c SS |
2893 | return &temp_proc_desc; |
2894 | } | |
2895 | ||
6c0d6680 DJ |
2896 | struct mips_objfile_private |
2897 | { | |
2898 | bfd_size_type size; | |
2899 | char *contents; | |
2900 | }; | |
2901 | ||
2902 | /* Global used to communicate between non_heuristic_proc_desc and | |
2903 | compare_pdr_entries within qsort (). */ | |
2904 | static bfd *the_bfd; | |
2905 | ||
2906 | static int | |
2907 | compare_pdr_entries (const void *a, const void *b) | |
2908 | { | |
2909 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2910 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2911 | ||
2912 | if (lhs < rhs) | |
2913 | return -1; | |
2914 | else if (lhs == rhs) | |
2915 | return 0; | |
2916 | else | |
2917 | return 1; | |
2918 | } | |
2919 | ||
c906108c | 2920 | static mips_extra_func_info_t |
acdb74a0 | 2921 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2922 | { |
2923 | CORE_ADDR startaddr; | |
2924 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2925 | struct block *b = block_for_pc (pc); |
c906108c | 2926 | struct symbol *sym; |
6c0d6680 DJ |
2927 | struct obj_section *sec; |
2928 | struct mips_objfile_private *priv; | |
2929 | ||
c906108c SS |
2930 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
2931 | if (addrptr) | |
2932 | *addrptr = startaddr; | |
6c0d6680 DJ |
2933 | |
2934 | priv = NULL; | |
2935 | ||
2936 | sec = find_pc_section (pc); | |
2937 | if (sec != NULL) | |
c906108c | 2938 | { |
8d5f9dcb | 2939 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2940 | |
2941 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2942 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2943 | |
2944 | the_bfd = sec->objfile->obfd; | |
2945 | if (priv == NULL | |
2946 | && (the_bfd->format == bfd_object | |
2947 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2948 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2949 | { | |
2950 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2951 | This means that we should not bother with this method on 64-bit | |
2952 | targets (until that is fixed). */ | |
2953 | ||
8b92e4d5 | 2954 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2955 | sizeof (struct mips_objfile_private)); |
2956 | priv->size = 0; | |
8d5f9dcb | 2957 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2958 | } |
2959 | else if (priv == NULL) | |
2960 | { | |
2961 | asection *bfdsec; | |
2962 | ||
8b92e4d5 | 2963 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2964 | sizeof (struct mips_objfile_private)); |
2965 | ||
2966 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2967 | if (bfdsec != NULL) | |
2968 | { | |
2969 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2970 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2971 | priv->size); |
2972 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2973 | priv->contents, 0, priv->size); | |
2974 | ||
2975 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2976 | presence of multiple code sections (and other corner cases) |
2977 | it can become unsorted. Sort it so that we can use a faster | |
2978 | binary search. */ | |
2979 | qsort (priv->contents, priv->size / 32, 32, | |
2980 | compare_pdr_entries); | |
6c0d6680 DJ |
2981 | } |
2982 | else | |
2983 | priv->size = 0; | |
2984 | ||
8d5f9dcb | 2985 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2986 | } |
2987 | the_bfd = NULL; | |
2988 | ||
2989 | if (priv->size != 0) | |
2990 | { | |
2991 | int low, mid, high; | |
2992 | char *ptr; | |
34fcf120 | 2993 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2994 | |
2995 | low = 0; | |
2996 | high = priv->size / 32; | |
2997 | ||
34fcf120 DJ |
2998 | /* We've found a .pdr section describing this objfile. We want to |
2999 | find the entry which describes this code address. The .pdr | |
3000 | information is not very descriptive; we have only a function | |
3001 | start address. We have to look for the closest entry, because | |
3002 | the local symbol at the beginning of this function may have | |
3003 | been stripped - so if we ask the symbol table for the start | |
3004 | address we may get a preceding global function. */ | |
3005 | ||
3006 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
3007 | do |
3008 | { | |
6c0d6680 DJ |
3009 | mid = (low + high) / 2; |
3010 | ||
3011 | ptr = priv->contents + mid * 32; | |
3012 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
3013 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
3014 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
3015 | |
3016 | if (pdr_pc > pc) | |
6c0d6680 DJ |
3017 | high = mid; |
3018 | else | |
3019 | low = mid + 1; | |
3020 | } | |
3021 | while (low != high); | |
3022 | ||
34fcf120 DJ |
3023 | /* Both low and high point one past the PDR of interest. If |
3024 | both are zero, that means this PC is before any region | |
3025 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
3026 | greater than PC. */ | |
3027 | if (low > 0) | |
3028 | { | |
3029 | ptr = priv->contents + (low - 1) * 32; | |
3030 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
3031 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
3032 | SECT_OFF_TEXT (sec->objfile)); | |
3033 | } | |
3034 | ||
3035 | /* We don't have a range, so we have no way to know for sure | |
3036 | whether we're in the correct PDR or a PDR for a preceding | |
3037 | function and the current function was a stripped local | |
3038 | symbol. But if the PDR's PC is at least as great as the | |
3039 | best guess from the symbol table, assume that it does cover | |
3040 | the right area; if a .pdr section is present at all then | |
3041 | nearly every function will have an entry. The biggest exception | |
3042 | will be the dynamic linker stubs; conveniently these are | |
3043 | placed before .text instead of after. */ | |
3044 | ||
3045 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
3046 | { |
3047 | struct symbol *sym = find_pc_function (pc); | |
3048 | ||
34fcf120 DJ |
3049 | if (addrptr) |
3050 | *addrptr = pdr_pc; | |
3051 | ||
6c0d6680 DJ |
3052 | /* Fill in what we need of the proc_desc. */ |
3053 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 3054 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 3055 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 3056 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
3057 | |
3058 | /* Only used for dummy frames. */ | |
3059 | PROC_HIGH_ADDR (proc_desc) = 0; | |
3060 | ||
3061 | PROC_FRAME_OFFSET (proc_desc) | |
3062 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
3063 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3064 | ptr + 24); | |
3065 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
3066 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3067 | ptr + 4); | |
3068 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3069 | ptr + 12); | |
3070 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3071 | ptr + 8); | |
3072 | PROC_FREG_OFFSET (proc_desc) | |
3073 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
3074 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3075 | ptr + 28); | |
3076 | proc_desc->pdr.isym = (long) sym; | |
3077 | ||
3078 | return proc_desc; | |
3079 | } | |
3080 | } | |
c906108c SS |
3081 | } |
3082 | ||
6c0d6680 DJ |
3083 | if (b == NULL) |
3084 | return NULL; | |
3085 | ||
3086 | if (startaddr > BLOCK_START (b)) | |
3087 | { | |
3088 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
3089 | print_frame_info. It might be better to move this check into |
3090 | symbol reading. */ | |
6c0d6680 DJ |
3091 | return NULL; |
3092 | } | |
3093 | ||
176620f1 | 3094 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 3095 | |
c906108c SS |
3096 | /* If we never found a PDR for this function in symbol reading, then |
3097 | examine prologues to find the information. */ | |
3098 | if (sym) | |
3099 | { | |
3100 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
3101 | if (PROC_FRAME_REG (proc_desc) == -1) | |
3102 | return NULL; | |
3103 | else | |
3104 | return proc_desc; | |
3105 | } | |
3106 | else | |
3107 | return NULL; | |
3108 | } | |
3109 | ||
c906108c SS |
3110 | /* MIPS stack frames are almost impenetrable. When execution stops, |
3111 | we basically have to look at symbol information for the function | |
3112 | that we stopped in, which tells us *which* register (if any) is | |
3113 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 3114 | the frame itself is at. |
c906108c SS |
3115 | |
3116 | This presents a problem when trying to examine a stack in memory | |
3117 | (that isn't executing at the moment), using the "frame" command. We | |
3118 | don't have a PC, nor do we have any registers except SP. | |
3119 | ||
3120 | This routine takes two arguments, SP and PC, and tries to make the | |
3121 | cached frames look as if these two arguments defined a frame on the | |
3122 | cache. This allows the rest of info frame to extract the important | |
3123 | arguments without difficulty. */ | |
3124 | ||
3125 | struct frame_info * | |
acdb74a0 | 3126 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
3127 | { |
3128 | if (argc != 2) | |
3129 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
3130 | ||
3131 | return create_new_frame (argv[0], argv[1]); | |
3132 | } | |
3133 | ||
f09ded24 AC |
3134 | /* According to the current ABI, should the type be passed in a |
3135 | floating-point register (assuming that there is space)? When there | |
3136 | is no FPU, FP are not even considered as possibile candidates for | |
3137 | FP registers and, consequently this returns false - forces FP | |
3138 | arguments into integer registers. */ | |
3139 | ||
3140 | static int | |
3141 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
3142 | { | |
3143 | return ((typecode == TYPE_CODE_FLT | |
3144 | || (MIPS_EABI | |
6d82d43b AC |
3145 | && (typecode == TYPE_CODE_STRUCT |
3146 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
3147 | && TYPE_NFIELDS (arg_type) == 1 |
3148 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 3149 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
3150 | } |
3151 | ||
49e790b0 DJ |
3152 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
3153 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
3154 | ||
3155 | static int | |
3156 | mips_type_needs_double_align (struct type *type) | |
3157 | { | |
3158 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 3159 | |
49e790b0 DJ |
3160 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
3161 | return 1; | |
3162 | else if (typecode == TYPE_CODE_STRUCT) | |
3163 | { | |
3164 | if (TYPE_NFIELDS (type) < 1) | |
3165 | return 0; | |
3166 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
3167 | } | |
3168 | else if (typecode == TYPE_CODE_UNION) | |
3169 | { | |
361d1df0 | 3170 | int i, n; |
49e790b0 DJ |
3171 | |
3172 | n = TYPE_NFIELDS (type); | |
3173 | for (i = 0; i < n; i++) | |
3174 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
3175 | return 1; | |
3176 | return 0; | |
3177 | } | |
3178 | return 0; | |
3179 | } | |
3180 | ||
dc604539 AC |
3181 | /* Adjust the address downward (direction of stack growth) so that it |
3182 | is correctly aligned for a new stack frame. */ | |
3183 | static CORE_ADDR | |
3184 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
3185 | { | |
5b03f266 | 3186 | return align_down (addr, 16); |
dc604539 AC |
3187 | } |
3188 | ||
6d82d43b AC |
3189 | /* Determine how a return value is stored within the MIPS register |
3190 | file, given the return type `valtype'. */ | |
3191 | ||
3192 | struct return_value_word | |
3193 | { | |
3194 | int len; | |
3195 | int reg; | |
3196 | int reg_offset; | |
3197 | int buf_offset; | |
3198 | }; | |
3199 | ||
3200 | static void | |
3201 | return_value_location (struct type *valtype, | |
3202 | struct return_value_word *hi, | |
3203 | struct return_value_word *lo) | |
3204 | { | |
3205 | int len = TYPE_LENGTH (valtype); | |
3206 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3207 | ||
3208 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3209 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3210 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3211 | { | |
ceae6e75 | 3212 | if (mips_abi_regsize (current_gdbarch) < 8 && len == 8) |
6d82d43b AC |
3213 | { |
3214 | /* We need to break a 64bit float in two 32 bit halves and | |
ceae6e75 | 3215 | spread them across a floating-point register pair. */ |
6d82d43b AC |
3216 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
3217 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
3218 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3219 | && register_size (current_gdbarch, | |
3220 | mips_regnum (current_gdbarch)-> | |
3221 | fp0) == 8) ? 4 : 0); | |
3222 | hi->reg_offset = lo->reg_offset; | |
3223 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
3224 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
3225 | lo->len = 4; | |
3226 | hi->len = 4; | |
3227 | } | |
3228 | else | |
3229 | { | |
3230 | /* The floating point value fits in a single floating-point | |
3231 | register. */ | |
3232 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3233 | && register_size (current_gdbarch, | |
3234 | mips_regnum (current_gdbarch)-> | |
3235 | fp0) == 8 | |
3236 | && len == 4) ? 4 : 0); | |
3237 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
3238 | lo->len = len; | |
3239 | lo->buf_offset = 0; | |
3240 | hi->len = 0; | |
3241 | hi->reg_offset = 0; | |
3242 | hi->buf_offset = 0; | |
3243 | hi->reg = 0; | |
3244 | } | |
3245 | } | |
3246 | else | |
3247 | { | |
3248 | /* Locate a result possibly spread across two registers. */ | |
3249 | int regnum = 2; | |
3250 | lo->reg = regnum + 0; | |
3251 | hi->reg = regnum + 1; | |
3252 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3253 | && len < mips_abi_regsize (current_gdbarch)) |
6d82d43b AC |
3254 | { |
3255 | /* "un-left-justify" the value in the low register */ | |
13326b4e | 3256 | lo->reg_offset = mips_abi_regsize (current_gdbarch) - len; |
6d82d43b AC |
3257 | lo->len = len; |
3258 | hi->reg_offset = 0; | |
3259 | hi->len = 0; | |
3260 | } | |
13326b4e AC |
3261 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_abi_regsize (current_gdbarch) /* odd-size structs */ |
3262 | && len < mips_abi_regsize (current_gdbarch) * 2 | |
6d82d43b AC |
3263 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
3264 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3265 | { | |
3266 | /* "un-left-justify" the value spread across two registers. */ | |
13326b4e AC |
3267 | lo->reg_offset = 2 * mips_abi_regsize (current_gdbarch) - len; |
3268 | lo->len = mips_abi_regsize (current_gdbarch) - lo->reg_offset; | |
6d82d43b AC |
3269 | hi->reg_offset = 0; |
3270 | hi->len = len - lo->len; | |
3271 | } | |
3272 | else | |
3273 | { | |
3274 | /* Only perform a partial copy of the second register. */ | |
3275 | lo->reg_offset = 0; | |
3276 | hi->reg_offset = 0; | |
13326b4e | 3277 | if (len > mips_abi_regsize (current_gdbarch)) |
6d82d43b | 3278 | { |
13326b4e AC |
3279 | lo->len = mips_abi_regsize (current_gdbarch); |
3280 | hi->len = len - mips_abi_regsize (current_gdbarch); | |
6d82d43b AC |
3281 | } |
3282 | else | |
3283 | { | |
3284 | lo->len = len; | |
3285 | hi->len = 0; | |
3286 | } | |
3287 | } | |
3288 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3289 | && register_size (current_gdbarch, regnum) == 8 | |
13326b4e | 3290 | && mips_abi_regsize (current_gdbarch) == 4) |
6d82d43b AC |
3291 | { |
3292 | /* Account for the fact that only the least-signficant part | |
3293 | of the register is being used */ | |
3294 | lo->reg_offset += 4; | |
3295 | hi->reg_offset += 4; | |
3296 | } | |
3297 | lo->buf_offset = 0; | |
3298 | hi->buf_offset = lo->len; | |
3299 | } | |
3300 | } | |
3301 | ||
3302 | /* Should call_function allocate stack space for a struct return? */ | |
3303 | ||
3304 | static int | |
3305 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
3306 | { | |
3307 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
13326b4e | 3308 | return (TYPE_LENGTH (type) > 2 * mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3309 | } |
3310 | ||
3311 | /* Should call_function pass struct by reference? | |
3312 | For each architecture, structs are passed either by | |
3313 | value or by reference, depending on their size. */ | |
3314 | ||
3315 | static int | |
3316 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
3317 | { | |
3318 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
3319 | int len = TYPE_LENGTH (check_typedef (type)); | |
3320 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3321 | ||
3322 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
13326b4e | 3323 | return (len > mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3324 | |
3325 | return 0; | |
3326 | } | |
3327 | ||
f7ab6ec6 | 3328 | static CORE_ADDR |
7d9b040b | 3329 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3330 | struct regcache *regcache, CORE_ADDR bp_addr, |
3331 | int nargs, struct value **args, CORE_ADDR sp, | |
3332 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
3333 | { |
3334 | int argreg; | |
3335 | int float_argreg; | |
3336 | int argnum; | |
3337 | int len = 0; | |
3338 | int stack_offset = 0; | |
480d3dd2 | 3339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3340 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 3341 | |
25ab4790 AC |
3342 | /* For shared libraries, "t9" needs to point at the function |
3343 | address. */ | |
3344 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3345 | ||
3346 | /* Set the return address register to point to the entry point of | |
3347 | the program, where a breakpoint lies in wait. */ | |
3348 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3349 | ||
c906108c | 3350 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
3351 | are properly aligned. The stack has to be at least 64-bit |
3352 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3353 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3354 | aligned, so we round to this widest known alignment. */ | |
3355 | ||
5b03f266 AC |
3356 | sp = align_down (sp, 16); |
3357 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 3358 | |
46e0f506 | 3359 | /* Now make space on the stack for the args. We allocate more |
c906108c | 3360 | than necessary for EABI, because the first few arguments are |
46e0f506 | 3361 | passed in registers, but that's OK. */ |
c906108c | 3362 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 3363 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3364 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3365 | sp -= align_up (len, 16); |
c906108c | 3366 | |
9ace0497 | 3367 | if (mips_debug) |
6d82d43b | 3368 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3369 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
3370 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 3371 | |
c906108c SS |
3372 | /* Initialize the integer and float register pointers. */ |
3373 | argreg = A0_REGNUM; | |
56cea623 | 3374 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 3375 | |
46e0f506 | 3376 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 3377 | if (struct_return) |
9ace0497 AC |
3378 | { |
3379 | if (mips_debug) | |
3380 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3381 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3382 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
3383 | write_register (argreg++, struct_addr); |
3384 | } | |
c906108c SS |
3385 | |
3386 | /* Now load as many as possible of the first arguments into | |
3387 | registers, and push the rest onto the stack. Loop thru args | |
3388 | from first to last. */ | |
3389 | for (argnum = 0; argnum < nargs; argnum++) | |
3390 | { | |
3391 | char *val; | |
d9d9c31f | 3392 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 3393 | struct value *arg = args[argnum]; |
c906108c SS |
3394 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
3395 | int len = TYPE_LENGTH (arg_type); | |
3396 | enum type_code typecode = TYPE_CODE (arg_type); | |
3397 | ||
9ace0497 AC |
3398 | if (mips_debug) |
3399 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3400 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3401 | argnum + 1, len, (int) typecode); |
9ace0497 | 3402 | |
c906108c | 3403 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3404 | reference. */ |
13326b4e | 3405 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 3406 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3407 | { |
13326b4e | 3408 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 3409 | VALUE_ADDRESS (arg)); |
c906108c | 3410 | typecode = TYPE_CODE_PTR; |
13326b4e | 3411 | len = mips_abi_regsize (gdbarch); |
c906108c | 3412 | val = valbuf; |
9ace0497 AC |
3413 | if (mips_debug) |
3414 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3415 | } |
3416 | else | |
c5aa993b | 3417 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
3418 | |
3419 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3420 | even-numbered floating point register. Round the FP register |
3421 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3422 | left. Non MIPS_EABI targets also pass the FP in the integer |
3423 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3424 | if (mips_abi_regsize (gdbarch) < 8 |
3425 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
3426 | { |
3427 | if ((float_argreg & 1)) | |
3428 | float_argreg++; | |
3429 | } | |
c906108c SS |
3430 | |
3431 | /* Floating point arguments passed in registers have to be | |
3432 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3433 | are passed in register pairs; the even register gets |
3434 | the low word, and the odd register gets the high word. | |
3435 | On non-EABI processors, the first two floating point arguments are | |
3436 | also copied to general registers, because MIPS16 functions | |
3437 | don't use float registers for arguments. This duplication of | |
3438 | arguments in general registers can't hurt non-MIPS16 functions | |
3439 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3440 | /* MIPS_EABI squeezes a struct that contains a single floating |
3441 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3442 | stack. */ |
f09ded24 AC |
3443 | if (fp_register_arg_p (typecode, arg_type) |
3444 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 3445 | { |
ceae6e75 | 3446 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 3447 | { |
d7449b42 | 3448 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
3449 | unsigned long regval; |
3450 | ||
3451 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 3452 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 3453 | if (mips_debug) |
acdb74a0 | 3454 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3455 | float_argreg, phex (regval, 4)); |
c906108c | 3456 | write_register (float_argreg++, regval); |
c906108c SS |
3457 | |
3458 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 3459 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 3460 | if (mips_debug) |
acdb74a0 | 3461 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3462 | float_argreg, phex (regval, 4)); |
c906108c | 3463 | write_register (float_argreg++, regval); |
c906108c SS |
3464 | } |
3465 | else | |
3466 | { | |
3467 | /* This is a floating point value that fits entirely | |
3468 | in a single register. */ | |
53a5351d | 3469 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3470 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
3471 | LONGEST regval = extract_unsigned_integer (val, len); |
3472 | if (mips_debug) | |
acdb74a0 | 3473 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3474 | float_argreg, phex (regval, len)); |
c906108c | 3475 | write_register (float_argreg++, regval); |
c906108c SS |
3476 | } |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | /* Copy the argument to general registers or the stack in | |
3481 | register-sized pieces. Large arguments are split between | |
3482 | registers and stack. */ | |
4246e332 | 3483 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3484 | mips_abi_regsize() are treated specially: Irix cc passes |
3485 | them in registers where gcc sometimes puts them on the | |
3486 | stack. For maximum compatibility, we will put them in | |
3487 | both places. */ | |
13326b4e AC |
3488 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3489 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 3490 | |
f09ded24 | 3491 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3492 | register are only written to memory. */ |
c906108c SS |
3493 | while (len > 0) |
3494 | { | |
ebafbe83 | 3495 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3496 | int stack_used_p = 0; |
13326b4e AC |
3497 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3498 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 3499 | |
acdb74a0 AC |
3500 | if (mips_debug) |
3501 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3502 | partial_len); | |
3503 | ||
566f0f7a | 3504 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3505 | if (argreg > MIPS_LAST_ARG_REGNUM |
3506 | || odd_sized_struct | |
3507 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3508 | { |
c906108c SS |
3509 | /* Should shorter than int integer values be |
3510 | promoted to int before being stored? */ | |
c906108c | 3511 | int longword_offset = 0; |
9ace0497 | 3512 | CORE_ADDR addr; |
566f0f7a | 3513 | stack_used_p = 1; |
d7449b42 | 3514 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3515 | { |
13326b4e | 3516 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3517 | && (typecode == TYPE_CODE_INT |
3518 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3519 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3520 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
3521 | else if ((typecode == TYPE_CODE_STRUCT |
3522 | || typecode == TYPE_CODE_UNION) | |
3523 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
3524 | < mips_stack_argsize (gdbarch))) |
3525 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 3526 | } |
c5aa993b | 3527 | |
9ace0497 AC |
3528 | if (mips_debug) |
3529 | { | |
cb3d25d1 MS |
3530 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3531 | paddr_nz (stack_offset)); | |
3532 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3533 | paddr_nz (longword_offset)); | |
9ace0497 | 3534 | } |
361d1df0 | 3535 | |
9ace0497 AC |
3536 | addr = sp + stack_offset + longword_offset; |
3537 | ||
3538 | if (mips_debug) | |
3539 | { | |
3540 | int i; | |
6d82d43b | 3541 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3542 | paddr_nz (addr)); |
9ace0497 AC |
3543 | for (i = 0; i < partial_len; i++) |
3544 | { | |
6d82d43b | 3545 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3546 | val[i] & 0xff); |
9ace0497 AC |
3547 | } |
3548 | } | |
3549 | write_memory (addr, val, partial_len); | |
c906108c SS |
3550 | } |
3551 | ||
f09ded24 AC |
3552 | /* Note!!! This is NOT an else clause. Odd sized |
3553 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3554 | arguments will not. */ |
566f0f7a | 3555 | /* Write this portion of the argument to a general |
6d82d43b | 3556 | purpose register. */ |
f09ded24 AC |
3557 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3558 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3559 | { |
6d82d43b AC |
3560 | LONGEST regval = |
3561 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3562 | |
9ace0497 | 3563 | if (mips_debug) |
acdb74a0 | 3564 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3565 | argreg, |
6d82d43b | 3566 | phex (regval, |
13326b4e | 3567 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3568 | write_register (argreg, regval); |
3569 | argreg++; | |
c906108c | 3570 | } |
c5aa993b | 3571 | |
c906108c SS |
3572 | len -= partial_len; |
3573 | val += partial_len; | |
3574 | ||
566f0f7a | 3575 | /* Compute the the offset into the stack at which we |
6d82d43b | 3576 | will copy the next parameter. |
566f0f7a | 3577 | |
566f0f7a | 3578 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3579 | only needs to be adjusted when it has been used. */ |
c906108c | 3580 | |
46e0f506 | 3581 | if (stack_used_p) |
480d3dd2 | 3582 | stack_offset += align_up (partial_len, |
13326b4e | 3583 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3584 | } |
3585 | } | |
9ace0497 AC |
3586 | if (mips_debug) |
3587 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3588 | } |
3589 | ||
f10683bb | 3590 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3591 | |
0f71a2f6 JM |
3592 | /* Return adjusted stack pointer. */ |
3593 | return sp; | |
3594 | } | |
3595 | ||
6d82d43b AC |
3596 | /* Given a return value in `regbuf' with a type `valtype', extract and |
3597 | copy its value into `valbuf'. */ | |
3598 | ||
3599 | static void | |
3600 | mips_eabi_extract_return_value (struct type *valtype, | |
3601 | char regbuf[], char *valbuf) | |
3602 | { | |
3603 | struct return_value_word lo; | |
3604 | struct return_value_word hi; | |
3605 | return_value_location (valtype, &hi, &lo); | |
3606 | ||
3607 | memcpy (valbuf + lo.buf_offset, | |
3608 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
3609 | lo.reg_offset, lo.len); | |
3610 | ||
3611 | if (hi.len > 0) | |
3612 | memcpy (valbuf + hi.buf_offset, | |
3613 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3614 | hi.reg_offset, hi.len); | |
3615 | } | |
3616 | ||
3617 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3618 | value into the appropriate register. */ | |
3619 | ||
3620 | static void | |
3621 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3622 | { | |
3623 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3624 | struct return_value_word lo; | |
3625 | struct return_value_word hi; | |
3626 | return_value_location (valtype, &hi, &lo); | |
3627 | ||
3628 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3629 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3630 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3631 | raw_buffer, register_size (current_gdbarch, | |
3632 | lo.reg)); | |
3633 | ||
3634 | if (hi.len > 0) | |
3635 | { | |
3636 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3637 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3638 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3639 | raw_buffer, | |
3640 | register_size (current_gdbarch, | |
3641 | hi.reg)); | |
3642 | } | |
3643 | } | |
3644 | ||
3645 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3646 | |
f7ab6ec6 | 3647 | static CORE_ADDR |
7d9b040b | 3648 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3649 | struct regcache *regcache, CORE_ADDR bp_addr, |
3650 | int nargs, struct value **args, CORE_ADDR sp, | |
3651 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3652 | { |
3653 | int argreg; | |
3654 | int float_argreg; | |
3655 | int argnum; | |
3656 | int len = 0; | |
3657 | int stack_offset = 0; | |
480d3dd2 | 3658 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3659 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3660 | |
25ab4790 AC |
3661 | /* For shared libraries, "t9" needs to point at the function |
3662 | address. */ | |
3663 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3664 | ||
3665 | /* Set the return address register to point to the entry point of | |
3666 | the program, where a breakpoint lies in wait. */ | |
3667 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3668 | ||
cb3d25d1 MS |
3669 | /* First ensure that the stack and structure return address (if any) |
3670 | are properly aligned. The stack has to be at least 64-bit | |
3671 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3672 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3673 | aligned, so we round to this widest known alignment. */ | |
3674 | ||
5b03f266 AC |
3675 | sp = align_down (sp, 16); |
3676 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3677 | |
3678 | /* Now make space on the stack for the args. */ | |
3679 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3680 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3681 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3682 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3683 | |
3684 | if (mips_debug) | |
6d82d43b | 3685 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3686 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3687 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3688 | |
3689 | /* Initialize the integer and float register pointers. */ | |
3690 | argreg = A0_REGNUM; | |
56cea623 | 3691 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3692 | |
46e0f506 | 3693 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3694 | if (struct_return) |
3695 | { | |
3696 | if (mips_debug) | |
3697 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3698 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3699 | argreg, paddr_nz (struct_addr)); |
3700 | write_register (argreg++, struct_addr); | |
3701 | } | |
3702 | ||
3703 | /* Now load as many as possible of the first arguments into | |
3704 | registers, and push the rest onto the stack. Loop thru args | |
3705 | from first to last. */ | |
3706 | for (argnum = 0; argnum < nargs; argnum++) | |
3707 | { | |
3708 | char *val; | |
cb3d25d1 MS |
3709 | struct value *arg = args[argnum]; |
3710 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3711 | int len = TYPE_LENGTH (arg_type); | |
3712 | enum type_code typecode = TYPE_CODE (arg_type); | |
3713 | ||
3714 | if (mips_debug) | |
3715 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3716 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3717 | argnum + 1, len, (int) typecode); |
3718 | ||
3719 | val = (char *) VALUE_CONTENTS (arg); | |
3720 | ||
3721 | if (fp_register_arg_p (typecode, arg_type) | |
3722 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3723 | { | |
3724 | /* This is a floating point value that fits entirely | |
3725 | in a single register. */ | |
3726 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3727 | above to ensure that it is even register aligned. */ | |
3728 | LONGEST regval = extract_unsigned_integer (val, len); | |
3729 | if (mips_debug) | |
3730 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3731 | float_argreg, phex (regval, len)); | |
3732 | write_register (float_argreg++, regval); | |
3733 | ||
3734 | if (mips_debug) | |
3735 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3736 | argreg, phex (regval, len)); | |
3737 | write_register (argreg, regval); | |
3738 | argreg += 1; | |
3739 | } | |
3740 | else | |
3741 | { | |
3742 | /* Copy the argument to general registers or the stack in | |
3743 | register-sized pieces. Large arguments are split between | |
3744 | registers and stack. */ | |
4246e332 | 3745 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3746 | mips_abi_regsize() are treated specially: Irix cc passes |
3747 | them in registers where gcc sometimes puts them on the | |
3748 | stack. For maximum compatibility, we will put them in | |
3749 | both places. */ | |
13326b4e AC |
3750 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3751 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3752 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3753 | register are only written to memory. */ |
cb3d25d1 MS |
3754 | while (len > 0) |
3755 | { | |
3756 | /* Rememer if the argument was written to the stack. */ | |
3757 | int stack_used_p = 0; | |
13326b4e AC |
3758 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3759 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3760 | |
3761 | if (mips_debug) | |
3762 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3763 | partial_len); | |
3764 | ||
3765 | /* Write this portion of the argument to the stack. */ | |
3766 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3767 | || odd_sized_struct | |
3768 | || fp_register_arg_p (typecode, arg_type)) | |
3769 | { | |
3770 | /* Should shorter than int integer values be | |
3771 | promoted to int before being stored? */ | |
3772 | int longword_offset = 0; | |
3773 | CORE_ADDR addr; | |
3774 | stack_used_p = 1; | |
3775 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3776 | { | |
13326b4e | 3777 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3778 | && (typecode == TYPE_CODE_INT |
3779 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3780 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3781 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3782 | } |
3783 | ||
3784 | if (mips_debug) | |
3785 | { | |
3786 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3787 | paddr_nz (stack_offset)); | |
3788 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3789 | paddr_nz (longword_offset)); | |
3790 | } | |
3791 | ||
3792 | addr = sp + stack_offset + longword_offset; | |
3793 | ||
3794 | if (mips_debug) | |
3795 | { | |
3796 | int i; | |
6d82d43b | 3797 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3798 | paddr_nz (addr)); |
3799 | for (i = 0; i < partial_len; i++) | |
3800 | { | |
6d82d43b | 3801 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3802 | val[i] & 0xff); |
3803 | } | |
3804 | } | |
3805 | write_memory (addr, val, partial_len); | |
3806 | } | |
3807 | ||
3808 | /* Note!!! This is NOT an else clause. Odd sized | |
3809 | structs may go thru BOTH paths. Floating point | |
3810 | arguments will not. */ | |
3811 | /* Write this portion of the argument to a general | |
6d82d43b | 3812 | purpose register. */ |
cb3d25d1 MS |
3813 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3814 | && !fp_register_arg_p (typecode, arg_type)) | |
3815 | { | |
6d82d43b AC |
3816 | LONGEST regval = |
3817 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3818 | |
3819 | /* A non-floating-point argument being passed in a | |
3820 | general register. If a struct or union, and if | |
3821 | the remaining length is smaller than the register | |
3822 | size, we have to adjust the register value on | |
3823 | big endian targets. | |
3824 | ||
3825 | It does not seem to be necessary to do the | |
3826 | same for integral types. | |
3827 | ||
3828 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3829 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3830 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3831 | part of storing the argument in a register a |
3832 | register (the left shift isn't generated when | |
1b13c4f6 | 3833 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3834 | it is quite possible that this is GCC |
3835 | contradicting the LE/O32 ABI, GDB has not been | |
3836 | adjusted to accommodate this. Either someone | |
3837 | needs to demonstrate that the LE/O32 ABI | |
3838 | specifies such a left shift OR this new ABI gets | |
3839 | identified as such and GDB gets tweaked | |
3840 | accordingly. */ | |
cb3d25d1 MS |
3841 | |
3842 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3843 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3844 | && (typecode == TYPE_CODE_STRUCT || |
3845 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3846 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3847 | TARGET_CHAR_BIT); |
3848 | ||
3849 | if (mips_debug) | |
3850 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3851 | argreg, | |
6d82d43b | 3852 | phex (regval, |
13326b4e | 3853 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3854 | write_register (argreg, regval); |
3855 | argreg++; | |
3856 | } | |
3857 | ||
3858 | len -= partial_len; | |
3859 | val += partial_len; | |
3860 | ||
3861 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3862 | will copy the next parameter. |
cb3d25d1 MS |
3863 | |
3864 | In N32 (N64?), the stack_offset only needs to be | |
3865 | adjusted when it has been used. */ | |
3866 | ||
3867 | if (stack_used_p) | |
480d3dd2 | 3868 | stack_offset += align_up (partial_len, |
13326b4e | 3869 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3870 | } |
3871 | } | |
3872 | if (mips_debug) | |
3873 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3874 | } | |
3875 | ||
f10683bb | 3876 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3877 | |
cb3d25d1 MS |
3878 | /* Return adjusted stack pointer. */ |
3879 | return sp; | |
3880 | } | |
3881 | ||
6d82d43b AC |
3882 | static enum return_value_convention |
3883 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3884 | struct type *type, struct regcache *regcache, | |
3885 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3886 | { |
6d82d43b AC |
3887 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3888 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3889 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3890 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3891 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3892 | return RETURN_VALUE_STRUCT_CONVENTION; |
3893 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3894 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3895 | { | |
3896 | /* A floating-point value belongs in the least significant part | |
3897 | of FP0. */ | |
3898 | if (mips_debug) | |
3899 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3900 | mips_xfer_register (regcache, | |
3901 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3902 | TYPE_LENGTH (type), | |
3903 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3904 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3905 | } | |
3906 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3907 | && TYPE_NFIELDS (type) <= 2 | |
3908 | && TYPE_NFIELDS (type) >= 1 | |
3909 | && ((TYPE_NFIELDS (type) == 1 | |
3910 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3911 | == TYPE_CODE_FLT)) | |
3912 | || (TYPE_NFIELDS (type) == 2 | |
3913 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3914 | == TYPE_CODE_FLT) | |
3915 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3916 | == TYPE_CODE_FLT))) | |
3917 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3918 | { | |
3919 | /* A struct that contains one or two floats. Each value is part | |
3920 | in the least significant part of their floating point | |
3921 | register.. */ | |
6d82d43b AC |
3922 | int regnum; |
3923 | int field; | |
3924 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3925 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3926 | { | |
3927 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3928 | / TARGET_CHAR_BIT); | |
3929 | if (mips_debug) | |
3930 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3931 | offset); | |
3932 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3933 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3934 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3935 | } | |
3936 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3937 | } | |
3938 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3939 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3940 | { | |
3941 | /* A structure or union. Extract the left justified value, | |
3942 | regardless of the byte order. I.e. DO NOT USE | |
3943 | mips_xfer_lower. */ | |
3944 | int offset; | |
3945 | int regnum; | |
3946 | for (offset = 0, regnum = V0_REGNUM; | |
3947 | offset < TYPE_LENGTH (type); | |
3948 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3949 | { | |
3950 | int xfer = register_size (current_gdbarch, regnum); | |
3951 | if (offset + xfer > TYPE_LENGTH (type)) | |
3952 | xfer = TYPE_LENGTH (type) - offset; | |
3953 | if (mips_debug) | |
3954 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3955 | offset, xfer, regnum); | |
3956 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3957 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3958 | } | |
3959 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3960 | } | |
3961 | else | |
3962 | { | |
3963 | /* A scalar extract each part but least-significant-byte | |
3964 | justified. */ | |
3965 | int offset; | |
3966 | int regnum; | |
3967 | for (offset = 0, regnum = V0_REGNUM; | |
3968 | offset < TYPE_LENGTH (type); | |
3969 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3970 | { | |
3971 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3972 | if (offset + xfer > TYPE_LENGTH (type)) |
3973 | xfer = TYPE_LENGTH (type) - offset; | |
3974 | if (mips_debug) | |
3975 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3976 | offset, xfer, regnum); | |
3977 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3978 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3979 | } | |
3980 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3981 | } | |
3982 | } | |
3983 | ||
3984 | /* O32 ABI stuff. */ | |
3985 | ||
3986 | static CORE_ADDR | |
7d9b040b | 3987 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3988 | struct regcache *regcache, CORE_ADDR bp_addr, |
3989 | int nargs, struct value **args, CORE_ADDR sp, | |
3990 | int struct_return, CORE_ADDR struct_addr) | |
3991 | { | |
3992 | int argreg; | |
3993 | int float_argreg; | |
3994 | int argnum; | |
3995 | int len = 0; | |
3996 | int stack_offset = 0; | |
3997 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3998 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3999 | |
4000 | /* For shared libraries, "t9" needs to point at the function | |
4001 | address. */ | |
4002 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
4003 | ||
4004 | /* Set the return address register to point to the entry point of | |
4005 | the program, where a breakpoint lies in wait. */ | |
4006 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
4007 | ||
4008 | /* First ensure that the stack and structure return address (if any) | |
4009 | are properly aligned. The stack has to be at least 64-bit | |
4010 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
4011 | aligned. For n32 and n64, stack frames need to be 128-bit |
4012 | aligned, so we round to this widest known alignment. */ | |
4013 | ||
5b03f266 AC |
4014 | sp = align_down (sp, 16); |
4015 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
4016 | |
4017 | /* Now make space on the stack for the args. */ | |
4018 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4019 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4020 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4021 | sp -= align_up (len, 16); |
ebafbe83 MS |
4022 | |
4023 | if (mips_debug) | |
6d82d43b | 4024 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4025 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
4026 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
4027 | |
4028 | /* Initialize the integer and float register pointers. */ | |
4029 | argreg = A0_REGNUM; | |
56cea623 | 4030 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 4031 | |
bcb0cc15 | 4032 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
4033 | if (struct_return) |
4034 | { | |
4035 | if (mips_debug) | |
4036 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4037 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
4038 | argreg, paddr_nz (struct_addr)); |
4039 | write_register (argreg++, struct_addr); | |
13326b4e | 4040 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
4041 | } |
4042 | ||
4043 | /* Now load as many as possible of the first arguments into | |
4044 | registers, and push the rest onto the stack. Loop thru args | |
4045 | from first to last. */ | |
4046 | for (argnum = 0; argnum < nargs; argnum++) | |
4047 | { | |
4048 | char *val; | |
ebafbe83 MS |
4049 | struct value *arg = args[argnum]; |
4050 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4051 | int len = TYPE_LENGTH (arg_type); | |
4052 | enum type_code typecode = TYPE_CODE (arg_type); | |
4053 | ||
4054 | if (mips_debug) | |
4055 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4056 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
4057 | argnum + 1, len, (int) typecode); |
4058 | ||
4059 | val = (char *) VALUE_CONTENTS (arg); | |
4060 | ||
4061 | /* 32-bit ABIs always start floating point arguments in an | |
4062 | even-numbered floating point register. Round the FP register | |
4063 | up before the check to see if there are any FP registers | |
4064 | left. O32/O64 targets also pass the FP in the integer | |
4065 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4066 | if (mips_abi_regsize (gdbarch) < 8 |
4067 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
4068 | { |
4069 | if ((float_argreg & 1)) | |
4070 | float_argreg++; | |
4071 | } | |
4072 | ||
4073 | /* Floating point arguments passed in registers have to be | |
4074 | treated specially. On 32-bit architectures, doubles | |
4075 | are passed in register pairs; the even register gets | |
4076 | the low word, and the odd register gets the high word. | |
4077 | On O32/O64, the first two floating point arguments are | |
4078 | also copied to general registers, because MIPS16 functions | |
4079 | don't use float registers for arguments. This duplication of | |
4080 | arguments in general registers can't hurt non-MIPS16 functions | |
4081 | because those registers are normally skipped. */ | |
4082 | ||
4083 | if (fp_register_arg_p (typecode, arg_type) | |
4084 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4085 | { | |
ceae6e75 | 4086 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
4087 | { |
4088 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4089 | unsigned long regval; | |
4090 | ||
4091 | /* Write the low word of the double to the even register(s). */ | |
4092 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4093 | if (mips_debug) | |
4094 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4095 | float_argreg, phex (regval, 4)); | |
4096 | write_register (float_argreg++, regval); | |
4097 | if (mips_debug) | |
4098 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4099 | argreg, phex (regval, 4)); | |
4100 | write_register (argreg++, regval); | |
4101 | ||
4102 | /* Write the high word of the double to the odd register(s). */ | |
4103 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4104 | if (mips_debug) | |
4105 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4106 | float_argreg, phex (regval, 4)); | |
4107 | write_register (float_argreg++, regval); | |
4108 | ||
4109 | if (mips_debug) | |
4110 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4111 | argreg, phex (regval, 4)); | |
4112 | write_register (argreg++, regval); | |
4113 | } | |
4114 | else | |
4115 | { | |
4116 | /* This is a floating point value that fits entirely | |
4117 | in a single register. */ | |
4118 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4119 | above to ensure that it is even register aligned. */ |
46cac009 AC |
4120 | LONGEST regval = extract_unsigned_integer (val, len); |
4121 | if (mips_debug) | |
4122 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4123 | float_argreg, phex (regval, len)); | |
4124 | write_register (float_argreg++, regval); | |
4125 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4126 | registers for each argument. The below is (my |
4127 | guess) to ensure that the corresponding integer | |
4128 | register has reserved the same space. */ | |
46cac009 AC |
4129 | if (mips_debug) |
4130 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4131 | argreg, phex (regval, len)); | |
4132 | write_register (argreg, regval); | |
ceae6e75 | 4133 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
4134 | } |
4135 | /* Reserve space for the FP register. */ | |
13326b4e | 4136 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
4137 | } |
4138 | else | |
4139 | { | |
4140 | /* Copy the argument to general registers or the stack in | |
4141 | register-sized pieces. Large arguments are split between | |
4142 | registers and stack. */ | |
4246e332 | 4143 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4144 | mips_abi_regsize() are treated specially: Irix cc passes |
4145 | them in registers where gcc sometimes puts them on the | |
4146 | stack. For maximum compatibility, we will put them in | |
4147 | both places. */ | |
13326b4e AC |
4148 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4149 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
4150 | /* Structures should be aligned to eight bytes (even arg registers) |
4151 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4152 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
4153 | && mips_type_needs_double_align (arg_type)) |
4154 | { | |
4155 | if ((argreg & 1)) | |
6d82d43b | 4156 | argreg++; |
46cac009 AC |
4157 | } |
4158 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4159 | register are only written to memory. */ |
46cac009 AC |
4160 | while (len > 0) |
4161 | { | |
4162 | /* Remember if the argument was written to the stack. */ | |
4163 | int stack_used_p = 0; | |
13326b4e AC |
4164 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4165 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
4166 | |
4167 | if (mips_debug) | |
4168 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4169 | partial_len); | |
4170 | ||
4171 | /* Write this portion of the argument to the stack. */ | |
4172 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4173 | || odd_sized_struct | |
4174 | || fp_register_arg_p (typecode, arg_type)) | |
4175 | { | |
4176 | /* Should shorter than int integer values be | |
4177 | promoted to int before being stored? */ | |
4178 | int longword_offset = 0; | |
4179 | CORE_ADDR addr; | |
4180 | stack_used_p = 1; | |
4181 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4182 | { | |
13326b4e | 4183 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4184 | && (typecode == TYPE_CODE_INT |
4185 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4186 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4187 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
4188 | } |
4189 | ||
4190 | if (mips_debug) | |
4191 | { | |
4192 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4193 | paddr_nz (stack_offset)); | |
4194 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4195 | paddr_nz (longword_offset)); | |
4196 | } | |
4197 | ||
4198 | addr = sp + stack_offset + longword_offset; | |
4199 | ||
4200 | if (mips_debug) | |
4201 | { | |
4202 | int i; | |
6d82d43b | 4203 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
4204 | paddr_nz (addr)); |
4205 | for (i = 0; i < partial_len; i++) | |
4206 | { | |
6d82d43b | 4207 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
4208 | val[i] & 0xff); |
4209 | } | |
4210 | } | |
4211 | write_memory (addr, val, partial_len); | |
4212 | } | |
4213 | ||
4214 | /* Note!!! This is NOT an else clause. Odd sized | |
4215 | structs may go thru BOTH paths. Floating point | |
4216 | arguments will not. */ | |
4217 | /* Write this portion of the argument to a general | |
6d82d43b | 4218 | purpose register. */ |
46cac009 AC |
4219 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4220 | && !fp_register_arg_p (typecode, arg_type)) | |
4221 | { | |
4222 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4223 | /* Value may need to be sign extended, because |
1b13c4f6 | 4224 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
4225 | |
4226 | /* A non-floating-point argument being passed in a | |
4227 | general register. If a struct or union, and if | |
4228 | the remaining length is smaller than the register | |
4229 | size, we have to adjust the register value on | |
4230 | big endian targets. | |
4231 | ||
4232 | It does not seem to be necessary to do the | |
4233 | same for integral types. | |
4234 | ||
4235 | Also don't do this adjustment on O64 binaries. | |
4236 | ||
4237 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4238 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4239 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
4240 | part of storing the argument in a register a |
4241 | register (the left shift isn't generated when | |
1b13c4f6 | 4242 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4243 | it is quite possible that this is GCC |
4244 | contradicting the LE/O32 ABI, GDB has not been | |
4245 | adjusted to accommodate this. Either someone | |
4246 | needs to demonstrate that the LE/O32 ABI | |
4247 | specifies such a left shift OR this new ABI gets | |
4248 | identified as such and GDB gets tweaked | |
4249 | accordingly. */ | |
4250 | ||
13326b4e | 4251 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 4252 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4253 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
4254 | && (typecode == TYPE_CODE_STRUCT || |
4255 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4256 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
4257 | TARGET_CHAR_BIT); |
4258 | ||
4259 | if (mips_debug) | |
4260 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4261 | argreg, | |
6d82d43b | 4262 | phex (regval, |
13326b4e | 4263 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
4264 | write_register (argreg, regval); |
4265 | argreg++; | |
4266 | ||
4267 | /* Prevent subsequent floating point arguments from | |
4268 | being passed in floating point registers. */ | |
4269 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4270 | } | |
4271 | ||
4272 | len -= partial_len; | |
4273 | val += partial_len; | |
4274 | ||
4275 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4276 | will copy the next parameter. |
46cac009 | 4277 | |
6d82d43b AC |
4278 | In older ABIs, the caller reserved space for |
4279 | registers that contained arguments. This was loosely | |
4280 | refered to as their "home". Consequently, space is | |
4281 | always allocated. */ | |
46cac009 | 4282 | |
480d3dd2 | 4283 | stack_offset += align_up (partial_len, |
13326b4e | 4284 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
4285 | } |
4286 | } | |
4287 | if (mips_debug) | |
4288 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4289 | } | |
4290 | ||
f10683bb | 4291 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4292 | |
46cac009 AC |
4293 | /* Return adjusted stack pointer. */ |
4294 | return sp; | |
4295 | } | |
4296 | ||
6d82d43b AC |
4297 | static enum return_value_convention |
4298 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4299 | struct regcache *regcache, | |
4300 | void *readbuf, const void *writebuf) | |
4301 | { | |
4302 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4303 | ||
4304 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4305 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4306 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4307 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4308 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4309 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4310 | { | |
4311 | /* A single-precision floating-point value. It fits in the | |
4312 | least significant part of FP0. */ | |
4313 | if (mips_debug) | |
4314 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4315 | mips_xfer_register (regcache, | |
4316 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4317 | TYPE_LENGTH (type), | |
4318 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4319 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4320 | } | |
4321 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4322 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4323 | { | |
4324 | /* A double-precision floating-point value. The most | |
4325 | significant part goes in FP1, and the least significant in | |
4326 | FP0. */ | |
4327 | if (mips_debug) | |
4328 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4329 | switch (TARGET_BYTE_ORDER) | |
4330 | { | |
4331 | case BFD_ENDIAN_LITTLE: | |
4332 | mips_xfer_register (regcache, | |
4333 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4334 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4335 | mips_xfer_register (regcache, | |
4336 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4337 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4338 | break; | |
4339 | case BFD_ENDIAN_BIG: | |
4340 | mips_xfer_register (regcache, | |
4341 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4342 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4343 | mips_xfer_register (regcache, | |
4344 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4345 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4346 | break; | |
4347 | default: | |
4348 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4349 | } | |
4350 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4351 | } | |
4352 | #if 0 | |
4353 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4354 | && TYPE_NFIELDS (type) <= 2 | |
4355 | && TYPE_NFIELDS (type) >= 1 | |
4356 | && ((TYPE_NFIELDS (type) == 1 | |
4357 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4358 | == TYPE_CODE_FLT)) | |
4359 | || (TYPE_NFIELDS (type) == 2 | |
4360 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4361 | == TYPE_CODE_FLT) | |
4362 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4363 | == TYPE_CODE_FLT))) | |
4364 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4365 | { | |
4366 | /* A struct that contains one or two floats. Each value is part | |
4367 | in the least significant part of their floating point | |
4368 | register.. */ | |
4369 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
4370 | int regnum; | |
4371 | int field; | |
4372 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
4373 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
4374 | { | |
4375 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4376 | / TARGET_CHAR_BIT); | |
4377 | if (mips_debug) | |
4378 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4379 | offset); | |
4380 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
4381 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4382 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4383 | } | |
4384 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4385 | } | |
4386 | #endif | |
4387 | #if 0 | |
4388 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4389 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4390 | { | |
4391 | /* A structure or union. Extract the left justified value, | |
4392 | regardless of the byte order. I.e. DO NOT USE | |
4393 | mips_xfer_lower. */ | |
4394 | int offset; | |
4395 | int regnum; | |
4396 | for (offset = 0, regnum = V0_REGNUM; | |
4397 | offset < TYPE_LENGTH (type); | |
4398 | offset += register_size (current_gdbarch, regnum), regnum++) | |
4399 | { | |
4400 | int xfer = register_size (current_gdbarch, regnum); | |
4401 | if (offset + xfer > TYPE_LENGTH (type)) | |
4402 | xfer = TYPE_LENGTH (type) - offset; | |
4403 | if (mips_debug) | |
4404 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4405 | offset, xfer, regnum); | |
4406 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4407 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
4408 | } | |
4409 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4410 | } | |
4411 | #endif | |
4412 | else | |
4413 | { | |
4414 | /* A scalar extract each part but least-significant-byte | |
4415 | justified. o32 thinks registers are 4 byte, regardless of | |
4416 | the ISA. mips_stack_argsize controls this. */ | |
4417 | int offset; | |
4418 | int regnum; | |
4419 | for (offset = 0, regnum = V0_REGNUM; | |
4420 | offset < TYPE_LENGTH (type); | |
13326b4e | 4421 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 4422 | { |
13326b4e | 4423 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
4424 | if (offset + xfer > TYPE_LENGTH (type)) |
4425 | xfer = TYPE_LENGTH (type) - offset; | |
4426 | if (mips_debug) | |
4427 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4428 | offset, xfer, regnum); | |
4429 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4430 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4431 | } | |
4432 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4433 | } | |
4434 | } | |
4435 | ||
4436 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4437 | ABI. */ | |
46cac009 AC |
4438 | |
4439 | static CORE_ADDR | |
7d9b040b | 4440 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4441 | struct regcache *regcache, CORE_ADDR bp_addr, |
4442 | int nargs, | |
4443 | struct value **args, CORE_ADDR sp, | |
4444 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4445 | { |
4446 | int argreg; | |
4447 | int float_argreg; | |
4448 | int argnum; | |
4449 | int len = 0; | |
4450 | int stack_offset = 0; | |
480d3dd2 | 4451 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 4452 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4453 | |
25ab4790 AC |
4454 | /* For shared libraries, "t9" needs to point at the function |
4455 | address. */ | |
4456 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
4457 | ||
4458 | /* Set the return address register to point to the entry point of | |
4459 | the program, where a breakpoint lies in wait. */ | |
4460 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
4461 | ||
46cac009 AC |
4462 | /* First ensure that the stack and structure return address (if any) |
4463 | are properly aligned. The stack has to be at least 64-bit | |
4464 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4465 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4466 | aligned, so we round to this widest known alignment. */ | |
4467 | ||
5b03f266 AC |
4468 | sp = align_down (sp, 16); |
4469 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4470 | |
4471 | /* Now make space on the stack for the args. */ | |
4472 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4473 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4474 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4475 | sp -= align_up (len, 16); |
46cac009 AC |
4476 | |
4477 | if (mips_debug) | |
6d82d43b | 4478 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4479 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
4480 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
4481 | |
4482 | /* Initialize the integer and float register pointers. */ | |
4483 | argreg = A0_REGNUM; | |
56cea623 | 4484 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4485 | |
4486 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4487 | if (struct_return) | |
4488 | { | |
4489 | if (mips_debug) | |
4490 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4491 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4492 | argreg, paddr_nz (struct_addr)); |
4493 | write_register (argreg++, struct_addr); | |
13326b4e | 4494 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
4495 | } |
4496 | ||
4497 | /* Now load as many as possible of the first arguments into | |
4498 | registers, and push the rest onto the stack. Loop thru args | |
4499 | from first to last. */ | |
4500 | for (argnum = 0; argnum < nargs; argnum++) | |
4501 | { | |
4502 | char *val; | |
46cac009 AC |
4503 | struct value *arg = args[argnum]; |
4504 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4505 | int len = TYPE_LENGTH (arg_type); | |
4506 | enum type_code typecode = TYPE_CODE (arg_type); | |
4507 | ||
4508 | if (mips_debug) | |
4509 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4510 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4511 | argnum + 1, len, (int) typecode); |
4512 | ||
4513 | val = (char *) VALUE_CONTENTS (arg); | |
4514 | ||
4515 | /* 32-bit ABIs always start floating point arguments in an | |
4516 | even-numbered floating point register. Round the FP register | |
4517 | up before the check to see if there are any FP registers | |
4518 | left. O32/O64 targets also pass the FP in the integer | |
4519 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4520 | if (mips_abi_regsize (gdbarch) < 8 |
4521 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
4522 | { |
4523 | if ((float_argreg & 1)) | |
4524 | float_argreg++; | |
4525 | } | |
4526 | ||
4527 | /* Floating point arguments passed in registers have to be | |
4528 | treated specially. On 32-bit architectures, doubles | |
4529 | are passed in register pairs; the even register gets | |
4530 | the low word, and the odd register gets the high word. | |
4531 | On O32/O64, the first two floating point arguments are | |
4532 | also copied to general registers, because MIPS16 functions | |
4533 | don't use float registers for arguments. This duplication of | |
4534 | arguments in general registers can't hurt non-MIPS16 functions | |
4535 | because those registers are normally skipped. */ | |
4536 | ||
4537 | if (fp_register_arg_p (typecode, arg_type) | |
4538 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4539 | { | |
ceae6e75 | 4540 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
4541 | { |
4542 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4543 | unsigned long regval; | |
4544 | ||
4545 | /* Write the low word of the double to the even register(s). */ | |
4546 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4547 | if (mips_debug) | |
4548 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4549 | float_argreg, phex (regval, 4)); | |
4550 | write_register (float_argreg++, regval); | |
4551 | if (mips_debug) | |
4552 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4553 | argreg, phex (regval, 4)); | |
4554 | write_register (argreg++, regval); | |
4555 | ||
4556 | /* Write the high word of the double to the odd register(s). */ | |
4557 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4558 | if (mips_debug) | |
4559 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4560 | float_argreg, phex (regval, 4)); | |
4561 | write_register (float_argreg++, regval); | |
4562 | ||
4563 | if (mips_debug) | |
4564 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4565 | argreg, phex (regval, 4)); | |
4566 | write_register (argreg++, regval); | |
4567 | } | |
4568 | else | |
4569 | { | |
4570 | /* This is a floating point value that fits entirely | |
4571 | in a single register. */ | |
4572 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4573 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4574 | LONGEST regval = extract_unsigned_integer (val, len); |
4575 | if (mips_debug) | |
4576 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4577 | float_argreg, phex (regval, len)); | |
4578 | write_register (float_argreg++, regval); | |
4579 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4580 | registers for each argument. The below is (my |
4581 | guess) to ensure that the corresponding integer | |
4582 | register has reserved the same space. */ | |
ebafbe83 MS |
4583 | if (mips_debug) |
4584 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4585 | argreg, phex (regval, len)); | |
4586 | write_register (argreg, regval); | |
ceae6e75 | 4587 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4588 | } |
4589 | /* Reserve space for the FP register. */ | |
13326b4e | 4590 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4591 | } |
4592 | else | |
4593 | { | |
4594 | /* Copy the argument to general registers or the stack in | |
4595 | register-sized pieces. Large arguments are split between | |
4596 | registers and stack. */ | |
4246e332 | 4597 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4598 | mips_abi_regsize() are treated specially: Irix cc passes |
4599 | them in registers where gcc sometimes puts them on the | |
4600 | stack. For maximum compatibility, we will put them in | |
4601 | both places. */ | |
13326b4e AC |
4602 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4603 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4604 | /* Structures should be aligned to eight bytes (even arg registers) |
4605 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4606 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4607 | && mips_type_needs_double_align (arg_type)) |
4608 | { | |
4609 | if ((argreg & 1)) | |
6d82d43b | 4610 | argreg++; |
ebafbe83 MS |
4611 | } |
4612 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4613 | register are only written to memory. */ |
ebafbe83 MS |
4614 | while (len > 0) |
4615 | { | |
4616 | /* Remember if the argument was written to the stack. */ | |
4617 | int stack_used_p = 0; | |
13326b4e AC |
4618 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4619 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4620 | |
4621 | if (mips_debug) | |
4622 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4623 | partial_len); | |
4624 | ||
4625 | /* Write this portion of the argument to the stack. */ | |
4626 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4627 | || odd_sized_struct | |
4628 | || fp_register_arg_p (typecode, arg_type)) | |
4629 | { | |
4630 | /* Should shorter than int integer values be | |
4631 | promoted to int before being stored? */ | |
4632 | int longword_offset = 0; | |
4633 | CORE_ADDR addr; | |
4634 | stack_used_p = 1; | |
4635 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4636 | { | |
13326b4e | 4637 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4638 | && (typecode == TYPE_CODE_INT |
4639 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4640 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4641 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4642 | } |
4643 | ||
4644 | if (mips_debug) | |
4645 | { | |
4646 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4647 | paddr_nz (stack_offset)); | |
4648 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4649 | paddr_nz (longword_offset)); | |
4650 | } | |
4651 | ||
4652 | addr = sp + stack_offset + longword_offset; | |
4653 | ||
4654 | if (mips_debug) | |
4655 | { | |
4656 | int i; | |
6d82d43b | 4657 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4658 | paddr_nz (addr)); |
4659 | for (i = 0; i < partial_len; i++) | |
4660 | { | |
6d82d43b | 4661 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4662 | val[i] & 0xff); |
4663 | } | |
4664 | } | |
4665 | write_memory (addr, val, partial_len); | |
4666 | } | |
4667 | ||
4668 | /* Note!!! This is NOT an else clause. Odd sized | |
4669 | structs may go thru BOTH paths. Floating point | |
4670 | arguments will not. */ | |
4671 | /* Write this portion of the argument to a general | |
6d82d43b | 4672 | purpose register. */ |
ebafbe83 MS |
4673 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4674 | && !fp_register_arg_p (typecode, arg_type)) | |
4675 | { | |
4676 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4677 | /* Value may need to be sign extended, because |
1b13c4f6 | 4678 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4679 | |
4680 | /* A non-floating-point argument being passed in a | |
4681 | general register. If a struct or union, and if | |
4682 | the remaining length is smaller than the register | |
4683 | size, we have to adjust the register value on | |
4684 | big endian targets. | |
4685 | ||
4686 | It does not seem to be necessary to do the | |
4687 | same for integral types. | |
4688 | ||
4689 | Also don't do this adjustment on O64 binaries. | |
4690 | ||
4691 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4692 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4693 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4694 | part of storing the argument in a register a |
4695 | register (the left shift isn't generated when | |
1b13c4f6 | 4696 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4697 | it is quite possible that this is GCC |
4698 | contradicting the LE/O32 ABI, GDB has not been | |
4699 | adjusted to accommodate this. Either someone | |
4700 | needs to demonstrate that the LE/O32 ABI | |
4701 | specifies such a left shift OR this new ABI gets | |
4702 | identified as such and GDB gets tweaked | |
4703 | accordingly. */ | |
4704 | ||
13326b4e | 4705 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4706 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4707 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4708 | && (typecode == TYPE_CODE_STRUCT || |
4709 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4710 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4711 | TARGET_CHAR_BIT); |
4712 | ||
4713 | if (mips_debug) | |
4714 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4715 | argreg, | |
6d82d43b | 4716 | phex (regval, |
13326b4e | 4717 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4718 | write_register (argreg, regval); |
4719 | argreg++; | |
4720 | ||
4721 | /* Prevent subsequent floating point arguments from | |
4722 | being passed in floating point registers. */ | |
4723 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4724 | } | |
4725 | ||
4726 | len -= partial_len; | |
4727 | val += partial_len; | |
4728 | ||
4729 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4730 | will copy the next parameter. |
ebafbe83 | 4731 | |
6d82d43b AC |
4732 | In older ABIs, the caller reserved space for |
4733 | registers that contained arguments. This was loosely | |
4734 | refered to as their "home". Consequently, space is | |
4735 | always allocated. */ | |
ebafbe83 | 4736 | |
480d3dd2 | 4737 | stack_offset += align_up (partial_len, |
13326b4e | 4738 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4739 | } |
4740 | } | |
4741 | if (mips_debug) | |
4742 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4743 | } | |
4744 | ||
f10683bb | 4745 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4746 | |
ebafbe83 MS |
4747 | /* Return adjusted stack pointer. */ |
4748 | return sp; | |
4749 | } | |
4750 | ||
f7ab6ec6 | 4751 | static void |
6d82d43b AC |
4752 | mips_o64_extract_return_value (struct type *valtype, |
4753 | char regbuf[], char *valbuf) | |
c906108c | 4754 | { |
6d82d43b AC |
4755 | struct return_value_word lo; |
4756 | struct return_value_word hi; | |
4757 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4758 | |
6d82d43b AC |
4759 | memcpy (valbuf + lo.buf_offset, |
4760 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4761 | lo.reg_offset, lo.len); | |
4762 | ||
4763 | if (hi.len > 0) | |
4764 | memcpy (valbuf + hi.buf_offset, | |
4765 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4766 | hi.reg_offset, hi.len); | |
4767 | } | |
4768 | ||
4769 | static void | |
4770 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4771 | { | |
4772 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4773 | struct return_value_word lo; | |
4774 | struct return_value_word hi; | |
4775 | return_value_location (valtype, &hi, &lo); | |
4776 | ||
4777 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4778 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4779 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4780 | raw_buffer, register_size (current_gdbarch, | |
4781 | lo.reg)); | |
4782 | ||
4783 | if (hi.len > 0) | |
4784 | { | |
4785 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4786 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4787 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4788 | raw_buffer, | |
4789 | register_size (current_gdbarch, | |
4790 | hi.reg)); | |
4791 | } | |
4792 | } | |
4793 | ||
dd824b04 DJ |
4794 | /* Floating point register management. |
4795 | ||
4796 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4797 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4798 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4799 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4800 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4801 | double precision floats into two 32-bit chunks and store them in | |
4802 | consecutive fp regs. To display 64-bit floats stored in this | |
4803 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4804 | Throw in user-configurable endianness and you have a real mess. | |
4805 | ||
4806 | The way this works is: | |
4807 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4808 | double-precision value will be split across two logical registers. | |
4809 | The lower-numbered logical register will hold the low-order bits, | |
4810 | regardless of the processor's endianness. | |
4811 | - If we are on a 64-bit processor, and we are looking for a | |
4812 | single-precision value, it will be in the low ordered bits | |
4813 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4814 | save slot in memory. | |
4815 | - If we are in 64-bit mode, everything is straightforward. | |
4816 | ||
4817 | Note that this code only deals with "live" registers at the top of the | |
4818 | stack. We will attempt to deal with saved registers later, when | |
4819 | the raw/cooked register interface is in place. (We need a general | |
4820 | interface that can deal with dynamic saved register sizes -- fp | |
4821 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4822 | and below). */ | |
4823 | ||
67b2c998 DJ |
4824 | static struct type * |
4825 | mips_float_register_type (void) | |
4826 | { | |
361d1df0 | 4827 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4828 | return builtin_type_ieee_single_big; |
4829 | else | |
4830 | return builtin_type_ieee_single_little; | |
4831 | } | |
4832 | ||
4833 | static struct type * | |
4834 | mips_double_register_type (void) | |
4835 | { | |
361d1df0 | 4836 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4837 | return builtin_type_ieee_double_big; |
4838 | else | |
4839 | return builtin_type_ieee_double_little; | |
4840 | } | |
4841 | ||
dd824b04 DJ |
4842 | /* Copy a 32-bit single-precision value from the current frame |
4843 | into rare_buffer. */ | |
4844 | ||
4845 | static void | |
e11c53d2 AC |
4846 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4847 | char *rare_buffer) | |
dd824b04 | 4848 | { |
719ec221 | 4849 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4850 | char *raw_buffer = alloca (raw_size); |
4851 | ||
e11c53d2 | 4852 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4853 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4854 | if (raw_size == 8) | |
4855 | { | |
4856 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4857 | 32 bits. */ |
dd824b04 DJ |
4858 | int offset; |
4859 | ||
4860 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4861 | offset = 4; | |
4862 | else | |
4863 | offset = 0; | |
4864 | ||
4865 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4866 | } | |
4867 | else | |
4868 | { | |
4869 | memcpy (rare_buffer, raw_buffer, 4); | |
4870 | } | |
4871 | } | |
4872 | ||
4873 | /* Copy a 64-bit double-precision value from the current frame into | |
4874 | rare_buffer. This may include getting half of it from the next | |
4875 | register. */ | |
4876 | ||
4877 | static void | |
e11c53d2 AC |
4878 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4879 | char *rare_buffer) | |
dd824b04 | 4880 | { |
719ec221 | 4881 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4882 | |
4883 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4884 | { | |
4885 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4886 | all 64 bits. */ |
e11c53d2 | 4887 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4888 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4889 | } | |
4890 | else | |
4891 | { | |
56cea623 | 4892 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4893 | internal_error (__FILE__, __LINE__, |
4894 | "mips_read_fp_register_double: bad access to " | |
4895 | "odd-numbered FP register"); | |
4896 | ||
4897 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4898 | each register. */ |
dd824b04 DJ |
4899 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4900 | { | |
e11c53d2 AC |
4901 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4902 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4903 | } |
361d1df0 | 4904 | else |
dd824b04 | 4905 | { |
e11c53d2 AC |
4906 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4907 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4908 | } |
4909 | } | |
4910 | } | |
4911 | ||
c906108c | 4912 | static void |
e11c53d2 AC |
4913 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4914 | int regnum) | |
c5aa993b | 4915 | { /* do values for FP (float) regs */ |
dd824b04 | 4916 | char *raw_buffer; |
3903d437 AC |
4917 | double doub, flt1; /* doubles extracted from raw hex data */ |
4918 | int inv1, inv2; | |
c5aa993b | 4919 | |
6d82d43b AC |
4920 | raw_buffer = |
4921 | (char *) alloca (2 * | |
4922 | register_size (current_gdbarch, | |
4923 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4924 | |
e11c53d2 AC |
4925 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4926 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4927 | ""); | |
f0ef6b29 | 4928 | |
719ec221 | 4929 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4930 | { |
f0ef6b29 KB |
4931 | /* 4-byte registers: Print hex and floating. Also print even |
4932 | numbered registers as doubles. */ | |
e11c53d2 | 4933 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4934 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4935 | |
6d82d43b AC |
4936 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4937 | file); | |
dd824b04 | 4938 | |
e11c53d2 | 4939 | fprintf_filtered (file, " flt: "); |
1adad886 | 4940 | if (inv1) |
e11c53d2 | 4941 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4942 | else |
e11c53d2 | 4943 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4944 | |
f0ef6b29 KB |
4945 | if (regnum % 2 == 0) |
4946 | { | |
e11c53d2 | 4947 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4948 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4949 | &inv2); |
1adad886 | 4950 | |
e11c53d2 | 4951 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4952 | if (inv2) |
e11c53d2 | 4953 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4954 | else |
e11c53d2 | 4955 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4956 | } |
c906108c SS |
4957 | } |
4958 | else | |
dd824b04 | 4959 | { |
f0ef6b29 | 4960 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4961 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4962 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4963 | |
e11c53d2 | 4964 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4965 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4966 | ||
361d1df0 | 4967 | |
6d82d43b AC |
4968 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4969 | file); | |
f0ef6b29 | 4970 | |
e11c53d2 | 4971 | fprintf_filtered (file, " flt: "); |
1adad886 | 4972 | if (inv1) |
e11c53d2 | 4973 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4974 | else |
e11c53d2 | 4975 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4976 | |
e11c53d2 | 4977 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4978 | if (inv2) |
e11c53d2 | 4979 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4980 | else |
e11c53d2 | 4981 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4982 | } |
4983 | } | |
4984 | ||
4985 | static void | |
e11c53d2 AC |
4986 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4987 | int regnum, int all) | |
f0ef6b29 | 4988 | { |
a4b8ebc8 | 4989 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4990 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4991 | int offset; |
1adad886 | 4992 | |
a4b8ebc8 | 4993 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4994 | { |
e11c53d2 | 4995 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4996 | return; |
4997 | } | |
4998 | ||
4999 | /* Get the data in raw format. */ | |
e11c53d2 | 5000 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 5001 | { |
e11c53d2 | 5002 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 5003 | return; |
c906108c | 5004 | } |
f0ef6b29 | 5005 | |
e11c53d2 | 5006 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
5007 | |
5008 | /* The problem with printing numeric register names (r26, etc.) is that | |
5009 | the user can't use them on input. Probably the best solution is to | |
5010 | fix it so that either the numeric or the funky (a2, etc.) names | |
5011 | are accepted on input. */ | |
5012 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 5013 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 5014 | else |
e11c53d2 | 5015 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
5016 | |
5017 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
5018 | offset = |
5019 | register_size (current_gdbarch, | |
5020 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
5021 | else |
5022 | offset = 0; | |
5023 | ||
6d82d43b AC |
5024 | print_scalar_formatted (raw_buffer + offset, |
5025 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
5026 | file); | |
c906108c SS |
5027 | } |
5028 | ||
f0ef6b29 KB |
5029 | /* Replacement for generic do_registers_info. |
5030 | Print regs in pretty columns. */ | |
5031 | ||
5032 | static int | |
e11c53d2 AC |
5033 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
5034 | int regnum) | |
f0ef6b29 | 5035 | { |
e11c53d2 AC |
5036 | fprintf_filtered (file, " "); |
5037 | mips_print_fp_register (file, frame, regnum); | |
5038 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
5039 | return regnum + 1; |
5040 | } | |
5041 | ||
5042 | ||
c906108c SS |
5043 | /* Print a row's worth of GP (int) registers, with name labels above */ |
5044 | ||
5045 | static int | |
e11c53d2 | 5046 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 5047 | int start_regnum) |
c906108c | 5048 | { |
a4b8ebc8 | 5049 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 5050 | /* do values for GP (int) regs */ |
d9d9c31f | 5051 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 5052 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 5053 | int col, byte; |
a4b8ebc8 | 5054 | int regnum; |
c906108c SS |
5055 | |
5056 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 5057 | fprintf_filtered (file, " "); |
a4b8ebc8 | 5058 | for (col = 0, regnum = start_regnum; |
6d82d43b | 5059 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
5060 | { |
5061 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 5062 | continue; /* unused register */ |
6d82d43b AC |
5063 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5064 | TYPE_CODE_FLT) | |
c5aa993b | 5065 | break; /* end the row: reached FP register */ |
6d82d43b | 5066 | fprintf_filtered (file, |
d5ac5a39 | 5067 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 5068 | REGISTER_NAME (regnum)); |
c906108c SS |
5069 | col++; |
5070 | } | |
a4b8ebc8 | 5071 | /* print the R0 to R31 names */ |
20e6603c AC |
5072 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
5073 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
5074 | else | |
5075 | fprintf_filtered (file, "\n "); | |
c906108c | 5076 | |
c906108c | 5077 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 5078 | for (col = 0, regnum = start_regnum; |
6d82d43b | 5079 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
5080 | { |
5081 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 5082 | continue; /* unused register */ |
6d82d43b AC |
5083 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5084 | TYPE_CODE_FLT) | |
c5aa993b | 5085 | break; /* end row: reached FP register */ |
c906108c | 5086 | /* OK: get the data in raw format. */ |
e11c53d2 | 5087 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
5088 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
5089 | /* pad small registers */ | |
4246e332 | 5090 | for (byte = 0; |
d5ac5a39 | 5091 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 5092 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
5093 | printf_filtered (" "); |
5094 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 5095 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
5096 | for (byte = |
5097 | register_size (current_gdbarch, | |
5098 | regnum) - register_size (current_gdbarch, regnum); | |
5099 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 5100 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 5101 | else |
c73e8f27 | 5102 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 5103 | byte >= 0; byte--) |
e11c53d2 AC |
5104 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
5105 | fprintf_filtered (file, " "); | |
c906108c SS |
5106 | col++; |
5107 | } | |
c5aa993b | 5108 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 5109 | fprintf_filtered (file, "\n"); |
c906108c SS |
5110 | |
5111 | return regnum; | |
5112 | } | |
5113 | ||
5114 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
5115 | ||
bf1f5b4c | 5116 | static void |
e11c53d2 AC |
5117 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
5118 | struct frame_info *frame, int regnum, int all) | |
c906108c | 5119 | { |
c5aa993b | 5120 | if (regnum != -1) /* do one specified register */ |
c906108c | 5121 | { |
a4b8ebc8 | 5122 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
5123 | if (*(REGISTER_NAME (regnum)) == '\0') |
5124 | error ("Not a valid register for the current processor type"); | |
5125 | ||
e11c53d2 AC |
5126 | mips_print_register (file, frame, regnum, 0); |
5127 | fprintf_filtered (file, "\n"); | |
c906108c | 5128 | } |
c5aa993b JM |
5129 | else |
5130 | /* do all (or most) registers */ | |
c906108c | 5131 | { |
a4b8ebc8 AC |
5132 | regnum = NUM_REGS; |
5133 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 5134 | { |
6d82d43b AC |
5135 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5136 | TYPE_CODE_FLT) | |
e11c53d2 AC |
5137 | { |
5138 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
5139 | regnum = print_fp_register_row (file, frame, regnum); | |
5140 | else | |
5141 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
5142 | } | |
c906108c | 5143 | else |
e11c53d2 | 5144 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
5145 | } |
5146 | } | |
5147 | } | |
5148 | ||
c906108c SS |
5149 | /* Is this a branch with a delay slot? */ |
5150 | ||
a14ed312 | 5151 | static int is_delayed (unsigned long); |
c906108c SS |
5152 | |
5153 | static int | |
acdb74a0 | 5154 | is_delayed (unsigned long insn) |
c906108c SS |
5155 | { |
5156 | int i; | |
5157 | for (i = 0; i < NUMOPCODES; ++i) | |
5158 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
5159 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
5160 | break; | |
5161 | return (i < NUMOPCODES | |
5162 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
5163 | | INSN_COND_BRANCH_DELAY | |
5164 | | INSN_COND_BRANCH_LIKELY))); | |
5165 | } | |
5166 | ||
5167 | int | |
acdb74a0 | 5168 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
5169 | { |
5170 | char buf[MIPS_INSTLEN]; | |
5171 | ||
5172 | /* There is no branch delay slot on MIPS16. */ | |
5173 | if (pc_is_mips16 (pc)) | |
5174 | return 0; | |
5175 | ||
5176 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
5177 | /* If error reading memory, guess that it is not a delayed branch. */ | |
5178 | return 0; | |
6d82d43b AC |
5179 | return is_delayed ((unsigned long) |
5180 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
5181 | } |
5182 | ||
c906108c SS |
5183 | /* Skip the PC past function prologue instructions (32-bit version). |
5184 | This is a helper function for mips_skip_prologue. */ | |
5185 | ||
5186 | static CORE_ADDR | |
f7b9e9fc | 5187 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 5188 | { |
c5aa993b JM |
5189 | t_inst inst; |
5190 | CORE_ADDR end_pc; | |
5191 | int seen_sp_adjust = 0; | |
5192 | int load_immediate_bytes = 0; | |
5193 | ||
74da7425 AC |
5194 | /* Find an upper bound on the prologue. */ |
5195 | end_pc = skip_prologue_using_sal (pc); | |
5196 | if (end_pc == 0) | |
6d82d43b | 5197 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 5198 | |
c5aa993b JM |
5199 | /* Skip the typical prologue instructions. These are the stack adjustment |
5200 | instruction and the instructions that save registers on the stack | |
5201 | or in the gcc frame. */ | |
74da7425 | 5202 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
5203 | { |
5204 | unsigned long high_word; | |
c906108c | 5205 | |
c5aa993b JM |
5206 | inst = mips_fetch_instruction (pc); |
5207 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 5208 | |
c5aa993b JM |
5209 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
5210 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
5211 | seen_sp_adjust = 1; | |
5212 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
5213 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
5214 | seen_sp_adjust = 1; | |
5215 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
5216 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
5217 | && (inst & 0x001F0000)) /* reg != $zero */ | |
5218 | continue; | |
5219 | ||
5220 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
5221 | continue; | |
5222 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
5223 | /* sx reg,n($s8) */ | |
5224 | continue; /* reg != $zero */ | |
5225 | ||
5226 | /* move $s8,$sp. With different versions of gas this will be either | |
5227 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
5228 | Accept any one of these. */ | |
5229 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
5230 | continue; | |
5231 | ||
5232 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
5233 | continue; | |
6d82d43b AC |
5234 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
5235 | continue; | |
5236 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
5237 | continue; | |
5238 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
5239 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
5240 | continue; | |
5241 | /* The following instructions load $at or $t0 with an immediate | |
5242 | value in preparation for a stack adjustment via | |
5243 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
5244 | a local variable, so we accept them only before a stack adjustment | |
5245 | instruction was seen. */ | |
5246 | else if (!seen_sp_adjust) | |
cb1d2653 | 5247 | { |
6d82d43b AC |
5248 | if (high_word == 0x3c01 || /* lui $at,n */ |
5249 | high_word == 0x3c08) /* lui $t0,n */ | |
5250 | { | |
5251 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
5252 | continue; | |
5253 | } | |
5254 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
5255 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
5256 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
5257 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
5258 | { | |
5259 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
5260 | continue; | |
5261 | } | |
5262 | else | |
5263 | break; | |
cb1d2653 | 5264 | } |
6d82d43b AC |
5265 | else |
5266 | break; | |
46cac009 | 5267 | } |
6d82d43b AC |
5268 | |
5269 | /* In a frameless function, we might have incorrectly | |
5270 | skipped some load immediate instructions. Undo the skipping | |
5271 | if the load immediate was not followed by a stack adjustment. */ | |
5272 | if (load_immediate_bytes && !seen_sp_adjust) | |
5273 | pc -= load_immediate_bytes; | |
5274 | return pc; | |
46cac009 AC |
5275 | } |
5276 | ||
6d82d43b AC |
5277 | /* Skip the PC past function prologue instructions (16-bit version). |
5278 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 5279 | |
6d82d43b AC |
5280 | static CORE_ADDR |
5281 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 5282 | { |
6d82d43b AC |
5283 | CORE_ADDR end_pc; |
5284 | int extend_bytes = 0; | |
5285 | int prev_extend_bytes; | |
5286 | ||
5287 | /* Table of instructions likely to be found in a function prologue. */ | |
5288 | static struct | |
5289 | { | |
5290 | unsigned short inst; | |
5291 | unsigned short mask; | |
5292 | } | |
5293 | table[] = | |
5294 | { | |
7a292a7a | 5295 | { |
6d82d43b AC |
5296 | 0x6300, 0xff00} |
5297 | , /* addiu $sp,offset */ | |
88658117 | 5298 | { |
6d82d43b AC |
5299 | 0xfb00, 0xff00} |
5300 | , /* daddiu $sp,offset */ | |
88658117 | 5301 | { |
6d82d43b AC |
5302 | 0xd000, 0xf800} |
5303 | , /* sw reg,n($sp) */ | |
5304 | { | |
5305 | 0xf900, 0xff00} | |
5306 | , /* sd reg,n($sp) */ | |
5307 | { | |
5308 | 0x6200, 0xff00} | |
5309 | , /* sw $ra,n($sp) */ | |
5310 | { | |
5311 | 0xfa00, 0xff00} | |
5312 | , /* sd $ra,n($sp) */ | |
5313 | { | |
5314 | 0x673d, 0xffff} | |
5315 | , /* move $s1,sp */ | |
5316 | { | |
5317 | 0xd980, 0xff80} | |
5318 | , /* sw $a0-$a3,n($s1) */ | |
5319 | { | |
5320 | 0x6704, 0xff1c} | |
5321 | , /* move reg,$a0-$a3 */ | |
5322 | { | |
5323 | 0xe809, 0xf81f} | |
5324 | , /* entry pseudo-op */ | |
5325 | { | |
5326 | 0x0100, 0xff00} | |
5327 | , /* addiu $s1,$sp,n */ | |
5328 | { | |
5329 | 0, 0} /* end of table marker */ | |
5330 | }; | |
5331 | ||
5332 | /* Find an upper bound on the prologue. */ | |
5333 | end_pc = skip_prologue_using_sal (pc); | |
5334 | if (end_pc == 0) | |
5335 | end_pc = pc + 100; /* Magic. */ | |
5336 | ||
5337 | /* Skip the typical prologue instructions. These are the stack adjustment | |
5338 | instruction and the instructions that save registers on the stack | |
5339 | or in the gcc frame. */ | |
5340 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
5341 | { | |
5342 | unsigned short inst; | |
5343 | int i; | |
5344 | ||
5345 | inst = mips_fetch_instruction (pc); | |
5346 | ||
5347 | /* Normally we ignore an extend instruction. However, if it is | |
5348 | not followed by a valid prologue instruction, we must adjust | |
5349 | the pc back over the extend so that it won't be considered | |
5350 | part of the prologue. */ | |
5351 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 5352 | { |
6d82d43b AC |
5353 | extend_bytes = MIPS16_INSTLEN; |
5354 | continue; | |
88658117 | 5355 | } |
6d82d43b AC |
5356 | prev_extend_bytes = extend_bytes; |
5357 | extend_bytes = 0; | |
5358 | ||
5359 | /* Check for other valid prologue instructions besides extend. */ | |
5360 | for (i = 0; table[i].mask != 0; i++) | |
5361 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
5362 | break; | |
5363 | if (table[i].mask != 0) /* it was in table? */ | |
5364 | continue; /* ignore it */ | |
5365 | else | |
5366 | /* non-prologue */ | |
88658117 | 5367 | { |
6d82d43b AC |
5368 | /* Return the current pc, adjusted backwards by 2 if |
5369 | the previous instruction was an extend. */ | |
5370 | return pc - prev_extend_bytes; | |
88658117 AC |
5371 | } |
5372 | } | |
6d82d43b AC |
5373 | return pc; |
5374 | } | |
5375 | ||
5376 | /* To skip prologues, I use this predicate. Returns either PC itself | |
5377 | if the code at PC does not look like a function prologue; otherwise | |
5378 | returns an address that (if we're lucky) follows the prologue. If | |
5379 | LENIENT, then we must skip everything which is involved in setting | |
5380 | up the frame (it's OK to skip more, just so long as we don't skip | |
5381 | anything which might clobber the registers which are being saved. | |
5382 | We must skip more in the case where part of the prologue is in the | |
5383 | delay slot of a non-prologue instruction). */ | |
5384 | ||
5385 | static CORE_ADDR | |
5386 | mips_skip_prologue (CORE_ADDR pc) | |
5387 | { | |
5388 | /* See if we can determine the end of the prologue via the symbol table. | |
5389 | If so, then return either PC, or the PC after the prologue, whichever | |
5390 | is greater. */ | |
5391 | ||
177f84a3 | 5392 | CORE_ADDR post_prologue_pc = after_prologue (pc); |
6d82d43b AC |
5393 | |
5394 | if (post_prologue_pc != 0) | |
5395 | return max (pc, post_prologue_pc); | |
5396 | ||
5397 | /* Can't determine prologue from the symbol table, need to examine | |
5398 | instructions. */ | |
5399 | ||
5400 | if (pc_is_mips16 (pc)) | |
5401 | return mips16_skip_prologue (pc); | |
5402 | else | |
5403 | return mips32_skip_prologue (pc); | |
88658117 AC |
5404 | } |
5405 | ||
a5ea2558 AC |
5406 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5407 | used for all MIPS-specific commands. */ | |
5408 | ||
a5ea2558 | 5409 | static void |
acdb74a0 | 5410 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5411 | { |
5412 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5413 | } | |
5414 | ||
a5ea2558 | 5415 | static void |
acdb74a0 | 5416 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5417 | { |
6d82d43b AC |
5418 | printf_unfiltered |
5419 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5420 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5421 | } | |
5422 | ||
c906108c SS |
5423 | /* Commands to show/set the MIPS FPU type. */ |
5424 | ||
c906108c | 5425 | static void |
acdb74a0 | 5426 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5427 | { |
c906108c SS |
5428 | char *fpu; |
5429 | switch (MIPS_FPU_TYPE) | |
5430 | { | |
5431 | case MIPS_FPU_SINGLE: | |
5432 | fpu = "single-precision"; | |
5433 | break; | |
5434 | case MIPS_FPU_DOUBLE: | |
5435 | fpu = "double-precision"; | |
5436 | break; | |
5437 | case MIPS_FPU_NONE: | |
5438 | fpu = "absent (none)"; | |
5439 | break; | |
93d56215 AC |
5440 | default: |
5441 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5442 | } |
5443 | if (mips_fpu_type_auto) | |
6d82d43b AC |
5444 | printf_unfiltered |
5445 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5446 | fpu); | |
c906108c | 5447 | else |
6d82d43b AC |
5448 | printf_unfiltered |
5449 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5450 | } |
5451 | ||
5452 | ||
c906108c | 5453 | static void |
acdb74a0 | 5454 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5455 | { |
6d82d43b AC |
5456 | printf_unfiltered |
5457 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5458 | show_mipsfpu_command (args, from_tty); |
5459 | } | |
5460 | ||
c906108c | 5461 | static void |
acdb74a0 | 5462 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5463 | { |
8d5838b5 AC |
5464 | struct gdbarch_info info; |
5465 | gdbarch_info_init (&info); | |
c906108c SS |
5466 | mips_fpu_type = MIPS_FPU_SINGLE; |
5467 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5468 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5469 | instead of relying on globals. Doing that would let generic code | |
5470 | handle the search for this specific architecture. */ | |
5471 | if (!gdbarch_update_p (info)) | |
5472 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5473 | } |
5474 | ||
c906108c | 5475 | static void |
acdb74a0 | 5476 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5477 | { |
8d5838b5 AC |
5478 | struct gdbarch_info info; |
5479 | gdbarch_info_init (&info); | |
c906108c SS |
5480 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5481 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5482 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5483 | instead of relying on globals. Doing that would let generic code | |
5484 | handle the search for this specific architecture. */ | |
5485 | if (!gdbarch_update_p (info)) | |
5486 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5487 | } |
5488 | ||
c906108c | 5489 | static void |
acdb74a0 | 5490 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5491 | { |
8d5838b5 AC |
5492 | struct gdbarch_info info; |
5493 | gdbarch_info_init (&info); | |
c906108c SS |
5494 | mips_fpu_type = MIPS_FPU_NONE; |
5495 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5496 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5497 | instead of relying on globals. Doing that would let generic code | |
5498 | handle the search for this specific architecture. */ | |
5499 | if (!gdbarch_update_p (info)) | |
5500 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5501 | } |
5502 | ||
c906108c | 5503 | static void |
acdb74a0 | 5504 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5505 | { |
5506 | mips_fpu_type_auto = 1; | |
5507 | } | |
5508 | ||
c906108c | 5509 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5510 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5511 | the relevant processor still exists (it dates back to '94) and | |
5512 | secondly this is not the way to do this. The processor type should | |
5513 | be set by forcing an architecture change. */ | |
c906108c | 5514 | |
691c0433 AC |
5515 | void |
5516 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5517 | { |
691c0433 | 5518 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5519 | CORE_ADDR prid; |
5520 | ||
5521 | prid = read_register (PRID_REGNUM); | |
5522 | ||
5523 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5524 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5525 | } |
5526 | ||
5527 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5528 | callable as an sfunc. */ | |
5529 | ||
5530 | static void | |
acdb74a0 AC |
5531 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5532 | struct cmd_list_element *c) | |
c906108c SS |
5533 | { |
5534 | reinit_frame_cache (); | |
5535 | } | |
5536 | ||
a89aa300 AC |
5537 | static int |
5538 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5539 | { |
e5ab0dce | 5540 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5541 | mips_extra_func_info_t proc_desc; |
5542 | ||
5543 | /* Search for the function containing this address. Set the low bit | |
5544 | of the address when searching, in case we were given an even address | |
5545 | that is the start of a 16-bit function. If we didn't do this, | |
5546 | the search would fail because the symbol table says the function | |
5547 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5548 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5549 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5550 | |
5551 | /* Make an attempt to determine if this is a 16-bit function. If | |
5552 | the procedure descriptor exists and the address therein is odd, | |
5553 | it's definitely a 16-bit function. Otherwise, we have to just | |
5554 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5555 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5556 | disassembler needs to be able to locally determine the ISA, and | |
5557 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5558 | work. */ | |
c906108c | 5559 | if (proc_desc) |
d31431ed AC |
5560 | { |
5561 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 5562 | info->mach = bfd_mach_mips16; |
d31431ed | 5563 | } |
c906108c | 5564 | else |
d31431ed AC |
5565 | { |
5566 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5567 | info->mach = bfd_mach_mips16; |
5568 | } | |
c906108c SS |
5569 | |
5570 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5571 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5572 | |
e5ab0dce | 5573 | /* Set the disassembler options. */ |
6d82d43b | 5574 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5575 | { |
5576 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5577 | register names from libopcodes. */ |
e5ab0dce AC |
5578 | if (tdep->mips_abi == MIPS_ABI_N32) |
5579 | info->disassembler_options = "gpr-names=n32"; | |
5580 | else | |
5581 | info->disassembler_options = "gpr-names=64"; | |
5582 | info->flavour = bfd_target_elf_flavour; | |
5583 | } | |
5584 | else | |
5585 | /* This string is not recognized explicitly by the disassembler, | |
5586 | but it tells the disassembler to not try to guess the ABI from | |
5587 | the bfd elf headers, such that, if the user overrides the ABI | |
5588 | of a program linked as NewABI, the disassembly will follow the | |
5589 | register naming conventions specified by the user. */ | |
5590 | info->disassembler_options = "gpr-names=32"; | |
5591 | ||
c906108c | 5592 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5593 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5594 | return print_insn_big_mips (memaddr, info); |
5595 | else | |
5596 | return print_insn_little_mips (memaddr, info); | |
5597 | } | |
5598 | ||
c906108c SS |
5599 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5600 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5601 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5602 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5603 | (if necessary) to point to the actual memory location where the | |
5604 | breakpoint should be inserted. */ | |
5605 | ||
f7ab6ec6 | 5606 | static const unsigned char * |
6d82d43b | 5607 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5608 | { |
d7449b42 | 5609 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5610 | { |
5611 | if (pc_is_mips16 (*pcptr)) | |
5612 | { | |
6d82d43b | 5613 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5614 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5615 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5616 | return mips16_big_breakpoint; |
5617 | } | |
5618 | else | |
5619 | { | |
aaab4dba AC |
5620 | /* The IDT board uses an unusual breakpoint value, and |
5621 | sometimes gets confused when it sees the usual MIPS | |
5622 | breakpoint instruction. */ | |
6d82d43b AC |
5623 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5624 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5625 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5626 | |
c5aa993b | 5627 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5628 | |
5629 | if (strcmp (target_shortname, "mips") == 0) | |
5630 | return idt_big_breakpoint; | |
5631 | else if (strcmp (target_shortname, "ddb") == 0 | |
5632 | || strcmp (target_shortname, "pmon") == 0 | |
5633 | || strcmp (target_shortname, "lsi") == 0) | |
5634 | return pmon_big_breakpoint; | |
5635 | else | |
5636 | return big_breakpoint; | |
5637 | } | |
5638 | } | |
5639 | else | |
5640 | { | |
5641 | if (pc_is_mips16 (*pcptr)) | |
5642 | { | |
6d82d43b | 5643 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5644 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5645 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5646 | return mips16_little_breakpoint; |
5647 | } | |
5648 | else | |
5649 | { | |
6d82d43b AC |
5650 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5651 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5652 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5653 | |
c5aa993b | 5654 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5655 | |
5656 | if (strcmp (target_shortname, "mips") == 0) | |
5657 | return idt_little_breakpoint; | |
5658 | else if (strcmp (target_shortname, "ddb") == 0 | |
5659 | || strcmp (target_shortname, "pmon") == 0 | |
5660 | || strcmp (target_shortname, "lsi") == 0) | |
5661 | return pmon_little_breakpoint; | |
5662 | else | |
5663 | return little_breakpoint; | |
5664 | } | |
5665 | } | |
5666 | } | |
5667 | ||
5668 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5669 | PC, which is either the callee or the caller. There are several | |
5670 | cases which must be handled: | |
5671 | ||
5672 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5673 | target PC is in $31 ($ra). |
c906108c | 5674 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5675 | and the target PC is in $2. |
c906108c | 5676 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5677 | before the jal instruction, this is effectively a call stub |
5678 | and the the target PC is in $2. Otherwise this is effectively | |
5679 | a return stub and the target PC is in $18. | |
c906108c SS |
5680 | |
5681 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5682 | gory details. | |
5683 | ||
5684 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5685 | */ |
c906108c | 5686 | |
757a7cc6 | 5687 | static CORE_ADDR |
acdb74a0 | 5688 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5689 | { |
5690 | char *name; | |
5691 | CORE_ADDR start_addr; | |
5692 | ||
5693 | /* Find the starting address and name of the function containing the PC. */ | |
5694 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5695 | return 0; | |
5696 | ||
5697 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5698 | target PC is in $31 ($ra). */ | |
5699 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5700 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5701 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5702 | |
5703 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5704 | { | |
5705 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5706 | and the target PC is in $2. */ | |
5707 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5708 | return read_signed_register (2); |
c906108c SS |
5709 | |
5710 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5711 | before the jal instruction, this is effectively a call stub |
5712 | and the the target PC is in $2. Otherwise this is effectively | |
5713 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5714 | else if (name[19] == 's' || name[19] == 'd') |
5715 | { | |
5716 | if (pc == start_addr) | |
5717 | { | |
5718 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5719 | stub. Such a stub for a function bar might have a name |
5720 | like __fn_stub_bar, and might look like this: | |
5721 | mfc1 $4,$f13 | |
5722 | mfc1 $5,$f12 | |
5723 | mfc1 $6,$f15 | |
5724 | mfc1 $7,$f14 | |
5725 | la $1,bar (becomes a lui/addiu pair) | |
5726 | jr $1 | |
5727 | So scan down to the lui/addi and extract the target | |
5728 | address from those two instructions. */ | |
c906108c | 5729 | |
6c997a34 | 5730 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5731 | t_inst inst; |
5732 | int i; | |
5733 | ||
5734 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5735 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5736 | 0) | |
c906108c SS |
5737 | return target_pc; |
5738 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5739 | && strcmp (name, "etext") != 0 | |
5740 | && strcmp (name, "_etext") != 0) | |
5741 | return target_pc; | |
5742 | ||
5743 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5744 | The limit on the search is arbitrarily set to 20 |
5745 | instructions. FIXME. */ | |
c906108c SS |
5746 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5747 | { | |
c5aa993b JM |
5748 | inst = mips_fetch_instruction (target_pc); |
5749 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5750 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5751 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5752 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5753 | } |
5754 | ||
5755 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5756 | return target_pc; | |
5757 | } | |
5758 | else | |
5759 | /* This is the 'return' part of a call stub. The return | |
5760 | address is in $r18. */ | |
6c997a34 | 5761 | return read_signed_register (18); |
c906108c SS |
5762 | } |
5763 | } | |
c5aa993b | 5764 | return 0; /* not a stub */ |
c906108c SS |
5765 | } |
5766 | ||
5767 | ||
5768 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5769 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5770 | ||
757a7cc6 | 5771 | static int |
acdb74a0 | 5772 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5773 | { |
5774 | CORE_ADDR start_addr; | |
5775 | ||
5776 | /* Find the starting address of the function containing the PC. If the | |
5777 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5778 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5779 | 0) | |
c906108c SS |
5780 | return 0; |
5781 | ||
5782 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5783 | { | |
5784 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5785 | if (name[19] >= '0' && name[19] <= '9') | |
5786 | return 1; | |
5787 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5788 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5789 | else if (name[19] == 's' || name[19] == 'd') |
5790 | return pc == start_addr; | |
5791 | } | |
5792 | ||
c5aa993b | 5793 | return 0; /* not a stub */ |
c906108c SS |
5794 | } |
5795 | ||
5796 | ||
5797 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5798 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5799 | ||
e41b17f0 | 5800 | static int |
acdb74a0 | 5801 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5802 | { |
5803 | CORE_ADDR start_addr; | |
5804 | ||
5805 | /* Find the starting address of the function containing the PC. */ | |
5806 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5807 | return 0; | |
5808 | ||
5809 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5810 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5811 | || strcmp (name, "__mips16_ret_df") == 0) | |
5812 | return 1; | |
5813 | ||
5814 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5815 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5816 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5817 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5818 | return 1; |
5819 | ||
c5aa993b | 5820 | return 0; /* not a stub */ |
c906108c SS |
5821 | } |
5822 | ||
5823 | ||
a53c66de AC |
5824 | /* Return non-zero if the PC is in a library helper function that |
5825 | should be ignored. This implements the | |
5826 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
5827 | |
5828 | int | |
acdb74a0 | 5829 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5830 | { |
5831 | char *name; | |
5832 | ||
5833 | /* Find the starting address and name of the function containing the PC. */ | |
5834 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5835 | return 0; | |
5836 | ||
5837 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5838 | that we want to ignore. */ | |
5839 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5840 | || strcmp (name, "__mips16_ret_df") == 0); | |
5841 | } | |
5842 | ||
5843 | ||
a4b8ebc8 AC |
5844 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5845 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5846 | |
5847 | static int | |
5848 | mips_stab_reg_to_regnum (int num) | |
5849 | { | |
a4b8ebc8 | 5850 | int regnum; |
2f38ef89 | 5851 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5852 | regnum = num; |
2f38ef89 | 5853 | else if (num >= 38 && num < 70) |
56cea623 | 5854 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5855 | else if (num == 70) |
56cea623 | 5856 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5857 | else if (num == 71) |
56cea623 | 5858 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5859 | else |
a4b8ebc8 AC |
5860 | /* This will hopefully (eventually) provoke a warning. Should |
5861 | we be calling complaint() here? */ | |
5862 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5863 | return NUM_REGS + regnum; | |
88c72b7d AC |
5864 | } |
5865 | ||
2f38ef89 | 5866 | |
a4b8ebc8 AC |
5867 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5868 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5869 | |
5870 | static int | |
2f38ef89 | 5871 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5872 | { |
a4b8ebc8 | 5873 | int regnum; |
2f38ef89 | 5874 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5875 | regnum = num; |
2f38ef89 | 5876 | else if (num >= 32 && num < 64) |
56cea623 | 5877 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5878 | else if (num == 64) |
56cea623 | 5879 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5880 | else if (num == 65) |
56cea623 | 5881 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5882 | else |
a4b8ebc8 AC |
5883 | /* This will hopefully (eventually) provoke a warning. Should we |
5884 | be calling complaint() here? */ | |
5885 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5886 | return NUM_REGS + regnum; | |
5887 | } | |
5888 | ||
5889 | static int | |
5890 | mips_register_sim_regno (int regnum) | |
5891 | { | |
5892 | /* Only makes sense to supply raw registers. */ | |
5893 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5894 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5895 | decide if it is valid. Should instead define a standard sim/gdb | |
5896 | register numbering scheme. */ | |
5897 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5898 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5899 | return regnum; | |
5900 | else | |
6d82d43b | 5901 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5902 | } |
5903 | ||
2f38ef89 | 5904 | |
fc0c74b1 AC |
5905 | /* Convert an integer into an address. By first converting the value |
5906 | into a pointer and then extracting it signed, the address is | |
5907 | guarenteed to be correctly sign extended. */ | |
5908 | ||
5909 | static CORE_ADDR | |
5910 | mips_integer_to_address (struct type *type, void *buf) | |
5911 | { | |
5912 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5913 | LONGEST val = unpack_long (type, buf); | |
5914 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5915 | return extract_signed_integer (tmp, | |
5916 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5917 | } | |
5918 | ||
caaa3122 DJ |
5919 | static void |
5920 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5921 | { | |
5922 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5923 | const char *name = bfd_get_section_name (abfd, sect); | |
5924 | ||
5925 | if (*abip != MIPS_ABI_UNKNOWN) | |
5926 | return; | |
5927 | ||
5928 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5929 | return; | |
5930 | ||
5931 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5932 | *abip = MIPS_ABI_O32; | |
5933 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5934 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5935 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5936 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5937 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5938 | *abip = MIPS_ABI_O64; | |
5939 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5940 | *abip = MIPS_ABI_EABI32; | |
5941 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5942 | *abip = MIPS_ABI_EABI64; | |
5943 | else | |
5944 | warning ("unsupported ABI %s.", name + 8); | |
5945 | } | |
5946 | ||
2e4ebe70 DJ |
5947 | static enum mips_abi |
5948 | global_mips_abi (void) | |
5949 | { | |
5950 | int i; | |
5951 | ||
5952 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5953 | if (mips_abi_strings[i] == mips_abi_string) | |
5954 | return (enum mips_abi) i; | |
5955 | ||
6d82d43b | 5956 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5957 | } |
5958 | ||
c2d11a7d | 5959 | static struct gdbarch * |
6d82d43b | 5960 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5961 | { |
c2d11a7d JM |
5962 | struct gdbarch *gdbarch; |
5963 | struct gdbarch_tdep *tdep; | |
5964 | int elf_flags; | |
2e4ebe70 | 5965 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5966 | int num_regs; |
8d5838b5 | 5967 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5968 | |
ec03c1ac AC |
5969 | /* First of all, extract the elf_flags, if available. */ |
5970 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5971 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5972 | else if (arches != NULL) |
5973 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5974 | else |
5975 | elf_flags = 0; | |
5976 | if (gdbarch_debug) | |
5977 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5978 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5979 | |
102182a9 | 5980 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5981 | switch ((elf_flags & EF_MIPS_ABI)) |
5982 | { | |
5983 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5984 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5985 | break; |
5986 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5987 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5988 | break; |
5989 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5990 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5991 | break; |
5992 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5993 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5994 | break; |
5995 | default: | |
acdb74a0 | 5996 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5997 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5998 | else |
ec03c1ac | 5999 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
6000 | break; |
6001 | } | |
acdb74a0 | 6002 | |
caaa3122 | 6003 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
6004 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
6005 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 6006 | |
dc305454 | 6007 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
6008 | MIPS architecture (if there is one). */ |
6009 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
6010 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 6011 | |
32a6503c | 6012 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 6013 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
6014 | && info.bfd_arch_info != NULL |
6015 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6016 | { | |
6017 | switch (info.bfd_arch_info->mach) | |
6018 | { | |
6019 | case bfd_mach_mips3900: | |
ec03c1ac | 6020 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
6021 | break; |
6022 | case bfd_mach_mips4100: | |
6023 | case bfd_mach_mips5000: | |
ec03c1ac | 6024 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 6025 | break; |
1d06468c EZ |
6026 | case bfd_mach_mips8000: |
6027 | case bfd_mach_mips10000: | |
32a6503c KB |
6028 | /* On Irix, ELF64 executables use the N64 ABI. The |
6029 | pseudo-sections which describe the ABI aren't present | |
6030 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
6031 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
6032 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 6033 | found_abi = MIPS_ABI_N64; |
28d169de | 6034 | else |
ec03c1ac | 6035 | found_abi = MIPS_ABI_N32; |
1d06468c | 6036 | break; |
bf64bfd6 AC |
6037 | } |
6038 | } | |
2e4ebe70 | 6039 | |
ec03c1ac AC |
6040 | if (gdbarch_debug) |
6041 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
6042 | found_abi); | |
6043 | ||
6044 | /* What has the user specified from the command line? */ | |
6045 | wanted_abi = global_mips_abi (); | |
6046 | if (gdbarch_debug) | |
6047 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
6048 | wanted_abi); | |
2e4ebe70 DJ |
6049 | |
6050 | /* Now that we have found what the ABI for this binary would be, | |
6051 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
6052 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
6053 | mips_abi = wanted_abi; | |
ec03c1ac AC |
6054 | else if (found_abi != MIPS_ABI_UNKNOWN) |
6055 | mips_abi = found_abi; | |
6056 | else | |
6057 | mips_abi = MIPS_ABI_O32; | |
6058 | if (gdbarch_debug) | |
6059 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
6060 | mips_abi); | |
2e4ebe70 | 6061 | |
ec03c1ac | 6062 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 6063 | if (gdbarch_debug) |
ec03c1ac AC |
6064 | fprintf_unfiltered (gdb_stdlog, |
6065 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
6066 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 6067 | |
8d5838b5 AC |
6068 | /* Determine the MIPS FPU type. */ |
6069 | if (!mips_fpu_type_auto) | |
6070 | fpu_type = mips_fpu_type; | |
6071 | else if (info.bfd_arch_info != NULL | |
6072 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6073 | switch (info.bfd_arch_info->mach) | |
6074 | { | |
6075 | case bfd_mach_mips3900: | |
6076 | case bfd_mach_mips4100: | |
6077 | case bfd_mach_mips4111: | |
a9d61c86 | 6078 | case bfd_mach_mips4120: |
8d5838b5 AC |
6079 | fpu_type = MIPS_FPU_NONE; |
6080 | break; | |
6081 | case bfd_mach_mips4650: | |
6082 | fpu_type = MIPS_FPU_SINGLE; | |
6083 | break; | |
6084 | default: | |
6085 | fpu_type = MIPS_FPU_DOUBLE; | |
6086 | break; | |
6087 | } | |
6088 | else if (arches != NULL) | |
6089 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
6090 | else | |
6091 | fpu_type = MIPS_FPU_DOUBLE; | |
6092 | if (gdbarch_debug) | |
6093 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6094 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 6095 | |
c2d11a7d JM |
6096 | /* try to find a pre-existing architecture */ |
6097 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
6098 | arches != NULL; | |
6099 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6100 | { | |
6101 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 6102 | using. */ |
9103eae0 | 6103 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 6104 | continue; |
9103eae0 | 6105 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 6106 | continue; |
719ec221 AC |
6107 | /* Need to be pedantic about which register virtual size is |
6108 | used. */ | |
6109 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
6110 | != mips64_transfers_32bit_regs_p) | |
6111 | continue; | |
8d5838b5 AC |
6112 | /* Be pedantic about which FPU is selected. */ |
6113 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
6114 | continue; | |
4be87837 | 6115 | return arches->gdbarch; |
c2d11a7d JM |
6116 | } |
6117 | ||
102182a9 | 6118 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
6119 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
6120 | gdbarch = gdbarch_alloc (&info, tdep); | |
6121 | tdep->elf_flags = elf_flags; | |
719ec221 | 6122 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
6123 | tdep->found_abi = found_abi; |
6124 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 6125 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 6126 | |
102182a9 | 6127 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6128 | set_gdbarch_short_bit (gdbarch, 16); |
6129 | set_gdbarch_int_bit (gdbarch, 32); | |
6130 | set_gdbarch_float_bit (gdbarch, 32); | |
6131 | set_gdbarch_double_bit (gdbarch, 64); | |
6132 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6133 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6134 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6135 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6136 | |
6d82d43b | 6137 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6138 | mips_elf_make_msymbol_special); |
6139 | ||
16e109ca | 6140 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 6141 | { |
16e109ca | 6142 | const char **reg_names; |
56cea623 AC |
6143 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
6144 | struct mips_regnum); | |
56cea623 AC |
6145 | if (info.osabi == GDB_OSABI_IRIX) |
6146 | { | |
6147 | regnum->fp0 = 32; | |
6148 | regnum->pc = 64; | |
6149 | regnum->cause = 65; | |
6150 | regnum->badvaddr = 66; | |
6151 | regnum->hi = 67; | |
6152 | regnum->lo = 68; | |
6153 | regnum->fp_control_status = 69; | |
6154 | regnum->fp_implementation_revision = 70; | |
6155 | num_regs = 71; | |
16e109ca | 6156 | reg_names = mips_irix_reg_names; |
56cea623 AC |
6157 | } |
6158 | else | |
6159 | { | |
6160 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6161 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6162 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6163 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6164 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6165 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6166 | regnum->fp_control_status = 70; | |
6167 | regnum->fp_implementation_revision = 71; | |
6168 | num_regs = 90; | |
16e109ca AC |
6169 | if (info.bfd_arch_info != NULL |
6170 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6171 | reg_names = mips_tx39_reg_names; | |
6172 | else | |
6173 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
6174 | } |
6175 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
6176 | replaced by read_pc? */ | |
f10683bb MH |
6177 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
6178 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
6179 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6180 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6181 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
6182 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6183 | tdep->mips_processor_reg_names = reg_names; | |
6184 | tdep->regnum = regnum; | |
56cea623 | 6185 | } |
fe29b929 | 6186 | |
0dadbba0 | 6187 | switch (mips_abi) |
c2d11a7d | 6188 | { |
0dadbba0 | 6189 | case MIPS_ABI_O32: |
25ab4790 | 6190 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6191 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
acdb74a0 | 6192 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 6193 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6194 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6195 | set_gdbarch_long_bit (gdbarch, 32); |
6196 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6197 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6198 | break; | |
0dadbba0 | 6199 | case MIPS_ABI_O64: |
25ab4790 | 6200 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
6201 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6202 | mips_o64_store_return_value); | |
6203 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6204 | mips_o64_extract_return_value); | |
acdb74a0 | 6205 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 6206 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6207 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6208 | set_gdbarch_long_bit (gdbarch, 32); |
6209 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6210 | set_gdbarch_long_long_bit (gdbarch, 64); | |
b5622e8d | 6211 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 6212 | break; |
0dadbba0 | 6213 | case MIPS_ABI_EABI32: |
25ab4790 | 6214 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
6215 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6216 | mips_eabi_store_return_value); | |
6217 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6218 | mips_eabi_extract_return_value); | |
acdb74a0 | 6219 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6220 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6221 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6222 | set_gdbarch_long_bit (gdbarch, 32); |
6223 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6224 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
6225 | set_gdbarch_deprecated_reg_struct_has_addr |
6226 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 6227 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 6228 | break; |
0dadbba0 | 6229 | case MIPS_ABI_EABI64: |
25ab4790 | 6230 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
6231 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6232 | mips_eabi_store_return_value); | |
6233 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6234 | mips_eabi_extract_return_value); | |
acdb74a0 | 6235 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6236 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6237 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6238 | set_gdbarch_long_bit (gdbarch, 64); |
6239 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6240 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
6241 | set_gdbarch_deprecated_reg_struct_has_addr |
6242 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 6243 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 6244 | break; |
0dadbba0 | 6245 | case MIPS_ABI_N32: |
25ab4790 | 6246 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6247 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
acdb74a0 | 6248 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6249 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6250 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6251 | set_gdbarch_long_bit (gdbarch, 32); |
6252 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6253 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
6254 | set_gdbarch_long_double_bit (gdbarch, 128); |
6255 | set_gdbarch_long_double_format (gdbarch, | |
6256 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
6257 | break; |
6258 | case MIPS_ABI_N64: | |
25ab4790 | 6259 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6260 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de | 6261 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6262 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6263 | tdep->default_mask_address_p = 0; |
6264 | set_gdbarch_long_bit (gdbarch, 64); | |
6265 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6266 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
6267 | set_gdbarch_long_double_bit (gdbarch, 128); |
6268 | set_gdbarch_long_double_format (gdbarch, | |
6269 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 6270 | break; |
c2d11a7d | 6271 | default: |
6d82d43b | 6272 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
6273 | } |
6274 | ||
a5ea2558 AC |
6275 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6276 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6277 | comment: | |
6278 | ||
6279 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6280 | flag in object files because to do so would make it impossible to | |
102182a9 | 6281 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6282 | unnecessarily restrictive. |
361d1df0 | 6283 | |
a5ea2558 AC |
6284 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6285 | but to set this flag before gcc is built with such multilibs will | |
6286 | break too many systems.'' | |
6287 | ||
6288 | But even more unhelpfully, the default linker output target for | |
6289 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6290 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6291 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6292 | this flag to detect 32-bit mode would do the wrong thing given |
6293 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6294 | as 32-bit programs by default. */ |
a5ea2558 | 6295 | |
6c997a34 | 6296 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6297 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 6298 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6299 | |
102182a9 MS |
6300 | /* Add/remove bits from an address. The MIPS needs be careful to |
6301 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6302 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6303 | ||
58dfe9ff AC |
6304 | /* Unwind the frame. */ |
6305 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 6306 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 6307 | |
102182a9 | 6308 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6309 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6310 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6311 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6312 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
6313 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6314 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
6315 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6316 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6317 | |
c2d11a7d JM |
6318 | /* MIPS version of CALL_DUMMY */ |
6319 | ||
9710e734 AC |
6320 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6321 | replaced by a command, and all targets will default to on stack | |
6322 | (regardless of the stack's execute status). */ | |
6323 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6324 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6325 | |
87783b8b AC |
6326 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6327 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6328 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6329 | ||
f7b9e9fc AC |
6330 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6331 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6332 | |
6333 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6334 | |
fc0c74b1 AC |
6335 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6336 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6337 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6338 | |
a4b8ebc8 | 6339 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6340 | |
e11c53d2 | 6341 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6342 | |
e5ab0dce AC |
6343 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6344 | ||
3a3bc038 AC |
6345 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6346 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6347 | need to all be folded into the target vector. Since they are | |
6348 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6349 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6350 | is sitting on? */ | |
6351 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6352 | ||
757a7cc6 MS |
6353 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
6354 | ||
6de918a6 DJ |
6355 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
6356 | to support MIPS16. This is a bad thing. Make sure not to do it | |
6357 | if we have an OS ABI that actually supports shared libraries, since | |
6358 | shared library support is more important. If we have an OS someday | |
6359 | that supports both shared libraries and MIPS16, we'll have to find | |
6360 | a better place for these. */ | |
6361 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
6362 | { | |
6363 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
6364 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
6365 | } | |
6366 | ||
6367 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
6368 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 6369 | |
5792a79b | 6370 | /* Unwind the frame. */ |
eec63939 | 6371 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
5792a79b | 6372 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
45c9dd44 AC |
6373 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
6374 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 6375 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
5792a79b | 6376 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); |
45c9dd44 AC |
6377 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6378 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6379 | |
4b9b3959 AC |
6380 | return gdbarch; |
6381 | } | |
6382 | ||
2e4ebe70 | 6383 | static void |
6d82d43b | 6384 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6385 | { |
6386 | struct gdbarch_info info; | |
6387 | ||
6388 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6389 | mips_gdbarch_init will take care of the rest. */ | |
6390 | gdbarch_info_init (&info); | |
6391 | gdbarch_update_p (info); | |
6392 | } | |
6393 | ||
ad188201 KB |
6394 | /* Print out which MIPS ABI is in use. */ |
6395 | ||
6396 | static void | |
6397 | show_mips_abi (char *ignore_args, int from_tty) | |
6398 | { | |
6399 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
6400 | printf_filtered |
6401 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
6402 | else |
6403 | { | |
6404 | enum mips_abi global_abi = global_mips_abi (); | |
6405 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6406 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6407 | ||
6408 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
6409 | printf_filtered |
6410 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6411 | actual_abi_str); | |
ad188201 | 6412 | else if (global_abi == actual_abi) |
6d82d43b AC |
6413 | printf_filtered |
6414 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6415 | actual_abi_str); | |
ad188201 KB |
6416 | else |
6417 | { | |
6418 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
6419 | printf_filtered |
6420 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6421 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
6422 | } |
6423 | } | |
6424 | } | |
6425 | ||
4b9b3959 AC |
6426 | static void |
6427 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6428 | { | |
6429 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6430 | if (tdep != NULL) | |
c2d11a7d | 6431 | { |
acdb74a0 AC |
6432 | int ef_mips_arch; |
6433 | int ef_mips_32bitmode; | |
6434 | /* determine the ISA */ | |
6435 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6436 | { | |
6437 | case E_MIPS_ARCH_1: | |
6438 | ef_mips_arch = 1; | |
6439 | break; | |
6440 | case E_MIPS_ARCH_2: | |
6441 | ef_mips_arch = 2; | |
6442 | break; | |
6443 | case E_MIPS_ARCH_3: | |
6444 | ef_mips_arch = 3; | |
6445 | break; | |
6446 | case E_MIPS_ARCH_4: | |
93d56215 | 6447 | ef_mips_arch = 4; |
acdb74a0 AC |
6448 | break; |
6449 | default: | |
93d56215 | 6450 | ef_mips_arch = 0; |
acdb74a0 AC |
6451 | break; |
6452 | } | |
6453 | /* determine the size of a pointer */ | |
6454 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6455 | fprintf_unfiltered (file, |
6456 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6457 | tdep->elf_flags); |
4b9b3959 | 6458 | fprintf_unfiltered (file, |
acdb74a0 AC |
6459 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6460 | ef_mips_32bitmode); | |
6461 | fprintf_unfiltered (file, | |
6462 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6463 | ef_mips_arch); | |
6464 | fprintf_unfiltered (file, | |
6465 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6466 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6467 | fprintf_unfiltered (file, |
6468 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6469 | mips_mask_address_p (tdep), |
4014092b | 6470 | tdep->default_mask_address_p); |
c2d11a7d | 6471 | } |
4b9b3959 AC |
6472 | fprintf_unfiltered (file, |
6473 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6474 | MIPS_DEFAULT_FPU_TYPE, | |
6475 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6476 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6477 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6478 | : "???")); | |
6d82d43b | 6479 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
6480 | fprintf_unfiltered (file, |
6481 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6482 | MIPS_FPU_TYPE, | |
6483 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6484 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6485 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6486 | : "???")); | |
4b9b3959 | 6487 | fprintf_unfiltered (file, |
480d3dd2 | 6488 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 6489 | mips_stack_argsize (current_gdbarch)); |
6d82d43b | 6490 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
6491 | fprintf_unfiltered (file, |
6492 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 6493 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
6494 | fprintf_unfiltered (file, |
6495 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6496 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6497 | fprintf_unfiltered (file, |
6498 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6499 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6500 | fprintf_unfiltered (file, | |
6501 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6502 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6503 | fprintf_unfiltered (file, |
6504 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6505 | FIRST_EMBED_REGNUM); | |
2475bac3 | 6506 | fprintf_unfiltered (file, |
a53c66de AC |
6507 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
6508 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6509 | fprintf_unfiltered (file, |
6510 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6511 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6512 | fprintf_unfiltered (file, | |
6513 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6514 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6515 | fprintf_unfiltered (file, |
6516 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6517 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6518 | #ifdef MACHINE_CPROC_FP_OFFSET |
6519 | fprintf_unfiltered (file, | |
6520 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6521 | MACHINE_CPROC_FP_OFFSET); | |
6522 | #endif | |
6523 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6524 | fprintf_unfiltered (file, | |
6525 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6526 | MACHINE_CPROC_PC_OFFSET); | |
6527 | #endif | |
6528 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6529 | fprintf_unfiltered (file, | |
6530 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6531 | MACHINE_CPROC_SP_OFFSET); | |
6532 | #endif | |
2475bac3 AC |
6533 | fprintf_unfiltered (file, |
6534 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6535 | MIPS16_INSTLEN); | |
6d82d43b | 6536 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
6537 | fprintf_unfiltered (file, |
6538 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6539 | fprintf_unfiltered (file, | |
6d82d43b | 6540 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 6541 | fprintf_unfiltered (file, |
acdb74a0 AC |
6542 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6543 | MIPS_LAST_ARG_REGNUM, | |
6544 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 6545 | fprintf_unfiltered (file, |
6d82d43b | 6546 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 6547 | fprintf_unfiltered (file, |
1b13c4f6 | 6548 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 6549 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 6550 | fprintf_unfiltered (file, |
6d82d43b | 6551 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
6552 | fprintf_unfiltered (file, |
6553 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6554 | fprintf_unfiltered (file, | |
6555 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6556 | fprintf_unfiltered (file, | |
6557 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
6558 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
6559 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6560 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6561 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6562 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6563 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6564 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6565 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6566 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6567 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
6568 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
6569 | #ifdef SAVED_BYTES |
6570 | fprintf_unfiltered (file, | |
6d82d43b | 6571 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
6572 | #endif |
6573 | #ifdef SAVED_FP | |
6d82d43b | 6574 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6575 | #endif |
6576 | #ifdef SAVED_PC | |
6d82d43b | 6577 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6578 | #endif |
6579 | fprintf_unfiltered (file, | |
6580 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6581 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6582 | fprintf_unfiltered (file, | |
6583 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
2475bac3 AC |
6584 | fprintf_unfiltered (file, |
6585 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6586 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6587 | fprintf_unfiltered (file, | |
6588 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6589 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6590 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6591 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6592 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6593 | fprintf_unfiltered (file, |
6594 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6595 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6596 | #ifdef STACK_END_ADDR | |
6597 | fprintf_unfiltered (file, | |
6598 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6599 | STACK_END_ADDR); | |
6600 | #endif | |
6601 | fprintf_unfiltered (file, | |
6602 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6603 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6604 | fprintf_unfiltered (file, | |
6605 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6606 | STEP_SKIPS_DELAY_P); | |
6607 | fprintf_unfiltered (file, | |
6608 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6609 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6610 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6611 | fprintf_unfiltered (file, |
6612 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6613 | fprintf_unfiltered (file, | |
6614 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6615 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6616 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6617 | fprintf_unfiltered (file, |
6618 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6619 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6620 | #ifdef TRACE_CLEAR |
6621 | fprintf_unfiltered (file, | |
6622 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6623 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6624 | #endif | |
6625 | #ifdef TRACE_FLAVOR | |
6626 | fprintf_unfiltered (file, | |
6d82d43b | 6627 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6628 | #endif |
6629 | #ifdef TRACE_FLAVOR_SIZE | |
6630 | fprintf_unfiltered (file, | |
6631 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6632 | TRACE_FLAVOR_SIZE); | |
6633 | #endif | |
6634 | #ifdef TRACE_SET | |
6635 | fprintf_unfiltered (file, | |
6636 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6637 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6638 | #endif |
2475bac3 AC |
6639 | #ifdef UNUSED_REGNUM |
6640 | fprintf_unfiltered (file, | |
6d82d43b | 6641 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6642 | #endif |
6d82d43b | 6643 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6644 | fprintf_unfiltered (file, |
6645 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6646 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6647 | fprintf_unfiltered (file, |
6d82d43b | 6648 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
2475bac3 | 6649 | fprintf_unfiltered (file, |
6d82d43b | 6650 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); |
c2d11a7d JM |
6651 | } |
6652 | ||
6d82d43b | 6653 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6654 | |
c906108c | 6655 | void |
acdb74a0 | 6656 | _initialize_mips_tdep (void) |
c906108c SS |
6657 | { |
6658 | static struct cmd_list_element *mipsfpulist = NULL; | |
6659 | struct cmd_list_element *c; | |
6660 | ||
6d82d43b | 6661 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6662 | if (MIPS_ABI_LAST + 1 |
6663 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6664 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6665 | ||
4b9b3959 | 6666 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6667 | |
8d5f9dcb DJ |
6668 | mips_pdr_data = register_objfile_data (); |
6669 | ||
a5ea2558 AC |
6670 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6671 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6672 | "Various MIPS specific commands.", | |
6673 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6674 | ||
6675 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6676 | "Various MIPS specific commands.", | |
6677 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6678 | ||
6679 | /* Allow the user to override the saved register size. */ | |
cb1a6d5f AC |
6680 | deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", |
6681 | class_obscure, | |
6682 | size_enums, | |
6683 | &mips_abi_regsize_string, "\ | |
a5ea2558 AC |
6684 | Set size of general purpose registers saved on the stack.\n\ |
6685 | This option can be set to one of:\n\ | |
6686 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6687 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6688 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6689 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6690 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6691 | |
d929b26f | 6692 | /* Allow the user to override the argument stack size. */ |
cb1a6d5f AC |
6693 | deprecated_add_show_from_set |
6694 | (add_set_enum_cmd ("stack-arg-size", | |
6695 | class_obscure, | |
6696 | size_enums, | |
6697 | &mips_stack_argsize_string, "\ | |
d929b26f AC |
6698 | Set the amount of stack space reserved for each argument.\n\ |
6699 | This option can be set to one of:\n\ | |
6700 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6701 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6702 | auto - Allow GDB to determine the correct setting from the current\n\ | |
cb1a6d5f AC |
6703 | target and executable (default)", &setmipscmdlist), |
6704 | &showmipscmdlist); | |
d929b26f | 6705 | |
2e4ebe70 DJ |
6706 | /* Allow the user to override the ABI. */ |
6707 | c = add_set_enum_cmd | |
6708 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6709 | "Set the ABI used by this program.\n" | |
6710 | "This option can be set to one of:\n" | |
6711 | " auto - the default ABI associated with the current binary\n" | |
6712 | " o32\n" | |
6d82d43b | 6713 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6714 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6715 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6716 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6717 | |
c906108c SS |
6718 | /* Let the user turn off floating point and set the fence post for |
6719 | heuristic_proc_start. */ | |
6720 | ||
6721 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6722 | "Set use of MIPS floating-point coprocessor.", | |
6723 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6724 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6725 | "Select single-precision MIPS floating-point coprocessor.", | |
6726 | &mipsfpulist); | |
6727 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6728 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6729 | &mipsfpulist); |
6730 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6731 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6732 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6733 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6734 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6735 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6736 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6737 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6738 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6739 | "Select MIPS floating-point coprocessor automatically.", | |
6740 | &mipsfpulist); | |
6741 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6742 | "Show current use of MIPS floating-point coprocessor target.", | |
6743 | &showlist); | |
6744 | ||
c906108c SS |
6745 | /* We really would like to have both "0" and "unlimited" work, but |
6746 | command.c doesn't deal with that. So make it a var_zinteger | |
6747 | because the user can always use "999999" or some such for unlimited. */ | |
6748 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6749 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6750 | Set the distance searched for the start of a function.\n\ |
6751 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6752 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6753 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6754 | /* We need to throw away the frame cache when we set this, since it |
6755 | might change our ability to get backtraces. */ | |
9f60d481 | 6756 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
cb1a6d5f | 6757 | deprecated_add_show_from_set (c, &showlist); |
c906108c SS |
6758 | |
6759 | /* Allow the user to control whether the upper bits of 64-bit | |
6760 | addresses should be zeroed. */ | |
e9e68a56 | 6761 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
6762 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
6763 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
6764 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
6765 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 6766 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 6767 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6768 | |
6769 | /* Allow the user to control the size of 32 bit registers within the | |
6770 | raw remote packet. */ | |
b3f42336 AC |
6771 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6772 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
6773 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
6774 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
6775 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6776 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6777 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
6778 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
6779 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
6780 | |
6781 | /* Debug this files internals. */ | |
cb1a6d5f AC |
6782 | deprecated_add_show_from_set |
6783 | (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6784 | &mips_debug, "Set mips debugging.\n\ | |
6785 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6786 | &showdebuglist); | |
c906108c | 6787 | } |