Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
24 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
25 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
29709017 DJ |
58 | #include "remote.h" |
59 | #include "target-descriptions.h" | |
2bd0c3d7 | 60 | #include "dwarf2-frame.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
7a292a7a | 97 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 98 | support single-precision floating-point operations. */ |
c906108c SS |
99 | |
100 | enum mips_fpu_type | |
6d82d43b AC |
101 | { |
102 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
103 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
104 | MIPS_FPU_NONE /* No floating point. */ | |
105 | }; | |
c906108c SS |
106 | |
107 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
108 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
109 | #endif | |
110 | static int mips_fpu_type_auto = 1; | |
111 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 112 | |
9ace0497 | 113 | static int mips_debug = 0; |
7a292a7a | 114 | |
29709017 DJ |
115 | /* Properties (for struct target_desc) describing the g/G packet |
116 | layout. */ | |
117 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
118 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
119 | ||
c2d11a7d JM |
120 | /* MIPS specific per-architecture information */ |
121 | struct gdbarch_tdep | |
6d82d43b AC |
122 | { |
123 | /* from the elf header */ | |
124 | int elf_flags; | |
125 | ||
126 | /* mips options */ | |
127 | enum mips_abi mips_abi; | |
128 | enum mips_abi found_abi; | |
129 | enum mips_fpu_type mips_fpu_type; | |
130 | int mips_last_arg_regnum; | |
131 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
132 | int default_mask_address_p; |
133 | /* Is the target using 64-bit raw integer registers but only | |
134 | storing a left-aligned 32-bit value in each? */ | |
135 | int mips64_transfers_32bit_regs_p; | |
136 | /* Indexes for various registers. IRIX and embedded have | |
137 | different values. This contains the "public" fields. Don't | |
138 | add any that do not need to be public. */ | |
139 | const struct mips_regnum *regnum; | |
140 | /* Register names table for the current register set. */ | |
141 | const char **mips_processor_reg_names; | |
29709017 DJ |
142 | |
143 | /* The size of register data available from the target, if known. | |
144 | This doesn't quite obsolete the manual | |
145 | mips64_transfers_32bit_regs_p, since that is documented to force | |
146 | left alignment even for big endian (very strange). */ | |
147 | int register_size_valid_p; | |
148 | int register_size; | |
6d82d43b | 149 | }; |
c2d11a7d | 150 | |
fed7ba43 JB |
151 | static int |
152 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 153 | const void *from) |
fed7ba43 JB |
154 | { |
155 | return 1; | |
156 | } | |
157 | ||
158 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
159 | They are implemented as a pair of 64bit doubles where the high | |
160 | part holds the result of the operation rounded to double, and | |
161 | the low double holds the difference between the exact result and | |
162 | the rounded result. So "high" + "low" contains the result with | |
163 | added precision. Unfortunately, the floatformat structure used | |
164 | by GDB is not powerful enough to describe this format. As a temporary | |
165 | measure, we define a 128bit floatformat that only uses the high part. | |
166 | We lose a bit of precision but that's probably the best we can do | |
167 | for now with the current infrastructure. */ | |
168 | ||
169 | static const struct floatformat floatformat_n32n64_long_double_big = | |
170 | { | |
171 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
172 | floatformat_intbit_no, | |
8da61cc4 | 173 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
174 | n32n64_floatformat_always_valid |
175 | }; | |
176 | ||
8da61cc4 DJ |
177 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
178 | { | |
179 | &floatformat_n32n64_long_double_big, | |
180 | &floatformat_n32n64_long_double_big | |
181 | }; | |
182 | ||
56cea623 AC |
183 | const struct mips_regnum * |
184 | mips_regnum (struct gdbarch *gdbarch) | |
185 | { | |
186 | return gdbarch_tdep (gdbarch)->regnum; | |
187 | } | |
188 | ||
189 | static int | |
190 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
191 | { | |
192 | return mips_regnum (gdbarch)->fp0 + 12; | |
193 | } | |
194 | ||
0dadbba0 | 195 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 196 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 197 | |
c2d11a7d | 198 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 199 | |
c2d11a7d | 200 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 201 | |
c2d11a7d | 202 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 203 | |
95404a3e AC |
204 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
205 | functions to test, set, or clear bit 0 of addresses. */ | |
206 | ||
207 | static CORE_ADDR | |
208 | is_mips16_addr (CORE_ADDR addr) | |
209 | { | |
210 | return ((addr) & 1); | |
211 | } | |
212 | ||
95404a3e AC |
213 | static CORE_ADDR |
214 | unmake_mips16_addr (CORE_ADDR addr) | |
215 | { | |
5b652102 | 216 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
217 | } |
218 | ||
22540ece AC |
219 | /* Return the contents of register REGNUM as a signed integer. */ |
220 | ||
221 | static LONGEST | |
222 | read_signed_register (int regnum) | |
223 | { | |
1d93fe1a AC |
224 | LONGEST val; |
225 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
226 | return val; | |
22540ece AC |
227 | } |
228 | ||
229 | static LONGEST | |
230 | read_signed_register_pid (int regnum, ptid_t ptid) | |
231 | { | |
232 | ptid_t save_ptid; | |
233 | LONGEST retval; | |
234 | ||
235 | if (ptid_equal (ptid, inferior_ptid)) | |
236 | return read_signed_register (regnum); | |
237 | ||
238 | save_ptid = inferior_ptid; | |
239 | ||
240 | inferior_ptid = ptid; | |
241 | ||
242 | retval = read_signed_register (regnum); | |
243 | ||
244 | inferior_ptid = save_ptid; | |
245 | ||
246 | return retval; | |
247 | } | |
248 | ||
d1973055 KB |
249 | /* Return the MIPS ABI associated with GDBARCH. */ |
250 | enum mips_abi | |
251 | mips_abi (struct gdbarch *gdbarch) | |
252 | { | |
253 | return gdbarch_tdep (gdbarch)->mips_abi; | |
254 | } | |
255 | ||
4246e332 | 256 | int |
1b13c4f6 | 257 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 258 | { |
29709017 DJ |
259 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
260 | ||
261 | /* If we know how big the registers are, use that size. */ | |
262 | if (tdep->register_size_valid_p) | |
263 | return tdep->register_size; | |
264 | ||
265 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
266 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
267 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
268 | } | |
269 | ||
480d3dd2 AC |
270 | /* Return the currently configured (or set) saved register size. */ |
271 | ||
e6bc2e8a | 272 | unsigned int |
13326b4e | 273 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 274 | { |
1a69e1e4 DJ |
275 | switch (mips_abi (gdbarch)) |
276 | { | |
277 | case MIPS_ABI_EABI32: | |
278 | case MIPS_ABI_O32: | |
279 | return 4; | |
280 | case MIPS_ABI_N32: | |
281 | case MIPS_ABI_N64: | |
282 | case MIPS_ABI_O64: | |
283 | case MIPS_ABI_EABI64: | |
284 | return 8; | |
285 | case MIPS_ABI_UNKNOWN: | |
286 | case MIPS_ABI_LAST: | |
287 | default: | |
288 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
289 | } | |
d929b26f AC |
290 | } |
291 | ||
71b8ef93 | 292 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 293 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 294 | "info" field is used for this purpose. |
5a89d8aa MS |
295 | |
296 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
297 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
298 | minimal symbol to mark it as a 16-bit function | |
299 | ||
f594e5e9 | 300 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 301 | |
5a89d8aa | 302 | static void |
6d82d43b AC |
303 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
304 | { | |
305 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
306 | { | |
307 | MSYMBOL_INFO (msym) = (char *) | |
308 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
309 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
310 | } | |
5a89d8aa MS |
311 | } |
312 | ||
71b8ef93 MS |
313 | static int |
314 | msymbol_is_special (struct minimal_symbol *msym) | |
315 | { | |
316 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
317 | } | |
318 | ||
88658117 AC |
319 | /* XFER a value from the big/little/left end of the register. |
320 | Depending on the size of the value it might occupy the entire | |
321 | register or just part of it. Make an allowance for this, aligning | |
322 | things accordingly. */ | |
323 | ||
324 | static void | |
325 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
326 | enum bfd_endian endian, gdb_byte *in, |
327 | const gdb_byte *out, int buf_offset) | |
88658117 | 328 | { |
88658117 | 329 | int reg_offset = 0; |
a4b8ebc8 | 330 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
331 | /* Need to transfer the left or right part of the register, based on |
332 | the targets byte order. */ | |
88658117 AC |
333 | switch (endian) |
334 | { | |
335 | case BFD_ENDIAN_BIG: | |
719ec221 | 336 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
337 | break; |
338 | case BFD_ENDIAN_LITTLE: | |
339 | reg_offset = 0; | |
340 | break; | |
6d82d43b | 341 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
342 | reg_offset = 0; |
343 | break; | |
344 | default: | |
e2e0b3e5 | 345 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
346 | } |
347 | if (mips_debug) | |
cb1d2653 AC |
348 | fprintf_unfiltered (gdb_stderr, |
349 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
350 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
351 | if (mips_debug && out != NULL) |
352 | { | |
353 | int i; | |
cb1d2653 | 354 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 355 | for (i = 0; i < length; i++) |
cb1d2653 | 356 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
357 | } |
358 | if (in != NULL) | |
6d82d43b AC |
359 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
360 | in + buf_offset); | |
88658117 | 361 | if (out != NULL) |
6d82d43b AC |
362 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
363 | out + buf_offset); | |
88658117 AC |
364 | if (mips_debug && in != NULL) |
365 | { | |
366 | int i; | |
cb1d2653 | 367 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 368 | for (i = 0; i < length; i++) |
cb1d2653 | 369 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
370 | } |
371 | if (mips_debug) | |
372 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
373 | } | |
374 | ||
dd824b04 DJ |
375 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
376 | compatiblity mode. A return value of 1 means that we have | |
377 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
378 | ||
379 | static int | |
380 | mips2_fp_compat (void) | |
381 | { | |
382 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
383 | meaningful. */ | |
6d82d43b AC |
384 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
385 | 4) | |
dd824b04 DJ |
386 | return 0; |
387 | ||
388 | #if 0 | |
389 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
390 | in all the places we deal with FP registers. PR gdb/413. */ | |
391 | /* Otherwise check the FR bit in the status register - it controls | |
392 | the FP compatiblity mode. If it is clear we are in compatibility | |
393 | mode. */ | |
24e05951 | 394 | if ((read_register (MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
395 | return 1; |
396 | #endif | |
361d1df0 | 397 | |
dd824b04 DJ |
398 | return 0; |
399 | } | |
400 | ||
7a292a7a | 401 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 402 | |
a14ed312 | 403 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 404 | |
a14ed312 | 405 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 406 | |
a14ed312 | 407 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 408 | |
67b2c998 DJ |
409 | static struct type *mips_float_register_type (void); |
410 | static struct type *mips_double_register_type (void); | |
411 | ||
acdb74a0 AC |
412 | /* The list of available "set mips " and "show mips " commands */ |
413 | ||
414 | static struct cmd_list_element *setmipscmdlist = NULL; | |
415 | static struct cmd_list_element *showmipscmdlist = NULL; | |
416 | ||
5e2e9765 KB |
417 | /* Integer registers 0 thru 31 are handled explicitly by |
418 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 419 | are listed in the following tables. */ |
691c0433 | 420 | |
6d82d43b AC |
421 | enum |
422 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
423 | |
424 | /* Generic MIPS. */ | |
425 | ||
426 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
427 | "sr", "lo", "hi", "bad", "cause", "pc", |
428 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
429 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
430 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
431 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
432 | "fsr", "fir", "" /*"fp" */ , "", | |
433 | "", "", "", "", "", "", "", "", | |
434 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
435 | }; |
436 | ||
437 | /* Names of IDT R3041 registers. */ | |
438 | ||
439 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
440 | "sr", "lo", "hi", "bad", "cause", "pc", |
441 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
442 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
443 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
444 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
445 | "fsr", "fir", "", /*"fp" */ "", | |
446 | "", "", "bus", "ccfg", "", "", "", "", | |
447 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
448 | }; |
449 | ||
450 | /* Names of tx39 registers. */ | |
451 | ||
452 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
453 | "sr", "lo", "hi", "bad", "cause", "pc", |
454 | "", "", "", "", "", "", "", "", | |
455 | "", "", "", "", "", "", "", "", | |
456 | "", "", "", "", "", "", "", "", | |
457 | "", "", "", "", "", "", "", "", | |
458 | "", "", "", "", | |
459 | "", "", "", "", "", "", "", "", | |
460 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
461 | }; |
462 | ||
463 | /* Names of IRIX registers. */ | |
464 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
465 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
466 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
467 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
468 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
469 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
470 | }; |
471 | ||
cce74817 | 472 | |
5e2e9765 | 473 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 474 | static const char * |
5e2e9765 | 475 | mips_register_name (int regno) |
cce74817 | 476 | { |
691c0433 | 477 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
478 | /* GPR names for all ABIs other than n32/n64. */ |
479 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
480 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
481 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
482 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
483 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
484 | }; |
485 | ||
486 | /* GPR names for n32 and n64 ABIs. */ | |
487 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
488 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
489 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
490 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
491 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
492 | }; |
493 | ||
494 | enum mips_abi abi = mips_abi (current_gdbarch); | |
495 | ||
a4b8ebc8 AC |
496 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
497 | don't make the raw register names visible. */ | |
498 | int rawnum = regno % NUM_REGS; | |
499 | if (regno < NUM_REGS) | |
500 | return ""; | |
501 | ||
5e2e9765 KB |
502 | /* The MIPS integer registers are always mapped from 0 to 31. The |
503 | names of the registers (which reflects the conventions regarding | |
504 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 505 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
506 | { |
507 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 508 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 509 | else |
a4b8ebc8 | 510 | return mips_gpr_names[rawnum]; |
5e2e9765 | 511 | } |
a4b8ebc8 | 512 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
513 | { |
514 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
515 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
516 | } | |
5e2e9765 KB |
517 | else |
518 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 519 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 520 | } |
5e2e9765 | 521 | |
a4b8ebc8 | 522 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 523 | |
a4b8ebc8 AC |
524 | static int |
525 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
526 | struct reggroup *reggroup) | |
527 | { | |
528 | int vector_p; | |
529 | int float_p; | |
530 | int raw_p; | |
531 | int rawnum = regnum % NUM_REGS; | |
532 | int pseudo = regnum / NUM_REGS; | |
533 | if (reggroup == all_reggroup) | |
534 | return pseudo; | |
535 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
536 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
537 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
538 | (gdbarch), as not all architectures are multi-arch. */ | |
539 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 540 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
541 | return 0; |
542 | if (reggroup == float_reggroup) | |
543 | return float_p && pseudo; | |
544 | if (reggroup == vector_reggroup) | |
545 | return vector_p && pseudo; | |
546 | if (reggroup == general_reggroup) | |
547 | return (!vector_p && !float_p) && pseudo; | |
548 | /* Save the pseudo registers. Need to make certain that any code | |
549 | extracting register values from a saved register cache also uses | |
550 | pseudo registers. */ | |
551 | if (reggroup == save_reggroup) | |
552 | return raw_p && pseudo; | |
553 | /* Restore the same pseudo register. */ | |
554 | if (reggroup == restore_reggroup) | |
555 | return raw_p && pseudo; | |
6d82d43b | 556 | return 0; |
a4b8ebc8 AC |
557 | } |
558 | ||
559 | /* Map the symbol table registers which live in the range [1 * | |
560 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 561 | registers. Take care of alignment and size problems. */ |
c5aa993b | 562 | |
a4b8ebc8 AC |
563 | static void |
564 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 565 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 566 | { |
47ebcfbe | 567 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 568 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 569 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 570 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
571 | else if (register_size (gdbarch, rawnum) > |
572 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
573 | { |
574 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
575 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
576 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
577 | else | |
578 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
579 | } | |
580 | else | |
e2e0b3e5 | 581 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
582 | } |
583 | ||
584 | static void | |
6d82d43b AC |
585 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
586 | struct regcache *regcache, int cookednum, | |
47a35522 | 587 | const gdb_byte *buf) |
a4b8ebc8 | 588 | { |
47ebcfbe | 589 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 590 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 591 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 592 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
593 | else if (register_size (gdbarch, rawnum) > |
594 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
595 | { |
596 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
597 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
598 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
599 | else | |
600 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
601 | } | |
602 | else | |
e2e0b3e5 | 603 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 604 | } |
c5aa993b | 605 | |
c906108c | 606 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 607 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
608 | |
609 | /* Heuristic_proc_start may hunt through the text section for a long | |
610 | time across a 2400 baud serial line. Allows the user to limit this | |
611 | search. */ | |
612 | ||
613 | static unsigned int heuristic_fence_post = 0; | |
614 | ||
46cd78fb | 615 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
616 | register N. NOTE: This defines the pseudo register type so need to |
617 | rebuild the architecture vector. */ | |
43e526b9 JM |
618 | |
619 | static int mips64_transfers_32bit_regs_p = 0; | |
620 | ||
719ec221 AC |
621 | static void |
622 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
623 | struct cmd_list_element *c) | |
43e526b9 | 624 | { |
719ec221 AC |
625 | struct gdbarch_info info; |
626 | gdbarch_info_init (&info); | |
627 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
628 | instead of relying on globals. Doing that would let generic code | |
629 | handle the search for this specific architecture. */ | |
630 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 631 | { |
719ec221 | 632 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 633 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 634 | } |
a4b8ebc8 AC |
635 | } |
636 | ||
47ebcfbe | 637 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 638 | |
ff2e87ac AC |
639 | static int |
640 | mips_convert_register_p (int regnum, struct type *type) | |
641 | { | |
642 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 643 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
644 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
645 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 646 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
647 | } |
648 | ||
42c466d7 | 649 | static void |
ff2e87ac | 650 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 651 | struct type *type, gdb_byte *to) |
102182a9 | 652 | { |
47a35522 MK |
653 | get_frame_register (frame, regnum + 0, to + 4); |
654 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
655 | } |
656 | ||
42c466d7 | 657 | static void |
ff2e87ac | 658 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 659 | struct type *type, const gdb_byte *from) |
102182a9 | 660 | { |
47a35522 MK |
661 | put_frame_register (frame, regnum + 0, from + 4); |
662 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
663 | } |
664 | ||
a4b8ebc8 AC |
665 | /* Return the GDB type object for the "standard" data type of data in |
666 | register REG. */ | |
78fde5f8 KB |
667 | |
668 | static struct type * | |
a4b8ebc8 AC |
669 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
670 | { | |
5ef80fb0 | 671 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
672 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
673 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 674 | { |
5ef80fb0 | 675 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 676 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
677 | if (mips_isa_regsize (gdbarch) == 4) |
678 | return builtin_type_ieee_single; | |
679 | else | |
680 | return builtin_type_ieee_double; | |
a6425924 | 681 | } |
d5ac5a39 AC |
682 | else if (regnum < NUM_REGS) |
683 | { | |
684 | /* The raw or ISA registers. These are all sized according to | |
685 | the ISA regsize. */ | |
686 | if (mips_isa_regsize (gdbarch) == 4) | |
687 | return builtin_type_int32; | |
688 | else | |
689 | return builtin_type_int64; | |
690 | } | |
78fde5f8 | 691 | else |
d5ac5a39 AC |
692 | { |
693 | /* The cooked or ABI registers. These are sized according to | |
694 | the ABI (with a few complications). */ | |
695 | if (regnum >= (NUM_REGS | |
696 | + mips_regnum (current_gdbarch)->fp_control_status) | |
607fc93c | 697 | && regnum <= NUM_REGS + MIPS_LAST_EMBED_REGNUM) |
d5ac5a39 AC |
698 | /* The pseudo/cooked view of the embedded registers is always |
699 | 32-bit. The raw view is handled below. */ | |
700 | return builtin_type_int32; | |
701 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
702 | /* The target, while possibly using a 64-bit register buffer, | |
703 | is only transfering 32-bits of each integer register. | |
704 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
705 | return builtin_type_int32; | |
706 | else if (mips_abi_regsize (gdbarch) == 4) | |
707 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
708 | 32- or 64-bit). */ | |
709 | return builtin_type_int32; | |
710 | else | |
711 | /* 64-bit ABI. */ | |
712 | return builtin_type_int64; | |
713 | } | |
78fde5f8 KB |
714 | } |
715 | ||
bcb0cc15 | 716 | |
c906108c | 717 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 718 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
719 | |
720 | static int | |
480d3dd2 | 721 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
722 | { |
723 | switch (mask_address_var) | |
724 | { | |
7f19b9a2 | 725 | case AUTO_BOOLEAN_TRUE: |
4014092b | 726 | return 1; |
7f19b9a2 | 727 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
728 | return 0; |
729 | break; | |
7f19b9a2 | 730 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 731 | return tdep->default_mask_address_p; |
4014092b | 732 | default: |
e2e0b3e5 | 733 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 734 | return -1; |
361d1df0 | 735 | } |
4014092b AC |
736 | } |
737 | ||
738 | static void | |
08546159 AC |
739 | show_mask_address (struct ui_file *file, int from_tty, |
740 | struct cmd_list_element *c, const char *value) | |
4014092b | 741 | { |
480d3dd2 | 742 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
743 | |
744 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
745 | switch (mask_address_var) |
746 | { | |
7f19b9a2 | 747 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
748 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
749 | break; | |
7f19b9a2 | 750 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
751 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
752 | break; | |
7f19b9a2 | 753 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
754 | printf_filtered |
755 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
756 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
757 | break; |
758 | default: | |
e2e0b3e5 | 759 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 760 | break; |
361d1df0 | 761 | } |
4014092b | 762 | } |
c906108c | 763 | |
c906108c SS |
764 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
765 | ||
0fe7e7c8 AC |
766 | int |
767 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
768 | { |
769 | struct minimal_symbol *sym; | |
770 | ||
771 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 772 | if (is_mips16_addr (memaddr)) |
c906108c SS |
773 | return 1; |
774 | ||
775 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
776 | the high bit of the info field. Use this to decide if the function is | |
777 | MIPS16 or normal MIPS. */ | |
778 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
779 | if (sym) | |
71b8ef93 | 780 | return msymbol_is_special (sym); |
c906108c SS |
781 | else |
782 | return 0; | |
783 | } | |
784 | ||
b2fa5097 | 785 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
786 | all registers should be sign extended for simplicity? */ |
787 | ||
788 | static CORE_ADDR | |
39f77062 | 789 | mips_read_pc (ptid_t ptid) |
6c997a34 | 790 | { |
b6cb9035 AC |
791 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
792 | } | |
793 | ||
58dfe9ff AC |
794 | static CORE_ADDR |
795 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
796 | { | |
edfae063 AC |
797 | return frame_unwind_register_signed (next_frame, |
798 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
799 | } | |
800 | ||
30244cd8 UW |
801 | static CORE_ADDR |
802 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
803 | { | |
804 | return frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
805 | } | |
806 | ||
edfae063 AC |
807 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
808 | dummy frame. The frame ID's base needs to match the TOS value | |
809 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
810 | breakpoint. */ | |
811 | ||
812 | static struct frame_id | |
813 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
814 | { | |
f10683bb | 815 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 816 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
817 | } |
818 | ||
b6cb9035 AC |
819 | static void |
820 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
821 | { | |
822 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 823 | } |
c906108c | 824 | |
c906108c SS |
825 | /* Fetch and return instruction from the specified location. If the PC |
826 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
827 | ||
d37cca3d | 828 | static ULONGEST |
acdb74a0 | 829 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 830 | { |
47a35522 | 831 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
832 | int instlen; |
833 | int status; | |
834 | ||
0fe7e7c8 | 835 | if (mips_pc_is_mips16 (addr)) |
c906108c | 836 | { |
95ac2dcf | 837 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 838 | addr = unmake_mips16_addr (addr); |
c906108c SS |
839 | } |
840 | else | |
95ac2dcf | 841 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 842 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
843 | if (status) |
844 | memory_error (status, addr); | |
845 | return extract_unsigned_integer (buf, instlen); | |
846 | } | |
847 | ||
c906108c | 848 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
849 | #define mips32_op(x) (x >> 26) |
850 | #define itype_op(x) (x >> 26) | |
851 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 852 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 853 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 854 | |
e135b889 DJ |
855 | #define jtype_op(x) (x >> 26) |
856 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 857 | |
e135b889 DJ |
858 | #define rtype_op(x) (x >> 26) |
859 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
860 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
861 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
862 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
863 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 864 | |
06987e64 MK |
865 | static LONGEST |
866 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 867 | { |
06987e64 | 868 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
869 | } |
870 | ||
f49e4e6d MS |
871 | /* Determine where to set a single step breakpoint while considering |
872 | branch prediction. */ | |
5a89d8aa | 873 | static CORE_ADDR |
c5aa993b JM |
874 | mips32_next_pc (CORE_ADDR pc) |
875 | { | |
876 | unsigned long inst; | |
877 | int op; | |
878 | inst = mips_fetch_instruction (pc); | |
e135b889 | 879 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 880 | { |
e135b889 | 881 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 882 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 883 | { |
e135b889 | 884 | op = (itype_op (inst) & 0x03); |
c906108c SS |
885 | switch (op) |
886 | { | |
e135b889 DJ |
887 | case 0: /* BEQL */ |
888 | goto equal_branch; | |
889 | case 1: /* BNEL */ | |
890 | goto neq_branch; | |
891 | case 2: /* BLEZL */ | |
892 | goto less_branch; | |
893 | case 3: /* BGTZ */ | |
894 | goto greater_branch; | |
c5aa993b JM |
895 | default: |
896 | pc += 4; | |
c906108c SS |
897 | } |
898 | } | |
e135b889 | 899 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 900 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
901 | { |
902 | int tf = itype_rt (inst) & 0x01; | |
903 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
904 | int fcrcs = |
905 | read_signed_register (mips_regnum (current_gdbarch)-> | |
906 | fp_control_status); | |
e135b889 DJ |
907 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
908 | ||
909 | if (((cond >> cnum) & 0x01) == tf) | |
910 | pc += mips32_relative_offset (inst) + 4; | |
911 | else | |
912 | pc += 8; | |
913 | } | |
c5aa993b JM |
914 | else |
915 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
916 | } |
917 | else | |
c5aa993b JM |
918 | { /* This gets way messy */ |
919 | ||
c906108c | 920 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 921 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 922 | { |
c5aa993b JM |
923 | case 0: /* SPECIAL */ |
924 | op = rtype_funct (inst); | |
925 | switch (op) | |
926 | { | |
927 | case 8: /* JR */ | |
928 | case 9: /* JALR */ | |
6c997a34 AC |
929 | /* Set PC to that address */ |
930 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
931 | break; |
932 | default: | |
933 | pc += 4; | |
934 | } | |
935 | ||
6d82d43b | 936 | break; /* end SPECIAL */ |
c5aa993b | 937 | case 1: /* REGIMM */ |
c906108c | 938 | { |
e135b889 DJ |
939 | op = itype_rt (inst); /* branch condition */ |
940 | switch (op) | |
c906108c | 941 | { |
c5aa993b | 942 | case 0: /* BLTZ */ |
e135b889 DJ |
943 | case 2: /* BLTZL */ |
944 | case 16: /* BLTZAL */ | |
c5aa993b | 945 | case 18: /* BLTZALL */ |
c906108c | 946 | less_branch: |
6c997a34 | 947 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
948 | pc += mips32_relative_offset (inst) + 4; |
949 | else | |
950 | pc += 8; /* after the delay slot */ | |
951 | break; | |
e135b889 | 952 | case 1: /* BGEZ */ |
c5aa993b JM |
953 | case 3: /* BGEZL */ |
954 | case 17: /* BGEZAL */ | |
955 | case 19: /* BGEZALL */ | |
6c997a34 | 956 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
957 | pc += mips32_relative_offset (inst) + 4; |
958 | else | |
959 | pc += 8; /* after the delay slot */ | |
960 | break; | |
e135b889 | 961 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
962 | default: |
963 | pc += 4; | |
c906108c SS |
964 | } |
965 | } | |
6d82d43b | 966 | break; /* end REGIMM */ |
c5aa993b JM |
967 | case 2: /* J */ |
968 | case 3: /* JAL */ | |
969 | { | |
970 | unsigned long reg; | |
971 | reg = jtype_target (inst) << 2; | |
e135b889 | 972 | /* Upper four bits get never changed... */ |
5b652102 | 973 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 974 | } |
c5aa993b JM |
975 | break; |
976 | /* FIXME case JALX : */ | |
977 | { | |
978 | unsigned long reg; | |
979 | reg = jtype_target (inst) << 2; | |
5b652102 | 980 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
981 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
982 | } | |
c5aa993b | 983 | break; /* The new PC will be alternate mode */ |
e135b889 | 984 | case 4: /* BEQ, BEQL */ |
c5aa993b | 985 | equal_branch: |
6c997a34 AC |
986 | if (read_signed_register (itype_rs (inst)) == |
987 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
988 | pc += mips32_relative_offset (inst) + 4; |
989 | else | |
990 | pc += 8; | |
991 | break; | |
e135b889 | 992 | case 5: /* BNE, BNEL */ |
c5aa993b | 993 | neq_branch: |
6c997a34 | 994 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 995 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
996 | pc += mips32_relative_offset (inst) + 4; |
997 | else | |
998 | pc += 8; | |
999 | break; | |
e135b889 | 1000 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1001 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1002 | pc += mips32_relative_offset (inst) + 4; |
1003 | else | |
1004 | pc += 8; | |
1005 | break; | |
1006 | case 7: | |
e135b889 DJ |
1007 | default: |
1008 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1009 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1010 | pc += mips32_relative_offset (inst) + 4; |
1011 | else | |
1012 | pc += 8; | |
1013 | break; | |
c5aa993b JM |
1014 | } /* switch */ |
1015 | } /* else */ | |
1016 | return pc; | |
1017 | } /* mips32_next_pc */ | |
c906108c SS |
1018 | |
1019 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1020 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1021 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1022 | We dont want to set a single step instruction on the extend instruction | |
1023 | either. | |
c5aa993b | 1024 | */ |
c906108c SS |
1025 | |
1026 | /* Lots of mips16 instruction formats */ | |
1027 | /* Predicting jumps requires itype,ritype,i8type | |
1028 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1029 | */ |
c906108c SS |
1030 | enum mips16_inst_fmts |
1031 | { | |
c5aa993b JM |
1032 | itype, /* 0 immediate 5,10 */ |
1033 | ritype, /* 1 5,3,8 */ | |
1034 | rrtype, /* 2 5,3,3,5 */ | |
1035 | rritype, /* 3 5,3,3,5 */ | |
1036 | rrrtype, /* 4 5,3,3,3,2 */ | |
1037 | rriatype, /* 5 5,3,3,1,4 */ | |
1038 | shifttype, /* 6 5,3,3,3,2 */ | |
1039 | i8type, /* 7 5,3,8 */ | |
1040 | i8movtype, /* 8 5,3,3,5 */ | |
1041 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1042 | i64type, /* 10 5,3,8 */ | |
1043 | ri64type, /* 11 5,3,3,5 */ | |
1044 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1045 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1046 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1047 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1048 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1049 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1050 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1051 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1052 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1053 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1054 | }; | |
12f02c2a AC |
1055 | /* I am heaping all the fields of the formats into one structure and |
1056 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1057 | struct upk_mips16 |
6d82d43b AC |
1058 | { |
1059 | CORE_ADDR offset; | |
1060 | unsigned int regx; /* Function in i8 type */ | |
1061 | unsigned int regy; | |
1062 | }; | |
c906108c SS |
1063 | |
1064 | ||
12f02c2a AC |
1065 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1066 | for the bits which make up the immediatate extension. */ | |
c906108c | 1067 | |
12f02c2a AC |
1068 | static CORE_ADDR |
1069 | extended_offset (unsigned int extension) | |
c906108c | 1070 | { |
12f02c2a | 1071 | CORE_ADDR value; |
c5aa993b JM |
1072 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1073 | value = value << 6; | |
1074 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1075 | value = value << 5; | |
1076 | value |= extension & 0x01f; /* extract 4:0 */ | |
1077 | return value; | |
c906108c SS |
1078 | } |
1079 | ||
1080 | /* Only call this function if you know that this is an extendable | |
1081 | instruction, It wont malfunction, but why make excess remote memory references? | |
1082 | If the immediate operands get sign extended or somthing, do it after | |
1083 | the extension is performed. | |
c5aa993b | 1084 | */ |
c906108c SS |
1085 | /* FIXME: Every one of these cases needs to worry about sign extension |
1086 | when the offset is to be used in relative addressing */ | |
1087 | ||
1088 | ||
12f02c2a | 1089 | static unsigned int |
c5aa993b | 1090 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1091 | { |
47a35522 | 1092 | gdb_byte buf[8]; |
c5aa993b JM |
1093 | pc &= 0xfffffffe; /* clear the low order bit */ |
1094 | target_read_memory (pc, buf, 2); | |
1095 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1096 | } |
1097 | ||
1098 | static void | |
c5aa993b | 1099 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1100 | unsigned int extension, |
1101 | unsigned int inst, | |
6d82d43b | 1102 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1103 | { |
12f02c2a AC |
1104 | CORE_ADDR offset; |
1105 | int regx; | |
1106 | int regy; | |
1107 | switch (insn_format) | |
c906108c | 1108 | { |
c5aa993b | 1109 | case itype: |
c906108c | 1110 | { |
12f02c2a AC |
1111 | CORE_ADDR value; |
1112 | if (extension) | |
c5aa993b JM |
1113 | { |
1114 | value = extended_offset (extension); | |
1115 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1116 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1117 | } |
1118 | else | |
c5aa993b | 1119 | { |
12f02c2a | 1120 | value = inst & 0x7ff; |
c5aa993b | 1121 | /* FIXME : Consider sign extension */ |
c906108c | 1122 | } |
12f02c2a AC |
1123 | offset = value; |
1124 | regx = -1; | |
1125 | regy = -1; | |
c906108c | 1126 | } |
c5aa993b JM |
1127 | break; |
1128 | case ritype: | |
1129 | case i8type: | |
1130 | { /* A register identifier and an offset */ | |
c906108c SS |
1131 | /* Most of the fields are the same as I type but the |
1132 | immediate value is of a different length */ | |
12f02c2a AC |
1133 | CORE_ADDR value; |
1134 | if (extension) | |
c906108c | 1135 | { |
c5aa993b JM |
1136 | value = extended_offset (extension); |
1137 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1138 | value |= inst & 0xff; /* eleven bits from instruction */ |
1139 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1140 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1141 | { | |
1142 | value &= ~0x3fff; /* remove the sign bit */ | |
1143 | value = -value; | |
c906108c SS |
1144 | } |
1145 | } | |
c5aa993b JM |
1146 | else |
1147 | { | |
12f02c2a AC |
1148 | value = inst & 0xff; /* 8 bits */ |
1149 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1150 | /* FIXME: Do sign extension , this format needs it */ |
1151 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1152 | { | |
1153 | value &= 0xef; /* remove the sign bit */ | |
1154 | value = -value; | |
1155 | } | |
c5aa993b | 1156 | } |
12f02c2a AC |
1157 | offset = value; |
1158 | regy = -1; | |
c5aa993b | 1159 | break; |
c906108c | 1160 | } |
c5aa993b | 1161 | case jalxtype: |
c906108c | 1162 | { |
c5aa993b | 1163 | unsigned long value; |
12f02c2a AC |
1164 | unsigned int nexthalf; |
1165 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1166 | value = value << 16; |
1167 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1168 | value |= nexthalf; | |
12f02c2a AC |
1169 | offset = value; |
1170 | regx = -1; | |
1171 | regy = -1; | |
c5aa993b | 1172 | break; |
c906108c SS |
1173 | } |
1174 | default: | |
e2e0b3e5 | 1175 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1176 | } |
12f02c2a AC |
1177 | upk->offset = offset; |
1178 | upk->regx = regx; | |
1179 | upk->regy = regy; | |
c906108c SS |
1180 | } |
1181 | ||
1182 | ||
c5aa993b JM |
1183 | static CORE_ADDR |
1184 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1185 | { |
5b652102 | 1186 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1187 | } |
1188 | ||
12f02c2a AC |
1189 | static CORE_ADDR |
1190 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1191 | unsigned int extension, unsigned int insn) |
c906108c | 1192 | { |
12f02c2a AC |
1193 | int op = (insn >> 11); |
1194 | switch (op) | |
c906108c | 1195 | { |
6d82d43b | 1196 | case 2: /* Branch */ |
12f02c2a AC |
1197 | { |
1198 | CORE_ADDR offset; | |
1199 | struct upk_mips16 upk; | |
1200 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1201 | offset = upk.offset; | |
1202 | if (offset & 0x800) | |
1203 | { | |
1204 | offset &= 0xeff; | |
1205 | offset = -offset; | |
1206 | } | |
1207 | pc += (offset << 1) + 2; | |
1208 | break; | |
1209 | } | |
6d82d43b | 1210 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1211 | { |
1212 | struct upk_mips16 upk; | |
1213 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1214 | pc = add_offset_16 (pc, upk.offset); | |
1215 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1216 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1217 | else | |
1218 | pc |= 0x01; | |
1219 | break; | |
1220 | } | |
6d82d43b | 1221 | case 4: /* beqz */ |
12f02c2a AC |
1222 | { |
1223 | struct upk_mips16 upk; | |
1224 | int reg; | |
1225 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1226 | reg = read_signed_register (upk.regx); | |
1227 | if (reg == 0) | |
1228 | pc += (upk.offset << 1) + 2; | |
1229 | else | |
1230 | pc += 2; | |
1231 | break; | |
1232 | } | |
6d82d43b | 1233 | case 5: /* bnez */ |
12f02c2a AC |
1234 | { |
1235 | struct upk_mips16 upk; | |
1236 | int reg; | |
1237 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1238 | reg = read_signed_register (upk.regx); | |
1239 | if (reg != 0) | |
1240 | pc += (upk.offset << 1) + 2; | |
1241 | else | |
1242 | pc += 2; | |
1243 | break; | |
1244 | } | |
6d82d43b | 1245 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1246 | { |
1247 | struct upk_mips16 upk; | |
1248 | int reg; | |
1249 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1250 | /* upk.regx contains the opcode */ | |
1251 | reg = read_signed_register (24); /* Test register is 24 */ | |
1252 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1253 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1254 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1255 | pc += (upk.offset << 1) + 2; | |
1256 | else | |
1257 | pc += 2; | |
1258 | break; | |
1259 | } | |
6d82d43b | 1260 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1261 | { |
1262 | struct upk_mips16 upk; | |
1263 | /* upk.fmt = rrtype; */ | |
1264 | op = insn & 0x1f; | |
1265 | if (op == 0) | |
c5aa993b | 1266 | { |
12f02c2a AC |
1267 | int reg; |
1268 | upk.regx = (insn >> 8) & 0x07; | |
1269 | upk.regy = (insn >> 5) & 0x07; | |
1270 | switch (upk.regy) | |
c5aa993b | 1271 | { |
12f02c2a AC |
1272 | case 0: |
1273 | reg = upk.regx; | |
1274 | break; | |
1275 | case 1: | |
1276 | reg = 31; | |
6d82d43b | 1277 | break; /* Function return instruction */ |
12f02c2a AC |
1278 | case 2: |
1279 | reg = upk.regx; | |
1280 | break; | |
1281 | default: | |
1282 | reg = 31; | |
6d82d43b | 1283 | break; /* BOGUS Guess */ |
c906108c | 1284 | } |
12f02c2a | 1285 | pc = read_signed_register (reg); |
c906108c | 1286 | } |
12f02c2a | 1287 | else |
c5aa993b | 1288 | pc += 2; |
12f02c2a AC |
1289 | break; |
1290 | } | |
1291 | case 30: | |
1292 | /* This is an instruction extension. Fetch the real instruction | |
1293 | (which follows the extension) and decode things based on | |
1294 | that. */ | |
1295 | { | |
1296 | pc += 2; | |
1297 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1298 | break; | |
1299 | } | |
1300 | default: | |
1301 | { | |
1302 | pc += 2; | |
1303 | break; | |
1304 | } | |
c906108c | 1305 | } |
c5aa993b | 1306 | return pc; |
12f02c2a | 1307 | } |
c906108c | 1308 | |
5a89d8aa | 1309 | static CORE_ADDR |
12f02c2a AC |
1310 | mips16_next_pc (CORE_ADDR pc) |
1311 | { | |
1312 | unsigned int insn = fetch_mips_16 (pc); | |
1313 | return extended_mips16_next_pc (pc, 0, insn); | |
1314 | } | |
1315 | ||
1316 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1317 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1318 | It works by decoding the current instruction and predicting where a |
1319 | branch will go. This isnt hard because all the data is available. | |
1320 | The MIPS32 and MIPS16 variants are quite different */ | |
ad527d2e | 1321 | static CORE_ADDR |
c5aa993b | 1322 | mips_next_pc (CORE_ADDR pc) |
c906108c | 1323 | { |
c5aa993b JM |
1324 | if (pc & 0x01) |
1325 | return mips16_next_pc (pc); | |
1326 | else | |
1327 | return mips32_next_pc (pc); | |
12f02c2a | 1328 | } |
c906108c | 1329 | |
edfae063 AC |
1330 | struct mips_frame_cache |
1331 | { | |
1332 | CORE_ADDR base; | |
1333 | struct trad_frame_saved_reg *saved_regs; | |
1334 | }; | |
1335 | ||
29639122 JB |
1336 | /* Set a register's saved stack address in temp_saved_regs. If an |
1337 | address has already been set for this register, do nothing; this | |
1338 | way we will only recognize the first save of a given register in a | |
1339 | function prologue. | |
eec63939 | 1340 | |
29639122 JB |
1341 | For simplicity, save the address in both [0 .. NUM_REGS) and |
1342 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1343 | is used as it is only second range (the ABI instead of ISA | |
1344 | registers) that comes into play when finding saved registers in a | |
1345 | frame. */ | |
eec63939 AC |
1346 | |
1347 | static void | |
29639122 JB |
1348 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1349 | CORE_ADDR offset) | |
eec63939 | 1350 | { |
29639122 JB |
1351 | if (this_cache != NULL |
1352 | && this_cache->saved_regs[regnum].addr == -1) | |
1353 | { | |
1354 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; | |
1355 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
1356 | } | |
eec63939 AC |
1357 | } |
1358 | ||
eec63939 | 1359 | |
29639122 JB |
1360 | /* Fetch the immediate value from a MIPS16 instruction. |
1361 | If the previous instruction was an EXTEND, use it to extend | |
1362 | the upper bits of the immediate value. This is a helper function | |
1363 | for mips16_scan_prologue. */ | |
eec63939 | 1364 | |
29639122 JB |
1365 | static int |
1366 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1367 | unsigned short inst, /* current instruction */ | |
1368 | int nbits, /* number of bits in imm field */ | |
1369 | int scale, /* scale factor to be applied to imm */ | |
1370 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1371 | { |
29639122 | 1372 | int offset; |
eec63939 | 1373 | |
29639122 JB |
1374 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1375 | { | |
1376 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1377 | if (offset & 0x8000) /* check for negative extend */ | |
1378 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1379 | return offset | (inst & 0x1f); | |
1380 | } | |
eec63939 | 1381 | else |
29639122 JB |
1382 | { |
1383 | int max_imm = 1 << nbits; | |
1384 | int mask = max_imm - 1; | |
1385 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1386 | |
29639122 JB |
1387 | offset = inst & mask; |
1388 | if (is_signed && (offset & sign_bit)) | |
1389 | offset = 0 - (max_imm - offset); | |
1390 | return offset * scale; | |
1391 | } | |
1392 | } | |
eec63939 | 1393 | |
65596487 | 1394 | |
29639122 JB |
1395 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1396 | the associated FRAME_CACHE if not null. | |
1397 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1398 | |
29639122 JB |
1399 | static CORE_ADDR |
1400 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1401 | struct frame_info *next_frame, | |
1402 | struct mips_frame_cache *this_cache) | |
1403 | { | |
1404 | CORE_ADDR cur_pc; | |
1405 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1406 | CORE_ADDR sp; | |
1407 | long frame_offset = 0; /* Size of stack frame. */ | |
1408 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1409 | int frame_reg = MIPS_SP_REGNUM; | |
1410 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1411 | unsigned inst = 0; /* current instruction */ | |
1412 | unsigned entry_inst = 0; /* the entry instruction */ | |
1413 | int reg, offset; | |
a343eb3c | 1414 | |
29639122 JB |
1415 | int extend_bytes = 0; |
1416 | int prev_extend_bytes; | |
1417 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1418 | |
29639122 JB |
1419 | /* Can be called when there's no process, and hence when there's no |
1420 | NEXT_FRAME. */ | |
1421 | if (next_frame != NULL) | |
1422 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
1423 | else | |
1424 | sp = 0; | |
eec63939 | 1425 | |
29639122 JB |
1426 | if (limit_pc > start_pc + 200) |
1427 | limit_pc = start_pc + 200; | |
eec63939 | 1428 | |
95ac2dcf | 1429 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1430 | { |
1431 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1432 | the immediate offset extension from it in mips16_get_imm. */ | |
1433 | prev_inst = inst; | |
eec63939 | 1434 | |
29639122 JB |
1435 | /* Fetch and decode the instruction. */ |
1436 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1437 | |
29639122 JB |
1438 | /* Normally we ignore extend instructions. However, if it is |
1439 | not followed by a valid prologue instruction, then this | |
1440 | instruction is not part of the prologue either. We must | |
1441 | remember in this case to adjust the end_prologue_addr back | |
1442 | over the extend. */ | |
1443 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1444 | { | |
95ac2dcf | 1445 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1446 | continue; |
1447 | } | |
eec63939 | 1448 | |
29639122 JB |
1449 | prev_extend_bytes = extend_bytes; |
1450 | extend_bytes = 0; | |
eec63939 | 1451 | |
29639122 JB |
1452 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1453 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1454 | { | |
1455 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1456 | if (offset < 0) /* negative stack adjustment? */ | |
1457 | frame_offset -= offset; | |
1458 | else | |
1459 | /* Exit loop if a positive stack adjustment is found, which | |
1460 | usually means that the stack cleanup code in the function | |
1461 | epilogue is reached. */ | |
1462 | break; | |
1463 | } | |
1464 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1465 | { | |
1466 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1467 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1468 | set_reg_offset (this_cache, reg, sp + offset); | |
1469 | } | |
1470 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1471 | { | |
1472 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1473 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1474 | set_reg_offset (this_cache, reg, sp + offset); | |
1475 | } | |
1476 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1477 | { | |
1478 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1479 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1480 | } |
1481 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1482 | { | |
1483 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1484 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1485 | } |
1486 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1487 | { | |
1488 | frame_addr = sp; | |
1489 | frame_reg = 17; | |
1490 | } | |
1491 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1492 | { | |
1493 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1494 | frame_addr = sp + offset; | |
1495 | frame_reg = 17; | |
1496 | frame_adjust = offset; | |
1497 | } | |
1498 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1499 | { | |
1500 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1501 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1502 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1503 | } | |
1504 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1505 | { | |
1506 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1507 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1508 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1509 | } | |
1510 | else if ((inst & 0xf81f) == 0xe809 | |
1511 | && (inst & 0x700) != 0x700) /* entry */ | |
1512 | entry_inst = inst; /* save for later processing */ | |
1513 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1514 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1515 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1516 | { | |
1517 | /* This instruction is part of the prologue, but we don't | |
1518 | need to do anything special to handle it. */ | |
1519 | } | |
1520 | else | |
1521 | { | |
1522 | /* This instruction is not an instruction typically found | |
1523 | in a prologue, so we must have reached the end of the | |
1524 | prologue. */ | |
1525 | if (end_prologue_addr == 0) | |
1526 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1527 | } | |
1528 | } | |
eec63939 | 1529 | |
29639122 JB |
1530 | /* The entry instruction is typically the first instruction in a function, |
1531 | and it stores registers at offsets relative to the value of the old SP | |
1532 | (before the prologue). But the value of the sp parameter to this | |
1533 | function is the new SP (after the prologue has been executed). So we | |
1534 | can't calculate those offsets until we've seen the entire prologue, | |
1535 | and can calculate what the old SP must have been. */ | |
1536 | if (entry_inst != 0) | |
1537 | { | |
1538 | int areg_count = (entry_inst >> 8) & 7; | |
1539 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1540 | |
29639122 JB |
1541 | /* The entry instruction always subtracts 32 from the SP. */ |
1542 | frame_offset += 32; | |
1543 | ||
1544 | /* Now we can calculate what the SP must have been at the | |
1545 | start of the function prologue. */ | |
1546 | sp += frame_offset; | |
1547 | ||
1548 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1549 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1550 | { | |
1551 | set_reg_offset (this_cache, reg, sp + offset); | |
1552 | offset += mips_abi_regsize (current_gdbarch); | |
1553 | } | |
1554 | ||
1555 | /* Check if the ra register was pushed on the stack. */ | |
1556 | offset = -4; | |
1557 | if (entry_inst & 0x20) | |
1558 | { | |
4c7d22cb | 1559 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1560 | offset -= mips_abi_regsize (current_gdbarch); |
1561 | } | |
1562 | ||
1563 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1564 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1565 | { | |
1566 | set_reg_offset (this_cache, reg, sp + offset); | |
1567 | offset -= mips_abi_regsize (current_gdbarch); | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | if (this_cache != NULL) | |
1572 | { | |
1573 | this_cache->base = | |
1574 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1575 | + frame_offset - frame_adjust); | |
1576 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1577 | be able to get rid of the assignment below, evetually. But it's | |
1578 | still needed for now. */ | |
1579 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1580 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 JB |
1581 | } |
1582 | ||
1583 | /* If we didn't reach the end of the prologue when scanning the function | |
1584 | instructions, then set end_prologue_addr to the address of the | |
1585 | instruction immediately after the last one we scanned. */ | |
1586 | if (end_prologue_addr == 0) | |
1587 | end_prologue_addr = cur_pc; | |
1588 | ||
1589 | return end_prologue_addr; | |
eec63939 AC |
1590 | } |
1591 | ||
29639122 JB |
1592 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1593 | Procedures that use the 32-bit instruction set are handled by the | |
1594 | mips_insn32 unwinder. */ | |
1595 | ||
1596 | static struct mips_frame_cache * | |
1597 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1598 | { |
29639122 | 1599 | struct mips_frame_cache *cache; |
eec63939 AC |
1600 | |
1601 | if ((*this_cache) != NULL) | |
1602 | return (*this_cache); | |
29639122 JB |
1603 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1604 | (*this_cache) = cache; | |
1605 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1606 | |
29639122 JB |
1607 | /* Analyze the function prologue. */ |
1608 | { | |
6de5b849 JB |
1609 | const CORE_ADDR pc = |
1610 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1611 | CORE_ADDR start_addr; |
eec63939 | 1612 | |
29639122 JB |
1613 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1614 | if (start_addr == 0) | |
1615 | start_addr = heuristic_proc_start (pc); | |
1616 | /* We can't analyze the prologue if we couldn't find the begining | |
1617 | of the function. */ | |
1618 | if (start_addr == 0) | |
1619 | return cache; | |
eec63939 | 1620 | |
29639122 JB |
1621 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1622 | } | |
1623 | ||
1624 | /* SP_REGNUM, contains the value and not the address. */ | |
1625 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1626 | |
29639122 | 1627 | return (*this_cache); |
eec63939 AC |
1628 | } |
1629 | ||
1630 | static void | |
29639122 JB |
1631 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1632 | struct frame_id *this_id) | |
eec63939 | 1633 | { |
29639122 JB |
1634 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1635 | this_cache); | |
93d42b30 DJ |
1636 | (*this_id) = frame_id_build (info->base, |
1637 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1638 | } |
1639 | ||
1640 | static void | |
29639122 | 1641 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1642 | void **this_cache, |
1643 | int regnum, int *optimizedp, | |
1644 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1645 | int *realnump, gdb_byte *valuep) |
eec63939 | 1646 | { |
29639122 JB |
1647 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1648 | this_cache); | |
1649 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1650 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1651 | } |
1652 | ||
29639122 | 1653 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1654 | { |
1655 | NORMAL_FRAME, | |
29639122 JB |
1656 | mips_insn16_frame_this_id, |
1657 | mips_insn16_frame_prev_register | |
eec63939 AC |
1658 | }; |
1659 | ||
1660 | static const struct frame_unwind * | |
29639122 | 1661 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1662 | { |
6de5b849 | 1663 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1664 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1665 | return &mips_insn16_frame_unwind; |
1666 | return NULL; | |
eec63939 AC |
1667 | } |
1668 | ||
1669 | static CORE_ADDR | |
29639122 JB |
1670 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1671 | void **this_cache) | |
eec63939 | 1672 | { |
29639122 JB |
1673 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1674 | this_cache); | |
1675 | return info->base; | |
eec63939 AC |
1676 | } |
1677 | ||
29639122 | 1678 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1679 | { |
29639122 JB |
1680 | &mips_insn16_frame_unwind, |
1681 | mips_insn16_frame_base_address, | |
1682 | mips_insn16_frame_base_address, | |
1683 | mips_insn16_frame_base_address | |
eec63939 AC |
1684 | }; |
1685 | ||
1686 | static const struct frame_base * | |
29639122 | 1687 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1688 | { |
29639122 JB |
1689 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1690 | return &mips_insn16_frame_base; | |
eec63939 AC |
1691 | else |
1692 | return NULL; | |
edfae063 AC |
1693 | } |
1694 | ||
29639122 JB |
1695 | /* Mark all the registers as unset in the saved_regs array |
1696 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1697 | ||
1698 | void | |
1699 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1700 | { |
29639122 JB |
1701 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1702 | return; | |
1703 | ||
1704 | { | |
1705 | const int num_regs = NUM_REGS; | |
1706 | int i; | |
64159455 | 1707 | |
29639122 JB |
1708 | for (i = 0; i < num_regs; i++) |
1709 | { | |
1710 | this_cache->saved_regs[i].addr = -1; | |
1711 | } | |
1712 | } | |
c906108c SS |
1713 | } |
1714 | ||
29639122 JB |
1715 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1716 | the associated FRAME_CACHE if not null. | |
1717 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1718 | |
875e1767 | 1719 | static CORE_ADDR |
29639122 JB |
1720 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1721 | struct frame_info *next_frame, | |
1722 | struct mips_frame_cache *this_cache) | |
c906108c | 1723 | { |
29639122 JB |
1724 | CORE_ADDR cur_pc; |
1725 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1726 | CORE_ADDR sp; | |
1727 | long frame_offset; | |
1728 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1729 | |
29639122 JB |
1730 | CORE_ADDR end_prologue_addr = 0; |
1731 | int seen_sp_adjust = 0; | |
1732 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1733 | |
29639122 JB |
1734 | /* Can be called when there's no process, and hence when there's no |
1735 | NEXT_FRAME. */ | |
1736 | if (next_frame != NULL) | |
1737 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1738 | else |
29639122 | 1739 | sp = 0; |
9022177c | 1740 | |
29639122 JB |
1741 | if (limit_pc > start_pc + 200) |
1742 | limit_pc = start_pc + 200; | |
9022177c | 1743 | |
29639122 | 1744 | restart: |
9022177c | 1745 | |
29639122 | 1746 | frame_offset = 0; |
95ac2dcf | 1747 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1748 | { |
29639122 JB |
1749 | unsigned long inst, high_word, low_word; |
1750 | int reg; | |
9022177c | 1751 | |
29639122 JB |
1752 | /* Fetch the instruction. */ |
1753 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1754 | |
29639122 JB |
1755 | /* Save some code by pre-extracting some useful fields. */ |
1756 | high_word = (inst >> 16) & 0xffff; | |
1757 | low_word = inst & 0xffff; | |
1758 | reg = high_word & 0x1f; | |
fe29b929 | 1759 | |
29639122 JB |
1760 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1761 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1762 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1763 | { | |
1764 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1765 | frame_offset += 0x10000 - low_word; | |
1766 | else | |
1767 | /* Exit loop if a positive stack adjustment is found, which | |
1768 | usually means that the stack cleanup code in the function | |
1769 | epilogue is reached. */ | |
1770 | break; | |
1771 | seen_sp_adjust = 1; | |
1772 | } | |
1773 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1774 | { | |
1775 | set_reg_offset (this_cache, reg, sp + low_word); | |
1776 | } | |
1777 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1778 | { | |
1779 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1780 | set_reg_offset (this_cache, reg, sp + low_word); | |
1781 | } | |
1782 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1783 | { | |
1784 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1785 | if ((long) low_word != frame_offset) | |
1786 | frame_addr = sp + low_word; | |
1787 | else if (frame_reg == MIPS_SP_REGNUM) | |
1788 | { | |
1789 | unsigned alloca_adjust; | |
a4b8ebc8 | 1790 | |
29639122 JB |
1791 | frame_reg = 30; |
1792 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
1793 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
1794 | if (alloca_adjust > 0) | |
1795 | { | |
1796 | /* FP > SP + frame_size. This may be because of | |
1797 | an alloca or somethings similar. Fix sp to | |
1798 | "pre-alloca" value, and try again. */ | |
1799 | sp += alloca_adjust; | |
1800 | /* Need to reset the status of all registers. Otherwise, | |
1801 | we will hit a guard that prevents the new address | |
1802 | for each register to be recomputed during the second | |
1803 | pass. */ | |
1804 | reset_saved_regs (this_cache); | |
1805 | goto restart; | |
1806 | } | |
1807 | } | |
1808 | } | |
1809 | /* move $30,$sp. With different versions of gas this will be either | |
1810 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1811 | Accept any one of these. */ | |
1812 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1813 | { | |
1814 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1815 | if (frame_reg == MIPS_SP_REGNUM) | |
1816 | { | |
1817 | unsigned alloca_adjust; | |
c906108c | 1818 | |
29639122 JB |
1819 | frame_reg = 30; |
1820 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
1821 | alloca_adjust = (unsigned) (frame_addr - sp); | |
1822 | if (alloca_adjust > 0) | |
1823 | { | |
1824 | /* FP > SP + frame_size. This may be because of | |
1825 | an alloca or somethings similar. Fix sp to | |
1826 | "pre-alloca" value, and try again. */ | |
1827 | sp = frame_addr; | |
1828 | /* Need to reset the status of all registers. Otherwise, | |
1829 | we will hit a guard that prevents the new address | |
1830 | for each register to be recomputed during the second | |
1831 | pass. */ | |
1832 | reset_saved_regs (this_cache); | |
1833 | goto restart; | |
1834 | } | |
1835 | } | |
1836 | } | |
1837 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1838 | { | |
1839 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1840 | } | |
1841 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1842 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1843 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1844 | || high_word == 0x3c1c /* lui $gp,n */ | |
1845 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1846 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1847 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1848 | ) | |
1849 | { | |
1850 | /* These instructions are part of the prologue, but we don't | |
1851 | need to do anything special to handle them. */ | |
1852 | } | |
1853 | /* The instructions below load $at or $t0 with an immediate | |
1854 | value in preparation for a stack adjustment via | |
1855 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1856 | initialize a local variable, so we accept them only before | |
1857 | a stack adjustment instruction was seen. */ | |
1858 | else if (!seen_sp_adjust | |
1859 | && (high_word == 0x3c01 /* lui $at,n */ | |
1860 | || high_word == 0x3c08 /* lui $t0,n */ | |
1861 | || high_word == 0x3421 /* ori $at,$at,n */ | |
1862 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
1863 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
1864 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
1865 | )) | |
1866 | { | |
95ac2dcf | 1867 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
1868 | } |
1869 | else | |
1870 | { | |
1871 | /* This instruction is not an instruction typically found | |
1872 | in a prologue, so we must have reached the end of the | |
1873 | prologue. */ | |
1874 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
1875 | loop now? Why would we need to continue scanning the function | |
1876 | instructions? */ | |
1877 | if (end_prologue_addr == 0) | |
1878 | end_prologue_addr = cur_pc; | |
1879 | } | |
a4b8ebc8 | 1880 | } |
c906108c | 1881 | |
29639122 JB |
1882 | if (this_cache != NULL) |
1883 | { | |
1884 | this_cache->base = | |
1885 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1886 | + frame_offset); | |
1887 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
1888 | this assignment below, eventually. But it's still needed | |
1889 | for now. */ | |
1890 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1891 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 | 1892 | } |
c906108c | 1893 | |
29639122 JB |
1894 | /* If we didn't reach the end of the prologue when scanning the function |
1895 | instructions, then set end_prologue_addr to the address of the | |
1896 | instruction immediately after the last one we scanned. */ | |
1897 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
1898 | we may as well be careful and do our best if we have a null | |
1899 | end_prologue_addr. */ | |
1900 | if (end_prologue_addr == 0) | |
1901 | end_prologue_addr = cur_pc; | |
1902 | ||
1903 | /* In a frameless function, we might have incorrectly | |
1904 | skipped some load immediate instructions. Undo the skipping | |
1905 | if the load immediate was not followed by a stack adjustment. */ | |
1906 | if (load_immediate_bytes && !seen_sp_adjust) | |
1907 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 1908 | |
29639122 | 1909 | return end_prologue_addr; |
c906108c SS |
1910 | } |
1911 | ||
29639122 JB |
1912 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
1913 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
1914 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
1915 | unwinder. */ | |
c906108c | 1916 | |
29639122 JB |
1917 | static struct mips_frame_cache * |
1918 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 1919 | { |
29639122 | 1920 | struct mips_frame_cache *cache; |
c906108c | 1921 | |
29639122 JB |
1922 | if ((*this_cache) != NULL) |
1923 | return (*this_cache); | |
c5aa993b | 1924 | |
29639122 JB |
1925 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1926 | (*this_cache) = cache; | |
1927 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 1928 | |
29639122 JB |
1929 | /* Analyze the function prologue. */ |
1930 | { | |
6de5b849 JB |
1931 | const CORE_ADDR pc = |
1932 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1933 | CORE_ADDR start_addr; |
c906108c | 1934 | |
29639122 JB |
1935 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1936 | if (start_addr == 0) | |
1937 | start_addr = heuristic_proc_start (pc); | |
1938 | /* We can't analyze the prologue if we couldn't find the begining | |
1939 | of the function. */ | |
1940 | if (start_addr == 0) | |
1941 | return cache; | |
c5aa993b | 1942 | |
29639122 JB |
1943 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1944 | } | |
1945 | ||
1946 | /* SP_REGNUM, contains the value and not the address. */ | |
1947 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
c5aa993b | 1948 | |
29639122 | 1949 | return (*this_cache); |
c906108c SS |
1950 | } |
1951 | ||
29639122 JB |
1952 | static void |
1953 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1954 | struct frame_id *this_id) | |
c906108c | 1955 | { |
29639122 JB |
1956 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
1957 | this_cache); | |
93d42b30 DJ |
1958 | (*this_id) = frame_id_build (info->base, |
1959 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 1960 | } |
c906108c | 1961 | |
29639122 JB |
1962 | static void |
1963 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
1964 | void **this_cache, | |
1965 | int regnum, int *optimizedp, | |
1966 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1967 | int *realnump, gdb_byte *valuep) |
29639122 JB |
1968 | { |
1969 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
1970 | this_cache); | |
1971 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1972 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1973 | } |
1974 | ||
29639122 JB |
1975 | static const struct frame_unwind mips_insn32_frame_unwind = |
1976 | { | |
1977 | NORMAL_FRAME, | |
1978 | mips_insn32_frame_this_id, | |
1979 | mips_insn32_frame_prev_register | |
1980 | }; | |
c906108c | 1981 | |
29639122 JB |
1982 | static const struct frame_unwind * |
1983 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
1984 | { | |
6de5b849 | 1985 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1986 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
1987 | return &mips_insn32_frame_unwind; |
1988 | return NULL; | |
1989 | } | |
c906108c | 1990 | |
1c645fec | 1991 | static CORE_ADDR |
29639122 JB |
1992 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
1993 | void **this_cache) | |
c906108c | 1994 | { |
29639122 JB |
1995 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
1996 | this_cache); | |
1997 | return info->base; | |
1998 | } | |
c906108c | 1999 | |
29639122 JB |
2000 | static const struct frame_base mips_insn32_frame_base = |
2001 | { | |
2002 | &mips_insn32_frame_unwind, | |
2003 | mips_insn32_frame_base_address, | |
2004 | mips_insn32_frame_base_address, | |
2005 | mips_insn32_frame_base_address | |
2006 | }; | |
1c645fec | 2007 | |
29639122 JB |
2008 | static const struct frame_base * |
2009 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2010 | { | |
2011 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2012 | return &mips_insn32_frame_base; | |
a65bbe44 | 2013 | else |
29639122 JB |
2014 | return NULL; |
2015 | } | |
a65bbe44 | 2016 | |
29639122 JB |
2017 | static struct trad_frame_cache * |
2018 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2019 | { | |
2020 | CORE_ADDR pc; | |
2021 | CORE_ADDR start_addr; | |
2022 | CORE_ADDR stack_addr; | |
2023 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2024 | |
29639122 JB |
2025 | if ((*this_cache) != NULL) |
2026 | return (*this_cache); | |
2027 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2028 | (*this_cache) = this_trad_cache; | |
1c645fec | 2029 | |
29639122 | 2030 | /* The return address is in the link register. */ |
4c7d22cb | 2031 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2032 | |
29639122 JB |
2033 | /* Frame ID, since it's a frameless / stackless function, no stack |
2034 | space is allocated and SP on entry is the current SP. */ | |
2035 | pc = frame_pc_unwind (next_frame); | |
2036 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2037 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2038 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2039 | |
29639122 JB |
2040 | /* Assume that the frame's base is the same as the |
2041 | stack-pointer. */ | |
2042 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2043 | |
29639122 JB |
2044 | return this_trad_cache; |
2045 | } | |
c906108c | 2046 | |
29639122 JB |
2047 | static void |
2048 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2049 | struct frame_id *this_id) | |
2050 | { | |
2051 | struct trad_frame_cache *this_trad_cache | |
2052 | = mips_stub_frame_cache (next_frame, this_cache); | |
2053 | trad_frame_get_id (this_trad_cache, this_id); | |
2054 | } | |
c906108c | 2055 | |
29639122 JB |
2056 | static void |
2057 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2058 | void **this_cache, | |
2059 | int regnum, int *optimizedp, | |
2060 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2061 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2062 | { |
2063 | struct trad_frame_cache *this_trad_cache | |
2064 | = mips_stub_frame_cache (next_frame, this_cache); | |
2065 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2066 | lvalp, addrp, realnump, valuep); | |
2067 | } | |
c906108c | 2068 | |
29639122 JB |
2069 | static const struct frame_unwind mips_stub_frame_unwind = |
2070 | { | |
2071 | NORMAL_FRAME, | |
2072 | mips_stub_frame_this_id, | |
2073 | mips_stub_frame_prev_register | |
2074 | }; | |
c906108c | 2075 | |
29639122 JB |
2076 | static const struct frame_unwind * |
2077 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2078 | { | |
979b38e0 | 2079 | struct obj_section *s; |
93d42b30 | 2080 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2081 | |
29639122 JB |
2082 | if (in_plt_section (pc, NULL)) |
2083 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2084 | |
2085 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2086 | s = find_pc_section (pc); | |
2087 | ||
2088 | if (s != NULL | |
2089 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2090 | ".MIPS.stubs") == 0) | |
2091 | return &mips_stub_frame_unwind; | |
2092 | ||
2093 | return NULL; | |
29639122 | 2094 | } |
c906108c | 2095 | |
29639122 JB |
2096 | static CORE_ADDR |
2097 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2098 | void **this_cache) | |
2099 | { | |
2100 | struct trad_frame_cache *this_trad_cache | |
2101 | = mips_stub_frame_cache (next_frame, this_cache); | |
2102 | return trad_frame_get_this_base (this_trad_cache); | |
2103 | } | |
0fce0821 | 2104 | |
29639122 JB |
2105 | static const struct frame_base mips_stub_frame_base = |
2106 | { | |
2107 | &mips_stub_frame_unwind, | |
2108 | mips_stub_frame_base_address, | |
2109 | mips_stub_frame_base_address, | |
2110 | mips_stub_frame_base_address | |
2111 | }; | |
2112 | ||
2113 | static const struct frame_base * | |
2114 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2115 | { | |
2116 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2117 | return &mips_stub_frame_base; | |
2118 | else | |
2119 | return NULL; | |
2120 | } | |
2121 | ||
2122 | static CORE_ADDR | |
2123 | read_next_frame_reg (struct frame_info *fi, int regno) | |
2124 | { | |
2125 | /* Always a pseudo. */ | |
2126 | gdb_assert (regno >= NUM_REGS); | |
2127 | if (fi == NULL) | |
0fce0821 | 2128 | { |
29639122 JB |
2129 | LONGEST val; |
2130 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2131 | return val; | |
0fce0821 | 2132 | } |
29639122 JB |
2133 | else |
2134 | return frame_unwind_register_signed (fi, regno); | |
1c645fec | 2135 | |
c906108c SS |
2136 | } |
2137 | ||
29639122 | 2138 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2139 | |
29639122 JB |
2140 | static CORE_ADDR |
2141 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2142 | { |
29639122 JB |
2143 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2144 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2145 | /* This hack is a work-around for existing boards using PMON, the | |
2146 | simulator, and any other 64-bit targets that doesn't have true | |
2147 | 64-bit addressing. On these targets, the upper 32 bits of | |
2148 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2149 | likely to have been sign extended to all 1s by instruction | |
2150 | sequences that load 32-bit addresses. For example, a typical | |
2151 | piece of code that loads an address is this: | |
65596487 | 2152 | |
29639122 JB |
2153 | lui $r2, <upper 16 bits> |
2154 | ori $r2, <lower 16 bits> | |
65596487 | 2155 | |
29639122 JB |
2156 | But the lui sign-extends the value such that the upper 32 bits |
2157 | may be all 1s. The workaround is simply to mask off these | |
2158 | bits. In the future, gcc may be changed to support true 64-bit | |
2159 | addressing, and this masking will have to be disabled. */ | |
2160 | return addr &= 0xffffffffUL; | |
2161 | else | |
2162 | return addr; | |
65596487 JB |
2163 | } |
2164 | ||
29639122 JB |
2165 | /* mips_software_single_step() is called just before we want to resume |
2166 | the inferior, if we want to single-step it but there is no hardware | |
2167 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2168 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2169 | |
e6590a1b | 2170 | int |
e0cd558a | 2171 | mips_software_single_step (struct regcache *regcache) |
c906108c | 2172 | { |
8181d85f | 2173 | CORE_ADDR pc, next_pc; |
65596487 | 2174 | |
e0cd558a UW |
2175 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
2176 | next_pc = mips_next_pc (pc); | |
e6590a1b | 2177 | |
e0cd558a | 2178 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2179 | return 1; |
29639122 | 2180 | } |
a65bbe44 | 2181 | |
29639122 JB |
2182 | /* Test whether the PC points to the return instruction at the |
2183 | end of a function. */ | |
65596487 | 2184 | |
29639122 JB |
2185 | static int |
2186 | mips_about_to_return (CORE_ADDR pc) | |
2187 | { | |
0fe7e7c8 | 2188 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2189 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2190 | generates a "jr $ra"; other times it generates code to load | |
2191 | the return address from the stack to an accessible register (such | |
2192 | as $a3), then a "jr" using that register. This second case | |
2193 | is almost impossible to distinguish from an indirect jump | |
2194 | used for switch statements, so we don't even try. */ | |
2195 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2196 | else | |
2197 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2198 | } | |
c906108c | 2199 | |
c906108c | 2200 | |
29639122 JB |
2201 | /* This fencepost looks highly suspicious to me. Removing it also |
2202 | seems suspicious as it could affect remote debugging across serial | |
2203 | lines. */ | |
c906108c | 2204 | |
29639122 JB |
2205 | static CORE_ADDR |
2206 | heuristic_proc_start (CORE_ADDR pc) | |
2207 | { | |
2208 | CORE_ADDR start_pc; | |
2209 | CORE_ADDR fence; | |
2210 | int instlen; | |
2211 | int seen_adjsp = 0; | |
65596487 | 2212 | |
29639122 JB |
2213 | pc = ADDR_BITS_REMOVE (pc); |
2214 | start_pc = pc; | |
2215 | fence = start_pc - heuristic_fence_post; | |
2216 | if (start_pc == 0) | |
2217 | return 0; | |
65596487 | 2218 | |
29639122 JB |
2219 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2220 | fence = VM_MIN_ADDRESS; | |
65596487 | 2221 | |
95ac2dcf | 2222 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2223 | |
29639122 JB |
2224 | /* search back for previous return */ |
2225 | for (start_pc -= instlen;; start_pc -= instlen) | |
2226 | if (start_pc < fence) | |
2227 | { | |
2228 | /* It's not clear to me why we reach this point when | |
2229 | stop_soon, but with this test, at least we | |
2230 | don't print out warnings for every child forked (eg, on | |
2231 | decstation). 22apr93 rich@cygnus.com. */ | |
2232 | if (stop_soon == NO_STOP_QUIETLY) | |
2233 | { | |
2234 | static int blurb_printed = 0; | |
98b4dd94 | 2235 | |
8a3fe4f8 | 2236 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2237 | paddr_nz (pc)); |
2238 | ||
2239 | if (!blurb_printed) | |
2240 | { | |
2241 | /* This actually happens frequently in embedded | |
2242 | development, when you first connect to a board | |
2243 | and your stack pointer and pc are nowhere in | |
2244 | particular. This message needs to give people | |
2245 | in that situation enough information to | |
2246 | determine that it's no big deal. */ | |
2247 | printf_filtered ("\n\ | |
2248 | GDB is unable to find the start of the function at 0x%s\n\ | |
2249 | and thus can't determine the size of that function's stack frame.\n\ | |
2250 | This means that GDB may be unable to access that stack frame, or\n\ | |
2251 | the frames below it.\n\ | |
2252 | This problem is most likely caused by an invalid program counter or\n\ | |
2253 | stack pointer.\n\ | |
2254 | However, if you think GDB should simply search farther back\n\ | |
2255 | from 0x%s for code which looks like the beginning of a\n\ | |
2256 | function, you can increase the range of the search using the `set\n\ | |
2257 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2258 | blurb_printed = 1; | |
2259 | } | |
2260 | } | |
2261 | ||
2262 | return 0; | |
2263 | } | |
0fe7e7c8 | 2264 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2265 | { |
2266 | unsigned short inst; | |
2267 | ||
2268 | /* On MIPS16, any one of the following is likely to be the | |
2269 | start of a function: | |
2270 | entry | |
2271 | addiu sp,-n | |
2272 | daddiu sp,-n | |
2273 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2274 | inst = mips_fetch_instruction (start_pc); | |
2275 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2276 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2277 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2278 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2279 | break; | |
2280 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2281 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2282 | seen_adjsp = 1; | |
2283 | else | |
2284 | seen_adjsp = 0; | |
2285 | } | |
2286 | else if (mips_about_to_return (start_pc)) | |
2287 | { | |
4c7d22cb | 2288 | /* Skip return and its delay slot. */ |
95ac2dcf | 2289 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2290 | break; |
2291 | } | |
2292 | ||
2293 | return start_pc; | |
c906108c SS |
2294 | } |
2295 | ||
6c0d6680 DJ |
2296 | struct mips_objfile_private |
2297 | { | |
2298 | bfd_size_type size; | |
2299 | char *contents; | |
2300 | }; | |
2301 | ||
f09ded24 AC |
2302 | /* According to the current ABI, should the type be passed in a |
2303 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2304 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2305 | FP registers and, consequently this returns false - forces FP |
2306 | arguments into integer registers. */ | |
2307 | ||
2308 | static int | |
2309 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2310 | { | |
2311 | return ((typecode == TYPE_CODE_FLT | |
2312 | || (MIPS_EABI | |
6d82d43b AC |
2313 | && (typecode == TYPE_CODE_STRUCT |
2314 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2315 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2316 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2317 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2318 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2319 | } |
2320 | ||
49e790b0 DJ |
2321 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2322 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2323 | ||
2324 | static int | |
2325 | mips_type_needs_double_align (struct type *type) | |
2326 | { | |
2327 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2328 | |
49e790b0 DJ |
2329 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2330 | return 1; | |
2331 | else if (typecode == TYPE_CODE_STRUCT) | |
2332 | { | |
2333 | if (TYPE_NFIELDS (type) < 1) | |
2334 | return 0; | |
2335 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2336 | } | |
2337 | else if (typecode == TYPE_CODE_UNION) | |
2338 | { | |
361d1df0 | 2339 | int i, n; |
49e790b0 DJ |
2340 | |
2341 | n = TYPE_NFIELDS (type); | |
2342 | for (i = 0; i < n; i++) | |
2343 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2344 | return 1; | |
2345 | return 0; | |
2346 | } | |
2347 | return 0; | |
2348 | } | |
2349 | ||
dc604539 AC |
2350 | /* Adjust the address downward (direction of stack growth) so that it |
2351 | is correctly aligned for a new stack frame. */ | |
2352 | static CORE_ADDR | |
2353 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2354 | { | |
5b03f266 | 2355 | return align_down (addr, 16); |
dc604539 AC |
2356 | } |
2357 | ||
f7ab6ec6 | 2358 | static CORE_ADDR |
7d9b040b | 2359 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2360 | struct regcache *regcache, CORE_ADDR bp_addr, |
2361 | int nargs, struct value **args, CORE_ADDR sp, | |
2362 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2363 | { |
2364 | int argreg; | |
2365 | int float_argreg; | |
2366 | int argnum; | |
2367 | int len = 0; | |
2368 | int stack_offset = 0; | |
480d3dd2 | 2369 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2370 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2371 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2372 | |
25ab4790 AC |
2373 | /* For shared libraries, "t9" needs to point at the function |
2374 | address. */ | |
4c7d22cb | 2375 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2376 | |
2377 | /* Set the return address register to point to the entry point of | |
2378 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2379 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2380 | |
c906108c | 2381 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2382 | are properly aligned. The stack has to be at least 64-bit |
2383 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2384 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2385 | aligned, so we round to this widest known alignment. */ | |
2386 | ||
5b03f266 AC |
2387 | sp = align_down (sp, 16); |
2388 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2389 | |
46e0f506 | 2390 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2391 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2392 | passed in registers, but that's OK. */ |
c906108c | 2393 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2394 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2395 | sp -= align_up (len, 16); |
c906108c | 2396 | |
9ace0497 | 2397 | if (mips_debug) |
6d82d43b | 2398 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2399 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2400 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2401 | |
c906108c | 2402 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2403 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2404 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2405 | |
46e0f506 | 2406 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2407 | if (struct_return) |
9ace0497 AC |
2408 | { |
2409 | if (mips_debug) | |
2410 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2411 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2412 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2413 | write_register (argreg++, struct_addr); |
2414 | } | |
c906108c SS |
2415 | |
2416 | /* Now load as many as possible of the first arguments into | |
2417 | registers, and push the rest onto the stack. Loop thru args | |
2418 | from first to last. */ | |
2419 | for (argnum = 0; argnum < nargs; argnum++) | |
2420 | { | |
47a35522 MK |
2421 | const gdb_byte *val; |
2422 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2423 | struct value *arg = args[argnum]; |
4991999e | 2424 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2425 | int len = TYPE_LENGTH (arg_type); |
2426 | enum type_code typecode = TYPE_CODE (arg_type); | |
2427 | ||
9ace0497 AC |
2428 | if (mips_debug) |
2429 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2430 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2431 | argnum + 1, len, (int) typecode); |
9ace0497 | 2432 | |
c906108c | 2433 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2434 | reference. */ |
1a69e1e4 | 2435 | if (len > regsize |
9ace0497 | 2436 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2437 | { |
1a69e1e4 | 2438 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2439 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2440 | len = regsize; |
c906108c | 2441 | val = valbuf; |
9ace0497 AC |
2442 | if (mips_debug) |
2443 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2444 | } |
2445 | else | |
47a35522 | 2446 | val = value_contents (arg); |
c906108c SS |
2447 | |
2448 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2449 | even-numbered floating point register. Round the FP register |
2450 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2451 | left. Non MIPS_EABI targets also pass the FP in the integer |
2452 | registers so also round up normal registers. */ | |
1a69e1e4 | 2453 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2454 | { |
2455 | if ((float_argreg & 1)) | |
2456 | float_argreg++; | |
2457 | } | |
c906108c SS |
2458 | |
2459 | /* Floating point arguments passed in registers have to be | |
2460 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2461 | are passed in register pairs; the even register gets |
2462 | the low word, and the odd register gets the high word. | |
2463 | On non-EABI processors, the first two floating point arguments are | |
2464 | also copied to general registers, because MIPS16 functions | |
2465 | don't use float registers for arguments. This duplication of | |
2466 | arguments in general registers can't hurt non-MIPS16 functions | |
2467 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2468 | /* MIPS_EABI squeezes a struct that contains a single floating |
2469 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2470 | stack. */ |
f09ded24 AC |
2471 | if (fp_register_arg_p (typecode, arg_type) |
2472 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2473 | { |
6da397e0 KB |
2474 | /* EABI32 will pass doubles in consecutive registers, even on |
2475 | 64-bit cores. At one time, we used to check the size of | |
2476 | `float_argreg' to determine whether or not to pass doubles | |
2477 | in consecutive registers, but this is not sufficient for | |
2478 | making the ABI determination. */ | |
2479 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2480 | { |
d7449b42 | 2481 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2482 | unsigned long regval; |
2483 | ||
2484 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2485 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2486 | if (mips_debug) |
acdb74a0 | 2487 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2488 | float_argreg, phex (regval, 4)); |
c906108c | 2489 | write_register (float_argreg++, regval); |
c906108c SS |
2490 | |
2491 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2492 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2493 | if (mips_debug) |
acdb74a0 | 2494 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2495 | float_argreg, phex (regval, 4)); |
c906108c | 2496 | write_register (float_argreg++, regval); |
c906108c SS |
2497 | } |
2498 | else | |
2499 | { | |
2500 | /* This is a floating point value that fits entirely | |
2501 | in a single register. */ | |
53a5351d | 2502 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2503 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2504 | LONGEST regval = extract_unsigned_integer (val, len); |
2505 | if (mips_debug) | |
acdb74a0 | 2506 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2507 | float_argreg, phex (regval, len)); |
c906108c | 2508 | write_register (float_argreg++, regval); |
c906108c SS |
2509 | } |
2510 | } | |
2511 | else | |
2512 | { | |
2513 | /* Copy the argument to general registers or the stack in | |
2514 | register-sized pieces. Large arguments are split between | |
2515 | registers and stack. */ | |
1a69e1e4 DJ |
2516 | /* Note: structs whose size is not a multiple of regsize |
2517 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2518 | them in registers where gcc sometimes puts them on the |
2519 | stack. For maximum compatibility, we will put them in | |
2520 | both places. */ | |
1a69e1e4 | 2521 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2522 | |
f09ded24 | 2523 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2524 | register are only written to memory. */ |
c906108c SS |
2525 | while (len > 0) |
2526 | { | |
ebafbe83 | 2527 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2528 | int stack_used_p = 0; |
1a69e1e4 | 2529 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2530 | |
acdb74a0 AC |
2531 | if (mips_debug) |
2532 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2533 | partial_len); | |
2534 | ||
566f0f7a | 2535 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2536 | if (argreg > MIPS_LAST_ARG_REGNUM |
2537 | || odd_sized_struct | |
2538 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2539 | { |
c906108c SS |
2540 | /* Should shorter than int integer values be |
2541 | promoted to int before being stored? */ | |
c906108c | 2542 | int longword_offset = 0; |
9ace0497 | 2543 | CORE_ADDR addr; |
566f0f7a | 2544 | stack_used_p = 1; |
d7449b42 | 2545 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2546 | { |
1a69e1e4 | 2547 | if (regsize == 8 |
480d3dd2 AC |
2548 | && (typecode == TYPE_CODE_INT |
2549 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2550 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2551 | longword_offset = regsize - len; |
480d3dd2 AC |
2552 | else if ((typecode == TYPE_CODE_STRUCT |
2553 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2554 | && TYPE_LENGTH (arg_type) < regsize) |
2555 | longword_offset = regsize - len; | |
7a292a7a | 2556 | } |
c5aa993b | 2557 | |
9ace0497 AC |
2558 | if (mips_debug) |
2559 | { | |
cb3d25d1 MS |
2560 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2561 | paddr_nz (stack_offset)); | |
2562 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2563 | paddr_nz (longword_offset)); | |
9ace0497 | 2564 | } |
361d1df0 | 2565 | |
9ace0497 AC |
2566 | addr = sp + stack_offset + longword_offset; |
2567 | ||
2568 | if (mips_debug) | |
2569 | { | |
2570 | int i; | |
6d82d43b | 2571 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2572 | paddr_nz (addr)); |
9ace0497 AC |
2573 | for (i = 0; i < partial_len; i++) |
2574 | { | |
6d82d43b | 2575 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2576 | val[i] & 0xff); |
9ace0497 AC |
2577 | } |
2578 | } | |
2579 | write_memory (addr, val, partial_len); | |
c906108c SS |
2580 | } |
2581 | ||
f09ded24 AC |
2582 | /* Note!!! This is NOT an else clause. Odd sized |
2583 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2584 | arguments will not. */ |
566f0f7a | 2585 | /* Write this portion of the argument to a general |
6d82d43b | 2586 | purpose register. */ |
f09ded24 AC |
2587 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2588 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2589 | { |
6d82d43b AC |
2590 | LONGEST regval = |
2591 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2592 | |
9ace0497 | 2593 | if (mips_debug) |
acdb74a0 | 2594 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2595 | argreg, |
1a69e1e4 | 2596 | phex (regval, regsize)); |
c906108c SS |
2597 | write_register (argreg, regval); |
2598 | argreg++; | |
c906108c | 2599 | } |
c5aa993b | 2600 | |
c906108c SS |
2601 | len -= partial_len; |
2602 | val += partial_len; | |
2603 | ||
566f0f7a | 2604 | /* Compute the the offset into the stack at which we |
6d82d43b | 2605 | will copy the next parameter. |
566f0f7a | 2606 | |
566f0f7a | 2607 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2608 | only needs to be adjusted when it has been used. */ |
c906108c | 2609 | |
46e0f506 | 2610 | if (stack_used_p) |
1a69e1e4 | 2611 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2612 | } |
2613 | } | |
9ace0497 AC |
2614 | if (mips_debug) |
2615 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2616 | } |
2617 | ||
f10683bb | 2618 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2619 | |
0f71a2f6 JM |
2620 | /* Return adjusted stack pointer. */ |
2621 | return sp; | |
2622 | } | |
2623 | ||
a1f5b845 | 2624 | /* Determine the return value convention being used. */ |
6d82d43b | 2625 | |
9c8fdbfa AC |
2626 | static enum return_value_convention |
2627 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2628 | struct type *type, struct regcache *regcache, | |
47a35522 | 2629 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2630 | { |
9c8fdbfa AC |
2631 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2632 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2633 | if (readbuf) | |
2634 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2635 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2636 | } |
2637 | ||
6d82d43b AC |
2638 | |
2639 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2640 | |
f7ab6ec6 | 2641 | static CORE_ADDR |
7d9b040b | 2642 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2643 | struct regcache *regcache, CORE_ADDR bp_addr, |
2644 | int nargs, struct value **args, CORE_ADDR sp, | |
2645 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2646 | { |
2647 | int argreg; | |
2648 | int float_argreg; | |
2649 | int argnum; | |
2650 | int len = 0; | |
2651 | int stack_offset = 0; | |
480d3dd2 | 2652 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2653 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2654 | |
25ab4790 AC |
2655 | /* For shared libraries, "t9" needs to point at the function |
2656 | address. */ | |
4c7d22cb | 2657 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2658 | |
2659 | /* Set the return address register to point to the entry point of | |
2660 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2661 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2662 | |
cb3d25d1 MS |
2663 | /* First ensure that the stack and structure return address (if any) |
2664 | are properly aligned. The stack has to be at least 64-bit | |
2665 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2666 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2667 | aligned, so we round to this widest known alignment. */ | |
2668 | ||
5b03f266 AC |
2669 | sp = align_down (sp, 16); |
2670 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2671 | |
2672 | /* Now make space on the stack for the args. */ | |
2673 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2674 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2675 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2676 | |
2677 | if (mips_debug) | |
6d82d43b | 2678 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2679 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2680 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2681 | |
2682 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2683 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2684 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2685 | |
46e0f506 | 2686 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2687 | if (struct_return) |
2688 | { | |
2689 | if (mips_debug) | |
2690 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2691 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
2692 | argreg, paddr_nz (struct_addr)); |
2693 | write_register (argreg++, struct_addr); | |
2694 | } | |
2695 | ||
2696 | /* Now load as many as possible of the first arguments into | |
2697 | registers, and push the rest onto the stack. Loop thru args | |
2698 | from first to last. */ | |
2699 | for (argnum = 0; argnum < nargs; argnum++) | |
2700 | { | |
47a35522 | 2701 | const gdb_byte *val; |
cb3d25d1 | 2702 | struct value *arg = args[argnum]; |
4991999e | 2703 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2704 | int len = TYPE_LENGTH (arg_type); |
2705 | enum type_code typecode = TYPE_CODE (arg_type); | |
2706 | ||
2707 | if (mips_debug) | |
2708 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2709 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2710 | argnum + 1, len, (int) typecode); |
2711 | ||
47a35522 | 2712 | val = value_contents (arg); |
cb3d25d1 MS |
2713 | |
2714 | if (fp_register_arg_p (typecode, arg_type) | |
2715 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2716 | { | |
2717 | /* This is a floating point value that fits entirely | |
2718 | in a single register. */ | |
2719 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2720 | above to ensure that it is even register aligned. */ | |
2721 | LONGEST regval = extract_unsigned_integer (val, len); | |
2722 | if (mips_debug) | |
2723 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2724 | float_argreg, phex (regval, len)); | |
2725 | write_register (float_argreg++, regval); | |
2726 | ||
2727 | if (mips_debug) | |
2728 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2729 | argreg, phex (regval, len)); | |
2730 | write_register (argreg, regval); | |
2731 | argreg += 1; | |
2732 | } | |
2733 | else | |
2734 | { | |
2735 | /* Copy the argument to general registers or the stack in | |
2736 | register-sized pieces. Large arguments are split between | |
2737 | registers and stack. */ | |
1a69e1e4 | 2738 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
2739 | are treated specially: Irix cc passes them in registers |
2740 | where gcc sometimes puts them on the stack. For maximum | |
2741 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
2742 | int odd_sized_struct = (len > MIPS64_REGSIZE |
2743 | && len % MIPS64_REGSIZE != 0); | |
cb3d25d1 | 2744 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2745 | register are only written to memory. */ |
cb3d25d1 MS |
2746 | while (len > 0) |
2747 | { | |
ad018eee | 2748 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2749 | int stack_used_p = 0; |
1a69e1e4 | 2750 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2751 | |
2752 | if (mips_debug) | |
2753 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2754 | partial_len); | |
2755 | ||
2756 | /* Write this portion of the argument to the stack. */ | |
2757 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2758 | || odd_sized_struct | |
2759 | || fp_register_arg_p (typecode, arg_type)) | |
2760 | { | |
2761 | /* Should shorter than int integer values be | |
2762 | promoted to int before being stored? */ | |
2763 | int longword_offset = 0; | |
2764 | CORE_ADDR addr; | |
2765 | stack_used_p = 1; | |
2766 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2767 | { | |
1a69e1e4 DJ |
2768 | if ((typecode == TYPE_CODE_INT |
2769 | || typecode == TYPE_CODE_PTR | |
2770 | || typecode == TYPE_CODE_FLT) | |
2771 | && len <= 4) | |
2772 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2773 | } |
2774 | ||
2775 | if (mips_debug) | |
2776 | { | |
2777 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2778 | paddr_nz (stack_offset)); | |
2779 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2780 | paddr_nz (longword_offset)); | |
2781 | } | |
2782 | ||
2783 | addr = sp + stack_offset + longword_offset; | |
2784 | ||
2785 | if (mips_debug) | |
2786 | { | |
2787 | int i; | |
6d82d43b | 2788 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2789 | paddr_nz (addr)); |
2790 | for (i = 0; i < partial_len; i++) | |
2791 | { | |
6d82d43b | 2792 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2793 | val[i] & 0xff); |
2794 | } | |
2795 | } | |
2796 | write_memory (addr, val, partial_len); | |
2797 | } | |
2798 | ||
2799 | /* Note!!! This is NOT an else clause. Odd sized | |
2800 | structs may go thru BOTH paths. Floating point | |
2801 | arguments will not. */ | |
2802 | /* Write this portion of the argument to a general | |
6d82d43b | 2803 | purpose register. */ |
cb3d25d1 MS |
2804 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2805 | && !fp_register_arg_p (typecode, arg_type)) | |
2806 | { | |
6d82d43b AC |
2807 | LONGEST regval = |
2808 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
2809 | |
2810 | /* A non-floating-point argument being passed in a | |
2811 | general register. If a struct or union, and if | |
2812 | the remaining length is smaller than the register | |
2813 | size, we have to adjust the register value on | |
2814 | big endian targets. | |
2815 | ||
2816 | It does not seem to be necessary to do the | |
1a69e1e4 | 2817 | same for integral types. */ |
cb3d25d1 MS |
2818 | |
2819 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
1a69e1e4 | 2820 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
2821 | && (typecode == TYPE_CODE_STRUCT |
2822 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 2823 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 2824 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
2825 | |
2826 | if (mips_debug) | |
2827 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2828 | argreg, | |
1a69e1e4 | 2829 | phex (regval, MIPS64_REGSIZE)); |
cb3d25d1 MS |
2830 | write_register (argreg, regval); |
2831 | argreg++; | |
2832 | } | |
2833 | ||
2834 | len -= partial_len; | |
2835 | val += partial_len; | |
2836 | ||
2837 | /* Compute the the offset into the stack at which we | |
6d82d43b | 2838 | will copy the next parameter. |
cb3d25d1 MS |
2839 | |
2840 | In N32 (N64?), the stack_offset only needs to be | |
2841 | adjusted when it has been used. */ | |
2842 | ||
2843 | if (stack_used_p) | |
1a69e1e4 | 2844 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
2845 | } |
2846 | } | |
2847 | if (mips_debug) | |
2848 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
2849 | } | |
2850 | ||
f10683bb | 2851 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2852 | |
cb3d25d1 MS |
2853 | /* Return adjusted stack pointer. */ |
2854 | return sp; | |
2855 | } | |
2856 | ||
6d82d43b AC |
2857 | static enum return_value_convention |
2858 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
2859 | struct type *type, struct regcache *regcache, | |
47a35522 | 2860 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 2861 | { |
6d82d43b AC |
2862 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2863 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2864 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
2865 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 2866 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 2867 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
2868 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
2869 | && TYPE_LENGTH (type) == 16 | |
2870 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2871 | { | |
2872 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
2873 | two registers are used in the same as memory order, so the | |
2874 | eight bytes with the lower memory address are in $f0. */ | |
2875 | if (mips_debug) | |
2876 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
2877 | mips_xfer_register (regcache, | |
2878 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
2879 | 8, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
2880 | mips_xfer_register (regcache, | |
2881 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 2, | |
2882 | 8, TARGET_BYTE_ORDER, readbuf ? readbuf + 8 : readbuf, | |
2883 | writebuf ? writebuf + 8 : writebuf, 0); | |
2884 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2885 | } | |
6d82d43b AC |
2886 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
2887 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2888 | { | |
2889 | /* A floating-point value belongs in the least significant part | |
2890 | of FP0. */ | |
2891 | if (mips_debug) | |
2892 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
2893 | mips_xfer_register (regcache, | |
2894 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
2895 | TYPE_LENGTH (type), | |
2896 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
2897 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2898 | } | |
2899 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2900 | && TYPE_NFIELDS (type) <= 2 | |
2901 | && TYPE_NFIELDS (type) >= 1 | |
2902 | && ((TYPE_NFIELDS (type) == 1 | |
2903 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
2904 | == TYPE_CODE_FLT)) | |
2905 | || (TYPE_NFIELDS (type) == 2 | |
2906 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
2907 | == TYPE_CODE_FLT) | |
2908 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
2909 | == TYPE_CODE_FLT))) | |
2910 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2911 | { | |
2912 | /* A struct that contains one or two floats. Each value is part | |
2913 | in the least significant part of their floating point | |
2914 | register.. */ | |
6d82d43b AC |
2915 | int regnum; |
2916 | int field; | |
2917 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
2918 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
2919 | { | |
2920 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
2921 | / TARGET_CHAR_BIT); | |
2922 | if (mips_debug) | |
2923 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
2924 | offset); | |
2925 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
2926 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
2927 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
2928 | } | |
2929 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2930 | } | |
2931 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2932 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2933 | { | |
2934 | /* A structure or union. Extract the left justified value, | |
2935 | regardless of the byte order. I.e. DO NOT USE | |
2936 | mips_xfer_lower. */ | |
2937 | int offset; | |
2938 | int regnum; | |
4c7d22cb | 2939 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
2940 | offset < TYPE_LENGTH (type); |
2941 | offset += register_size (current_gdbarch, regnum), regnum++) | |
2942 | { | |
2943 | int xfer = register_size (current_gdbarch, regnum); | |
2944 | if (offset + xfer > TYPE_LENGTH (type)) | |
2945 | xfer = TYPE_LENGTH (type) - offset; | |
2946 | if (mips_debug) | |
2947 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
2948 | offset, xfer, regnum); | |
2949 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
2950 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
2951 | } | |
2952 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2953 | } | |
2954 | else | |
2955 | { | |
2956 | /* A scalar extract each part but least-significant-byte | |
2957 | justified. */ | |
2958 | int offset; | |
2959 | int regnum; | |
4c7d22cb | 2960 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
2961 | offset < TYPE_LENGTH (type); |
2962 | offset += register_size (current_gdbarch, regnum), regnum++) | |
2963 | { | |
2964 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
2965 | if (offset + xfer > TYPE_LENGTH (type)) |
2966 | xfer = TYPE_LENGTH (type) - offset; | |
2967 | if (mips_debug) | |
2968 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
2969 | offset, xfer, regnum); | |
2970 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
2971 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
2972 | } | |
2973 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2974 | } | |
2975 | } | |
2976 | ||
2977 | /* O32 ABI stuff. */ | |
2978 | ||
2979 | static CORE_ADDR | |
7d9b040b | 2980 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2981 | struct regcache *regcache, CORE_ADDR bp_addr, |
2982 | int nargs, struct value **args, CORE_ADDR sp, | |
2983 | int struct_return, CORE_ADDR struct_addr) | |
2984 | { | |
2985 | int argreg; | |
2986 | int float_argreg; | |
2987 | int argnum; | |
2988 | int len = 0; | |
2989 | int stack_offset = 0; | |
2990 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 2991 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
2992 | |
2993 | /* For shared libraries, "t9" needs to point at the function | |
2994 | address. */ | |
4c7d22cb | 2995 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
2996 | |
2997 | /* Set the return address register to point to the entry point of | |
2998 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2999 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3000 | |
3001 | /* First ensure that the stack and structure return address (if any) | |
3002 | are properly aligned. The stack has to be at least 64-bit | |
3003 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3004 | aligned. For n32 and n64, stack frames need to be 128-bit |
3005 | aligned, so we round to this widest known alignment. */ | |
3006 | ||
5b03f266 AC |
3007 | sp = align_down (sp, 16); |
3008 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3009 | |
3010 | /* Now make space on the stack for the args. */ | |
3011 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3012 | { |
3013 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3014 | int arglen = TYPE_LENGTH (arg_type); | |
3015 | ||
3016 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3017 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3018 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3019 | /* Allocate space on the stack. */ |
1a69e1e4 | 3020 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3021 | } |
5b03f266 | 3022 | sp -= align_up (len, 16); |
ebafbe83 MS |
3023 | |
3024 | if (mips_debug) | |
6d82d43b | 3025 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3026 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3027 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3028 | |
3029 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3030 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3031 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3032 | |
bcb0cc15 | 3033 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3034 | if (struct_return) |
3035 | { | |
3036 | if (mips_debug) | |
3037 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3038 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3039 | argreg, paddr_nz (struct_addr)); |
3040 | write_register (argreg++, struct_addr); | |
1a69e1e4 | 3041 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3042 | } |
3043 | ||
3044 | /* Now load as many as possible of the first arguments into | |
3045 | registers, and push the rest onto the stack. Loop thru args | |
3046 | from first to last. */ | |
3047 | for (argnum = 0; argnum < nargs; argnum++) | |
3048 | { | |
47a35522 | 3049 | const gdb_byte *val; |
ebafbe83 | 3050 | struct value *arg = args[argnum]; |
4991999e | 3051 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3052 | int len = TYPE_LENGTH (arg_type); |
3053 | enum type_code typecode = TYPE_CODE (arg_type); | |
3054 | ||
3055 | if (mips_debug) | |
3056 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3057 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3058 | argnum + 1, len, (int) typecode); |
3059 | ||
47a35522 | 3060 | val = value_contents (arg); |
46cac009 AC |
3061 | |
3062 | /* 32-bit ABIs always start floating point arguments in an | |
3063 | even-numbered floating point register. Round the FP register | |
3064 | up before the check to see if there are any FP registers | |
3065 | left. O32/O64 targets also pass the FP in the integer | |
3066 | registers so also round up normal registers. */ | |
2afd3f0a | 3067 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3068 | { |
3069 | if ((float_argreg & 1)) | |
3070 | float_argreg++; | |
3071 | } | |
3072 | ||
3073 | /* Floating point arguments passed in registers have to be | |
3074 | treated specially. On 32-bit architectures, doubles | |
3075 | are passed in register pairs; the even register gets | |
3076 | the low word, and the odd register gets the high word. | |
3077 | On O32/O64, the first two floating point arguments are | |
3078 | also copied to general registers, because MIPS16 functions | |
3079 | don't use float registers for arguments. This duplication of | |
3080 | arguments in general registers can't hurt non-MIPS16 functions | |
3081 | because those registers are normally skipped. */ | |
3082 | ||
3083 | if (fp_register_arg_p (typecode, arg_type) | |
3084 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3085 | { | |
8b07f6d8 | 3086 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 AC |
3087 | { |
3088 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3089 | unsigned long regval; | |
3090 | ||
3091 | /* Write the low word of the double to the even register(s). */ | |
3092 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3093 | if (mips_debug) | |
3094 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3095 | float_argreg, phex (regval, 4)); | |
3096 | write_register (float_argreg++, regval); | |
3097 | if (mips_debug) | |
3098 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3099 | argreg, phex (regval, 4)); | |
3100 | write_register (argreg++, regval); | |
3101 | ||
3102 | /* Write the high word of the double to the odd register(s). */ | |
3103 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3104 | if (mips_debug) | |
3105 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3106 | float_argreg, phex (regval, 4)); | |
3107 | write_register (float_argreg++, regval); | |
3108 | ||
3109 | if (mips_debug) | |
3110 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3111 | argreg, phex (regval, 4)); | |
3112 | write_register (argreg++, regval); | |
3113 | } | |
3114 | else | |
3115 | { | |
3116 | /* This is a floating point value that fits entirely | |
3117 | in a single register. */ | |
3118 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3119 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3120 | LONGEST regval = extract_unsigned_integer (val, len); |
3121 | if (mips_debug) | |
3122 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3123 | float_argreg, phex (regval, len)); | |
3124 | write_register (float_argreg++, regval); | |
3125 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3126 | registers for each argument. The below is (my |
3127 | guess) to ensure that the corresponding integer | |
3128 | register has reserved the same space. */ | |
46cac009 AC |
3129 | if (mips_debug) |
3130 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3131 | argreg, phex (regval, len)); | |
3132 | write_register (argreg, regval); | |
2afd3f0a | 3133 | argreg += 2; |
46cac009 AC |
3134 | } |
3135 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3136 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3137 | } |
3138 | else | |
3139 | { | |
3140 | /* Copy the argument to general registers or the stack in | |
3141 | register-sized pieces. Large arguments are split between | |
3142 | registers and stack. */ | |
1a69e1e4 DJ |
3143 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3144 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3145 | them in registers where gcc sometimes puts them on the |
3146 | stack. For maximum compatibility, we will put them in | |
3147 | both places. */ | |
1a69e1e4 DJ |
3148 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3149 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3150 | /* Structures should be aligned to eight bytes (even arg registers) |
3151 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3152 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3153 | { |
3154 | if ((argreg & 1)) | |
968b5391 MR |
3155 | { |
3156 | argreg++; | |
1a69e1e4 | 3157 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3158 | } |
46cac009 | 3159 | } |
46cac009 AC |
3160 | while (len > 0) |
3161 | { | |
3162 | /* Remember if the argument was written to the stack. */ | |
3163 | int stack_used_p = 0; | |
1a69e1e4 | 3164 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3165 | |
3166 | if (mips_debug) | |
3167 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3168 | partial_len); | |
3169 | ||
3170 | /* Write this portion of the argument to the stack. */ | |
3171 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3172 | || odd_sized_struct) |
46cac009 AC |
3173 | { |
3174 | /* Should shorter than int integer values be | |
3175 | promoted to int before being stored? */ | |
3176 | int longword_offset = 0; | |
3177 | CORE_ADDR addr; | |
3178 | stack_used_p = 1; | |
46cac009 AC |
3179 | |
3180 | if (mips_debug) | |
3181 | { | |
3182 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3183 | paddr_nz (stack_offset)); | |
3184 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3185 | paddr_nz (longword_offset)); | |
3186 | } | |
3187 | ||
3188 | addr = sp + stack_offset + longword_offset; | |
3189 | ||
3190 | if (mips_debug) | |
3191 | { | |
3192 | int i; | |
6d82d43b | 3193 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3194 | paddr_nz (addr)); |
3195 | for (i = 0; i < partial_len; i++) | |
3196 | { | |
6d82d43b | 3197 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3198 | val[i] & 0xff); |
3199 | } | |
3200 | } | |
3201 | write_memory (addr, val, partial_len); | |
3202 | } | |
3203 | ||
3204 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3205 | structs may go thru BOTH paths. */ |
46cac009 | 3206 | /* Write this portion of the argument to a general |
6d82d43b | 3207 | purpose register. */ |
968b5391 | 3208 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3209 | { |
3210 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3211 | /* Value may need to be sign extended, because |
1b13c4f6 | 3212 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3213 | |
3214 | /* A non-floating-point argument being passed in a | |
3215 | general register. If a struct or union, and if | |
3216 | the remaining length is smaller than the register | |
3217 | size, we have to adjust the register value on | |
3218 | big endian targets. | |
3219 | ||
3220 | It does not seem to be necessary to do the | |
3221 | same for integral types. | |
3222 | ||
3223 | Also don't do this adjustment on O64 binaries. | |
3224 | ||
3225 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3226 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3227 | mips_abi_regsize(), generates a left shift |
3228 | as part of storing the argument in a register | |
3229 | (the left shift isn't generated when | |
1b13c4f6 | 3230 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3231 | it is quite possible that this is GCC |
3232 | contradicting the LE/O32 ABI, GDB has not been | |
3233 | adjusted to accommodate this. Either someone | |
3234 | needs to demonstrate that the LE/O32 ABI | |
3235 | specifies such a left shift OR this new ABI gets | |
3236 | identified as such and GDB gets tweaked | |
3237 | accordingly. */ | |
3238 | ||
2afd3f0a | 3239 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
1a69e1e4 | 3240 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3241 | && (typecode == TYPE_CODE_STRUCT |
3242 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3243 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3244 | * TARGET_CHAR_BIT); |
46cac009 AC |
3245 | |
3246 | if (mips_debug) | |
3247 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3248 | argreg, | |
1a69e1e4 | 3249 | phex (regval, MIPS32_REGSIZE)); |
46cac009 AC |
3250 | write_register (argreg, regval); |
3251 | argreg++; | |
3252 | ||
3253 | /* Prevent subsequent floating point arguments from | |
3254 | being passed in floating point registers. */ | |
3255 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3256 | } | |
3257 | ||
3258 | len -= partial_len; | |
3259 | val += partial_len; | |
3260 | ||
3261 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3262 | will copy the next parameter. |
46cac009 | 3263 | |
6d82d43b AC |
3264 | In older ABIs, the caller reserved space for |
3265 | registers that contained arguments. This was loosely | |
3266 | refered to as their "home". Consequently, space is | |
3267 | always allocated. */ | |
46cac009 | 3268 | |
1a69e1e4 | 3269 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3270 | } |
3271 | } | |
3272 | if (mips_debug) | |
3273 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3274 | } | |
3275 | ||
f10683bb | 3276 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3277 | |
46cac009 AC |
3278 | /* Return adjusted stack pointer. */ |
3279 | return sp; | |
3280 | } | |
3281 | ||
6d82d43b AC |
3282 | static enum return_value_convention |
3283 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3284 | struct regcache *regcache, | |
47a35522 | 3285 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3286 | { |
3287 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3288 | ||
3289 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3290 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3291 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3292 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3293 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3294 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3295 | { | |
3296 | /* A single-precision floating-point value. It fits in the | |
3297 | least significant part of FP0. */ | |
3298 | if (mips_debug) | |
3299 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3300 | mips_xfer_register (regcache, | |
3301 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3302 | TYPE_LENGTH (type), | |
3303 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3304 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3305 | } | |
3306 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3307 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3308 | { | |
3309 | /* A double-precision floating-point value. The most | |
3310 | significant part goes in FP1, and the least significant in | |
3311 | FP0. */ | |
3312 | if (mips_debug) | |
3313 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3314 | switch (TARGET_BYTE_ORDER) | |
3315 | { | |
3316 | case BFD_ENDIAN_LITTLE: | |
3317 | mips_xfer_register (regcache, | |
3318 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3319 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3320 | mips_xfer_register (regcache, | |
3321 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3322 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3323 | break; | |
3324 | case BFD_ENDIAN_BIG: | |
3325 | mips_xfer_register (regcache, | |
3326 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3327 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3328 | mips_xfer_register (regcache, | |
3329 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3330 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3331 | break; | |
3332 | default: | |
e2e0b3e5 | 3333 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3334 | } |
3335 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3336 | } | |
3337 | #if 0 | |
3338 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3339 | && TYPE_NFIELDS (type) <= 2 | |
3340 | && TYPE_NFIELDS (type) >= 1 | |
3341 | && ((TYPE_NFIELDS (type) == 1 | |
3342 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3343 | == TYPE_CODE_FLT)) | |
3344 | || (TYPE_NFIELDS (type) == 2 | |
3345 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3346 | == TYPE_CODE_FLT) | |
3347 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3348 | == TYPE_CODE_FLT))) | |
3349 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3350 | { | |
3351 | /* A struct that contains one or two floats. Each value is part | |
3352 | in the least significant part of their floating point | |
3353 | register.. */ | |
870cd05e | 3354 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3355 | int regnum; |
3356 | int field; | |
3357 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3358 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3359 | { | |
3360 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3361 | / TARGET_CHAR_BIT); | |
3362 | if (mips_debug) | |
3363 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3364 | offset); | |
3365 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3366 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3367 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3368 | } | |
3369 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3370 | } | |
3371 | #endif | |
3372 | #if 0 | |
3373 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3374 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3375 | { | |
3376 | /* A structure or union. Extract the left justified value, | |
3377 | regardless of the byte order. I.e. DO NOT USE | |
3378 | mips_xfer_lower. */ | |
3379 | int offset; | |
3380 | int regnum; | |
4c7d22cb | 3381 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3382 | offset < TYPE_LENGTH (type); |
3383 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3384 | { | |
3385 | int xfer = register_size (current_gdbarch, regnum); | |
3386 | if (offset + xfer > TYPE_LENGTH (type)) | |
3387 | xfer = TYPE_LENGTH (type) - offset; | |
3388 | if (mips_debug) | |
3389 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3390 | offset, xfer, regnum); | |
3391 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3392 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3393 | } | |
3394 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3395 | } | |
3396 | #endif | |
3397 | else | |
3398 | { | |
3399 | /* A scalar extract each part but least-significant-byte | |
3400 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3401 | the ISA. */ |
6d82d43b AC |
3402 | int offset; |
3403 | int regnum; | |
4c7d22cb | 3404 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3405 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3406 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3407 | { |
1a69e1e4 | 3408 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3409 | if (offset + xfer > TYPE_LENGTH (type)) |
3410 | xfer = TYPE_LENGTH (type) - offset; | |
3411 | if (mips_debug) | |
3412 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3413 | offset, xfer, regnum); | |
3414 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3415 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3416 | } | |
3417 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3418 | } | |
3419 | } | |
3420 | ||
3421 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3422 | ABI. */ | |
46cac009 AC |
3423 | |
3424 | static CORE_ADDR | |
7d9b040b | 3425 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3426 | struct regcache *regcache, CORE_ADDR bp_addr, |
3427 | int nargs, | |
3428 | struct value **args, CORE_ADDR sp, | |
3429 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3430 | { |
3431 | int argreg; | |
3432 | int float_argreg; | |
3433 | int argnum; | |
3434 | int len = 0; | |
3435 | int stack_offset = 0; | |
480d3dd2 | 3436 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3437 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3438 | |
25ab4790 AC |
3439 | /* For shared libraries, "t9" needs to point at the function |
3440 | address. */ | |
4c7d22cb | 3441 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3442 | |
3443 | /* Set the return address register to point to the entry point of | |
3444 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3445 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3446 | |
46cac009 AC |
3447 | /* First ensure that the stack and structure return address (if any) |
3448 | are properly aligned. The stack has to be at least 64-bit | |
3449 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3450 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3451 | aligned, so we round to this widest known alignment. */ | |
3452 | ||
5b03f266 AC |
3453 | sp = align_down (sp, 16); |
3454 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3455 | |
3456 | /* Now make space on the stack for the args. */ | |
3457 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3458 | { |
3459 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3460 | int arglen = TYPE_LENGTH (arg_type); | |
3461 | ||
968b5391 | 3462 | /* Allocate space on the stack. */ |
1a69e1e4 | 3463 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3464 | } |
5b03f266 | 3465 | sp -= align_up (len, 16); |
46cac009 AC |
3466 | |
3467 | if (mips_debug) | |
6d82d43b | 3468 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3469 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3470 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3471 | |
3472 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3473 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3474 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3475 | |
3476 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3477 | if (struct_return) | |
3478 | { | |
3479 | if (mips_debug) | |
3480 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3481 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3482 | argreg, paddr_nz (struct_addr)); |
3483 | write_register (argreg++, struct_addr); | |
1a69e1e4 | 3484 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3485 | } |
3486 | ||
3487 | /* Now load as many as possible of the first arguments into | |
3488 | registers, and push the rest onto the stack. Loop thru args | |
3489 | from first to last. */ | |
3490 | for (argnum = 0; argnum < nargs; argnum++) | |
3491 | { | |
47a35522 | 3492 | const gdb_byte *val; |
46cac009 | 3493 | struct value *arg = args[argnum]; |
4991999e | 3494 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3495 | int len = TYPE_LENGTH (arg_type); |
3496 | enum type_code typecode = TYPE_CODE (arg_type); | |
3497 | ||
3498 | if (mips_debug) | |
3499 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3500 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3501 | argnum + 1, len, (int) typecode); |
3502 | ||
47a35522 | 3503 | val = value_contents (arg); |
ebafbe83 | 3504 | |
ebafbe83 MS |
3505 | /* Floating point arguments passed in registers have to be |
3506 | treated specially. On 32-bit architectures, doubles | |
3507 | are passed in register pairs; the even register gets | |
3508 | the low word, and the odd register gets the high word. | |
3509 | On O32/O64, the first two floating point arguments are | |
3510 | also copied to general registers, because MIPS16 functions | |
3511 | don't use float registers for arguments. This duplication of | |
3512 | arguments in general registers can't hurt non-MIPS16 functions | |
3513 | because those registers are normally skipped. */ | |
3514 | ||
3515 | if (fp_register_arg_p (typecode, arg_type) | |
3516 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3517 | { | |
2afd3f0a MR |
3518 | LONGEST regval = extract_unsigned_integer (val, len); |
3519 | if (mips_debug) | |
3520 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3521 | float_argreg, phex (regval, len)); | |
3522 | write_register (float_argreg++, regval); | |
3523 | if (mips_debug) | |
3524 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3525 | argreg, phex (regval, len)); | |
3526 | write_register (argreg, regval); | |
3527 | argreg++; | |
ebafbe83 | 3528 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3529 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3530 | } |
3531 | else | |
3532 | { | |
3533 | /* Copy the argument to general registers or the stack in | |
3534 | register-sized pieces. Large arguments are split between | |
3535 | registers and stack. */ | |
1a69e1e4 | 3536 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3537 | are treated specially: Irix cc passes them in registers |
3538 | where gcc sometimes puts them on the stack. For maximum | |
3539 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3540 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3541 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3542 | while (len > 0) |
3543 | { | |
3544 | /* Remember if the argument was written to the stack. */ | |
3545 | int stack_used_p = 0; | |
1a69e1e4 | 3546 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3547 | |
3548 | if (mips_debug) | |
3549 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3550 | partial_len); | |
3551 | ||
3552 | /* Write this portion of the argument to the stack. */ | |
3553 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3554 | || odd_sized_struct) |
ebafbe83 MS |
3555 | { |
3556 | /* Should shorter than int integer values be | |
3557 | promoted to int before being stored? */ | |
3558 | int longword_offset = 0; | |
3559 | CORE_ADDR addr; | |
3560 | stack_used_p = 1; | |
3561 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3562 | { | |
1a69e1e4 DJ |
3563 | if ((typecode == TYPE_CODE_INT |
3564 | || typecode == TYPE_CODE_PTR | |
3565 | || typecode == TYPE_CODE_FLT) | |
3566 | && len <= 4) | |
3567 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3568 | } |
3569 | ||
3570 | if (mips_debug) | |
3571 | { | |
3572 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3573 | paddr_nz (stack_offset)); | |
3574 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3575 | paddr_nz (longword_offset)); | |
3576 | } | |
3577 | ||
3578 | addr = sp + stack_offset + longword_offset; | |
3579 | ||
3580 | if (mips_debug) | |
3581 | { | |
3582 | int i; | |
6d82d43b | 3583 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3584 | paddr_nz (addr)); |
3585 | for (i = 0; i < partial_len; i++) | |
3586 | { | |
6d82d43b | 3587 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3588 | val[i] & 0xff); |
3589 | } | |
3590 | } | |
3591 | write_memory (addr, val, partial_len); | |
3592 | } | |
3593 | ||
3594 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3595 | structs may go thru BOTH paths. */ |
ebafbe83 | 3596 | /* Write this portion of the argument to a general |
6d82d43b | 3597 | purpose register. */ |
968b5391 | 3598 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3599 | { |
3600 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3601 | /* Value may need to be sign extended, because |
1b13c4f6 | 3602 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3603 | |
3604 | /* A non-floating-point argument being passed in a | |
3605 | general register. If a struct or union, and if | |
3606 | the remaining length is smaller than the register | |
3607 | size, we have to adjust the register value on | |
3608 | big endian targets. | |
3609 | ||
3610 | It does not seem to be necessary to do the | |
401835eb | 3611 | same for integral types. */ |
480d3dd2 | 3612 | |
401835eb | 3613 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
1a69e1e4 | 3614 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3615 | && (typecode == TYPE_CODE_STRUCT |
3616 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3617 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3618 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3619 | |
3620 | if (mips_debug) | |
3621 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3622 | argreg, | |
1a69e1e4 | 3623 | phex (regval, MIPS64_REGSIZE)); |
ebafbe83 MS |
3624 | write_register (argreg, regval); |
3625 | argreg++; | |
3626 | ||
3627 | /* Prevent subsequent floating point arguments from | |
3628 | being passed in floating point registers. */ | |
3629 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3630 | } | |
3631 | ||
3632 | len -= partial_len; | |
3633 | val += partial_len; | |
3634 | ||
3635 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3636 | will copy the next parameter. |
ebafbe83 | 3637 | |
6d82d43b AC |
3638 | In older ABIs, the caller reserved space for |
3639 | registers that contained arguments. This was loosely | |
3640 | refered to as their "home". Consequently, space is | |
3641 | always allocated. */ | |
ebafbe83 | 3642 | |
1a69e1e4 | 3643 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3644 | } |
3645 | } | |
3646 | if (mips_debug) | |
3647 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3648 | } | |
3649 | ||
f10683bb | 3650 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3651 | |
ebafbe83 MS |
3652 | /* Return adjusted stack pointer. */ |
3653 | return sp; | |
3654 | } | |
3655 | ||
9c8fdbfa AC |
3656 | static enum return_value_convention |
3657 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3658 | struct type *type, struct regcache *regcache, | |
47a35522 | 3659 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3660 | { |
7a076fd2 FF |
3661 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3662 | ||
3663 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3664 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3665 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3666 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3667 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3668 | { | |
3669 | /* A floating-point value. It fits in the least significant | |
3670 | part of FP0. */ | |
3671 | if (mips_debug) | |
3672 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3673 | mips_xfer_register (regcache, | |
3674 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3675 | TYPE_LENGTH (type), | |
3676 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3677 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3678 | } | |
3679 | else | |
3680 | { | |
3681 | /* A scalar extract each part but least-significant-byte | |
3682 | justified. */ | |
3683 | int offset; | |
3684 | int regnum; | |
3685 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3686 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3687 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3688 | { |
1a69e1e4 | 3689 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3690 | if (offset + xfer > TYPE_LENGTH (type)) |
3691 | xfer = TYPE_LENGTH (type) - offset; | |
3692 | if (mips_debug) | |
3693 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3694 | offset, xfer, regnum); | |
3695 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3696 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3697 | } | |
3698 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3699 | } | |
6d82d43b AC |
3700 | } |
3701 | ||
dd824b04 DJ |
3702 | /* Floating point register management. |
3703 | ||
3704 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3705 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3706 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3707 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3708 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3709 | double precision floats into two 32-bit chunks and store them in | |
3710 | consecutive fp regs. To display 64-bit floats stored in this | |
3711 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3712 | Throw in user-configurable endianness and you have a real mess. | |
3713 | ||
3714 | The way this works is: | |
3715 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3716 | double-precision value will be split across two logical registers. | |
3717 | The lower-numbered logical register will hold the low-order bits, | |
3718 | regardless of the processor's endianness. | |
3719 | - If we are on a 64-bit processor, and we are looking for a | |
3720 | single-precision value, it will be in the low ordered bits | |
3721 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3722 | save slot in memory. | |
3723 | - If we are in 64-bit mode, everything is straightforward. | |
3724 | ||
3725 | Note that this code only deals with "live" registers at the top of the | |
3726 | stack. We will attempt to deal with saved registers later, when | |
3727 | the raw/cooked register interface is in place. (We need a general | |
3728 | interface that can deal with dynamic saved register sizes -- fp | |
3729 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3730 | and below). */ | |
3731 | ||
67b2c998 DJ |
3732 | static struct type * |
3733 | mips_float_register_type (void) | |
3734 | { | |
8da61cc4 | 3735 | return builtin_type_ieee_single; |
67b2c998 DJ |
3736 | } |
3737 | ||
3738 | static struct type * | |
3739 | mips_double_register_type (void) | |
3740 | { | |
8da61cc4 | 3741 | return builtin_type_ieee_double; |
67b2c998 DJ |
3742 | } |
3743 | ||
dd824b04 DJ |
3744 | /* Copy a 32-bit single-precision value from the current frame |
3745 | into rare_buffer. */ | |
3746 | ||
3747 | static void | |
e11c53d2 | 3748 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 3749 | gdb_byte *rare_buffer) |
dd824b04 | 3750 | { |
719ec221 | 3751 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 3752 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 3753 | |
e11c53d2 | 3754 | if (!frame_register_read (frame, regno, raw_buffer)) |
8a3fe4f8 | 3755 | error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno)); |
dd824b04 DJ |
3756 | if (raw_size == 8) |
3757 | { | |
3758 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3759 | 32 bits. */ |
dd824b04 DJ |
3760 | int offset; |
3761 | ||
3762 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3763 | offset = 4; | |
3764 | else | |
3765 | offset = 0; | |
3766 | ||
3767 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3768 | } | |
3769 | else | |
3770 | { | |
3771 | memcpy (rare_buffer, raw_buffer, 4); | |
3772 | } | |
3773 | } | |
3774 | ||
3775 | /* Copy a 64-bit double-precision value from the current frame into | |
3776 | rare_buffer. This may include getting half of it from the next | |
3777 | register. */ | |
3778 | ||
3779 | static void | |
e11c53d2 | 3780 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 3781 | gdb_byte *rare_buffer) |
dd824b04 | 3782 | { |
719ec221 | 3783 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3784 | |
3785 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3786 | { | |
3787 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 3788 | all 64 bits. */ |
e11c53d2 | 3789 | if (!frame_register_read (frame, regno, rare_buffer)) |
8a3fe4f8 | 3790 | error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno)); |
dd824b04 DJ |
3791 | } |
3792 | else | |
3793 | { | |
56cea623 | 3794 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 | 3795 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
3796 | _("mips_read_fp_register_double: bad access to " |
3797 | "odd-numbered FP register")); | |
dd824b04 DJ |
3798 | |
3799 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 3800 | each register. */ |
dd824b04 DJ |
3801 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3802 | { | |
e11c53d2 AC |
3803 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3804 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3805 | } |
361d1df0 | 3806 | else |
dd824b04 | 3807 | { |
e11c53d2 AC |
3808 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3809 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
3810 | } |
3811 | } | |
3812 | } | |
3813 | ||
c906108c | 3814 | static void |
e11c53d2 AC |
3815 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
3816 | int regnum) | |
c5aa993b | 3817 | { /* do values for FP (float) regs */ |
47a35522 | 3818 | gdb_byte *raw_buffer; |
3903d437 AC |
3819 | double doub, flt1; /* doubles extracted from raw hex data */ |
3820 | int inv1, inv2; | |
c5aa993b | 3821 | |
47a35522 MK |
3822 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
3823 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 3824 | |
e11c53d2 AC |
3825 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
3826 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
3827 | ""); | |
f0ef6b29 | 3828 | |
719ec221 | 3829 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 3830 | { |
f0ef6b29 KB |
3831 | /* 4-byte registers: Print hex and floating. Also print even |
3832 | numbered registers as doubles. */ | |
e11c53d2 | 3833 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 3834 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 3835 | |
6d82d43b AC |
3836 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
3837 | file); | |
dd824b04 | 3838 | |
e11c53d2 | 3839 | fprintf_filtered (file, " flt: "); |
1adad886 | 3840 | if (inv1) |
e11c53d2 | 3841 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 3842 | else |
e11c53d2 | 3843 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 3844 | |
f0ef6b29 KB |
3845 | if (regnum % 2 == 0) |
3846 | { | |
e11c53d2 | 3847 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 3848 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 3849 | &inv2); |
1adad886 | 3850 | |
e11c53d2 | 3851 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 3852 | if (inv2) |
e11c53d2 | 3853 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 3854 | else |
e11c53d2 | 3855 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 3856 | } |
c906108c SS |
3857 | } |
3858 | else | |
dd824b04 | 3859 | { |
f0ef6b29 | 3860 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 3861 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 3862 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 3863 | |
e11c53d2 | 3864 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
3865 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
3866 | ||
361d1df0 | 3867 | |
6d82d43b AC |
3868 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
3869 | file); | |
f0ef6b29 | 3870 | |
e11c53d2 | 3871 | fprintf_filtered (file, " flt: "); |
1adad886 | 3872 | if (inv1) |
e11c53d2 | 3873 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 3874 | else |
e11c53d2 | 3875 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 3876 | |
e11c53d2 | 3877 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 3878 | if (inv2) |
e11c53d2 | 3879 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 3880 | else |
e11c53d2 | 3881 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
3882 | } |
3883 | } | |
3884 | ||
3885 | static void | |
e11c53d2 AC |
3886 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
3887 | int regnum, int all) | |
f0ef6b29 | 3888 | { |
a4b8ebc8 | 3889 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 3890 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 3891 | int offset; |
1adad886 | 3892 | |
7b9ee6a8 | 3893 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 3894 | { |
e11c53d2 | 3895 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
3896 | return; |
3897 | } | |
3898 | ||
3899 | /* Get the data in raw format. */ | |
e11c53d2 | 3900 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 3901 | { |
e11c53d2 | 3902 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 3903 | return; |
c906108c | 3904 | } |
f0ef6b29 | 3905 | |
e11c53d2 | 3906 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
3907 | |
3908 | /* The problem with printing numeric register names (r26, etc.) is that | |
3909 | the user can't use them on input. Probably the best solution is to | |
3910 | fix it so that either the numeric or the funky (a2, etc.) names | |
3911 | are accepted on input. */ | |
3912 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 3913 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 3914 | else |
e11c53d2 | 3915 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
3916 | |
3917 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
3918 | offset = |
3919 | register_size (current_gdbarch, | |
3920 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
3921 | else |
3922 | offset = 0; | |
3923 | ||
6d82d43b | 3924 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 3925 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 3926 | file); |
c906108c SS |
3927 | } |
3928 | ||
f0ef6b29 KB |
3929 | /* Replacement for generic do_registers_info. |
3930 | Print regs in pretty columns. */ | |
3931 | ||
3932 | static int | |
e11c53d2 AC |
3933 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
3934 | int regnum) | |
f0ef6b29 | 3935 | { |
e11c53d2 AC |
3936 | fprintf_filtered (file, " "); |
3937 | mips_print_fp_register (file, frame, regnum); | |
3938 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
3939 | return regnum + 1; |
3940 | } | |
3941 | ||
3942 | ||
c906108c SS |
3943 | /* Print a row's worth of GP (int) registers, with name labels above */ |
3944 | ||
3945 | static int | |
e11c53d2 | 3946 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 3947 | int start_regnum) |
c906108c | 3948 | { |
a4b8ebc8 | 3949 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 3950 | /* do values for GP (int) regs */ |
47a35522 | 3951 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 3952 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 3953 | int col, byte; |
a4b8ebc8 | 3954 | int regnum; |
c906108c SS |
3955 | |
3956 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 3957 | for (col = 0, regnum = start_regnum; |
6d82d43b | 3958 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
3959 | { |
3960 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 3961 | continue; /* unused register */ |
7b9ee6a8 | 3962 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 3963 | TYPE_CODE_FLT) |
c5aa993b | 3964 | break; /* end the row: reached FP register */ |
d05f6826 DJ |
3965 | if (col == 0) |
3966 | fprintf_filtered (file, " "); | |
6d82d43b | 3967 | fprintf_filtered (file, |
d5ac5a39 | 3968 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 3969 | REGISTER_NAME (regnum)); |
c906108c SS |
3970 | col++; |
3971 | } | |
d05f6826 DJ |
3972 | |
3973 | if (col == 0) | |
3974 | return regnum; | |
3975 | ||
a4b8ebc8 | 3976 | /* print the R0 to R31 names */ |
20e6603c AC |
3977 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
3978 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
3979 | else | |
3980 | fprintf_filtered (file, "\n "); | |
c906108c | 3981 | |
c906108c | 3982 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 3983 | for (col = 0, regnum = start_regnum; |
6d82d43b | 3984 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
3985 | { |
3986 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 3987 | continue; /* unused register */ |
7b9ee6a8 | 3988 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 3989 | TYPE_CODE_FLT) |
c5aa993b | 3990 | break; /* end row: reached FP register */ |
c906108c | 3991 | /* OK: get the data in raw format. */ |
e11c53d2 | 3992 | if (!frame_register_read (frame, regnum, raw_buffer)) |
8a3fe4f8 | 3993 | error (_("can't read register %d (%s)"), regnum, REGISTER_NAME (regnum)); |
c906108c | 3994 | /* pad small registers */ |
4246e332 | 3995 | for (byte = 0; |
d5ac5a39 | 3996 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 3997 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
3998 | printf_filtered (" "); |
3999 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4000 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4001 | for (byte = |
4002 | register_size (current_gdbarch, | |
4003 | regnum) - register_size (current_gdbarch, regnum); | |
4004 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4005 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4006 | else |
c73e8f27 | 4007 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4008 | byte >= 0; byte--) |
47a35522 | 4009 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4010 | fprintf_filtered (file, " "); |
c906108c SS |
4011 | col++; |
4012 | } | |
c5aa993b | 4013 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4014 | fprintf_filtered (file, "\n"); |
c906108c SS |
4015 | |
4016 | return regnum; | |
4017 | } | |
4018 | ||
4019 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4020 | ||
bf1f5b4c | 4021 | static void |
e11c53d2 AC |
4022 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4023 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4024 | { |
c5aa993b | 4025 | if (regnum != -1) /* do one specified register */ |
c906108c | 4026 | { |
a4b8ebc8 | 4027 | gdb_assert (regnum >= NUM_REGS); |
c906108c | 4028 | if (*(REGISTER_NAME (regnum)) == '\0') |
8a3fe4f8 | 4029 | error (_("Not a valid register for the current processor type")); |
c906108c | 4030 | |
e11c53d2 AC |
4031 | mips_print_register (file, frame, regnum, 0); |
4032 | fprintf_filtered (file, "\n"); | |
c906108c | 4033 | } |
c5aa993b JM |
4034 | else |
4035 | /* do all (or most) registers */ | |
c906108c | 4036 | { |
a4b8ebc8 AC |
4037 | regnum = NUM_REGS; |
4038 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4039 | { |
7b9ee6a8 | 4040 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4041 | TYPE_CODE_FLT) |
e11c53d2 AC |
4042 | { |
4043 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4044 | regnum = print_fp_register_row (file, frame, regnum); | |
4045 | else | |
4046 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4047 | } | |
c906108c | 4048 | else |
e11c53d2 | 4049 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4050 | } |
4051 | } | |
4052 | } | |
4053 | ||
c906108c SS |
4054 | /* Is this a branch with a delay slot? */ |
4055 | ||
c906108c | 4056 | static int |
acdb74a0 | 4057 | is_delayed (unsigned long insn) |
c906108c SS |
4058 | { |
4059 | int i; | |
4060 | for (i = 0; i < NUMOPCODES; ++i) | |
4061 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4062 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4063 | break; | |
4064 | return (i < NUMOPCODES | |
4065 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4066 | | INSN_COND_BRANCH_DELAY | |
4067 | | INSN_COND_BRANCH_LIKELY))); | |
4068 | } | |
4069 | ||
4070 | int | |
3352ef37 AC |
4071 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4072 | struct frame_info *frame) | |
c906108c | 4073 | { |
3352ef37 | 4074 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4075 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4076 | |
4077 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4078 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4079 | return 0; |
4080 | ||
06648491 MK |
4081 | if (!breakpoint_here_p (pc + 4)) |
4082 | return 0; | |
4083 | ||
3352ef37 AC |
4084 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4085 | /* If error reading memory, guess that it is not a delayed | |
4086 | branch. */ | |
c906108c | 4087 | return 0; |
4c7d22cb | 4088 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4089 | } |
4090 | ||
6d82d43b AC |
4091 | /* To skip prologues, I use this predicate. Returns either PC itself |
4092 | if the code at PC does not look like a function prologue; otherwise | |
4093 | returns an address that (if we're lucky) follows the prologue. If | |
4094 | LENIENT, then we must skip everything which is involved in setting | |
4095 | up the frame (it's OK to skip more, just so long as we don't skip | |
4096 | anything which might clobber the registers which are being saved. | |
4097 | We must skip more in the case where part of the prologue is in the | |
4098 | delay slot of a non-prologue instruction). */ | |
4099 | ||
4100 | static CORE_ADDR | |
4101 | mips_skip_prologue (CORE_ADDR pc) | |
4102 | { | |
8b622e6a AC |
4103 | CORE_ADDR limit_pc; |
4104 | CORE_ADDR func_addr; | |
4105 | ||
6d82d43b AC |
4106 | /* See if we can determine the end of the prologue via the symbol table. |
4107 | If so, then return either PC, or the PC after the prologue, whichever | |
4108 | is greater. */ | |
8b622e6a AC |
4109 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4110 | { | |
4111 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4112 | if (post_prologue_pc != 0) | |
4113 | return max (pc, post_prologue_pc); | |
4114 | } | |
6d82d43b AC |
4115 | |
4116 | /* Can't determine prologue from the symbol table, need to examine | |
4117 | instructions. */ | |
4118 | ||
98b4dd94 JB |
4119 | /* Find an upper limit on the function prologue using the debug |
4120 | information. If the debug information could not be used to provide | |
4121 | that bound, then use an arbitrary large number as the upper bound. */ | |
4122 | limit_pc = skip_prologue_using_sal (pc); | |
4123 | if (limit_pc == 0) | |
4124 | limit_pc = pc + 100; /* Magic. */ | |
4125 | ||
0fe7e7c8 | 4126 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4127 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4128 | else |
a65bbe44 | 4129 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4130 | } |
4131 | ||
a5ea2558 AC |
4132 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4133 | used for all MIPS-specific commands. */ | |
4134 | ||
a5ea2558 | 4135 | static void |
acdb74a0 | 4136 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4137 | { |
4138 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4139 | } | |
4140 | ||
a5ea2558 | 4141 | static void |
acdb74a0 | 4142 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4143 | { |
6d82d43b AC |
4144 | printf_unfiltered |
4145 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4146 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4147 | } | |
4148 | ||
c906108c SS |
4149 | /* Commands to show/set the MIPS FPU type. */ |
4150 | ||
c906108c | 4151 | static void |
acdb74a0 | 4152 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4153 | { |
c906108c SS |
4154 | char *fpu; |
4155 | switch (MIPS_FPU_TYPE) | |
4156 | { | |
4157 | case MIPS_FPU_SINGLE: | |
4158 | fpu = "single-precision"; | |
4159 | break; | |
4160 | case MIPS_FPU_DOUBLE: | |
4161 | fpu = "double-precision"; | |
4162 | break; | |
4163 | case MIPS_FPU_NONE: | |
4164 | fpu = "absent (none)"; | |
4165 | break; | |
93d56215 | 4166 | default: |
e2e0b3e5 | 4167 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4168 | } |
4169 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4170 | printf_unfiltered |
4171 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4172 | fpu); | |
c906108c | 4173 | else |
6d82d43b AC |
4174 | printf_unfiltered |
4175 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4176 | } |
4177 | ||
4178 | ||
c906108c | 4179 | static void |
acdb74a0 | 4180 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4181 | { |
6d82d43b AC |
4182 | printf_unfiltered |
4183 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4184 | show_mipsfpu_command (args, from_tty); |
4185 | } | |
4186 | ||
c906108c | 4187 | static void |
acdb74a0 | 4188 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4189 | { |
8d5838b5 AC |
4190 | struct gdbarch_info info; |
4191 | gdbarch_info_init (&info); | |
c906108c SS |
4192 | mips_fpu_type = MIPS_FPU_SINGLE; |
4193 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4194 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4195 | instead of relying on globals. Doing that would let generic code | |
4196 | handle the search for this specific architecture. */ | |
4197 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4198 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4199 | } |
4200 | ||
c906108c | 4201 | static void |
acdb74a0 | 4202 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4203 | { |
8d5838b5 AC |
4204 | struct gdbarch_info info; |
4205 | gdbarch_info_init (&info); | |
c906108c SS |
4206 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4207 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4208 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4209 | instead of relying on globals. Doing that would let generic code | |
4210 | handle the search for this specific architecture. */ | |
4211 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4212 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4213 | } |
4214 | ||
c906108c | 4215 | static void |
acdb74a0 | 4216 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4217 | { |
8d5838b5 AC |
4218 | struct gdbarch_info info; |
4219 | gdbarch_info_init (&info); | |
c906108c SS |
4220 | mips_fpu_type = MIPS_FPU_NONE; |
4221 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4222 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4223 | instead of relying on globals. Doing that would let generic code | |
4224 | handle the search for this specific architecture. */ | |
4225 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4226 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4227 | } |
4228 | ||
c906108c | 4229 | static void |
acdb74a0 | 4230 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4231 | { |
4232 | mips_fpu_type_auto = 1; | |
4233 | } | |
4234 | ||
c906108c | 4235 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4236 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4237 | the relevant processor still exists (it dates back to '94) and | |
4238 | secondly this is not the way to do this. The processor type should | |
4239 | be set by forcing an architecture change. */ | |
c906108c | 4240 | |
691c0433 AC |
4241 | void |
4242 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4243 | { |
691c0433 | 4244 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4245 | CORE_ADDR prid; |
4246 | ||
a5c9623c | 4247 | prid = read_register (MIPS_PRID_REGNUM); |
c906108c SS |
4248 | |
4249 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4250 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4251 | } |
4252 | ||
4253 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4254 | callable as an sfunc. */ | |
4255 | ||
4256 | static void | |
acdb74a0 AC |
4257 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4258 | struct cmd_list_element *c) | |
c906108c SS |
4259 | { |
4260 | reinit_frame_cache (); | |
4261 | } | |
4262 | ||
a89aa300 AC |
4263 | static int |
4264 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4265 | { |
e5ab0dce | 4266 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4267 | |
d31431ed AC |
4268 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4269 | disassembler needs to be able to locally determine the ISA, and | |
4270 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4271 | work. */ | |
ec4045ea AC |
4272 | if (mips_pc_is_mips16 (memaddr)) |
4273 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4274 | |
4275 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4276 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4277 | |
e5ab0dce | 4278 | /* Set the disassembler options. */ |
6d82d43b | 4279 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4280 | { |
4281 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4282 | register names from libopcodes. */ |
e5ab0dce AC |
4283 | if (tdep->mips_abi == MIPS_ABI_N32) |
4284 | info->disassembler_options = "gpr-names=n32"; | |
4285 | else | |
4286 | info->disassembler_options = "gpr-names=64"; | |
4287 | info->flavour = bfd_target_elf_flavour; | |
4288 | } | |
4289 | else | |
4290 | /* This string is not recognized explicitly by the disassembler, | |
4291 | but it tells the disassembler to not try to guess the ABI from | |
4292 | the bfd elf headers, such that, if the user overrides the ABI | |
4293 | of a program linked as NewABI, the disassembly will follow the | |
4294 | register naming conventions specified by the user. */ | |
4295 | info->disassembler_options = "gpr-names=32"; | |
4296 | ||
c906108c | 4297 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 4298 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4299 | return print_insn_big_mips (memaddr, info); |
4300 | else | |
4301 | return print_insn_little_mips (memaddr, info); | |
4302 | } | |
4303 | ||
c906108c SS |
4304 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
4305 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
4306 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
4307 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
4308 | (if necessary) to point to the actual memory location where the | |
4309 | breakpoint should be inserted. */ | |
4310 | ||
47a35522 | 4311 | static const gdb_byte * |
6d82d43b | 4312 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4313 | { |
d7449b42 | 4314 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c | 4315 | { |
0fe7e7c8 | 4316 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4317 | { |
47a35522 | 4318 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4319 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4320 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4321 | return mips16_big_breakpoint; |
4322 | } | |
4323 | else | |
4324 | { | |
aaab4dba AC |
4325 | /* The IDT board uses an unusual breakpoint value, and |
4326 | sometimes gets confused when it sees the usual MIPS | |
4327 | breakpoint instruction. */ | |
47a35522 MK |
4328 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4329 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4330 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4331 | |
c5aa993b | 4332 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4333 | |
4334 | if (strcmp (target_shortname, "mips") == 0) | |
4335 | return idt_big_breakpoint; | |
4336 | else if (strcmp (target_shortname, "ddb") == 0 | |
4337 | || strcmp (target_shortname, "pmon") == 0 | |
4338 | || strcmp (target_shortname, "lsi") == 0) | |
4339 | return pmon_big_breakpoint; | |
4340 | else | |
4341 | return big_breakpoint; | |
4342 | } | |
4343 | } | |
4344 | else | |
4345 | { | |
0fe7e7c8 | 4346 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4347 | { |
47a35522 | 4348 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4349 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4350 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4351 | return mips16_little_breakpoint; |
4352 | } | |
4353 | else | |
4354 | { | |
47a35522 MK |
4355 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4356 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4357 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4358 | |
c5aa993b | 4359 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4360 | |
4361 | if (strcmp (target_shortname, "mips") == 0) | |
4362 | return idt_little_breakpoint; | |
4363 | else if (strcmp (target_shortname, "ddb") == 0 | |
4364 | || strcmp (target_shortname, "pmon") == 0 | |
4365 | || strcmp (target_shortname, "lsi") == 0) | |
4366 | return pmon_little_breakpoint; | |
4367 | else | |
4368 | return little_breakpoint; | |
4369 | } | |
4370 | } | |
4371 | } | |
4372 | ||
4373 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4374 | PC, which is either the callee or the caller. There are several | |
4375 | cases which must be handled: | |
4376 | ||
4377 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4378 | target PC is in $31 ($ra). |
c906108c | 4379 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4380 | and the target PC is in $2. |
c906108c | 4381 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4382 | before the jal instruction, this is effectively a call stub |
4383 | and the the target PC is in $2. Otherwise this is effectively | |
4384 | a return stub and the target PC is in $18. | |
c906108c SS |
4385 | |
4386 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4387 | gory details. */ |
c906108c | 4388 | |
757a7cc6 | 4389 | static CORE_ADDR |
e7d6a6d2 | 4390 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
4391 | { |
4392 | char *name; | |
4393 | CORE_ADDR start_addr; | |
4394 | ||
4395 | /* Find the starting address and name of the function containing the PC. */ | |
4396 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4397 | return 0; | |
4398 | ||
4399 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4400 | target PC is in $31 ($ra). */ | |
4401 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4402 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 4403 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
4404 | |
4405 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4406 | { | |
4407 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4408 | and the target PC is in $2. */ | |
4409 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4410 | return read_signed_register (2); |
c906108c SS |
4411 | |
4412 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4413 | before the jal instruction, this is effectively a call stub |
4414 | and the the target PC is in $2. Otherwise this is effectively | |
4415 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4416 | else if (name[19] == 's' || name[19] == 'd') |
4417 | { | |
4418 | if (pc == start_addr) | |
4419 | { | |
4420 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4421 | stub. Such a stub for a function bar might have a name |
4422 | like __fn_stub_bar, and might look like this: | |
4423 | mfc1 $4,$f13 | |
4424 | mfc1 $5,$f12 | |
4425 | mfc1 $6,$f15 | |
4426 | mfc1 $7,$f14 | |
4427 | la $1,bar (becomes a lui/addiu pair) | |
4428 | jr $1 | |
4429 | So scan down to the lui/addi and extract the target | |
4430 | address from those two instructions. */ | |
c906108c | 4431 | |
6c997a34 | 4432 | CORE_ADDR target_pc = read_signed_register (2); |
d37cca3d | 4433 | ULONGEST inst; |
c906108c SS |
4434 | int i; |
4435 | ||
4436 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4437 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4438 | 0) | |
c906108c SS |
4439 | return target_pc; |
4440 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4441 | && strcmp (name, "etext") != 0 | |
4442 | && strcmp (name, "_etext") != 0) | |
4443 | return target_pc; | |
4444 | ||
4445 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4446 | The limit on the search is arbitrarily set to 20 |
4447 | instructions. FIXME. */ | |
95ac2dcf | 4448 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4449 | { |
c5aa993b JM |
4450 | inst = mips_fetch_instruction (target_pc); |
4451 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4452 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4453 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4454 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4455 | } |
4456 | ||
4457 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4458 | return target_pc; | |
4459 | } | |
4460 | else | |
4461 | /* This is the 'return' part of a call stub. The return | |
4462 | address is in $r18. */ | |
6c997a34 | 4463 | return read_signed_register (18); |
c906108c SS |
4464 | } |
4465 | } | |
c5aa993b | 4466 | return 0; /* not a stub */ |
c906108c SS |
4467 | } |
4468 | ||
a4b8ebc8 AC |
4469 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
4470 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
4471 | |
4472 | static int | |
4473 | mips_stab_reg_to_regnum (int num) | |
4474 | { | |
a4b8ebc8 | 4475 | int regnum; |
2f38ef89 | 4476 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4477 | regnum = num; |
2f38ef89 | 4478 | else if (num >= 38 && num < 70) |
56cea623 | 4479 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4480 | else if (num == 70) |
56cea623 | 4481 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4482 | else if (num == 71) |
56cea623 | 4483 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4484 | else |
a4b8ebc8 AC |
4485 | /* This will hopefully (eventually) provoke a warning. Should |
4486 | we be calling complaint() here? */ | |
4487 | return NUM_REGS + NUM_PSEUDO_REGS; | |
4488 | return NUM_REGS + regnum; | |
88c72b7d AC |
4489 | } |
4490 | ||
2f38ef89 | 4491 | |
a4b8ebc8 AC |
4492 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
4493 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
4494 | |
4495 | static int | |
2f38ef89 | 4496 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4497 | { |
a4b8ebc8 | 4498 | int regnum; |
2f38ef89 | 4499 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4500 | regnum = num; |
2f38ef89 | 4501 | else if (num >= 32 && num < 64) |
56cea623 | 4502 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4503 | else if (num == 64) |
56cea623 | 4504 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4505 | else if (num == 65) |
56cea623 | 4506 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4507 | else |
a4b8ebc8 AC |
4508 | /* This will hopefully (eventually) provoke a warning. Should we |
4509 | be calling complaint() here? */ | |
4510 | return NUM_REGS + NUM_PSEUDO_REGS; | |
4511 | return NUM_REGS + regnum; | |
4512 | } | |
4513 | ||
4514 | static int | |
4515 | mips_register_sim_regno (int regnum) | |
4516 | { | |
4517 | /* Only makes sense to supply raw registers. */ | |
4518 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
4519 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
4520 | decide if it is valid. Should instead define a standard sim/gdb | |
4521 | register numbering scheme. */ | |
4522 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
4523 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
4524 | return regnum; | |
4525 | else | |
6d82d43b | 4526 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4527 | } |
4528 | ||
2f38ef89 | 4529 | |
4844f454 CV |
4530 | /* Convert an integer into an address. Extracting the value signed |
4531 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4532 | |
4533 | static CORE_ADDR | |
79dd2d24 | 4534 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4535 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4536 | { |
4844f454 | 4537 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4538 | } |
4539 | ||
caaa3122 DJ |
4540 | static void |
4541 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4542 | { | |
4543 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4544 | const char *name = bfd_get_section_name (abfd, sect); | |
4545 | ||
4546 | if (*abip != MIPS_ABI_UNKNOWN) | |
4547 | return; | |
4548 | ||
4549 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4550 | return; | |
4551 | ||
4552 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4553 | *abip = MIPS_ABI_O32; | |
4554 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4555 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4556 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4557 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4558 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4559 | *abip = MIPS_ABI_O64; | |
4560 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4561 | *abip = MIPS_ABI_EABI32; | |
4562 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4563 | *abip = MIPS_ABI_EABI64; | |
4564 | else | |
8a3fe4f8 | 4565 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4566 | } |
4567 | ||
22e47e37 FF |
4568 | static void |
4569 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4570 | { | |
4571 | int *lbp = (int *) obj; | |
4572 | const char *name = bfd_get_section_name (abfd, sect); | |
4573 | ||
4574 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4575 | *lbp = 32; | |
4576 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4577 | *lbp = 64; | |
4578 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4579 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4580 | } | |
4581 | ||
2e4ebe70 DJ |
4582 | static enum mips_abi |
4583 | global_mips_abi (void) | |
4584 | { | |
4585 | int i; | |
4586 | ||
4587 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4588 | if (mips_abi_strings[i] == mips_abi_string) | |
4589 | return (enum mips_abi) i; | |
4590 | ||
e2e0b3e5 | 4591 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4592 | } |
4593 | ||
29709017 DJ |
4594 | static void |
4595 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
4596 | { | |
4597 | static struct target_desc *tdesc_gp32, *tdesc_gp64; | |
4598 | ||
4599 | if (tdesc_gp32 == NULL) | |
4600 | { | |
4601 | /* Create feature sets with the appropriate properties. The values | |
4602 | are not important. */ | |
4603 | ||
4604 | tdesc_gp32 = allocate_target_description (); | |
4605 | set_tdesc_property (tdesc_gp32, PROPERTY_GP32, ""); | |
4606 | ||
4607 | tdesc_gp64 = allocate_target_description (); | |
4608 | set_tdesc_property (tdesc_gp64, PROPERTY_GP64, ""); | |
4609 | } | |
4610 | ||
4611 | /* If the size matches the set of 32-bit or 64-bit integer registers, | |
4612 | assume that's what we've got. */ | |
4613 | register_remote_g_packet_guess (gdbarch, 38 * 4, tdesc_gp32); | |
4614 | register_remote_g_packet_guess (gdbarch, 38 * 8, tdesc_gp64); | |
4615 | ||
4616 | /* If the size matches the full set of registers GDB traditionally | |
4617 | knows about, including floating point, for either 32-bit or | |
4618 | 64-bit, assume that's what we've got. */ | |
4619 | register_remote_g_packet_guess (gdbarch, 90 * 4, tdesc_gp32); | |
4620 | register_remote_g_packet_guess (gdbarch, 90 * 8, tdesc_gp64); | |
4621 | ||
4622 | /* Otherwise we don't have a useful guess. */ | |
4623 | } | |
4624 | ||
c2d11a7d | 4625 | static struct gdbarch * |
6d82d43b | 4626 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4627 | { |
c2d11a7d JM |
4628 | struct gdbarch *gdbarch; |
4629 | struct gdbarch_tdep *tdep; | |
4630 | int elf_flags; | |
2e4ebe70 | 4631 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 4632 | int num_regs; |
8d5838b5 | 4633 | enum mips_fpu_type fpu_type; |
c2d11a7d | 4634 | |
ec03c1ac AC |
4635 | /* First of all, extract the elf_flags, if available. */ |
4636 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4637 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
4638 | else if (arches != NULL) |
4639 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
4640 | else |
4641 | elf_flags = 0; | |
4642 | if (gdbarch_debug) | |
4643 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4644 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 4645 | |
102182a9 | 4646 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
4647 | switch ((elf_flags & EF_MIPS_ABI)) |
4648 | { | |
4649 | case E_MIPS_ABI_O32: | |
ec03c1ac | 4650 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
4651 | break; |
4652 | case E_MIPS_ABI_O64: | |
ec03c1ac | 4653 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
4654 | break; |
4655 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 4656 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
4657 | break; |
4658 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 4659 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4660 | break; |
4661 | default: | |
acdb74a0 | 4662 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 4663 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 4664 | else |
ec03c1ac | 4665 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
4666 | break; |
4667 | } | |
acdb74a0 | 4668 | |
caaa3122 | 4669 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
4670 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
4671 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 4672 | |
dc305454 | 4673 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
4674 | MIPS architecture (if there is one). */ |
4675 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
4676 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 4677 | |
32a6503c | 4678 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 4679 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
4680 | && info.bfd_arch_info != NULL |
4681 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4682 | { | |
4683 | switch (info.bfd_arch_info->mach) | |
4684 | { | |
4685 | case bfd_mach_mips3900: | |
ec03c1ac | 4686 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
4687 | break; |
4688 | case bfd_mach_mips4100: | |
4689 | case bfd_mach_mips5000: | |
ec03c1ac | 4690 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 4691 | break; |
1d06468c EZ |
4692 | case bfd_mach_mips8000: |
4693 | case bfd_mach_mips10000: | |
32a6503c KB |
4694 | /* On Irix, ELF64 executables use the N64 ABI. The |
4695 | pseudo-sections which describe the ABI aren't present | |
4696 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
4697 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
4698 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 4699 | found_abi = MIPS_ABI_N64; |
28d169de | 4700 | else |
ec03c1ac | 4701 | found_abi = MIPS_ABI_N32; |
1d06468c | 4702 | break; |
bf64bfd6 AC |
4703 | } |
4704 | } | |
2e4ebe70 | 4705 | |
26c53e50 DJ |
4706 | /* Default 64-bit objects to N64 instead of O32. */ |
4707 | if (found_abi == MIPS_ABI_UNKNOWN | |
4708 | && info.abfd != NULL | |
4709 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
4710 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
4711 | found_abi = MIPS_ABI_N64; | |
4712 | ||
ec03c1ac AC |
4713 | if (gdbarch_debug) |
4714 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
4715 | found_abi); | |
4716 | ||
4717 | /* What has the user specified from the command line? */ | |
4718 | wanted_abi = global_mips_abi (); | |
4719 | if (gdbarch_debug) | |
4720 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
4721 | wanted_abi); | |
2e4ebe70 DJ |
4722 | |
4723 | /* Now that we have found what the ABI for this binary would be, | |
4724 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
4725 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
4726 | mips_abi = wanted_abi; | |
ec03c1ac AC |
4727 | else if (found_abi != MIPS_ABI_UNKNOWN) |
4728 | mips_abi = found_abi; | |
4729 | else | |
4730 | mips_abi = MIPS_ABI_O32; | |
4731 | if (gdbarch_debug) | |
4732 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
4733 | mips_abi); | |
2e4ebe70 | 4734 | |
ec03c1ac | 4735 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 4736 | if (gdbarch_debug) |
ec03c1ac AC |
4737 | fprintf_unfiltered (gdb_stdlog, |
4738 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
4739 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 4740 | |
8d5838b5 AC |
4741 | /* Determine the MIPS FPU type. */ |
4742 | if (!mips_fpu_type_auto) | |
4743 | fpu_type = mips_fpu_type; | |
4744 | else if (info.bfd_arch_info != NULL | |
4745 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4746 | switch (info.bfd_arch_info->mach) | |
4747 | { | |
4748 | case bfd_mach_mips3900: | |
4749 | case bfd_mach_mips4100: | |
4750 | case bfd_mach_mips4111: | |
a9d61c86 | 4751 | case bfd_mach_mips4120: |
8d5838b5 AC |
4752 | fpu_type = MIPS_FPU_NONE; |
4753 | break; | |
4754 | case bfd_mach_mips4650: | |
4755 | fpu_type = MIPS_FPU_SINGLE; | |
4756 | break; | |
4757 | default: | |
4758 | fpu_type = MIPS_FPU_DOUBLE; | |
4759 | break; | |
4760 | } | |
4761 | else if (arches != NULL) | |
4762 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
4763 | else | |
4764 | fpu_type = MIPS_FPU_DOUBLE; | |
4765 | if (gdbarch_debug) | |
4766 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4767 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 4768 | |
29709017 DJ |
4769 | /* Check for blatant incompatibilities. */ |
4770 | ||
4771 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
4772 | ABI. */ | |
4773 | if (info.target_desc | |
4774 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
4775 | && mips_abi != MIPS_ABI_EABI32 | |
4776 | && mips_abi != MIPS_ABI_O32) | |
4777 | return NULL; | |
4778 | ||
c2d11a7d JM |
4779 | /* try to find a pre-existing architecture */ |
4780 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4781 | arches != NULL; | |
4782 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4783 | { | |
4784 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 4785 | using. */ |
9103eae0 | 4786 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 4787 | continue; |
9103eae0 | 4788 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 4789 | continue; |
719ec221 AC |
4790 | /* Need to be pedantic about which register virtual size is |
4791 | used. */ | |
4792 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
4793 | != mips64_transfers_32bit_regs_p) | |
4794 | continue; | |
8d5838b5 AC |
4795 | /* Be pedantic about which FPU is selected. */ |
4796 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
4797 | continue; | |
4be87837 | 4798 | return arches->gdbarch; |
c2d11a7d JM |
4799 | } |
4800 | ||
102182a9 | 4801 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
4802 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
4803 | gdbarch = gdbarch_alloc (&info, tdep); | |
4804 | tdep->elf_flags = elf_flags; | |
719ec221 | 4805 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
4806 | tdep->found_abi = found_abi; |
4807 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 4808 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
4809 | tdep->register_size_valid_p = 0; |
4810 | tdep->register_size = 0; | |
4811 | ||
4812 | if (info.target_desc) | |
4813 | { | |
4814 | /* Some useful properties can be inferred from the target. */ | |
4815 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
4816 | { | |
4817 | tdep->register_size_valid_p = 1; | |
4818 | tdep->register_size = 4; | |
4819 | } | |
4820 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
4821 | { | |
4822 | tdep->register_size_valid_p = 1; | |
4823 | tdep->register_size = 8; | |
4824 | } | |
4825 | } | |
c2d11a7d | 4826 | |
102182a9 | 4827 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
4828 | set_gdbarch_short_bit (gdbarch, 16); |
4829 | set_gdbarch_int_bit (gdbarch, 32); | |
4830 | set_gdbarch_float_bit (gdbarch, 32); | |
4831 | set_gdbarch_double_bit (gdbarch, 64); | |
4832 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
4833 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
4834 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
4835 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 4836 | |
6d82d43b | 4837 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
4838 | mips_elf_make_msymbol_special); |
4839 | ||
16e109ca | 4840 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 4841 | { |
16e109ca | 4842 | const char **reg_names; |
56cea623 AC |
4843 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
4844 | struct mips_regnum); | |
56cea623 AC |
4845 | if (info.osabi == GDB_OSABI_IRIX) |
4846 | { | |
4847 | regnum->fp0 = 32; | |
4848 | regnum->pc = 64; | |
4849 | regnum->cause = 65; | |
4850 | regnum->badvaddr = 66; | |
4851 | regnum->hi = 67; | |
4852 | regnum->lo = 68; | |
4853 | regnum->fp_control_status = 69; | |
4854 | regnum->fp_implementation_revision = 70; | |
4855 | num_regs = 71; | |
16e109ca | 4856 | reg_names = mips_irix_reg_names; |
56cea623 AC |
4857 | } |
4858 | else | |
4859 | { | |
4860 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
4861 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
4862 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
4863 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
4864 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
4865 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
4866 | regnum->fp_control_status = 70; | |
4867 | regnum->fp_implementation_revision = 71; | |
4868 | num_regs = 90; | |
16e109ca AC |
4869 | if (info.bfd_arch_info != NULL |
4870 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
4871 | reg_names = mips_tx39_reg_names; | |
4872 | else | |
4873 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
4874 | } |
4875 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
4876 | replaced by read_pc? */ | |
f10683bb MH |
4877 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
4878 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
4879 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
4880 | set_gdbarch_num_regs (gdbarch, num_regs); | |
4881 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
4882 | set_gdbarch_register_name (gdbarch, mips_register_name); |
4883 | tdep->mips_processor_reg_names = reg_names; | |
4884 | tdep->regnum = regnum; | |
56cea623 | 4885 | } |
fe29b929 | 4886 | |
0dadbba0 | 4887 | switch (mips_abi) |
c2d11a7d | 4888 | { |
0dadbba0 | 4889 | case MIPS_ABI_O32: |
25ab4790 | 4890 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 4891 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 4892 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 4893 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 4894 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4895 | set_gdbarch_long_bit (gdbarch, 32); |
4896 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4897 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4898 | break; | |
0dadbba0 | 4899 | case MIPS_ABI_O64: |
25ab4790 | 4900 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 4901 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 4902 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 4903 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 4904 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4905 | set_gdbarch_long_bit (gdbarch, 32); |
4906 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4907 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4908 | break; | |
0dadbba0 | 4909 | case MIPS_ABI_EABI32: |
25ab4790 | 4910 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 4911 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 4912 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4913 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 4914 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4915 | set_gdbarch_long_bit (gdbarch, 32); |
4916 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4917 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4918 | break; | |
0dadbba0 | 4919 | case MIPS_ABI_EABI64: |
25ab4790 | 4920 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 4921 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 4922 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4923 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 4924 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4925 | set_gdbarch_long_bit (gdbarch, 64); |
4926 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4927 | set_gdbarch_long_long_bit (gdbarch, 64); | |
4928 | break; | |
0dadbba0 | 4929 | case MIPS_ABI_N32: |
25ab4790 | 4930 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 4931 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 4932 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4933 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 4934 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
4935 | set_gdbarch_long_bit (gdbarch, 32); |
4936 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4937 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 4938 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 4939 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
4940 | break; |
4941 | case MIPS_ABI_N64: | |
25ab4790 | 4942 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 4943 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 4944 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 4945 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
4946 | tdep->default_mask_address_p = 0; |
4947 | set_gdbarch_long_bit (gdbarch, 64); | |
4948 | set_gdbarch_ptr_bit (gdbarch, 64); | |
4949 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 4950 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 4951 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 4952 | break; |
c2d11a7d | 4953 | default: |
e2e0b3e5 | 4954 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
4955 | } |
4956 | ||
22e47e37 FF |
4957 | /* GCC creates a pseudo-section whose name specifies the size of |
4958 | longs, since -mlong32 or -mlong64 may be used independent of | |
4959 | other options. How those options affect pointer sizes is ABI and | |
4960 | architecture dependent, so use them to override the default sizes | |
4961 | set by the ABI. This table shows the relationship between ABI, | |
4962 | -mlongXX, and size of pointers: | |
4963 | ||
4964 | ABI -mlongXX ptr bits | |
4965 | --- -------- -------- | |
4966 | o32 32 32 | |
4967 | o32 64 32 | |
4968 | n32 32 32 | |
4969 | n32 64 64 | |
4970 | o64 32 32 | |
4971 | o64 64 64 | |
4972 | n64 32 32 | |
4973 | n64 64 64 | |
4974 | eabi32 32 32 | |
4975 | eabi32 64 32 | |
4976 | eabi64 32 32 | |
4977 | eabi64 64 64 | |
4978 | ||
4979 | Note that for o32 and eabi32, pointers are always 32 bits | |
4980 | regardless of any -mlongXX option. For all others, pointers and | |
4981 | longs are the same, as set by -mlongXX or set by defaults. | |
4982 | */ | |
4983 | ||
4984 | if (info.abfd != NULL) | |
4985 | { | |
4986 | int long_bit = 0; | |
4987 | ||
4988 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
4989 | if (long_bit) | |
4990 | { | |
4991 | set_gdbarch_long_bit (gdbarch, long_bit); | |
4992 | switch (mips_abi) | |
4993 | { | |
4994 | case MIPS_ABI_O32: | |
4995 | case MIPS_ABI_EABI32: | |
4996 | break; | |
4997 | case MIPS_ABI_N32: | |
4998 | case MIPS_ABI_O64: | |
4999 | case MIPS_ABI_N64: | |
5000 | case MIPS_ABI_EABI64: | |
5001 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5002 | break; | |
5003 | default: | |
5004 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5005 | } | |
5006 | } | |
5007 | } | |
5008 | ||
a5ea2558 AC |
5009 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5010 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5011 | comment: | |
5012 | ||
5013 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5014 | flag in object files because to do so would make it impossible to | |
102182a9 | 5015 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5016 | unnecessarily restrictive. |
361d1df0 | 5017 | |
a5ea2558 AC |
5018 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5019 | but to set this flag before gcc is built with such multilibs will | |
5020 | break too many systems.'' | |
5021 | ||
5022 | But even more unhelpfully, the default linker output target for | |
5023 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5024 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5025 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5026 | this flag to detect 32-bit mode would do the wrong thing given |
5027 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5028 | as 32-bit programs by default. */ |
a5ea2558 | 5029 | |
6c997a34 | 5030 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5031 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5032 | |
102182a9 MS |
5033 | /* Add/remove bits from an address. The MIPS needs be careful to |
5034 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5035 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5036 | ||
58dfe9ff AC |
5037 | /* Unwind the frame. */ |
5038 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5039 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5040 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5041 | |
102182a9 | 5042 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5043 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5044 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5045 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5046 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5047 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5048 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5049 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5050 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5051 | |
c2d11a7d JM |
5052 | /* MIPS version of CALL_DUMMY */ |
5053 | ||
9710e734 AC |
5054 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5055 | replaced by a command, and all targets will default to on stack | |
5056 | (regardless of the stack's execute status). */ | |
5057 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5058 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5059 | |
87783b8b AC |
5060 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5061 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5062 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5063 | ||
f7b9e9fc AC |
5064 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5065 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5066 | |
5067 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5068 | |
fc0c74b1 AC |
5069 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5070 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5071 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5072 | |
a4b8ebc8 | 5073 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5074 | |
e11c53d2 | 5075 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5076 | |
e5ab0dce AC |
5077 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5078 | ||
3a3bc038 AC |
5079 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5080 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5081 | need to all be folded into the target vector. Since they are | |
5082 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5083 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5084 | is sitting on? */ | |
5085 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5086 | ||
e7d6a6d2 | 5087 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5088 | |
3352ef37 AC |
5089 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5090 | ||
0d5de010 DJ |
5091 | /* Virtual tables. */ |
5092 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5093 | ||
29709017 DJ |
5094 | mips_register_g_packet_guesses (gdbarch); |
5095 | ||
6de918a6 DJ |
5096 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
5097 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5098 | |
5792a79b | 5099 | /* Unwind the frame. */ |
2bd0c3d7 | 5100 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5101 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5102 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5103 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5104 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5105 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5106 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5107 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5108 | |
4b9b3959 AC |
5109 | return gdbarch; |
5110 | } | |
5111 | ||
2e4ebe70 | 5112 | static void |
6d82d43b | 5113 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5114 | { |
5115 | struct gdbarch_info info; | |
5116 | ||
5117 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5118 | mips_gdbarch_init will take care of the rest. */ | |
5119 | gdbarch_info_init (&info); | |
5120 | gdbarch_update_p (info); | |
5121 | } | |
5122 | ||
ad188201 KB |
5123 | /* Print out which MIPS ABI is in use. */ |
5124 | ||
5125 | static void | |
1f8ca57c JB |
5126 | show_mips_abi (struct ui_file *file, |
5127 | int from_tty, | |
5128 | struct cmd_list_element *ignored_cmd, | |
5129 | const char *ignored_value) | |
ad188201 KB |
5130 | { |
5131 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5132 | fprintf_filtered |
5133 | (file, | |
5134 | "The MIPS ABI is unknown because the current architecture " | |
5135 | "is not MIPS.\n"); | |
ad188201 KB |
5136 | else |
5137 | { | |
5138 | enum mips_abi global_abi = global_mips_abi (); | |
5139 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5140 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5141 | ||
5142 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5143 | fprintf_filtered |
5144 | (file, | |
5145 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5146 | actual_abi_str); |
ad188201 | 5147 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5148 | fprintf_filtered |
5149 | (file, | |
5150 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5151 | actual_abi_str); |
ad188201 KB |
5152 | else |
5153 | { | |
5154 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5155 | fprintf_filtered |
5156 | (file, | |
5157 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5158 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5159 | } |
5160 | } | |
5161 | } | |
5162 | ||
4b9b3959 AC |
5163 | static void |
5164 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5165 | { | |
5166 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5167 | if (tdep != NULL) | |
c2d11a7d | 5168 | { |
acdb74a0 AC |
5169 | int ef_mips_arch; |
5170 | int ef_mips_32bitmode; | |
f49e4e6d | 5171 | /* Determine the ISA. */ |
acdb74a0 AC |
5172 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5173 | { | |
5174 | case E_MIPS_ARCH_1: | |
5175 | ef_mips_arch = 1; | |
5176 | break; | |
5177 | case E_MIPS_ARCH_2: | |
5178 | ef_mips_arch = 2; | |
5179 | break; | |
5180 | case E_MIPS_ARCH_3: | |
5181 | ef_mips_arch = 3; | |
5182 | break; | |
5183 | case E_MIPS_ARCH_4: | |
93d56215 | 5184 | ef_mips_arch = 4; |
acdb74a0 AC |
5185 | break; |
5186 | default: | |
93d56215 | 5187 | ef_mips_arch = 0; |
acdb74a0 AC |
5188 | break; |
5189 | } | |
f49e4e6d | 5190 | /* Determine the size of a pointer. */ |
acdb74a0 | 5191 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5192 | fprintf_unfiltered (file, |
5193 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5194 | tdep->elf_flags); |
4b9b3959 | 5195 | fprintf_unfiltered (file, |
acdb74a0 AC |
5196 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5197 | ef_mips_32bitmode); | |
5198 | fprintf_unfiltered (file, | |
5199 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5200 | ef_mips_arch); | |
5201 | fprintf_unfiltered (file, | |
5202 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5203 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5204 | fprintf_unfiltered (file, |
5205 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5206 | mips_mask_address_p (tdep), |
4014092b | 5207 | tdep->default_mask_address_p); |
c2d11a7d | 5208 | } |
4b9b3959 AC |
5209 | fprintf_unfiltered (file, |
5210 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5211 | MIPS_DEFAULT_FPU_TYPE, | |
5212 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5213 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5214 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5215 | : "???")); | |
6d82d43b | 5216 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5217 | fprintf_unfiltered (file, |
5218 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5219 | MIPS_FPU_TYPE, | |
5220 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5221 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5222 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5223 | : "???")); | |
c2d11a7d JM |
5224 | } |
5225 | ||
6d82d43b | 5226 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5227 | |
c906108c | 5228 | void |
acdb74a0 | 5229 | _initialize_mips_tdep (void) |
c906108c SS |
5230 | { |
5231 | static struct cmd_list_element *mipsfpulist = NULL; | |
5232 | struct cmd_list_element *c; | |
5233 | ||
6d82d43b | 5234 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5235 | if (MIPS_ABI_LAST + 1 |
5236 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5237 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5238 | |
4b9b3959 | 5239 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5240 | |
8d5f9dcb DJ |
5241 | mips_pdr_data = register_objfile_data (); |
5242 | ||
a5ea2558 AC |
5243 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5244 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5245 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5246 | &setmipscmdlist, "set mips ", 0, &setlist); |
5247 | ||
5248 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5249 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5250 | &showmipscmdlist, "show mips ", 0, &showlist); |
5251 | ||
2e4ebe70 | 5252 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5253 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5254 | &mips_abi_string, _("\ | |
5255 | Set the MIPS ABI used by this program."), _("\ | |
5256 | Show the MIPS ABI used by this program."), _("\ | |
5257 | This option can be set to one of:\n\ | |
5258 | auto - the default ABI associated with the current binary\n\ | |
5259 | o32\n\ | |
5260 | o64\n\ | |
5261 | n32\n\ | |
5262 | n64\n\ | |
5263 | eabi32\n\ | |
5264 | eabi64"), | |
5265 | mips_abi_update, | |
5266 | show_mips_abi, | |
5267 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5268 | |
c906108c SS |
5269 | /* Let the user turn off floating point and set the fence post for |
5270 | heuristic_proc_start. */ | |
5271 | ||
5272 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5273 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5274 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5275 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5276 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5277 | &mipsfpulist); |
5278 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5279 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5280 | &mipsfpulist); |
5281 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5282 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5283 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5284 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5285 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5286 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5287 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5288 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5289 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5290 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5291 | &mipsfpulist); |
5292 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5293 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5294 | &showlist); |
5295 | ||
c906108c SS |
5296 | /* We really would like to have both "0" and "unlimited" work, but |
5297 | command.c doesn't deal with that. So make it a var_zinteger | |
5298 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5299 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5300 | &heuristic_fence_post, _("\ |
5301 | Set the distance searched for the start of a function."), _("\ | |
5302 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5303 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5304 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5305 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5306 | reinit_frame_cache_sfunc, |
7915a72c | 5307 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5308 | &setlist, &showlist); |
c906108c SS |
5309 | |
5310 | /* Allow the user to control whether the upper bits of 64-bit | |
5311 | addresses should be zeroed. */ | |
7915a72c AC |
5312 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5313 | &mask_address_var, _("\ | |
5314 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5315 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5316 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5317 | allow GDB to determine the correct value."), |
08546159 AC |
5318 | NULL, show_mask_address, |
5319 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5320 | |
5321 | /* Allow the user to control the size of 32 bit registers within the | |
5322 | raw remote packet. */ | |
b3f42336 | 5323 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5324 | &mips64_transfers_32bit_regs_p, _("\ |
5325 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5326 | _("\ | |
5327 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5328 | _("\ | |
719ec221 AC |
5329 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5330 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5331 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5332 | set_mips64_transfers_32bit_regs, |
7915a72c | 5333 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5334 | &setlist, &showlist); |
9ace0497 AC |
5335 | |
5336 | /* Debug this files internals. */ | |
6bcadd06 | 5337 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5338 | &mips_debug, _("\ |
5339 | Set mips debugging."), _("\ | |
5340 | Show mips debugging."), _("\ | |
5341 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5342 | NULL, |
7915a72c | 5343 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5344 | &setdebuglist, &showdebuglist); |
c906108c | 5345 | } |