Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
f8b73d13 DJ |
97 | /* The standard register names, and all the valid aliases for them. */ |
98 | struct register_alias | |
99 | { | |
100 | const char *name; | |
101 | int regnum; | |
102 | }; | |
103 | ||
104 | /* Aliases for o32 and most other ABIs. */ | |
105 | const struct register_alias mips_o32_aliases[] = { | |
106 | { "ta0", 12 }, | |
107 | { "ta1", 13 }, | |
108 | { "ta2", 14 }, | |
109 | { "ta3", 15 } | |
110 | }; | |
111 | ||
112 | /* Aliases for n32 and n64. */ | |
113 | const struct register_alias mips_n32_n64_aliases[] = { | |
114 | { "ta0", 8 }, | |
115 | { "ta1", 9 }, | |
116 | { "ta2", 10 }, | |
117 | { "ta3", 11 } | |
118 | }; | |
119 | ||
120 | /* Aliases for ABI-independent registers. */ | |
121 | const struct register_alias mips_register_aliases[] = { | |
122 | /* The architecture manuals specify these ABI-independent names for | |
123 | the GPRs. */ | |
124 | #define R(n) { "r" #n, n } | |
125 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
126 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
127 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
128 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
129 | #undef R | |
130 | ||
131 | /* k0 and k1 are sometimes called these instead (for "kernel | |
132 | temp"). */ | |
133 | { "kt0", 26 }, | |
134 | { "kt1", 27 }, | |
135 | ||
136 | /* This is the traditional GDB name for the CP0 status register. */ | |
137 | { "sr", MIPS_PS_REGNUM }, | |
138 | ||
139 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
140 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
141 | ||
142 | /* This is the traditional GDB name for the FCSR. */ | |
143 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
144 | }; | |
145 | ||
865093a3 AR |
146 | const struct register_alias mips_numeric_register_aliases[] = { |
147 | #define R(n) { #n, n } | |
148 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
149 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
150 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
151 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
152 | #undef R | |
153 | }; | |
154 | ||
c906108c SS |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
56cea623 AC |
171 | const struct mips_regnum * |
172 | mips_regnum (struct gdbarch *gdbarch) | |
173 | { | |
174 | return gdbarch_tdep (gdbarch)->regnum; | |
175 | } | |
176 | ||
177 | static int | |
178 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
179 | { | |
180 | return mips_regnum (gdbarch)->fp0 + 12; | |
181 | } | |
182 | ||
74ed0bb4 MD |
183 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
184 | == MIPS_ABI_EABI32 \ | |
185 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 186 | |
74ed0bb4 | 187 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 188 | |
74ed0bb4 | 189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 190 | |
74ed0bb4 | 191 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 192 | |
95404a3e AC |
193 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
194 | functions to test, set, or clear bit 0 of addresses. */ | |
195 | ||
196 | static CORE_ADDR | |
197 | is_mips16_addr (CORE_ADDR addr) | |
198 | { | |
199 | return ((addr) & 1); | |
200 | } | |
201 | ||
95404a3e AC |
202 | static CORE_ADDR |
203 | unmake_mips16_addr (CORE_ADDR addr) | |
204 | { | |
5b652102 | 205 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
206 | } |
207 | ||
d1973055 KB |
208 | /* Return the MIPS ABI associated with GDBARCH. */ |
209 | enum mips_abi | |
210 | mips_abi (struct gdbarch *gdbarch) | |
211 | { | |
212 | return gdbarch_tdep (gdbarch)->mips_abi; | |
213 | } | |
214 | ||
4246e332 | 215 | int |
1b13c4f6 | 216 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 217 | { |
29709017 DJ |
218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
219 | ||
220 | /* If we know how big the registers are, use that size. */ | |
221 | if (tdep->register_size_valid_p) | |
222 | return tdep->register_size; | |
223 | ||
224 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
225 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
226 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
227 | } | |
228 | ||
480d3dd2 AC |
229 | /* Return the currently configured (or set) saved register size. */ |
230 | ||
e6bc2e8a | 231 | unsigned int |
13326b4e | 232 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 233 | { |
1a69e1e4 DJ |
234 | switch (mips_abi (gdbarch)) |
235 | { | |
236 | case MIPS_ABI_EABI32: | |
237 | case MIPS_ABI_O32: | |
238 | return 4; | |
239 | case MIPS_ABI_N32: | |
240 | case MIPS_ABI_N64: | |
241 | case MIPS_ABI_O64: | |
242 | case MIPS_ABI_EABI64: | |
243 | return 8; | |
244 | case MIPS_ABI_UNKNOWN: | |
245 | case MIPS_ABI_LAST: | |
246 | default: | |
247 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
248 | } | |
d929b26f AC |
249 | } |
250 | ||
71b8ef93 | 251 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 252 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 253 | "info" field is used for this purpose. |
5a89d8aa | 254 | |
95f1da47 | 255 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
256 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
257 | minimal symbol to mark it as a 16-bit function | |
258 | ||
f594e5e9 | 259 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 260 | |
5a89d8aa | 261 | static void |
6d82d43b AC |
262 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
263 | { | |
264 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
265 | { | |
b887350f | 266 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b AC |
267 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
268 | } | |
5a89d8aa MS |
269 | } |
270 | ||
71b8ef93 MS |
271 | static int |
272 | msymbol_is_special (struct minimal_symbol *msym) | |
273 | { | |
b887350f | 274 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
275 | } |
276 | ||
88658117 AC |
277 | /* XFER a value from the big/little/left end of the register. |
278 | Depending on the size of the value it might occupy the entire | |
279 | register or just part of it. Make an allowance for this, aligning | |
280 | things accordingly. */ | |
281 | ||
282 | static void | |
ba32f989 DJ |
283 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
284 | int reg_num, int length, | |
870cd05e MK |
285 | enum bfd_endian endian, gdb_byte *in, |
286 | const gdb_byte *out, int buf_offset) | |
88658117 | 287 | { |
88658117 | 288 | int reg_offset = 0; |
72a155b4 UW |
289 | |
290 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
291 | /* Need to transfer the left or right part of the register, based on |
292 | the targets byte order. */ | |
88658117 AC |
293 | switch (endian) |
294 | { | |
295 | case BFD_ENDIAN_BIG: | |
72a155b4 | 296 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
297 | break; |
298 | case BFD_ENDIAN_LITTLE: | |
299 | reg_offset = 0; | |
300 | break; | |
6d82d43b | 301 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
302 | reg_offset = 0; |
303 | break; | |
304 | default: | |
e2e0b3e5 | 305 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
306 | } |
307 | if (mips_debug) | |
cb1d2653 AC |
308 | fprintf_unfiltered (gdb_stderr, |
309 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
310 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
311 | if (mips_debug && out != NULL) |
312 | { | |
313 | int i; | |
cb1d2653 | 314 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 315 | for (i = 0; i < length; i++) |
cb1d2653 | 316 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
317 | } |
318 | if (in != NULL) | |
6d82d43b AC |
319 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
320 | in + buf_offset); | |
88658117 | 321 | if (out != NULL) |
6d82d43b AC |
322 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
323 | out + buf_offset); | |
88658117 AC |
324 | if (mips_debug && in != NULL) |
325 | { | |
326 | int i; | |
cb1d2653 | 327 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 328 | for (i = 0; i < length; i++) |
cb1d2653 | 329 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
330 | } |
331 | if (mips_debug) | |
332 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
333 | } | |
334 | ||
dd824b04 DJ |
335 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
336 | compatiblity mode. A return value of 1 means that we have | |
337 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
338 | ||
339 | static int | |
9c9acae0 | 340 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 341 | { |
72a155b4 | 342 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
344 | meaningful. */ | |
72a155b4 | 345 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
346 | return 0; |
347 | ||
348 | #if 0 | |
349 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
350 | in all the places we deal with FP registers. PR gdb/413. */ | |
351 | /* Otherwise check the FR bit in the status register - it controls | |
352 | the FP compatiblity mode. If it is clear we are in compatibility | |
353 | mode. */ | |
9c9acae0 | 354 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
355 | return 1; |
356 | #endif | |
361d1df0 | 357 | |
dd824b04 DJ |
358 | return 0; |
359 | } | |
360 | ||
7a292a7a | 361 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 362 | |
74ed0bb4 | 363 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 364 | |
a14ed312 | 365 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 366 | |
acdb74a0 AC |
367 | /* The list of available "set mips " and "show mips " commands */ |
368 | ||
369 | static struct cmd_list_element *setmipscmdlist = NULL; | |
370 | static struct cmd_list_element *showmipscmdlist = NULL; | |
371 | ||
5e2e9765 KB |
372 | /* Integer registers 0 thru 31 are handled explicitly by |
373 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 374 | are listed in the following tables. */ |
691c0433 | 375 | |
6d82d43b AC |
376 | enum |
377 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
378 | |
379 | /* Generic MIPS. */ | |
380 | ||
381 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
382 | "sr", "lo", "hi", "bad", "cause", "pc", |
383 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
384 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
385 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
386 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
387 | "fsr", "fir", "" /*"fp" */ , "", | |
388 | "", "", "", "", "", "", "", "", | |
389 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
390 | }; |
391 | ||
392 | /* Names of IDT R3041 registers. */ | |
393 | ||
394 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
395 | "sr", "lo", "hi", "bad", "cause", "pc", |
396 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
397 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
398 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
399 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
400 | "fsr", "fir", "", /*"fp" */ "", | |
401 | "", "", "bus", "ccfg", "", "", "", "", | |
402 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
403 | }; |
404 | ||
405 | /* Names of tx39 registers. */ | |
406 | ||
407 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
408 | "sr", "lo", "hi", "bad", "cause", "pc", |
409 | "", "", "", "", "", "", "", "", | |
410 | "", "", "", "", "", "", "", "", | |
411 | "", "", "", "", "", "", "", "", | |
412 | "", "", "", "", "", "", "", "", | |
413 | "", "", "", "", | |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
416 | }; |
417 | ||
418 | /* Names of IRIX registers. */ | |
419 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
420 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
421 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
422 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
423 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
424 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
425 | }; |
426 | ||
cce74817 | 427 | |
5e2e9765 | 428 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 429 | static const char * |
d93859e2 | 430 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 431 | { |
d93859e2 | 432 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
433 | /* GPR names for all ABIs other than n32/n64. */ |
434 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
435 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
436 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
437 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
438 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
439 | }; |
440 | ||
441 | /* GPR names for n32 and n64 ABIs. */ | |
442 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
444 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
447 | }; |
448 | ||
d93859e2 | 449 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 450 | |
f57d151a UW |
451 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
452 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
453 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
454 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
455 | return ""; |
456 | ||
5e2e9765 KB |
457 | /* The MIPS integer registers are always mapped from 0 to 31. The |
458 | names of the registers (which reflects the conventions regarding | |
459 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 460 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
461 | { |
462 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 463 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 464 | else |
a4b8ebc8 | 465 | return mips_gpr_names[rawnum]; |
5e2e9765 | 466 | } |
d93859e2 UW |
467 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
468 | return tdesc_register_name (gdbarch, rawnum); | |
469 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
470 | { |
471 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
472 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
473 | } | |
5e2e9765 KB |
474 | else |
475 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 476 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 477 | } |
5e2e9765 | 478 | |
a4b8ebc8 | 479 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 480 | |
a4b8ebc8 AC |
481 | static int |
482 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
483 | struct reggroup *reggroup) | |
484 | { | |
485 | int vector_p; | |
486 | int float_p; | |
487 | int raw_p; | |
72a155b4 UW |
488 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
489 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
490 | if (reggroup == all_reggroup) |
491 | return pseudo; | |
492 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
493 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
494 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
495 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
496 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
497 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
498 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
499 | return 0; |
500 | if (reggroup == float_reggroup) | |
501 | return float_p && pseudo; | |
502 | if (reggroup == vector_reggroup) | |
503 | return vector_p && pseudo; | |
504 | if (reggroup == general_reggroup) | |
505 | return (!vector_p && !float_p) && pseudo; | |
506 | /* Save the pseudo registers. Need to make certain that any code | |
507 | extracting register values from a saved register cache also uses | |
508 | pseudo registers. */ | |
509 | if (reggroup == save_reggroup) | |
510 | return raw_p && pseudo; | |
511 | /* Restore the same pseudo register. */ | |
512 | if (reggroup == restore_reggroup) | |
513 | return raw_p && pseudo; | |
6d82d43b | 514 | return 0; |
a4b8ebc8 AC |
515 | } |
516 | ||
f8b73d13 DJ |
517 | /* Return the groups that a MIPS register can be categorised into. |
518 | This version is only used if we have a target description which | |
519 | describes real registers (and their groups). */ | |
520 | ||
521 | static int | |
522 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
523 | struct reggroup *reggroup) | |
524 | { | |
525 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
526 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
527 | int ret; | |
528 | ||
529 | /* Only save, restore, and display the pseudo registers. Need to | |
530 | make certain that any code extracting register values from a | |
531 | saved register cache also uses pseudo registers. | |
532 | ||
533 | Note: saving and restoring the pseudo registers is slightly | |
534 | strange; if we have 64 bits, we should save and restore all | |
535 | 64 bits. But this is hard and has little benefit. */ | |
536 | if (!pseudo) | |
537 | return 0; | |
538 | ||
539 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
540 | if (ret != -1) | |
541 | return ret; | |
542 | ||
543 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
544 | } | |
545 | ||
a4b8ebc8 | 546 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 547 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 548 | registers. Take care of alignment and size problems. */ |
c5aa993b | 549 | |
a4b8ebc8 AC |
550 | static void |
551 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 552 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 553 | { |
72a155b4 UW |
554 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
555 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
556 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 557 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 558 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
559 | else if (register_size (gdbarch, rawnum) > |
560 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 561 | { |
8bdf35dc | 562 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
563 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
564 | else | |
8bdf35dc KB |
565 | { |
566 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
567 | LONGEST regval; | |
568 | regcache_raw_read_signed (regcache, rawnum, ®val); | |
569 | store_signed_integer (buf, 4, byte_order, regval); | |
570 | } | |
47ebcfbe AC |
571 | } |
572 | else | |
e2e0b3e5 | 573 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
574 | } |
575 | ||
576 | static void | |
6d82d43b AC |
577 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
578 | struct regcache *regcache, int cookednum, | |
47a35522 | 579 | const gdb_byte *buf) |
a4b8ebc8 | 580 | { |
72a155b4 UW |
581 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
582 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
583 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 584 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 585 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
586 | else if (register_size (gdbarch, rawnum) > |
587 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 588 | { |
8bdf35dc | 589 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
590 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
591 | else | |
8bdf35dc KB |
592 | { |
593 | /* Sign extend the shortened version of the register prior | |
594 | to placing it in the raw register. This is required for | |
595 | some mips64 parts in order to avoid unpredictable behavior. */ | |
596 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
597 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
598 | regcache_raw_write_signed (regcache, rawnum, regval); | |
599 | } | |
47ebcfbe AC |
600 | } |
601 | else | |
e2e0b3e5 | 602 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 603 | } |
c5aa993b | 604 | |
c906108c | 605 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 606 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
607 | |
608 | /* Heuristic_proc_start may hunt through the text section for a long | |
609 | time across a 2400 baud serial line. Allows the user to limit this | |
610 | search. */ | |
611 | ||
612 | static unsigned int heuristic_fence_post = 0; | |
613 | ||
46cd78fb | 614 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
615 | register N. NOTE: This defines the pseudo register type so need to |
616 | rebuild the architecture vector. */ | |
43e526b9 JM |
617 | |
618 | static int mips64_transfers_32bit_regs_p = 0; | |
619 | ||
719ec221 AC |
620 | static void |
621 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
622 | struct cmd_list_element *c) | |
43e526b9 | 623 | { |
719ec221 AC |
624 | struct gdbarch_info info; |
625 | gdbarch_info_init (&info); | |
626 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
627 | instead of relying on globals. Doing that would let generic code | |
628 | handle the search for this specific architecture. */ | |
629 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 630 | { |
719ec221 | 631 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 632 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 633 | } |
a4b8ebc8 AC |
634 | } |
635 | ||
47ebcfbe | 636 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 637 | |
ee51a8c7 KB |
638 | /* This predicate tests for the case of an 8 byte floating point |
639 | value that is being transferred to or from a pair of floating point | |
640 | registers each of which are (or are considered to be) only 4 bytes | |
641 | wide. */ | |
ff2e87ac | 642 | static int |
ee51a8c7 KB |
643 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
644 | struct type *type) | |
ff2e87ac | 645 | { |
0abe36f5 MD |
646 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
647 | && register_size (gdbarch, regnum) == 4 | |
648 | && (regnum % gdbarch_num_regs (gdbarch)) | |
649 | >= mips_regnum (gdbarch)->fp0 | |
650 | && (regnum % gdbarch_num_regs (gdbarch)) | |
651 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 652 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
653 | } |
654 | ||
ee51a8c7 KB |
655 | /* This predicate tests for the case of a value of less than 8 |
656 | bytes in width that is being transfered to or from an 8 byte | |
657 | general purpose register. */ | |
658 | static int | |
659 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
660 | struct type *type) | |
661 | { | |
662 | int num_regs = gdbarch_num_regs (gdbarch); | |
663 | ||
664 | return (register_size (gdbarch, regnum) == 8 | |
665 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
666 | && TYPE_LENGTH (type) < 8); | |
667 | } | |
668 | ||
669 | static int | |
670 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) | |
671 | { | |
672 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
673 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
674 | } | |
675 | ||
42c466d7 | 676 | static void |
ff2e87ac | 677 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 678 | struct type *type, gdb_byte *to) |
102182a9 | 679 | { |
ee51a8c7 KB |
680 | struct gdbarch *gdbarch = get_frame_arch (frame); |
681 | ||
682 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
683 | { | |
684 | get_frame_register (frame, regnum + 0, to + 4); | |
685 | get_frame_register (frame, regnum + 1, to + 0); | |
686 | } | |
687 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
688 | { | |
689 | int len = TYPE_LENGTH (type); | |
690 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
691 | get_frame_register_bytes (frame, regnum, 8 - len, len, to); | |
692 | else | |
693 | get_frame_register_bytes (frame, regnum, 0, len, to); | |
694 | } | |
695 | else | |
696 | { | |
697 | internal_error (__FILE__, __LINE__, | |
698 | _("mips_register_to_value: unrecognized case")); | |
699 | } | |
102182a9 MS |
700 | } |
701 | ||
42c466d7 | 702 | static void |
ff2e87ac | 703 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 704 | struct type *type, const gdb_byte *from) |
102182a9 | 705 | { |
ee51a8c7 KB |
706 | struct gdbarch *gdbarch = get_frame_arch (frame); |
707 | ||
708 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
709 | { | |
710 | put_frame_register (frame, regnum + 0, from + 4); | |
711 | put_frame_register (frame, regnum + 1, from + 0); | |
712 | } | |
713 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
714 | { | |
715 | gdb_byte fill[8]; | |
716 | int len = TYPE_LENGTH (type); | |
717 | ||
718 | /* Sign extend values, irrespective of type, that are stored to | |
719 | a 64-bit general purpose register. (32-bit unsigned values | |
720 | are stored as signed quantities within a 64-bit register. | |
721 | When performing an operation, in compiled code, that combines | |
722 | a 32-bit unsigned value with a signed 64-bit value, a type | |
723 | conversion is first performed that zeroes out the high 32 bits.) */ | |
724 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
725 | { | |
726 | if (from[0] & 0x80) | |
727 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
728 | else | |
729 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
730 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
731 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
732 | } | |
733 | else | |
734 | { | |
735 | if (from[len-1] & 0x80) | |
736 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
737 | else | |
738 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
739 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
740 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
741 | } | |
742 | } | |
743 | else | |
744 | { | |
745 | internal_error (__FILE__, __LINE__, | |
746 | _("mips_value_to_register: unrecognized case")); | |
747 | } | |
102182a9 MS |
748 | } |
749 | ||
a4b8ebc8 AC |
750 | /* Return the GDB type object for the "standard" data type of data in |
751 | register REG. */ | |
78fde5f8 KB |
752 | |
753 | static struct type * | |
a4b8ebc8 AC |
754 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
755 | { | |
72a155b4 UW |
756 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
757 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
758 | && (regnum % gdbarch_num_regs (gdbarch)) | |
759 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 760 | { |
5ef80fb0 | 761 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 762 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 763 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 764 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 765 | else |
27067745 | 766 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 767 | } |
72a155b4 | 768 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
769 | { |
770 | /* The raw or ISA registers. These are all sized according to | |
771 | the ISA regsize. */ | |
772 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 773 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 774 | else |
df4df182 | 775 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 776 | } |
78fde5f8 | 777 | else |
d5ac5a39 AC |
778 | { |
779 | /* The cooked or ABI registers. These are sized according to | |
780 | the ABI (with a few complications). */ | |
72a155b4 UW |
781 | if (regnum >= (gdbarch_num_regs (gdbarch) |
782 | + mips_regnum (gdbarch)->fp_control_status) | |
783 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
784 | /* The pseudo/cooked view of the embedded registers is always |
785 | 32-bit. The raw view is handled below. */ | |
df4df182 | 786 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
787 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
788 | /* The target, while possibly using a 64-bit register buffer, | |
789 | is only transfering 32-bits of each integer register. | |
790 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 791 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
792 | else if (mips_abi_regsize (gdbarch) == 4) |
793 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
794 | 32- or 64-bit). */ | |
df4df182 | 795 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
796 | else |
797 | /* 64-bit ABI. */ | |
df4df182 | 798 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 799 | } |
78fde5f8 KB |
800 | } |
801 | ||
f8b73d13 DJ |
802 | /* Return the GDB type for the pseudo register REGNUM, which is the |
803 | ABI-level view. This function is only called if there is a target | |
804 | description which includes registers, so we know precisely the | |
805 | types of hardware registers. */ | |
806 | ||
807 | static struct type * | |
808 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
809 | { | |
810 | const int num_regs = gdbarch_num_regs (gdbarch); | |
811 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
812 | int rawnum = regnum % num_regs; | |
813 | struct type *rawtype; | |
814 | ||
815 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
816 | ||
817 | /* Absent registers are still absent. */ | |
818 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
819 | if (TYPE_LENGTH (rawtype) == 0) | |
820 | return rawtype; | |
821 | ||
822 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
823 | /* Present the floating point registers however the hardware did; | |
824 | do not try to convert between FPU layouts. */ | |
825 | return rawtype; | |
826 | ||
827 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
828 | { | |
829 | /* The pseudo/cooked view of embedded registers is always | |
830 | 32-bit, even if the target transfers 64-bit values for them. | |
831 | New targets relying on XML descriptions should only transfer | |
832 | the necessary 32 bits, but older versions of GDB expected 64, | |
833 | so allow the target to provide 64 bits without interfering | |
834 | with the displayed type. */ | |
df4df182 | 835 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
836 | } |
837 | ||
838 | /* Use pointer types for registers if we can. For n32 we can not, | |
839 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
840 | if (mips_abi_regsize (gdbarch) |
841 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
842 | { |
843 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 844 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 845 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 846 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
847 | } |
848 | ||
849 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
850 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 851 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
852 | |
853 | /* For all other registers, pass through the hardware type. */ | |
854 | return rawtype; | |
855 | } | |
bcb0cc15 | 856 | |
c906108c | 857 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 858 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
859 | |
860 | static int | |
480d3dd2 | 861 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
862 | { |
863 | switch (mask_address_var) | |
864 | { | |
7f19b9a2 | 865 | case AUTO_BOOLEAN_TRUE: |
4014092b | 866 | return 1; |
7f19b9a2 | 867 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
868 | return 0; |
869 | break; | |
7f19b9a2 | 870 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 871 | return tdep->default_mask_address_p; |
4014092b | 872 | default: |
e2e0b3e5 | 873 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 874 | return -1; |
361d1df0 | 875 | } |
4014092b AC |
876 | } |
877 | ||
878 | static void | |
08546159 AC |
879 | show_mask_address (struct ui_file *file, int from_tty, |
880 | struct cmd_list_element *c, const char *value) | |
4014092b | 881 | { |
1cf3db46 | 882 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
883 | |
884 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
885 | switch (mask_address_var) |
886 | { | |
7f19b9a2 | 887 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
888 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
889 | break; | |
7f19b9a2 | 890 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
891 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
892 | break; | |
7f19b9a2 | 893 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
894 | printf_filtered |
895 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
896 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
897 | break; |
898 | default: | |
e2e0b3e5 | 899 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 900 | break; |
361d1df0 | 901 | } |
4014092b | 902 | } |
c906108c | 903 | |
c906108c SS |
904 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
905 | ||
0fe7e7c8 AC |
906 | int |
907 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
908 | { |
909 | struct minimal_symbol *sym; | |
910 | ||
911 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 912 | if (is_mips16_addr (memaddr)) |
c906108c SS |
913 | return 1; |
914 | ||
915 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
916 | the high bit of the info field. Use this to decide if the function is | |
917 | MIPS16 or normal MIPS. */ | |
918 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
919 | if (sym) | |
71b8ef93 | 920 | return msymbol_is_special (sym); |
c906108c SS |
921 | else |
922 | return 0; | |
923 | } | |
924 | ||
b2fa5097 | 925 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
926 | all registers should be sign extended for simplicity? */ |
927 | ||
928 | static CORE_ADDR | |
61a1198a | 929 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 930 | { |
61a1198a UW |
931 | ULONGEST pc; |
932 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
933 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
934 | return pc; | |
b6cb9035 AC |
935 | } |
936 | ||
58dfe9ff AC |
937 | static CORE_ADDR |
938 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
939 | { | |
72a155b4 UW |
940 | return frame_unwind_register_signed |
941 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
942 | } |
943 | ||
30244cd8 UW |
944 | static CORE_ADDR |
945 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
946 | { | |
72a155b4 UW |
947 | return frame_unwind_register_signed |
948 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
949 | } |
950 | ||
b8a22b94 | 951 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
952 | dummy frame. The frame ID's base needs to match the TOS value |
953 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
954 | breakpoint. */ | |
955 | ||
956 | static struct frame_id | |
b8a22b94 | 957 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 958 | { |
f57d151a | 959 | return frame_id_build |
b8a22b94 DJ |
960 | (get_frame_register_signed (this_frame, |
961 | gdbarch_num_regs (gdbarch) | |
962 | + MIPS_SP_REGNUM), | |
963 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
964 | } |
965 | ||
b6cb9035 | 966 | static void |
61a1198a | 967 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 968 | { |
61a1198a UW |
969 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
970 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 971 | } |
c906108c | 972 | |
c906108c SS |
973 | /* Fetch and return instruction from the specified location. If the PC |
974 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
975 | ||
d37cca3d | 976 | static ULONGEST |
e17a4113 | 977 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 978 | { |
e17a4113 | 979 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 980 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
981 | int instlen; |
982 | int status; | |
983 | ||
0fe7e7c8 | 984 | if (mips_pc_is_mips16 (addr)) |
c906108c | 985 | { |
95ac2dcf | 986 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 987 | addr = unmake_mips16_addr (addr); |
c906108c SS |
988 | } |
989 | else | |
95ac2dcf | 990 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 991 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
992 | if (status) |
993 | memory_error (status, addr); | |
e17a4113 | 994 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
995 | } |
996 | ||
c906108c | 997 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
998 | #define mips32_op(x) (x >> 26) |
999 | #define itype_op(x) (x >> 26) | |
1000 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1001 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1002 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1003 | |
e135b889 DJ |
1004 | #define jtype_op(x) (x >> 26) |
1005 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1006 | |
e135b889 DJ |
1007 | #define rtype_op(x) (x >> 26) |
1008 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1009 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1010 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1011 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1012 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1013 | |
06987e64 MK |
1014 | static LONGEST |
1015 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1016 | { |
06987e64 | 1017 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1018 | } |
1019 | ||
f49e4e6d MS |
1020 | /* Determine where to set a single step breakpoint while considering |
1021 | branch prediction. */ | |
5a89d8aa | 1022 | static CORE_ADDR |
0b1b3e42 | 1023 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1024 | { |
e17a4113 | 1025 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1026 | unsigned long inst; |
1027 | int op; | |
e17a4113 | 1028 | inst = mips_fetch_instruction (gdbarch, pc); |
e135b889 | 1029 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1030 | { |
e135b889 | 1031 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1032 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1033 | { |
e135b889 | 1034 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1035 | switch (op) |
1036 | { | |
e135b889 DJ |
1037 | case 0: /* BEQL */ |
1038 | goto equal_branch; | |
1039 | case 1: /* BNEL */ | |
1040 | goto neq_branch; | |
1041 | case 2: /* BLEZL */ | |
1042 | goto less_branch; | |
313628cc | 1043 | case 3: /* BGTZL */ |
e135b889 | 1044 | goto greater_branch; |
c5aa993b JM |
1045 | default: |
1046 | pc += 4; | |
c906108c SS |
1047 | } |
1048 | } | |
e135b889 | 1049 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1050 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1051 | { |
1052 | int tf = itype_rt (inst) & 0x01; | |
1053 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1054 | int fcrcs = |
72a155b4 UW |
1055 | get_frame_register_signed (frame, |
1056 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 1057 | fp_control_status); |
e135b889 DJ |
1058 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1059 | ||
1060 | if (((cond >> cnum) & 0x01) == tf) | |
1061 | pc += mips32_relative_offset (inst) + 4; | |
1062 | else | |
1063 | pc += 8; | |
1064 | } | |
c5aa993b JM |
1065 | else |
1066 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1067 | } |
1068 | else | |
c5aa993b JM |
1069 | { /* This gets way messy */ |
1070 | ||
c906108c | 1071 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1072 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1073 | { |
c5aa993b JM |
1074 | case 0: /* SPECIAL */ |
1075 | op = rtype_funct (inst); | |
1076 | switch (op) | |
1077 | { | |
1078 | case 8: /* JR */ | |
1079 | case 9: /* JALR */ | |
6c997a34 | 1080 | /* Set PC to that address */ |
0b1b3e42 | 1081 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1082 | break; |
e38d4e1a DJ |
1083 | case 12: /* SYSCALL */ |
1084 | { | |
1085 | struct gdbarch_tdep *tdep; | |
1086 | ||
1087 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1088 | if (tdep->syscall_next_pc != NULL) | |
1089 | pc = tdep->syscall_next_pc (frame); | |
1090 | else | |
1091 | pc += 4; | |
1092 | } | |
1093 | break; | |
c5aa993b JM |
1094 | default: |
1095 | pc += 4; | |
1096 | } | |
1097 | ||
6d82d43b | 1098 | break; /* end SPECIAL */ |
c5aa993b | 1099 | case 1: /* REGIMM */ |
c906108c | 1100 | { |
e135b889 DJ |
1101 | op = itype_rt (inst); /* branch condition */ |
1102 | switch (op) | |
c906108c | 1103 | { |
c5aa993b | 1104 | case 0: /* BLTZ */ |
e135b889 DJ |
1105 | case 2: /* BLTZL */ |
1106 | case 16: /* BLTZAL */ | |
c5aa993b | 1107 | case 18: /* BLTZALL */ |
c906108c | 1108 | less_branch: |
0b1b3e42 | 1109 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1110 | pc += mips32_relative_offset (inst) + 4; |
1111 | else | |
1112 | pc += 8; /* after the delay slot */ | |
1113 | break; | |
e135b889 | 1114 | case 1: /* BGEZ */ |
c5aa993b JM |
1115 | case 3: /* BGEZL */ |
1116 | case 17: /* BGEZAL */ | |
1117 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1118 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1119 | pc += mips32_relative_offset (inst) + 4; |
1120 | else | |
1121 | pc += 8; /* after the delay slot */ | |
1122 | break; | |
e135b889 | 1123 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1124 | default: |
1125 | pc += 4; | |
c906108c SS |
1126 | } |
1127 | } | |
6d82d43b | 1128 | break; /* end REGIMM */ |
c5aa993b JM |
1129 | case 2: /* J */ |
1130 | case 3: /* JAL */ | |
1131 | { | |
1132 | unsigned long reg; | |
1133 | reg = jtype_target (inst) << 2; | |
e135b889 | 1134 | /* Upper four bits get never changed... */ |
5b652102 | 1135 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1136 | } |
c5aa993b JM |
1137 | break; |
1138 | /* FIXME case JALX : */ | |
1139 | { | |
1140 | unsigned long reg; | |
1141 | reg = jtype_target (inst) << 2; | |
5b652102 | 1142 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1143 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1144 | } | |
c5aa993b | 1145 | break; /* The new PC will be alternate mode */ |
e135b889 | 1146 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1147 | equal_branch: |
0b1b3e42 UW |
1148 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1149 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1150 | pc += mips32_relative_offset (inst) + 4; |
1151 | else | |
1152 | pc += 8; | |
1153 | break; | |
e135b889 | 1154 | case 5: /* BNE, BNEL */ |
c5aa993b | 1155 | neq_branch: |
0b1b3e42 UW |
1156 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1157 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1158 | pc += mips32_relative_offset (inst) + 4; |
1159 | else | |
1160 | pc += 8; | |
1161 | break; | |
e135b889 | 1162 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1163 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1164 | pc += mips32_relative_offset (inst) + 4; |
1165 | else | |
1166 | pc += 8; | |
1167 | break; | |
1168 | case 7: | |
e135b889 DJ |
1169 | default: |
1170 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1171 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1172 | pc += mips32_relative_offset (inst) + 4; |
1173 | else | |
1174 | pc += 8; | |
1175 | break; | |
c5aa993b JM |
1176 | } /* switch */ |
1177 | } /* else */ | |
1178 | return pc; | |
1179 | } /* mips32_next_pc */ | |
c906108c SS |
1180 | |
1181 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1182 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1183 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1184 | We dont want to set a single step instruction on the extend instruction | |
1185 | either. | |
c5aa993b | 1186 | */ |
c906108c SS |
1187 | |
1188 | /* Lots of mips16 instruction formats */ | |
1189 | /* Predicting jumps requires itype,ritype,i8type | |
1190 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1191 | */ |
c906108c SS |
1192 | enum mips16_inst_fmts |
1193 | { | |
c5aa993b JM |
1194 | itype, /* 0 immediate 5,10 */ |
1195 | ritype, /* 1 5,3,8 */ | |
1196 | rrtype, /* 2 5,3,3,5 */ | |
1197 | rritype, /* 3 5,3,3,5 */ | |
1198 | rrrtype, /* 4 5,3,3,3,2 */ | |
1199 | rriatype, /* 5 5,3,3,1,4 */ | |
1200 | shifttype, /* 6 5,3,3,3,2 */ | |
1201 | i8type, /* 7 5,3,8 */ | |
1202 | i8movtype, /* 8 5,3,3,5 */ | |
1203 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1204 | i64type, /* 10 5,3,8 */ | |
1205 | ri64type, /* 11 5,3,3,5 */ | |
1206 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1207 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1208 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1209 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1210 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1211 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1212 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1213 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1214 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1215 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1216 | }; | |
12f02c2a AC |
1217 | /* I am heaping all the fields of the formats into one structure and |
1218 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1219 | struct upk_mips16 |
6d82d43b AC |
1220 | { |
1221 | CORE_ADDR offset; | |
1222 | unsigned int regx; /* Function in i8 type */ | |
1223 | unsigned int regy; | |
1224 | }; | |
c906108c SS |
1225 | |
1226 | ||
12f02c2a | 1227 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1228 | for the bits which make up the immediate extension. */ |
c906108c | 1229 | |
12f02c2a AC |
1230 | static CORE_ADDR |
1231 | extended_offset (unsigned int extension) | |
c906108c | 1232 | { |
12f02c2a | 1233 | CORE_ADDR value; |
c5aa993b JM |
1234 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1235 | value = value << 6; | |
1236 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1237 | value = value << 5; | |
1238 | value |= extension & 0x01f; /* extract 4:0 */ | |
1239 | return value; | |
c906108c SS |
1240 | } |
1241 | ||
1242 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1243 | instruction. It won't malfunction, but why make excess remote memory |
1244 | references? If the immediate operands get sign extended or something, | |
1245 | do it after the extension is performed. */ | |
c906108c | 1246 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1247 | when the offset is to be used in relative addressing. */ |
c906108c | 1248 | |
12f02c2a | 1249 | static unsigned int |
e17a4113 | 1250 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1251 | { |
e17a4113 | 1252 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1253 | gdb_byte buf[8]; |
c5aa993b JM |
1254 | pc &= 0xfffffffe; /* clear the low order bit */ |
1255 | target_read_memory (pc, buf, 2); | |
e17a4113 | 1256 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1257 | } |
1258 | ||
1259 | static void | |
e17a4113 | 1260 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1261 | unsigned int extension, |
1262 | unsigned int inst, | |
6d82d43b | 1263 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1264 | { |
12f02c2a AC |
1265 | CORE_ADDR offset; |
1266 | int regx; | |
1267 | int regy; | |
1268 | switch (insn_format) | |
c906108c | 1269 | { |
c5aa993b | 1270 | case itype: |
c906108c | 1271 | { |
12f02c2a AC |
1272 | CORE_ADDR value; |
1273 | if (extension) | |
c5aa993b JM |
1274 | { |
1275 | value = extended_offset (extension); | |
1276 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1277 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1278 | } |
1279 | else | |
c5aa993b | 1280 | { |
12f02c2a | 1281 | value = inst & 0x7ff; |
c5aa993b | 1282 | /* FIXME : Consider sign extension */ |
c906108c | 1283 | } |
12f02c2a AC |
1284 | offset = value; |
1285 | regx = -1; | |
1286 | regy = -1; | |
c906108c | 1287 | } |
c5aa993b JM |
1288 | break; |
1289 | case ritype: | |
1290 | case i8type: | |
1291 | { /* A register identifier and an offset */ | |
c906108c SS |
1292 | /* Most of the fields are the same as I type but the |
1293 | immediate value is of a different length */ | |
12f02c2a AC |
1294 | CORE_ADDR value; |
1295 | if (extension) | |
c906108c | 1296 | { |
c5aa993b JM |
1297 | value = extended_offset (extension); |
1298 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1299 | value |= inst & 0xff; /* eleven bits from instruction */ |
1300 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1301 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1302 | { | |
1303 | value &= ~0x3fff; /* remove the sign bit */ | |
1304 | value = -value; | |
c906108c SS |
1305 | } |
1306 | } | |
c5aa993b JM |
1307 | else |
1308 | { | |
12f02c2a AC |
1309 | value = inst & 0xff; /* 8 bits */ |
1310 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1311 | /* FIXME: Do sign extension , this format needs it */ |
1312 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1313 | { | |
1314 | value &= 0xef; /* remove the sign bit */ | |
1315 | value = -value; | |
1316 | } | |
c5aa993b | 1317 | } |
12f02c2a AC |
1318 | offset = value; |
1319 | regy = -1; | |
c5aa993b | 1320 | break; |
c906108c | 1321 | } |
c5aa993b | 1322 | case jalxtype: |
c906108c | 1323 | { |
c5aa993b | 1324 | unsigned long value; |
12f02c2a AC |
1325 | unsigned int nexthalf; |
1326 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1327 | value = value << 16; |
e17a4113 | 1328 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit still set */ |
c5aa993b | 1329 | value |= nexthalf; |
12f02c2a AC |
1330 | offset = value; |
1331 | regx = -1; | |
1332 | regy = -1; | |
c5aa993b | 1333 | break; |
c906108c SS |
1334 | } |
1335 | default: | |
e2e0b3e5 | 1336 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1337 | } |
12f02c2a AC |
1338 | upk->offset = offset; |
1339 | upk->regx = regx; | |
1340 | upk->regy = regy; | |
c906108c SS |
1341 | } |
1342 | ||
1343 | ||
c5aa993b JM |
1344 | static CORE_ADDR |
1345 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1346 | { |
5b652102 | 1347 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1348 | } |
1349 | ||
12f02c2a | 1350 | static CORE_ADDR |
0b1b3e42 | 1351 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1352 | unsigned int extension, unsigned int insn) |
c906108c | 1353 | { |
e17a4113 | 1354 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1355 | int op = (insn >> 11); |
1356 | switch (op) | |
c906108c | 1357 | { |
6d82d43b | 1358 | case 2: /* Branch */ |
12f02c2a AC |
1359 | { |
1360 | CORE_ADDR offset; | |
1361 | struct upk_mips16 upk; | |
e17a4113 | 1362 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
12f02c2a AC |
1363 | offset = upk.offset; |
1364 | if (offset & 0x800) | |
1365 | { | |
1366 | offset &= 0xeff; | |
1367 | offset = -offset; | |
1368 | } | |
1369 | pc += (offset << 1) + 2; | |
1370 | break; | |
1371 | } | |
6d82d43b | 1372 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1373 | { |
1374 | struct upk_mips16 upk; | |
e17a4113 | 1375 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1376 | pc = add_offset_16 (pc, upk.offset); |
1377 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1378 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1379 | else | |
1380 | pc |= 0x01; | |
1381 | break; | |
1382 | } | |
6d82d43b | 1383 | case 4: /* beqz */ |
12f02c2a AC |
1384 | { |
1385 | struct upk_mips16 upk; | |
1386 | int reg; | |
e17a4113 | 1387 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1388 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1389 | if (reg == 0) |
1390 | pc += (upk.offset << 1) + 2; | |
1391 | else | |
1392 | pc += 2; | |
1393 | break; | |
1394 | } | |
6d82d43b | 1395 | case 5: /* bnez */ |
12f02c2a AC |
1396 | { |
1397 | struct upk_mips16 upk; | |
1398 | int reg; | |
e17a4113 | 1399 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1400 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1401 | if (reg != 0) |
1402 | pc += (upk.offset << 1) + 2; | |
1403 | else | |
1404 | pc += 2; | |
1405 | break; | |
1406 | } | |
6d82d43b | 1407 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1408 | { |
1409 | struct upk_mips16 upk; | |
1410 | int reg; | |
e17a4113 | 1411 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1412 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1413 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1414 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1415 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1416 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1417 | pc += (upk.offset << 1) + 2; | |
1418 | else | |
1419 | pc += 2; | |
1420 | break; | |
1421 | } | |
6d82d43b | 1422 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1423 | { |
1424 | struct upk_mips16 upk; | |
1425 | /* upk.fmt = rrtype; */ | |
1426 | op = insn & 0x1f; | |
1427 | if (op == 0) | |
c5aa993b | 1428 | { |
12f02c2a AC |
1429 | int reg; |
1430 | upk.regx = (insn >> 8) & 0x07; | |
1431 | upk.regy = (insn >> 5) & 0x07; | |
1432 | switch (upk.regy) | |
c5aa993b | 1433 | { |
12f02c2a AC |
1434 | case 0: |
1435 | reg = upk.regx; | |
1436 | break; | |
1437 | case 1: | |
1438 | reg = 31; | |
6d82d43b | 1439 | break; /* Function return instruction */ |
12f02c2a AC |
1440 | case 2: |
1441 | reg = upk.regx; | |
1442 | break; | |
1443 | default: | |
1444 | reg = 31; | |
6d82d43b | 1445 | break; /* BOGUS Guess */ |
c906108c | 1446 | } |
0b1b3e42 | 1447 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1448 | } |
12f02c2a | 1449 | else |
c5aa993b | 1450 | pc += 2; |
12f02c2a AC |
1451 | break; |
1452 | } | |
1453 | case 30: | |
1454 | /* This is an instruction extension. Fetch the real instruction | |
1455 | (which follows the extension) and decode things based on | |
1456 | that. */ | |
1457 | { | |
1458 | pc += 2; | |
e17a4113 UW |
1459 | pc = extended_mips16_next_pc (frame, pc, insn, |
1460 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1461 | break; |
1462 | } | |
1463 | default: | |
1464 | { | |
1465 | pc += 2; | |
1466 | break; | |
1467 | } | |
c906108c | 1468 | } |
c5aa993b | 1469 | return pc; |
12f02c2a | 1470 | } |
c906108c | 1471 | |
5a89d8aa | 1472 | static CORE_ADDR |
0b1b3e42 | 1473 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1474 | { |
e17a4113 UW |
1475 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1476 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1477 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1478 | } |
1479 | ||
1480 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1481 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1482 | It works by decoding the current instruction and predicting where a |
1483 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1484 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1485 | static CORE_ADDR |
0b1b3e42 | 1486 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1487 | { |
ce1f96de | 1488 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1489 | return mips16_next_pc (frame, pc); |
c5aa993b | 1490 | else |
0b1b3e42 | 1491 | return mips32_next_pc (frame, pc); |
12f02c2a | 1492 | } |
c906108c | 1493 | |
edfae063 AC |
1494 | struct mips_frame_cache |
1495 | { | |
1496 | CORE_ADDR base; | |
1497 | struct trad_frame_saved_reg *saved_regs; | |
1498 | }; | |
1499 | ||
29639122 JB |
1500 | /* Set a register's saved stack address in temp_saved_regs. If an |
1501 | address has already been set for this register, do nothing; this | |
1502 | way we will only recognize the first save of a given register in a | |
1503 | function prologue. | |
eec63939 | 1504 | |
f57d151a UW |
1505 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1506 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1507 | Strictly speaking, only the second range is used as it is only second | |
1508 | range (the ABI instead of ISA registers) that comes into play when finding | |
1509 | saved registers in a frame. */ | |
eec63939 AC |
1510 | |
1511 | static void | |
74ed0bb4 MD |
1512 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1513 | int regnum, CORE_ADDR offset) | |
eec63939 | 1514 | { |
29639122 JB |
1515 | if (this_cache != NULL |
1516 | && this_cache->saved_regs[regnum].addr == -1) | |
1517 | { | |
74ed0bb4 MD |
1518 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1519 | = offset; | |
1520 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1521 | = offset; | |
29639122 | 1522 | } |
eec63939 AC |
1523 | } |
1524 | ||
eec63939 | 1525 | |
29639122 JB |
1526 | /* Fetch the immediate value from a MIPS16 instruction. |
1527 | If the previous instruction was an EXTEND, use it to extend | |
1528 | the upper bits of the immediate value. This is a helper function | |
1529 | for mips16_scan_prologue. */ | |
eec63939 | 1530 | |
29639122 JB |
1531 | static int |
1532 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1533 | unsigned short inst, /* current instruction */ | |
1534 | int nbits, /* number of bits in imm field */ | |
1535 | int scale, /* scale factor to be applied to imm */ | |
1536 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1537 | { |
29639122 | 1538 | int offset; |
eec63939 | 1539 | |
29639122 JB |
1540 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1541 | { | |
1542 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1543 | if (offset & 0x8000) /* check for negative extend */ | |
1544 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1545 | return offset | (inst & 0x1f); | |
1546 | } | |
eec63939 | 1547 | else |
29639122 JB |
1548 | { |
1549 | int max_imm = 1 << nbits; | |
1550 | int mask = max_imm - 1; | |
1551 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1552 | |
29639122 JB |
1553 | offset = inst & mask; |
1554 | if (is_signed && (offset & sign_bit)) | |
1555 | offset = 0 - (max_imm - offset); | |
1556 | return offset * scale; | |
1557 | } | |
1558 | } | |
eec63939 | 1559 | |
65596487 | 1560 | |
29639122 JB |
1561 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1562 | the associated FRAME_CACHE if not null. | |
1563 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1564 | |
29639122 | 1565 | static CORE_ADDR |
e17a4113 UW |
1566 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1567 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1568 | struct frame_info *this_frame, |
29639122 JB |
1569 | struct mips_frame_cache *this_cache) |
1570 | { | |
1571 | CORE_ADDR cur_pc; | |
1572 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1573 | CORE_ADDR sp; | |
1574 | long frame_offset = 0; /* Size of stack frame. */ | |
1575 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1576 | int frame_reg = MIPS_SP_REGNUM; | |
1577 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1578 | unsigned inst = 0; /* current instruction */ | |
1579 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1580 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1581 | int reg, offset; |
a343eb3c | 1582 | |
29639122 JB |
1583 | int extend_bytes = 0; |
1584 | int prev_extend_bytes; | |
1585 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1586 | |
29639122 | 1587 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1588 | THIS_FRAME. */ |
1589 | if (this_frame != NULL) | |
1590 | sp = get_frame_register_signed (this_frame, | |
1591 | gdbarch_num_regs (gdbarch) | |
1592 | + MIPS_SP_REGNUM); | |
29639122 JB |
1593 | else |
1594 | sp = 0; | |
eec63939 | 1595 | |
29639122 JB |
1596 | if (limit_pc > start_pc + 200) |
1597 | limit_pc = start_pc + 200; | |
eec63939 | 1598 | |
95ac2dcf | 1599 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1600 | { |
1601 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1602 | the immediate offset extension from it in mips16_get_imm. */ | |
1603 | prev_inst = inst; | |
eec63939 | 1604 | |
29639122 | 1605 | /* Fetch and decode the instruction. */ |
e17a4113 | 1606 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1607 | |
29639122 JB |
1608 | /* Normally we ignore extend instructions. However, if it is |
1609 | not followed by a valid prologue instruction, then this | |
1610 | instruction is not part of the prologue either. We must | |
1611 | remember in this case to adjust the end_prologue_addr back | |
1612 | over the extend. */ | |
1613 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1614 | { | |
95ac2dcf | 1615 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1616 | continue; |
1617 | } | |
eec63939 | 1618 | |
29639122 JB |
1619 | prev_extend_bytes = extend_bytes; |
1620 | extend_bytes = 0; | |
eec63939 | 1621 | |
29639122 JB |
1622 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1623 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1624 | { | |
1625 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1626 | if (offset < 0) /* negative stack adjustment? */ | |
1627 | frame_offset -= offset; | |
1628 | else | |
1629 | /* Exit loop if a positive stack adjustment is found, which | |
1630 | usually means that the stack cleanup code in the function | |
1631 | epilogue is reached. */ | |
1632 | break; | |
1633 | } | |
1634 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1635 | { | |
1636 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1637 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1638 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1639 | } |
1640 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1641 | { | |
1642 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1643 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1644 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1645 | } |
1646 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1647 | { | |
1648 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1649 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1650 | } |
1651 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1652 | { | |
1653 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1654 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1655 | } |
1656 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1657 | { | |
1658 | frame_addr = sp; | |
1659 | frame_reg = 17; | |
1660 | } | |
1661 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1662 | { | |
1663 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1664 | frame_addr = sp + offset; | |
1665 | frame_reg = 17; | |
1666 | frame_adjust = offset; | |
1667 | } | |
1668 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1669 | { | |
1670 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1671 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1672 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1673 | } |
1674 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1675 | { | |
1676 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1677 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1678 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1679 | } |
1680 | else if ((inst & 0xf81f) == 0xe809 | |
1681 | && (inst & 0x700) != 0x700) /* entry */ | |
1682 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1683 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1684 | { | |
1685 | save_inst = inst; /* save for later processing */ | |
1686 | if (prev_extend_bytes) /* extend */ | |
1687 | save_inst |= prev_inst << 16; | |
1688 | } | |
29639122 | 1689 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1690 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1691 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1692 | { | |
1693 | /* This instruction is part of the prologue, but we don't | |
1694 | need to do anything special to handle it. */ | |
1695 | } | |
1696 | else | |
1697 | { | |
1698 | /* This instruction is not an instruction typically found | |
1699 | in a prologue, so we must have reached the end of the | |
1700 | prologue. */ | |
1701 | if (end_prologue_addr == 0) | |
1702 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1703 | } | |
1704 | } | |
eec63939 | 1705 | |
29639122 JB |
1706 | /* The entry instruction is typically the first instruction in a function, |
1707 | and it stores registers at offsets relative to the value of the old SP | |
1708 | (before the prologue). But the value of the sp parameter to this | |
1709 | function is the new SP (after the prologue has been executed). So we | |
1710 | can't calculate those offsets until we've seen the entire prologue, | |
1711 | and can calculate what the old SP must have been. */ | |
1712 | if (entry_inst != 0) | |
1713 | { | |
1714 | int areg_count = (entry_inst >> 8) & 7; | |
1715 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1716 | |
29639122 JB |
1717 | /* The entry instruction always subtracts 32 from the SP. */ |
1718 | frame_offset += 32; | |
1719 | ||
1720 | /* Now we can calculate what the SP must have been at the | |
1721 | start of the function prologue. */ | |
1722 | sp += frame_offset; | |
1723 | ||
1724 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1725 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1726 | { | |
74ed0bb4 | 1727 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1728 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1729 | } |
1730 | ||
1731 | /* Check if the ra register was pushed on the stack. */ | |
1732 | offset = -4; | |
1733 | if (entry_inst & 0x20) | |
1734 | { | |
74ed0bb4 | 1735 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1736 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1737 | } |
1738 | ||
1739 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1740 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1741 | { | |
74ed0bb4 | 1742 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1743 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1744 | } |
1745 | } | |
1746 | ||
2207132d MR |
1747 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1748 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1749 | size of the frame is specified as an immediate field of instruction | |
1750 | and an extended variation exists which lets additional registers and | |
1751 | frame space to be specified. The instruction always treats registers | |
1752 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1753 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1754 | { | |
1755 | static int args_table[16] = { | |
1756 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1757 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1758 | }; | |
1759 | static int astatic_table[16] = { | |
1760 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1761 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1762 | }; | |
1763 | int aregs = (save_inst >> 16) & 0xf; | |
1764 | int xsregs = (save_inst >> 24) & 0x7; | |
1765 | int args = args_table[aregs]; | |
1766 | int astatic = astatic_table[aregs]; | |
1767 | long frame_size; | |
1768 | ||
1769 | if (args < 0) | |
1770 | { | |
1771 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1772 | args = 0; | |
1773 | } | |
1774 | if (astatic < 0) | |
1775 | { | |
1776 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1777 | astatic = 0; | |
1778 | } | |
1779 | ||
1780 | /* For standard SAVE the frame size of 0 means 128. */ | |
1781 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1782 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1783 | frame_size = 16; | |
1784 | frame_size *= 8; | |
1785 | frame_offset += frame_size; | |
1786 | ||
1787 | /* Now we can calculate what the SP must have been at the | |
1788 | start of the function prologue. */ | |
1789 | sp += frame_offset; | |
1790 | ||
1791 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1792 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1793 | { | |
74ed0bb4 | 1794 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1795 | offset += mips_abi_regsize (gdbarch); |
1796 | } | |
1797 | ||
1798 | offset = -4; | |
1799 | ||
1800 | /* Check if the RA register was pushed on the stack. */ | |
1801 | if (save_inst & 0x40) | |
1802 | { | |
74ed0bb4 | 1803 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1804 | offset -= mips_abi_regsize (gdbarch); |
1805 | } | |
1806 | ||
1807 | /* Check if the S8 register was pushed on the stack. */ | |
1808 | if (xsregs > 6) | |
1809 | { | |
74ed0bb4 | 1810 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1811 | offset -= mips_abi_regsize (gdbarch); |
1812 | xsregs--; | |
1813 | } | |
1814 | /* Check if S2-S7 were pushed on the stack. */ | |
1815 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1816 | { | |
74ed0bb4 | 1817 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1818 | offset -= mips_abi_regsize (gdbarch); |
1819 | } | |
1820 | ||
1821 | /* Check if the S1 register was pushed on the stack. */ | |
1822 | if (save_inst & 0x10) | |
1823 | { | |
74ed0bb4 | 1824 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1825 | offset -= mips_abi_regsize (gdbarch); |
1826 | } | |
1827 | /* Check if the S0 register was pushed on the stack. */ | |
1828 | if (save_inst & 0x20) | |
1829 | { | |
74ed0bb4 | 1830 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1831 | offset -= mips_abi_regsize (gdbarch); |
1832 | } | |
1833 | ||
1834 | /* Check if A0-A3 were pushed on the stack. */ | |
1835 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1836 | { | |
74ed0bb4 | 1837 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1838 | offset -= mips_abi_regsize (gdbarch); |
1839 | } | |
1840 | } | |
1841 | ||
29639122 JB |
1842 | if (this_cache != NULL) |
1843 | { | |
1844 | this_cache->base = | |
b8a22b94 DJ |
1845 | (get_frame_register_signed (this_frame, |
1846 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1847 | + frame_offset - frame_adjust); |
1848 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1849 | be able to get rid of the assignment below, evetually. But it's | |
1850 | still needed for now. */ | |
72a155b4 UW |
1851 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1852 | + mips_regnum (gdbarch)->pc] | |
1853 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1854 | } |
1855 | ||
1856 | /* If we didn't reach the end of the prologue when scanning the function | |
1857 | instructions, then set end_prologue_addr to the address of the | |
1858 | instruction immediately after the last one we scanned. */ | |
1859 | if (end_prologue_addr == 0) | |
1860 | end_prologue_addr = cur_pc; | |
1861 | ||
1862 | return end_prologue_addr; | |
eec63939 AC |
1863 | } |
1864 | ||
29639122 JB |
1865 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1866 | Procedures that use the 32-bit instruction set are handled by the | |
1867 | mips_insn32 unwinder. */ | |
1868 | ||
1869 | static struct mips_frame_cache * | |
b8a22b94 | 1870 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1871 | { |
e17a4113 | 1872 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1873 | struct mips_frame_cache *cache; |
eec63939 AC |
1874 | |
1875 | if ((*this_cache) != NULL) | |
1876 | return (*this_cache); | |
29639122 JB |
1877 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1878 | (*this_cache) = cache; | |
b8a22b94 | 1879 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1880 | |
29639122 JB |
1881 | /* Analyze the function prologue. */ |
1882 | { | |
b8a22b94 | 1883 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1884 | CORE_ADDR start_addr; |
eec63939 | 1885 | |
29639122 JB |
1886 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1887 | if (start_addr == 0) | |
e17a4113 | 1888 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1889 | /* We can't analyze the prologue if we couldn't find the begining |
1890 | of the function. */ | |
1891 | if (start_addr == 0) | |
1892 | return cache; | |
eec63939 | 1893 | |
e17a4113 | 1894 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1895 | } |
1896 | ||
3e8c568d | 1897 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1898 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1899 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1900 | cache->base); |
eec63939 | 1901 | |
29639122 | 1902 | return (*this_cache); |
eec63939 AC |
1903 | } |
1904 | ||
1905 | static void | |
b8a22b94 | 1906 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1907 | struct frame_id *this_id) |
eec63939 | 1908 | { |
b8a22b94 | 1909 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1910 | this_cache); |
21327321 DJ |
1911 | /* This marks the outermost frame. */ |
1912 | if (info->base == 0) | |
1913 | return; | |
b8a22b94 | 1914 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1915 | } |
1916 | ||
b8a22b94 DJ |
1917 | static struct value * |
1918 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1919 | void **this_cache, int regnum) | |
eec63939 | 1920 | { |
b8a22b94 | 1921 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1922 | this_cache); |
b8a22b94 DJ |
1923 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1924 | } | |
1925 | ||
1926 | static int | |
1927 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1928 | struct frame_info *this_frame, void **this_cache) | |
1929 | { | |
1930 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1931 | if (mips_pc_is_mips16 (pc)) | |
1932 | return 1; | |
1933 | return 0; | |
eec63939 AC |
1934 | } |
1935 | ||
29639122 | 1936 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1937 | { |
1938 | NORMAL_FRAME, | |
29639122 | 1939 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1940 | mips_insn16_frame_prev_register, |
1941 | NULL, | |
1942 | mips_insn16_frame_sniffer | |
eec63939 AC |
1943 | }; |
1944 | ||
eec63939 | 1945 | static CORE_ADDR |
b8a22b94 | 1946 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1947 | void **this_cache) |
eec63939 | 1948 | { |
b8a22b94 | 1949 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1950 | this_cache); |
1951 | return info->base; | |
eec63939 AC |
1952 | } |
1953 | ||
29639122 | 1954 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1955 | { |
29639122 JB |
1956 | &mips_insn16_frame_unwind, |
1957 | mips_insn16_frame_base_address, | |
1958 | mips_insn16_frame_base_address, | |
1959 | mips_insn16_frame_base_address | |
eec63939 AC |
1960 | }; |
1961 | ||
1962 | static const struct frame_base * | |
b8a22b94 | 1963 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1964 | { |
b8a22b94 DJ |
1965 | CORE_ADDR pc = get_frame_pc (this_frame); |
1966 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1967 | return &mips_insn16_frame_base; |
eec63939 AC |
1968 | else |
1969 | return NULL; | |
edfae063 AC |
1970 | } |
1971 | ||
29639122 JB |
1972 | /* Mark all the registers as unset in the saved_regs array |
1973 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1974 | ||
74ed0bb4 MD |
1975 | static void |
1976 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 1977 | { |
29639122 JB |
1978 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1979 | return; | |
1980 | ||
1981 | { | |
74ed0bb4 | 1982 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 1983 | int i; |
64159455 | 1984 | |
29639122 JB |
1985 | for (i = 0; i < num_regs; i++) |
1986 | { | |
1987 | this_cache->saved_regs[i].addr = -1; | |
1988 | } | |
1989 | } | |
c906108c SS |
1990 | } |
1991 | ||
29639122 JB |
1992 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1993 | the associated FRAME_CACHE if not null. | |
1994 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1995 | |
875e1767 | 1996 | static CORE_ADDR |
e17a4113 UW |
1997 | mips32_scan_prologue (struct gdbarch *gdbarch, |
1998 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1999 | struct frame_info *this_frame, |
29639122 | 2000 | struct mips_frame_cache *this_cache) |
c906108c | 2001 | { |
29639122 JB |
2002 | CORE_ADDR cur_pc; |
2003 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
2004 | CORE_ADDR sp; | |
2005 | long frame_offset; | |
2006 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2007 | |
29639122 JB |
2008 | CORE_ADDR end_prologue_addr = 0; |
2009 | int seen_sp_adjust = 0; | |
2010 | int load_immediate_bytes = 0; | |
db5f024e | 2011 | int in_delay_slot = 0; |
7d1e6fb8 | 2012 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2013 | |
29639122 | 2014 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2015 | THIS_FRAME. */ |
2016 | if (this_frame != NULL) | |
2017 | sp = get_frame_register_signed (this_frame, | |
2018 | gdbarch_num_regs (gdbarch) | |
2019 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2020 | else |
29639122 | 2021 | sp = 0; |
9022177c | 2022 | |
29639122 JB |
2023 | if (limit_pc > start_pc + 200) |
2024 | limit_pc = start_pc + 200; | |
9022177c | 2025 | |
29639122 | 2026 | restart: |
9022177c | 2027 | |
29639122 | 2028 | frame_offset = 0; |
95ac2dcf | 2029 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2030 | { |
29639122 JB |
2031 | unsigned long inst, high_word, low_word; |
2032 | int reg; | |
9022177c | 2033 | |
29639122 | 2034 | /* Fetch the instruction. */ |
e17a4113 | 2035 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2036 | |
29639122 JB |
2037 | /* Save some code by pre-extracting some useful fields. */ |
2038 | high_word = (inst >> 16) & 0xffff; | |
2039 | low_word = inst & 0xffff; | |
2040 | reg = high_word & 0x1f; | |
fe29b929 | 2041 | |
29639122 JB |
2042 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
2043 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
2044 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2045 | { | |
2046 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
2047 | frame_offset += 0x10000 - low_word; | |
2048 | else | |
2049 | /* Exit loop if a positive stack adjustment is found, which | |
2050 | usually means that the stack cleanup code in the function | |
2051 | epilogue is reached. */ | |
2052 | break; | |
2053 | seen_sp_adjust = 1; | |
2054 | } | |
7d1e6fb8 KB |
2055 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2056 | && !regsize_is_64_bits) | |
29639122 | 2057 | { |
74ed0bb4 | 2058 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2059 | } |
7d1e6fb8 KB |
2060 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2061 | && regsize_is_64_bits) | |
29639122 JB |
2062 | { |
2063 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2064 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2065 | } |
2066 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2067 | { | |
2068 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2069 | if ((long) low_word != frame_offset) | |
2070 | frame_addr = sp + low_word; | |
b8a22b94 | 2071 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2072 | { |
2073 | unsigned alloca_adjust; | |
a4b8ebc8 | 2074 | |
29639122 | 2075 | frame_reg = 30; |
b8a22b94 DJ |
2076 | frame_addr = get_frame_register_signed |
2077 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2078 | |
29639122 JB |
2079 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2080 | if (alloca_adjust > 0) | |
2081 | { | |
2082 | /* FP > SP + frame_size. This may be because of | |
2083 | an alloca or somethings similar. Fix sp to | |
2084 | "pre-alloca" value, and try again. */ | |
2085 | sp += alloca_adjust; | |
2086 | /* Need to reset the status of all registers. Otherwise, | |
2087 | we will hit a guard that prevents the new address | |
2088 | for each register to be recomputed during the second | |
2089 | pass. */ | |
74ed0bb4 | 2090 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2091 | goto restart; |
2092 | } | |
2093 | } | |
2094 | } | |
2095 | /* move $30,$sp. With different versions of gas this will be either | |
2096 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2097 | Accept any one of these. */ | |
2098 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2099 | { | |
2100 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2101 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2102 | { |
2103 | unsigned alloca_adjust; | |
c906108c | 2104 | |
29639122 | 2105 | frame_reg = 30; |
b8a22b94 DJ |
2106 | frame_addr = get_frame_register_signed |
2107 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2108 | |
29639122 JB |
2109 | alloca_adjust = (unsigned) (frame_addr - sp); |
2110 | if (alloca_adjust > 0) | |
2111 | { | |
2112 | /* FP > SP + frame_size. This may be because of | |
2113 | an alloca or somethings similar. Fix sp to | |
2114 | "pre-alloca" value, and try again. */ | |
2115 | sp = frame_addr; | |
2116 | /* Need to reset the status of all registers. Otherwise, | |
2117 | we will hit a guard that prevents the new address | |
2118 | for each register to be recomputed during the second | |
2119 | pass. */ | |
74ed0bb4 | 2120 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2121 | goto restart; |
2122 | } | |
2123 | } | |
2124 | } | |
7d1e6fb8 KB |
2125 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2126 | && !regsize_is_64_bits) | |
29639122 | 2127 | { |
74ed0bb4 | 2128 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2129 | } |
2130 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2131 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2132 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2133 | || high_word == 0x3c1c /* lui $gp,n */ | |
2134 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2135 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2136 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2137 | ) | |
2138 | { | |
2139 | /* These instructions are part of the prologue, but we don't | |
2140 | need to do anything special to handle them. */ | |
2141 | } | |
2142 | /* The instructions below load $at or $t0 with an immediate | |
2143 | value in preparation for a stack adjustment via | |
2144 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2145 | initialize a local variable, so we accept them only before | |
2146 | a stack adjustment instruction was seen. */ | |
2147 | else if (!seen_sp_adjust | |
2148 | && (high_word == 0x3c01 /* lui $at,n */ | |
2149 | || high_word == 0x3c08 /* lui $t0,n */ | |
2150 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2151 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2152 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2153 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2154 | )) | |
2155 | { | |
95ac2dcf | 2156 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2157 | } |
2158 | else | |
2159 | { | |
2160 | /* This instruction is not an instruction typically found | |
2161 | in a prologue, so we must have reached the end of the | |
2162 | prologue. */ | |
2163 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2164 | loop now? Why would we need to continue scanning the function | |
2165 | instructions? */ | |
2166 | if (end_prologue_addr == 0) | |
2167 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2168 | |
2169 | /* Check for branches and jumps. For now, only jump to | |
2170 | register are caught (i.e. returns). */ | |
2171 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2172 | in_delay_slot = 1; | |
29639122 | 2173 | } |
db5f024e DJ |
2174 | |
2175 | /* If the previous instruction was a jump, we must have reached | |
2176 | the end of the prologue by now. Stop scanning so that we do | |
2177 | not go past the function return. */ | |
2178 | if (in_delay_slot) | |
2179 | break; | |
a4b8ebc8 | 2180 | } |
c906108c | 2181 | |
29639122 JB |
2182 | if (this_cache != NULL) |
2183 | { | |
2184 | this_cache->base = | |
b8a22b94 DJ |
2185 | (get_frame_register_signed (this_frame, |
2186 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2187 | + frame_offset); |
2188 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2189 | this assignment below, eventually. But it's still needed | |
2190 | for now. */ | |
72a155b4 UW |
2191 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2192 | + mips_regnum (gdbarch)->pc] | |
2193 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2194 | + MIPS_RA_REGNUM]; |
29639122 | 2195 | } |
c906108c | 2196 | |
29639122 JB |
2197 | /* If we didn't reach the end of the prologue when scanning the function |
2198 | instructions, then set end_prologue_addr to the address of the | |
2199 | instruction immediately after the last one we scanned. */ | |
2200 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2201 | we may as well be careful and do our best if we have a null | |
2202 | end_prologue_addr. */ | |
2203 | if (end_prologue_addr == 0) | |
2204 | end_prologue_addr = cur_pc; | |
2205 | ||
2206 | /* In a frameless function, we might have incorrectly | |
2207 | skipped some load immediate instructions. Undo the skipping | |
2208 | if the load immediate was not followed by a stack adjustment. */ | |
2209 | if (load_immediate_bytes && !seen_sp_adjust) | |
2210 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2211 | |
29639122 | 2212 | return end_prologue_addr; |
c906108c SS |
2213 | } |
2214 | ||
29639122 JB |
2215 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2216 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2217 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2218 | unwinder. */ | |
c906108c | 2219 | |
29639122 | 2220 | static struct mips_frame_cache * |
b8a22b94 | 2221 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2222 | { |
e17a4113 | 2223 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2224 | struct mips_frame_cache *cache; |
c906108c | 2225 | |
29639122 JB |
2226 | if ((*this_cache) != NULL) |
2227 | return (*this_cache); | |
c5aa993b | 2228 | |
29639122 JB |
2229 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2230 | (*this_cache) = cache; | |
b8a22b94 | 2231 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2232 | |
29639122 JB |
2233 | /* Analyze the function prologue. */ |
2234 | { | |
b8a22b94 | 2235 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2236 | CORE_ADDR start_addr; |
c906108c | 2237 | |
29639122 JB |
2238 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2239 | if (start_addr == 0) | |
e17a4113 | 2240 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2241 | /* We can't analyze the prologue if we couldn't find the begining |
2242 | of the function. */ | |
2243 | if (start_addr == 0) | |
2244 | return cache; | |
c5aa993b | 2245 | |
e17a4113 | 2246 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2247 | } |
2248 | ||
3e8c568d | 2249 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2250 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2251 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2252 | cache->base); |
c5aa993b | 2253 | |
29639122 | 2254 | return (*this_cache); |
c906108c SS |
2255 | } |
2256 | ||
29639122 | 2257 | static void |
b8a22b94 | 2258 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2259 | struct frame_id *this_id) |
c906108c | 2260 | { |
b8a22b94 | 2261 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2262 | this_cache); |
21327321 DJ |
2263 | /* This marks the outermost frame. */ |
2264 | if (info->base == 0) | |
2265 | return; | |
b8a22b94 | 2266 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2267 | } |
c906108c | 2268 | |
b8a22b94 DJ |
2269 | static struct value * |
2270 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2271 | void **this_cache, int regnum) | |
29639122 | 2272 | { |
b8a22b94 | 2273 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2274 | this_cache); |
b8a22b94 DJ |
2275 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2276 | } | |
2277 | ||
2278 | static int | |
2279 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2280 | struct frame_info *this_frame, void **this_cache) | |
2281 | { | |
2282 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2283 | if (! mips_pc_is_mips16 (pc)) | |
2284 | return 1; | |
2285 | return 0; | |
c906108c SS |
2286 | } |
2287 | ||
29639122 JB |
2288 | static const struct frame_unwind mips_insn32_frame_unwind = |
2289 | { | |
2290 | NORMAL_FRAME, | |
2291 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2292 | mips_insn32_frame_prev_register, |
2293 | NULL, | |
2294 | mips_insn32_frame_sniffer | |
29639122 | 2295 | }; |
c906108c | 2296 | |
1c645fec | 2297 | static CORE_ADDR |
b8a22b94 | 2298 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2299 | void **this_cache) |
c906108c | 2300 | { |
b8a22b94 | 2301 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2302 | this_cache); |
2303 | return info->base; | |
2304 | } | |
c906108c | 2305 | |
29639122 JB |
2306 | static const struct frame_base mips_insn32_frame_base = |
2307 | { | |
2308 | &mips_insn32_frame_unwind, | |
2309 | mips_insn32_frame_base_address, | |
2310 | mips_insn32_frame_base_address, | |
2311 | mips_insn32_frame_base_address | |
2312 | }; | |
1c645fec | 2313 | |
29639122 | 2314 | static const struct frame_base * |
b8a22b94 | 2315 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2316 | { |
b8a22b94 DJ |
2317 | CORE_ADDR pc = get_frame_pc (this_frame); |
2318 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2319 | return &mips_insn32_frame_base; |
a65bbe44 | 2320 | else |
29639122 JB |
2321 | return NULL; |
2322 | } | |
a65bbe44 | 2323 | |
29639122 | 2324 | static struct trad_frame_cache * |
b8a22b94 | 2325 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2326 | { |
2327 | CORE_ADDR pc; | |
2328 | CORE_ADDR start_addr; | |
2329 | CORE_ADDR stack_addr; | |
2330 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2331 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2332 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2333 | |
29639122 JB |
2334 | if ((*this_cache) != NULL) |
2335 | return (*this_cache); | |
b8a22b94 | 2336 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2337 | (*this_cache) = this_trad_cache; |
1c645fec | 2338 | |
29639122 | 2339 | /* The return address is in the link register. */ |
3e8c568d | 2340 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2341 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2342 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2343 | |
29639122 JB |
2344 | /* Frame ID, since it's a frameless / stackless function, no stack |
2345 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2346 | pc = get_frame_pc (this_frame); |
29639122 | 2347 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2348 | stack_addr = get_frame_register_signed (this_frame, |
2349 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2350 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2351 | |
29639122 JB |
2352 | /* Assume that the frame's base is the same as the |
2353 | stack-pointer. */ | |
2354 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2355 | |
29639122 JB |
2356 | return this_trad_cache; |
2357 | } | |
c906108c | 2358 | |
29639122 | 2359 | static void |
b8a22b94 | 2360 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2361 | struct frame_id *this_id) |
2362 | { | |
2363 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2364 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2365 | trad_frame_get_id (this_trad_cache, this_id); |
2366 | } | |
c906108c | 2367 | |
b8a22b94 DJ |
2368 | static struct value * |
2369 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2370 | void **this_cache, int regnum) | |
29639122 JB |
2371 | { |
2372 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2373 | = mips_stub_frame_cache (this_frame, this_cache); |
2374 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2375 | } |
c906108c | 2376 | |
b8a22b94 DJ |
2377 | static int |
2378 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2379 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2380 | { |
aa6c981f | 2381 | gdb_byte dummy[4]; |
979b38e0 | 2382 | struct obj_section *s; |
b8a22b94 | 2383 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2384 | struct minimal_symbol *msym; |
979b38e0 | 2385 | |
aa6c981f | 2386 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2387 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2388 | return 1; | |
aa6c981f | 2389 | |
29639122 | 2390 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2391 | return 1; |
979b38e0 DJ |
2392 | |
2393 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2394 | s = find_pc_section (pc); | |
2395 | ||
2396 | if (s != NULL | |
2397 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2398 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2399 | return 1; |
979b38e0 | 2400 | |
db5f024e DJ |
2401 | /* Calling a PIC function from a non-PIC function passes through a |
2402 | stub. The stub for foo is named ".pic.foo". */ | |
2403 | msym = lookup_minimal_symbol_by_pc (pc); | |
2404 | if (msym != NULL | |
2405 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2406 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2407 | return 1; | |
2408 | ||
b8a22b94 | 2409 | return 0; |
29639122 | 2410 | } |
c906108c | 2411 | |
b8a22b94 DJ |
2412 | static const struct frame_unwind mips_stub_frame_unwind = |
2413 | { | |
2414 | NORMAL_FRAME, | |
2415 | mips_stub_frame_this_id, | |
2416 | mips_stub_frame_prev_register, | |
2417 | NULL, | |
2418 | mips_stub_frame_sniffer | |
2419 | }; | |
2420 | ||
29639122 | 2421 | static CORE_ADDR |
b8a22b94 | 2422 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2423 | void **this_cache) |
2424 | { | |
2425 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2426 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2427 | return trad_frame_get_this_base (this_trad_cache); |
2428 | } | |
0fce0821 | 2429 | |
29639122 JB |
2430 | static const struct frame_base mips_stub_frame_base = |
2431 | { | |
2432 | &mips_stub_frame_unwind, | |
2433 | mips_stub_frame_base_address, | |
2434 | mips_stub_frame_base_address, | |
2435 | mips_stub_frame_base_address | |
2436 | }; | |
2437 | ||
2438 | static const struct frame_base * | |
b8a22b94 | 2439 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2440 | { |
b8a22b94 | 2441 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2442 | return &mips_stub_frame_base; |
2443 | else | |
2444 | return NULL; | |
2445 | } | |
2446 | ||
29639122 | 2447 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2448 | |
29639122 | 2449 | static CORE_ADDR |
24568a2c | 2450 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2451 | { |
24568a2c | 2452 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29639122 JB |
2453 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2454 | /* This hack is a work-around for existing boards using PMON, the | |
2455 | simulator, and any other 64-bit targets that doesn't have true | |
2456 | 64-bit addressing. On these targets, the upper 32 bits of | |
2457 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2458 | likely to have been sign extended to all 1s by instruction | |
2459 | sequences that load 32-bit addresses. For example, a typical | |
2460 | piece of code that loads an address is this: | |
65596487 | 2461 | |
29639122 JB |
2462 | lui $r2, <upper 16 bits> |
2463 | ori $r2, <lower 16 bits> | |
65596487 | 2464 | |
29639122 JB |
2465 | But the lui sign-extends the value such that the upper 32 bits |
2466 | may be all 1s. The workaround is simply to mask off these | |
2467 | bits. In the future, gcc may be changed to support true 64-bit | |
2468 | addressing, and this masking will have to be disabled. */ | |
2469 | return addr &= 0xffffffffUL; | |
2470 | else | |
2471 | return addr; | |
65596487 JB |
2472 | } |
2473 | ||
3d5f6d12 DJ |
2474 | /* Instructions used during single-stepping of atomic sequences. */ |
2475 | #define LL_OPCODE 0x30 | |
2476 | #define LLD_OPCODE 0x34 | |
2477 | #define SC_OPCODE 0x38 | |
2478 | #define SCD_OPCODE 0x3c | |
2479 | ||
2480 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2481 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2482 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2483 | the sequence. */ | |
2484 | ||
2485 | static int | |
6c95b8df PA |
2486 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2487 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2488 | { |
2489 | CORE_ADDR breaks[2] = {-1, -1}; | |
2490 | CORE_ADDR loc = pc; | |
2491 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2492 | unsigned long insn; | |
2493 | int insn_count; | |
2494 | int index; | |
2495 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2496 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2497 | ||
2498 | if (pc & 0x01) | |
2499 | return 0; | |
2500 | ||
e17a4113 | 2501 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2502 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2503 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2504 | return 0; | |
2505 | ||
2506 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2507 | instructions. */ | |
2508 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2509 | { | |
2510 | int is_branch = 0; | |
2511 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2512 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2513 | |
2514 | /* Assume that there is at most one branch in the atomic | |
2515 | sequence. If a branch is found, put a breakpoint in its | |
2516 | destination address. */ | |
2517 | switch (itype_op (insn)) | |
2518 | { | |
2519 | case 0: /* SPECIAL */ | |
2520 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2521 | return 0; /* fallback to the standard single-step code. */ | |
2522 | break; | |
2523 | case 1: /* REGIMM */ | |
2524 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2525 | break; | |
2526 | case 2: /* J */ | |
2527 | case 3: /* JAL */ | |
2528 | return 0; /* fallback to the standard single-step code. */ | |
2529 | case 4: /* BEQ */ | |
2530 | case 5: /* BNE */ | |
2531 | case 6: /* BLEZ */ | |
2532 | case 7: /* BGTZ */ | |
2533 | case 20: /* BEQL */ | |
2534 | case 21: /* BNEL */ | |
2535 | case 22: /* BLEZL */ | |
2536 | case 23: /* BGTTL */ | |
2537 | is_branch = 1; | |
2538 | break; | |
2539 | case 17: /* COP1 */ | |
2540 | case 18: /* COP2 */ | |
2541 | case 19: /* COP3 */ | |
2542 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2543 | break; | |
2544 | } | |
2545 | if (is_branch) | |
2546 | { | |
2547 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2548 | if (last_breakpoint >= 1) | |
2549 | return 0; /* More than one branch found, fallback to the | |
2550 | standard single-step code. */ | |
2551 | breaks[1] = branch_bp; | |
2552 | last_breakpoint++; | |
2553 | } | |
2554 | ||
2555 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2556 | break; | |
2557 | } | |
2558 | ||
2559 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2560 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2561 | return 0; | |
2562 | ||
2563 | loc += MIPS_INSN32_SIZE; | |
2564 | ||
2565 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2566 | breaks[0] = loc; | |
2567 | ||
2568 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2569 | placed (branch instruction's destination) in the atomic sequence */ | |
2570 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2571 | last_breakpoint = 0; | |
2572 | ||
2573 | /* Effectively inserts the breakpoints. */ | |
2574 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2575 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2576 | |
2577 | return 1; | |
2578 | } | |
2579 | ||
29639122 JB |
2580 | /* mips_software_single_step() is called just before we want to resume |
2581 | the inferior, if we want to single-step it but there is no hardware | |
2582 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2583 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2584 | |
e6590a1b | 2585 | int |
0b1b3e42 | 2586 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2587 | { |
a6d9a66e | 2588 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2589 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2590 | CORE_ADDR pc, next_pc; |
65596487 | 2591 | |
0b1b3e42 | 2592 | pc = get_frame_pc (frame); |
6c95b8df | 2593 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2594 | return 1; |
2595 | ||
0b1b3e42 | 2596 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2597 | |
6c95b8df | 2598 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2599 | return 1; |
29639122 | 2600 | } |
a65bbe44 | 2601 | |
29639122 JB |
2602 | /* Test whether the PC points to the return instruction at the |
2603 | end of a function. */ | |
65596487 | 2604 | |
29639122 | 2605 | static int |
e17a4113 | 2606 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2607 | { |
0fe7e7c8 | 2608 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2609 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2610 | generates a "jr $ra"; other times it generates code to load | |
2611 | the return address from the stack to an accessible register (such | |
2612 | as $a3), then a "jr" using that register. This second case | |
2613 | is almost impossible to distinguish from an indirect jump | |
2614 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2615 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2616 | else |
e17a4113 | 2617 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2618 | } |
c906108c | 2619 | |
c906108c | 2620 | |
29639122 JB |
2621 | /* This fencepost looks highly suspicious to me. Removing it also |
2622 | seems suspicious as it could affect remote debugging across serial | |
2623 | lines. */ | |
c906108c | 2624 | |
29639122 | 2625 | static CORE_ADDR |
74ed0bb4 | 2626 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2627 | { |
2628 | CORE_ADDR start_pc; | |
2629 | CORE_ADDR fence; | |
2630 | int instlen; | |
2631 | int seen_adjsp = 0; | |
d6b48e9c | 2632 | struct inferior *inf; |
65596487 | 2633 | |
74ed0bb4 | 2634 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2635 | start_pc = pc; |
2636 | fence = start_pc - heuristic_fence_post; | |
2637 | if (start_pc == 0) | |
2638 | return 0; | |
65596487 | 2639 | |
29639122 JB |
2640 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2641 | fence = VM_MIN_ADDRESS; | |
65596487 | 2642 | |
95ac2dcf | 2643 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2644 | |
d6b48e9c PA |
2645 | inf = current_inferior (); |
2646 | ||
29639122 JB |
2647 | /* search back for previous return */ |
2648 | for (start_pc -= instlen;; start_pc -= instlen) | |
2649 | if (start_pc < fence) | |
2650 | { | |
2651 | /* It's not clear to me why we reach this point when | |
2652 | stop_soon, but with this test, at least we | |
2653 | don't print out warnings for every child forked (eg, on | |
2654 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2655 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2656 | { |
2657 | static int blurb_printed = 0; | |
98b4dd94 | 2658 | |
5af949e3 UW |
2659 | warning (_("GDB can't find the start of the function at %s."), |
2660 | paddress (gdbarch, pc)); | |
29639122 JB |
2661 | |
2662 | if (!blurb_printed) | |
2663 | { | |
2664 | /* This actually happens frequently in embedded | |
2665 | development, when you first connect to a board | |
2666 | and your stack pointer and pc are nowhere in | |
2667 | particular. This message needs to give people | |
2668 | in that situation enough information to | |
2669 | determine that it's no big deal. */ | |
2670 | printf_filtered ("\n\ | |
5af949e3 | 2671 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2672 | and thus can't determine the size of that function's stack frame.\n\ |
2673 | This means that GDB may be unable to access that stack frame, or\n\ | |
2674 | the frames below it.\n\ | |
2675 | This problem is most likely caused by an invalid program counter or\n\ | |
2676 | stack pointer.\n\ | |
2677 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2678 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2679 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2680 | heuristic-fence-post' command.\n", |
2681 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2682 | blurb_printed = 1; |
2683 | } | |
2684 | } | |
2685 | ||
2686 | return 0; | |
2687 | } | |
0fe7e7c8 | 2688 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2689 | { |
2690 | unsigned short inst; | |
2691 | ||
2692 | /* On MIPS16, any one of the following is likely to be the | |
2693 | start of a function: | |
193774b3 MR |
2694 | extend save |
2695 | save | |
29639122 JB |
2696 | entry |
2697 | addiu sp,-n | |
2698 | daddiu sp,-n | |
2699 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
e17a4113 | 2700 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2701 | if ((inst & 0xff80) == 0x6480) /* save */ |
2702 | { | |
2703 | if (start_pc - instlen >= fence) | |
2704 | { | |
e17a4113 | 2705 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2706 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2707 | start_pc -= instlen; | |
2708 | } | |
2709 | break; | |
2710 | } | |
2711 | else if (((inst & 0xf81f) == 0xe809 | |
2712 | && (inst & 0x700) != 0x700) /* entry */ | |
2713 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2714 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2715 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2716 | break; |
2717 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2718 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2719 | seen_adjsp = 1; | |
2720 | else | |
2721 | seen_adjsp = 0; | |
2722 | } | |
e17a4113 | 2723 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2724 | { |
4c7d22cb | 2725 | /* Skip return and its delay slot. */ |
95ac2dcf | 2726 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2727 | break; |
2728 | } | |
2729 | ||
2730 | return start_pc; | |
c906108c SS |
2731 | } |
2732 | ||
6c0d6680 DJ |
2733 | struct mips_objfile_private |
2734 | { | |
2735 | bfd_size_type size; | |
2736 | char *contents; | |
2737 | }; | |
2738 | ||
f09ded24 AC |
2739 | /* According to the current ABI, should the type be passed in a |
2740 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2741 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2742 | FP registers and, consequently this returns false - forces FP |
2743 | arguments into integer registers. */ | |
2744 | ||
2745 | static int | |
74ed0bb4 MD |
2746 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2747 | struct type *arg_type) | |
f09ded24 AC |
2748 | { |
2749 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2750 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2751 | && (typecode == TYPE_CODE_STRUCT |
2752 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2753 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2754 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2755 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2756 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2757 | } |
2758 | ||
49e790b0 DJ |
2759 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2760 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2761 | ||
2762 | static int | |
2763 | mips_type_needs_double_align (struct type *type) | |
2764 | { | |
2765 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2766 | |
49e790b0 DJ |
2767 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2768 | return 1; | |
2769 | else if (typecode == TYPE_CODE_STRUCT) | |
2770 | { | |
2771 | if (TYPE_NFIELDS (type) < 1) | |
2772 | return 0; | |
2773 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2774 | } | |
2775 | else if (typecode == TYPE_CODE_UNION) | |
2776 | { | |
361d1df0 | 2777 | int i, n; |
49e790b0 DJ |
2778 | |
2779 | n = TYPE_NFIELDS (type); | |
2780 | for (i = 0; i < n; i++) | |
2781 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2782 | return 1; | |
2783 | return 0; | |
2784 | } | |
2785 | return 0; | |
2786 | } | |
2787 | ||
dc604539 AC |
2788 | /* Adjust the address downward (direction of stack growth) so that it |
2789 | is correctly aligned for a new stack frame. */ | |
2790 | static CORE_ADDR | |
2791 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2792 | { | |
5b03f266 | 2793 | return align_down (addr, 16); |
dc604539 AC |
2794 | } |
2795 | ||
f7ab6ec6 | 2796 | static CORE_ADDR |
7d9b040b | 2797 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2798 | struct regcache *regcache, CORE_ADDR bp_addr, |
2799 | int nargs, struct value **args, CORE_ADDR sp, | |
2800 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2801 | { |
2802 | int argreg; | |
2803 | int float_argreg; | |
2804 | int argnum; | |
2805 | int len = 0; | |
2806 | int stack_offset = 0; | |
480d3dd2 | 2807 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2808 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2809 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2810 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2811 | |
25ab4790 AC |
2812 | /* For shared libraries, "t9" needs to point at the function |
2813 | address. */ | |
4c7d22cb | 2814 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2815 | |
2816 | /* Set the return address register to point to the entry point of | |
2817 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2818 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2819 | |
c906108c | 2820 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2821 | are properly aligned. The stack has to be at least 64-bit |
2822 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2823 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2824 | aligned, so we round to this widest known alignment. */ | |
2825 | ||
5b03f266 AC |
2826 | sp = align_down (sp, 16); |
2827 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2828 | |
46e0f506 | 2829 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2830 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2831 | passed in registers, but that's OK. */ |
c906108c | 2832 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2833 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2834 | sp -= align_up (len, 16); |
c906108c | 2835 | |
9ace0497 | 2836 | if (mips_debug) |
6d82d43b | 2837 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2838 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2839 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2840 | |
c906108c | 2841 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2842 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2843 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2844 | |
46e0f506 | 2845 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2846 | if (struct_return) |
9ace0497 AC |
2847 | { |
2848 | if (mips_debug) | |
2849 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
2850 | "mips_eabi_push_dummy_call: struct_return reg=%d %s\n", |
2851 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 2852 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2853 | } |
c906108c SS |
2854 | |
2855 | /* Now load as many as possible of the first arguments into | |
2856 | registers, and push the rest onto the stack. Loop thru args | |
2857 | from first to last. */ | |
2858 | for (argnum = 0; argnum < nargs; argnum++) | |
2859 | { | |
47a35522 MK |
2860 | const gdb_byte *val; |
2861 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2862 | struct value *arg = args[argnum]; |
4991999e | 2863 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2864 | int len = TYPE_LENGTH (arg_type); |
2865 | enum type_code typecode = TYPE_CODE (arg_type); | |
2866 | ||
9ace0497 AC |
2867 | if (mips_debug) |
2868 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2869 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2870 | argnum + 1, len, (int) typecode); |
9ace0497 | 2871 | |
c906108c | 2872 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2873 | reference. */ |
1a69e1e4 | 2874 | if (len > regsize |
9ace0497 | 2875 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2876 | { |
e17a4113 UW |
2877 | store_unsigned_integer (valbuf, regsize, byte_order, |
2878 | value_address (arg)); | |
c906108c | 2879 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2880 | len = regsize; |
c906108c | 2881 | val = valbuf; |
9ace0497 AC |
2882 | if (mips_debug) |
2883 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2884 | } |
2885 | else | |
47a35522 | 2886 | val = value_contents (arg); |
c906108c SS |
2887 | |
2888 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2889 | even-numbered floating point register. Round the FP register |
2890 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2891 | left. Non MIPS_EABI targets also pass the FP in the integer |
2892 | registers so also round up normal registers. */ | |
74ed0bb4 | 2893 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2894 | { |
2895 | if ((float_argreg & 1)) | |
2896 | float_argreg++; | |
2897 | } | |
c906108c SS |
2898 | |
2899 | /* Floating point arguments passed in registers have to be | |
2900 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2901 | are passed in register pairs; the even register gets |
2902 | the low word, and the odd register gets the high word. | |
2903 | On non-EABI processors, the first two floating point arguments are | |
2904 | also copied to general registers, because MIPS16 functions | |
2905 | don't use float registers for arguments. This duplication of | |
2906 | arguments in general registers can't hurt non-MIPS16 functions | |
2907 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2908 | /* MIPS_EABI squeezes a struct that contains a single floating |
2909 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2910 | stack. */ |
74ed0bb4 MD |
2911 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2912 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2913 | { |
6da397e0 KB |
2914 | /* EABI32 will pass doubles in consecutive registers, even on |
2915 | 64-bit cores. At one time, we used to check the size of | |
2916 | `float_argreg' to determine whether or not to pass doubles | |
2917 | in consecutive registers, but this is not sufficient for | |
2918 | making the ABI determination. */ | |
2919 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2920 | { |
72a155b4 | 2921 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2922 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 2923 | long regval; |
c906108c SS |
2924 | |
2925 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
2926 | regval = extract_signed_integer (val + low_offset, |
2927 | 4, byte_order); | |
9ace0497 | 2928 | if (mips_debug) |
acdb74a0 | 2929 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2930 | float_argreg, phex (regval, 4)); |
a8852dc5 | 2931 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2932 | |
2933 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
2934 | regval = extract_signed_integer (val + 4 - low_offset, |
2935 | 4, byte_order); | |
9ace0497 | 2936 | if (mips_debug) |
acdb74a0 | 2937 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2938 | float_argreg, phex (regval, 4)); |
a8852dc5 | 2939 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2940 | } |
2941 | else | |
2942 | { | |
2943 | /* This is a floating point value that fits entirely | |
2944 | in a single register. */ | |
53a5351d | 2945 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2946 | above to ensure that it is even register aligned. */ |
a8852dc5 | 2947 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 2948 | if (mips_debug) |
acdb74a0 | 2949 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2950 | float_argreg, phex (regval, len)); |
a8852dc5 | 2951 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2952 | } |
2953 | } | |
2954 | else | |
2955 | { | |
2956 | /* Copy the argument to general registers or the stack in | |
2957 | register-sized pieces. Large arguments are split between | |
2958 | registers and stack. */ | |
1a69e1e4 DJ |
2959 | /* Note: structs whose size is not a multiple of regsize |
2960 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2961 | them in registers where gcc sometimes puts them on the |
2962 | stack. For maximum compatibility, we will put them in | |
2963 | both places. */ | |
1a69e1e4 | 2964 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2965 | |
f09ded24 | 2966 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2967 | register are only written to memory. */ |
c906108c SS |
2968 | while (len > 0) |
2969 | { | |
ebafbe83 | 2970 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2971 | int stack_used_p = 0; |
1a69e1e4 | 2972 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2973 | |
acdb74a0 AC |
2974 | if (mips_debug) |
2975 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2976 | partial_len); | |
2977 | ||
566f0f7a | 2978 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 2979 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 2980 | || odd_sized_struct |
74ed0bb4 | 2981 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 2982 | { |
c906108c SS |
2983 | /* Should shorter than int integer values be |
2984 | promoted to int before being stored? */ | |
c906108c | 2985 | int longword_offset = 0; |
9ace0497 | 2986 | CORE_ADDR addr; |
566f0f7a | 2987 | stack_used_p = 1; |
72a155b4 | 2988 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2989 | { |
1a69e1e4 | 2990 | if (regsize == 8 |
480d3dd2 AC |
2991 | && (typecode == TYPE_CODE_INT |
2992 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2993 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2994 | longword_offset = regsize - len; |
480d3dd2 AC |
2995 | else if ((typecode == TYPE_CODE_STRUCT |
2996 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2997 | && TYPE_LENGTH (arg_type) < regsize) |
2998 | longword_offset = regsize - len; | |
7a292a7a | 2999 | } |
c5aa993b | 3000 | |
9ace0497 AC |
3001 | if (mips_debug) |
3002 | { | |
5af949e3 UW |
3003 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3004 | paddress (gdbarch, stack_offset)); | |
3005 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3006 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3007 | } |
361d1df0 | 3008 | |
9ace0497 AC |
3009 | addr = sp + stack_offset + longword_offset; |
3010 | ||
3011 | if (mips_debug) | |
3012 | { | |
3013 | int i; | |
5af949e3 UW |
3014 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3015 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3016 | for (i = 0; i < partial_len; i++) |
3017 | { | |
6d82d43b | 3018 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3019 | val[i] & 0xff); |
9ace0497 AC |
3020 | } |
3021 | } | |
3022 | write_memory (addr, val, partial_len); | |
c906108c SS |
3023 | } |
3024 | ||
f09ded24 AC |
3025 | /* Note!!! This is NOT an else clause. Odd sized |
3026 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3027 | arguments will not. */ |
566f0f7a | 3028 | /* Write this portion of the argument to a general |
6d82d43b | 3029 | purpose register. */ |
74ed0bb4 MD |
3030 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3031 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3032 | { |
6d82d43b | 3033 | LONGEST regval = |
a8852dc5 | 3034 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3035 | |
9ace0497 | 3036 | if (mips_debug) |
acdb74a0 | 3037 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3038 | argreg, |
1a69e1e4 | 3039 | phex (regval, regsize)); |
a8852dc5 | 3040 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3041 | argreg++; |
c906108c | 3042 | } |
c5aa993b | 3043 | |
c906108c SS |
3044 | len -= partial_len; |
3045 | val += partial_len; | |
3046 | ||
566f0f7a | 3047 | /* Compute the the offset into the stack at which we |
6d82d43b | 3048 | will copy the next parameter. |
566f0f7a | 3049 | |
566f0f7a | 3050 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3051 | only needs to be adjusted when it has been used. */ |
c906108c | 3052 | |
46e0f506 | 3053 | if (stack_used_p) |
1a69e1e4 | 3054 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3055 | } |
3056 | } | |
9ace0497 AC |
3057 | if (mips_debug) |
3058 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3059 | } |
3060 | ||
f10683bb | 3061 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3062 | |
0f71a2f6 JM |
3063 | /* Return adjusted stack pointer. */ |
3064 | return sp; | |
3065 | } | |
3066 | ||
a1f5b845 | 3067 | /* Determine the return value convention being used. */ |
6d82d43b | 3068 | |
9c8fdbfa | 3069 | static enum return_value_convention |
c055b101 | 3070 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3071 | struct type *type, struct regcache *regcache, |
47a35522 | 3072 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3073 | { |
609ba780 JM |
3074 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3075 | int fp_return_type = 0; | |
3076 | int offset, regnum, xfer; | |
3077 | ||
9c8fdbfa AC |
3078 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3079 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3080 | |
3081 | /* Floating point type? */ | |
3082 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3083 | { | |
3084 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3085 | fp_return_type = 1; | |
3086 | /* Structs with a single field of float type | |
3087 | are returned in a floating point register. */ | |
3088 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3089 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3090 | && TYPE_NFIELDS (type) == 1) | |
3091 | { | |
3092 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3093 | ||
3094 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3095 | fp_return_type = 1; | |
3096 | } | |
3097 | } | |
3098 | ||
3099 | if (fp_return_type) | |
3100 | { | |
3101 | /* A floating-point value belongs in the least significant part | |
3102 | of FP0/FP1. */ | |
3103 | if (mips_debug) | |
3104 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3105 | regnum = mips_regnum (gdbarch)->fp0; | |
3106 | } | |
3107 | else | |
3108 | { | |
3109 | /* An integer value goes in V0/V1. */ | |
3110 | if (mips_debug) | |
3111 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3112 | regnum = MIPS_V0_REGNUM; | |
3113 | } | |
3114 | for (offset = 0; | |
3115 | offset < TYPE_LENGTH (type); | |
3116 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3117 | { | |
3118 | xfer = mips_abi_regsize (gdbarch); | |
3119 | if (offset + xfer > TYPE_LENGTH (type)) | |
3120 | xfer = TYPE_LENGTH (type) - offset; | |
3121 | mips_xfer_register (gdbarch, regcache, | |
3122 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3123 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3124 | offset); | |
3125 | } | |
3126 | ||
9c8fdbfa | 3127 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3128 | } |
3129 | ||
6d82d43b AC |
3130 | |
3131 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3132 | |
8d26208a DJ |
3133 | /* Search for a naturally aligned double at OFFSET inside a struct |
3134 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3135 | registers. */ | |
3136 | ||
3137 | static int | |
74ed0bb4 MD |
3138 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3139 | int offset) | |
8d26208a DJ |
3140 | { |
3141 | int i; | |
3142 | ||
3143 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3144 | return 0; | |
3145 | ||
74ed0bb4 | 3146 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3147 | return 0; |
3148 | ||
3149 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3150 | return 0; | |
3151 | ||
3152 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3153 | { | |
3154 | int pos; | |
3155 | struct type *field_type; | |
3156 | ||
3157 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3158 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3159 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3160 | continue; | |
3161 | ||
3162 | /* If we have gone past the offset, there is no double to pass. */ | |
3163 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3164 | if (pos > offset) | |
3165 | return 0; | |
3166 | ||
3167 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3168 | ||
3169 | /* If this field is entirely before the requested offset, go | |
3170 | on to the next one. */ | |
3171 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3172 | continue; | |
3173 | ||
3174 | /* If this is our special aligned double, we can stop. */ | |
3175 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3176 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3177 | return 1; | |
3178 | ||
3179 | /* This field starts at or before the requested offset, and | |
3180 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3181 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3182 | } |
3183 | ||
3184 | return 0; | |
3185 | } | |
3186 | ||
f7ab6ec6 | 3187 | static CORE_ADDR |
7d9b040b | 3188 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3189 | struct regcache *regcache, CORE_ADDR bp_addr, |
3190 | int nargs, struct value **args, CORE_ADDR sp, | |
3191 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3192 | { |
3193 | int argreg; | |
3194 | int float_argreg; | |
3195 | int argnum; | |
3196 | int len = 0; | |
3197 | int stack_offset = 0; | |
480d3dd2 | 3198 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3199 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3200 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3201 | |
25ab4790 AC |
3202 | /* For shared libraries, "t9" needs to point at the function |
3203 | address. */ | |
4c7d22cb | 3204 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3205 | |
3206 | /* Set the return address register to point to the entry point of | |
3207 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3208 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3209 | |
cb3d25d1 MS |
3210 | /* First ensure that the stack and structure return address (if any) |
3211 | are properly aligned. The stack has to be at least 64-bit | |
3212 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3213 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3214 | aligned, so we round to this widest known alignment. */ | |
3215 | ||
5b03f266 AC |
3216 | sp = align_down (sp, 16); |
3217 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3218 | |
3219 | /* Now make space on the stack for the args. */ | |
3220 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3221 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3222 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3223 | |
3224 | if (mips_debug) | |
6d82d43b | 3225 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3226 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3227 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3228 | |
3229 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3230 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3231 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3232 | |
46e0f506 | 3233 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3234 | if (struct_return) |
3235 | { | |
3236 | if (mips_debug) | |
3237 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3238 | "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n", |
3239 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3240 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3241 | } |
3242 | ||
3243 | /* Now load as many as possible of the first arguments into | |
3244 | registers, and push the rest onto the stack. Loop thru args | |
3245 | from first to last. */ | |
3246 | for (argnum = 0; argnum < nargs; argnum++) | |
3247 | { | |
47a35522 | 3248 | const gdb_byte *val; |
cb3d25d1 | 3249 | struct value *arg = args[argnum]; |
4991999e | 3250 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3251 | int len = TYPE_LENGTH (arg_type); |
3252 | enum type_code typecode = TYPE_CODE (arg_type); | |
3253 | ||
3254 | if (mips_debug) | |
3255 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3256 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3257 | argnum + 1, len, (int) typecode); |
3258 | ||
47a35522 | 3259 | val = value_contents (arg); |
cb3d25d1 | 3260 | |
5b68030f JM |
3261 | /* A 128-bit long double value requires an even-odd pair of |
3262 | floating-point registers. */ | |
3263 | if (len == 16 | |
3264 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3265 | && (float_argreg & 1)) | |
3266 | { | |
3267 | float_argreg++; | |
3268 | argreg++; | |
3269 | } | |
3270 | ||
74ed0bb4 MD |
3271 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3272 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3273 | { |
3274 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3275 | in a single register or a pair of registers. */ |
3276 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3277 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3278 | if (mips_debug) |
3279 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3280 | float_argreg, phex (regval, reglen)); |
8d26208a | 3281 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3282 | |
3283 | if (mips_debug) | |
3284 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3285 | argreg, phex (regval, reglen)); |
9c9acae0 | 3286 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3287 | float_argreg++; |
3288 | argreg++; | |
5b68030f JM |
3289 | if (len == 16) |
3290 | { | |
e17a4113 UW |
3291 | regval = extract_unsigned_integer (val + reglen, |
3292 | reglen, byte_order); | |
5b68030f JM |
3293 | if (mips_debug) |
3294 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3295 | float_argreg, phex (regval, reglen)); | |
3296 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3297 | ||
3298 | if (mips_debug) | |
3299 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3300 | argreg, phex (regval, reglen)); | |
3301 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3302 | float_argreg++; | |
3303 | argreg++; | |
3304 | } | |
cb3d25d1 MS |
3305 | } |
3306 | else | |
3307 | { | |
3308 | /* Copy the argument to general registers or the stack in | |
3309 | register-sized pieces. Large arguments are split between | |
3310 | registers and stack. */ | |
ab2e1992 MR |
3311 | /* For N32/N64, structs, unions, or other composite types are |
3312 | treated as a sequence of doublewords, and are passed in integer | |
3313 | or floating point registers as though they were simple scalar | |
3314 | parameters to the extent that they fit, with any excess on the | |
3315 | stack packed according to the normal memory layout of the | |
3316 | object. | |
3317 | The caller does not reserve space for the register arguments; | |
3318 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3319 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3320 | register are only written to memory. */ |
cb3d25d1 MS |
3321 | while (len > 0) |
3322 | { | |
ad018eee | 3323 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3324 | int stack_used_p = 0; |
1a69e1e4 | 3325 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3326 | |
3327 | if (mips_debug) | |
3328 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3329 | partial_len); | |
3330 | ||
74ed0bb4 MD |
3331 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3332 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3333 | |
cb3d25d1 | 3334 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3335 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3336 | { |
3337 | /* Should shorter than int integer values be | |
3338 | promoted to int before being stored? */ | |
3339 | int longword_offset = 0; | |
3340 | CORE_ADDR addr; | |
3341 | stack_used_p = 1; | |
72a155b4 | 3342 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3343 | { |
1a69e1e4 | 3344 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3345 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3346 | && len <= 4) |
3347 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3348 | } |
3349 | ||
3350 | if (mips_debug) | |
3351 | { | |
5af949e3 UW |
3352 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3353 | paddress (gdbarch, stack_offset)); | |
3354 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3355 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3356 | } |
3357 | ||
3358 | addr = sp + stack_offset + longword_offset; | |
3359 | ||
3360 | if (mips_debug) | |
3361 | { | |
3362 | int i; | |
5af949e3 UW |
3363 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3364 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3365 | for (i = 0; i < partial_len; i++) |
3366 | { | |
6d82d43b | 3367 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3368 | val[i] & 0xff); |
3369 | } | |
3370 | } | |
3371 | write_memory (addr, val, partial_len); | |
3372 | } | |
3373 | ||
3374 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3375 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3376 | /* Write this portion of the argument to a general |
6d82d43b | 3377 | purpose register. */ |
74ed0bb4 | 3378 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3379 | { |
5863b5d5 MR |
3380 | LONGEST regval; |
3381 | ||
3382 | /* Sign extend pointers, 32-bit integers and signed | |
3383 | 16-bit and 8-bit integers; everything else is taken | |
3384 | as is. */ | |
3385 | ||
3386 | if ((partial_len == 4 | |
3387 | && (typecode == TYPE_CODE_PTR | |
3388 | || typecode == TYPE_CODE_INT)) | |
3389 | || (partial_len < 4 | |
3390 | && typecode == TYPE_CODE_INT | |
3391 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3392 | regval = extract_signed_integer (val, partial_len, |
3393 | byte_order); | |
5863b5d5 | 3394 | else |
e17a4113 UW |
3395 | regval = extract_unsigned_integer (val, partial_len, |
3396 | byte_order); | |
cb3d25d1 MS |
3397 | |
3398 | /* A non-floating-point argument being passed in a | |
3399 | general register. If a struct or union, and if | |
3400 | the remaining length is smaller than the register | |
3401 | size, we have to adjust the register value on | |
3402 | big endian targets. | |
3403 | ||
3404 | It does not seem to be necessary to do the | |
1a69e1e4 | 3405 | same for integral types. */ |
cb3d25d1 | 3406 | |
72a155b4 | 3407 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3408 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3409 | && (typecode == TYPE_CODE_STRUCT |
3410 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3411 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3412 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3413 | |
3414 | if (mips_debug) | |
3415 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3416 | argreg, | |
1a69e1e4 | 3417 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3418 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3419 | |
74ed0bb4 | 3420 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3421 | TYPE_LENGTH (arg_type) - len)) |
3422 | { | |
3423 | if (mips_debug) | |
3424 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3425 | float_argreg, | |
3426 | phex (regval, MIPS64_REGSIZE)); | |
3427 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3428 | regval); | |
3429 | } | |
3430 | ||
3431 | float_argreg++; | |
cb3d25d1 MS |
3432 | argreg++; |
3433 | } | |
3434 | ||
3435 | len -= partial_len; | |
3436 | val += partial_len; | |
3437 | ||
3438 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3439 | will copy the next parameter. |
cb3d25d1 MS |
3440 | |
3441 | In N32 (N64?), the stack_offset only needs to be | |
3442 | adjusted when it has been used. */ | |
3443 | ||
3444 | if (stack_used_p) | |
1a69e1e4 | 3445 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3446 | } |
3447 | } | |
3448 | if (mips_debug) | |
3449 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3450 | } | |
3451 | ||
f10683bb | 3452 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3453 | |
cb3d25d1 MS |
3454 | /* Return adjusted stack pointer. */ |
3455 | return sp; | |
3456 | } | |
3457 | ||
6d82d43b | 3458 | static enum return_value_convention |
c055b101 | 3459 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3460 | struct type *type, struct regcache *regcache, |
47a35522 | 3461 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3462 | { |
72a155b4 | 3463 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3464 | |
3465 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3466 | ||
3467 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3468 | if needed), as appropriate for the type. Composite results (struct, | |
3469 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3470 | following rules: | |
3471 | ||
3472 | * A struct with only one or two floating point fields is returned in $f0 | |
3473 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3474 | case. | |
3475 | ||
f08877ba | 3476 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3477 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3478 | ||
3479 | * Larger composite results are handled by converting the function to a | |
3480 | procedure with an implicit first parameter, which is a pointer to an area | |
3481 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3482 | that all composite results be handled by conversion to implicit first | |
3483 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3484 | specific exception to return COMPLEX results in the floating point | |
3485 | registers.] */ | |
3486 | ||
f08877ba | 3487 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3488 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3489 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3490 | && TYPE_LENGTH (type) == 16 | |
3491 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3492 | { | |
3493 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3494 | two registers are used in the same as memory order, so the | |
3495 | eight bytes with the lower memory address are in $f0. */ | |
3496 | if (mips_debug) | |
3497 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3498 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3499 | gdbarch_num_regs (gdbarch) |
3500 | + mips_regnum (gdbarch)->fp0, | |
3501 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3502 | readbuf, writebuf, 0); |
ba32f989 | 3503 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3504 | gdbarch_num_regs (gdbarch) |
3505 | + mips_regnum (gdbarch)->fp0 + 2, | |
3506 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3507 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3508 | writebuf ? writebuf + 8 : writebuf, 0); |
3509 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3510 | } | |
6d82d43b AC |
3511 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3512 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3513 | { | |
59aa1faa | 3514 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3515 | if (mips_debug) |
3516 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3517 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3518 | gdbarch_num_regs (gdbarch) |
3519 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3520 | TYPE_LENGTH (type), |
72a155b4 | 3521 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3522 | readbuf, writebuf, 0); |
6d82d43b AC |
3523 | return RETURN_VALUE_REGISTER_CONVENTION; |
3524 | } | |
3525 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3526 | && TYPE_NFIELDS (type) <= 2 | |
3527 | && TYPE_NFIELDS (type) >= 1 | |
3528 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3529 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3530 | == TYPE_CODE_FLT)) |
3531 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3532 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3533 | == TYPE_CODE_FLT) |
b18bb924 | 3534 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3535 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3536 | { |
3537 | /* A struct that contains one or two floats. Each value is part | |
3538 | in the least significant part of their floating point | |
5b68030f | 3539 | register (or GPR, for soft float). */ |
6d82d43b AC |
3540 | int regnum; |
3541 | int field; | |
5b68030f JM |
3542 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3543 | ? mips_regnum (gdbarch)->fp0 | |
3544 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3545 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3546 | { | |
3547 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3548 | / TARGET_CHAR_BIT); | |
3549 | if (mips_debug) | |
3550 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3551 | offset); | |
5b68030f JM |
3552 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3553 | { | |
3554 | /* A 16-byte long double field goes in two consecutive | |
3555 | registers. */ | |
3556 | mips_xfer_register (gdbarch, regcache, | |
3557 | gdbarch_num_regs (gdbarch) + regnum, | |
3558 | 8, | |
3559 | gdbarch_byte_order (gdbarch), | |
3560 | readbuf, writebuf, offset); | |
3561 | mips_xfer_register (gdbarch, regcache, | |
3562 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3563 | 8, | |
3564 | gdbarch_byte_order (gdbarch), | |
3565 | readbuf, writebuf, offset + 8); | |
3566 | } | |
3567 | else | |
3568 | mips_xfer_register (gdbarch, regcache, | |
3569 | gdbarch_num_regs (gdbarch) + regnum, | |
3570 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3571 | gdbarch_byte_order (gdbarch), | |
3572 | readbuf, writebuf, offset); | |
6d82d43b AC |
3573 | } |
3574 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3575 | } | |
3576 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3577 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3578 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3579 | { |
f08877ba | 3580 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3581 | regardless of the byte order. I.e. DO NOT USE |
3582 | mips_xfer_lower. */ | |
3583 | int offset; | |
3584 | int regnum; | |
4c7d22cb | 3585 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3586 | offset < TYPE_LENGTH (type); |
72a155b4 | 3587 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3588 | { |
72a155b4 | 3589 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3590 | if (offset + xfer > TYPE_LENGTH (type)) |
3591 | xfer = TYPE_LENGTH (type) - offset; | |
3592 | if (mips_debug) | |
3593 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3594 | offset, xfer, regnum); | |
ba32f989 DJ |
3595 | mips_xfer_register (gdbarch, regcache, |
3596 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3597 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3598 | offset); | |
6d82d43b AC |
3599 | } |
3600 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3601 | } | |
3602 | else | |
3603 | { | |
3604 | /* A scalar extract each part but least-significant-byte | |
3605 | justified. */ | |
3606 | int offset; | |
3607 | int regnum; | |
4c7d22cb | 3608 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3609 | offset < TYPE_LENGTH (type); |
72a155b4 | 3610 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3611 | { |
72a155b4 | 3612 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3613 | if (offset + xfer > TYPE_LENGTH (type)) |
3614 | xfer = TYPE_LENGTH (type) - offset; | |
3615 | if (mips_debug) | |
3616 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3617 | offset, xfer, regnum); | |
ba32f989 DJ |
3618 | mips_xfer_register (gdbarch, regcache, |
3619 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3620 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3621 | readbuf, writebuf, offset); |
6d82d43b AC |
3622 | } |
3623 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3624 | } | |
3625 | } | |
3626 | ||
3627 | /* O32 ABI stuff. */ | |
3628 | ||
3629 | static CORE_ADDR | |
7d9b040b | 3630 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3631 | struct regcache *regcache, CORE_ADDR bp_addr, |
3632 | int nargs, struct value **args, CORE_ADDR sp, | |
3633 | int struct_return, CORE_ADDR struct_addr) | |
3634 | { | |
3635 | int argreg; | |
3636 | int float_argreg; | |
3637 | int argnum; | |
3638 | int len = 0; | |
3639 | int stack_offset = 0; | |
3640 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3641 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3642 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3643 | |
3644 | /* For shared libraries, "t9" needs to point at the function | |
3645 | address. */ | |
4c7d22cb | 3646 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3647 | |
3648 | /* Set the return address register to point to the entry point of | |
3649 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3650 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3651 | |
3652 | /* First ensure that the stack and structure return address (if any) | |
3653 | are properly aligned. The stack has to be at least 64-bit | |
3654 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3655 | aligned. For n32 and n64, stack frames need to be 128-bit |
3656 | aligned, so we round to this widest known alignment. */ | |
3657 | ||
5b03f266 AC |
3658 | sp = align_down (sp, 16); |
3659 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3660 | |
3661 | /* Now make space on the stack for the args. */ | |
3662 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3663 | { |
3664 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3665 | int arglen = TYPE_LENGTH (arg_type); | |
3666 | ||
3667 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3668 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3669 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3670 | /* Allocate space on the stack. */ |
1a69e1e4 | 3671 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3672 | } |
5b03f266 | 3673 | sp -= align_up (len, 16); |
ebafbe83 MS |
3674 | |
3675 | if (mips_debug) | |
6d82d43b | 3676 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3677 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3678 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3679 | |
3680 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3681 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3682 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3683 | |
bcb0cc15 | 3684 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3685 | if (struct_return) |
3686 | { | |
3687 | if (mips_debug) | |
3688 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3689 | "mips_o32_push_dummy_call: struct_return reg=%d %s\n", |
3690 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3691 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3692 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3693 | } |
3694 | ||
3695 | /* Now load as many as possible of the first arguments into | |
3696 | registers, and push the rest onto the stack. Loop thru args | |
3697 | from first to last. */ | |
3698 | for (argnum = 0; argnum < nargs; argnum++) | |
3699 | { | |
47a35522 | 3700 | const gdb_byte *val; |
ebafbe83 | 3701 | struct value *arg = args[argnum]; |
4991999e | 3702 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3703 | int len = TYPE_LENGTH (arg_type); |
3704 | enum type_code typecode = TYPE_CODE (arg_type); | |
3705 | ||
3706 | if (mips_debug) | |
3707 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3708 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3709 | argnum + 1, len, (int) typecode); |
3710 | ||
47a35522 | 3711 | val = value_contents (arg); |
46cac009 AC |
3712 | |
3713 | /* 32-bit ABIs always start floating point arguments in an | |
3714 | even-numbered floating point register. Round the FP register | |
3715 | up before the check to see if there are any FP registers | |
3716 | left. O32/O64 targets also pass the FP in the integer | |
3717 | registers so also round up normal registers. */ | |
74ed0bb4 | 3718 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3719 | { |
3720 | if ((float_argreg & 1)) | |
3721 | float_argreg++; | |
3722 | } | |
3723 | ||
3724 | /* Floating point arguments passed in registers have to be | |
3725 | treated specially. On 32-bit architectures, doubles | |
3726 | are passed in register pairs; the even register gets | |
3727 | the low word, and the odd register gets the high word. | |
3728 | On O32/O64, the first two floating point arguments are | |
3729 | also copied to general registers, because MIPS16 functions | |
3730 | don't use float registers for arguments. This duplication of | |
3731 | arguments in general registers can't hurt non-MIPS16 functions | |
3732 | because those registers are normally skipped. */ | |
3733 | ||
74ed0bb4 MD |
3734 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3735 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3736 | { |
8b07f6d8 | 3737 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3738 | { |
72a155b4 | 3739 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3740 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3741 | unsigned long regval; |
3742 | ||
3743 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3744 | regval = extract_unsigned_integer (val + low_offset, |
3745 | 4, byte_order); | |
46cac009 AC |
3746 | if (mips_debug) |
3747 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3748 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3749 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3750 | if (mips_debug) |
3751 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3752 | argreg, phex (regval, 4)); | |
9c9acae0 | 3753 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3754 | |
3755 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3756 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3757 | 4, byte_order); | |
46cac009 AC |
3758 | if (mips_debug) |
3759 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3760 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3761 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3762 | |
3763 | if (mips_debug) | |
3764 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3765 | argreg, phex (regval, 4)); | |
9c9acae0 | 3766 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3767 | } |
3768 | else | |
3769 | { | |
3770 | /* This is a floating point value that fits entirely | |
3771 | in a single register. */ | |
3772 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3773 | above to ensure that it is even register aligned. */ |
e17a4113 | 3774 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3775 | if (mips_debug) |
3776 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3777 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3778 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3779 | /* Although two FP registers are reserved for each |
3780 | argument, only one corresponding integer register is | |
3781 | reserved. */ | |
46cac009 AC |
3782 | if (mips_debug) |
3783 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3784 | argreg, phex (regval, len)); | |
5b68030f | 3785 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3786 | } |
3787 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3788 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3789 | } |
3790 | else | |
3791 | { | |
3792 | /* Copy the argument to general registers or the stack in | |
3793 | register-sized pieces. Large arguments are split between | |
3794 | registers and stack. */ | |
1a69e1e4 DJ |
3795 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3796 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3797 | them in registers where gcc sometimes puts them on the |
3798 | stack. For maximum compatibility, we will put them in | |
3799 | both places. */ | |
1a69e1e4 DJ |
3800 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3801 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3802 | /* Structures should be aligned to eight bytes (even arg registers) |
3803 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3804 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3805 | { |
3806 | if ((argreg & 1)) | |
968b5391 MR |
3807 | { |
3808 | argreg++; | |
1a69e1e4 | 3809 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3810 | } |
46cac009 | 3811 | } |
46cac009 AC |
3812 | while (len > 0) |
3813 | { | |
3814 | /* Remember if the argument was written to the stack. */ | |
3815 | int stack_used_p = 0; | |
1a69e1e4 | 3816 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3817 | |
3818 | if (mips_debug) | |
3819 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3820 | partial_len); | |
3821 | ||
3822 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3823 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3824 | || odd_sized_struct) |
46cac009 AC |
3825 | { |
3826 | /* Should shorter than int integer values be | |
3827 | promoted to int before being stored? */ | |
3828 | int longword_offset = 0; | |
3829 | CORE_ADDR addr; | |
3830 | stack_used_p = 1; | |
46cac009 AC |
3831 | |
3832 | if (mips_debug) | |
3833 | { | |
5af949e3 UW |
3834 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3835 | paddress (gdbarch, stack_offset)); | |
3836 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3837 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3838 | } |
3839 | ||
3840 | addr = sp + stack_offset + longword_offset; | |
3841 | ||
3842 | if (mips_debug) | |
3843 | { | |
3844 | int i; | |
5af949e3 UW |
3845 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3846 | paddress (gdbarch, addr)); | |
46cac009 AC |
3847 | for (i = 0; i < partial_len; i++) |
3848 | { | |
6d82d43b | 3849 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3850 | val[i] & 0xff); |
3851 | } | |
3852 | } | |
3853 | write_memory (addr, val, partial_len); | |
3854 | } | |
3855 | ||
3856 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3857 | structs may go thru BOTH paths. */ |
46cac009 | 3858 | /* Write this portion of the argument to a general |
6d82d43b | 3859 | purpose register. */ |
74ed0bb4 | 3860 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3861 | { |
e17a4113 UW |
3862 | LONGEST regval = extract_signed_integer (val, partial_len, |
3863 | byte_order); | |
4246e332 | 3864 | /* Value may need to be sign extended, because |
1b13c4f6 | 3865 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3866 | |
3867 | /* A non-floating-point argument being passed in a | |
3868 | general register. If a struct or union, and if | |
3869 | the remaining length is smaller than the register | |
3870 | size, we have to adjust the register value on | |
3871 | big endian targets. | |
3872 | ||
3873 | It does not seem to be necessary to do the | |
3874 | same for integral types. | |
3875 | ||
3876 | Also don't do this adjustment on O64 binaries. | |
3877 | ||
3878 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3879 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3880 | mips_abi_regsize(), generates a left shift |
3881 | as part of storing the argument in a register | |
3882 | (the left shift isn't generated when | |
1b13c4f6 | 3883 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3884 | it is quite possible that this is GCC |
3885 | contradicting the LE/O32 ABI, GDB has not been | |
3886 | adjusted to accommodate this. Either someone | |
3887 | needs to demonstrate that the LE/O32 ABI | |
3888 | specifies such a left shift OR this new ABI gets | |
3889 | identified as such and GDB gets tweaked | |
3890 | accordingly. */ | |
3891 | ||
72a155b4 | 3892 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3893 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3894 | && (typecode == TYPE_CODE_STRUCT |
3895 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3896 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3897 | * TARGET_CHAR_BIT); |
46cac009 AC |
3898 | |
3899 | if (mips_debug) | |
3900 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3901 | argreg, | |
1a69e1e4 | 3902 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3903 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3904 | argreg++; |
3905 | ||
3906 | /* Prevent subsequent floating point arguments from | |
3907 | being passed in floating point registers. */ | |
74ed0bb4 | 3908 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3909 | } |
3910 | ||
3911 | len -= partial_len; | |
3912 | val += partial_len; | |
3913 | ||
3914 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3915 | will copy the next parameter. |
46cac009 | 3916 | |
6d82d43b AC |
3917 | In older ABIs, the caller reserved space for |
3918 | registers that contained arguments. This was loosely | |
3919 | refered to as their "home". Consequently, space is | |
3920 | always allocated. */ | |
46cac009 | 3921 | |
1a69e1e4 | 3922 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3923 | } |
3924 | } | |
3925 | if (mips_debug) | |
3926 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3927 | } | |
3928 | ||
f10683bb | 3929 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3930 | |
46cac009 AC |
3931 | /* Return adjusted stack pointer. */ |
3932 | return sp; | |
3933 | } | |
3934 | ||
6d82d43b | 3935 | static enum return_value_convention |
c055b101 CV |
3936 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3937 | struct type *type, struct regcache *regcache, | |
47a35522 | 3938 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3939 | { |
72a155b4 | 3940 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3941 | |
3942 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3943 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3944 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3945 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3946 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3947 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3948 | { | |
3949 | /* A single-precision floating-point value. It fits in the | |
3950 | least significant part of FP0. */ | |
3951 | if (mips_debug) | |
3952 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3953 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3954 | gdbarch_num_regs (gdbarch) |
3955 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3956 | TYPE_LENGTH (type), |
72a155b4 | 3957 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3958 | readbuf, writebuf, 0); |
6d82d43b AC |
3959 | return RETURN_VALUE_REGISTER_CONVENTION; |
3960 | } | |
3961 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3962 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3963 | { | |
3964 | /* A double-precision floating-point value. The most | |
3965 | significant part goes in FP1, and the least significant in | |
3966 | FP0. */ | |
3967 | if (mips_debug) | |
3968 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3969 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3970 | { |
3971 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3972 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3973 | gdbarch_num_regs (gdbarch) |
3974 | + mips_regnum (gdbarch)->fp0 + | |
3975 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3976 | readbuf, writebuf, 0); |
ba32f989 | 3977 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3978 | gdbarch_num_regs (gdbarch) |
3979 | + mips_regnum (gdbarch)->fp0 + 1, | |
3980 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3981 | readbuf, writebuf, 4); |
6d82d43b AC |
3982 | break; |
3983 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3984 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3985 | gdbarch_num_regs (gdbarch) |
3986 | + mips_regnum (gdbarch)->fp0 + 1, | |
3987 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3988 | readbuf, writebuf, 0); |
ba32f989 | 3989 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3990 | gdbarch_num_regs (gdbarch) |
3991 | + mips_regnum (gdbarch)->fp0 + 0, | |
3992 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3993 | readbuf, writebuf, 4); |
6d82d43b AC |
3994 | break; |
3995 | default: | |
e2e0b3e5 | 3996 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3997 | } |
3998 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3999 | } | |
4000 | #if 0 | |
4001 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4002 | && TYPE_NFIELDS (type) <= 2 | |
4003 | && TYPE_NFIELDS (type) >= 1 | |
4004 | && ((TYPE_NFIELDS (type) == 1 | |
4005 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4006 | == TYPE_CODE_FLT)) | |
4007 | || (TYPE_NFIELDS (type) == 2 | |
4008 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4009 | == TYPE_CODE_FLT) | |
4010 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4011 | == TYPE_CODE_FLT))) | |
4012 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4013 | { | |
4014 | /* A struct that contains one or two floats. Each value is part | |
4015 | in the least significant part of their floating point | |
4016 | register.. */ | |
870cd05e | 4017 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4018 | int regnum; |
4019 | int field; | |
72a155b4 | 4020 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4021 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4022 | { | |
4023 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4024 | / TARGET_CHAR_BIT); | |
4025 | if (mips_debug) | |
4026 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4027 | offset); | |
ba32f989 DJ |
4028 | mips_xfer_register (gdbarch, regcache, |
4029 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4030 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4031 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4032 | readbuf, writebuf, offset); |
6d82d43b AC |
4033 | } |
4034 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4035 | } | |
4036 | #endif | |
4037 | #if 0 | |
4038 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4039 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4040 | { | |
4041 | /* A structure or union. Extract the left justified value, | |
4042 | regardless of the byte order. I.e. DO NOT USE | |
4043 | mips_xfer_lower. */ | |
4044 | int offset; | |
4045 | int regnum; | |
4c7d22cb | 4046 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4047 | offset < TYPE_LENGTH (type); |
72a155b4 | 4048 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4049 | { |
72a155b4 | 4050 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4051 | if (offset + xfer > TYPE_LENGTH (type)) |
4052 | xfer = TYPE_LENGTH (type) - offset; | |
4053 | if (mips_debug) | |
4054 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4055 | offset, xfer, regnum); | |
ba32f989 DJ |
4056 | mips_xfer_register (gdbarch, regcache, |
4057 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4058 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4059 | } | |
4060 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4061 | } | |
4062 | #endif | |
4063 | else | |
4064 | { | |
4065 | /* A scalar extract each part but least-significant-byte | |
4066 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4067 | the ISA. */ |
6d82d43b AC |
4068 | int offset; |
4069 | int regnum; | |
4c7d22cb | 4070 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4071 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4072 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4073 | { |
1a69e1e4 | 4074 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4075 | if (offset + xfer > TYPE_LENGTH (type)) |
4076 | xfer = TYPE_LENGTH (type) - offset; | |
4077 | if (mips_debug) | |
4078 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4079 | offset, xfer, regnum); | |
ba32f989 DJ |
4080 | mips_xfer_register (gdbarch, regcache, |
4081 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4082 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4083 | readbuf, writebuf, offset); |
6d82d43b AC |
4084 | } |
4085 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4086 | } | |
4087 | } | |
4088 | ||
4089 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4090 | ABI. */ | |
46cac009 AC |
4091 | |
4092 | static CORE_ADDR | |
7d9b040b | 4093 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4094 | struct regcache *regcache, CORE_ADDR bp_addr, |
4095 | int nargs, | |
4096 | struct value **args, CORE_ADDR sp, | |
4097 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4098 | { |
4099 | int argreg; | |
4100 | int float_argreg; | |
4101 | int argnum; | |
4102 | int len = 0; | |
4103 | int stack_offset = 0; | |
480d3dd2 | 4104 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4105 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4106 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4107 | |
25ab4790 AC |
4108 | /* For shared libraries, "t9" needs to point at the function |
4109 | address. */ | |
4c7d22cb | 4110 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4111 | |
4112 | /* Set the return address register to point to the entry point of | |
4113 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4114 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4115 | |
46cac009 AC |
4116 | /* First ensure that the stack and structure return address (if any) |
4117 | are properly aligned. The stack has to be at least 64-bit | |
4118 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4119 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4120 | aligned, so we round to this widest known alignment. */ | |
4121 | ||
5b03f266 AC |
4122 | sp = align_down (sp, 16); |
4123 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4124 | |
4125 | /* Now make space on the stack for the args. */ | |
4126 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4127 | { |
4128 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4129 | int arglen = TYPE_LENGTH (arg_type); | |
4130 | ||
968b5391 | 4131 | /* Allocate space on the stack. */ |
1a69e1e4 | 4132 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4133 | } |
5b03f266 | 4134 | sp -= align_up (len, 16); |
46cac009 AC |
4135 | |
4136 | if (mips_debug) | |
6d82d43b | 4137 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4138 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4139 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4140 | |
4141 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4142 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4143 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4144 | |
4145 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4146 | if (struct_return) | |
4147 | { | |
4148 | if (mips_debug) | |
4149 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
4150 | "mips_o64_push_dummy_call: struct_return reg=%d %s\n", |
4151 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4152 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4153 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4154 | } |
4155 | ||
4156 | /* Now load as many as possible of the first arguments into | |
4157 | registers, and push the rest onto the stack. Loop thru args | |
4158 | from first to last. */ | |
4159 | for (argnum = 0; argnum < nargs; argnum++) | |
4160 | { | |
47a35522 | 4161 | const gdb_byte *val; |
46cac009 | 4162 | struct value *arg = args[argnum]; |
4991999e | 4163 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4164 | int len = TYPE_LENGTH (arg_type); |
4165 | enum type_code typecode = TYPE_CODE (arg_type); | |
4166 | ||
4167 | if (mips_debug) | |
4168 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4169 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4170 | argnum + 1, len, (int) typecode); |
4171 | ||
47a35522 | 4172 | val = value_contents (arg); |
ebafbe83 | 4173 | |
ebafbe83 MS |
4174 | /* Floating point arguments passed in registers have to be |
4175 | treated specially. On 32-bit architectures, doubles | |
4176 | are passed in register pairs; the even register gets | |
4177 | the low word, and the odd register gets the high word. | |
4178 | On O32/O64, the first two floating point arguments are | |
4179 | also copied to general registers, because MIPS16 functions | |
4180 | don't use float registers for arguments. This duplication of | |
4181 | arguments in general registers can't hurt non-MIPS16 functions | |
4182 | because those registers are normally skipped. */ | |
4183 | ||
74ed0bb4 MD |
4184 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4185 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4186 | { |
e17a4113 | 4187 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4188 | if (mips_debug) |
4189 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4190 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4191 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4192 | if (mips_debug) |
4193 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4194 | argreg, phex (regval, len)); | |
9c9acae0 | 4195 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4196 | argreg++; |
ebafbe83 | 4197 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4198 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4199 | } |
4200 | else | |
4201 | { | |
4202 | /* Copy the argument to general registers or the stack in | |
4203 | register-sized pieces. Large arguments are split between | |
4204 | registers and stack. */ | |
1a69e1e4 | 4205 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4206 | are treated specially: Irix cc passes them in registers |
4207 | where gcc sometimes puts them on the stack. For maximum | |
4208 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4209 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4210 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4211 | while (len > 0) |
4212 | { | |
4213 | /* Remember if the argument was written to the stack. */ | |
4214 | int stack_used_p = 0; | |
1a69e1e4 | 4215 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4216 | |
4217 | if (mips_debug) | |
4218 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4219 | partial_len); | |
4220 | ||
4221 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4222 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4223 | || odd_sized_struct) |
ebafbe83 MS |
4224 | { |
4225 | /* Should shorter than int integer values be | |
4226 | promoted to int before being stored? */ | |
4227 | int longword_offset = 0; | |
4228 | CORE_ADDR addr; | |
4229 | stack_used_p = 1; | |
72a155b4 | 4230 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4231 | { |
1a69e1e4 DJ |
4232 | if ((typecode == TYPE_CODE_INT |
4233 | || typecode == TYPE_CODE_PTR | |
4234 | || typecode == TYPE_CODE_FLT) | |
4235 | && len <= 4) | |
4236 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4237 | } |
4238 | ||
4239 | if (mips_debug) | |
4240 | { | |
5af949e3 UW |
4241 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4242 | paddress (gdbarch, stack_offset)); | |
4243 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4244 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4245 | } |
4246 | ||
4247 | addr = sp + stack_offset + longword_offset; | |
4248 | ||
4249 | if (mips_debug) | |
4250 | { | |
4251 | int i; | |
5af949e3 UW |
4252 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4253 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4254 | for (i = 0; i < partial_len; i++) |
4255 | { | |
6d82d43b | 4256 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4257 | val[i] & 0xff); |
4258 | } | |
4259 | } | |
4260 | write_memory (addr, val, partial_len); | |
4261 | } | |
4262 | ||
4263 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4264 | structs may go thru BOTH paths. */ |
ebafbe83 | 4265 | /* Write this portion of the argument to a general |
6d82d43b | 4266 | purpose register. */ |
74ed0bb4 | 4267 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4268 | { |
e17a4113 UW |
4269 | LONGEST regval = extract_signed_integer (val, partial_len, |
4270 | byte_order); | |
4246e332 | 4271 | /* Value may need to be sign extended, because |
1b13c4f6 | 4272 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4273 | |
4274 | /* A non-floating-point argument being passed in a | |
4275 | general register. If a struct or union, and if | |
4276 | the remaining length is smaller than the register | |
4277 | size, we have to adjust the register value on | |
4278 | big endian targets. | |
4279 | ||
4280 | It does not seem to be necessary to do the | |
401835eb | 4281 | same for integral types. */ |
480d3dd2 | 4282 | |
72a155b4 | 4283 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4284 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4285 | && (typecode == TYPE_CODE_STRUCT |
4286 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4287 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4288 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4289 | |
4290 | if (mips_debug) | |
4291 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4292 | argreg, | |
1a69e1e4 | 4293 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4294 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4295 | argreg++; |
4296 | ||
4297 | /* Prevent subsequent floating point arguments from | |
4298 | being passed in floating point registers. */ | |
74ed0bb4 | 4299 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4300 | } |
4301 | ||
4302 | len -= partial_len; | |
4303 | val += partial_len; | |
4304 | ||
4305 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4306 | will copy the next parameter. |
ebafbe83 | 4307 | |
6d82d43b AC |
4308 | In older ABIs, the caller reserved space for |
4309 | registers that contained arguments. This was loosely | |
4310 | refered to as their "home". Consequently, space is | |
4311 | always allocated. */ | |
ebafbe83 | 4312 | |
1a69e1e4 | 4313 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4314 | } |
4315 | } | |
4316 | if (mips_debug) | |
4317 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4318 | } | |
4319 | ||
f10683bb | 4320 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4321 | |
ebafbe83 MS |
4322 | /* Return adjusted stack pointer. */ |
4323 | return sp; | |
4324 | } | |
4325 | ||
9c8fdbfa | 4326 | static enum return_value_convention |
c055b101 | 4327 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4328 | struct type *type, struct regcache *regcache, |
47a35522 | 4329 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4330 | { |
72a155b4 | 4331 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4332 | |
4333 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4334 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4335 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4336 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4337 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4338 | { |
4339 | /* A floating-point value. It fits in the least significant | |
4340 | part of FP0. */ | |
4341 | if (mips_debug) | |
4342 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4343 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4344 | gdbarch_num_regs (gdbarch) |
4345 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4346 | TYPE_LENGTH (type), |
72a155b4 | 4347 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4348 | readbuf, writebuf, 0); |
7a076fd2 FF |
4349 | return RETURN_VALUE_REGISTER_CONVENTION; |
4350 | } | |
4351 | else | |
4352 | { | |
4353 | /* A scalar extract each part but least-significant-byte | |
4354 | justified. */ | |
4355 | int offset; | |
4356 | int regnum; | |
4357 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4358 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4359 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4360 | { |
1a69e1e4 | 4361 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4362 | if (offset + xfer > TYPE_LENGTH (type)) |
4363 | xfer = TYPE_LENGTH (type) - offset; | |
4364 | if (mips_debug) | |
4365 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4366 | offset, xfer, regnum); | |
ba32f989 DJ |
4367 | mips_xfer_register (gdbarch, regcache, |
4368 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4369 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4370 | readbuf, writebuf, offset); |
7a076fd2 FF |
4371 | } |
4372 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4373 | } | |
6d82d43b AC |
4374 | } |
4375 | ||
dd824b04 DJ |
4376 | /* Floating point register management. |
4377 | ||
4378 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4379 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4380 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4381 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4382 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4383 | double precision floats into two 32-bit chunks and store them in | |
4384 | consecutive fp regs. To display 64-bit floats stored in this | |
4385 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4386 | Throw in user-configurable endianness and you have a real mess. | |
4387 | ||
4388 | The way this works is: | |
4389 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4390 | double-precision value will be split across two logical registers. | |
4391 | The lower-numbered logical register will hold the low-order bits, | |
4392 | regardless of the processor's endianness. | |
4393 | - If we are on a 64-bit processor, and we are looking for a | |
4394 | single-precision value, it will be in the low ordered bits | |
4395 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4396 | save slot in memory. | |
4397 | - If we are in 64-bit mode, everything is straightforward. | |
4398 | ||
4399 | Note that this code only deals with "live" registers at the top of the | |
4400 | stack. We will attempt to deal with saved registers later, when | |
4401 | the raw/cooked register interface is in place. (We need a general | |
4402 | interface that can deal with dynamic saved register sizes -- fp | |
4403 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4404 | and below). */ | |
4405 | ||
4406 | /* Copy a 32-bit single-precision value from the current frame | |
4407 | into rare_buffer. */ | |
4408 | ||
4409 | static void | |
e11c53d2 | 4410 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4411 | gdb_byte *rare_buffer) |
dd824b04 | 4412 | { |
72a155b4 UW |
4413 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4414 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4415 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4416 | |
e11c53d2 | 4417 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4418 | error (_("can't read register %d (%s)"), |
72a155b4 | 4419 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4420 | if (raw_size == 8) |
4421 | { | |
4422 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4423 | 32 bits. */ |
dd824b04 DJ |
4424 | int offset; |
4425 | ||
72a155b4 | 4426 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4427 | offset = 4; |
4428 | else | |
4429 | offset = 0; | |
4430 | ||
4431 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4432 | } | |
4433 | else | |
4434 | { | |
4435 | memcpy (rare_buffer, raw_buffer, 4); | |
4436 | } | |
4437 | } | |
4438 | ||
4439 | /* Copy a 64-bit double-precision value from the current frame into | |
4440 | rare_buffer. This may include getting half of it from the next | |
4441 | register. */ | |
4442 | ||
4443 | static void | |
e11c53d2 | 4444 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4445 | gdb_byte *rare_buffer) |
dd824b04 | 4446 | { |
72a155b4 UW |
4447 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4448 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4449 | |
9c9acae0 | 4450 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4451 | { |
4452 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4453 | all 64 bits. */ |
e11c53d2 | 4454 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4455 | error (_("can't read register %d (%s)"), |
72a155b4 | 4456 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4457 | } |
4458 | else | |
4459 | { | |
72a155b4 | 4460 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4461 | |
72a155b4 | 4462 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4463 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4464 | _("mips_read_fp_register_double: bad access to " |
4465 | "odd-numbered FP register")); | |
dd824b04 DJ |
4466 | |
4467 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4468 | each register. */ |
72a155b4 | 4469 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4470 | { |
e11c53d2 AC |
4471 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4472 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4473 | } |
361d1df0 | 4474 | else |
dd824b04 | 4475 | { |
e11c53d2 AC |
4476 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4477 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4478 | } |
4479 | } | |
4480 | } | |
4481 | ||
c906108c | 4482 | static void |
e11c53d2 AC |
4483 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4484 | int regnum) | |
c5aa993b | 4485 | { /* do values for FP (float) regs */ |
72a155b4 | 4486 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4487 | gdb_byte *raw_buffer; |
3903d437 AC |
4488 | double doub, flt1; /* doubles extracted from raw hex data */ |
4489 | int inv1, inv2; | |
c5aa993b | 4490 | |
72a155b4 | 4491 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4492 | |
72a155b4 | 4493 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4494 | fprintf_filtered (file, "%*s", |
72a155b4 | 4495 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4496 | ""); |
f0ef6b29 | 4497 | |
72a155b4 | 4498 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4499 | { |
79a45b7d TT |
4500 | struct value_print_options opts; |
4501 | ||
f0ef6b29 KB |
4502 | /* 4-byte registers: Print hex and floating. Also print even |
4503 | numbered registers as doubles. */ | |
e11c53d2 | 4504 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 | 4505 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1); |
c5aa993b | 4506 | |
79a45b7d | 4507 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4508 | print_scalar_formatted (raw_buffer, |
4509 | builtin_type (gdbarch)->builtin_uint32, | |
4510 | &opts, 'w', file); | |
dd824b04 | 4511 | |
e11c53d2 | 4512 | fprintf_filtered (file, " flt: "); |
1adad886 | 4513 | if (inv1) |
e11c53d2 | 4514 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4515 | else |
e11c53d2 | 4516 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4517 | |
72a155b4 | 4518 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4519 | { |
e11c53d2 | 4520 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4521 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4522 | raw_buffer, &inv2); | |
1adad886 | 4523 | |
e11c53d2 | 4524 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4525 | if (inv2) |
e11c53d2 | 4526 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4527 | else |
e11c53d2 | 4528 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4529 | } |
c906108c SS |
4530 | } |
4531 | else | |
dd824b04 | 4532 | { |
79a45b7d TT |
4533 | struct value_print_options opts; |
4534 | ||
f0ef6b29 | 4535 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4536 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4537 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4538 | raw_buffer, &inv1); | |
c906108c | 4539 | |
e11c53d2 | 4540 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4541 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4542 | raw_buffer, &inv2); | |
f0ef6b29 | 4543 | |
79a45b7d | 4544 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4545 | print_scalar_formatted (raw_buffer, |
4546 | builtin_type (gdbarch)->builtin_uint64, | |
4547 | &opts, 'g', file); | |
f0ef6b29 | 4548 | |
e11c53d2 | 4549 | fprintf_filtered (file, " flt: "); |
1adad886 | 4550 | if (inv1) |
e11c53d2 | 4551 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4552 | else |
e11c53d2 | 4553 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4554 | |
e11c53d2 | 4555 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4556 | if (inv2) |
e11c53d2 | 4557 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4558 | else |
e11c53d2 | 4559 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4560 | } |
4561 | } | |
4562 | ||
4563 | static void | |
e11c53d2 | 4564 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4565 | int regnum) |
f0ef6b29 | 4566 | { |
a4b8ebc8 | 4567 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4568 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4569 | int offset; |
79a45b7d | 4570 | struct value_print_options opts; |
1adad886 | 4571 | |
7b9ee6a8 | 4572 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4573 | { |
e11c53d2 | 4574 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4575 | return; |
4576 | } | |
4577 | ||
4578 | /* Get the data in raw format. */ | |
e11c53d2 | 4579 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4580 | { |
c9f4d572 | 4581 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4582 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4583 | return; |
c906108c | 4584 | } |
f0ef6b29 | 4585 | |
72a155b4 | 4586 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4587 | |
4588 | /* The problem with printing numeric register names (r26, etc.) is that | |
4589 | the user can't use them on input. Probably the best solution is to | |
4590 | fix it so that either the numeric or the funky (a2, etc.) names | |
4591 | are accepted on input. */ | |
4592 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4593 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4594 | else |
e11c53d2 | 4595 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4596 | |
72a155b4 | 4597 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4598 | offset = |
72a155b4 | 4599 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4600 | else |
4601 | offset = 0; | |
4602 | ||
79a45b7d | 4603 | get_formatted_print_options (&opts, 'x'); |
6d82d43b | 4604 | print_scalar_formatted (raw_buffer + offset, |
79a45b7d | 4605 | register_type (gdbarch, regnum), &opts, 0, |
6d82d43b | 4606 | file); |
c906108c SS |
4607 | } |
4608 | ||
f0ef6b29 KB |
4609 | /* Replacement for generic do_registers_info. |
4610 | Print regs in pretty columns. */ | |
4611 | ||
4612 | static int | |
e11c53d2 AC |
4613 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4614 | int regnum) | |
f0ef6b29 | 4615 | { |
e11c53d2 AC |
4616 | fprintf_filtered (file, " "); |
4617 | mips_print_fp_register (file, frame, regnum); | |
4618 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4619 | return regnum + 1; |
4620 | } | |
4621 | ||
4622 | ||
c906108c SS |
4623 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4624 | ||
4625 | static int | |
e11c53d2 | 4626 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4627 | int start_regnum) |
c906108c | 4628 | { |
a4b8ebc8 | 4629 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4630 | /* do values for GP (int) regs */ |
47a35522 | 4631 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4632 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4633 | int col, byte; |
a4b8ebc8 | 4634 | int regnum; |
c906108c SS |
4635 | |
4636 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4637 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4638 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4639 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4640 | regnum++) |
c906108c | 4641 | { |
72a155b4 | 4642 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4643 | continue; /* unused register */ |
7b9ee6a8 | 4644 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4645 | TYPE_CODE_FLT) |
c5aa993b | 4646 | break; /* end the row: reached FP register */ |
0cc93a06 | 4647 | /* Large registers are handled separately. */ |
72a155b4 | 4648 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4649 | { |
4650 | if (col > 0) | |
4651 | break; /* End the row before this register. */ | |
4652 | ||
4653 | /* Print this register on a row by itself. */ | |
4654 | mips_print_register (file, frame, regnum); | |
4655 | fprintf_filtered (file, "\n"); | |
4656 | return regnum + 1; | |
4657 | } | |
d05f6826 DJ |
4658 | if (col == 0) |
4659 | fprintf_filtered (file, " "); | |
6d82d43b | 4660 | fprintf_filtered (file, |
72a155b4 UW |
4661 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4662 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4663 | col++; |
4664 | } | |
d05f6826 DJ |
4665 | |
4666 | if (col == 0) | |
4667 | return regnum; | |
4668 | ||
a4b8ebc8 | 4669 | /* print the R0 to R31 names */ |
72a155b4 | 4670 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4671 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4672 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4673 | else |
4674 | fprintf_filtered (file, "\n "); | |
c906108c | 4675 | |
c906108c | 4676 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4677 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4678 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4679 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4680 | regnum++) |
c906108c | 4681 | { |
72a155b4 | 4682 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4683 | continue; /* unused register */ |
7b9ee6a8 | 4684 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4685 | TYPE_CODE_FLT) |
c5aa993b | 4686 | break; /* end row: reached FP register */ |
72a155b4 | 4687 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4688 | break; /* End row: large register. */ |
4689 | ||
c906108c | 4690 | /* OK: get the data in raw format. */ |
e11c53d2 | 4691 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4692 | error (_("can't read register %d (%s)"), |
72a155b4 | 4693 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4694 | /* pad small registers */ |
4246e332 | 4695 | for (byte = 0; |
72a155b4 UW |
4696 | byte < (mips_abi_regsize (gdbarch) |
4697 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4698 | printf_filtered (" "); |
4699 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4700 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4701 | for (byte = |
72a155b4 UW |
4702 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4703 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4704 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4705 | else |
72a155b4 | 4706 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4707 | byte >= 0; byte--) |
47a35522 | 4708 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4709 | fprintf_filtered (file, " "); |
c906108c SS |
4710 | col++; |
4711 | } | |
c5aa993b | 4712 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4713 | fprintf_filtered (file, "\n"); |
c906108c SS |
4714 | |
4715 | return regnum; | |
4716 | } | |
4717 | ||
4718 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4719 | ||
bf1f5b4c | 4720 | static void |
e11c53d2 AC |
4721 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4722 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4723 | { |
c5aa993b | 4724 | if (regnum != -1) /* do one specified register */ |
c906108c | 4725 | { |
72a155b4 UW |
4726 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4727 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4728 | error (_("Not a valid register for the current processor type")); |
c906108c | 4729 | |
0cc93a06 | 4730 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4731 | fprintf_filtered (file, "\n"); |
c906108c | 4732 | } |
c5aa993b JM |
4733 | else |
4734 | /* do all (or most) registers */ | |
c906108c | 4735 | { |
72a155b4 UW |
4736 | regnum = gdbarch_num_regs (gdbarch); |
4737 | while (regnum < gdbarch_num_regs (gdbarch) | |
4738 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4739 | { |
7b9ee6a8 | 4740 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4741 | TYPE_CODE_FLT) |
e11c53d2 AC |
4742 | { |
4743 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4744 | regnum = print_fp_register_row (file, frame, regnum); | |
4745 | else | |
4746 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4747 | } | |
c906108c | 4748 | else |
e11c53d2 | 4749 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4750 | } |
4751 | } | |
4752 | } | |
4753 | ||
c906108c SS |
4754 | /* Is this a branch with a delay slot? */ |
4755 | ||
c906108c | 4756 | static int |
acdb74a0 | 4757 | is_delayed (unsigned long insn) |
c906108c SS |
4758 | { |
4759 | int i; | |
4760 | for (i = 0; i < NUMOPCODES; ++i) | |
4761 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4762 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4763 | break; | |
4764 | return (i < NUMOPCODES | |
4765 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4766 | | INSN_COND_BRANCH_DELAY | |
4767 | | INSN_COND_BRANCH_LIKELY))); | |
4768 | } | |
4769 | ||
63807e1d | 4770 | static int |
3352ef37 AC |
4771 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4772 | struct frame_info *frame) | |
c906108c | 4773 | { |
e17a4113 | 4774 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4775 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4776 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4777 | |
4778 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4779 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4780 | return 0; |
4781 | ||
6c95b8df | 4782 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4783 | return 0; |
4784 | ||
3352ef37 AC |
4785 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4786 | /* If error reading memory, guess that it is not a delayed | |
4787 | branch. */ | |
c906108c | 4788 | return 0; |
e17a4113 | 4789 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4790 | } |
4791 | ||
6d82d43b AC |
4792 | /* To skip prologues, I use this predicate. Returns either PC itself |
4793 | if the code at PC does not look like a function prologue; otherwise | |
4794 | returns an address that (if we're lucky) follows the prologue. If | |
4795 | LENIENT, then we must skip everything which is involved in setting | |
4796 | up the frame (it's OK to skip more, just so long as we don't skip | |
4797 | anything which might clobber the registers which are being saved. | |
4798 | We must skip more in the case where part of the prologue is in the | |
4799 | delay slot of a non-prologue instruction). */ | |
4800 | ||
4801 | static CORE_ADDR | |
6093d2eb | 4802 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4803 | { |
8b622e6a AC |
4804 | CORE_ADDR limit_pc; |
4805 | CORE_ADDR func_addr; | |
4806 | ||
6d82d43b AC |
4807 | /* See if we can determine the end of the prologue via the symbol table. |
4808 | If so, then return either PC, or the PC after the prologue, whichever | |
4809 | is greater. */ | |
8b622e6a AC |
4810 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4811 | { | |
d80b854b UW |
4812 | CORE_ADDR post_prologue_pc |
4813 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4814 | if (post_prologue_pc != 0) |
4815 | return max (pc, post_prologue_pc); | |
4816 | } | |
6d82d43b AC |
4817 | |
4818 | /* Can't determine prologue from the symbol table, need to examine | |
4819 | instructions. */ | |
4820 | ||
98b4dd94 JB |
4821 | /* Find an upper limit on the function prologue using the debug |
4822 | information. If the debug information could not be used to provide | |
4823 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4824 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4825 | if (limit_pc == 0) |
4826 | limit_pc = pc + 100; /* Magic. */ | |
4827 | ||
0fe7e7c8 | 4828 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4829 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4830 | else |
e17a4113 | 4831 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4832 | } |
4833 | ||
97ab0fdd MR |
4834 | /* Check whether the PC is in a function epilogue (32-bit version). |
4835 | This is a helper function for mips_in_function_epilogue_p. */ | |
4836 | static int | |
e17a4113 | 4837 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4838 | { |
4839 | CORE_ADDR func_addr = 0, func_end = 0; | |
4840 | ||
4841 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4842 | { | |
4843 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4844 | CORE_ADDR addr = func_end - 12; | |
4845 | ||
4846 | if (addr < func_addr + 4) | |
4847 | addr = func_addr + 4; | |
4848 | if (pc < addr) | |
4849 | return 0; | |
4850 | ||
4851 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4852 | { | |
4853 | unsigned long high_word; | |
4854 | unsigned long inst; | |
4855 | ||
e17a4113 | 4856 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4857 | high_word = (inst >> 16) & 0xffff; |
4858 | ||
4859 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4860 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4861 | && inst != 0x03e00008 /* jr $ra */ | |
4862 | && inst != 0x00000000) /* nop */ | |
4863 | return 0; | |
4864 | } | |
4865 | ||
4866 | return 1; | |
4867 | } | |
4868 | ||
4869 | return 0; | |
4870 | } | |
4871 | ||
4872 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4873 | This is a helper function for mips_in_function_epilogue_p. */ | |
4874 | static int | |
e17a4113 | 4875 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4876 | { |
4877 | CORE_ADDR func_addr = 0, func_end = 0; | |
4878 | ||
4879 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4880 | { | |
4881 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4882 | CORE_ADDR addr = func_end - 12; | |
4883 | ||
4884 | if (addr < func_addr + 4) | |
4885 | addr = func_addr + 4; | |
4886 | if (pc < addr) | |
4887 | return 0; | |
4888 | ||
4889 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4890 | { | |
4891 | unsigned short inst; | |
4892 | ||
e17a4113 | 4893 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4894 | |
4895 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4896 | continue; | |
4897 | ||
4898 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4899 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4900 | && inst != 0xe820 /* jr $ra */ | |
4901 | && inst != 0xe8a0 /* jrc $ra */ | |
4902 | && inst != 0x6500) /* nop */ | |
4903 | return 0; | |
4904 | } | |
4905 | ||
4906 | return 1; | |
4907 | } | |
4908 | ||
4909 | return 0; | |
4910 | } | |
4911 | ||
4912 | /* The epilogue is defined here as the area at the end of a function, | |
4913 | after an instruction which destroys the function's stack frame. */ | |
4914 | static int | |
4915 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4916 | { | |
4917 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 4918 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 4919 | else |
e17a4113 | 4920 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
4921 | } |
4922 | ||
a5ea2558 AC |
4923 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4924 | used for all MIPS-specific commands. */ | |
4925 | ||
a5ea2558 | 4926 | static void |
acdb74a0 | 4927 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4928 | { |
4929 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4930 | } | |
4931 | ||
a5ea2558 | 4932 | static void |
acdb74a0 | 4933 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4934 | { |
6d82d43b AC |
4935 | printf_unfiltered |
4936 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4937 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4938 | } | |
4939 | ||
c906108c SS |
4940 | /* Commands to show/set the MIPS FPU type. */ |
4941 | ||
c906108c | 4942 | static void |
acdb74a0 | 4943 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4944 | { |
c906108c | 4945 | char *fpu; |
6ca0852e | 4946 | |
1cf3db46 | 4947 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
4948 | { |
4949 | printf_unfiltered | |
4950 | ("The MIPS floating-point coprocessor is unknown " | |
4951 | "because the current architecture is not MIPS.\n"); | |
4952 | return; | |
4953 | } | |
4954 | ||
1cf3db46 | 4955 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
4956 | { |
4957 | case MIPS_FPU_SINGLE: | |
4958 | fpu = "single-precision"; | |
4959 | break; | |
4960 | case MIPS_FPU_DOUBLE: | |
4961 | fpu = "double-precision"; | |
4962 | break; | |
4963 | case MIPS_FPU_NONE: | |
4964 | fpu = "absent (none)"; | |
4965 | break; | |
93d56215 | 4966 | default: |
e2e0b3e5 | 4967 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4968 | } |
4969 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4970 | printf_unfiltered |
4971 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4972 | fpu); | |
c906108c | 4973 | else |
6d82d43b AC |
4974 | printf_unfiltered |
4975 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4976 | } |
4977 | ||
4978 | ||
c906108c | 4979 | static void |
acdb74a0 | 4980 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4981 | { |
6d82d43b AC |
4982 | printf_unfiltered |
4983 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4984 | show_mipsfpu_command (args, from_tty); |
4985 | } | |
4986 | ||
c906108c | 4987 | static void |
acdb74a0 | 4988 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4989 | { |
8d5838b5 AC |
4990 | struct gdbarch_info info; |
4991 | gdbarch_info_init (&info); | |
c906108c SS |
4992 | mips_fpu_type = MIPS_FPU_SINGLE; |
4993 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4994 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4995 | instead of relying on globals. Doing that would let generic code | |
4996 | handle the search for this specific architecture. */ | |
4997 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4998 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4999 | } |
5000 | ||
c906108c | 5001 | static void |
acdb74a0 | 5002 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5003 | { |
8d5838b5 AC |
5004 | struct gdbarch_info info; |
5005 | gdbarch_info_init (&info); | |
c906108c SS |
5006 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5007 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5008 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5009 | instead of relying on globals. Doing that would let generic code | |
5010 | handle the search for this specific architecture. */ | |
5011 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5012 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5013 | } |
5014 | ||
c906108c | 5015 | static void |
acdb74a0 | 5016 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5017 | { |
8d5838b5 AC |
5018 | struct gdbarch_info info; |
5019 | gdbarch_info_init (&info); | |
c906108c SS |
5020 | mips_fpu_type = MIPS_FPU_NONE; |
5021 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5022 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5023 | instead of relying on globals. Doing that would let generic code | |
5024 | handle the search for this specific architecture. */ | |
5025 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5026 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5027 | } |
5028 | ||
c906108c | 5029 | static void |
acdb74a0 | 5030 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5031 | { |
5032 | mips_fpu_type_auto = 1; | |
5033 | } | |
5034 | ||
c906108c | 5035 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5036 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5037 | the relevant processor still exists (it dates back to '94) and | |
5038 | secondly this is not the way to do this. The processor type should | |
5039 | be set by forcing an architecture change. */ | |
c906108c | 5040 | |
691c0433 AC |
5041 | void |
5042 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5043 | { |
bb486190 UW |
5044 | struct regcache *regcache = get_current_regcache (); |
5045 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5046 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5047 | ULONGEST prid; |
c906108c | 5048 | |
bb486190 | 5049 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5050 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5051 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5052 | } |
5053 | ||
5054 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5055 | callable as an sfunc. */ | |
5056 | ||
5057 | static void | |
acdb74a0 AC |
5058 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5059 | struct cmd_list_element *c) | |
c906108c SS |
5060 | { |
5061 | reinit_frame_cache (); | |
5062 | } | |
5063 | ||
a89aa300 AC |
5064 | static int |
5065 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5066 | { |
d31431ed AC |
5067 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5068 | disassembler needs to be able to locally determine the ISA, and | |
5069 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5070 | work. */ | |
ec4045ea AC |
5071 | if (mips_pc_is_mips16 (memaddr)) |
5072 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5073 | |
5074 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5075 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5076 | |
e5ab0dce | 5077 | /* Set the disassembler options. */ |
9dae60cc | 5078 | if (!info->disassembler_options) |
e5ab0dce AC |
5079 | /* This string is not recognized explicitly by the disassembler, |
5080 | but it tells the disassembler to not try to guess the ABI from | |
5081 | the bfd elf headers, such that, if the user overrides the ABI | |
5082 | of a program linked as NewABI, the disassembly will follow the | |
5083 | register naming conventions specified by the user. */ | |
5084 | info->disassembler_options = "gpr-names=32"; | |
5085 | ||
c906108c | 5086 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5087 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5088 | return print_insn_big_mips (memaddr, info); |
5089 | else | |
5090 | return print_insn_little_mips (memaddr, info); | |
5091 | } | |
5092 | ||
9dae60cc UW |
5093 | static int |
5094 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5095 | { | |
5096 | /* Set up the disassembler info, so that we get the right | |
5097 | register names from libopcodes. */ | |
5098 | info->disassembler_options = "gpr-names=n32"; | |
5099 | info->flavour = bfd_target_elf_flavour; | |
5100 | ||
5101 | return gdb_print_insn_mips (memaddr, info); | |
5102 | } | |
5103 | ||
5104 | static int | |
5105 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5106 | { | |
5107 | /* Set up the disassembler info, so that we get the right | |
5108 | register names from libopcodes. */ | |
5109 | info->disassembler_options = "gpr-names=64"; | |
5110 | info->flavour = bfd_target_elf_flavour; | |
5111 | ||
5112 | return gdb_print_insn_mips (memaddr, info); | |
5113 | } | |
5114 | ||
3b3b875c UW |
5115 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
5116 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
5117 | It returns a pointer to a string of bytes that encode a breakpoint | |
5118 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
5119 | necessary) to point to the actual memory location where the breakpoint | |
5120 | should be inserted. */ | |
c906108c | 5121 | |
47a35522 | 5122 | static const gdb_byte * |
67d57894 | 5123 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5124 | { |
67d57894 | 5125 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5126 | { |
0fe7e7c8 | 5127 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5128 | { |
47a35522 | 5129 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5130 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5131 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5132 | return mips16_big_breakpoint; |
5133 | } | |
5134 | else | |
5135 | { | |
aaab4dba AC |
5136 | /* The IDT board uses an unusual breakpoint value, and |
5137 | sometimes gets confused when it sees the usual MIPS | |
5138 | breakpoint instruction. */ | |
47a35522 MK |
5139 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5140 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5141 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf JB |
5142 | /* Likewise, IRIX appears to expect a different breakpoint, |
5143 | although this is not apparent until you try to use pthreads. */ | |
5144 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
c906108c | 5145 | |
c5aa993b | 5146 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5147 | |
5148 | if (strcmp (target_shortname, "mips") == 0) | |
5149 | return idt_big_breakpoint; | |
5150 | else if (strcmp (target_shortname, "ddb") == 0 | |
5151 | || strcmp (target_shortname, "pmon") == 0 | |
5152 | || strcmp (target_shortname, "lsi") == 0) | |
5153 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5154 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5155 | return irix_big_breakpoint; | |
c906108c SS |
5156 | else |
5157 | return big_breakpoint; | |
5158 | } | |
5159 | } | |
5160 | else | |
5161 | { | |
0fe7e7c8 | 5162 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5163 | { |
47a35522 | 5164 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5165 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5166 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5167 | return mips16_little_breakpoint; |
5168 | } | |
5169 | else | |
5170 | { | |
47a35522 MK |
5171 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5172 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5173 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5174 | |
c5aa993b | 5175 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5176 | |
5177 | if (strcmp (target_shortname, "mips") == 0) | |
5178 | return idt_little_breakpoint; | |
5179 | else if (strcmp (target_shortname, "ddb") == 0 | |
5180 | || strcmp (target_shortname, "pmon") == 0 | |
5181 | || strcmp (target_shortname, "lsi") == 0) | |
5182 | return pmon_little_breakpoint; | |
5183 | else | |
5184 | return little_breakpoint; | |
5185 | } | |
5186 | } | |
5187 | } | |
5188 | ||
5189 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5190 | PC, which is either the callee or the caller. There are several | |
5191 | cases which must be handled: | |
5192 | ||
5193 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5194 | target PC is in $31 ($ra). |
c906108c | 5195 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5196 | and the target PC is in $2. |
c906108c | 5197 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5198 | before the jal instruction, this is effectively a call stub |
5199 | and the the target PC is in $2. Otherwise this is effectively | |
5200 | a return stub and the target PC is in $18. | |
c906108c SS |
5201 | |
5202 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5203 | gory details. */ |
c906108c | 5204 | |
757a7cc6 | 5205 | static CORE_ADDR |
db5f024e | 5206 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5207 | { |
e17a4113 | 5208 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5209 | char *name; |
5210 | CORE_ADDR start_addr; | |
5211 | ||
5212 | /* Find the starting address and name of the function containing the PC. */ | |
5213 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5214 | return 0; | |
5215 | ||
5216 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5217 | target PC is in $31 ($ra). */ | |
5218 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5219 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5220 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5221 | |
5222 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5223 | { | |
5224 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5225 | and the target PC is in $2. */ | |
5226 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5227 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5228 | |
5229 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5230 | before the jal instruction, this is effectively a call stub |
5231 | and the the target PC is in $2. Otherwise this is effectively | |
5232 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5233 | else if (name[19] == 's' || name[19] == 'd') |
5234 | { | |
5235 | if (pc == start_addr) | |
5236 | { | |
5237 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5238 | stub. Such a stub for a function bar might have a name |
5239 | like __fn_stub_bar, and might look like this: | |
5240 | mfc1 $4,$f13 | |
5241 | mfc1 $5,$f12 | |
5242 | mfc1 $6,$f15 | |
5243 | mfc1 $7,$f14 | |
5244 | la $1,bar (becomes a lui/addiu pair) | |
5245 | jr $1 | |
5246 | So scan down to the lui/addi and extract the target | |
5247 | address from those two instructions. */ | |
c906108c | 5248 | |
52f729a7 | 5249 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5250 | ULONGEST inst; |
c906108c SS |
5251 | int i; |
5252 | ||
5253 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5254 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5255 | 0) | |
c906108c SS |
5256 | return target_pc; |
5257 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5258 | && strcmp (name, "etext") != 0 | |
5259 | && strcmp (name, "_etext") != 0) | |
5260 | return target_pc; | |
5261 | ||
5262 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5263 | The limit on the search is arbitrarily set to 20 |
5264 | instructions. FIXME. */ | |
95ac2dcf | 5265 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5266 | { |
e17a4113 | 5267 | inst = mips_fetch_instruction (gdbarch, target_pc); |
c5aa993b JM |
5268 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
5269 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5270 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5271 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5272 | } |
5273 | ||
5274 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5275 | return target_pc; | |
5276 | } | |
5277 | else | |
5278 | /* This is the 'return' part of a call stub. The return | |
5279 | address is in $r18. */ | |
52f729a7 | 5280 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5281 | } |
5282 | } | |
c5aa993b | 5283 | return 0; /* not a stub */ |
c906108c SS |
5284 | } |
5285 | ||
db5f024e DJ |
5286 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5287 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5288 | so that $t9 has the correct value at function entry. */ | |
5289 | ||
5290 | static CORE_ADDR | |
5291 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5292 | { | |
e17a4113 UW |
5293 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5294 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5295 | struct minimal_symbol *msym; |
5296 | int i; | |
5297 | gdb_byte stub_code[16]; | |
5298 | int32_t stub_words[4]; | |
5299 | ||
5300 | /* The stub for foo is named ".pic.foo", and is either two | |
5301 | instructions inserted before foo or a three instruction sequence | |
5302 | which jumps to foo. */ | |
5303 | msym = lookup_minimal_symbol_by_pc (pc); | |
5304 | if (msym == NULL | |
5305 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5306 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5307 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5308 | return 0; | |
5309 | ||
5310 | /* A two-instruction header. */ | |
5311 | if (MSYMBOL_SIZE (msym) == 8) | |
5312 | return pc + 8; | |
5313 | ||
5314 | /* A three-instruction (plus delay slot) trampoline. */ | |
5315 | if (MSYMBOL_SIZE (msym) == 16) | |
5316 | { | |
5317 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5318 | return 0; | |
5319 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5320 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5321 | 4, byte_order); | |
db5f024e DJ |
5322 | |
5323 | /* A stub contains these instructions: | |
5324 | lui t9, %hi(target) | |
5325 | j target | |
5326 | addiu t9, t9, %lo(target) | |
5327 | nop | |
5328 | ||
5329 | This works even for N64, since stubs are only generated with | |
5330 | -msym32. */ | |
5331 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5332 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5333 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5334 | && stub_words[3] == 0x00000000) | |
5335 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5336 | + (stub_words[2] & 0x0000ffff)); | |
5337 | } | |
5338 | ||
5339 | /* Not a recognized stub. */ | |
5340 | return 0; | |
5341 | } | |
5342 | ||
5343 | static CORE_ADDR | |
5344 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5345 | { | |
5346 | CORE_ADDR target_pc; | |
5347 | ||
5348 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5349 | if (target_pc) | |
5350 | return target_pc; | |
5351 | ||
5352 | target_pc = find_solib_trampoline_target (frame, pc); | |
5353 | if (target_pc) | |
5354 | return target_pc; | |
5355 | ||
5356 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5357 | if (target_pc) | |
5358 | return target_pc; | |
5359 | ||
5360 | return 0; | |
5361 | } | |
5362 | ||
a4b8ebc8 | 5363 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5364 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5365 | |
5366 | static int | |
d3f73121 | 5367 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5368 | { |
a4b8ebc8 | 5369 | int regnum; |
2f38ef89 | 5370 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5371 | regnum = num; |
2f38ef89 | 5372 | else if (num >= 38 && num < 70) |
d3f73121 | 5373 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5374 | else if (num == 70) |
d3f73121 | 5375 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5376 | else if (num == 71) |
d3f73121 | 5377 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5378 | else |
a4b8ebc8 AC |
5379 | /* This will hopefully (eventually) provoke a warning. Should |
5380 | we be calling complaint() here? */ | |
d3f73121 MD |
5381 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5382 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5383 | } |
5384 | ||
2f38ef89 | 5385 | |
a4b8ebc8 | 5386 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5387 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5388 | |
5389 | static int | |
d3f73121 | 5390 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5391 | { |
a4b8ebc8 | 5392 | int regnum; |
2f38ef89 | 5393 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5394 | regnum = num; |
2f38ef89 | 5395 | else if (num >= 32 && num < 64) |
d3f73121 | 5396 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5397 | else if (num == 64) |
d3f73121 | 5398 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5399 | else if (num == 65) |
d3f73121 | 5400 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5401 | else |
a4b8ebc8 AC |
5402 | /* This will hopefully (eventually) provoke a warning. Should we |
5403 | be calling complaint() here? */ | |
d3f73121 MD |
5404 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5405 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5406 | } |
5407 | ||
5408 | static int | |
e7faf938 | 5409 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5410 | { |
5411 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5412 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5413 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5414 | decide if it is valid. Should instead define a standard sim/gdb | |
5415 | register numbering scheme. */ | |
e7faf938 MD |
5416 | if (gdbarch_register_name (gdbarch, |
5417 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5418 | && gdbarch_register_name (gdbarch, | |
5419 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5420 | return regnum; |
5421 | else | |
6d82d43b | 5422 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5423 | } |
5424 | ||
2f38ef89 | 5425 | |
4844f454 CV |
5426 | /* Convert an integer into an address. Extracting the value signed |
5427 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5428 | |
5429 | static CORE_ADDR | |
79dd2d24 | 5430 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5431 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5432 | { |
e17a4113 UW |
5433 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5434 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5435 | } |
5436 | ||
82e91389 DJ |
5437 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5438 | than most other architectures; we just need to be explicit about it, | |
5439 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5440 | an assertion failure. */ | |
5441 | ||
5442 | static void | |
a54fba4c MD |
5443 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5444 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5445 | { |
5446 | *reg = MIPS_SP_REGNUM; | |
5447 | *offset = 0; | |
5448 | } | |
5449 | ||
caaa3122 DJ |
5450 | static void |
5451 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5452 | { | |
5453 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5454 | const char *name = bfd_get_section_name (abfd, sect); | |
5455 | ||
5456 | if (*abip != MIPS_ABI_UNKNOWN) | |
5457 | return; | |
5458 | ||
5459 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5460 | return; | |
5461 | ||
5462 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5463 | *abip = MIPS_ABI_O32; | |
5464 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5465 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5466 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5467 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5468 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5469 | *abip = MIPS_ABI_O64; | |
5470 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5471 | *abip = MIPS_ABI_EABI32; | |
5472 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5473 | *abip = MIPS_ABI_EABI64; | |
5474 | else | |
8a3fe4f8 | 5475 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5476 | } |
5477 | ||
22e47e37 FF |
5478 | static void |
5479 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5480 | { | |
5481 | int *lbp = (int *) obj; | |
5482 | const char *name = bfd_get_section_name (abfd, sect); | |
5483 | ||
5484 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5485 | *lbp = 32; | |
5486 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5487 | *lbp = 64; | |
5488 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5489 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5490 | } | |
5491 | ||
2e4ebe70 DJ |
5492 | static enum mips_abi |
5493 | global_mips_abi (void) | |
5494 | { | |
5495 | int i; | |
5496 | ||
5497 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5498 | if (mips_abi_strings[i] == mips_abi_string) | |
5499 | return (enum mips_abi) i; | |
5500 | ||
e2e0b3e5 | 5501 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5502 | } |
5503 | ||
29709017 DJ |
5504 | static void |
5505 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5506 | { | |
29709017 DJ |
5507 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5508 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5509 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5510 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5511 | |
5512 | /* If the size matches the full set of registers GDB traditionally | |
5513 | knows about, including floating point, for either 32-bit or | |
5514 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5515 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5516 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5517 | |
5518 | /* Otherwise we don't have a useful guess. */ | |
5519 | } | |
5520 | ||
f8b73d13 DJ |
5521 | static struct value * |
5522 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5523 | { | |
5524 | const int *reg_p = baton; | |
5525 | return value_of_register (*reg_p, frame); | |
5526 | } | |
5527 | ||
c2d11a7d | 5528 | static struct gdbarch * |
6d82d43b | 5529 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5530 | { |
c2d11a7d JM |
5531 | struct gdbarch *gdbarch; |
5532 | struct gdbarch_tdep *tdep; | |
5533 | int elf_flags; | |
2e4ebe70 | 5534 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5535 | int i, num_regs; |
8d5838b5 | 5536 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5537 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5538 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5539 | |
5540 | /* Check any target description for validity. */ | |
5541 | if (tdesc_has_registers (info.target_desc)) | |
5542 | { | |
5543 | static const char *const mips_gprs[] = { | |
5544 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5545 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5546 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5547 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5548 | }; | |
5549 | static const char *const mips_fprs[] = { | |
5550 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5551 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5552 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5553 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5554 | }; | |
5555 | ||
5556 | const struct tdesc_feature *feature; | |
5557 | int valid_p; | |
5558 | ||
5559 | feature = tdesc_find_feature (info.target_desc, | |
5560 | "org.gnu.gdb.mips.cpu"); | |
5561 | if (feature == NULL) | |
5562 | return NULL; | |
5563 | ||
5564 | tdesc_data = tdesc_data_alloc (); | |
5565 | ||
5566 | valid_p = 1; | |
5567 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5568 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5569 | mips_gprs[i]); | |
5570 | ||
5571 | ||
5572 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5573 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5574 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5575 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5576 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5577 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5578 | ||
5579 | if (!valid_p) | |
5580 | { | |
5581 | tdesc_data_cleanup (tdesc_data); | |
5582 | return NULL; | |
5583 | } | |
5584 | ||
5585 | feature = tdesc_find_feature (info.target_desc, | |
5586 | "org.gnu.gdb.mips.cp0"); | |
5587 | if (feature == NULL) | |
5588 | { | |
5589 | tdesc_data_cleanup (tdesc_data); | |
5590 | return NULL; | |
5591 | } | |
5592 | ||
5593 | valid_p = 1; | |
5594 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5595 | MIPS_EMBED_BADVADDR_REGNUM, | |
5596 | "badvaddr"); | |
5597 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5598 | MIPS_PS_REGNUM, "status"); | |
5599 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5600 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5601 | ||
5602 | if (!valid_p) | |
5603 | { | |
5604 | tdesc_data_cleanup (tdesc_data); | |
5605 | return NULL; | |
5606 | } | |
5607 | ||
5608 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5609 | backend is not prepared for that, though. */ | |
5610 | feature = tdesc_find_feature (info.target_desc, | |
5611 | "org.gnu.gdb.mips.fpu"); | |
5612 | if (feature == NULL) | |
5613 | { | |
5614 | tdesc_data_cleanup (tdesc_data); | |
5615 | return NULL; | |
5616 | } | |
5617 | ||
5618 | valid_p = 1; | |
5619 | for (i = 0; i < 32; i++) | |
5620 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5621 | i + MIPS_EMBED_FP0_REGNUM, | |
5622 | mips_fprs[i]); | |
5623 | ||
5624 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5625 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5626 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5627 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5628 | ||
5629 | if (!valid_p) | |
5630 | { | |
5631 | tdesc_data_cleanup (tdesc_data); | |
5632 | return NULL; | |
5633 | } | |
5634 | ||
5635 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5636 | when only 32-bit registers are provided. */ | |
5637 | } | |
c2d11a7d | 5638 | |
ec03c1ac AC |
5639 | /* First of all, extract the elf_flags, if available. */ |
5640 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5641 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5642 | else if (arches != NULL) |
5643 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5644 | else |
5645 | elf_flags = 0; | |
5646 | if (gdbarch_debug) | |
5647 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5648 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5649 | |
102182a9 | 5650 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5651 | switch ((elf_flags & EF_MIPS_ABI)) |
5652 | { | |
5653 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5654 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5655 | break; |
5656 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5657 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5658 | break; |
5659 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5660 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5661 | break; |
5662 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5663 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5664 | break; |
5665 | default: | |
acdb74a0 | 5666 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5667 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5668 | else |
ec03c1ac | 5669 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5670 | break; |
5671 | } | |
acdb74a0 | 5672 | |
caaa3122 | 5673 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5674 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5675 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5676 | |
dc305454 | 5677 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5678 | MIPS architecture (if there is one). */ |
5679 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5680 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5681 | |
32a6503c | 5682 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5683 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5684 | && info.bfd_arch_info != NULL |
5685 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5686 | { | |
5687 | switch (info.bfd_arch_info->mach) | |
5688 | { | |
5689 | case bfd_mach_mips3900: | |
ec03c1ac | 5690 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5691 | break; |
5692 | case bfd_mach_mips4100: | |
5693 | case bfd_mach_mips5000: | |
ec03c1ac | 5694 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5695 | break; |
1d06468c EZ |
5696 | case bfd_mach_mips8000: |
5697 | case bfd_mach_mips10000: | |
32a6503c KB |
5698 | /* On Irix, ELF64 executables use the N64 ABI. The |
5699 | pseudo-sections which describe the ABI aren't present | |
5700 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5701 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5702 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5703 | found_abi = MIPS_ABI_N64; |
28d169de | 5704 | else |
ec03c1ac | 5705 | found_abi = MIPS_ABI_N32; |
1d06468c | 5706 | break; |
bf64bfd6 AC |
5707 | } |
5708 | } | |
2e4ebe70 | 5709 | |
26c53e50 DJ |
5710 | /* Default 64-bit objects to N64 instead of O32. */ |
5711 | if (found_abi == MIPS_ABI_UNKNOWN | |
5712 | && info.abfd != NULL | |
5713 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5714 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5715 | found_abi = MIPS_ABI_N64; | |
5716 | ||
ec03c1ac AC |
5717 | if (gdbarch_debug) |
5718 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5719 | found_abi); | |
5720 | ||
5721 | /* What has the user specified from the command line? */ | |
5722 | wanted_abi = global_mips_abi (); | |
5723 | if (gdbarch_debug) | |
5724 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5725 | wanted_abi); | |
2e4ebe70 DJ |
5726 | |
5727 | /* Now that we have found what the ABI for this binary would be, | |
5728 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5729 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5730 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5731 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5732 | mips_abi = found_abi; | |
5733 | else | |
5734 | mips_abi = MIPS_ABI_O32; | |
5735 | if (gdbarch_debug) | |
5736 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5737 | mips_abi); | |
2e4ebe70 | 5738 | |
ec03c1ac | 5739 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5740 | if (gdbarch_debug) |
ec03c1ac AC |
5741 | fprintf_unfiltered (gdb_stdlog, |
5742 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5743 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5744 | |
8d5838b5 | 5745 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5746 | #ifdef HAVE_ELF |
5747 | if (info.abfd | |
5748 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5749 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5750 | Tag_GNU_MIPS_ABI_FP); | |
5751 | #endif /* HAVE_ELF */ | |
5752 | ||
8d5838b5 AC |
5753 | if (!mips_fpu_type_auto) |
5754 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5755 | else if (elf_fpu_type != 0) |
5756 | { | |
5757 | switch (elf_fpu_type) | |
5758 | { | |
5759 | case 1: | |
5760 | fpu_type = MIPS_FPU_DOUBLE; | |
5761 | break; | |
5762 | case 2: | |
5763 | fpu_type = MIPS_FPU_SINGLE; | |
5764 | break; | |
5765 | case 3: | |
5766 | default: | |
5767 | /* Soft float or unknown. */ | |
5768 | fpu_type = MIPS_FPU_NONE; | |
5769 | break; | |
5770 | } | |
5771 | } | |
8d5838b5 AC |
5772 | else if (info.bfd_arch_info != NULL |
5773 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5774 | switch (info.bfd_arch_info->mach) | |
5775 | { | |
5776 | case bfd_mach_mips3900: | |
5777 | case bfd_mach_mips4100: | |
5778 | case bfd_mach_mips4111: | |
a9d61c86 | 5779 | case bfd_mach_mips4120: |
8d5838b5 AC |
5780 | fpu_type = MIPS_FPU_NONE; |
5781 | break; | |
5782 | case bfd_mach_mips4650: | |
5783 | fpu_type = MIPS_FPU_SINGLE; | |
5784 | break; | |
5785 | default: | |
5786 | fpu_type = MIPS_FPU_DOUBLE; | |
5787 | break; | |
5788 | } | |
5789 | else if (arches != NULL) | |
5790 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5791 | else | |
5792 | fpu_type = MIPS_FPU_DOUBLE; | |
5793 | if (gdbarch_debug) | |
5794 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5795 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5796 | |
29709017 DJ |
5797 | /* Check for blatant incompatibilities. */ |
5798 | ||
5799 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5800 | ABI. */ | |
5801 | if (info.target_desc | |
5802 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5803 | && mips_abi != MIPS_ABI_EABI32 | |
5804 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5805 | { |
5806 | if (tdesc_data != NULL) | |
5807 | tdesc_data_cleanup (tdesc_data); | |
5808 | return NULL; | |
5809 | } | |
29709017 | 5810 | |
c2d11a7d JM |
5811 | /* try to find a pre-existing architecture */ |
5812 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5813 | arches != NULL; | |
5814 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5815 | { | |
5816 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5817 | using. */ |
9103eae0 | 5818 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5819 | continue; |
9103eae0 | 5820 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5821 | continue; |
719ec221 AC |
5822 | /* Need to be pedantic about which register virtual size is |
5823 | used. */ | |
5824 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5825 | != mips64_transfers_32bit_regs_p) | |
5826 | continue; | |
8d5838b5 AC |
5827 | /* Be pedantic about which FPU is selected. */ |
5828 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5829 | continue; | |
f8b73d13 DJ |
5830 | |
5831 | if (tdesc_data != NULL) | |
5832 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5833 | return arches->gdbarch; |
c2d11a7d JM |
5834 | } |
5835 | ||
102182a9 | 5836 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5837 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5838 | gdbarch = gdbarch_alloc (&info, tdep); | |
5839 | tdep->elf_flags = elf_flags; | |
719ec221 | 5840 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5841 | tdep->found_abi = found_abi; |
5842 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5843 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5844 | tdep->register_size_valid_p = 0; |
5845 | tdep->register_size = 0; | |
50e8a0d5 HZ |
5846 | tdep->gregset = NULL; |
5847 | tdep->gregset64 = NULL; | |
5848 | tdep->fpregset = NULL; | |
5849 | tdep->fpregset64 = NULL; | |
29709017 DJ |
5850 | |
5851 | if (info.target_desc) | |
5852 | { | |
5853 | /* Some useful properties can be inferred from the target. */ | |
5854 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5855 | { | |
5856 | tdep->register_size_valid_p = 1; | |
5857 | tdep->register_size = 4; | |
5858 | } | |
5859 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5860 | { | |
5861 | tdep->register_size_valid_p = 1; | |
5862 | tdep->register_size = 8; | |
5863 | } | |
5864 | } | |
c2d11a7d | 5865 | |
102182a9 | 5866 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5867 | set_gdbarch_short_bit (gdbarch, 16); |
5868 | set_gdbarch_int_bit (gdbarch, 32); | |
5869 | set_gdbarch_float_bit (gdbarch, 32); | |
5870 | set_gdbarch_double_bit (gdbarch, 64); | |
5871 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5872 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5873 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5874 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5875 | |
6d82d43b | 5876 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5877 | mips_elf_make_msymbol_special); |
5878 | ||
16e109ca | 5879 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5880 | { |
16e109ca | 5881 | const char **reg_names; |
56cea623 AC |
5882 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5883 | struct mips_regnum); | |
f8b73d13 DJ |
5884 | if (tdesc_has_registers (info.target_desc)) |
5885 | { | |
5886 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5887 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5888 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5889 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5890 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5891 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5892 | regnum->fp_control_status = 70; | |
5893 | regnum->fp_implementation_revision = 71; | |
5894 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5895 | reg_names = NULL; | |
5896 | } | |
5897 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5898 | { |
5899 | regnum->fp0 = 32; | |
5900 | regnum->pc = 64; | |
5901 | regnum->cause = 65; | |
5902 | regnum->badvaddr = 66; | |
5903 | regnum->hi = 67; | |
5904 | regnum->lo = 68; | |
5905 | regnum->fp_control_status = 69; | |
5906 | regnum->fp_implementation_revision = 70; | |
5907 | num_regs = 71; | |
16e109ca | 5908 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5909 | } |
5910 | else | |
5911 | { | |
5912 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5913 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5914 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5915 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5916 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5917 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5918 | regnum->fp_control_status = 70; | |
5919 | regnum->fp_implementation_revision = 71; | |
5920 | num_regs = 90; | |
16e109ca AC |
5921 | if (info.bfd_arch_info != NULL |
5922 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5923 | reg_names = mips_tx39_reg_names; | |
5924 | else | |
5925 | reg_names = mips_generic_reg_names; | |
56cea623 | 5926 | } |
3e8c568d | 5927 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 5928 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
5929 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5930 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5931 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5932 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5933 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5934 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5935 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5936 | tdep->mips_processor_reg_names = reg_names; |
5937 | tdep->regnum = regnum; | |
56cea623 | 5938 | } |
fe29b929 | 5939 | |
0dadbba0 | 5940 | switch (mips_abi) |
c2d11a7d | 5941 | { |
0dadbba0 | 5942 | case MIPS_ABI_O32: |
25ab4790 | 5943 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5944 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5945 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5946 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5947 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5948 | set_gdbarch_long_bit (gdbarch, 32); |
5949 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5950 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5951 | break; | |
0dadbba0 | 5952 | case MIPS_ABI_O64: |
25ab4790 | 5953 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5954 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5955 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5956 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5957 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5958 | set_gdbarch_long_bit (gdbarch, 32); |
5959 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5960 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5961 | break; | |
0dadbba0 | 5962 | case MIPS_ABI_EABI32: |
25ab4790 | 5963 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5964 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5965 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5966 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5967 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5968 | set_gdbarch_long_bit (gdbarch, 32); |
5969 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5970 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5971 | break; | |
0dadbba0 | 5972 | case MIPS_ABI_EABI64: |
25ab4790 | 5973 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5974 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5975 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5976 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5977 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5978 | set_gdbarch_long_bit (gdbarch, 64); |
5979 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5980 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5981 | break; | |
0dadbba0 | 5982 | case MIPS_ABI_N32: |
25ab4790 | 5983 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5984 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5985 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5986 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5987 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5988 | set_gdbarch_long_bit (gdbarch, 32); |
5989 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5990 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5991 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5992 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5993 | break; |
5994 | case MIPS_ABI_N64: | |
25ab4790 | 5995 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5996 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5997 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5998 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5999 | tdep->default_mask_address_p = 0; |
6000 | set_gdbarch_long_bit (gdbarch, 64); | |
6001 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6002 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6003 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6004 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6005 | break; |
c2d11a7d | 6006 | default: |
e2e0b3e5 | 6007 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6008 | } |
6009 | ||
22e47e37 FF |
6010 | /* GCC creates a pseudo-section whose name specifies the size of |
6011 | longs, since -mlong32 or -mlong64 may be used independent of | |
6012 | other options. How those options affect pointer sizes is ABI and | |
6013 | architecture dependent, so use them to override the default sizes | |
6014 | set by the ABI. This table shows the relationship between ABI, | |
6015 | -mlongXX, and size of pointers: | |
6016 | ||
6017 | ABI -mlongXX ptr bits | |
6018 | --- -------- -------- | |
6019 | o32 32 32 | |
6020 | o32 64 32 | |
6021 | n32 32 32 | |
6022 | n32 64 64 | |
6023 | o64 32 32 | |
6024 | o64 64 64 | |
6025 | n64 32 32 | |
6026 | n64 64 64 | |
6027 | eabi32 32 32 | |
6028 | eabi32 64 32 | |
6029 | eabi64 32 32 | |
6030 | eabi64 64 64 | |
6031 | ||
6032 | Note that for o32 and eabi32, pointers are always 32 bits | |
6033 | regardless of any -mlongXX option. For all others, pointers and | |
6034 | longs are the same, as set by -mlongXX or set by defaults. | |
6035 | */ | |
6036 | ||
6037 | if (info.abfd != NULL) | |
6038 | { | |
6039 | int long_bit = 0; | |
6040 | ||
6041 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6042 | if (long_bit) | |
6043 | { | |
6044 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6045 | switch (mips_abi) | |
6046 | { | |
6047 | case MIPS_ABI_O32: | |
6048 | case MIPS_ABI_EABI32: | |
6049 | break; | |
6050 | case MIPS_ABI_N32: | |
6051 | case MIPS_ABI_O64: | |
6052 | case MIPS_ABI_N64: | |
6053 | case MIPS_ABI_EABI64: | |
6054 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6055 | break; | |
6056 | default: | |
6057 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6058 | } | |
6059 | } | |
6060 | } | |
6061 | ||
a5ea2558 AC |
6062 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6063 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6064 | comment: | |
6065 | ||
6066 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6067 | flag in object files because to do so would make it impossible to | |
102182a9 | 6068 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6069 | unnecessarily restrictive. |
361d1df0 | 6070 | |
a5ea2558 AC |
6071 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6072 | but to set this flag before gcc is built with such multilibs will | |
6073 | break too many systems.'' | |
6074 | ||
6075 | But even more unhelpfully, the default linker output target for | |
6076 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6077 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6078 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6079 | this flag to detect 32-bit mode would do the wrong thing given |
6080 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6081 | as 32-bit programs by default. */ |
a5ea2558 | 6082 | |
6c997a34 | 6083 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6084 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6085 | |
102182a9 MS |
6086 | /* Add/remove bits from an address. The MIPS needs be careful to |
6087 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6088 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6089 | ||
58dfe9ff AC |
6090 | /* Unwind the frame. */ |
6091 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6092 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6093 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6094 | |
102182a9 | 6095 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6096 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6097 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6098 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6099 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6100 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6101 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6102 | |
c2d11a7d JM |
6103 | /* MIPS version of CALL_DUMMY */ |
6104 | ||
9710e734 AC |
6105 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6106 | replaced by a command, and all targets will default to on stack | |
6107 | (regardless of the stack's execute status). */ | |
6108 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6109 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6110 | |
87783b8b AC |
6111 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6112 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6113 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6114 | ||
f7b9e9fc AC |
6115 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6116 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6117 | |
6118 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6119 | |
97ab0fdd MR |
6120 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6121 | ||
fc0c74b1 AC |
6122 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6123 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6124 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6125 | |
a4b8ebc8 | 6126 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6127 | |
e11c53d2 | 6128 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6129 | |
9dae60cc UW |
6130 | if (mips_abi == MIPS_ABI_N32) |
6131 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6132 | else if (mips_abi == MIPS_ABI_N64) | |
6133 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6134 | else | |
6135 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6136 | |
d92524f1 PM |
6137 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6138 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6139 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6140 | being used as guards for target_stopped_by_watchpoint, why not have |
6141 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6142 | is sitting on? */ |
6143 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6144 | ||
e7d6a6d2 | 6145 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6146 | |
3352ef37 AC |
6147 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
6148 | ||
0d5de010 DJ |
6149 | /* Virtual tables. */ |
6150 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6151 | ||
29709017 DJ |
6152 | mips_register_g_packet_guesses (gdbarch); |
6153 | ||
6de918a6 | 6154 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6155 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6156 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6157 | |
5792a79b | 6158 | /* Unwind the frame. */ |
b8a22b94 DJ |
6159 | dwarf2_append_unwinders (gdbarch); |
6160 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6161 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6162 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6163 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6164 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6165 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6166 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6167 | |
f8b73d13 DJ |
6168 | if (tdesc_data) |
6169 | { | |
6170 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6171 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6172 | |
6173 | /* Override the normal target description methods to handle our | |
6174 | dual real and pseudo registers. */ | |
6175 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6176 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
6177 | ||
6178 | num_regs = gdbarch_num_regs (gdbarch); | |
6179 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6180 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6181 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6182 | } | |
6183 | ||
6184 | /* Add ABI-specific aliases for the registers. */ | |
6185 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6186 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6187 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6188 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6189 | else | |
6190 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6191 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6192 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6193 | ||
6194 | /* Add some other standard aliases. */ | |
6195 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6196 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6197 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6198 | ||
865093a3 AR |
6199 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6200 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6201 | value_of_mips_user_reg, | |
6202 | &mips_numeric_register_aliases[i].regnum); | |
6203 | ||
4b9b3959 AC |
6204 | return gdbarch; |
6205 | } | |
6206 | ||
2e4ebe70 | 6207 | static void |
6d82d43b | 6208 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6209 | { |
6210 | struct gdbarch_info info; | |
6211 | ||
6212 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6213 | mips_gdbarch_init will take care of the rest. */ | |
6214 | gdbarch_info_init (&info); | |
6215 | gdbarch_update_p (info); | |
6216 | } | |
6217 | ||
ad188201 KB |
6218 | /* Print out which MIPS ABI is in use. */ |
6219 | ||
6220 | static void | |
1f8ca57c JB |
6221 | show_mips_abi (struct ui_file *file, |
6222 | int from_tty, | |
6223 | struct cmd_list_element *ignored_cmd, | |
6224 | const char *ignored_value) | |
ad188201 | 6225 | { |
1cf3db46 | 6226 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6227 | fprintf_filtered |
6228 | (file, | |
6229 | "The MIPS ABI is unknown because the current architecture " | |
6230 | "is not MIPS.\n"); | |
ad188201 KB |
6231 | else |
6232 | { | |
6233 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6234 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6235 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6236 | ||
6237 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6238 | fprintf_filtered |
6239 | (file, | |
6240 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6241 | actual_abi_str); |
ad188201 | 6242 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6243 | fprintf_filtered |
6244 | (file, | |
6245 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6246 | actual_abi_str); |
ad188201 KB |
6247 | else |
6248 | { | |
6249 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6250 | fprintf_filtered |
6251 | (file, | |
6252 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6253 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6254 | } |
6255 | } | |
6256 | } | |
6257 | ||
4b9b3959 | 6258 | static void |
72a155b4 | 6259 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6260 | { |
72a155b4 | 6261 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6262 | if (tdep != NULL) |
c2d11a7d | 6263 | { |
acdb74a0 AC |
6264 | int ef_mips_arch; |
6265 | int ef_mips_32bitmode; | |
f49e4e6d | 6266 | /* Determine the ISA. */ |
acdb74a0 AC |
6267 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6268 | { | |
6269 | case E_MIPS_ARCH_1: | |
6270 | ef_mips_arch = 1; | |
6271 | break; | |
6272 | case E_MIPS_ARCH_2: | |
6273 | ef_mips_arch = 2; | |
6274 | break; | |
6275 | case E_MIPS_ARCH_3: | |
6276 | ef_mips_arch = 3; | |
6277 | break; | |
6278 | case E_MIPS_ARCH_4: | |
93d56215 | 6279 | ef_mips_arch = 4; |
acdb74a0 AC |
6280 | break; |
6281 | default: | |
93d56215 | 6282 | ef_mips_arch = 0; |
acdb74a0 AC |
6283 | break; |
6284 | } | |
f49e4e6d | 6285 | /* Determine the size of a pointer. */ |
acdb74a0 | 6286 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6287 | fprintf_unfiltered (file, |
6288 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6289 | tdep->elf_flags); |
4b9b3959 | 6290 | fprintf_unfiltered (file, |
acdb74a0 AC |
6291 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6292 | ef_mips_32bitmode); | |
6293 | fprintf_unfiltered (file, | |
6294 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6295 | ef_mips_arch); | |
6296 | fprintf_unfiltered (file, | |
6297 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6298 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6299 | fprintf_unfiltered (file, |
6300 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6301 | mips_mask_address_p (tdep), |
4014092b | 6302 | tdep->default_mask_address_p); |
c2d11a7d | 6303 | } |
4b9b3959 AC |
6304 | fprintf_unfiltered (file, |
6305 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6306 | MIPS_DEFAULT_FPU_TYPE, | |
6307 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6308 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6309 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6310 | : "???")); | |
74ed0bb4 MD |
6311 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6312 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6313 | fprintf_unfiltered (file, |
6314 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6315 | MIPS_FPU_TYPE (gdbarch), |
6316 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6317 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6318 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6319 | : "???")); |
c2d11a7d JM |
6320 | } |
6321 | ||
6d82d43b | 6322 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6323 | |
c906108c | 6324 | void |
acdb74a0 | 6325 | _initialize_mips_tdep (void) |
c906108c SS |
6326 | { |
6327 | static struct cmd_list_element *mipsfpulist = NULL; | |
6328 | struct cmd_list_element *c; | |
6329 | ||
6d82d43b | 6330 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6331 | if (MIPS_ABI_LAST + 1 |
6332 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6333 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6334 | |
4b9b3959 | 6335 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6336 | |
8d5f9dcb DJ |
6337 | mips_pdr_data = register_objfile_data (); |
6338 | ||
4eb0ad19 DJ |
6339 | /* Create feature sets with the appropriate properties. The values |
6340 | are not important. */ | |
6341 | mips_tdesc_gp32 = allocate_target_description (); | |
6342 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6343 | ||
6344 | mips_tdesc_gp64 = allocate_target_description (); | |
6345 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6346 | ||
a5ea2558 AC |
6347 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6348 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6349 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6350 | &setmipscmdlist, "set mips ", 0, &setlist); |
6351 | ||
6352 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6353 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6354 | &showmipscmdlist, "show mips ", 0, &showlist); |
6355 | ||
2e4ebe70 | 6356 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6357 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6358 | &mips_abi_string, _("\ | |
6359 | Set the MIPS ABI used by this program."), _("\ | |
6360 | Show the MIPS ABI used by this program."), _("\ | |
6361 | This option can be set to one of:\n\ | |
6362 | auto - the default ABI associated with the current binary\n\ | |
6363 | o32\n\ | |
6364 | o64\n\ | |
6365 | n32\n\ | |
6366 | n64\n\ | |
6367 | eabi32\n\ | |
6368 | eabi64"), | |
6369 | mips_abi_update, | |
6370 | show_mips_abi, | |
6371 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6372 | |
c906108c SS |
6373 | /* Let the user turn off floating point and set the fence post for |
6374 | heuristic_proc_start. */ | |
6375 | ||
6376 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6377 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6378 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6379 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6380 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6381 | &mipsfpulist); |
6382 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6383 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6384 | &mipsfpulist); |
6385 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6386 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6387 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6388 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6389 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6390 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6391 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6392 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6393 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6394 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6395 | &mipsfpulist); |
6396 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6397 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6398 | &showlist); |
6399 | ||
c906108c SS |
6400 | /* We really would like to have both "0" and "unlimited" work, but |
6401 | command.c doesn't deal with that. So make it a var_zinteger | |
6402 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6403 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6404 | &heuristic_fence_post, _("\ |
6405 | Set the distance searched for the start of a function."), _("\ | |
6406 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6407 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6408 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6409 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6410 | reinit_frame_cache_sfunc, |
7915a72c | 6411 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6412 | &setlist, &showlist); |
c906108c SS |
6413 | |
6414 | /* Allow the user to control whether the upper bits of 64-bit | |
6415 | addresses should be zeroed. */ | |
7915a72c AC |
6416 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6417 | &mask_address_var, _("\ | |
6418 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6419 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6420 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6421 | allow GDB to determine the correct value."), |
08546159 AC |
6422 | NULL, show_mask_address, |
6423 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6424 | |
6425 | /* Allow the user to control the size of 32 bit registers within the | |
6426 | raw remote packet. */ | |
b3f42336 | 6427 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6428 | &mips64_transfers_32bit_regs_p, _("\ |
6429 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6430 | _("\ | |
6431 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6432 | _("\ | |
719ec221 AC |
6433 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6434 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6435 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6436 | set_mips64_transfers_32bit_regs, |
7915a72c | 6437 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6438 | &setlist, &showlist); |
9ace0497 AC |
6439 | |
6440 | /* Debug this files internals. */ | |
6bcadd06 | 6441 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6442 | &mips_debug, _("\ |
6443 | Set mips debugging."), _("\ | |
6444 | Show mips debugging."), _("\ | |
6445 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6446 | NULL, |
7915a72c | 6447 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6448 | &setdebuglist, &showdebuglist); |
c906108c | 6449 | } |