Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
c906108c | 53 | |
e0f7ec59 | 54 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 55 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 56 | |
dd824b04 DJ |
57 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
58 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
59 | #define ST0_FR (1 << 26) | |
60 | ||
b0069a17 AC |
61 | /* The sizes of floating point registers. */ |
62 | ||
63 | enum | |
64 | { | |
65 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
66 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
67 | }; | |
68 | ||
0dadbba0 | 69 | |
2e4ebe70 DJ |
70 | static const char *mips_abi_string; |
71 | ||
72 | static const char *mips_abi_strings[] = { | |
73 | "auto", | |
74 | "n32", | |
75 | "o32", | |
28d169de | 76 | "n64", |
2e4ebe70 DJ |
77 | "o64", |
78 | "eabi32", | |
79 | "eabi64", | |
80 | NULL | |
81 | }; | |
82 | ||
cce74817 | 83 | struct frame_extra_info |
c5aa993b JM |
84 | { |
85 | mips_extra_func_info_t proc_desc; | |
86 | int num_args; | |
87 | }; | |
cce74817 | 88 | |
d929b26f AC |
89 | /* Various MIPS ISA options (related to stack analysis) can be |
90 | overridden dynamically. Establish an enum/array for managing | |
91 | them. */ | |
92 | ||
53904c9e AC |
93 | static const char size_auto[] = "auto"; |
94 | static const char size_32[] = "32"; | |
95 | static const char size_64[] = "64"; | |
d929b26f | 96 | |
53904c9e | 97 | static const char *size_enums[] = { |
d929b26f AC |
98 | size_auto, |
99 | size_32, | |
100 | size_64, | |
a5ea2558 AC |
101 | 0 |
102 | }; | |
103 | ||
7a292a7a SS |
104 | /* Some MIPS boards don't support floating point while others only |
105 | support single-precision floating-point operations. See also | |
106 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
107 | |
108 | enum mips_fpu_type | |
c5aa993b JM |
109 | { |
110 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
111 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
112 | MIPS_FPU_NONE /* No floating point. */ | |
113 | }; | |
c906108c SS |
114 | |
115 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
116 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
117 | #endif | |
118 | static int mips_fpu_type_auto = 1; | |
119 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 120 | |
9ace0497 | 121 | static int mips_debug = 0; |
7a292a7a | 122 | |
c2d11a7d JM |
123 | /* MIPS specific per-architecture information */ |
124 | struct gdbarch_tdep | |
125 | { | |
126 | /* from the elf header */ | |
127 | int elf_flags; | |
70f80edf | 128 | |
c2d11a7d | 129 | /* mips options */ |
0dadbba0 | 130 | enum mips_abi mips_abi; |
2e4ebe70 | 131 | enum mips_abi found_abi; |
c2d11a7d JM |
132 | enum mips_fpu_type mips_fpu_type; |
133 | int mips_last_arg_regnum; | |
134 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 135 | int mips_default_saved_regsize; |
c2d11a7d | 136 | int mips_fp_register_double; |
d929b26f | 137 | int mips_default_stack_argsize; |
4014092b | 138 | int default_mask_address_p; |
719ec221 AC |
139 | /* Is the target using 64-bit raw integer registers but only |
140 | storing a left-aligned 32-bit value in each? */ | |
141 | int mips64_transfers_32bit_regs_p; | |
56cea623 AC |
142 | /* Indexes for various registers. IRIX and embedded have |
143 | different values. This contains the "public" fields. Don't | |
144 | add any that do not need to be public. */ | |
145 | const struct mips_regnum *regnum; | |
691c0433 AC |
146 | /* Register names table for the current register set. */ |
147 | const char **mips_processor_reg_names; | |
c2d11a7d JM |
148 | }; |
149 | ||
56cea623 AC |
150 | const struct mips_regnum * |
151 | mips_regnum (struct gdbarch *gdbarch) | |
152 | { | |
153 | return gdbarch_tdep (gdbarch)->regnum; | |
154 | } | |
155 | ||
156 | static int | |
157 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
158 | { | |
159 | return mips_regnum (gdbarch)->fp0 + 12; | |
160 | } | |
161 | ||
0dadbba0 | 162 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 163 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 164 | |
c2d11a7d | 165 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 166 | |
c2d11a7d | 167 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 168 | |
c2d11a7d | 169 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 170 | |
d929b26f AC |
171 | /* Return the currently configured (or set) saved register size. */ |
172 | ||
a5ea2558 | 173 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 174 | |
53904c9e | 175 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
176 | |
177 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
178 | ||
95404a3e AC |
179 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
180 | functions to test, set, or clear bit 0 of addresses. */ | |
181 | ||
182 | static CORE_ADDR | |
183 | is_mips16_addr (CORE_ADDR addr) | |
184 | { | |
185 | return ((addr) & 1); | |
186 | } | |
187 | ||
188 | static CORE_ADDR | |
189 | make_mips16_addr (CORE_ADDR addr) | |
190 | { | |
191 | return ((addr) | 1); | |
192 | } | |
193 | ||
194 | static CORE_ADDR | |
195 | unmake_mips16_addr (CORE_ADDR addr) | |
196 | { | |
197 | return ((addr) & ~1); | |
198 | } | |
199 | ||
22540ece AC |
200 | /* Return the contents of register REGNUM as a signed integer. */ |
201 | ||
202 | static LONGEST | |
203 | read_signed_register (int regnum) | |
204 | { | |
719ec221 | 205 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 206 | deprecated_read_register_gen (regnum, buf); |
719ec221 | 207 | return (extract_signed_integer (buf, register_size (current_gdbarch, regnum))); |
22540ece AC |
208 | } |
209 | ||
210 | static LONGEST | |
211 | read_signed_register_pid (int regnum, ptid_t ptid) | |
212 | { | |
213 | ptid_t save_ptid; | |
214 | LONGEST retval; | |
215 | ||
216 | if (ptid_equal (ptid, inferior_ptid)) | |
217 | return read_signed_register (regnum); | |
218 | ||
219 | save_ptid = inferior_ptid; | |
220 | ||
221 | inferior_ptid = ptid; | |
222 | ||
223 | retval = read_signed_register (regnum); | |
224 | ||
225 | inferior_ptid = save_ptid; | |
226 | ||
227 | return retval; | |
228 | } | |
229 | ||
d1973055 KB |
230 | /* Return the MIPS ABI associated with GDBARCH. */ |
231 | enum mips_abi | |
232 | mips_abi (struct gdbarch *gdbarch) | |
233 | { | |
234 | return gdbarch_tdep (gdbarch)->mips_abi; | |
235 | } | |
236 | ||
4246e332 AC |
237 | int |
238 | mips_regsize (struct gdbarch *gdbarch) | |
239 | { | |
240 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
241 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
242 | } | |
243 | ||
d929b26f | 244 | static unsigned int |
acdb74a0 | 245 | mips_saved_regsize (void) |
d929b26f AC |
246 | { |
247 | if (mips_saved_regsize_string == size_auto) | |
248 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
249 | else if (mips_saved_regsize_string == size_64) | |
250 | return 8; | |
251 | else /* if (mips_saved_regsize_string == size_32) */ | |
252 | return 4; | |
253 | } | |
254 | ||
71b8ef93 | 255 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 256 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 257 | "info" field is used for this purpose. |
5a89d8aa MS |
258 | |
259 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
260 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
261 | minimal symbol to mark it as a 16-bit function | |
262 | ||
f594e5e9 | 263 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 264 | |
5a89d8aa MS |
265 | static void |
266 | mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
267 | { | |
268 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) | |
269 | { | |
270 | MSYMBOL_INFO (msym) = (char *) | |
271 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
272 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
273 | } | |
274 | } | |
275 | ||
71b8ef93 MS |
276 | static int |
277 | msymbol_is_special (struct minimal_symbol *msym) | |
278 | { | |
279 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
280 | } | |
281 | ||
88658117 AC |
282 | /* XFER a value from the big/little/left end of the register. |
283 | Depending on the size of the value it might occupy the entire | |
284 | register or just part of it. Make an allowance for this, aligning | |
285 | things accordingly. */ | |
286 | ||
287 | static void | |
288 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
289 | enum bfd_endian endian, bfd_byte *in, const bfd_byte *out, | |
290 | int buf_offset) | |
291 | { | |
d9d9c31f | 292 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 | 293 | int reg_offset = 0; |
a4b8ebc8 | 294 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
295 | /* Need to transfer the left or right part of the register, based on |
296 | the targets byte order. */ | |
88658117 AC |
297 | switch (endian) |
298 | { | |
299 | case BFD_ENDIAN_BIG: | |
719ec221 | 300 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
301 | break; |
302 | case BFD_ENDIAN_LITTLE: | |
303 | reg_offset = 0; | |
304 | break; | |
305 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ | |
306 | reg_offset = 0; | |
307 | break; | |
308 | default: | |
309 | internal_error (__FILE__, __LINE__, "bad switch"); | |
310 | } | |
311 | if (mips_debug) | |
cb1d2653 AC |
312 | fprintf_unfiltered (gdb_stderr, |
313 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
314 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
315 | if (mips_debug && out != NULL) |
316 | { | |
317 | int i; | |
cb1d2653 | 318 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 319 | for (i = 0; i < length; i++) |
cb1d2653 | 320 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
321 | } |
322 | if (in != NULL) | |
a4b8ebc8 | 323 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset); |
88658117 | 324 | if (out != NULL) |
a4b8ebc8 | 325 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
326 | if (mips_debug && in != NULL) |
327 | { | |
328 | int i; | |
cb1d2653 | 329 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 330 | for (i = 0; i < length; i++) |
cb1d2653 | 331 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
332 | } |
333 | if (mips_debug) | |
334 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
335 | } | |
336 | ||
dd824b04 DJ |
337 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
338 | compatiblity mode. A return value of 1 means that we have | |
339 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
340 | ||
341 | static int | |
342 | mips2_fp_compat (void) | |
343 | { | |
344 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
345 | meaningful. */ | |
56cea623 | 346 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 4) |
dd824b04 DJ |
347 | return 0; |
348 | ||
349 | #if 0 | |
350 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
351 | in all the places we deal with FP registers. PR gdb/413. */ | |
352 | /* Otherwise check the FR bit in the status register - it controls | |
353 | the FP compatiblity mode. If it is clear we are in compatibility | |
354 | mode. */ | |
355 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
356 | return 1; | |
357 | #endif | |
361d1df0 | 358 | |
dd824b04 DJ |
359 | return 0; |
360 | } | |
361 | ||
c2d11a7d JM |
362 | /* Indicate that the ABI makes use of double-precision registers |
363 | provided by the FPU (rather than combining pairs of registers to | |
8fa9cfa1 | 364 | form double-precision values). See also MIPS_FPU_TYPE. */ |
c2d11a7d | 365 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 366 | |
d929b26f AC |
367 | /* The amount of space reserved on the stack for registers. This is |
368 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
369 | data allocated after the registers have run out. */ | |
370 | ||
0dadbba0 | 371 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
372 | |
373 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
374 | ||
53904c9e | 375 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
376 | |
377 | static unsigned int | |
378 | mips_stack_argsize (void) | |
379 | { | |
380 | if (mips_stack_argsize_string == size_auto) | |
381 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
382 | else if (mips_stack_argsize_string == size_64) | |
383 | return 8; | |
384 | else /* if (mips_stack_argsize_string == size_32) */ | |
385 | return 4; | |
386 | } | |
387 | ||
92e1c15c | 388 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 389 | |
7a292a7a | 390 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 391 | |
570b8f7c AC |
392 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
393 | struct frame_info *, int); | |
c906108c | 394 | |
a14ed312 | 395 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 396 | |
a14ed312 | 397 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 398 | |
a14ed312 | 399 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 400 | |
570b8f7c AC |
401 | static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, |
402 | struct frame_info *next_frame, | |
403 | int cur_frame); | |
c906108c | 404 | |
a14ed312 KB |
405 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
406 | mips_extra_func_info_t proc_desc); | |
c906108c | 407 | |
67b2c998 DJ |
408 | static struct type *mips_float_register_type (void); |
409 | static struct type *mips_double_register_type (void); | |
410 | ||
acdb74a0 AC |
411 | /* The list of available "set mips " and "show mips " commands */ |
412 | ||
413 | static struct cmd_list_element *setmipscmdlist = NULL; | |
414 | static struct cmd_list_element *showmipscmdlist = NULL; | |
415 | ||
5e2e9765 KB |
416 | /* Integer registers 0 thru 31 are handled explicitly by |
417 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
418 | are listed in the followign tables. */ |
419 | ||
420 | enum { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
421 | ||
422 | /* Generic MIPS. */ | |
423 | ||
424 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
425 | "sr", "lo", "hi", "bad", "cause","pc", | |
426 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
427 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
428 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
429 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
430 | "fsr", "fir", ""/*"fp"*/, "", | |
431 | "", "", "", "", "", "", "", "", | |
432 | "", "", "", "", "", "", "", "", | |
433 | }; | |
434 | ||
435 | /* Names of IDT R3041 registers. */ | |
436 | ||
437 | static const char *mips_r3041_reg_names[] = { | |
438 | "sr", "lo", "hi", "bad", "cause","pc", | |
439 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
440 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
441 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
442 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
443 | "fsr", "fir", "",/*"fp"*/ "", | |
444 | "", "", "bus", "ccfg", "", "", "", "", | |
445 | "", "", "port", "cmp", "", "", "epc", "prid", | |
446 | }; | |
447 | ||
448 | /* Names of tx39 registers. */ | |
449 | ||
450 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
451 | "sr", "lo", "hi", "bad", "cause","pc", | |
452 | "", "", "", "", "", "", "", "", | |
453 | "", "", "", "", "", "", "", "", | |
454 | "", "", "", "", "", "", "", "", | |
455 | "", "", "", "", "", "", "", "", | |
456 | "", "", "", "", | |
457 | "", "", "", "", "", "", "", "", | |
458 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
459 | }; | |
460 | ||
461 | /* Names of IRIX registers. */ | |
462 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
463 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
464 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
465 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
466 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
467 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
468 | }; | |
469 | ||
cce74817 | 470 | |
5e2e9765 | 471 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 472 | static const char * |
5e2e9765 | 473 | mips_register_name (int regno) |
cce74817 | 474 | { |
691c0433 | 475 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
476 | /* GPR names for all ABIs other than n32/n64. */ |
477 | static char *mips_gpr_names[] = { | |
478 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
479 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
480 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
481 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
482 | }; | |
483 | ||
484 | /* GPR names for n32 and n64 ABIs. */ | |
485 | static char *mips_n32_n64_gpr_names[] = { | |
486 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
487 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
488 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
489 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
490 | }; | |
491 | ||
492 | enum mips_abi abi = mips_abi (current_gdbarch); | |
493 | ||
a4b8ebc8 AC |
494 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
495 | don't make the raw register names visible. */ | |
496 | int rawnum = regno % NUM_REGS; | |
497 | if (regno < NUM_REGS) | |
498 | return ""; | |
499 | ||
5e2e9765 KB |
500 | /* The MIPS integer registers are always mapped from 0 to 31. The |
501 | names of the registers (which reflects the conventions regarding | |
502 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 503 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
504 | { |
505 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 506 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 507 | else |
a4b8ebc8 | 508 | return mips_gpr_names[rawnum]; |
5e2e9765 | 509 | } |
a4b8ebc8 | 510 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
511 | { |
512 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
513 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
514 | } | |
5e2e9765 KB |
515 | else |
516 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 517 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 518 | } |
5e2e9765 | 519 | |
a4b8ebc8 | 520 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 521 | |
a4b8ebc8 AC |
522 | static int |
523 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
524 | struct reggroup *reggroup) | |
525 | { | |
526 | int vector_p; | |
527 | int float_p; | |
528 | int raw_p; | |
529 | int rawnum = regnum % NUM_REGS; | |
530 | int pseudo = regnum / NUM_REGS; | |
531 | if (reggroup == all_reggroup) | |
532 | return pseudo; | |
533 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
534 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
535 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
536 | (gdbarch), as not all architectures are multi-arch. */ | |
537 | raw_p = rawnum < NUM_REGS; | |
538 | if (REGISTER_NAME (regnum) == NULL | |
539 | || REGISTER_NAME (regnum)[0] == '\0') | |
540 | return 0; | |
541 | if (reggroup == float_reggroup) | |
542 | return float_p && pseudo; | |
543 | if (reggroup == vector_reggroup) | |
544 | return vector_p && pseudo; | |
545 | if (reggroup == general_reggroup) | |
546 | return (!vector_p && !float_p) && pseudo; | |
547 | /* Save the pseudo registers. Need to make certain that any code | |
548 | extracting register values from a saved register cache also uses | |
549 | pseudo registers. */ | |
550 | if (reggroup == save_reggroup) | |
551 | return raw_p && pseudo; | |
552 | /* Restore the same pseudo register. */ | |
553 | if (reggroup == restore_reggroup) | |
554 | return raw_p && pseudo; | |
555 | return 0; | |
556 | } | |
557 | ||
558 | /* Map the symbol table registers which live in the range [1 * | |
559 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 560 | registers. Take care of alignment and size problems. */ |
c5aa993b | 561 | |
a4b8ebc8 AC |
562 | static void |
563 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
564 | int cookednum, void *buf) | |
565 | { | |
47ebcfbe | 566 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 567 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
568 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
569 | return regcache_raw_read (regcache, rawnum, buf); | |
570 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
571 | { | |
572 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
573 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
574 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
575 | else | |
576 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
577 | } | |
578 | else | |
579 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
580 | } |
581 | ||
582 | static void | |
583 | mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
584 | int cookednum, const void *buf) | |
585 | { | |
47ebcfbe | 586 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 587 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe AC |
588 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
589 | return regcache_raw_write (regcache, rawnum, buf); | |
590 | else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum)) | |
591 | { | |
592 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
593 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
594 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
595 | else | |
596 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
597 | } | |
598 | else | |
599 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 600 | } |
c5aa993b | 601 | |
c906108c | 602 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
603 | static int mips16_to_32_reg[8] = |
604 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
605 | |
606 | /* Heuristic_proc_start may hunt through the text section for a long | |
607 | time across a 2400 baud serial line. Allows the user to limit this | |
608 | search. */ | |
609 | ||
610 | static unsigned int heuristic_fence_post = 0; | |
611 | ||
c5aa993b JM |
612 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
613 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
614 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
615 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
616 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
617 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
618 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
619 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
620 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
621 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
622 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
623 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
624 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
625 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
626 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
627 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
628 | ||
629 | struct linked_proc_info | |
c5aa993b JM |
630 | { |
631 | struct mips_extra_func_info info; | |
632 | struct linked_proc_info *next; | |
633 | } | |
634 | *linked_proc_desc_table = NULL; | |
c906108c | 635 | |
46cd78fb | 636 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
637 | register N. NOTE: This defines the pseudo register type so need to |
638 | rebuild the architecture vector. */ | |
43e526b9 JM |
639 | |
640 | static int mips64_transfers_32bit_regs_p = 0; | |
641 | ||
719ec221 AC |
642 | static void |
643 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
644 | struct cmd_list_element *c) | |
43e526b9 | 645 | { |
719ec221 AC |
646 | struct gdbarch_info info; |
647 | gdbarch_info_init (&info); | |
648 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
649 | instead of relying on globals. Doing that would let generic code | |
650 | handle the search for this specific architecture. */ | |
651 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 652 | { |
719ec221 AC |
653 | mips64_transfers_32bit_regs_p = 0; |
654 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 655 | } |
a4b8ebc8 AC |
656 | } |
657 | ||
47ebcfbe | 658 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 659 | |
ff2e87ac AC |
660 | static int |
661 | mips_convert_register_p (int regnum, struct type *type) | |
662 | { | |
663 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 664 | && register_size (current_gdbarch, regnum) == 4 |
56cea623 | 665 | && (regnum) >= mips_regnum (current_gdbarch)->fp0 && (regnum) < mips_regnum (current_gdbarch)->fp0 + 32 |
ff2e87ac AC |
666 | && TYPE_CODE(type) == TYPE_CODE_FLT |
667 | && TYPE_LENGTH(type) == 8); | |
668 | } | |
669 | ||
42c466d7 | 670 | static void |
ff2e87ac AC |
671 | mips_register_to_value (struct frame_info *frame, int regnum, |
672 | struct type *type, void *to) | |
102182a9 | 673 | { |
7f5f525d AC |
674 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
675 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
676 | } |
677 | ||
42c466d7 | 678 | static void |
ff2e87ac AC |
679 | mips_value_to_register (struct frame_info *frame, int regnum, |
680 | struct type *type, const void *from) | |
102182a9 | 681 | { |
ff2e87ac AC |
682 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
683 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
684 | } |
685 | ||
a4b8ebc8 AC |
686 | /* Return the GDB type object for the "standard" data type of data in |
687 | register REG. */ | |
78fde5f8 KB |
688 | |
689 | static struct type * | |
a4b8ebc8 AC |
690 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
691 | { | |
5ef80fb0 | 692 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
693 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
694 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 695 | { |
5ef80fb0 AC |
696 | /* The floating-point registers raw, or cooked, always match |
697 | mips_regsize(), and also map 1:1, byte for byte. */ | |
698 | switch (gdbarch_byte_order (gdbarch)) | |
699 | { | |
700 | case BFD_ENDIAN_BIG: | |
701 | if (mips_regsize (gdbarch) == 4) | |
702 | return builtin_type_ieee_single_big; | |
703 | else | |
704 | return builtin_type_ieee_double_big; | |
705 | case BFD_ENDIAN_LITTLE: | |
706 | if (mips_regsize (gdbarch) == 4) | |
707 | return builtin_type_ieee_single_little; | |
708 | else | |
709 | return builtin_type_ieee_double_little; | |
710 | case BFD_ENDIAN_UNKNOWN: | |
711 | default: | |
712 | internal_error (__FILE__, __LINE__, "bad switch"); | |
713 | } | |
a6425924 | 714 | } |
56cea623 | 715 | else if (regnum >= (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) |
5ef80fb0 AC |
716 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) |
717 | /* The pseudo/cooked view of the embedded registers is always | |
718 | 32-bit. The raw view is handled below. */ | |
719 | return builtin_type_int32; | |
719ec221 AC |
720 | else if (regnum >= NUM_REGS && mips_regsize (gdbarch) |
721 | && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
722 | /* The target, while using a 64-bit register buffer, is only | |
723 | transfering 32-bits of each integer register. Reflect this in | |
724 | the cooked/pseudo register value. */ | |
725 | return builtin_type_int32; | |
5ef80fb0 AC |
726 | else if (mips_regsize (gdbarch) == 8) |
727 | /* 64-bit ISA. */ | |
728 | return builtin_type_int64; | |
78fde5f8 | 729 | else |
5ef80fb0 AC |
730 | /* 32-bit ISA. */ |
731 | return builtin_type_int32; | |
78fde5f8 KB |
732 | } |
733 | ||
bcb0cc15 MS |
734 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
735 | ||
736 | static CORE_ADDR | |
737 | mips_read_sp (void) | |
738 | { | |
e227b13c | 739 | return read_signed_register (SP_REGNUM); |
bcb0cc15 MS |
740 | } |
741 | ||
c906108c | 742 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 743 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
744 | |
745 | static int | |
746 | mips_mask_address_p (void) | |
747 | { | |
748 | switch (mask_address_var) | |
749 | { | |
7f19b9a2 | 750 | case AUTO_BOOLEAN_TRUE: |
4014092b | 751 | return 1; |
7f19b9a2 | 752 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
753 | return 0; |
754 | break; | |
7f19b9a2 | 755 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 756 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 757 | default: |
8e65ff28 AC |
758 | internal_error (__FILE__, __LINE__, |
759 | "mips_mask_address_p: bad switch"); | |
4014092b | 760 | return -1; |
361d1df0 | 761 | } |
4014092b AC |
762 | } |
763 | ||
764 | static void | |
e9e68a56 | 765 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
766 | { |
767 | switch (mask_address_var) | |
768 | { | |
7f19b9a2 | 769 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
770 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
771 | break; | |
7f19b9a2 | 772 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
773 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
774 | break; | |
7f19b9a2 | 775 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
776 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
777 | mips_mask_address_p () ? "enabled" : "disabled"); | |
778 | break; | |
779 | default: | |
8e65ff28 AC |
780 | internal_error (__FILE__, __LINE__, |
781 | "show_mask_address: bad switch"); | |
4014092b | 782 | break; |
361d1df0 | 783 | } |
4014092b | 784 | } |
c906108c SS |
785 | |
786 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 787 | |
f7ab6ec6 | 788 | static int |
cb811fe7 | 789 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 790 | { |
cb811fe7 MS |
791 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
792 | } | |
793 | ||
8b389c40 MS |
794 | /* Should call_function pass struct by reference? |
795 | For each architecture, structs are passed either by | |
796 | value or by reference, depending on their size. */ | |
797 | ||
798 | static int | |
799 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
800 | { | |
801 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
802 | int len = TYPE_LENGTH (check_typedef (type)); | |
803 | ||
804 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
805 | return (len > MIPS_SAVED_REGSIZE); | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static int | |
811 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
812 | { | |
813 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
814 | } | |
815 | ||
f7ab6ec6 | 816 | static int |
8b389c40 MS |
817 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) |
818 | { | |
819 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
820 | } | |
821 | ||
c906108c SS |
822 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
823 | ||
824 | static int | |
825 | pc_is_mips16 (bfd_vma memaddr) | |
826 | { | |
827 | struct minimal_symbol *sym; | |
828 | ||
829 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 830 | if (is_mips16_addr (memaddr)) |
c906108c SS |
831 | return 1; |
832 | ||
833 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
834 | the high bit of the info field. Use this to decide if the function is | |
835 | MIPS16 or normal MIPS. */ | |
836 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
837 | if (sym) | |
71b8ef93 | 838 | return msymbol_is_special (sym); |
c906108c SS |
839 | else |
840 | return 0; | |
841 | } | |
842 | ||
6c997a34 AC |
843 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
844 | all registers should be sign extended for simplicity? */ | |
845 | ||
846 | static CORE_ADDR | |
39f77062 | 847 | mips_read_pc (ptid_t ptid) |
6c997a34 | 848 | { |
39f77062 | 849 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 850 | } |
c906108c SS |
851 | |
852 | /* This returns the PC of the first inst after the prologue. If we can't | |
853 | find the prologue, then return 0. */ | |
854 | ||
855 | static CORE_ADDR | |
acdb74a0 AC |
856 | after_prologue (CORE_ADDR pc, |
857 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
858 | { |
859 | struct symtab_and_line sal; | |
860 | CORE_ADDR func_addr, func_end; | |
861 | ||
479412cd DJ |
862 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
863 | to read the stack pointer from the current machine state, because | |
864 | the current machine state has nothing to do with the information | |
865 | we need from the proc_desc; and the process may or may not exist | |
866 | right now. */ | |
c906108c | 867 | if (!proc_desc) |
479412cd | 868 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
869 | |
870 | if (proc_desc) | |
871 | { | |
872 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 873 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
874 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
875 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
876 | return 0; | |
877 | } | |
878 | ||
879 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
880 | return 0; /* Unknown */ | |
881 | ||
882 | sal = find_pc_line (func_addr, 0); | |
883 | ||
884 | if (sal.end < func_end) | |
885 | return sal.end; | |
886 | ||
887 | /* The line after the prologue is after the end of the function. In this | |
888 | case, tell the caller to find the prologue the hard way. */ | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
894 | set the appropriate bit in the general register mask or float register mask | |
895 | to indicate which register is saved. This is a helper function | |
896 | for mips_find_saved_regs. */ | |
897 | ||
898 | static void | |
acdb74a0 AC |
899 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
900 | unsigned long *float_mask) | |
c906108c SS |
901 | { |
902 | int reg; | |
903 | ||
904 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
905 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
906 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
907 | { | |
908 | /* It might be possible to use the instruction to | |
c5aa993b JM |
909 | find the offset, rather than the code below which |
910 | is based on things being in a certain order in the | |
911 | frame, but figuring out what the instruction's offset | |
912 | is relative to might be a little tricky. */ | |
c906108c SS |
913 | reg = (inst & 0x001f0000) >> 16; |
914 | *gen_mask |= (1 << reg); | |
915 | } | |
916 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
917 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
918 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
919 | |
920 | { | |
921 | reg = ((inst & 0x001f0000) >> 16); | |
922 | *float_mask |= (1 << reg); | |
923 | } | |
924 | } | |
925 | ||
926 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
927 | set the appropriate bit in the general register or float register mask | |
928 | to indicate which register is saved. This is a helper function | |
929 | for mips_find_saved_regs. */ | |
930 | ||
931 | static void | |
acdb74a0 | 932 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 933 | { |
c5aa993b | 934 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
935 | { |
936 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
937 | *gen_mask |= (1 << reg); | |
938 | } | |
c5aa993b | 939 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
940 | { |
941 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
942 | *gen_mask |= (1 << reg); | |
943 | } | |
c5aa993b | 944 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
945 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
946 | *gen_mask |= (1 << RA_REGNUM); | |
947 | } | |
948 | ||
949 | ||
950 | /* Fetch and return instruction from the specified location. If the PC | |
951 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
952 | ||
953 | static t_inst | |
acdb74a0 | 954 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
955 | { |
956 | char buf[MIPS_INSTLEN]; | |
957 | int instlen; | |
958 | int status; | |
959 | ||
960 | if (pc_is_mips16 (addr)) | |
961 | { | |
962 | instlen = MIPS16_INSTLEN; | |
95404a3e | 963 | addr = unmake_mips16_addr (addr); |
c906108c SS |
964 | } |
965 | else | |
c5aa993b | 966 | instlen = MIPS_INSTLEN; |
c906108c SS |
967 | status = read_memory_nobpt (addr, buf, instlen); |
968 | if (status) | |
969 | memory_error (status, addr); | |
970 | return extract_unsigned_integer (buf, instlen); | |
971 | } | |
972 | ||
973 | ||
974 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
975 | #define mips32_op(x) (x >> 26) |
976 | #define itype_op(x) (x >> 26) | |
977 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 978 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 979 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 980 | |
e135b889 DJ |
981 | #define jtype_op(x) (x >> 26) |
982 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 983 | |
e135b889 DJ |
984 | #define rtype_op(x) (x >> 26) |
985 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
986 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
987 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
988 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
989 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
990 | |
991 | static CORE_ADDR | |
c5aa993b JM |
992 | mips32_relative_offset (unsigned long inst) |
993 | { | |
994 | long x; | |
995 | x = itype_immediate (inst); | |
996 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 997 | { |
c5aa993b | 998 | x |= 0xffff0000; /* sign extension */ |
c906108c | 999 | } |
c5aa993b JM |
1000 | x = x << 2; |
1001 | return x; | |
c906108c SS |
1002 | } |
1003 | ||
1004 | /* Determine whate to set a single step breakpoint while considering | |
1005 | branch prediction */ | |
5a89d8aa | 1006 | static CORE_ADDR |
c5aa993b JM |
1007 | mips32_next_pc (CORE_ADDR pc) |
1008 | { | |
1009 | unsigned long inst; | |
1010 | int op; | |
1011 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1012 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1013 | { |
e135b889 DJ |
1014 | if (itype_op (inst) >> 2 == 5) |
1015 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 1016 | { |
e135b889 | 1017 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1018 | switch (op) |
1019 | { | |
e135b889 DJ |
1020 | case 0: /* BEQL */ |
1021 | goto equal_branch; | |
1022 | case 1: /* BNEL */ | |
1023 | goto neq_branch; | |
1024 | case 2: /* BLEZL */ | |
1025 | goto less_branch; | |
1026 | case 3: /* BGTZ */ | |
1027 | goto greater_branch; | |
c5aa993b JM |
1028 | default: |
1029 | pc += 4; | |
c906108c SS |
1030 | } |
1031 | } | |
e135b889 DJ |
1032 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1033 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
1034 | { | |
1035 | int tf = itype_rt (inst) & 0x01; | |
1036 | int cnum = itype_rt (inst) >> 2; | |
56cea623 | 1037 | int fcrcs = read_signed_register (mips_regnum (current_gdbarch)->fp_control_status); |
e135b889 DJ |
1038 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1039 | ||
1040 | if (((cond >> cnum) & 0x01) == tf) | |
1041 | pc += mips32_relative_offset (inst) + 4; | |
1042 | else | |
1043 | pc += 8; | |
1044 | } | |
c5aa993b JM |
1045 | else |
1046 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1047 | } |
1048 | else | |
c5aa993b JM |
1049 | { /* This gets way messy */ |
1050 | ||
c906108c | 1051 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1052 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1053 | { |
c5aa993b JM |
1054 | case 0: /* SPECIAL */ |
1055 | op = rtype_funct (inst); | |
1056 | switch (op) | |
1057 | { | |
1058 | case 8: /* JR */ | |
1059 | case 9: /* JALR */ | |
6c997a34 AC |
1060 | /* Set PC to that address */ |
1061 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1062 | break; |
1063 | default: | |
1064 | pc += 4; | |
1065 | } | |
1066 | ||
e135b889 | 1067 | break; /* end SPECIAL */ |
c5aa993b | 1068 | case 1: /* REGIMM */ |
c906108c | 1069 | { |
e135b889 DJ |
1070 | op = itype_rt (inst); /* branch condition */ |
1071 | switch (op) | |
c906108c | 1072 | { |
c5aa993b | 1073 | case 0: /* BLTZ */ |
e135b889 DJ |
1074 | case 2: /* BLTZL */ |
1075 | case 16: /* BLTZAL */ | |
c5aa993b | 1076 | case 18: /* BLTZALL */ |
c906108c | 1077 | less_branch: |
6c997a34 | 1078 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1079 | pc += mips32_relative_offset (inst) + 4; |
1080 | else | |
1081 | pc += 8; /* after the delay slot */ | |
1082 | break; | |
e135b889 | 1083 | case 1: /* BGEZ */ |
c5aa993b JM |
1084 | case 3: /* BGEZL */ |
1085 | case 17: /* BGEZAL */ | |
1086 | case 19: /* BGEZALL */ | |
6c997a34 | 1087 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1088 | pc += mips32_relative_offset (inst) + 4; |
1089 | else | |
1090 | pc += 8; /* after the delay slot */ | |
1091 | break; | |
e135b889 | 1092 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1093 | default: |
1094 | pc += 4; | |
c906108c SS |
1095 | } |
1096 | } | |
e135b889 | 1097 | break; /* end REGIMM */ |
c5aa993b JM |
1098 | case 2: /* J */ |
1099 | case 3: /* JAL */ | |
1100 | { | |
1101 | unsigned long reg; | |
1102 | reg = jtype_target (inst) << 2; | |
e135b889 | 1103 | /* Upper four bits get never changed... */ |
c5aa993b | 1104 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1105 | } |
c5aa993b JM |
1106 | break; |
1107 | /* FIXME case JALX : */ | |
1108 | { | |
1109 | unsigned long reg; | |
1110 | reg = jtype_target (inst) << 2; | |
1111 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1112 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1113 | } | |
c5aa993b | 1114 | break; /* The new PC will be alternate mode */ |
e135b889 | 1115 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1116 | equal_branch: |
6c997a34 AC |
1117 | if (read_signed_register (itype_rs (inst)) == |
1118 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1119 | pc += mips32_relative_offset (inst) + 4; |
1120 | else | |
1121 | pc += 8; | |
1122 | break; | |
e135b889 | 1123 | case 5: /* BNE, BNEL */ |
c5aa993b | 1124 | neq_branch: |
6c997a34 | 1125 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1126 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1127 | pc += mips32_relative_offset (inst) + 4; |
1128 | else | |
1129 | pc += 8; | |
1130 | break; | |
e135b889 | 1131 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1132 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1133 | pc += mips32_relative_offset (inst) + 4; |
1134 | else | |
1135 | pc += 8; | |
1136 | break; | |
1137 | case 7: | |
e135b889 DJ |
1138 | default: |
1139 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1140 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1141 | pc += mips32_relative_offset (inst) + 4; |
1142 | else | |
1143 | pc += 8; | |
1144 | break; | |
c5aa993b JM |
1145 | } /* switch */ |
1146 | } /* else */ | |
1147 | return pc; | |
1148 | } /* mips32_next_pc */ | |
c906108c SS |
1149 | |
1150 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1151 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1152 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1153 | We dont want to set a single step instruction on the extend instruction | |
1154 | either. | |
c5aa993b | 1155 | */ |
c906108c SS |
1156 | |
1157 | /* Lots of mips16 instruction formats */ | |
1158 | /* Predicting jumps requires itype,ritype,i8type | |
1159 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1160 | */ |
c906108c SS |
1161 | enum mips16_inst_fmts |
1162 | { | |
c5aa993b JM |
1163 | itype, /* 0 immediate 5,10 */ |
1164 | ritype, /* 1 5,3,8 */ | |
1165 | rrtype, /* 2 5,3,3,5 */ | |
1166 | rritype, /* 3 5,3,3,5 */ | |
1167 | rrrtype, /* 4 5,3,3,3,2 */ | |
1168 | rriatype, /* 5 5,3,3,1,4 */ | |
1169 | shifttype, /* 6 5,3,3,3,2 */ | |
1170 | i8type, /* 7 5,3,8 */ | |
1171 | i8movtype, /* 8 5,3,3,5 */ | |
1172 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1173 | i64type, /* 10 5,3,8 */ | |
1174 | ri64type, /* 11 5,3,3,5 */ | |
1175 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1176 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1177 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1178 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1179 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1180 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1181 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1182 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1183 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1184 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1185 | }; | |
12f02c2a AC |
1186 | /* I am heaping all the fields of the formats into one structure and |
1187 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1188 | struct upk_mips16 |
c5aa993b | 1189 | { |
12f02c2a | 1190 | CORE_ADDR offset; |
c5aa993b JM |
1191 | unsigned int regx; /* Function in i8 type */ |
1192 | unsigned int regy; | |
1193 | }; | |
c906108c SS |
1194 | |
1195 | ||
12f02c2a AC |
1196 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1197 | for the bits which make up the immediatate extension. */ | |
c906108c | 1198 | |
12f02c2a AC |
1199 | static CORE_ADDR |
1200 | extended_offset (unsigned int extension) | |
c906108c | 1201 | { |
12f02c2a | 1202 | CORE_ADDR value; |
c5aa993b JM |
1203 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1204 | value = value << 6; | |
1205 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1206 | value = value << 5; | |
1207 | value |= extension & 0x01f; /* extract 4:0 */ | |
1208 | return value; | |
c906108c SS |
1209 | } |
1210 | ||
1211 | /* Only call this function if you know that this is an extendable | |
1212 | instruction, It wont malfunction, but why make excess remote memory references? | |
1213 | If the immediate operands get sign extended or somthing, do it after | |
1214 | the extension is performed. | |
c5aa993b | 1215 | */ |
c906108c SS |
1216 | /* FIXME: Every one of these cases needs to worry about sign extension |
1217 | when the offset is to be used in relative addressing */ | |
1218 | ||
1219 | ||
12f02c2a | 1220 | static unsigned int |
c5aa993b | 1221 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1222 | { |
c5aa993b JM |
1223 | char buf[8]; |
1224 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1225 | target_read_memory (pc, buf, 2); | |
1226 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1227 | } |
1228 | ||
1229 | static void | |
c5aa993b | 1230 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1231 | unsigned int extension, |
1232 | unsigned int inst, | |
1233 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1234 | struct upk_mips16 *upk) |
c906108c | 1235 | { |
12f02c2a AC |
1236 | CORE_ADDR offset; |
1237 | int regx; | |
1238 | int regy; | |
1239 | switch (insn_format) | |
c906108c | 1240 | { |
c5aa993b | 1241 | case itype: |
c906108c | 1242 | { |
12f02c2a AC |
1243 | CORE_ADDR value; |
1244 | if (extension) | |
c5aa993b JM |
1245 | { |
1246 | value = extended_offset (extension); | |
1247 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1248 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1249 | } |
1250 | else | |
c5aa993b | 1251 | { |
12f02c2a | 1252 | value = inst & 0x7ff; |
c5aa993b | 1253 | /* FIXME : Consider sign extension */ |
c906108c | 1254 | } |
12f02c2a AC |
1255 | offset = value; |
1256 | regx = -1; | |
1257 | regy = -1; | |
c906108c | 1258 | } |
c5aa993b JM |
1259 | break; |
1260 | case ritype: | |
1261 | case i8type: | |
1262 | { /* A register identifier and an offset */ | |
c906108c SS |
1263 | /* Most of the fields are the same as I type but the |
1264 | immediate value is of a different length */ | |
12f02c2a AC |
1265 | CORE_ADDR value; |
1266 | if (extension) | |
c906108c | 1267 | { |
c5aa993b JM |
1268 | value = extended_offset (extension); |
1269 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1270 | value |= inst & 0xff; /* eleven bits from instruction */ |
1271 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1272 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1273 | { | |
1274 | value &= ~0x3fff; /* remove the sign bit */ | |
1275 | value = -value; | |
c906108c SS |
1276 | } |
1277 | } | |
c5aa993b JM |
1278 | else |
1279 | { | |
12f02c2a AC |
1280 | value = inst & 0xff; /* 8 bits */ |
1281 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1282 | /* FIXME: Do sign extension , this format needs it */ |
1283 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1284 | { | |
1285 | value &= 0xef; /* remove the sign bit */ | |
1286 | value = -value; | |
1287 | } | |
c5aa993b | 1288 | } |
12f02c2a AC |
1289 | offset = value; |
1290 | regy = -1; | |
c5aa993b | 1291 | break; |
c906108c | 1292 | } |
c5aa993b | 1293 | case jalxtype: |
c906108c | 1294 | { |
c5aa993b | 1295 | unsigned long value; |
12f02c2a AC |
1296 | unsigned int nexthalf; |
1297 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1298 | value = value << 16; |
1299 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1300 | value |= nexthalf; | |
12f02c2a AC |
1301 | offset = value; |
1302 | regx = -1; | |
1303 | regy = -1; | |
c5aa993b | 1304 | break; |
c906108c SS |
1305 | } |
1306 | default: | |
8e65ff28 AC |
1307 | internal_error (__FILE__, __LINE__, |
1308 | "bad switch"); | |
c906108c | 1309 | } |
12f02c2a AC |
1310 | upk->offset = offset; |
1311 | upk->regx = regx; | |
1312 | upk->regy = regy; | |
c906108c SS |
1313 | } |
1314 | ||
1315 | ||
c5aa993b JM |
1316 | static CORE_ADDR |
1317 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1318 | { |
c5aa993b | 1319 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1320 | } |
1321 | ||
12f02c2a AC |
1322 | static CORE_ADDR |
1323 | extended_mips16_next_pc (CORE_ADDR pc, | |
1324 | unsigned int extension, | |
1325 | unsigned int insn) | |
c906108c | 1326 | { |
12f02c2a AC |
1327 | int op = (insn >> 11); |
1328 | switch (op) | |
c906108c | 1329 | { |
12f02c2a AC |
1330 | case 2: /* Branch */ |
1331 | { | |
1332 | CORE_ADDR offset; | |
1333 | struct upk_mips16 upk; | |
1334 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1335 | offset = upk.offset; | |
1336 | if (offset & 0x800) | |
1337 | { | |
1338 | offset &= 0xeff; | |
1339 | offset = -offset; | |
1340 | } | |
1341 | pc += (offset << 1) + 2; | |
1342 | break; | |
1343 | } | |
1344 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1345 | { | |
1346 | struct upk_mips16 upk; | |
1347 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1348 | pc = add_offset_16 (pc, upk.offset); | |
1349 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1350 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1351 | else | |
1352 | pc |= 0x01; | |
1353 | break; | |
1354 | } | |
1355 | case 4: /* beqz */ | |
1356 | { | |
1357 | struct upk_mips16 upk; | |
1358 | int reg; | |
1359 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1360 | reg = read_signed_register (upk.regx); | |
1361 | if (reg == 0) | |
1362 | pc += (upk.offset << 1) + 2; | |
1363 | else | |
1364 | pc += 2; | |
1365 | break; | |
1366 | } | |
1367 | case 5: /* bnez */ | |
1368 | { | |
1369 | struct upk_mips16 upk; | |
1370 | int reg; | |
1371 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1372 | reg = read_signed_register (upk.regx); | |
1373 | if (reg != 0) | |
1374 | pc += (upk.offset << 1) + 2; | |
1375 | else | |
1376 | pc += 2; | |
1377 | break; | |
1378 | } | |
1379 | case 12: /* I8 Formats btez btnez */ | |
1380 | { | |
1381 | struct upk_mips16 upk; | |
1382 | int reg; | |
1383 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1384 | /* upk.regx contains the opcode */ | |
1385 | reg = read_signed_register (24); /* Test register is 24 */ | |
1386 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1387 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1388 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1389 | pc += (upk.offset << 1) + 2; | |
1390 | else | |
1391 | pc += 2; | |
1392 | break; | |
1393 | } | |
1394 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1395 | { | |
1396 | struct upk_mips16 upk; | |
1397 | /* upk.fmt = rrtype; */ | |
1398 | op = insn & 0x1f; | |
1399 | if (op == 0) | |
c5aa993b | 1400 | { |
12f02c2a AC |
1401 | int reg; |
1402 | upk.regx = (insn >> 8) & 0x07; | |
1403 | upk.regy = (insn >> 5) & 0x07; | |
1404 | switch (upk.regy) | |
c5aa993b | 1405 | { |
12f02c2a AC |
1406 | case 0: |
1407 | reg = upk.regx; | |
1408 | break; | |
1409 | case 1: | |
1410 | reg = 31; | |
1411 | break; /* Function return instruction */ | |
1412 | case 2: | |
1413 | reg = upk.regx; | |
1414 | break; | |
1415 | default: | |
1416 | reg = 31; | |
1417 | break; /* BOGUS Guess */ | |
c906108c | 1418 | } |
12f02c2a | 1419 | pc = read_signed_register (reg); |
c906108c | 1420 | } |
12f02c2a | 1421 | else |
c5aa993b | 1422 | pc += 2; |
12f02c2a AC |
1423 | break; |
1424 | } | |
1425 | case 30: | |
1426 | /* This is an instruction extension. Fetch the real instruction | |
1427 | (which follows the extension) and decode things based on | |
1428 | that. */ | |
1429 | { | |
1430 | pc += 2; | |
1431 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1432 | break; | |
1433 | } | |
1434 | default: | |
1435 | { | |
1436 | pc += 2; | |
1437 | break; | |
1438 | } | |
c906108c | 1439 | } |
c5aa993b | 1440 | return pc; |
12f02c2a | 1441 | } |
c906108c | 1442 | |
5a89d8aa | 1443 | static CORE_ADDR |
12f02c2a AC |
1444 | mips16_next_pc (CORE_ADDR pc) |
1445 | { | |
1446 | unsigned int insn = fetch_mips_16 (pc); | |
1447 | return extended_mips16_next_pc (pc, 0, insn); | |
1448 | } | |
1449 | ||
1450 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1451 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1452 | It works by decoding the current instruction and predicting where a |
1453 | branch will go. This isnt hard because all the data is available. | |
1454 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1455 | CORE_ADDR |
1456 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1457 | { |
c5aa993b JM |
1458 | if (pc & 0x01) |
1459 | return mips16_next_pc (pc); | |
1460 | else | |
1461 | return mips32_next_pc (pc); | |
12f02c2a | 1462 | } |
c906108c | 1463 | |
e0f7ec59 AC |
1464 | /* Set up the 'saved_regs' array. This is a data structure containing |
1465 | the addresses on the stack where each register has been saved, for | |
1466 | each stack frame. Registers that have not been saved will have | |
1467 | zero here. The stack pointer register is special: rather than the | |
1468 | address where the stack register has been saved, | |
1469 | saved_regs[SP_REGNUM] will have the actual value of the previous | |
1470 | frame's stack register. */ | |
c906108c | 1471 | |
d28e01f4 | 1472 | static void |
acdb74a0 | 1473 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1474 | { |
1475 | int ireg; | |
c906108c SS |
1476 | /* r0 bit means kernel trap */ |
1477 | int kernel_trap; | |
1478 | /* What registers have been saved? Bitmasks. */ | |
1479 | unsigned long gen_mask, float_mask; | |
1480 | mips_extra_func_info_t proc_desc; | |
1481 | t_inst inst; | |
e0f7ec59 | 1482 | CORE_ADDR *saved_regs; |
c906108c | 1483 | |
1b1d3794 | 1484 | if (deprecated_get_frame_saved_regs (fci) != NULL) |
e0f7ec59 AC |
1485 | return; |
1486 | saved_regs = frame_saved_regs_zalloc (fci); | |
c906108c SS |
1487 | |
1488 | /* If it is the frame for sigtramp, the saved registers are located | |
e0f7ec59 AC |
1489 | in a sigcontext structure somewhere on the stack. If the stack |
1490 | layout for sigtramp changes we might have to change these | |
1491 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
c906108c | 1492 | #ifndef SIGFRAME_BASE |
e0f7ec59 AC |
1493 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
1494 | above the sigtramp frame. */ | |
4246e332 | 1495 | #define SIGFRAME_BASE mips_regsize (current_gdbarch) |
c906108c | 1496 | /* FIXME! Are these correct?? */ |
4246e332 AC |
1497 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch)) |
1498 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch)) | |
c906108c | 1499 | #define SIGFRAME_FPREGSAVE_OFF \ |
4246e332 | 1500 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch)) |
c906108c | 1501 | #endif |
5a203e44 | 1502 | if ((get_frame_type (fci) == SIGTRAMP_FRAME)) |
c906108c SS |
1503 | { |
1504 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1505 | { | |
e0f7ec59 | 1506 | CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF |
10a08821 | 1507 | + ireg * mips_regsize (current_gdbarch)); |
e0f7ec59 | 1508 | set_reg_offset (saved_regs, ireg, reg_position); |
c906108c SS |
1509 | } |
1510 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1511 | { | |
e0f7ec59 AC |
1512 | CORE_ADDR reg_position = (get_frame_base (fci) |
1513 | + SIGFRAME_FPREGSAVE_OFF | |
10a08821 | 1514 | + ireg * mips_regsize (current_gdbarch)); |
56cea623 | 1515 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
c906108c | 1516 | } |
e0f7ec59 AC |
1517 | |
1518 | set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF); | |
1519 | /* SP_REGNUM, contains the value and not the address. */ | |
1520 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
c906108c SS |
1521 | return; |
1522 | } | |
1523 | ||
da50a4b7 | 1524 | proc_desc = get_frame_extra_info (fci)->proc_desc; |
c906108c | 1525 | if (proc_desc == NULL) |
e0f7ec59 AC |
1526 | /* I'm not sure how/whether this can happen. Normally when we |
1527 | can't find a proc_desc, we "synthesize" one using | |
1528 | heuristic_proc_desc and set the saved_regs right away. */ | |
c906108c SS |
1529 | return; |
1530 | ||
c5aa993b JM |
1531 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1532 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1533 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1534 | |
e0f7ec59 AC |
1535 | if (/* In any frame other than the innermost or a frame interrupted |
1536 | by a signal, we assume that all registers have been saved. | |
1537 | This assumes that all register saves in a function happen | |
1538 | before the first function call. */ | |
11c02a10 AC |
1539 | (get_next_frame (fci) == NULL |
1540 | || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME)) | |
c906108c | 1541 | |
e0f7ec59 | 1542 | /* In a dummy frame we know exactly where things are saved. */ |
c5aa993b | 1543 | && !PROC_DESC_IS_DUMMY (proc_desc) |
c906108c | 1544 | |
e0f7ec59 AC |
1545 | /* Don't bother unless we are inside a function prologue. |
1546 | Outside the prologue, we know where everything is. */ | |
c906108c | 1547 | |
50abf9e5 | 1548 | && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc)) |
c906108c | 1549 | |
e0f7ec59 AC |
1550 | /* Not sure exactly what kernel_trap means, but if it means the |
1551 | kernel saves the registers without a prologue doing it, we | |
1552 | better not examine the prologue to see whether registers | |
1553 | have been saved yet. */ | |
c5aa993b | 1554 | && !kernel_trap) |
c906108c | 1555 | { |
e0f7ec59 AC |
1556 | /* We need to figure out whether the registers that the |
1557 | proc_desc claims are saved have been saved yet. */ | |
c906108c SS |
1558 | |
1559 | CORE_ADDR addr; | |
1560 | ||
1561 | /* Bitmasks; set if we have found a save for the register. */ | |
1562 | unsigned long gen_save_found = 0; | |
1563 | unsigned long float_save_found = 0; | |
1564 | int instlen; | |
1565 | ||
1566 | /* If the address is odd, assume this is MIPS16 code. */ | |
1567 | addr = PROC_LOW_ADDR (proc_desc); | |
1568 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1569 | ||
e0f7ec59 AC |
1570 | /* Scan through this function's instructions preceding the |
1571 | current PC, and look for those that save registers. */ | |
50abf9e5 | 1572 | while (addr < get_frame_pc (fci)) |
c906108c SS |
1573 | { |
1574 | inst = mips_fetch_instruction (addr); | |
1575 | if (pc_is_mips16 (addr)) | |
1576 | mips16_decode_reg_save (inst, &gen_save_found); | |
1577 | else | |
1578 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1579 | addr += instlen; | |
1580 | } | |
1581 | gen_mask = gen_save_found; | |
1582 | float_mask = float_save_found; | |
1583 | } | |
1584 | ||
e0f7ec59 AC |
1585 | /* Fill in the offsets for the registers which gen_mask says were |
1586 | saved. */ | |
1587 | { | |
1588 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1589 | + PROC_REG_OFFSET (proc_desc)); | |
1590 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1591 | if (gen_mask & 0x80000000) | |
1592 | { | |
1593 | set_reg_offset (saved_regs, ireg, reg_position); | |
1594 | reg_position -= MIPS_SAVED_REGSIZE; | |
1595 | } | |
1596 | } | |
c906108c | 1597 | |
e0f7ec59 AC |
1598 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse |
1599 | order of that normally used by gcc. Therefore, we have to fetch | |
1600 | the first instruction of the function, and if it's an entry | |
1601 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
c906108c SS |
1602 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
1603 | { | |
1604 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
e0f7ec59 AC |
1605 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) |
1606 | /* entry */ | |
c906108c SS |
1607 | { |
1608 | int reg; | |
1609 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1610 | |
c906108c | 1611 | /* Check if the ra register was pushed on the stack. */ |
e0f7ec59 AC |
1612 | CORE_ADDR reg_position = (get_frame_base (fci) |
1613 | + PROC_REG_OFFSET (proc_desc)); | |
c906108c | 1614 | if (inst & 0x20) |
7a292a7a | 1615 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c | 1616 | |
e0f7ec59 AC |
1617 | /* Check if the s0 and s1 registers were pushed on the |
1618 | stack. */ | |
c5aa993b | 1619 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c | 1620 | { |
e0f7ec59 | 1621 | set_reg_offset (saved_regs, reg, reg_position); |
7a292a7a | 1622 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1623 | } |
1624 | } | |
1625 | } | |
1626 | ||
e0f7ec59 AC |
1627 | /* Fill in the offsets for the registers which float_mask says were |
1628 | saved. */ | |
1629 | { | |
1630 | CORE_ADDR reg_position = (get_frame_base (fci) | |
1631 | + PROC_FREG_OFFSET (proc_desc)); | |
6acdf5c7 | 1632 | |
e0f7ec59 AC |
1633 | /* Fill in the offsets for the float registers which float_mask |
1634 | says were saved. */ | |
1635 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1636 | if (float_mask & 0x80000000) | |
1637 | { | |
c57bb9fa AC |
1638 | if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1639 | { | |
1640 | /* On a big endian 32 bit ABI, floating point registers | |
1641 | are paired to form doubles such that the most | |
1642 | significant part is in $f[N+1] and the least | |
1643 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1644 | registers are also spilled as a pair and stored as a | |
1645 | double. | |
1646 | ||
1647 | When little-endian the least significant part is | |
1648 | stored first leading to the memory order $f[N] and | |
1649 | then $f[N+1]. | |
1650 | ||
ce2826aa | 1651 | Unfortunately, when big-endian the most significant |
c57bb9fa AC |
1652 | part of the double is stored first, and the least |
1653 | significant is stored second. This leads to the | |
1654 | registers being ordered in memory as firt $f[N+1] and | |
1655 | then $f[N]. | |
1656 | ||
1657 | For the big-endian case make certain that the | |
1658 | addresses point at the correct (swapped) locations | |
1659 | $f[N] and $f[N+1] pair (keep in mind that | |
1660 | reg_position is decremented each time through the | |
1661 | loop). */ | |
1662 | if ((ireg & 1)) | |
56cea623 | 1663 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1664 | reg_position - MIPS_SAVED_REGSIZE); |
1665 | else | |
56cea623 | 1666 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, |
c57bb9fa AC |
1667 | reg_position + MIPS_SAVED_REGSIZE); |
1668 | } | |
1669 | else | |
56cea623 | 1670 | set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position); |
e0f7ec59 AC |
1671 | reg_position -= MIPS_SAVED_REGSIZE; |
1672 | } | |
c906108c | 1673 | |
e0f7ec59 AC |
1674 | set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]); |
1675 | } | |
d28e01f4 | 1676 | |
e0f7ec59 AC |
1677 | /* SP_REGNUM, contains the value and not the address. */ |
1678 | set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci)); | |
d28e01f4 KB |
1679 | } |
1680 | ||
c906108c | 1681 | static CORE_ADDR |
acdb74a0 | 1682 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 1683 | { |
a4b8ebc8 AC |
1684 | /* Always a pseudo. */ |
1685 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 1686 | if (fi == NULL) |
c906108c | 1687 | { |
a4b8ebc8 AC |
1688 | LONGEST val; |
1689 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
1690 | return val; | |
f796e4be | 1691 | } |
a4b8ebc8 AC |
1692 | else if ((regno % NUM_REGS) == SP_REGNUM) |
1693 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
1694 | In fact, it is so special that it can even only be fetched | |
1695 | using a raw register number! Once this code as been converted | |
1696 | to frame-unwind the problem goes away. */ | |
1697 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 1698 | else |
a4b8ebc8 | 1699 | return frame_unwind_register_signed (fi, regno); |
64159455 | 1700 | |
c906108c SS |
1701 | } |
1702 | ||
1703 | /* mips_addr_bits_remove - remove useless address bits */ | |
1704 | ||
875e1767 | 1705 | static CORE_ADDR |
acdb74a0 | 1706 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1707 | { |
8fa9cfa1 AC |
1708 | if (mips_mask_address_p () |
1709 | && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
1710 | /* This hack is a work-around for existing boards using PMON, the | |
1711 | simulator, and any other 64-bit targets that doesn't have true | |
1712 | 64-bit addressing. On these targets, the upper 32 bits of | |
1713 | addresses are ignored by the hardware. Thus, the PC or SP are | |
1714 | likely to have been sign extended to all 1s by instruction | |
1715 | sequences that load 32-bit addresses. For example, a typical | |
1716 | piece of code that loads an address is this: | |
1717 | ||
1718 | lui $r2, <upper 16 bits> | |
1719 | ori $r2, <lower 16 bits> | |
1720 | ||
1721 | But the lui sign-extends the value such that the upper 32 bits | |
1722 | may be all 1s. The workaround is simply to mask off these | |
1723 | bits. In the future, gcc may be changed to support true 64-bit | |
1724 | addressing, and this masking will have to be disabled. */ | |
1725 | return addr &= 0xffffffffUL; | |
1726 | else | |
1727 | return addr; | |
c906108c SS |
1728 | } |
1729 | ||
9022177c DJ |
1730 | /* mips_software_single_step() is called just before we want to resume |
1731 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1732 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1733 | the target of the coming instruction and breakpoint it. |
1734 | ||
1735 | single_step is also called just after the inferior stops. If we had | |
1736 | set up a simulated single-step, we undo our damage. */ | |
1737 | ||
1738 | void | |
1739 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1740 | { | |
1741 | static CORE_ADDR next_pc; | |
1742 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1743 | static binsn_quantum break_mem; | |
1744 | CORE_ADDR pc; | |
1745 | ||
1746 | if (insert_breakpoints_p) | |
1747 | { | |
1748 | pc = read_register (PC_REGNUM); | |
1749 | next_pc = mips_next_pc (pc); | |
1750 | ||
1751 | target_insert_breakpoint (next_pc, break_mem); | |
1752 | } | |
1753 | else | |
1754 | target_remove_breakpoint (next_pc, break_mem); | |
1755 | } | |
1756 | ||
97f46953 | 1757 | static CORE_ADDR |
acdb74a0 | 1758 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1759 | { |
1760 | CORE_ADDR pc, tmp; | |
1761 | ||
11c02a10 | 1762 | pc = ((fromleaf) |
6913c89a | 1763 | ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) |
11c02a10 | 1764 | : get_next_frame (prev) |
8bedc050 | 1765 | ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) |
11c02a10 | 1766 | : read_pc ()); |
5a89d8aa | 1767 | tmp = SKIP_TRAMPOLINE_CODE (pc); |
97f46953 | 1768 | return tmp ? tmp : pc; |
c906108c SS |
1769 | } |
1770 | ||
1771 | ||
f7ab6ec6 | 1772 | static CORE_ADDR |
acdb74a0 | 1773 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1774 | { |
1775 | CORE_ADDR saved_pc; | |
c906108c | 1776 | |
50abf9e5 | 1777 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 | 1778 | { |
a4b8ebc8 | 1779 | /* Always unwind the cooked PC register value. */ |
dd3ecc14 | 1780 | saved_pc = frame_unwind_register_signed (frame, NUM_REGS + PC_REGNUM); |
cedea778 | 1781 | } |
c906108c | 1782 | else |
a4b8ebc8 AC |
1783 | { |
1784 | mips_extra_func_info_t proc_desc | |
1785 | = get_frame_extra_info (frame)->proc_desc; | |
1786 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) | |
1787 | saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); | |
1788 | else | |
1789 | { | |
1790 | /* We have to get the saved pc from the sigcontext if it is | |
1791 | a signal handler frame. */ | |
1792 | int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM | |
1793 | : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); | |
1794 | saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg); | |
1795 | } | |
1796 | } | |
c906108c SS |
1797 | return ADDR_BITS_REMOVE (saved_pc); |
1798 | } | |
1799 | ||
1800 | static struct mips_extra_func_info temp_proc_desc; | |
fe29b929 KB |
1801 | |
1802 | /* This hack will go away once the get_prev_frame() code has been | |
1803 | modified to set the frame's type first. That is BEFORE init extra | |
1804 | frame info et.al. is called. This is because it will become | |
1805 | possible to skip the init extra info call for sigtramp and dummy | |
1806 | frames. */ | |
1807 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 1808 | |
e0f7ec59 AC |
1809 | /* Set a register's saved stack address in temp_saved_regs. If an |
1810 | address has already been set for this register, do nothing; this | |
1811 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
1812 | function prologue. |
1813 | ||
1814 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
1815 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1816 | is used as it is only second range (the ABI instead of ISA | |
1817 | registers) that comes into play when finding saved registers in a | |
1818 | frame. */ | |
c906108c SS |
1819 | |
1820 | static void | |
e0f7ec59 | 1821 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 1822 | { |
e0f7ec59 | 1823 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
1824 | { |
1825 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
1826 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
1827 | } | |
c906108c SS |
1828 | } |
1829 | ||
1830 | ||
1831 | /* Test whether the PC points to the return instruction at the | |
1832 | end of a function. */ | |
1833 | ||
c5aa993b | 1834 | static int |
acdb74a0 | 1835 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1836 | { |
1837 | if (pc_is_mips16 (pc)) | |
1838 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1839 | generates a "jr $ra"; other times it generates code to load | |
1840 | the return address from the stack to an accessible register (such | |
1841 | as $a3), then a "jr" using that register. This second case | |
1842 | is almost impossible to distinguish from an indirect jump | |
1843 | used for switch statements, so we don't even try. */ | |
1844 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1845 | else | |
1846 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1847 | } | |
1848 | ||
1849 | ||
1850 | /* This fencepost looks highly suspicious to me. Removing it also | |
1851 | seems suspicious as it could affect remote debugging across serial | |
1852 | lines. */ | |
1853 | ||
1854 | static CORE_ADDR | |
acdb74a0 | 1855 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1856 | { |
c5aa993b JM |
1857 | CORE_ADDR start_pc; |
1858 | CORE_ADDR fence; | |
1859 | int instlen; | |
1860 | int seen_adjsp = 0; | |
c906108c | 1861 | |
c5aa993b JM |
1862 | pc = ADDR_BITS_REMOVE (pc); |
1863 | start_pc = pc; | |
1864 | fence = start_pc - heuristic_fence_post; | |
1865 | if (start_pc == 0) | |
1866 | return 0; | |
c906108c | 1867 | |
c5aa993b JM |
1868 | if (heuristic_fence_post == UINT_MAX |
1869 | || fence < VM_MIN_ADDRESS) | |
1870 | fence = VM_MIN_ADDRESS; | |
c906108c | 1871 | |
c5aa993b | 1872 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1873 | |
c5aa993b JM |
1874 | /* search back for previous return */ |
1875 | for (start_pc -= instlen;; start_pc -= instlen) | |
1876 | if (start_pc < fence) | |
1877 | { | |
1878 | /* It's not clear to me why we reach this point when | |
c0236d92 | 1879 | stop_soon, but with this test, at least we |
c5aa993b JM |
1880 | don't print out warnings for every child forked (eg, on |
1881 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 1882 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 1883 | { |
c5aa993b JM |
1884 | static int blurb_printed = 0; |
1885 | ||
1886 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1887 | paddr_nz (pc)); | |
1888 | ||
1889 | if (!blurb_printed) | |
c906108c | 1890 | { |
c5aa993b JM |
1891 | /* This actually happens frequently in embedded |
1892 | development, when you first connect to a board | |
1893 | and your stack pointer and pc are nowhere in | |
1894 | particular. This message needs to give people | |
1895 | in that situation enough information to | |
1896 | determine that it's no big deal. */ | |
1897 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1898 | GDB is unable to find the start of the function at 0x%s\n\ |
1899 | and thus can't determine the size of that function's stack frame.\n\ | |
1900 | This means that GDB may be unable to access that stack frame, or\n\ | |
1901 | the frames below it.\n\ | |
1902 | This problem is most likely caused by an invalid program counter or\n\ | |
1903 | stack pointer.\n\ | |
1904 | However, if you think GDB should simply search farther back\n\ | |
1905 | from 0x%s for code which looks like the beginning of a\n\ | |
1906 | function, you can increase the range of the search using the `set\n\ | |
1907 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1908 | paddr_nz (pc), paddr_nz (pc)); |
1909 | blurb_printed = 1; | |
c906108c | 1910 | } |
c906108c SS |
1911 | } |
1912 | ||
c5aa993b JM |
1913 | return 0; |
1914 | } | |
1915 | else if (pc_is_mips16 (start_pc)) | |
1916 | { | |
1917 | unsigned short inst; | |
1918 | ||
1919 | /* On MIPS16, any one of the following is likely to be the | |
1920 | start of a function: | |
1921 | entry | |
1922 | addiu sp,-n | |
1923 | daddiu sp,-n | |
1924 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1925 | inst = mips_fetch_instruction (start_pc); | |
1926 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1927 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1928 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1929 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1930 | break; | |
1931 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1932 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1933 | seen_adjsp = 1; | |
1934 | else | |
1935 | seen_adjsp = 0; | |
1936 | } | |
1937 | else if (mips_about_to_return (start_pc)) | |
1938 | { | |
1939 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1940 | break; | |
1941 | } | |
1942 | ||
c5aa993b | 1943 | return start_pc; |
c906108c SS |
1944 | } |
1945 | ||
1946 | /* Fetch the immediate value from a MIPS16 instruction. | |
1947 | If the previous instruction was an EXTEND, use it to extend | |
1948 | the upper bits of the immediate value. This is a helper function | |
1949 | for mips16_heuristic_proc_desc. */ | |
1950 | ||
1951 | static int | |
acdb74a0 AC |
1952 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1953 | unsigned short inst, /* current instruction */ | |
1954 | int nbits, /* number of bits in imm field */ | |
1955 | int scale, /* scale factor to be applied to imm */ | |
1956 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1957 | { |
1958 | int offset; | |
1959 | ||
1960 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1961 | { | |
1962 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1963 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1964 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1965 | return offset | (inst & 0x1f); | |
1966 | } | |
1967 | else | |
1968 | { | |
1969 | int max_imm = 1 << nbits; | |
1970 | int mask = max_imm - 1; | |
1971 | int sign_bit = max_imm >> 1; | |
1972 | ||
1973 | offset = inst & mask; | |
1974 | if (is_signed && (offset & sign_bit)) | |
1975 | offset = 0 - (max_imm - offset); | |
1976 | return offset * scale; | |
1977 | } | |
1978 | } | |
1979 | ||
1980 | ||
1981 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1982 | stream from start_pc to limit_pc. */ | |
1983 | ||
1984 | static void | |
acdb74a0 AC |
1985 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1986 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1987 | { |
1988 | CORE_ADDR cur_pc; | |
1989 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1990 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1991 | unsigned inst = 0; /* current instruction */ | |
1992 | unsigned entry_inst = 0; /* the entry instruction */ | |
1993 | int reg, offset; | |
1994 | ||
c5aa993b JM |
1995 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1996 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1997 | |
1998 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1999 | { | |
2000 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2001 | the immediate offset extension from it in mips16_get_imm. */ | |
2002 | prev_inst = inst; | |
2003 | ||
2004 | /* Fetch and decode the instruction. */ | |
2005 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2006 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
2007 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
2008 | { | |
2009 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2010 | if (offset < 0) /* negative stack adjustment? */ |
2011 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2012 | else |
2013 | /* Exit loop if a positive stack adjustment is found, which | |
2014 | usually means that the stack cleanup code in the function | |
2015 | epilogue is reached. */ | |
2016 | break; | |
2017 | } | |
2018 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2019 | { | |
2020 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2021 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2022 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2023 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2024 | } |
2025 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2026 | { | |
2027 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2028 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2029 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2030 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2031 | } |
2032 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2033 | { | |
2034 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2035 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2036 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2037 | } |
2038 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2039 | { | |
2040 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2041 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2042 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2043 | } |
c5aa993b | 2044 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2045 | { |
2046 | frame_addr = sp; | |
2047 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2048 | } | |
2049 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2050 | { | |
2051 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2052 | frame_addr = sp + offset; | |
2053 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2054 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2055 | } | |
2056 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2057 | { | |
2058 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2059 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2060 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2061 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2062 | } |
2063 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2064 | { | |
2065 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2066 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2067 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2068 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2069 | } |
c5aa993b JM |
2070 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2071 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2072 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2073 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2074 | } |
2075 | ||
c5aa993b JM |
2076 | /* The entry instruction is typically the first instruction in a function, |
2077 | and it stores registers at offsets relative to the value of the old SP | |
2078 | (before the prologue). But the value of the sp parameter to this | |
2079 | function is the new SP (after the prologue has been executed). So we | |
2080 | can't calculate those offsets until we've seen the entire prologue, | |
2081 | and can calculate what the old SP must have been. */ | |
2082 | if (entry_inst != 0) | |
2083 | { | |
2084 | int areg_count = (entry_inst >> 8) & 7; | |
2085 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2086 | |
c5aa993b JM |
2087 | /* The entry instruction always subtracts 32 from the SP. */ |
2088 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2089 | |
c5aa993b JM |
2090 | /* Now we can calculate what the SP must have been at the |
2091 | start of the function prologue. */ | |
2092 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2093 | |
c5aa993b JM |
2094 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2095 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2096 | { | |
2097 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2098 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2099 | offset += MIPS_SAVED_REGSIZE; |
2100 | } | |
c906108c | 2101 | |
c5aa993b JM |
2102 | /* Check if the ra register was pushed on the stack. */ |
2103 | offset = -4; | |
2104 | if (entry_inst & 0x20) | |
2105 | { | |
2106 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2107 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c5aa993b JM |
2108 | offset -= MIPS_SAVED_REGSIZE; |
2109 | } | |
c906108c | 2110 | |
c5aa993b JM |
2111 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2112 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2113 | { | |
2114 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2115 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c5aa993b JM |
2116 | offset -= MIPS_SAVED_REGSIZE; |
2117 | } | |
2118 | } | |
c906108c SS |
2119 | } |
2120 | ||
2121 | static void | |
fba45db2 KB |
2122 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2123 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2124 | { |
2125 | CORE_ADDR cur_pc; | |
c5aa993b | 2126 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2127 | restart: |
fe29b929 | 2128 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2129 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2130 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2131 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2132 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2133 | { | |
2134 | unsigned long inst, high_word, low_word; | |
2135 | int reg; | |
2136 | ||
2137 | /* Fetch the instruction. */ | |
2138 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2139 | ||
2140 | /* Save some code by pre-extracting some useful fields. */ | |
2141 | high_word = (inst >> 16) & 0xffff; | |
2142 | low_word = inst & 0xffff; | |
2143 | reg = high_word & 0x1f; | |
2144 | ||
c5aa993b | 2145 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2146 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2147 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2148 | { | |
2149 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2150 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2151 | else |
2152 | /* Exit loop if a positive stack adjustment is found, which | |
2153 | usually means that the stack cleanup code in the function | |
2154 | epilogue is reached. */ | |
2155 | break; | |
2156 | } | |
2157 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2158 | { | |
c5aa993b | 2159 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2160 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2161 | } |
2162 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2163 | { | |
2164 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
2165 | but the register size used is only 32 bits. Make the address | |
2166 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 2167 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
4246e332 | 2168 | set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch)); |
c906108c | 2169 | } |
c5aa993b | 2170 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2171 | { |
2172 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2173 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2174 | frame_addr = sp + low_word; | |
c906108c SS |
2175 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
2176 | { | |
2177 | unsigned alloca_adjust; | |
2178 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2179 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2180 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2181 | if (alloca_adjust > 0) |
2182 | { | |
2183 | /* FP > SP + frame_size. This may be because | |
2184 | * of an alloca or somethings similar. | |
2185 | * Fix sp to "pre-alloca" value, and try again. | |
2186 | */ | |
2187 | sp += alloca_adjust; | |
2188 | goto restart; | |
2189 | } | |
2190 | } | |
2191 | } | |
c5aa993b JM |
2192 | /* move $30,$sp. With different versions of gas this will be either |
2193 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2194 | Accept any one of these. */ | |
c906108c SS |
2195 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2196 | { | |
2197 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2198 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
2199 | { | |
2200 | unsigned alloca_adjust; | |
2201 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2202 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2203 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2204 | if (alloca_adjust > 0) |
2205 | { | |
2206 | /* FP > SP + frame_size. This may be because | |
2207 | * of an alloca or somethings similar. | |
2208 | * Fix sp to "pre-alloca" value, and try again. | |
2209 | */ | |
2210 | sp += alloca_adjust; | |
2211 | goto restart; | |
2212 | } | |
2213 | } | |
2214 | } | |
c5aa993b | 2215 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2216 | { |
c5aa993b | 2217 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2218 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2219 | } |
2220 | } | |
2221 | } | |
2222 | ||
2223 | static mips_extra_func_info_t | |
acdb74a0 | 2224 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 2225 | struct frame_info *next_frame, int cur_frame) |
c906108c | 2226 | { |
479412cd DJ |
2227 | CORE_ADDR sp; |
2228 | ||
2229 | if (cur_frame) | |
a4b8ebc8 | 2230 | sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); |
479412cd DJ |
2231 | else |
2232 | sp = 0; | |
c906108c | 2233 | |
c5aa993b JM |
2234 | if (start_pc == 0) |
2235 | return NULL; | |
2236 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2237 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2238 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2239 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
2240 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2241 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2242 | ||
2243 | if (start_pc + 200 < limit_pc) | |
2244 | limit_pc = start_pc + 200; | |
2245 | if (pc_is_mips16 (start_pc)) | |
2246 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2247 | else | |
2248 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2249 | return &temp_proc_desc; | |
2250 | } | |
2251 | ||
6c0d6680 DJ |
2252 | struct mips_objfile_private |
2253 | { | |
2254 | bfd_size_type size; | |
2255 | char *contents; | |
2256 | }; | |
2257 | ||
2258 | /* Global used to communicate between non_heuristic_proc_desc and | |
2259 | compare_pdr_entries within qsort (). */ | |
2260 | static bfd *the_bfd; | |
2261 | ||
2262 | static int | |
2263 | compare_pdr_entries (const void *a, const void *b) | |
2264 | { | |
2265 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2266 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2267 | ||
2268 | if (lhs < rhs) | |
2269 | return -1; | |
2270 | else if (lhs == rhs) | |
2271 | return 0; | |
2272 | else | |
2273 | return 1; | |
2274 | } | |
2275 | ||
c906108c | 2276 | static mips_extra_func_info_t |
acdb74a0 | 2277 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2278 | { |
2279 | CORE_ADDR startaddr; | |
2280 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2281 | struct block *b = block_for_pc (pc); |
c906108c | 2282 | struct symbol *sym; |
6c0d6680 DJ |
2283 | struct obj_section *sec; |
2284 | struct mips_objfile_private *priv; | |
2285 | ||
ae45cd16 | 2286 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
6c0d6680 | 2287 | return NULL; |
c906108c SS |
2288 | |
2289 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2290 | if (addrptr) | |
2291 | *addrptr = startaddr; | |
6c0d6680 DJ |
2292 | |
2293 | priv = NULL; | |
2294 | ||
2295 | sec = find_pc_section (pc); | |
2296 | if (sec != NULL) | |
c906108c | 2297 | { |
6c0d6680 DJ |
2298 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2299 | ||
2300 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2301 | the information normally found in ECOFF PDRs. */ | |
2302 | ||
2303 | the_bfd = sec->objfile->obfd; | |
2304 | if (priv == NULL | |
2305 | && (the_bfd->format == bfd_object | |
2306 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2307 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2308 | { | |
2309 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2310 | This means that we should not bother with this method on 64-bit | |
2311 | targets (until that is fixed). */ | |
2312 | ||
2313 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2314 | sizeof (struct mips_objfile_private)); | |
2315 | priv->size = 0; | |
2316 | sec->objfile->obj_private = priv; | |
2317 | } | |
2318 | else if (priv == NULL) | |
2319 | { | |
2320 | asection *bfdsec; | |
2321 | ||
2322 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2323 | sizeof (struct mips_objfile_private)); | |
2324 | ||
2325 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2326 | if (bfdsec != NULL) | |
2327 | { | |
2328 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2329 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2330 | priv->size); | |
2331 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2332 | priv->contents, 0, priv->size); | |
2333 | ||
2334 | /* In general, the .pdr section is sorted. However, in the | |
2335 | presence of multiple code sections (and other corner cases) | |
2336 | it can become unsorted. Sort it so that we can use a faster | |
2337 | binary search. */ | |
2338 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2339 | } | |
2340 | else | |
2341 | priv->size = 0; | |
2342 | ||
2343 | sec->objfile->obj_private = priv; | |
2344 | } | |
2345 | the_bfd = NULL; | |
2346 | ||
2347 | if (priv->size != 0) | |
2348 | { | |
2349 | int low, mid, high; | |
2350 | char *ptr; | |
2351 | ||
2352 | low = 0; | |
2353 | high = priv->size / 32; | |
2354 | ||
2355 | do | |
2356 | { | |
2357 | CORE_ADDR pdr_pc; | |
2358 | ||
2359 | mid = (low + high) / 2; | |
2360 | ||
2361 | ptr = priv->contents + mid * 32; | |
2362 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2363 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2364 | SECT_OFF_TEXT (sec->objfile)); | |
2365 | if (pdr_pc == startaddr) | |
2366 | break; | |
2367 | if (pdr_pc > startaddr) | |
2368 | high = mid; | |
2369 | else | |
2370 | low = mid + 1; | |
2371 | } | |
2372 | while (low != high); | |
2373 | ||
2374 | if (low != high) | |
2375 | { | |
2376 | struct symbol *sym = find_pc_function (pc); | |
2377 | ||
2378 | /* Fill in what we need of the proc_desc. */ | |
2379 | proc_desc = (mips_extra_func_info_t) | |
2380 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2381 | sizeof (struct mips_extra_func_info)); | |
2382 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2383 | ||
2384 | /* Only used for dummy frames. */ | |
2385 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2386 | ||
2387 | PROC_FRAME_OFFSET (proc_desc) | |
2388 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2389 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2390 | ptr + 24); | |
2391 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2392 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2393 | ptr + 4); | |
2394 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2395 | ptr + 12); | |
2396 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2397 | ptr + 8); | |
2398 | PROC_FREG_OFFSET (proc_desc) | |
2399 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2400 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2401 | ptr + 28); | |
2402 | proc_desc->pdr.isym = (long) sym; | |
2403 | ||
2404 | return proc_desc; | |
2405 | } | |
2406 | } | |
c906108c SS |
2407 | } |
2408 | ||
6c0d6680 DJ |
2409 | if (b == NULL) |
2410 | return NULL; | |
2411 | ||
2412 | if (startaddr > BLOCK_START (b)) | |
2413 | { | |
2414 | /* This is the "pathological" case referred to in a comment in | |
2415 | print_frame_info. It might be better to move this check into | |
2416 | symbol reading. */ | |
2417 | return NULL; | |
2418 | } | |
2419 | ||
176620f1 | 2420 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2421 | |
c906108c SS |
2422 | /* If we never found a PDR for this function in symbol reading, then |
2423 | examine prologues to find the information. */ | |
2424 | if (sym) | |
2425 | { | |
2426 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2427 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2428 | return NULL; | |
2429 | else | |
2430 | return proc_desc; | |
2431 | } | |
2432 | else | |
2433 | return NULL; | |
2434 | } | |
2435 | ||
2436 | ||
2437 | static mips_extra_func_info_t | |
479412cd | 2438 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2439 | { |
2440 | mips_extra_func_info_t proc_desc; | |
4e0df2df | 2441 | CORE_ADDR startaddr = 0; |
c906108c SS |
2442 | |
2443 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2444 | ||
2445 | if (proc_desc) | |
2446 | { | |
2447 | /* IF this is the topmost frame AND | |
2448 | * (this proc does not have debugging information OR | |
2449 | * the PC is in the procedure prologue) | |
2450 | * THEN create a "heuristic" proc_desc (by analyzing | |
2451 | * the actual code) to replace the "official" proc_desc. | |
2452 | */ | |
2453 | if (next_frame == NULL) | |
2454 | { | |
2455 | struct symtab_and_line val; | |
2456 | struct symbol *proc_symbol = | |
c86b5b38 | 2457 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2458 | |
2459 | if (proc_symbol) | |
2460 | { | |
2461 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2462 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2463 | 0); |
2464 | val.pc = val.end ? val.end : pc; | |
2465 | } | |
2466 | if (!proc_symbol || pc < val.pc) | |
2467 | { | |
2468 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2469 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2470 | pc, next_frame, cur_frame); | |
c906108c SS |
2471 | if (found_heuristic) |
2472 | proc_desc = found_heuristic; | |
2473 | } | |
2474 | } | |
2475 | } | |
2476 | else | |
2477 | { | |
2478 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2479 | by procedure call dummys. However, the procedures being called ought |
2480 | to have their own proc_descs, and even if they don't, | |
2481 | heuristic_proc_desc knows how to create them! */ | |
c906108c | 2482 | |
aa1ee363 | 2483 | struct linked_proc_info *link; |
c906108c SS |
2484 | |
2485 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2486 | if (PROC_LOW_ADDR (&link->info) <= pc |
2487 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2488 | return &link->info; |
2489 | ||
2490 | if (startaddr == 0) | |
2491 | startaddr = heuristic_proc_start (pc); | |
2492 | ||
2493 | proc_desc = | |
479412cd | 2494 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2495 | } |
2496 | return proc_desc; | |
2497 | } | |
2498 | ||
2499 | static CORE_ADDR | |
acdb74a0 AC |
2500 | get_frame_pointer (struct frame_info *frame, |
2501 | mips_extra_func_info_t proc_desc) | |
c906108c | 2502 | { |
a4b8ebc8 | 2503 | return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) |
e227b13c AC |
2504 | + PROC_FRAME_OFFSET (proc_desc) |
2505 | - PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2506 | } |
2507 | ||
5a89d8aa | 2508 | static mips_extra_func_info_t cached_proc_desc; |
c906108c | 2509 | |
f7ab6ec6 | 2510 | static CORE_ADDR |
acdb74a0 | 2511 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2512 | { |
2513 | mips_extra_func_info_t proc_desc; | |
2514 | CORE_ADDR tmp; | |
8bedc050 | 2515 | CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame); |
c906108c | 2516 | |
c906108c SS |
2517 | /* Check if the PC is inside a call stub. If it is, fetch the |
2518 | PC of the caller of that stub. */ | |
5a89d8aa | 2519 | if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) |
c906108c SS |
2520 | saved_pc = tmp; |
2521 | ||
ae45cd16 | 2522 | if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0)) |
cedea778 AC |
2523 | { |
2524 | /* A dummy frame, uses SP not FP. Get the old SP value. If all | |
2525 | is well, frame->frame the bottom of the current frame will | |
2526 | contain that value. */ | |
1e2330ba | 2527 | return get_frame_base (frame); |
cedea778 AC |
2528 | } |
2529 | ||
c906108c | 2530 | /* Look up the procedure descriptor for this PC. */ |
479412cd | 2531 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2532 | if (!proc_desc) |
2533 | return 0; | |
2534 | ||
2535 | cached_proc_desc = proc_desc; | |
2536 | ||
2537 | /* If no frame pointer and frame size is zero, we must be at end | |
2538 | of stack (or otherwise hosed). If we don't check frame size, | |
2539 | we loop forever if we see a zero size frame. */ | |
2540 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2541 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
7807aa61 MS |
2542 | /* The previous frame from a sigtramp frame might be frameless |
2543 | and have frame size zero. */ | |
5a203e44 | 2544 | && !(get_frame_type (frame) == SIGTRAMP_FRAME) |
cedea778 AC |
2545 | /* For a generic dummy frame, let get_frame_pointer() unwind a |
2546 | register value saved as part of the dummy frame call. */ | |
50abf9e5 | 2547 | && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))) |
c906108c SS |
2548 | return 0; |
2549 | else | |
2550 | return get_frame_pointer (frame, proc_desc); | |
2551 | } | |
2552 | ||
f7ab6ec6 | 2553 | static void |
acdb74a0 | 2554 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2555 | { |
2556 | int regnum; | |
f2c16bd6 KB |
2557 | mips_extra_func_info_t proc_desc; |
2558 | ||
2559 | if (get_frame_type (fci) == DUMMY_FRAME) | |
2560 | return; | |
c906108c | 2561 | |
f796e4be KB |
2562 | /* Use proc_desc calculated in frame_chain. When there is no |
2563 | next frame, i.e, get_next_frame (fci) == NULL, we call | |
2564 | find_proc_desc () to calculate it, passing an explicit | |
2565 | NULL as the frame parameter. */ | |
f2c16bd6 | 2566 | proc_desc = |
11c02a10 AC |
2567 | get_next_frame (fci) |
2568 | ? cached_proc_desc | |
f796e4be KB |
2569 | : find_proc_desc (get_frame_pc (fci), |
2570 | NULL /* i.e, get_next_frame (fci) */, | |
2571 | 1); | |
c906108c | 2572 | |
a00a19e9 | 2573 | frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info)); |
cce74817 | 2574 | |
da50a4b7 | 2575 | get_frame_extra_info (fci)->proc_desc = |
c906108c SS |
2576 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2577 | if (proc_desc) | |
2578 | { | |
2579 | /* Fixup frame-pointer - only needed for top frame */ | |
2580 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2581 | Get the value of the frame relative sp, procedure might have been |
2582 | interrupted by a signal at it's very start. */ | |
50abf9e5 | 2583 | if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc) |
c906108c | 2584 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
a4b8ebc8 | 2585 | deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM)); |
50abf9e5 | 2586 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0)) |
cedea778 AC |
2587 | /* Do not ``fix'' fci->frame. It will have the value of the |
2588 | generic dummy frame's top-of-stack (since the draft | |
2589 | fci->frame is obtained by returning the unwound stack | |
2590 | pointer) and that is what we want. That way the fci->frame | |
2591 | value will match the top-of-stack value that was saved as | |
2592 | part of the dummy frames data. */ | |
2593 | /* Do nothing. */; | |
c906108c | 2594 | else |
11c02a10 | 2595 | deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc)); |
c906108c SS |
2596 | |
2597 | if (proc_desc == &temp_proc_desc) | |
2598 | { | |
2599 | char *name; | |
2600 | ||
2601 | /* Do not set the saved registers for a sigtramp frame, | |
5a203e44 AC |
2602 | mips_find_saved_registers will do that for us. We can't |
2603 | use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not | |
2604 | yet set. */ | |
2605 | /* FIXME: cagney/2002-11-18: This problem will go away once | |
2606 | frame.c:get_prev_frame() is modified to set the frame's | |
2607 | type before calling functions like this. */ | |
50abf9e5 | 2608 | find_pc_partial_function (get_frame_pc (fci), &name, |
c5aa993b | 2609 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
50abf9e5 | 2610 | if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name)) |
c906108c | 2611 | { |
c5aa993b | 2612 | frame_saved_regs_zalloc (fci); |
e0f7ec59 AC |
2613 | /* Set value of previous frame's stack pointer. |
2614 | Remember that saved_regs[SP_REGNUM] is special in | |
2615 | that it contains the value of the stack pointer | |
2616 | register. The other saved_regs values are addresses | |
2617 | (in the inferior) at which a given register's value | |
2618 | may be found. */ | |
2619 | set_reg_offset (temp_saved_regs, SP_REGNUM, | |
2620 | get_frame_base (fci)); | |
2621 | set_reg_offset (temp_saved_regs, PC_REGNUM, | |
2622 | temp_saved_regs[RA_REGNUM]); | |
1b1d3794 | 2623 | memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs, |
e0f7ec59 | 2624 | SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2625 | } |
2626 | } | |
2627 | ||
2628 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 | 2629 | /* assume we can't tell how many args for now */ |
da50a4b7 | 2630 | get_frame_extra_info (fci)->num_args = -1; |
c906108c SS |
2631 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2632 | { | |
c5aa993b | 2633 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2634 | { |
da50a4b7 | 2635 | get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2636 | break; |
2637 | } | |
c5aa993b | 2638 | } |
c906108c SS |
2639 | } |
2640 | } | |
2641 | ||
2642 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2643 | we basically have to look at symbol information for the function | |
2644 | that we stopped in, which tells us *which* register (if any) is | |
2645 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2646 | the frame itself is at. |
c906108c SS |
2647 | |
2648 | This presents a problem when trying to examine a stack in memory | |
2649 | (that isn't executing at the moment), using the "frame" command. We | |
2650 | don't have a PC, nor do we have any registers except SP. | |
2651 | ||
2652 | This routine takes two arguments, SP and PC, and tries to make the | |
2653 | cached frames look as if these two arguments defined a frame on the | |
2654 | cache. This allows the rest of info frame to extract the important | |
2655 | arguments without difficulty. */ | |
2656 | ||
2657 | struct frame_info * | |
acdb74a0 | 2658 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2659 | { |
2660 | if (argc != 2) | |
2661 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2662 | ||
2663 | return create_new_frame (argv[0], argv[1]); | |
2664 | } | |
2665 | ||
f09ded24 AC |
2666 | /* According to the current ABI, should the type be passed in a |
2667 | floating-point register (assuming that there is space)? When there | |
2668 | is no FPU, FP are not even considered as possibile candidates for | |
2669 | FP registers and, consequently this returns false - forces FP | |
2670 | arguments into integer registers. */ | |
2671 | ||
2672 | static int | |
2673 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2674 | { | |
2675 | return ((typecode == TYPE_CODE_FLT | |
2676 | || (MIPS_EABI | |
2677 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2678 | && TYPE_NFIELDS (arg_type) == 1 | |
2679 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2680 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2681 | } |
2682 | ||
49e790b0 DJ |
2683 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2684 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2685 | ||
2686 | static int | |
2687 | mips_type_needs_double_align (struct type *type) | |
2688 | { | |
2689 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2690 | |
49e790b0 DJ |
2691 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2692 | return 1; | |
2693 | else if (typecode == TYPE_CODE_STRUCT) | |
2694 | { | |
2695 | if (TYPE_NFIELDS (type) < 1) | |
2696 | return 0; | |
2697 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2698 | } | |
2699 | else if (typecode == TYPE_CODE_UNION) | |
2700 | { | |
361d1df0 | 2701 | int i, n; |
49e790b0 DJ |
2702 | |
2703 | n = TYPE_NFIELDS (type); | |
2704 | for (i = 0; i < n; i++) | |
2705 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2706 | return 1; | |
2707 | return 0; | |
2708 | } | |
2709 | return 0; | |
2710 | } | |
2711 | ||
dc604539 AC |
2712 | /* Adjust the address downward (direction of stack growth) so that it |
2713 | is correctly aligned for a new stack frame. */ | |
2714 | static CORE_ADDR | |
2715 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2716 | { | |
5b03f266 | 2717 | return align_down (addr, 16); |
dc604539 AC |
2718 | } |
2719 | ||
f7ab6ec6 | 2720 | static CORE_ADDR |
25ab4790 AC |
2721 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2722 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2723 | struct value **args, CORE_ADDR sp, int struct_return, | |
2724 | CORE_ADDR struct_addr) | |
c906108c SS |
2725 | { |
2726 | int argreg; | |
2727 | int float_argreg; | |
2728 | int argnum; | |
2729 | int len = 0; | |
2730 | int stack_offset = 0; | |
2731 | ||
25ab4790 AC |
2732 | /* For shared libraries, "t9" needs to point at the function |
2733 | address. */ | |
2734 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2735 | ||
2736 | /* Set the return address register to point to the entry point of | |
2737 | the program, where a breakpoint lies in wait. */ | |
2738 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
2739 | ||
c906108c | 2740 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2741 | are properly aligned. The stack has to be at least 64-bit |
2742 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2743 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2744 | aligned, so we round to this widest known alignment. */ | |
2745 | ||
5b03f266 AC |
2746 | sp = align_down (sp, 16); |
2747 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2748 | |
46e0f506 | 2749 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2750 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2751 | passed in registers, but that's OK. */ |
c906108c | 2752 | for (argnum = 0; argnum < nargs; argnum++) |
5b03f266 | 2753 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46e0f506 | 2754 | MIPS_STACK_ARGSIZE); |
5b03f266 | 2755 | sp -= align_up (len, 16); |
c906108c | 2756 | |
9ace0497 | 2757 | if (mips_debug) |
46e0f506 | 2758 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2759 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2760 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2761 | |
c906108c SS |
2762 | /* Initialize the integer and float register pointers. */ |
2763 | argreg = A0_REGNUM; | |
56cea623 | 2764 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2765 | |
46e0f506 | 2766 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2767 | if (struct_return) |
9ace0497 AC |
2768 | { |
2769 | if (mips_debug) | |
2770 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2771 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2772 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2773 | write_register (argreg++, struct_addr); |
2774 | } | |
c906108c SS |
2775 | |
2776 | /* Now load as many as possible of the first arguments into | |
2777 | registers, and push the rest onto the stack. Loop thru args | |
2778 | from first to last. */ | |
2779 | for (argnum = 0; argnum < nargs; argnum++) | |
2780 | { | |
2781 | char *val; | |
d9d9c31f | 2782 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2783 | struct value *arg = args[argnum]; |
c906108c SS |
2784 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2785 | int len = TYPE_LENGTH (arg_type); | |
2786 | enum type_code typecode = TYPE_CODE (arg_type); | |
2787 | ||
9ace0497 AC |
2788 | if (mips_debug) |
2789 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2790 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2791 | argnum + 1, len, (int) typecode); |
9ace0497 | 2792 | |
c906108c | 2793 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2794 | reference. */ |
2795 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2796 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2797 | { |
fbd9dcd3 | 2798 | store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2799 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2800 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2801 | val = valbuf; |
9ace0497 AC |
2802 | if (mips_debug) |
2803 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2804 | } |
2805 | else | |
c5aa993b | 2806 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2807 | |
2808 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2809 | even-numbered floating point register. Round the FP register |
2810 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2811 | left. Non MIPS_EABI targets also pass the FP in the integer |
2812 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2813 | if (!FP_REGISTER_DOUBLE |
2814 | && fp_register_arg_p (typecode, arg_type)) | |
2815 | { | |
2816 | if ((float_argreg & 1)) | |
2817 | float_argreg++; | |
2818 | } | |
c906108c SS |
2819 | |
2820 | /* Floating point arguments passed in registers have to be | |
2821 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2822 | are passed in register pairs; the even register gets |
2823 | the low word, and the odd register gets the high word. | |
2824 | On non-EABI processors, the first two floating point arguments are | |
2825 | also copied to general registers, because MIPS16 functions | |
2826 | don't use float registers for arguments. This duplication of | |
2827 | arguments in general registers can't hurt non-MIPS16 functions | |
2828 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2829 | /* MIPS_EABI squeezes a struct that contains a single floating |
2830 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2831 | stack. */ |
f09ded24 AC |
2832 | if (fp_register_arg_p (typecode, arg_type) |
2833 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2834 | { |
2835 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2836 | { | |
d7449b42 | 2837 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2838 | unsigned long regval; |
2839 | ||
2840 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2841 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2842 | if (mips_debug) |
acdb74a0 | 2843 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2844 | float_argreg, phex (regval, 4)); |
c906108c | 2845 | write_register (float_argreg++, regval); |
c906108c SS |
2846 | |
2847 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2848 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2849 | if (mips_debug) |
acdb74a0 | 2850 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2851 | float_argreg, phex (regval, 4)); |
c906108c | 2852 | write_register (float_argreg++, regval); |
c906108c SS |
2853 | } |
2854 | else | |
2855 | { | |
2856 | /* This is a floating point value that fits entirely | |
2857 | in a single register. */ | |
53a5351d | 2858 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2859 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2860 | LONGEST regval = extract_unsigned_integer (val, len); |
2861 | if (mips_debug) | |
acdb74a0 | 2862 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2863 | float_argreg, phex (regval, len)); |
c906108c | 2864 | write_register (float_argreg++, regval); |
c906108c SS |
2865 | } |
2866 | } | |
2867 | else | |
2868 | { | |
2869 | /* Copy the argument to general registers or the stack in | |
2870 | register-sized pieces. Large arguments are split between | |
2871 | registers and stack. */ | |
4246e332 AC |
2872 | /* Note: structs whose size is not a multiple of |
2873 | mips_regsize() are treated specially: Irix cc passes them | |
2874 | in registers where gcc sometimes puts them on the stack. | |
2875 | For maximum compatibility, we will put them in both | |
2876 | places. */ | |
c5aa993b | 2877 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2878 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2879 | |
f09ded24 | 2880 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2881 | register are only written to memory. */ |
c906108c SS |
2882 | while (len > 0) |
2883 | { | |
ebafbe83 | 2884 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2885 | int stack_used_p = 0; |
46e0f506 MS |
2886 | int partial_len = |
2887 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2888 | |
acdb74a0 AC |
2889 | if (mips_debug) |
2890 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2891 | partial_len); | |
2892 | ||
566f0f7a | 2893 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2894 | if (argreg > MIPS_LAST_ARG_REGNUM |
2895 | || odd_sized_struct | |
2896 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2897 | { |
c906108c SS |
2898 | /* Should shorter than int integer values be |
2899 | promoted to int before being stored? */ | |
c906108c | 2900 | int longword_offset = 0; |
9ace0497 | 2901 | CORE_ADDR addr; |
566f0f7a | 2902 | stack_used_p = 1; |
d7449b42 | 2903 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2904 | { |
d929b26f | 2905 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2906 | (typecode == TYPE_CODE_INT || |
2907 | typecode == TYPE_CODE_PTR || | |
2908 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2909 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2910 | else if ((typecode == TYPE_CODE_STRUCT || |
2911 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2912 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2913 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2914 | } |
c5aa993b | 2915 | |
9ace0497 AC |
2916 | if (mips_debug) |
2917 | { | |
cb3d25d1 MS |
2918 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2919 | paddr_nz (stack_offset)); | |
2920 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2921 | paddr_nz (longword_offset)); | |
9ace0497 | 2922 | } |
361d1df0 | 2923 | |
9ace0497 AC |
2924 | addr = sp + stack_offset + longword_offset; |
2925 | ||
2926 | if (mips_debug) | |
2927 | { | |
2928 | int i; | |
cb3d25d1 MS |
2929 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2930 | paddr_nz (addr)); | |
9ace0497 AC |
2931 | for (i = 0; i < partial_len; i++) |
2932 | { | |
cb3d25d1 MS |
2933 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2934 | val[i] & 0xff); | |
9ace0497 AC |
2935 | } |
2936 | } | |
2937 | write_memory (addr, val, partial_len); | |
c906108c SS |
2938 | } |
2939 | ||
f09ded24 AC |
2940 | /* Note!!! This is NOT an else clause. Odd sized |
2941 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2942 | arguments will not. */ |
566f0f7a | 2943 | /* Write this portion of the argument to a general |
46e0f506 | 2944 | purpose register. */ |
f09ded24 AC |
2945 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2946 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2947 | { |
9ace0497 | 2948 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2949 | |
9ace0497 | 2950 | if (mips_debug) |
acdb74a0 | 2951 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2952 | argreg, |
2953 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2954 | write_register (argreg, regval); |
2955 | argreg++; | |
c906108c | 2956 | } |
c5aa993b | 2957 | |
c906108c SS |
2958 | len -= partial_len; |
2959 | val += partial_len; | |
2960 | ||
566f0f7a AC |
2961 | /* Compute the the offset into the stack at which we |
2962 | will copy the next parameter. | |
2963 | ||
566f0f7a | 2964 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2965 | only needs to be adjusted when it has been used. */ |
c906108c | 2966 | |
46e0f506 | 2967 | if (stack_used_p) |
5b03f266 | 2968 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2969 | } |
2970 | } | |
9ace0497 AC |
2971 | if (mips_debug) |
2972 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2973 | } |
2974 | ||
310e9b6a AC |
2975 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
2976 | ||
0f71a2f6 JM |
2977 | /* Return adjusted stack pointer. */ |
2978 | return sp; | |
2979 | } | |
2980 | ||
25ab4790 | 2981 | /* N32/N64 version of push_dummy_call. */ |
ebafbe83 | 2982 | |
f7ab6ec6 | 2983 | static CORE_ADDR |
25ab4790 AC |
2984 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
2985 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2986 | struct value **args, CORE_ADDR sp, int struct_return, | |
2987 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2988 | { |
2989 | int argreg; | |
2990 | int float_argreg; | |
2991 | int argnum; | |
2992 | int len = 0; | |
2993 | int stack_offset = 0; | |
2994 | ||
25ab4790 AC |
2995 | /* For shared libraries, "t9" needs to point at the function |
2996 | address. */ | |
2997 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
2998 | ||
2999 | /* Set the return address register to point to the entry point of | |
3000 | the program, where a breakpoint lies in wait. */ | |
3001 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3002 | ||
cb3d25d1 MS |
3003 | /* First ensure that the stack and structure return address (if any) |
3004 | are properly aligned. The stack has to be at least 64-bit | |
3005 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3006 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3007 | aligned, so we round to this widest known alignment. */ | |
3008 | ||
5b03f266 AC |
3009 | sp = align_down (sp, 16); |
3010 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3011 | |
3012 | /* Now make space on the stack for the args. */ | |
3013 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3014 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
cb3d25d1 | 3015 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3016 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3017 | |
3018 | if (mips_debug) | |
3019 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3020 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3021 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3022 | |
3023 | /* Initialize the integer and float register pointers. */ | |
3024 | argreg = A0_REGNUM; | |
56cea623 | 3025 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3026 | |
46e0f506 | 3027 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3028 | if (struct_return) |
3029 | { | |
3030 | if (mips_debug) | |
3031 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3032 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3033 | argreg, paddr_nz (struct_addr)); |
3034 | write_register (argreg++, struct_addr); | |
3035 | } | |
3036 | ||
3037 | /* Now load as many as possible of the first arguments into | |
3038 | registers, and push the rest onto the stack. Loop thru args | |
3039 | from first to last. */ | |
3040 | for (argnum = 0; argnum < nargs; argnum++) | |
3041 | { | |
3042 | char *val; | |
d9d9c31f | 3043 | char valbuf[MAX_REGISTER_SIZE]; |
cb3d25d1 MS |
3044 | struct value *arg = args[argnum]; |
3045 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3046 | int len = TYPE_LENGTH (arg_type); | |
3047 | enum type_code typecode = TYPE_CODE (arg_type); | |
3048 | ||
3049 | if (mips_debug) | |
3050 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3051 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3052 | argnum + 1, len, (int) typecode); |
3053 | ||
3054 | val = (char *) VALUE_CONTENTS (arg); | |
3055 | ||
3056 | if (fp_register_arg_p (typecode, arg_type) | |
3057 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3058 | { | |
3059 | /* This is a floating point value that fits entirely | |
3060 | in a single register. */ | |
3061 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3062 | above to ensure that it is even register aligned. */ | |
3063 | LONGEST regval = extract_unsigned_integer (val, len); | |
3064 | if (mips_debug) | |
3065 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3066 | float_argreg, phex (regval, len)); | |
3067 | write_register (float_argreg++, regval); | |
3068 | ||
3069 | if (mips_debug) | |
3070 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3071 | argreg, phex (regval, len)); | |
3072 | write_register (argreg, regval); | |
3073 | argreg += 1; | |
3074 | } | |
3075 | else | |
3076 | { | |
3077 | /* Copy the argument to general registers or the stack in | |
3078 | register-sized pieces. Large arguments are split between | |
3079 | registers and stack. */ | |
4246e332 AC |
3080 | /* Note: structs whose size is not a multiple of |
3081 | mips_regsize() are treated specially: Irix cc passes them | |
3082 | in registers where gcc sometimes puts them on the stack. | |
3083 | For maximum compatibility, we will put them in both | |
3084 | places. */ | |
cb3d25d1 MS |
3085 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3086 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3087 | /* Note: Floating-point values that didn't fit into an FP | |
3088 | register are only written to memory. */ | |
3089 | while (len > 0) | |
3090 | { | |
3091 | /* Rememer if the argument was written to the stack. */ | |
3092 | int stack_used_p = 0; | |
3093 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
3094 | len : MIPS_SAVED_REGSIZE; | |
3095 | ||
3096 | if (mips_debug) | |
3097 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3098 | partial_len); | |
3099 | ||
3100 | /* Write this portion of the argument to the stack. */ | |
3101 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3102 | || odd_sized_struct | |
3103 | || fp_register_arg_p (typecode, arg_type)) | |
3104 | { | |
3105 | /* Should shorter than int integer values be | |
3106 | promoted to int before being stored? */ | |
3107 | int longword_offset = 0; | |
3108 | CORE_ADDR addr; | |
3109 | stack_used_p = 1; | |
3110 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3111 | { | |
3112 | if (MIPS_STACK_ARGSIZE == 8 && | |
3113 | (typecode == TYPE_CODE_INT || | |
3114 | typecode == TYPE_CODE_PTR || | |
3115 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3116 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
cb3d25d1 MS |
3117 | } |
3118 | ||
3119 | if (mips_debug) | |
3120 | { | |
3121 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3122 | paddr_nz (stack_offset)); | |
3123 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3124 | paddr_nz (longword_offset)); | |
3125 | } | |
3126 | ||
3127 | addr = sp + stack_offset + longword_offset; | |
3128 | ||
3129 | if (mips_debug) | |
3130 | { | |
3131 | int i; | |
3132 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3133 | paddr_nz (addr)); | |
3134 | for (i = 0; i < partial_len; i++) | |
3135 | { | |
3136 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3137 | val[i] & 0xff); | |
3138 | } | |
3139 | } | |
3140 | write_memory (addr, val, partial_len); | |
3141 | } | |
3142 | ||
3143 | /* Note!!! This is NOT an else clause. Odd sized | |
3144 | structs may go thru BOTH paths. Floating point | |
3145 | arguments will not. */ | |
3146 | /* Write this portion of the argument to a general | |
3147 | purpose register. */ | |
3148 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3149 | && !fp_register_arg_p (typecode, arg_type)) | |
3150 | { | |
3151 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
3152 | ||
3153 | /* A non-floating-point argument being passed in a | |
3154 | general register. If a struct or union, and if | |
3155 | the remaining length is smaller than the register | |
3156 | size, we have to adjust the register value on | |
3157 | big endian targets. | |
3158 | ||
3159 | It does not seem to be necessary to do the | |
3160 | same for integral types. | |
3161 | ||
3162 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3163 | outputting LE O32 with sizeof (struct) < | |
3164 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3165 | part of storing the argument in a register a | |
3166 | register (the left shift isn't generated when | |
3167 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3168 | is quite possible that this is GCC contradicting | |
3169 | the LE/O32 ABI, GDB has not been adjusted to | |
3170 | accommodate this. Either someone needs to | |
3171 | demonstrate that the LE/O32 ABI specifies such a | |
3172 | left shift OR this new ABI gets identified as | |
3173 | such and GDB gets tweaked accordingly. */ | |
3174 | ||
3175 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3176 | && partial_len < MIPS_SAVED_REGSIZE | |
3177 | && (typecode == TYPE_CODE_STRUCT || | |
3178 | typecode == TYPE_CODE_UNION)) | |
3179 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3180 | TARGET_CHAR_BIT); | |
3181 | ||
3182 | if (mips_debug) | |
3183 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3184 | argreg, | |
3185 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3186 | write_register (argreg, regval); | |
3187 | argreg++; | |
3188 | } | |
3189 | ||
3190 | len -= partial_len; | |
3191 | val += partial_len; | |
3192 | ||
3193 | /* Compute the the offset into the stack at which we | |
3194 | will copy the next parameter. | |
3195 | ||
3196 | In N32 (N64?), the stack_offset only needs to be | |
3197 | adjusted when it has been used. */ | |
3198 | ||
3199 | if (stack_used_p) | |
5b03f266 | 3200 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
cb3d25d1 MS |
3201 | } |
3202 | } | |
3203 | if (mips_debug) | |
3204 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3205 | } | |
3206 | ||
310e9b6a AC |
3207 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3208 | ||
cb3d25d1 MS |
3209 | /* Return adjusted stack pointer. */ |
3210 | return sp; | |
3211 | } | |
3212 | ||
25ab4790 | 3213 | /* O32 version of push_dummy_call. */ |
ebafbe83 | 3214 | |
46cac009 | 3215 | static CORE_ADDR |
25ab4790 AC |
3216 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3217 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3218 | struct value **args, CORE_ADDR sp, int struct_return, | |
3219 | CORE_ADDR struct_addr) | |
ebafbe83 MS |
3220 | { |
3221 | int argreg; | |
3222 | int float_argreg; | |
3223 | int argnum; | |
3224 | int len = 0; | |
3225 | int stack_offset = 0; | |
ebafbe83 | 3226 | |
25ab4790 AC |
3227 | /* For shared libraries, "t9" needs to point at the function |
3228 | address. */ | |
3229 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3230 | ||
3231 | /* Set the return address register to point to the entry point of | |
3232 | the program, where a breakpoint lies in wait. */ | |
3233 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3234 | ||
ebafbe83 MS |
3235 | /* First ensure that the stack and structure return address (if any) |
3236 | are properly aligned. The stack has to be at least 64-bit | |
3237 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3238 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3239 | aligned, so we round to this widest known alignment. */ | |
3240 | ||
5b03f266 AC |
3241 | sp = align_down (sp, 16); |
3242 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3243 | |
3244 | /* Now make space on the stack for the args. */ | |
3245 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3246 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
ebafbe83 | 3247 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3248 | sp -= align_up (len, 16); |
ebafbe83 MS |
3249 | |
3250 | if (mips_debug) | |
3251 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3252 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3253 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3254 | |
3255 | /* Initialize the integer and float register pointers. */ | |
3256 | argreg = A0_REGNUM; | |
56cea623 | 3257 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3258 | |
bcb0cc15 | 3259 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3260 | if (struct_return) |
3261 | { | |
3262 | if (mips_debug) | |
3263 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3264 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3265 | argreg, paddr_nz (struct_addr)); |
3266 | write_register (argreg++, struct_addr); | |
3267 | stack_offset += MIPS_STACK_ARGSIZE; | |
3268 | } | |
3269 | ||
3270 | /* Now load as many as possible of the first arguments into | |
3271 | registers, and push the rest onto the stack. Loop thru args | |
3272 | from first to last. */ | |
3273 | for (argnum = 0; argnum < nargs; argnum++) | |
3274 | { | |
3275 | char *val; | |
d9d9c31f | 3276 | char valbuf[MAX_REGISTER_SIZE]; |
ebafbe83 MS |
3277 | struct value *arg = args[argnum]; |
3278 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3279 | int len = TYPE_LENGTH (arg_type); | |
3280 | enum type_code typecode = TYPE_CODE (arg_type); | |
3281 | ||
3282 | if (mips_debug) | |
3283 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3284 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3285 | argnum + 1, len, (int) typecode); |
3286 | ||
3287 | val = (char *) VALUE_CONTENTS (arg); | |
3288 | ||
3289 | /* 32-bit ABIs always start floating point arguments in an | |
3290 | even-numbered floating point register. Round the FP register | |
3291 | up before the check to see if there are any FP registers | |
3292 | left. O32/O64 targets also pass the FP in the integer | |
3293 | registers so also round up normal registers. */ | |
3294 | if (!FP_REGISTER_DOUBLE | |
3295 | && fp_register_arg_p (typecode, arg_type)) | |
3296 | { | |
3297 | if ((float_argreg & 1)) | |
3298 | float_argreg++; | |
3299 | } | |
3300 | ||
3301 | /* Floating point arguments passed in registers have to be | |
3302 | treated specially. On 32-bit architectures, doubles | |
3303 | are passed in register pairs; the even register gets | |
3304 | the low word, and the odd register gets the high word. | |
3305 | On O32/O64, the first two floating point arguments are | |
3306 | also copied to general registers, because MIPS16 functions | |
3307 | don't use float registers for arguments. This duplication of | |
3308 | arguments in general registers can't hurt non-MIPS16 functions | |
3309 | because those registers are normally skipped. */ | |
3310 | ||
3311 | if (fp_register_arg_p (typecode, arg_type) | |
3312 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3313 | { | |
3314 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3315 | { | |
3316 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3317 | unsigned long regval; | |
3318 | ||
3319 | /* Write the low word of the double to the even register(s). */ | |
3320 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3321 | if (mips_debug) | |
3322 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3323 | float_argreg, phex (regval, 4)); | |
3324 | write_register (float_argreg++, regval); | |
3325 | if (mips_debug) | |
3326 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3327 | argreg, phex (regval, 4)); | |
3328 | write_register (argreg++, regval); | |
3329 | ||
3330 | /* Write the high word of the double to the odd register(s). */ | |
3331 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3332 | if (mips_debug) | |
3333 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3334 | float_argreg, phex (regval, 4)); | |
3335 | write_register (float_argreg++, regval); | |
3336 | ||
3337 | if (mips_debug) | |
3338 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3339 | argreg, phex (regval, 4)); | |
3340 | write_register (argreg++, regval); | |
3341 | } | |
3342 | else | |
3343 | { | |
3344 | /* This is a floating point value that fits entirely | |
3345 | in a single register. */ | |
3346 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3347 | above to ensure that it is even register aligned. */ | |
3348 | LONGEST regval = extract_unsigned_integer (val, len); | |
3349 | if (mips_debug) | |
3350 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3351 | float_argreg, phex (regval, len)); | |
3352 | write_register (float_argreg++, regval); | |
3353 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3354 | registers for each argument. The below is (my | |
3355 | guess) to ensure that the corresponding integer | |
3356 | register has reserved the same space. */ | |
3357 | if (mips_debug) | |
3358 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3359 | argreg, phex (regval, len)); | |
3360 | write_register (argreg, regval); | |
3361 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3362 | } | |
3363 | /* Reserve space for the FP register. */ | |
5b03f266 | 3364 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3365 | } |
3366 | else | |
3367 | { | |
3368 | /* Copy the argument to general registers or the stack in | |
3369 | register-sized pieces. Large arguments are split between | |
3370 | registers and stack. */ | |
4246e332 AC |
3371 | /* Note: structs whose size is not a multiple of |
3372 | mips_regsize() are treated specially: Irix cc passes them | |
3373 | in registers where gcc sometimes puts them on the stack. | |
3374 | For maximum compatibility, we will put them in both | |
3375 | places. */ | |
46cac009 AC |
3376 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3377 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3378 | /* Structures should be aligned to eight bytes (even arg registers) | |
3379 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3380 | if (MIPS_SAVED_REGSIZE < 8 | |
3381 | && mips_type_needs_double_align (arg_type)) | |
3382 | { | |
3383 | if ((argreg & 1)) | |
3384 | argreg++; | |
3385 | } | |
3386 | /* Note: Floating-point values that didn't fit into an FP | |
3387 | register are only written to memory. */ | |
3388 | while (len > 0) | |
3389 | { | |
3390 | /* Remember if the argument was written to the stack. */ | |
3391 | int stack_used_p = 0; | |
3392 | int partial_len = | |
3393 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3394 | ||
3395 | if (mips_debug) | |
3396 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3397 | partial_len); | |
3398 | ||
3399 | /* Write this portion of the argument to the stack. */ | |
3400 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3401 | || odd_sized_struct | |
3402 | || fp_register_arg_p (typecode, arg_type)) | |
3403 | { | |
3404 | /* Should shorter than int integer values be | |
3405 | promoted to int before being stored? */ | |
3406 | int longword_offset = 0; | |
3407 | CORE_ADDR addr; | |
3408 | stack_used_p = 1; | |
3409 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3410 | { | |
3411 | if (MIPS_STACK_ARGSIZE == 8 && | |
3412 | (typecode == TYPE_CODE_INT || | |
3413 | typecode == TYPE_CODE_PTR || | |
3414 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3415 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3416 | } | |
3417 | ||
3418 | if (mips_debug) | |
3419 | { | |
3420 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3421 | paddr_nz (stack_offset)); | |
3422 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3423 | paddr_nz (longword_offset)); | |
3424 | } | |
3425 | ||
3426 | addr = sp + stack_offset + longword_offset; | |
3427 | ||
3428 | if (mips_debug) | |
3429 | { | |
3430 | int i; | |
3431 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3432 | paddr_nz (addr)); | |
3433 | for (i = 0; i < partial_len; i++) | |
3434 | { | |
3435 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3436 | val[i] & 0xff); | |
3437 | } | |
3438 | } | |
3439 | write_memory (addr, val, partial_len); | |
3440 | } | |
3441 | ||
3442 | /* Note!!! This is NOT an else clause. Odd sized | |
3443 | structs may go thru BOTH paths. Floating point | |
3444 | arguments will not. */ | |
3445 | /* Write this portion of the argument to a general | |
3446 | purpose register. */ | |
3447 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3448 | && !fp_register_arg_p (typecode, arg_type)) | |
3449 | { | |
3450 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3451 | /* Value may need to be sign extended, because |
3452 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
46cac009 AC |
3453 | |
3454 | /* A non-floating-point argument being passed in a | |
3455 | general register. If a struct or union, and if | |
3456 | the remaining length is smaller than the register | |
3457 | size, we have to adjust the register value on | |
3458 | big endian targets. | |
3459 | ||
3460 | It does not seem to be necessary to do the | |
3461 | same for integral types. | |
3462 | ||
3463 | Also don't do this adjustment on O64 binaries. | |
3464 | ||
3465 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3466 | outputting LE O32 with sizeof (struct) < | |
3467 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3468 | part of storing the argument in a register a | |
3469 | register (the left shift isn't generated when | |
3470 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3471 | is quite possible that this is GCC contradicting | |
3472 | the LE/O32 ABI, GDB has not been adjusted to | |
3473 | accommodate this. Either someone needs to | |
3474 | demonstrate that the LE/O32 ABI specifies such a | |
3475 | left shift OR this new ABI gets identified as | |
3476 | such and GDB gets tweaked accordingly. */ | |
3477 | ||
3478 | if (MIPS_SAVED_REGSIZE < 8 | |
3479 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3480 | && partial_len < MIPS_SAVED_REGSIZE | |
3481 | && (typecode == TYPE_CODE_STRUCT || | |
3482 | typecode == TYPE_CODE_UNION)) | |
3483 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3484 | TARGET_CHAR_BIT); | |
3485 | ||
3486 | if (mips_debug) | |
3487 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3488 | argreg, | |
3489 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3490 | write_register (argreg, regval); | |
3491 | argreg++; | |
3492 | ||
3493 | /* Prevent subsequent floating point arguments from | |
3494 | being passed in floating point registers. */ | |
3495 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3496 | } | |
3497 | ||
3498 | len -= partial_len; | |
3499 | val += partial_len; | |
3500 | ||
3501 | /* Compute the the offset into the stack at which we | |
3502 | will copy the next parameter. | |
3503 | ||
3504 | In older ABIs, the caller reserved space for | |
3505 | registers that contained arguments. This was loosely | |
3506 | refered to as their "home". Consequently, space is | |
3507 | always allocated. */ | |
3508 | ||
5b03f266 | 3509 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
46cac009 AC |
3510 | } |
3511 | } | |
3512 | if (mips_debug) | |
3513 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3514 | } | |
3515 | ||
310e9b6a AC |
3516 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3517 | ||
46cac009 AC |
3518 | /* Return adjusted stack pointer. */ |
3519 | return sp; | |
3520 | } | |
3521 | ||
25ab4790 | 3522 | /* O64 version of push_dummy_call. */ |
46cac009 AC |
3523 | |
3524 | static CORE_ADDR | |
25ab4790 AC |
3525 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
3526 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
3527 | struct value **args, CORE_ADDR sp, int struct_return, | |
3528 | CORE_ADDR struct_addr) | |
46cac009 AC |
3529 | { |
3530 | int argreg; | |
3531 | int float_argreg; | |
3532 | int argnum; | |
3533 | int len = 0; | |
3534 | int stack_offset = 0; | |
3535 | ||
25ab4790 AC |
3536 | /* For shared libraries, "t9" needs to point at the function |
3537 | address. */ | |
3538 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3539 | ||
3540 | /* Set the return address register to point to the entry point of | |
3541 | the program, where a breakpoint lies in wait. */ | |
3542 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3543 | ||
46cac009 AC |
3544 | /* First ensure that the stack and structure return address (if any) |
3545 | are properly aligned. The stack has to be at least 64-bit | |
3546 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3547 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3548 | aligned, so we round to this widest known alignment. */ | |
3549 | ||
5b03f266 AC |
3550 | sp = align_down (sp, 16); |
3551 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3552 | |
3553 | /* Now make space on the stack for the args. */ | |
3554 | for (argnum = 0; argnum < nargs; argnum++) | |
5b03f266 | 3555 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
46cac009 | 3556 | MIPS_STACK_ARGSIZE); |
5b03f266 | 3557 | sp -= align_up (len, 16); |
46cac009 AC |
3558 | |
3559 | if (mips_debug) | |
3560 | fprintf_unfiltered (gdb_stdlog, | |
5b03f266 AC |
3561 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3562 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3563 | |
3564 | /* Initialize the integer and float register pointers. */ | |
3565 | argreg = A0_REGNUM; | |
56cea623 | 3566 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3567 | |
3568 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3569 | if (struct_return) | |
3570 | { | |
3571 | if (mips_debug) | |
3572 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3573 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3574 | argreg, paddr_nz (struct_addr)); |
3575 | write_register (argreg++, struct_addr); | |
3576 | stack_offset += MIPS_STACK_ARGSIZE; | |
3577 | } | |
3578 | ||
3579 | /* Now load as many as possible of the first arguments into | |
3580 | registers, and push the rest onto the stack. Loop thru args | |
3581 | from first to last. */ | |
3582 | for (argnum = 0; argnum < nargs; argnum++) | |
3583 | { | |
3584 | char *val; | |
d9d9c31f | 3585 | char valbuf[MAX_REGISTER_SIZE]; |
46cac009 AC |
3586 | struct value *arg = args[argnum]; |
3587 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3588 | int len = TYPE_LENGTH (arg_type); | |
3589 | enum type_code typecode = TYPE_CODE (arg_type); | |
3590 | ||
3591 | if (mips_debug) | |
3592 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3593 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3594 | argnum + 1, len, (int) typecode); |
3595 | ||
3596 | val = (char *) VALUE_CONTENTS (arg); | |
3597 | ||
3598 | /* 32-bit ABIs always start floating point arguments in an | |
3599 | even-numbered floating point register. Round the FP register | |
3600 | up before the check to see if there are any FP registers | |
3601 | left. O32/O64 targets also pass the FP in the integer | |
3602 | registers so also round up normal registers. */ | |
3603 | if (!FP_REGISTER_DOUBLE | |
3604 | && fp_register_arg_p (typecode, arg_type)) | |
3605 | { | |
3606 | if ((float_argreg & 1)) | |
3607 | float_argreg++; | |
3608 | } | |
3609 | ||
3610 | /* Floating point arguments passed in registers have to be | |
3611 | treated specially. On 32-bit architectures, doubles | |
3612 | are passed in register pairs; the even register gets | |
3613 | the low word, and the odd register gets the high word. | |
3614 | On O32/O64, the first two floating point arguments are | |
3615 | also copied to general registers, because MIPS16 functions | |
3616 | don't use float registers for arguments. This duplication of | |
3617 | arguments in general registers can't hurt non-MIPS16 functions | |
3618 | because those registers are normally skipped. */ | |
3619 | ||
3620 | if (fp_register_arg_p (typecode, arg_type) | |
3621 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3622 | { | |
3623 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3624 | { | |
3625 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3626 | unsigned long regval; | |
3627 | ||
3628 | /* Write the low word of the double to the even register(s). */ | |
3629 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3630 | if (mips_debug) | |
3631 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3632 | float_argreg, phex (regval, 4)); | |
3633 | write_register (float_argreg++, regval); | |
3634 | if (mips_debug) | |
3635 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3636 | argreg, phex (regval, 4)); | |
3637 | write_register (argreg++, regval); | |
3638 | ||
3639 | /* Write the high word of the double to the odd register(s). */ | |
3640 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3641 | if (mips_debug) | |
3642 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3643 | float_argreg, phex (regval, 4)); | |
3644 | write_register (float_argreg++, regval); | |
3645 | ||
3646 | if (mips_debug) | |
3647 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3648 | argreg, phex (regval, 4)); | |
3649 | write_register (argreg++, regval); | |
3650 | } | |
3651 | else | |
3652 | { | |
3653 | /* This is a floating point value that fits entirely | |
3654 | in a single register. */ | |
3655 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3656 | above to ensure that it is even register aligned. */ | |
3657 | LONGEST regval = extract_unsigned_integer (val, len); | |
3658 | if (mips_debug) | |
3659 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3660 | float_argreg, phex (regval, len)); | |
3661 | write_register (float_argreg++, regval); | |
3662 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3663 | registers for each argument. The below is (my | |
3664 | guess) to ensure that the corresponding integer | |
3665 | register has reserved the same space. */ | |
3666 | if (mips_debug) | |
3667 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3668 | argreg, phex (regval, len)); | |
3669 | write_register (argreg, regval); | |
3670 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3671 | } | |
3672 | /* Reserve space for the FP register. */ | |
5b03f266 | 3673 | stack_offset += align_up (len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3674 | } |
3675 | else | |
3676 | { | |
3677 | /* Copy the argument to general registers or the stack in | |
3678 | register-sized pieces. Large arguments are split between | |
3679 | registers and stack. */ | |
4246e332 AC |
3680 | /* Note: structs whose size is not a multiple of |
3681 | mips_regsize() are treated specially: Irix cc passes them | |
3682 | in registers where gcc sometimes puts them on the stack. | |
3683 | For maximum compatibility, we will put them in both | |
3684 | places. */ | |
ebafbe83 MS |
3685 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
3686 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3687 | /* Structures should be aligned to eight bytes (even arg registers) | |
3688 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3689 | if (MIPS_SAVED_REGSIZE < 8 | |
3690 | && mips_type_needs_double_align (arg_type)) | |
3691 | { | |
3692 | if ((argreg & 1)) | |
3693 | argreg++; | |
3694 | } | |
3695 | /* Note: Floating-point values that didn't fit into an FP | |
3696 | register are only written to memory. */ | |
3697 | while (len > 0) | |
3698 | { | |
3699 | /* Remember if the argument was written to the stack. */ | |
3700 | int stack_used_p = 0; | |
3701 | int partial_len = | |
3702 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3703 | ||
3704 | if (mips_debug) | |
3705 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3706 | partial_len); | |
3707 | ||
3708 | /* Write this portion of the argument to the stack. */ | |
3709 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3710 | || odd_sized_struct | |
3711 | || fp_register_arg_p (typecode, arg_type)) | |
3712 | { | |
3713 | /* Should shorter than int integer values be | |
3714 | promoted to int before being stored? */ | |
3715 | int longword_offset = 0; | |
3716 | CORE_ADDR addr; | |
3717 | stack_used_p = 1; | |
3718 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3719 | { | |
3720 | if (MIPS_STACK_ARGSIZE == 8 && | |
3721 | (typecode == TYPE_CODE_INT || | |
3722 | typecode == TYPE_CODE_PTR || | |
3723 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3724 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3725 | } | |
3726 | ||
3727 | if (mips_debug) | |
3728 | { | |
3729 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3730 | paddr_nz (stack_offset)); | |
3731 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3732 | paddr_nz (longword_offset)); | |
3733 | } | |
3734 | ||
3735 | addr = sp + stack_offset + longword_offset; | |
3736 | ||
3737 | if (mips_debug) | |
3738 | { | |
3739 | int i; | |
3740 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3741 | paddr_nz (addr)); | |
3742 | for (i = 0; i < partial_len; i++) | |
3743 | { | |
3744 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3745 | val[i] & 0xff); | |
3746 | } | |
3747 | } | |
3748 | write_memory (addr, val, partial_len); | |
3749 | } | |
3750 | ||
3751 | /* Note!!! This is NOT an else clause. Odd sized | |
3752 | structs may go thru BOTH paths. Floating point | |
3753 | arguments will not. */ | |
3754 | /* Write this portion of the argument to a general | |
3755 | purpose register. */ | |
3756 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3757 | && !fp_register_arg_p (typecode, arg_type)) | |
3758 | { | |
3759 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 AC |
3760 | /* Value may need to be sign extended, because |
3761 | mips_regsize() != MIPS_SAVED_REGSIZE. */ | |
ebafbe83 MS |
3762 | |
3763 | /* A non-floating-point argument being passed in a | |
3764 | general register. If a struct or union, and if | |
3765 | the remaining length is smaller than the register | |
3766 | size, we have to adjust the register value on | |
3767 | big endian targets. | |
3768 | ||
3769 | It does not seem to be necessary to do the | |
3770 | same for integral types. | |
3771 | ||
3772 | Also don't do this adjustment on O64 binaries. | |
3773 | ||
3774 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3775 | outputting LE O32 with sizeof (struct) < | |
3776 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3777 | part of storing the argument in a register a | |
3778 | register (the left shift isn't generated when | |
3779 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3780 | is quite possible that this is GCC contradicting | |
3781 | the LE/O32 ABI, GDB has not been adjusted to | |
3782 | accommodate this. Either someone needs to | |
3783 | demonstrate that the LE/O32 ABI specifies such a | |
3784 | left shift OR this new ABI gets identified as | |
3785 | such and GDB gets tweaked accordingly. */ | |
3786 | ||
3787 | if (MIPS_SAVED_REGSIZE < 8 | |
3788 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3789 | && partial_len < MIPS_SAVED_REGSIZE | |
3790 | && (typecode == TYPE_CODE_STRUCT || | |
3791 | typecode == TYPE_CODE_UNION)) | |
3792 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3793 | TARGET_CHAR_BIT); | |
3794 | ||
3795 | if (mips_debug) | |
3796 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3797 | argreg, | |
3798 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3799 | write_register (argreg, regval); | |
3800 | argreg++; | |
3801 | ||
3802 | /* Prevent subsequent floating point arguments from | |
3803 | being passed in floating point registers. */ | |
3804 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3805 | } | |
3806 | ||
3807 | len -= partial_len; | |
3808 | val += partial_len; | |
3809 | ||
3810 | /* Compute the the offset into the stack at which we | |
3811 | will copy the next parameter. | |
3812 | ||
3813 | In older ABIs, the caller reserved space for | |
3814 | registers that contained arguments. This was loosely | |
3815 | refered to as their "home". Consequently, space is | |
3816 | always allocated. */ | |
3817 | ||
5b03f266 | 3818 | stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE); |
ebafbe83 MS |
3819 | } |
3820 | } | |
3821 | if (mips_debug) | |
3822 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3823 | } | |
3824 | ||
310e9b6a AC |
3825 | regcache_cooked_write_signed (regcache, SP_REGNUM, sp); |
3826 | ||
ebafbe83 MS |
3827 | /* Return adjusted stack pointer. */ |
3828 | return sp; | |
3829 | } | |
3830 | ||
f7ab6ec6 | 3831 | static void |
acdb74a0 | 3832 | mips_pop_frame (void) |
c906108c | 3833 | { |
52f0bd74 | 3834 | int regnum; |
c906108c | 3835 | struct frame_info *frame = get_current_frame (); |
c193f6ac | 3836 | CORE_ADDR new_sp = get_frame_base (frame); |
e227b13c | 3837 | mips_extra_func_info_t proc_desc; |
c906108c | 3838 | |
50abf9e5 | 3839 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)) |
cedea778 AC |
3840 | { |
3841 | generic_pop_dummy_frame (); | |
3842 | flush_cached_frames (); | |
3843 | return; | |
3844 | } | |
3845 | ||
e227b13c | 3846 | proc_desc = get_frame_extra_info (frame)->proc_desc; |
8bedc050 | 3847 | write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
e0f7ec59 | 3848 | mips_find_saved_regs (frame); |
c906108c | 3849 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
21f87145 | 3850 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
1b1d3794 | 3851 | && deprecated_get_frame_saved_regs (frame)[regnum]) |
21f87145 MS |
3852 | { |
3853 | /* Floating point registers must not be sign extended, | |
3854 | in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ | |
3855 | ||
56cea623 | 3856 | if (mips_regnum (current_gdbarch)->fp0 <= regnum && regnum < mips_regnum (current_gdbarch)->fp0 + 32) |
21f87145 | 3857 | write_register (regnum, |
1b1d3794 | 3858 | read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3859 | MIPS_SAVED_REGSIZE)); |
3860 | else | |
3861 | write_register (regnum, | |
1b1d3794 | 3862 | read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], |
21f87145 MS |
3863 | MIPS_SAVED_REGSIZE)); |
3864 | } | |
757a7cc6 | 3865 | |
c906108c SS |
3866 | write_register (SP_REGNUM, new_sp); |
3867 | flush_cached_frames (); | |
3868 | ||
c5aa993b | 3869 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3870 | { |
3871 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3872 | ||
3873 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3874 | pi_ptr != NULL; | |
3875 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3876 | { | |
3877 | if (&pi_ptr->info == proc_desc) | |
3878 | break; | |
3879 | } | |
3880 | ||
3881 | if (pi_ptr == NULL) | |
3882 | error ("Can't locate dummy extra frame info\n"); | |
3883 | ||
3884 | if (prev_ptr != NULL) | |
3885 | prev_ptr->next = pi_ptr->next; | |
3886 | else | |
3887 | linked_proc_desc_table = pi_ptr->next; | |
3888 | ||
b8c9b27d | 3889 | xfree (pi_ptr); |
c906108c | 3890 | |
56cea623 | 3891 | write_register (mips_regnum (current_gdbarch)->hi, |
c5aa993b | 3892 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3893 | MIPS_SAVED_REGSIZE)); |
56cea623 | 3894 | write_register (mips_regnum (current_gdbarch)->lo, |
c5aa993b | 3895 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3896 | MIPS_SAVED_REGSIZE)); |
c906108c | 3897 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
56cea623 | 3898 | write_register (mips_regnum (current_gdbarch)->fp_control_status, |
c5aa993b | 3899 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3900 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3901 | } |
3902 | } | |
3903 | ||
dd824b04 DJ |
3904 | /* Floating point register management. |
3905 | ||
3906 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3907 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3908 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3909 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3910 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3911 | double precision floats into two 32-bit chunks and store them in | |
3912 | consecutive fp regs. To display 64-bit floats stored in this | |
3913 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3914 | Throw in user-configurable endianness and you have a real mess. | |
3915 | ||
3916 | The way this works is: | |
3917 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3918 | double-precision value will be split across two logical registers. | |
3919 | The lower-numbered logical register will hold the low-order bits, | |
3920 | regardless of the processor's endianness. | |
3921 | - If we are on a 64-bit processor, and we are looking for a | |
3922 | single-precision value, it will be in the low ordered bits | |
3923 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3924 | save slot in memory. | |
3925 | - If we are in 64-bit mode, everything is straightforward. | |
3926 | ||
3927 | Note that this code only deals with "live" registers at the top of the | |
3928 | stack. We will attempt to deal with saved registers later, when | |
3929 | the raw/cooked register interface is in place. (We need a general | |
3930 | interface that can deal with dynamic saved register sizes -- fp | |
3931 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3932 | and below). */ | |
3933 | ||
67b2c998 DJ |
3934 | static struct type * |
3935 | mips_float_register_type (void) | |
3936 | { | |
361d1df0 | 3937 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3938 | return builtin_type_ieee_single_big; |
3939 | else | |
3940 | return builtin_type_ieee_single_little; | |
3941 | } | |
3942 | ||
3943 | static struct type * | |
3944 | mips_double_register_type (void) | |
3945 | { | |
361d1df0 | 3946 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3947 | return builtin_type_ieee_double_big; |
3948 | else | |
3949 | return builtin_type_ieee_double_little; | |
3950 | } | |
3951 | ||
dd824b04 DJ |
3952 | /* Copy a 32-bit single-precision value from the current frame |
3953 | into rare_buffer. */ | |
3954 | ||
3955 | static void | |
e11c53d2 AC |
3956 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3957 | char *rare_buffer) | |
dd824b04 | 3958 | { |
719ec221 | 3959 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3960 | char *raw_buffer = alloca (raw_size); |
3961 | ||
e11c53d2 | 3962 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3963 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3964 | if (raw_size == 8) | |
3965 | { | |
3966 | /* We have a 64-bit value for this register. Find the low-order | |
3967 | 32 bits. */ | |
3968 | int offset; | |
3969 | ||
3970 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3971 | offset = 4; | |
3972 | else | |
3973 | offset = 0; | |
3974 | ||
3975 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3976 | } | |
3977 | else | |
3978 | { | |
3979 | memcpy (rare_buffer, raw_buffer, 4); | |
3980 | } | |
3981 | } | |
3982 | ||
3983 | /* Copy a 64-bit double-precision value from the current frame into | |
3984 | rare_buffer. This may include getting half of it from the next | |
3985 | register. */ | |
3986 | ||
3987 | static void | |
e11c53d2 AC |
3988 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3989 | char *rare_buffer) | |
dd824b04 | 3990 | { |
719ec221 | 3991 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3992 | |
3993 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3994 | { | |
3995 | /* We have a 64-bit value for this register, and we should use | |
3996 | all 64 bits. */ | |
e11c53d2 | 3997 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
3998 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3999 | } | |
4000 | else | |
4001 | { | |
56cea623 | 4002 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4003 | internal_error (__FILE__, __LINE__, |
4004 | "mips_read_fp_register_double: bad access to " | |
4005 | "odd-numbered FP register"); | |
4006 | ||
4007 | /* mips_read_fp_register_single will find the correct 32 bits from | |
4008 | each register. */ | |
4009 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4010 | { | |
e11c53d2 AC |
4011 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4012 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4013 | } |
361d1df0 | 4014 | else |
dd824b04 | 4015 | { |
e11c53d2 AC |
4016 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4017 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4018 | } |
4019 | } | |
4020 | } | |
4021 | ||
c906108c | 4022 | static void |
e11c53d2 AC |
4023 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4024 | int regnum) | |
c5aa993b | 4025 | { /* do values for FP (float) regs */ |
dd824b04 | 4026 | char *raw_buffer; |
c906108c | 4027 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
f0ef6b29 | 4028 | int inv1, inv2, namelen; |
c5aa993b | 4029 | |
56cea623 | 4030 | raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0)); |
c906108c | 4031 | |
e11c53d2 AC |
4032 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4033 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4034 | ""); | |
f0ef6b29 | 4035 | |
719ec221 | 4036 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4037 | { |
f0ef6b29 KB |
4038 | /* 4-byte registers: Print hex and floating. Also print even |
4039 | numbered registers as doubles. */ | |
e11c53d2 | 4040 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4041 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4042 | |
e11c53d2 | 4043 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file); |
dd824b04 | 4044 | |
e11c53d2 | 4045 | fprintf_filtered (file, " flt: "); |
1adad886 | 4046 | if (inv1) |
e11c53d2 | 4047 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4048 | else |
e11c53d2 | 4049 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4050 | |
f0ef6b29 KB |
4051 | if (regnum % 2 == 0) |
4052 | { | |
e11c53d2 | 4053 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4054 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
4055 | &inv2); | |
1adad886 | 4056 | |
e11c53d2 | 4057 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4058 | if (inv2) |
e11c53d2 | 4059 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4060 | else |
e11c53d2 | 4061 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4062 | } |
c906108c SS |
4063 | } |
4064 | else | |
dd824b04 | 4065 | { |
f0ef6b29 | 4066 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4067 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4068 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4069 | |
e11c53d2 | 4070 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4071 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4072 | ||
361d1df0 | 4073 | |
e11c53d2 | 4074 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file); |
f0ef6b29 | 4075 | |
e11c53d2 | 4076 | fprintf_filtered (file, " flt: "); |
1adad886 | 4077 | if (inv1) |
e11c53d2 | 4078 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4079 | else |
e11c53d2 | 4080 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4081 | |
e11c53d2 | 4082 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4083 | if (inv2) |
e11c53d2 | 4084 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4085 | else |
e11c53d2 | 4086 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4087 | } |
4088 | } | |
4089 | ||
4090 | static void | |
e11c53d2 AC |
4091 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4092 | int regnum, int all) | |
f0ef6b29 | 4093 | { |
a4b8ebc8 | 4094 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4095 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4096 | int offset; |
1adad886 | 4097 | |
a4b8ebc8 | 4098 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4099 | { |
e11c53d2 | 4100 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4101 | return; |
4102 | } | |
4103 | ||
4104 | /* Get the data in raw format. */ | |
e11c53d2 | 4105 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4106 | { |
e11c53d2 | 4107 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4108 | return; |
c906108c | 4109 | } |
f0ef6b29 | 4110 | |
e11c53d2 | 4111 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4112 | |
4113 | /* The problem with printing numeric register names (r26, etc.) is that | |
4114 | the user can't use them on input. Probably the best solution is to | |
4115 | fix it so that either the numeric or the funky (a2, etc.) names | |
4116 | are accepted on input. */ | |
4117 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4118 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4119 | else |
e11c53d2 | 4120 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4121 | |
4122 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
719ec221 | 4123 | offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
f0ef6b29 KB |
4124 | else |
4125 | offset = 0; | |
4126 | ||
a4b8ebc8 | 4127 | print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum), |
e11c53d2 | 4128 | 'x', 0, file); |
c906108c SS |
4129 | } |
4130 | ||
f0ef6b29 KB |
4131 | /* Replacement for generic do_registers_info. |
4132 | Print regs in pretty columns. */ | |
4133 | ||
4134 | static int | |
e11c53d2 AC |
4135 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4136 | int regnum) | |
f0ef6b29 | 4137 | { |
e11c53d2 AC |
4138 | fprintf_filtered (file, " "); |
4139 | mips_print_fp_register (file, frame, regnum); | |
4140 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4141 | return regnum + 1; |
4142 | } | |
4143 | ||
4144 | ||
c906108c SS |
4145 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4146 | ||
4147 | static int | |
e11c53d2 | 4148 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4149 | int start_regnum) |
c906108c | 4150 | { |
a4b8ebc8 | 4151 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4152 | /* do values for GP (int) regs */ |
d9d9c31f | 4153 | char raw_buffer[MAX_REGISTER_SIZE]; |
4246e332 | 4154 | int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4155 | int col, byte; |
a4b8ebc8 | 4156 | int regnum; |
c906108c SS |
4157 | |
4158 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4159 | fprintf_filtered (file, " "); |
a4b8ebc8 AC |
4160 | for (col = 0, regnum = start_regnum; |
4161 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4162 | regnum++) | |
c906108c SS |
4163 | { |
4164 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4165 | continue; /* unused register */ |
a4b8ebc8 | 4166 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4167 | break; /* end the row: reached FP register */ |
4246e332 | 4168 | fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4169 | REGISTER_NAME (regnum)); |
c906108c SS |
4170 | col++; |
4171 | } | |
a4b8ebc8 | 4172 | /* print the R0 to R31 names */ |
20e6603c AC |
4173 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4174 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4175 | else | |
4176 | fprintf_filtered (file, "\n "); | |
c906108c | 4177 | |
c906108c | 4178 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 AC |
4179 | for (col = 0, regnum = start_regnum; |
4180 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; | |
4181 | regnum++) | |
c906108c SS |
4182 | { |
4183 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4184 | continue; /* unused register */ |
a4b8ebc8 | 4185 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c5aa993b | 4186 | break; /* end row: reached FP register */ |
c906108c | 4187 | /* OK: get the data in raw format. */ |
e11c53d2 | 4188 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4189 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4190 | /* pad small registers */ | |
4246e332 AC |
4191 | for (byte = 0; |
4192 | byte < (mips_regsize (current_gdbarch) | |
c73e8f27 | 4193 | - register_size (current_gdbarch, regnum)); |
4246e332 | 4194 | byte++) |
c906108c SS |
4195 | printf_filtered (" "); |
4196 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4197 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
719ec221 AC |
4198 | for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum); |
4199 | byte < register_size (current_gdbarch, regnum); | |
43e526b9 | 4200 | byte++) |
e11c53d2 | 4201 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4202 | else |
c73e8f27 | 4203 | for (byte = register_size (current_gdbarch, regnum) - 1; |
43e526b9 JM |
4204 | byte >= 0; |
4205 | byte--) | |
e11c53d2 AC |
4206 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4207 | fprintf_filtered (file, " "); | |
c906108c SS |
4208 | col++; |
4209 | } | |
c5aa993b | 4210 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4211 | fprintf_filtered (file, "\n"); |
c906108c SS |
4212 | |
4213 | return regnum; | |
4214 | } | |
4215 | ||
4216 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4217 | ||
bf1f5b4c | 4218 | static void |
e11c53d2 AC |
4219 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4220 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4221 | { |
c5aa993b | 4222 | if (regnum != -1) /* do one specified register */ |
c906108c | 4223 | { |
a4b8ebc8 | 4224 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4225 | if (*(REGISTER_NAME (regnum)) == '\0') |
4226 | error ("Not a valid register for the current processor type"); | |
4227 | ||
e11c53d2 AC |
4228 | mips_print_register (file, frame, regnum, 0); |
4229 | fprintf_filtered (file, "\n"); | |
c906108c | 4230 | } |
c5aa993b JM |
4231 | else |
4232 | /* do all (or most) registers */ | |
c906108c | 4233 | { |
a4b8ebc8 AC |
4234 | regnum = NUM_REGS; |
4235 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4236 | { |
a4b8ebc8 | 4237 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
e11c53d2 AC |
4238 | { |
4239 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4240 | regnum = print_fp_register_row (file, frame, regnum); | |
4241 | else | |
4242 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4243 | } | |
c906108c | 4244 | else |
e11c53d2 | 4245 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4246 | } |
4247 | } | |
4248 | } | |
4249 | ||
c906108c SS |
4250 | /* Is this a branch with a delay slot? */ |
4251 | ||
a14ed312 | 4252 | static int is_delayed (unsigned long); |
c906108c SS |
4253 | |
4254 | static int | |
acdb74a0 | 4255 | is_delayed (unsigned long insn) |
c906108c SS |
4256 | { |
4257 | int i; | |
4258 | for (i = 0; i < NUMOPCODES; ++i) | |
4259 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4260 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4261 | break; | |
4262 | return (i < NUMOPCODES | |
4263 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4264 | | INSN_COND_BRANCH_DELAY | |
4265 | | INSN_COND_BRANCH_LIKELY))); | |
4266 | } | |
4267 | ||
4268 | int | |
acdb74a0 | 4269 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
4270 | { |
4271 | char buf[MIPS_INSTLEN]; | |
4272 | ||
4273 | /* There is no branch delay slot on MIPS16. */ | |
4274 | if (pc_is_mips16 (pc)) | |
4275 | return 0; | |
4276 | ||
4277 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
4278 | /* If error reading memory, guess that it is not a delayed branch. */ | |
4279 | return 0; | |
c5aa993b | 4280 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
4281 | } |
4282 | ||
4283 | ||
74da7425 AC |
4284 | /* Given PC at the function's start address, attempt to find the |
4285 | prologue end using SAL information. Return zero if the skip fails. | |
4286 | ||
4287 | A non-optimized prologue traditionally has one SAL for the function | |
4288 | and a second for the function body. A single line function has | |
4289 | them both pointing at the same line. | |
4290 | ||
4291 | An optimized prologue is similar but the prologue may contain | |
4292 | instructions (SALs) from the instruction body. Need to skip those | |
4293 | while not getting into the function body. | |
4294 | ||
4295 | The functions end point and an increasing SAL line are used as | |
4296 | indicators of the prologue's endpoint. | |
4297 | ||
4298 | This code is based on the function refine_prologue_limit (versions | |
4299 | found in both ia64 and ppc). */ | |
4300 | ||
4301 | static CORE_ADDR | |
4302 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
4303 | { | |
4304 | struct symtab_and_line prologue_sal; | |
4305 | CORE_ADDR start_pc; | |
4306 | CORE_ADDR end_pc; | |
4307 | ||
4308 | /* Get an initial range for the function. */ | |
4309 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
4310 | start_pc += FUNCTION_START_OFFSET; | |
4311 | ||
4312 | prologue_sal = find_pc_line (start_pc, 0); | |
4313 | if (prologue_sal.line != 0) | |
4314 | { | |
4315 | while (prologue_sal.end < end_pc) | |
4316 | { | |
4317 | struct symtab_and_line sal; | |
4318 | ||
4319 | sal = find_pc_line (prologue_sal.end, 0); | |
4320 | if (sal.line == 0) | |
4321 | break; | |
4322 | /* Assume that a consecutive SAL for the same (or larger) | |
4323 | line mark the prologue -> body transition. */ | |
4324 | if (sal.line >= prologue_sal.line) | |
4325 | break; | |
4326 | /* The case in which compiler's optimizer/scheduler has | |
4327 | moved instructions into the prologue. We look ahead in | |
4328 | the function looking for address ranges whose | |
4329 | corresponding line number is less the first one that we | |
4330 | found for the function. This is more conservative then | |
4331 | refine_prologue_limit which scans a large number of SALs | |
4332 | looking for any in the prologue */ | |
4333 | prologue_sal = sal; | |
4334 | } | |
4335 | } | |
4336 | return prologue_sal.end; | |
4337 | } | |
4338 | ||
c906108c SS |
4339 | /* Skip the PC past function prologue instructions (32-bit version). |
4340 | This is a helper function for mips_skip_prologue. */ | |
4341 | ||
4342 | static CORE_ADDR | |
f7b9e9fc | 4343 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 4344 | { |
c5aa993b JM |
4345 | t_inst inst; |
4346 | CORE_ADDR end_pc; | |
4347 | int seen_sp_adjust = 0; | |
4348 | int load_immediate_bytes = 0; | |
4349 | ||
74da7425 AC |
4350 | /* Find an upper bound on the prologue. */ |
4351 | end_pc = skip_prologue_using_sal (pc); | |
4352 | if (end_pc == 0) | |
4353 | end_pc = pc + 100; /* Magic. */ | |
4354 | ||
c5aa993b JM |
4355 | /* Skip the typical prologue instructions. These are the stack adjustment |
4356 | instruction and the instructions that save registers on the stack | |
4357 | or in the gcc frame. */ | |
74da7425 | 4358 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
4359 | { |
4360 | unsigned long high_word; | |
c906108c | 4361 | |
c5aa993b JM |
4362 | inst = mips_fetch_instruction (pc); |
4363 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 4364 | |
c5aa993b JM |
4365 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
4366 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
4367 | seen_sp_adjust = 1; | |
4368 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
4369 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
4370 | seen_sp_adjust = 1; | |
4371 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
4372 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
4373 | && (inst & 0x001F0000)) /* reg != $zero */ | |
4374 | continue; | |
4375 | ||
4376 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
4377 | continue; | |
4378 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
4379 | /* sx reg,n($s8) */ | |
4380 | continue; /* reg != $zero */ | |
4381 | ||
4382 | /* move $s8,$sp. With different versions of gas this will be either | |
4383 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
4384 | Accept any one of these. */ | |
4385 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
4386 | continue; | |
4387 | ||
4388 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
4389 | continue; | |
4390 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
4391 | continue; | |
4392 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
4393 | continue; | |
4394 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
4395 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
4396 | continue; | |
4397 | /* The following instructions load $at or $t0 with an immediate | |
4398 | value in preparation for a stack adjustment via | |
4399 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
4400 | a local variable, so we accept them only before a stack adjustment | |
4401 | instruction was seen. */ | |
4402 | else if (!seen_sp_adjust) | |
4403 | { | |
4404 | if (high_word == 0x3c01 || /* lui $at,n */ | |
4405 | high_word == 0x3c08) /* lui $t0,n */ | |
4406 | { | |
4407 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4408 | continue; | |
4409 | } | |
4410 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
4411 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
4412 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
4413 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
4414 | { | |
4415 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
4416 | continue; | |
4417 | } | |
4418 | else | |
4419 | break; | |
4420 | } | |
4421 | else | |
4422 | break; | |
c906108c SS |
4423 | } |
4424 | ||
c5aa993b JM |
4425 | /* In a frameless function, we might have incorrectly |
4426 | skipped some load immediate instructions. Undo the skipping | |
4427 | if the load immediate was not followed by a stack adjustment. */ | |
4428 | if (load_immediate_bytes && !seen_sp_adjust) | |
4429 | pc -= load_immediate_bytes; | |
4430 | return pc; | |
c906108c SS |
4431 | } |
4432 | ||
4433 | /* Skip the PC past function prologue instructions (16-bit version). | |
4434 | This is a helper function for mips_skip_prologue. */ | |
4435 | ||
4436 | static CORE_ADDR | |
f7b9e9fc | 4437 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 4438 | { |
c5aa993b JM |
4439 | CORE_ADDR end_pc; |
4440 | int extend_bytes = 0; | |
4441 | int prev_extend_bytes; | |
c906108c | 4442 | |
c5aa993b JM |
4443 | /* Table of instructions likely to be found in a function prologue. */ |
4444 | static struct | |
c906108c SS |
4445 | { |
4446 | unsigned short inst; | |
4447 | unsigned short mask; | |
c5aa993b JM |
4448 | } |
4449 | table[] = | |
4450 | { | |
c906108c | 4451 | { |
c5aa993b JM |
4452 | 0x6300, 0xff00 |
4453 | } | |
4454 | , /* addiu $sp,offset */ | |
4455 | { | |
4456 | 0xfb00, 0xff00 | |
4457 | } | |
4458 | , /* daddiu $sp,offset */ | |
4459 | { | |
4460 | 0xd000, 0xf800 | |
4461 | } | |
4462 | , /* sw reg,n($sp) */ | |
4463 | { | |
4464 | 0xf900, 0xff00 | |
4465 | } | |
4466 | , /* sd reg,n($sp) */ | |
4467 | { | |
4468 | 0x6200, 0xff00 | |
4469 | } | |
4470 | , /* sw $ra,n($sp) */ | |
4471 | { | |
4472 | 0xfa00, 0xff00 | |
4473 | } | |
4474 | , /* sd $ra,n($sp) */ | |
4475 | { | |
4476 | 0x673d, 0xffff | |
4477 | } | |
4478 | , /* move $s1,sp */ | |
4479 | { | |
4480 | 0xd980, 0xff80 | |
4481 | } | |
4482 | , /* sw $a0-$a3,n($s1) */ | |
4483 | { | |
4484 | 0x6704, 0xff1c | |
4485 | } | |
4486 | , /* move reg,$a0-$a3 */ | |
4487 | { | |
4488 | 0xe809, 0xf81f | |
4489 | } | |
4490 | , /* entry pseudo-op */ | |
4491 | { | |
4492 | 0x0100, 0xff00 | |
4493 | } | |
4494 | , /* addiu $s1,$sp,n */ | |
4495 | { | |
4496 | 0, 0 | |
4497 | } /* end of table marker */ | |
4498 | }; | |
4499 | ||
74da7425 AC |
4500 | /* Find an upper bound on the prologue. */ |
4501 | end_pc = skip_prologue_using_sal (pc); | |
4502 | if (end_pc == 0) | |
4503 | end_pc = pc + 100; /* Magic. */ | |
4504 | ||
c5aa993b JM |
4505 | /* Skip the typical prologue instructions. These are the stack adjustment |
4506 | instruction and the instructions that save registers on the stack | |
4507 | or in the gcc frame. */ | |
74da7425 | 4508 | for (; pc < end_pc; pc += MIPS16_INSTLEN) |
c5aa993b JM |
4509 | { |
4510 | unsigned short inst; | |
4511 | int i; | |
c906108c | 4512 | |
c5aa993b | 4513 | inst = mips_fetch_instruction (pc); |
c906108c | 4514 | |
c5aa993b JM |
4515 | /* Normally we ignore an extend instruction. However, if it is |
4516 | not followed by a valid prologue instruction, we must adjust | |
4517 | the pc back over the extend so that it won't be considered | |
4518 | part of the prologue. */ | |
4519 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4520 | { | |
4521 | extend_bytes = MIPS16_INSTLEN; | |
4522 | continue; | |
4523 | } | |
4524 | prev_extend_bytes = extend_bytes; | |
4525 | extend_bytes = 0; | |
c906108c | 4526 | |
c5aa993b JM |
4527 | /* Check for other valid prologue instructions besides extend. */ |
4528 | for (i = 0; table[i].mask != 0; i++) | |
4529 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
4530 | break; | |
4531 | if (table[i].mask != 0) /* it was in table? */ | |
4532 | continue; /* ignore it */ | |
4533 | else | |
4534 | /* non-prologue */ | |
4535 | { | |
4536 | /* Return the current pc, adjusted backwards by 2 if | |
4537 | the previous instruction was an extend. */ | |
4538 | return pc - prev_extend_bytes; | |
4539 | } | |
c906108c SS |
4540 | } |
4541 | return pc; | |
4542 | } | |
4543 | ||
4544 | /* To skip prologues, I use this predicate. Returns either PC itself | |
4545 | if the code at PC does not look like a function prologue; otherwise | |
4546 | returns an address that (if we're lucky) follows the prologue. If | |
4547 | LENIENT, then we must skip everything which is involved in setting | |
4548 | up the frame (it's OK to skip more, just so long as we don't skip | |
4549 | anything which might clobber the registers which are being saved. | |
4550 | We must skip more in the case where part of the prologue is in the | |
4551 | delay slot of a non-prologue instruction). */ | |
4552 | ||
f7ab6ec6 | 4553 | static CORE_ADDR |
f7b9e9fc | 4554 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4555 | { |
4556 | /* See if we can determine the end of the prologue via the symbol table. | |
4557 | If so, then return either PC, or the PC after the prologue, whichever | |
4558 | is greater. */ | |
4559 | ||
4560 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4561 | ||
4562 | if (post_prologue_pc != 0) | |
4563 | return max (pc, post_prologue_pc); | |
4564 | ||
4565 | /* Can't determine prologue from the symbol table, need to examine | |
4566 | instructions. */ | |
4567 | ||
4568 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4569 | return mips16_skip_prologue (pc); |
c906108c | 4570 | else |
f7b9e9fc | 4571 | return mips32_skip_prologue (pc); |
c906108c | 4572 | } |
c906108c | 4573 | |
7a292a7a SS |
4574 | /* Determine how a return value is stored within the MIPS register |
4575 | file, given the return type `valtype'. */ | |
4576 | ||
4577 | struct return_value_word | |
4578 | { | |
4579 | int len; | |
4580 | int reg; | |
4581 | int reg_offset; | |
4582 | int buf_offset; | |
4583 | }; | |
4584 | ||
7a292a7a | 4585 | static void |
acdb74a0 AC |
4586 | return_value_location (struct type *valtype, |
4587 | struct return_value_word *hi, | |
4588 | struct return_value_word *lo) | |
7a292a7a SS |
4589 | { |
4590 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4591 | |
7a292a7a SS |
4592 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4593 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4594 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4595 | { | |
4596 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4597 | { | |
4598 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4599 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4600 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4601 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4602 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
56cea623 | 4603 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8) |
7a292a7a SS |
4604 | ? 4 : 0); |
4605 | hi->reg_offset = lo->reg_offset; | |
56cea623 AC |
4606 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; |
4607 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
7a292a7a SS |
4608 | lo->len = 4; |
4609 | hi->len = 4; | |
4610 | } | |
4611 | else | |
4612 | { | |
4613 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4614 | register. */ |
d7449b42 | 4615 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
56cea623 | 4616 | && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8 |
7a292a7a SS |
4617 | && len == 4) |
4618 | ? 4 : 0); | |
56cea623 | 4619 | lo->reg = mips_regnum (current_gdbarch)->fp0; |
7a292a7a SS |
4620 | lo->len = len; |
4621 | lo->buf_offset = 0; | |
4622 | hi->len = 0; | |
4623 | hi->reg_offset = 0; | |
4624 | hi->buf_offset = 0; | |
4625 | hi->reg = 0; | |
4626 | } | |
4627 | } | |
4628 | else | |
4629 | { | |
4630 | /* Locate a result possibly spread across two registers. */ | |
4631 | int regnum = 2; | |
4632 | lo->reg = regnum + 0; | |
4633 | hi->reg = regnum + 1; | |
d7449b42 | 4634 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4635 | && len < MIPS_SAVED_REGSIZE) |
4636 | { | |
bf1f5b4c MS |
4637 | /* "un-left-justify" the value in the low register */ |
4638 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
bcb0cc15 | 4639 | lo->len = len; |
bf1f5b4c | 4640 | hi->reg_offset = 0; |
7a292a7a SS |
4641 | hi->len = 0; |
4642 | } | |
d7449b42 | 4643 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4644 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4645 | && len < MIPS_SAVED_REGSIZE * 2 | |
4646 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4647 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4648 | { | |
4649 | /* "un-left-justify" the value spread across two registers. */ | |
4650 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4651 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4652 | hi->reg_offset = 0; | |
4653 | hi->len = len - lo->len; | |
4654 | } | |
4655 | else | |
4656 | { | |
4657 | /* Only perform a partial copy of the second register. */ | |
4658 | lo->reg_offset = 0; | |
4659 | hi->reg_offset = 0; | |
4660 | if (len > MIPS_SAVED_REGSIZE) | |
4661 | { | |
4662 | lo->len = MIPS_SAVED_REGSIZE; | |
4663 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4664 | } | |
4665 | else | |
4666 | { | |
4667 | lo->len = len; | |
4668 | hi->len = 0; | |
4669 | } | |
4670 | } | |
d7449b42 | 4671 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
719ec221 | 4672 | && register_size (current_gdbarch, regnum) == 8 |
7a292a7a SS |
4673 | && MIPS_SAVED_REGSIZE == 4) |
4674 | { | |
4675 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4676 | of the register is being used */ |
7a292a7a SS |
4677 | lo->reg_offset += 4; |
4678 | hi->reg_offset += 4; | |
4679 | } | |
4680 | lo->buf_offset = 0; | |
4681 | hi->buf_offset = lo->len; | |
4682 | } | |
4683 | } | |
4684 | ||
4685 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4686 | copy its value into `valbuf'. */ | |
4687 | ||
46cac009 AC |
4688 | static void |
4689 | mips_eabi_extract_return_value (struct type *valtype, | |
b8b527c5 | 4690 | char regbuf[], |
46cac009 AC |
4691 | char *valbuf) |
4692 | { | |
4693 | struct return_value_word lo; | |
4694 | struct return_value_word hi; | |
4695 | return_value_location (valtype, &hi, &lo); | |
4696 | ||
4697 | memcpy (valbuf + lo.buf_offset, | |
78c63a3b | 4698 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset, |
46cac009 AC |
4699 | lo.len); |
4700 | ||
4701 | if (hi.len > 0) | |
4702 | memcpy (valbuf + hi.buf_offset, | |
78c63a3b | 4703 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset, |
46cac009 AC |
4704 | hi.len); |
4705 | } | |
4706 | ||
46cac009 AC |
4707 | static void |
4708 | mips_o64_extract_return_value (struct type *valtype, | |
b8b527c5 | 4709 | char regbuf[], |
46cac009 AC |
4710 | char *valbuf) |
4711 | { | |
4712 | struct return_value_word lo; | |
4713 | struct return_value_word hi; | |
4714 | return_value_location (valtype, &hi, &lo); | |
4715 | ||
4716 | memcpy (valbuf + lo.buf_offset, | |
78c63a3b | 4717 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset, |
46cac009 AC |
4718 | lo.len); |
4719 | ||
4720 | if (hi.len > 0) | |
4721 | memcpy (valbuf + hi.buf_offset, | |
78c63a3b | 4722 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset, |
46cac009 AC |
4723 | hi.len); |
4724 | } | |
4725 | ||
7a292a7a SS |
4726 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4727 | value into the appropriate register. */ | |
4728 | ||
46cac009 AC |
4729 | static void |
4730 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
4731 | { | |
d9d9c31f | 4732 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4733 | struct return_value_word lo; |
4734 | struct return_value_word hi; | |
4735 | return_value_location (valtype, &hi, &lo); | |
4736 | ||
4737 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4738 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4739 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4740 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4741 | |
4742 | if (hi.len > 0) | |
4743 | { | |
4744 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4745 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4746 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4747 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4748 | } |
4749 | } | |
4750 | ||
4751 | static void | |
cb1d2653 | 4752 | mips_o64_store_return_value (struct type *valtype, char *valbuf) |
46cac009 | 4753 | { |
d9d9c31f | 4754 | char raw_buffer[MAX_REGISTER_SIZE]; |
46cac009 AC |
4755 | struct return_value_word lo; |
4756 | struct return_value_word hi; | |
4757 | return_value_location (valtype, &hi, &lo); | |
4758 | ||
4759 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4760 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
62700349 | 4761 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer, |
719ec221 | 4762 | register_size (current_gdbarch, lo.reg)); |
46cac009 AC |
4763 | |
4764 | if (hi.len > 0) | |
4765 | { | |
4766 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4767 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
62700349 | 4768 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer, |
719ec221 | 4769 | register_size (current_gdbarch, hi.reg)); |
46cac009 AC |
4770 | } |
4771 | } | |
4772 | ||
cb1d2653 AC |
4773 | /* O32 ABI stuff. */ |
4774 | ||
29dfb2ac AC |
4775 | static enum return_value_convention |
4776 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4777 | struct regcache *regcache, | |
4778 | void *readbuf, const void *writebuf) | |
46cac009 | 4779 | { |
cb1d2653 | 4780 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4781 | |
4782 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT | |
4783 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4784 | || TYPE_CODE (type)== TYPE_CODE_ARRAY) | |
4785 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4786 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4787 | && TYPE_LENGTH (type) == 4 | |
4788 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
46cac009 | 4789 | { |
cb1d2653 AC |
4790 | /* A single-precision floating-point value. It fits in the |
4791 | least significant part of FP0. */ | |
4792 | if (mips_debug) | |
4793 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4794 | mips_xfer_register (regcache, |
4795 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4796 | TYPE_LENGTH (type), | |
4797 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4798 | return RETURN_VALUE_REGISTER_CONVENTION; | |
cb1d2653 AC |
4799 | } |
4800 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4801 | && TYPE_LENGTH (type) == 8 | |
4802 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4803 | { | |
a4b8ebc8 AC |
4804 | /* A double-precision floating-point value. The most |
4805 | significant part goes in FP1, and the least significant in | |
4806 | FP0. */ | |
cb1d2653 | 4807 | if (mips_debug) |
a4b8ebc8 | 4808 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
cb1d2653 AC |
4809 | switch (TARGET_BYTE_ORDER) |
4810 | { | |
4811 | case BFD_ENDIAN_LITTLE: | |
29dfb2ac AC |
4812 | mips_xfer_register (regcache, |
4813 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4814 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4815 | mips_xfer_register (regcache, | |
4816 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4817 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4818 | break; |
4819 | case BFD_ENDIAN_BIG: | |
29dfb2ac AC |
4820 | mips_xfer_register (regcache, |
4821 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1, | |
4822 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4823 | mips_xfer_register (regcache, | |
4824 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0, | |
4825 | 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
cb1d2653 AC |
4826 | break; |
4827 | default: | |
4828 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4829 | } | |
29dfb2ac | 4830 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4831 | } |
4832 | #if 0 | |
4833 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4834 | && TYPE_NFIELDS (type) <= 2 | |
4835 | && TYPE_NFIELDS (type) >= 1 | |
4836 | && ((TYPE_NFIELDS (type) == 1 | |
4837 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4838 | == TYPE_CODE_FLT)) | |
4839 | || (TYPE_NFIELDS (type) == 2 | |
4840 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4841 | == TYPE_CODE_FLT) | |
4842 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4843 | == TYPE_CODE_FLT))) | |
4844 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4845 | { | |
4846 | /* A struct that contains one or two floats. Each value is part | |
4847 | in the least significant part of their floating point | |
4848 | register.. */ | |
d9d9c31f | 4849 | bfd_byte reg[MAX_REGISTER_SIZE]; |
cb1d2653 AC |
4850 | int regnum; |
4851 | int field; | |
56cea623 | 4852 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
cb1d2653 AC |
4853 | field < TYPE_NFIELDS (type); |
4854 | field++, regnum += 2) | |
4855 | { | |
4856 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4857 | / TARGET_CHAR_BIT); | |
4858 | if (mips_debug) | |
4859 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4860 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4861 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4862 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4863 | } |
29dfb2ac | 4864 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4865 | } |
4866 | #endif | |
4867 | #if 0 | |
4868 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4869 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4870 | { | |
4871 | /* A structure or union. Extract the left justified value, | |
4872 | regardless of the byte order. I.e. DO NOT USE | |
4873 | mips_xfer_lower. */ | |
4874 | int offset; | |
4875 | int regnum; | |
4876 | for (offset = 0, regnum = V0_REGNUM; | |
4877 | offset < TYPE_LENGTH (type); | |
719ec221 | 4878 | offset += register_size (current_gdbarch, regnum), regnum++) |
cb1d2653 | 4879 | { |
719ec221 | 4880 | int xfer = register_size (current_gdbarch, regnum); |
cb1d2653 AC |
4881 | if (offset + xfer > TYPE_LENGTH (type)) |
4882 | xfer = TYPE_LENGTH (type) - offset; | |
4883 | if (mips_debug) | |
4884 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4885 | offset, xfer, regnum); | |
a4b8ebc8 | 4886 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4887 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
cb1d2653 | 4888 | } |
29dfb2ac | 4889 | return RETURN_VALUE_REGISTER_CONVENTION; |
cb1d2653 AC |
4890 | } |
4891 | #endif | |
4892 | else | |
4893 | { | |
4894 | /* A scalar extract each part but least-significant-byte | |
4895 | justified. o32 thinks registers are 4 byte, regardless of | |
4896 | the ISA. mips_stack_argsize controls this. */ | |
4897 | int offset; | |
4898 | int regnum; | |
4899 | for (offset = 0, regnum = V0_REGNUM; | |
4900 | offset < TYPE_LENGTH (type); | |
4901 | offset += mips_stack_argsize (), regnum++) | |
4902 | { | |
4903 | int xfer = mips_stack_argsize (); | |
4904 | int pos = 0; | |
4905 | if (offset + xfer > TYPE_LENGTH (type)) | |
4906 | xfer = TYPE_LENGTH (type) - offset; | |
4907 | if (mips_debug) | |
4908 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4909 | offset, xfer, regnum); | |
a4b8ebc8 | 4910 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4911 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
cb1d2653 | 4912 | } |
29dfb2ac | 4913 | return RETURN_VALUE_REGISTER_CONVENTION; |
46cac009 AC |
4914 | } |
4915 | } | |
4916 | ||
cb1d2653 AC |
4917 | /* N32/N44 ABI stuff. */ |
4918 | ||
29dfb2ac AC |
4919 | static enum return_value_convention |
4920 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
4921 | struct type *type, struct regcache *regcache, | |
4922 | void *readbuf, const void *writebuf) | |
c906108c | 4923 | { |
88658117 | 4924 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
29dfb2ac AC |
4925 | if (TYPE_CODE (type)== TYPE_CODE_STRUCT |
4926 | || TYPE_CODE (type)== TYPE_CODE_UNION | |
4927 | || TYPE_CODE (type)== TYPE_CODE_ARRAY | |
4928 | || TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE) | |
4929 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4930 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4931 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
7a292a7a | 4932 | { |
88658117 AC |
4933 | /* A floating-point value belongs in the least significant part |
4934 | of FP0. */ | |
4935 | if (mips_debug) | |
4936 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
29dfb2ac AC |
4937 | mips_xfer_register (regcache, |
4938 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4939 | TYPE_LENGTH (type), | |
4940 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4941 | return RETURN_VALUE_REGISTER_CONVENTION; | |
88658117 AC |
4942 | } |
4943 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4944 | && TYPE_NFIELDS (type) <= 2 | |
4945 | && TYPE_NFIELDS (type) >= 1 | |
4946 | && ((TYPE_NFIELDS (type) == 1 | |
4947 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4948 | == TYPE_CODE_FLT)) | |
4949 | || (TYPE_NFIELDS (type) == 2 | |
4950 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4951 | == TYPE_CODE_FLT) | |
4952 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4953 | == TYPE_CODE_FLT))) | |
4954 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4955 | { | |
4956 | /* A struct that contains one or two floats. Each value is part | |
4957 | in the least significant part of their floating point | |
4958 | register.. */ | |
d9d9c31f | 4959 | bfd_byte reg[MAX_REGISTER_SIZE]; |
88658117 AC |
4960 | int regnum; |
4961 | int field; | |
56cea623 | 4962 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; |
88658117 AC |
4963 | field < TYPE_NFIELDS (type); |
4964 | field++, regnum += 2) | |
4965 | { | |
4966 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4967 | / TARGET_CHAR_BIT); | |
4968 | if (mips_debug) | |
4969 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset); | |
a4b8ebc8 AC |
4970 | mips_xfer_register (regcache, NUM_REGS + regnum, |
4971 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
29dfb2ac | 4972 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 4973 | } |
29dfb2ac | 4974 | return RETURN_VALUE_REGISTER_CONVENTION; |
7a292a7a | 4975 | } |
88658117 AC |
4976 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4977 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4978 | { | |
4979 | /* A structure or union. Extract the left justified value, | |
4980 | regardless of the byte order. I.e. DO NOT USE | |
4981 | mips_xfer_lower. */ | |
4982 | int offset; | |
4983 | int regnum; | |
4984 | for (offset = 0, regnum = V0_REGNUM; | |
4985 | offset < TYPE_LENGTH (type); | |
719ec221 | 4986 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 4987 | { |
719ec221 | 4988 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
4989 | if (offset + xfer > TYPE_LENGTH (type)) |
4990 | xfer = TYPE_LENGTH (type) - offset; | |
4991 | if (mips_debug) | |
4992 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4993 | offset, xfer, regnum); | |
a4b8ebc8 | 4994 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 4995 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
88658117 | 4996 | } |
29dfb2ac | 4997 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
4998 | } |
4999 | else | |
5000 | { | |
5001 | /* A scalar extract each part but least-significant-byte | |
5002 | justified. */ | |
5003 | int offset; | |
5004 | int regnum; | |
5005 | for (offset = 0, regnum = V0_REGNUM; | |
5006 | offset < TYPE_LENGTH (type); | |
719ec221 | 5007 | offset += register_size (current_gdbarch, regnum), regnum++) |
88658117 | 5008 | { |
719ec221 | 5009 | int xfer = register_size (current_gdbarch, regnum); |
88658117 AC |
5010 | int pos = 0; |
5011 | if (offset + xfer > TYPE_LENGTH (type)) | |
5012 | xfer = TYPE_LENGTH (type) - offset; | |
5013 | if (mips_debug) | |
5014 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5015 | offset, xfer, regnum); | |
a4b8ebc8 | 5016 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, |
29dfb2ac | 5017 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); |
88658117 | 5018 | } |
29dfb2ac | 5019 | return RETURN_VALUE_REGISTER_CONVENTION; |
88658117 AC |
5020 | } |
5021 | } | |
5022 | ||
2f1488ce | 5023 | static CORE_ADDR |
6672060b | 5024 | mips_extract_struct_value_address (struct regcache *regcache) |
2f1488ce MS |
5025 | { |
5026 | /* FIXME: This will only work at random. The caller passes the | |
5027 | struct_return address in V0, but it is not preserved. It may | |
5028 | still be there, or this may be a random value. */ | |
77d8f2b4 MS |
5029 | LONGEST val; |
5030 | ||
5031 | regcache_cooked_read_signed (regcache, V0_REGNUM, &val); | |
6672060b | 5032 | return val; |
2f1488ce MS |
5033 | } |
5034 | ||
c906108c SS |
5035 | /* Exported procedure: Is PC in the signal trampoline code */ |
5036 | ||
102182a9 MS |
5037 | static int |
5038 | mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) | |
c906108c SS |
5039 | { |
5040 | if (sigtramp_address == 0) | |
5041 | fixup_sigtramp (); | |
5042 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
5043 | } | |
5044 | ||
a5ea2558 AC |
5045 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5046 | used for all MIPS-specific commands. */ | |
5047 | ||
a5ea2558 | 5048 | static void |
acdb74a0 | 5049 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5050 | { |
5051 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5052 | } | |
5053 | ||
a5ea2558 | 5054 | static void |
acdb74a0 | 5055 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5056 | { |
5057 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
5058 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
5059 | } | |
5060 | ||
c906108c SS |
5061 | /* Commands to show/set the MIPS FPU type. */ |
5062 | ||
c906108c | 5063 | static void |
acdb74a0 | 5064 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5065 | { |
c906108c SS |
5066 | char *fpu; |
5067 | switch (MIPS_FPU_TYPE) | |
5068 | { | |
5069 | case MIPS_FPU_SINGLE: | |
5070 | fpu = "single-precision"; | |
5071 | break; | |
5072 | case MIPS_FPU_DOUBLE: | |
5073 | fpu = "double-precision"; | |
5074 | break; | |
5075 | case MIPS_FPU_NONE: | |
5076 | fpu = "absent (none)"; | |
5077 | break; | |
93d56215 AC |
5078 | default: |
5079 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5080 | } |
5081 | if (mips_fpu_type_auto) | |
5082 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5083 | fpu); | |
5084 | else | |
5085 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
5086 | fpu); | |
5087 | } | |
5088 | ||
5089 | ||
c906108c | 5090 | static void |
acdb74a0 | 5091 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
5092 | { |
5093 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
5094 | show_mipsfpu_command (args, from_tty); | |
5095 | } | |
5096 | ||
c906108c | 5097 | static void |
acdb74a0 | 5098 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
5099 | { |
5100 | mips_fpu_type = MIPS_FPU_SINGLE; | |
5101 | mips_fpu_type_auto = 0; | |
9e364162 | 5102 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
5103 | } |
5104 | ||
c906108c | 5105 | static void |
acdb74a0 | 5106 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
5107 | { |
5108 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
5109 | mips_fpu_type_auto = 0; | |
9e364162 | 5110 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
5111 | } |
5112 | ||
c906108c | 5113 | static void |
acdb74a0 | 5114 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
5115 | { |
5116 | mips_fpu_type = MIPS_FPU_NONE; | |
5117 | mips_fpu_type_auto = 0; | |
9e364162 | 5118 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
5119 | } |
5120 | ||
c906108c | 5121 | static void |
acdb74a0 | 5122 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5123 | { |
5124 | mips_fpu_type_auto = 1; | |
5125 | } | |
5126 | ||
c906108c | 5127 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5128 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5129 | the relevant processor still exists (it dates back to '94) and | |
5130 | secondly this is not the way to do this. The processor type should | |
5131 | be set by forcing an architecture change. */ | |
c906108c | 5132 | |
691c0433 AC |
5133 | void |
5134 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5135 | { |
691c0433 | 5136 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5137 | CORE_ADDR prid; |
5138 | ||
5139 | prid = read_register (PRID_REGNUM); | |
5140 | ||
5141 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5142 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5143 | } |
5144 | ||
5145 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5146 | callable as an sfunc. */ | |
5147 | ||
5148 | static void | |
acdb74a0 AC |
5149 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5150 | struct cmd_list_element *c) | |
c906108c SS |
5151 | { |
5152 | reinit_frame_cache (); | |
5153 | } | |
5154 | ||
a89aa300 AC |
5155 | static int |
5156 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5157 | { |
e5ab0dce | 5158 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5159 | mips_extra_func_info_t proc_desc; |
5160 | ||
5161 | /* Search for the function containing this address. Set the low bit | |
5162 | of the address when searching, in case we were given an even address | |
5163 | that is the start of a 16-bit function. If we didn't do this, | |
5164 | the search would fail because the symbol table says the function | |
5165 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5166 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5167 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5168 | |
5169 | /* Make an attempt to determine if this is a 16-bit function. If | |
5170 | the procedure descriptor exists and the address therein is odd, | |
5171 | it's definitely a 16-bit function. Otherwise, we have to just | |
5172 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5173 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5174 | disassembler needs to be able to locally determine the ISA, and | |
5175 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5176 | work. */ | |
c906108c | 5177 | if (proc_desc) |
d31431ed AC |
5178 | { |
5179 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
5180 | info->mach = bfd_mach_mips16; | |
5181 | } | |
c906108c | 5182 | else |
d31431ed AC |
5183 | { |
5184 | if (pc_is_mips16 (memaddr)) | |
5185 | info->mach = bfd_mach_mips16; | |
5186 | } | |
c906108c SS |
5187 | |
5188 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5189 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5190 | |
e5ab0dce AC |
5191 | /* Set the disassembler options. */ |
5192 | if (tdep->mips_abi == MIPS_ABI_N32 | |
5193 | || tdep->mips_abi == MIPS_ABI_N64) | |
5194 | { | |
5195 | /* Set up the disassembler info, so that we get the right | |
5196 | register names from libopcodes. */ | |
5197 | if (tdep->mips_abi == MIPS_ABI_N32) | |
5198 | info->disassembler_options = "gpr-names=n32"; | |
5199 | else | |
5200 | info->disassembler_options = "gpr-names=64"; | |
5201 | info->flavour = bfd_target_elf_flavour; | |
5202 | } | |
5203 | else | |
5204 | /* This string is not recognized explicitly by the disassembler, | |
5205 | but it tells the disassembler to not try to guess the ABI from | |
5206 | the bfd elf headers, such that, if the user overrides the ABI | |
5207 | of a program linked as NewABI, the disassembly will follow the | |
5208 | register naming conventions specified by the user. */ | |
5209 | info->disassembler_options = "gpr-names=32"; | |
5210 | ||
c906108c | 5211 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5212 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5213 | return print_insn_big_mips (memaddr, info); |
5214 | else | |
5215 | return print_insn_little_mips (memaddr, info); | |
5216 | } | |
5217 | ||
c906108c SS |
5218 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5219 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5220 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5221 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5222 | (if necessary) to point to the actual memory location where the | |
5223 | breakpoint should be inserted. */ | |
5224 | ||
f7ab6ec6 | 5225 | static const unsigned char * |
acdb74a0 | 5226 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 5227 | { |
d7449b42 | 5228 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5229 | { |
5230 | if (pc_is_mips16 (*pcptr)) | |
5231 | { | |
aaab4dba | 5232 | static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5}; |
95404a3e | 5233 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5234 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5235 | return mips16_big_breakpoint; |
5236 | } | |
5237 | else | |
5238 | { | |
aaab4dba AC |
5239 | /* The IDT board uses an unusual breakpoint value, and |
5240 | sometimes gets confused when it sees the usual MIPS | |
5241 | breakpoint instruction. */ | |
5242 | static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd}; | |
5243 | static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd}; | |
5244 | static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd}; | |
c906108c | 5245 | |
c5aa993b | 5246 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5247 | |
5248 | if (strcmp (target_shortname, "mips") == 0) | |
5249 | return idt_big_breakpoint; | |
5250 | else if (strcmp (target_shortname, "ddb") == 0 | |
5251 | || strcmp (target_shortname, "pmon") == 0 | |
5252 | || strcmp (target_shortname, "lsi") == 0) | |
5253 | return pmon_big_breakpoint; | |
5254 | else | |
5255 | return big_breakpoint; | |
5256 | } | |
5257 | } | |
5258 | else | |
5259 | { | |
5260 | if (pc_is_mips16 (*pcptr)) | |
5261 | { | |
aaab4dba | 5262 | static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8}; |
95404a3e | 5263 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5264 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5265 | return mips16_little_breakpoint; |
5266 | } | |
5267 | else | |
5268 | { | |
aaab4dba AC |
5269 | static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0}; |
5270 | static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0}; | |
5271 | static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0}; | |
c906108c | 5272 | |
c5aa993b | 5273 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5274 | |
5275 | if (strcmp (target_shortname, "mips") == 0) | |
5276 | return idt_little_breakpoint; | |
5277 | else if (strcmp (target_shortname, "ddb") == 0 | |
5278 | || strcmp (target_shortname, "pmon") == 0 | |
5279 | || strcmp (target_shortname, "lsi") == 0) | |
5280 | return pmon_little_breakpoint; | |
5281 | else | |
5282 | return little_breakpoint; | |
5283 | } | |
5284 | } | |
5285 | } | |
5286 | ||
5287 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5288 | PC, which is either the callee or the caller. There are several | |
5289 | cases which must be handled: | |
5290 | ||
5291 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5292 | target PC is in $31 ($ra). |
c906108c | 5293 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5294 | and the target PC is in $2. |
c906108c | 5295 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5296 | before the jal instruction, this is effectively a call stub |
5297 | and the the target PC is in $2. Otherwise this is effectively | |
5298 | a return stub and the target PC is in $18. | |
c906108c SS |
5299 | |
5300 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5301 | gory details. | |
5302 | ||
5303 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5304 | */ |
c906108c | 5305 | |
757a7cc6 | 5306 | static CORE_ADDR |
acdb74a0 | 5307 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5308 | { |
5309 | char *name; | |
5310 | CORE_ADDR start_addr; | |
5311 | ||
5312 | /* Find the starting address and name of the function containing the PC. */ | |
5313 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5314 | return 0; | |
5315 | ||
5316 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5317 | target PC is in $31 ($ra). */ | |
5318 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5319 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5320 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5321 | |
5322 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5323 | { | |
5324 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5325 | and the target PC is in $2. */ | |
5326 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5327 | return read_signed_register (2); |
c906108c SS |
5328 | |
5329 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5330 | before the jal instruction, this is effectively a call stub |
5331 | and the the target PC is in $2. Otherwise this is effectively | |
5332 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5333 | else if (name[19] == 's' || name[19] == 'd') |
5334 | { | |
5335 | if (pc == start_addr) | |
5336 | { | |
5337 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5338 | stub. Such a stub for a function bar might have a name |
5339 | like __fn_stub_bar, and might look like this: | |
5340 | mfc1 $4,$f13 | |
5341 | mfc1 $5,$f12 | |
5342 | mfc1 $6,$f15 | |
5343 | mfc1 $7,$f14 | |
5344 | la $1,bar (becomes a lui/addiu pair) | |
5345 | jr $1 | |
5346 | So scan down to the lui/addi and extract the target | |
5347 | address from those two instructions. */ | |
c906108c | 5348 | |
6c997a34 | 5349 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5350 | t_inst inst; |
5351 | int i; | |
5352 | ||
5353 | /* See if the name of the target function is __fn_stub_*. */ | |
5354 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
5355 | return target_pc; | |
5356 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5357 | && strcmp (name, "etext") != 0 | |
5358 | && strcmp (name, "_etext") != 0) | |
5359 | return target_pc; | |
5360 | ||
5361 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5362 | The limit on the search is arbitrarily set to 20 |
5363 | instructions. FIXME. */ | |
c906108c SS |
5364 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5365 | { | |
c5aa993b JM |
5366 | inst = mips_fetch_instruction (target_pc); |
5367 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5368 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5369 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5370 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5371 | } |
5372 | ||
5373 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5374 | return target_pc; | |
5375 | } | |
5376 | else | |
5377 | /* This is the 'return' part of a call stub. The return | |
5378 | address is in $r18. */ | |
6c997a34 | 5379 | return read_signed_register (18); |
c906108c SS |
5380 | } |
5381 | } | |
c5aa993b | 5382 | return 0; /* not a stub */ |
c906108c SS |
5383 | } |
5384 | ||
5385 | ||
5386 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5387 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5388 | ||
757a7cc6 | 5389 | static int |
acdb74a0 | 5390 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5391 | { |
5392 | CORE_ADDR start_addr; | |
5393 | ||
5394 | /* Find the starting address of the function containing the PC. If the | |
5395 | caller didn't give us a name, look it up at the same time. */ | |
5396 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
5397 | return 0; | |
5398 | ||
5399 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5400 | { | |
5401 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5402 | if (name[19] >= '0' && name[19] <= '9') | |
5403 | return 1; | |
5404 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5405 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5406 | else if (name[19] == 's' || name[19] == 'd') |
5407 | return pc == start_addr; | |
5408 | } | |
5409 | ||
c5aa993b | 5410 | return 0; /* not a stub */ |
c906108c SS |
5411 | } |
5412 | ||
5413 | ||
5414 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5415 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5416 | ||
e41b17f0 | 5417 | static int |
acdb74a0 | 5418 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5419 | { |
5420 | CORE_ADDR start_addr; | |
5421 | ||
5422 | /* Find the starting address of the function containing the PC. */ | |
5423 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5424 | return 0; | |
5425 | ||
5426 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5427 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5428 | || strcmp (name, "__mips16_ret_df") == 0) | |
5429 | return 1; | |
5430 | ||
5431 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5432 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
5433 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
5434 | && (name[19] == 's' || name[19] == 'd') | |
5435 | && pc != start_addr) | |
5436 | return 1; | |
5437 | ||
c5aa993b | 5438 | return 0; /* not a stub */ |
c906108c SS |
5439 | } |
5440 | ||
5441 | ||
5442 | /* Return non-zero if the PC is in a library helper function that should | |
5443 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
5444 | ||
5445 | int | |
acdb74a0 | 5446 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5447 | { |
5448 | char *name; | |
5449 | ||
5450 | /* Find the starting address and name of the function containing the PC. */ | |
5451 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5452 | return 0; | |
5453 | ||
5454 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5455 | that we want to ignore. */ | |
5456 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5457 | || strcmp (name, "__mips16_ret_df") == 0); | |
5458 | } | |
5459 | ||
5460 | ||
47a8d4ba AC |
5461 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
5462 | the register stored on the stack (32) is different to its real raw | |
5463 | size (64). The below ensures that registers are fetched from the | |
5464 | stack using their ABI size and then stored into the RAW_BUFFER | |
5465 | using their raw size. | |
5466 | ||
5467 | The alternative to adding this function would be to add an ABI | |
5468 | macro - REGISTER_STACK_SIZE(). */ | |
5469 | ||
5470 | static void | |
acdb74a0 | 5471 | mips_get_saved_register (char *raw_buffer, |
795e1e11 | 5472 | int *optimizedp, |
acdb74a0 AC |
5473 | CORE_ADDR *addrp, |
5474 | struct frame_info *frame, | |
5475 | int regnum, | |
795e1e11 | 5476 | enum lval_type *lvalp) |
47a8d4ba | 5477 | { |
795e1e11 AC |
5478 | CORE_ADDR addrx; |
5479 | enum lval_type lvalx; | |
5480 | int optimizedx; | |
6e51443a | 5481 | int realnumx; |
47a8d4ba | 5482 | |
a4b8ebc8 AC |
5483 | /* Always a pseudo. */ |
5484 | gdb_assert (regnum >= NUM_REGS); | |
47a8d4ba | 5485 | |
795e1e11 AC |
5486 | /* Make certain that all needed parameters are present. */ |
5487 | if (addrp == NULL) | |
5488 | addrp = &addrx; | |
5489 | if (lvalp == NULL) | |
5490 | lvalp = &lvalx; | |
5491 | if (optimizedp == NULL) | |
5492 | optimizedp = &optimizedx; | |
a4b8ebc8 AC |
5493 | |
5494 | if ((regnum % NUM_REGS) == SP_REGNUM) | |
5495 | /* The SP_REGNUM is special, its value is stored in saved_regs. | |
5496 | In fact, it is so special that it can even only be fetched | |
5497 | using a raw register number! Once this code as been converted | |
5498 | to frame-unwind the problem goes away. */ | |
5499 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5500 | regnum % NUM_REGS, optimizedp, lvalp, addrp, | |
5501 | &realnumx, raw_buffer); | |
5502 | else | |
5503 | /* Get it from the next frame. */ | |
5504 | frame_register_unwind (deprecated_get_next_frame_hack (frame), | |
5505 | regnum, optimizedp, lvalp, addrp, | |
5506 | &realnumx, raw_buffer); | |
47a8d4ba | 5507 | } |
2acceee2 | 5508 | |
f7b9e9fc AC |
5509 | /* Immediately after a function call, return the saved pc. |
5510 | Can't always go through the frames for this because on some machines | |
5511 | the new frame is not set up until the new function executes | |
5512 | some instructions. */ | |
5513 | ||
5514 | static CORE_ADDR | |
5515 | mips_saved_pc_after_call (struct frame_info *frame) | |
5516 | { | |
6c997a34 | 5517 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
5518 | } |
5519 | ||
5520 | ||
a4b8ebc8 AC |
5521 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5522 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5523 | |
5524 | static int | |
5525 | mips_stab_reg_to_regnum (int num) | |
5526 | { | |
a4b8ebc8 | 5527 | int regnum; |
2f38ef89 | 5528 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5529 | regnum = num; |
2f38ef89 | 5530 | else if (num >= 38 && num < 70) |
56cea623 | 5531 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5532 | else if (num == 70) |
56cea623 | 5533 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5534 | else if (num == 71) |
56cea623 | 5535 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5536 | else |
a4b8ebc8 AC |
5537 | /* This will hopefully (eventually) provoke a warning. Should |
5538 | we be calling complaint() here? */ | |
5539 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5540 | return NUM_REGS + regnum; | |
88c72b7d AC |
5541 | } |
5542 | ||
2f38ef89 | 5543 | |
a4b8ebc8 AC |
5544 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5545 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5546 | |
5547 | static int | |
2f38ef89 | 5548 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5549 | { |
a4b8ebc8 | 5550 | int regnum; |
2f38ef89 | 5551 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5552 | regnum = num; |
2f38ef89 | 5553 | else if (num >= 32 && num < 64) |
56cea623 | 5554 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5555 | else if (num == 64) |
56cea623 | 5556 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5557 | else if (num == 65) |
56cea623 | 5558 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5559 | else |
a4b8ebc8 AC |
5560 | /* This will hopefully (eventually) provoke a warning. Should we |
5561 | be calling complaint() here? */ | |
5562 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5563 | return NUM_REGS + regnum; | |
5564 | } | |
5565 | ||
5566 | static int | |
5567 | mips_register_sim_regno (int regnum) | |
5568 | { | |
5569 | /* Only makes sense to supply raw registers. */ | |
5570 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5571 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5572 | decide if it is valid. Should instead define a standard sim/gdb | |
5573 | register numbering scheme. */ | |
5574 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5575 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5576 | return regnum; | |
5577 | else | |
5578 | return LEGACY_SIM_REGNO_IGNORE; | |
88c72b7d AC |
5579 | } |
5580 | ||
2f38ef89 | 5581 | |
fc0c74b1 AC |
5582 | /* Convert an integer into an address. By first converting the value |
5583 | into a pointer and then extracting it signed, the address is | |
5584 | guarenteed to be correctly sign extended. */ | |
5585 | ||
5586 | static CORE_ADDR | |
5587 | mips_integer_to_address (struct type *type, void *buf) | |
5588 | { | |
5589 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5590 | LONGEST val = unpack_long (type, buf); | |
5591 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5592 | return extract_signed_integer (tmp, | |
5593 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5594 | } | |
5595 | ||
caaa3122 DJ |
5596 | static void |
5597 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5598 | { | |
5599 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5600 | const char *name = bfd_get_section_name (abfd, sect); | |
5601 | ||
5602 | if (*abip != MIPS_ABI_UNKNOWN) | |
5603 | return; | |
5604 | ||
5605 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5606 | return; | |
5607 | ||
5608 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5609 | *abip = MIPS_ABI_O32; | |
5610 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5611 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5612 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5613 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5614 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5615 | *abip = MIPS_ABI_O64; | |
5616 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5617 | *abip = MIPS_ABI_EABI32; | |
5618 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5619 | *abip = MIPS_ABI_EABI64; | |
5620 | else | |
5621 | warning ("unsupported ABI %s.", name + 8); | |
5622 | } | |
5623 | ||
2e4ebe70 DJ |
5624 | static enum mips_abi |
5625 | global_mips_abi (void) | |
5626 | { | |
5627 | int i; | |
5628 | ||
5629 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5630 | if (mips_abi_strings[i] == mips_abi_string) | |
5631 | return (enum mips_abi) i; | |
5632 | ||
5633 | internal_error (__FILE__, __LINE__, | |
5634 | "unknown ABI string"); | |
5635 | } | |
5636 | ||
c2d11a7d | 5637 | static struct gdbarch * |
acdb74a0 AC |
5638 | mips_gdbarch_init (struct gdbarch_info info, |
5639 | struct gdbarch_list *arches) | |
c2d11a7d | 5640 | { |
c2d11a7d JM |
5641 | struct gdbarch *gdbarch; |
5642 | struct gdbarch_tdep *tdep; | |
5643 | int elf_flags; | |
2e4ebe70 | 5644 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5645 | int num_regs; |
c2d11a7d | 5646 | |
70f80edf JT |
5647 | elf_flags = 0; |
5648 | ||
5649 | if (info.abfd) | |
5650 | { | |
5651 | /* First of all, extract the elf_flags, if available. */ | |
5652 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5653 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
70f80edf | 5654 | } |
c2d11a7d | 5655 | |
102182a9 | 5656 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5657 | switch ((elf_flags & EF_MIPS_ABI)) |
5658 | { | |
5659 | case E_MIPS_ABI_O32: | |
5660 | mips_abi = MIPS_ABI_O32; | |
5661 | break; | |
5662 | case E_MIPS_ABI_O64: | |
5663 | mips_abi = MIPS_ABI_O64; | |
5664 | break; | |
5665 | case E_MIPS_ABI_EABI32: | |
5666 | mips_abi = MIPS_ABI_EABI32; | |
5667 | break; | |
5668 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 5669 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5670 | break; |
5671 | default: | |
acdb74a0 AC |
5672 | if ((elf_flags & EF_MIPS_ABI2)) |
5673 | mips_abi = MIPS_ABI_N32; | |
5674 | else | |
5675 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
5676 | break; |
5677 | } | |
acdb74a0 | 5678 | |
caaa3122 DJ |
5679 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
5680 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
5681 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
5682 | ||
2e4ebe70 DJ |
5683 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
5684 | Use the ABI from the last architecture if there is one. */ | |
5685 | if (info.abfd == NULL && arches != NULL) | |
5686 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
5687 | ||
32a6503c | 5688 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
5689 | if (mips_abi == MIPS_ABI_UNKNOWN |
5690 | && info.bfd_arch_info != NULL | |
5691 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5692 | { | |
5693 | switch (info.bfd_arch_info->mach) | |
5694 | { | |
5695 | case bfd_mach_mips3900: | |
5696 | mips_abi = MIPS_ABI_EABI32; | |
5697 | break; | |
5698 | case bfd_mach_mips4100: | |
5699 | case bfd_mach_mips5000: | |
5700 | mips_abi = MIPS_ABI_EABI64; | |
5701 | break; | |
1d06468c EZ |
5702 | case bfd_mach_mips8000: |
5703 | case bfd_mach_mips10000: | |
32a6503c KB |
5704 | /* On Irix, ELF64 executables use the N64 ABI. The |
5705 | pseudo-sections which describe the ABI aren't present | |
5706 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5707 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5708 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5709 | mips_abi = MIPS_ABI_N64; | |
5710 | else | |
5711 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 5712 | break; |
bf64bfd6 AC |
5713 | } |
5714 | } | |
2e4ebe70 | 5715 | |
2e4ebe70 DJ |
5716 | if (mips_abi == MIPS_ABI_UNKNOWN) |
5717 | mips_abi = MIPS_ABI_O32; | |
5718 | ||
5719 | /* Now that we have found what the ABI for this binary would be, | |
5720 | check whether the user is overriding it. */ | |
5721 | found_abi = mips_abi; | |
5722 | wanted_abi = global_mips_abi (); | |
5723 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
5724 | mips_abi = wanted_abi; | |
5725 | ||
4b9b3959 AC |
5726 | if (gdbarch_debug) |
5727 | { | |
5728 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 5729 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 5730 | elf_flags); |
4b9b3959 AC |
5731 | fprintf_unfiltered (gdb_stdlog, |
5732 | "mips_gdbarch_init: mips_abi = %d\n", | |
5733 | mips_abi); | |
2e4ebe70 DJ |
5734 | fprintf_unfiltered (gdb_stdlog, |
5735 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
5736 | found_abi); | |
4b9b3959 | 5737 | } |
0dadbba0 | 5738 | |
c2d11a7d JM |
5739 | /* try to find a pre-existing architecture */ |
5740 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5741 | arches != NULL; | |
5742 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5743 | { | |
5744 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5745 | using. */ |
9103eae0 | 5746 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5747 | continue; |
9103eae0 | 5748 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5749 | continue; |
719ec221 AC |
5750 | /* Need to be pedantic about which register virtual size is |
5751 | used. */ | |
5752 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5753 | != mips64_transfers_32bit_regs_p) | |
5754 | continue; | |
4be87837 | 5755 | return arches->gdbarch; |
c2d11a7d JM |
5756 | } |
5757 | ||
102182a9 | 5758 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5759 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5760 | gdbarch = gdbarch_alloc (&info, tdep); | |
5761 | tdep->elf_flags = elf_flags; | |
719ec221 | 5762 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
c2d11a7d | 5763 | |
102182a9 | 5764 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5765 | set_gdbarch_short_bit (gdbarch, 16); |
5766 | set_gdbarch_int_bit (gdbarch, 32); | |
5767 | set_gdbarch_float_bit (gdbarch, 32); | |
5768 | set_gdbarch_double_bit (gdbarch, 64); | |
5769 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5770 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5771 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5772 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
2e4ebe70 | 5773 | tdep->found_abi = found_abi; |
0dadbba0 | 5774 | tdep->mips_abi = mips_abi; |
1d06468c | 5775 | |
f7ab6ec6 MS |
5776 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
5777 | mips_elf_make_msymbol_special); | |
5778 | ||
16e109ca | 5779 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5780 | { |
16e109ca | 5781 | const char **reg_names; |
56cea623 AC |
5782 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5783 | struct mips_regnum); | |
56cea623 AC |
5784 | if (info.osabi == GDB_OSABI_IRIX) |
5785 | { | |
5786 | regnum->fp0 = 32; | |
5787 | regnum->pc = 64; | |
5788 | regnum->cause = 65; | |
5789 | regnum->badvaddr = 66; | |
5790 | regnum->hi = 67; | |
5791 | regnum->lo = 68; | |
5792 | regnum->fp_control_status = 69; | |
5793 | regnum->fp_implementation_revision = 70; | |
5794 | num_regs = 71; | |
16e109ca | 5795 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5796 | } |
5797 | else | |
5798 | { | |
5799 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5800 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5801 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5802 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5803 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5804 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5805 | regnum->fp_control_status = 70; | |
5806 | regnum->fp_implementation_revision = 71; | |
5807 | num_regs = 90; | |
16e109ca AC |
5808 | if (info.bfd_arch_info != NULL |
5809 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5810 | reg_names = mips_tx39_reg_names; | |
5811 | else | |
5812 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5813 | } |
5814 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5815 | replaced by read_pc? */ | |
5816 | set_gdbarch_pc_regnum (gdbarch, regnum->pc); | |
5817 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
5818 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5819 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5820 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5821 | tdep->mips_processor_reg_names = reg_names; | |
5822 | tdep->regnum = regnum; | |
56cea623 | 5823 | } |
fe29b929 | 5824 | |
0dadbba0 | 5825 | switch (mips_abi) |
c2d11a7d | 5826 | { |
0dadbba0 | 5827 | case MIPS_ABI_O32: |
25ab4790 | 5828 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5829 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
a5ea2558 | 5830 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5831 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5832 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5833 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5834 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5835 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5836 | set_gdbarch_long_bit (gdbarch, 32); |
5837 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5838 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5839 | set_gdbarch_deprecated_reg_struct_has_addr |
5840 | (gdbarch, mips_o32_reg_struct_has_addr); | |
c2d11a7d | 5841 | break; |
0dadbba0 | 5842 | case MIPS_ABI_O64: |
25ab4790 | 5843 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
ebba8386 | 5844 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); |
46cac009 | 5845 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); |
a5ea2558 | 5846 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5847 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5848 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5849 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 5850 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5851 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5852 | set_gdbarch_long_bit (gdbarch, 32); |
5853 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5854 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5855 | set_gdbarch_deprecated_reg_struct_has_addr |
5856 | (gdbarch, mips_o32_reg_struct_has_addr); | |
b060cbea | 5857 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 5858 | break; |
0dadbba0 | 5859 | case MIPS_ABI_EABI32: |
25ab4790 | 5860 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5861 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5862 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5863 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5864 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5865 | tdep->mips_fp_register_double = 0; |
acdb74a0 | 5866 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5867 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5868 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5869 | set_gdbarch_long_bit (gdbarch, 32); |
5870 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5871 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5872 | set_gdbarch_deprecated_reg_struct_has_addr |
5873 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5874 | set_gdbarch_use_struct_convention (gdbarch, |
5875 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5876 | break; |
0dadbba0 | 5877 | case MIPS_ABI_EABI64: |
25ab4790 | 5878 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
ebba8386 | 5879 | set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); |
46cac009 | 5880 | set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); |
a5ea2558 | 5881 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5882 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5883 | tdep->mips_fp_register_double = 1; |
acdb74a0 | 5884 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5885 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5886 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5887 | set_gdbarch_long_bit (gdbarch, 64); |
5888 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5889 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5890 | set_gdbarch_deprecated_reg_struct_has_addr |
5891 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5892 | set_gdbarch_use_struct_convention (gdbarch, |
5893 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5894 | break; |
0dadbba0 | 5895 | case MIPS_ABI_N32: |
25ab4790 | 5896 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5897 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
63db5580 | 5898 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5899 | tdep->mips_default_stack_argsize = 8; |
5900 | tdep->mips_fp_register_double = 1; | |
acdb74a0 | 5901 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 5902 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5903 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5904 | set_gdbarch_long_bit (gdbarch, 32); |
5905 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5906 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5907 | set_gdbarch_deprecated_reg_struct_has_addr |
5908 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5909 | break; |
5910 | case MIPS_ABI_N64: | |
25ab4790 | 5911 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5912 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de KB |
5913 | tdep->mips_default_saved_regsize = 8; |
5914 | tdep->mips_default_stack_argsize = 8; | |
5915 | tdep->mips_fp_register_double = 1; | |
5916 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
56cea623 | 5917 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5918 | tdep->default_mask_address_p = 0; |
5919 | set_gdbarch_long_bit (gdbarch, 64); | |
5920 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5921 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
5922 | set_gdbarch_deprecated_reg_struct_has_addr |
5923 | (gdbarch, mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5924 | break; |
c2d11a7d | 5925 | default: |
2e4ebe70 DJ |
5926 | internal_error (__FILE__, __LINE__, |
5927 | "unknown ABI in switch"); | |
c2d11a7d JM |
5928 | } |
5929 | ||
a5ea2558 AC |
5930 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5931 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5932 | comment: | |
5933 | ||
5934 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5935 | flag in object files because to do so would make it impossible to | |
102182a9 | 5936 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5937 | unnecessarily restrictive. |
361d1df0 | 5938 | |
a5ea2558 AC |
5939 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5940 | but to set this flag before gcc is built with such multilibs will | |
5941 | break too many systems.'' | |
5942 | ||
5943 | But even more unhelpfully, the default linker output target for | |
5944 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5945 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5946 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5947 | this flag to detect 32-bit mode would do the wrong thing given |
5948 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5949 | as 32-bit programs by default. */ |
a5ea2558 | 5950 | |
c2d11a7d JM |
5951 | /* enable/disable the MIPS FPU */ |
5952 | if (!mips_fpu_type_auto) | |
5953 | tdep->mips_fpu_type = mips_fpu_type; | |
5954 | else if (info.bfd_arch_info != NULL | |
5955 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5956 | switch (info.bfd_arch_info->mach) | |
5957 | { | |
b0069a17 | 5958 | case bfd_mach_mips3900: |
c2d11a7d | 5959 | case bfd_mach_mips4100: |
ed9a39eb | 5960 | case bfd_mach_mips4111: |
c2d11a7d JM |
5961 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5962 | break; | |
bf64bfd6 AC |
5963 | case bfd_mach_mips4650: |
5964 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5965 | break; | |
c2d11a7d JM |
5966 | default: |
5967 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5968 | break; | |
5969 | } | |
5970 | else | |
5971 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5972 | ||
6c997a34 | 5973 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d | 5974 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
0ba6dca9 | 5975 | set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ |
bcb0cc15 | 5976 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5977 | |
102182a9 MS |
5978 | /* Add/remove bits from an address. The MIPS needs be careful to |
5979 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5980 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5981 | ||
10312cc4 | 5982 | /* There's a mess in stack frame creation. See comments in |
2ca6c561 AC |
5983 | blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */ |
5984 | set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
10312cc4 | 5985 | |
102182a9 | 5986 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5987 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
2f38ef89 KB |
5988 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
5989 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5990 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5991 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5992 | |
c2d11a7d | 5993 | /* Initialize a frame */ |
e0f7ec59 | 5994 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs); |
e9582e71 | 5995 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
c2d11a7d JM |
5996 | |
5997 | /* MIPS version of CALL_DUMMY */ | |
5998 | ||
9710e734 AC |
5999 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6000 | replaced by a command, and all targets will default to on stack | |
6001 | (regardless of the stack's execute status). */ | |
6002 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
749b82f6 | 6003 | set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame); |
dc604539 | 6004 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
a59fe496 | 6005 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
d05285fa | 6006 | |
618ce49f | 6007 | set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain); |
b5d1566e MS |
6008 | set_gdbarch_frameless_function_invocation (gdbarch, |
6009 | generic_frameless_function_invocation_not); | |
8bedc050 | 6010 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc); |
b5d1566e MS |
6011 | set_gdbarch_frame_args_skip (gdbarch, 0); |
6012 | ||
129c1cd6 | 6013 | set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 6014 | |
f7b9e9fc AC |
6015 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6016 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
6017 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
6018 | |
6019 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
6913c89a | 6020 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); |
f7b9e9fc | 6021 | |
fc0c74b1 AC |
6022 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6023 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6024 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6025 | |
102182a9 MS |
6026 | set_gdbarch_function_start_offset (gdbarch, 0); |
6027 | ||
a4b8ebc8 | 6028 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6029 | |
e11c53d2 | 6030 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
102182a9 | 6031 | set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); |
bf1f5b4c | 6032 | |
e5ab0dce AC |
6033 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6034 | ||
3a3bc038 AC |
6035 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6036 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6037 | need to all be folded into the target vector. Since they are | |
6038 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6039 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6040 | is sitting on? */ | |
6041 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6042 | ||
70f80edf | 6043 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 6044 | gdbarch_init_osabi (info, gdbarch); |
70f80edf | 6045 | |
2f1488ce MS |
6046 | set_gdbarch_extract_struct_value_address (gdbarch, |
6047 | mips_extract_struct_value_address); | |
757a7cc6 MS |
6048 | |
6049 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); | |
6050 | ||
6051 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
e41b17f0 | 6052 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
757a7cc6 | 6053 | |
4b9b3959 AC |
6054 | return gdbarch; |
6055 | } | |
6056 | ||
2e4ebe70 DJ |
6057 | static void |
6058 | mips_abi_update (char *ignore_args, int from_tty, | |
6059 | struct cmd_list_element *c) | |
6060 | { | |
6061 | struct gdbarch_info info; | |
6062 | ||
6063 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6064 | mips_gdbarch_init will take care of the rest. */ | |
6065 | gdbarch_info_init (&info); | |
6066 | gdbarch_update_p (info); | |
6067 | } | |
6068 | ||
ad188201 KB |
6069 | /* Print out which MIPS ABI is in use. */ |
6070 | ||
6071 | static void | |
6072 | show_mips_abi (char *ignore_args, int from_tty) | |
6073 | { | |
6074 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6075 | printf_filtered ( | |
6076 | "The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
6077 | else | |
6078 | { | |
6079 | enum mips_abi global_abi = global_mips_abi (); | |
6080 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6081 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6082 | ||
6083 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6084 | printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6085 | actual_abi_str); | |
6086 | else if (global_abi == actual_abi) | |
6087 | printf_filtered ( | |
6088 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6089 | actual_abi_str); | |
6090 | else | |
6091 | { | |
6092 | /* Probably shouldn't happen... */ | |
6093 | printf_filtered ( | |
6094 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6095 | actual_abi_str, | |
6096 | mips_abi_strings[global_abi]); | |
6097 | } | |
6098 | } | |
6099 | } | |
6100 | ||
4b9b3959 AC |
6101 | static void |
6102 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6103 | { | |
6104 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6105 | if (tdep != NULL) | |
c2d11a7d | 6106 | { |
acdb74a0 AC |
6107 | int ef_mips_arch; |
6108 | int ef_mips_32bitmode; | |
6109 | /* determine the ISA */ | |
6110 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6111 | { | |
6112 | case E_MIPS_ARCH_1: | |
6113 | ef_mips_arch = 1; | |
6114 | break; | |
6115 | case E_MIPS_ARCH_2: | |
6116 | ef_mips_arch = 2; | |
6117 | break; | |
6118 | case E_MIPS_ARCH_3: | |
6119 | ef_mips_arch = 3; | |
6120 | break; | |
6121 | case E_MIPS_ARCH_4: | |
93d56215 | 6122 | ef_mips_arch = 4; |
acdb74a0 AC |
6123 | break; |
6124 | default: | |
93d56215 | 6125 | ef_mips_arch = 0; |
acdb74a0 AC |
6126 | break; |
6127 | } | |
6128 | /* determine the size of a pointer */ | |
6129 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6130 | fprintf_unfiltered (file, |
6131 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6132 | tdep->elf_flags); |
4b9b3959 | 6133 | fprintf_unfiltered (file, |
acdb74a0 AC |
6134 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6135 | ef_mips_32bitmode); | |
6136 | fprintf_unfiltered (file, | |
6137 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6138 | ef_mips_arch); | |
6139 | fprintf_unfiltered (file, | |
6140 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6141 | tdep->mips_abi, | |
2e4ebe70 | 6142 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6143 | fprintf_unfiltered (file, |
6144 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
6145 | mips_mask_address_p (), | |
6146 | tdep->default_mask_address_p); | |
c2d11a7d | 6147 | } |
4b9b3959 AC |
6148 | fprintf_unfiltered (file, |
6149 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6150 | FP_REGISTER_DOUBLE); | |
6151 | fprintf_unfiltered (file, | |
6152 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6153 | MIPS_DEFAULT_FPU_TYPE, | |
6154 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6155 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6156 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6157 | : "???")); | |
6158 | fprintf_unfiltered (file, | |
6159 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
6160 | MIPS_EABI); | |
4b9b3959 AC |
6161 | fprintf_unfiltered (file, |
6162 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6163 | MIPS_FPU_TYPE, | |
6164 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6165 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6166 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6167 | : "???")); | |
6168 | fprintf_unfiltered (file, | |
6169 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
6170 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
6171 | fprintf_unfiltered (file, |
6172 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
6173 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
6174 | fprintf_unfiltered (file, |
6175 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
6176 | MIPS_DEFAULT_STACK_ARGSIZE); | |
6177 | fprintf_unfiltered (file, | |
6178 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
6179 | MIPS_STACK_ARGSIZE); | |
2475bac3 AC |
6180 | fprintf_unfiltered (file, |
6181 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
6182 | A0_REGNUM); | |
6183 | fprintf_unfiltered (file, | |
6184 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6185 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
6186 | fprintf_unfiltered (file, | |
6187 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6188 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6189 | fprintf_unfiltered (file, |
6190 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6191 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6192 | fprintf_unfiltered (file, | |
6193 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6194 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6195 | fprintf_unfiltered (file, |
6196 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6197 | FIRST_EMBED_REGNUM); | |
2475bac3 AC |
6198 | fprintf_unfiltered (file, |
6199 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
6200 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6201 | fprintf_unfiltered (file, |
6202 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6203 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6204 | fprintf_unfiltered (file, | |
6205 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6206 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6207 | fprintf_unfiltered (file, |
6208 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6209 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6210 | #ifdef MACHINE_CPROC_FP_OFFSET |
6211 | fprintf_unfiltered (file, | |
6212 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6213 | MACHINE_CPROC_FP_OFFSET); | |
6214 | #endif | |
6215 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6216 | fprintf_unfiltered (file, | |
6217 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6218 | MACHINE_CPROC_PC_OFFSET); | |
6219 | #endif | |
6220 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6221 | fprintf_unfiltered (file, | |
6222 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6223 | MACHINE_CPROC_SP_OFFSET); | |
6224 | #endif | |
2475bac3 AC |
6225 | fprintf_unfiltered (file, |
6226 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6227 | MIPS16_INSTLEN); | |
2475bac3 AC |
6228 | fprintf_unfiltered (file, |
6229 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
6230 | fprintf_unfiltered (file, | |
6231 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6232 | fprintf_unfiltered (file, | |
6233 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
6234 | MIPS_INSTLEN); | |
6235 | fprintf_unfiltered (file, | |
acdb74a0 AC |
6236 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6237 | MIPS_LAST_ARG_REGNUM, | |
6238 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
6239 | fprintf_unfiltered (file, |
6240 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
6241 | MIPS_NUMREGS); | |
2475bac3 AC |
6242 | fprintf_unfiltered (file, |
6243 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
6244 | MIPS_SAVED_REGSIZE); | |
2475bac3 AC |
6245 | fprintf_unfiltered (file, |
6246 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
6247 | PRID_REGNUM); | |
2475bac3 AC |
6248 | fprintf_unfiltered (file, |
6249 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6250 | fprintf_unfiltered (file, | |
6251 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6252 | fprintf_unfiltered (file, | |
6253 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6254 | fprintf_unfiltered (file, | |
6255 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
6256 | fprintf_unfiltered (file, | |
6257 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6258 | fprintf_unfiltered (file, | |
6259 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6260 | fprintf_unfiltered (file, | |
6261 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6262 | fprintf_unfiltered (file, | |
6263 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6264 | fprintf_unfiltered (file, | |
6265 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6266 | fprintf_unfiltered (file, | |
6267 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6268 | fprintf_unfiltered (file, | |
6269 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6270 | fprintf_unfiltered (file, | |
6271 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6272 | fprintf_unfiltered (file, | |
6273 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
6274 | PS_REGNUM); | |
2475bac3 AC |
6275 | fprintf_unfiltered (file, |
6276 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
6277 | RA_REGNUM); | |
2475bac3 AC |
6278 | #ifdef SAVED_BYTES |
6279 | fprintf_unfiltered (file, | |
6280 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
6281 | SAVED_BYTES); | |
6282 | #endif | |
6283 | #ifdef SAVED_FP | |
6284 | fprintf_unfiltered (file, | |
6285 | "mips_dump_tdep: SAVED_FP = %d\n", | |
6286 | SAVED_FP); | |
6287 | #endif | |
6288 | #ifdef SAVED_PC | |
6289 | fprintf_unfiltered (file, | |
6290 | "mips_dump_tdep: SAVED_PC = %d\n", | |
6291 | SAVED_PC); | |
6292 | #endif | |
6293 | fprintf_unfiltered (file, | |
6294 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6295 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6296 | fprintf_unfiltered (file, | |
6297 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
6298 | fprintf_unfiltered (file, | |
6299 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
6300 | SIGFRAME_BASE); | |
6301 | fprintf_unfiltered (file, | |
6302 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
6303 | SIGFRAME_FPREGSAVE_OFF); | |
6304 | fprintf_unfiltered (file, | |
6305 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
6306 | SIGFRAME_PC_OFF); | |
6307 | fprintf_unfiltered (file, | |
6308 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
6309 | SIGFRAME_REGSAVE_OFF); | |
2475bac3 AC |
6310 | fprintf_unfiltered (file, |
6311 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6312 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6313 | fprintf_unfiltered (file, | |
6314 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6315 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6316 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6317 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6318 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6319 | fprintf_unfiltered (file, |
6320 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6321 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6322 | #ifdef STACK_END_ADDR | |
6323 | fprintf_unfiltered (file, | |
6324 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6325 | STACK_END_ADDR); | |
6326 | #endif | |
6327 | fprintf_unfiltered (file, | |
6328 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6329 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6330 | fprintf_unfiltered (file, | |
6331 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6332 | STEP_SKIPS_DELAY_P); | |
6333 | fprintf_unfiltered (file, | |
6334 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6335 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6336 | fprintf_unfiltered (file, | |
6337 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
6338 | T9_REGNUM); | |
6339 | fprintf_unfiltered (file, | |
6340 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6341 | fprintf_unfiltered (file, | |
6342 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6343 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
6344 | fprintf_unfiltered (file, | |
6345 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6346 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6347 | #ifdef TRACE_CLEAR |
6348 | fprintf_unfiltered (file, | |
6349 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6350 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6351 | #endif | |
6352 | #ifdef TRACE_FLAVOR | |
6353 | fprintf_unfiltered (file, | |
6354 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
6355 | TRACE_FLAVOR); | |
6356 | #endif | |
6357 | #ifdef TRACE_FLAVOR_SIZE | |
6358 | fprintf_unfiltered (file, | |
6359 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6360 | TRACE_FLAVOR_SIZE); | |
6361 | #endif | |
6362 | #ifdef TRACE_SET | |
6363 | fprintf_unfiltered (file, | |
6364 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6365 | XSTRING (TRACE_SET (X,STATE))); | |
6366 | #endif | |
2475bac3 AC |
6367 | #ifdef UNUSED_REGNUM |
6368 | fprintf_unfiltered (file, | |
6369 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
6370 | UNUSED_REGNUM); | |
6371 | #endif | |
6372 | fprintf_unfiltered (file, | |
6373 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
6374 | V0_REGNUM); | |
6375 | fprintf_unfiltered (file, | |
6376 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6377 | (long) VM_MIN_ADDRESS); | |
2475bac3 AC |
6378 | fprintf_unfiltered (file, |
6379 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
6380 | ZERO_REGNUM); | |
6381 | fprintf_unfiltered (file, | |
6382 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
6383 | _PROC_MAGIC_); | |
c2d11a7d JM |
6384 | } |
6385 | ||
a78f21af AC |
6386 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
6387 | ||
c906108c | 6388 | void |
acdb74a0 | 6389 | _initialize_mips_tdep (void) |
c906108c SS |
6390 | { |
6391 | static struct cmd_list_element *mipsfpulist = NULL; | |
6392 | struct cmd_list_element *c; | |
6393 | ||
2e4ebe70 DJ |
6394 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
6395 | if (MIPS_ABI_LAST + 1 | |
6396 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6397 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6398 | ||
4b9b3959 | 6399 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6400 | |
a5ea2558 AC |
6401 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6402 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6403 | "Various MIPS specific commands.", | |
6404 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6405 | ||
6406 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6407 | "Various MIPS specific commands.", | |
6408 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6409 | ||
6410 | /* Allow the user to override the saved register size. */ | |
6411 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
6412 | class_obscure, |
6413 | size_enums, | |
6414 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
6415 | Set size of general purpose registers saved on the stack.\n\ |
6416 | This option can be set to one of:\n\ | |
6417 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6418 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6419 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6420 | saved GP register size from information contained in the executable.\n\ | |
6421 | (default: auto)", | |
1ed2a135 | 6422 | &setmipscmdlist), |
a5ea2558 AC |
6423 | &showmipscmdlist); |
6424 | ||
d929b26f AC |
6425 | /* Allow the user to override the argument stack size. */ |
6426 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
6427 | class_obscure, | |
6428 | size_enums, | |
1ed2a135 | 6429 | &mips_stack_argsize_string, "\ |
d929b26f AC |
6430 | Set the amount of stack space reserved for each argument.\n\ |
6431 | This option can be set to one of:\n\ | |
6432 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6433 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6434 | auto - Allow GDB to determine the correct setting from the current\n\ | |
6435 | target and executable (default)", | |
6436 | &setmipscmdlist), | |
6437 | &showmipscmdlist); | |
6438 | ||
2e4ebe70 DJ |
6439 | /* Allow the user to override the ABI. */ |
6440 | c = add_set_enum_cmd | |
6441 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6442 | "Set the ABI used by this program.\n" | |
6443 | "This option can be set to one of:\n" | |
6444 | " auto - the default ABI associated with the current binary\n" | |
6445 | " o32\n" | |
6446 | " o64\n" | |
6447 | " n32\n" | |
f3a7b3a5 | 6448 | " n64\n" |
2e4ebe70 DJ |
6449 | " eabi32\n" |
6450 | " eabi64", | |
6451 | &setmipscmdlist); | |
2e4ebe70 | 6452 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 KB |
6453 | add_cmd ("abi", class_obscure, show_mips_abi, |
6454 | "Show ABI in use by MIPS target", &showmipscmdlist); | |
2e4ebe70 | 6455 | |
c906108c SS |
6456 | /* Let the user turn off floating point and set the fence post for |
6457 | heuristic_proc_start. */ | |
6458 | ||
6459 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6460 | "Set use of MIPS floating-point coprocessor.", | |
6461 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6462 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6463 | "Select single-precision MIPS floating-point coprocessor.", | |
6464 | &mipsfpulist); | |
6465 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6466 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6467 | &mipsfpulist); |
6468 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6469 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6470 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6471 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6472 | "Select no MIPS floating-point coprocessor.", | |
6473 | &mipsfpulist); | |
6474 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
6475 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6476 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6477 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6478 | "Select MIPS floating-point coprocessor automatically.", | |
6479 | &mipsfpulist); | |
6480 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6481 | "Show current use of MIPS floating-point coprocessor target.", | |
6482 | &showlist); | |
6483 | ||
c906108c SS |
6484 | /* We really would like to have both "0" and "unlimited" work, but |
6485 | command.c doesn't deal with that. So make it a var_zinteger | |
6486 | because the user can always use "999999" or some such for unlimited. */ | |
6487 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6488 | (char *) &heuristic_fence_post, | |
6489 | "\ | |
6490 | Set the distance searched for the start of a function.\n\ | |
6491 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6492 | program for the start of a function. This command sets the distance of the\n\ | |
6493 | search. The only need to set it is when debugging a stripped executable.", | |
6494 | &setlist); | |
6495 | /* We need to throw away the frame cache when we set this, since it | |
6496 | might change our ability to get backtraces. */ | |
9f60d481 | 6497 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
6498 | add_show_from_set (c, &showlist); |
6499 | ||
6500 | /* Allow the user to control whether the upper bits of 64-bit | |
6501 | addresses should be zeroed. */ | |
e9e68a56 AC |
6502 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
6503 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
6504 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
6505 | allow GDB to determine the correct value.\n", "\ | |
6506 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
6507 | NULL, show_mask_address, | |
6508 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6509 | |
6510 | /* Allow the user to control the size of 32 bit registers within the | |
6511 | raw remote packet. */ | |
719ec221 AC |
6512 | add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6513 | var_boolean, &mips64_transfers_32bit_regs_p, "\ | |
6514 | Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
6515 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
6516 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6517 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ | |
6518 | Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ | |
43e526b9 JM |
6519 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6520 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6521 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
719ec221 AC |
6522 | set_mips64_transfers_32bit_regs, NULL, |
6523 | &setlist, &showlist); | |
9ace0497 AC |
6524 | |
6525 | /* Debug this files internals. */ | |
6526 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6527 | &mips_debug, "Set mips debugging.\n\ | |
6528 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6529 | &showdebuglist); | |
c906108c | 6530 | } |