Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
e0f7ec59 | 61 | static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); |
5bbcb741 | 62 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 63 | |
dd824b04 DJ |
64 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
65 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
66 | #define ST0_FR (1 << 26) | |
67 | ||
b0069a17 AC |
68 | /* The sizes of floating point registers. */ |
69 | ||
70 | enum | |
71 | { | |
72 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
73 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
74 | }; | |
75 | ||
0dadbba0 | 76 | |
2e4ebe70 DJ |
77 | static const char *mips_abi_string; |
78 | ||
79 | static const char *mips_abi_strings[] = { | |
80 | "auto", | |
81 | "n32", | |
82 | "o32", | |
28d169de | 83 | "n64", |
2e4ebe70 DJ |
84 | "o64", |
85 | "eabi32", | |
86 | "eabi64", | |
87 | NULL | |
88 | }; | |
89 | ||
cce74817 | 90 | struct frame_extra_info |
6d82d43b AC |
91 | { |
92 | mips_extra_func_info_t proc_desc; | |
93 | int num_args; | |
94 | }; | |
cce74817 | 95 | |
d929b26f AC |
96 | /* Various MIPS ISA options (related to stack analysis) can be |
97 | overridden dynamically. Establish an enum/array for managing | |
98 | them. */ | |
99 | ||
53904c9e AC |
100 | static const char size_auto[] = "auto"; |
101 | static const char size_32[] = "32"; | |
102 | static const char size_64[] = "64"; | |
d929b26f | 103 | |
53904c9e | 104 | static const char *size_enums[] = { |
d929b26f AC |
105 | size_auto, |
106 | size_32, | |
107 | size_64, | |
a5ea2558 AC |
108 | 0 |
109 | }; | |
110 | ||
7a292a7a | 111 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 112 | support single-precision floating-point operations. */ |
c906108c SS |
113 | |
114 | enum mips_fpu_type | |
6d82d43b AC |
115 | { |
116 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
117 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
118 | MIPS_FPU_NONE /* No floating point. */ | |
119 | }; | |
c906108c SS |
120 | |
121 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
122 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
123 | #endif | |
124 | static int mips_fpu_type_auto = 1; | |
125 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 126 | |
9ace0497 | 127 | static int mips_debug = 0; |
7a292a7a | 128 | |
c2d11a7d JM |
129 | /* MIPS specific per-architecture information */ |
130 | struct gdbarch_tdep | |
6d82d43b AC |
131 | { |
132 | /* from the elf header */ | |
133 | int elf_flags; | |
134 | ||
135 | /* mips options */ | |
136 | enum mips_abi mips_abi; | |
137 | enum mips_abi found_abi; | |
138 | enum mips_fpu_type mips_fpu_type; | |
139 | int mips_last_arg_regnum; | |
140 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
141 | int default_mask_address_p; |
142 | /* Is the target using 64-bit raw integer registers but only | |
143 | storing a left-aligned 32-bit value in each? */ | |
144 | int mips64_transfers_32bit_regs_p; | |
145 | /* Indexes for various registers. IRIX and embedded have | |
146 | different values. This contains the "public" fields. Don't | |
147 | add any that do not need to be public. */ | |
148 | const struct mips_regnum *regnum; | |
149 | /* Register names table for the current register set. */ | |
150 | const char **mips_processor_reg_names; | |
151 | }; | |
c2d11a7d | 152 | |
fed7ba43 JB |
153 | static int |
154 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
155 | const char *from) | |
156 | { | |
157 | return 1; | |
158 | } | |
159 | ||
160 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
161 | They are implemented as a pair of 64bit doubles where the high | |
162 | part holds the result of the operation rounded to double, and | |
163 | the low double holds the difference between the exact result and | |
164 | the rounded result. So "high" + "low" contains the result with | |
165 | added precision. Unfortunately, the floatformat structure used | |
166 | by GDB is not powerful enough to describe this format. As a temporary | |
167 | measure, we define a 128bit floatformat that only uses the high part. | |
168 | We lose a bit of precision but that's probably the best we can do | |
169 | for now with the current infrastructure. */ | |
170 | ||
171 | static const struct floatformat floatformat_n32n64_long_double_big = | |
172 | { | |
173 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
174 | floatformat_intbit_no, | |
175 | "floatformat_ieee_double_big", | |
176 | n32n64_floatformat_always_valid | |
177 | }; | |
178 | ||
56cea623 AC |
179 | const struct mips_regnum * |
180 | mips_regnum (struct gdbarch *gdbarch) | |
181 | { | |
182 | return gdbarch_tdep (gdbarch)->regnum; | |
183 | } | |
184 | ||
185 | static int | |
186 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
187 | { | |
188 | return mips_regnum (gdbarch)->fp0 + 12; | |
189 | } | |
190 | ||
0dadbba0 | 191 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 192 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 193 | |
c2d11a7d | 194 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 195 | |
c2d11a7d | 196 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 197 | |
c2d11a7d | 198 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 199 | |
95404a3e AC |
200 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
201 | functions to test, set, or clear bit 0 of addresses. */ | |
202 | ||
203 | static CORE_ADDR | |
204 | is_mips16_addr (CORE_ADDR addr) | |
205 | { | |
206 | return ((addr) & 1); | |
207 | } | |
208 | ||
209 | static CORE_ADDR | |
210 | make_mips16_addr (CORE_ADDR addr) | |
211 | { | |
212 | return ((addr) | 1); | |
213 | } | |
214 | ||
215 | static CORE_ADDR | |
216 | unmake_mips16_addr (CORE_ADDR addr) | |
217 | { | |
218 | return ((addr) & ~1); | |
219 | } | |
220 | ||
22540ece AC |
221 | /* Return the contents of register REGNUM as a signed integer. */ |
222 | ||
223 | static LONGEST | |
224 | read_signed_register (int regnum) | |
225 | { | |
719ec221 | 226 | void *buf = alloca (register_size (current_gdbarch, regnum)); |
22540ece | 227 | deprecated_read_register_gen (regnum, buf); |
6d82d43b AC |
228 | return (extract_signed_integer |
229 | (buf, register_size (current_gdbarch, regnum))); | |
22540ece AC |
230 | } |
231 | ||
232 | static LONGEST | |
233 | read_signed_register_pid (int regnum, ptid_t ptid) | |
234 | { | |
235 | ptid_t save_ptid; | |
236 | LONGEST retval; | |
237 | ||
238 | if (ptid_equal (ptid, inferior_ptid)) | |
239 | return read_signed_register (regnum); | |
240 | ||
241 | save_ptid = inferior_ptid; | |
242 | ||
243 | inferior_ptid = ptid; | |
244 | ||
245 | retval = read_signed_register (regnum); | |
246 | ||
247 | inferior_ptid = save_ptid; | |
248 | ||
249 | return retval; | |
250 | } | |
251 | ||
d1973055 KB |
252 | /* Return the MIPS ABI associated with GDBARCH. */ |
253 | enum mips_abi | |
254 | mips_abi (struct gdbarch *gdbarch) | |
255 | { | |
256 | return gdbarch_tdep (gdbarch)->mips_abi; | |
257 | } | |
258 | ||
4246e332 | 259 | int |
1b13c4f6 | 260 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
261 | { |
262 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
263 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
264 | } | |
265 | ||
480d3dd2 AC |
266 | /* Return the currently configured (or set) saved register size. */ |
267 | ||
1b13c4f6 | 268 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 269 | |
d929b26f | 270 | static unsigned int |
13326b4e | 271 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 272 | { |
1b13c4f6 | 273 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
274 | switch (mips_abi (gdbarch)) |
275 | { | |
276 | case MIPS_ABI_EABI32: | |
277 | case MIPS_ABI_O32: | |
278 | return 4; | |
279 | case MIPS_ABI_N32: | |
280 | case MIPS_ABI_N64: | |
281 | case MIPS_ABI_O64: | |
282 | case MIPS_ABI_EABI64: | |
283 | return 8; | |
284 | case MIPS_ABI_UNKNOWN: | |
285 | case MIPS_ABI_LAST: | |
286 | default: | |
287 | internal_error (__FILE__, __LINE__, "bad switch"); | |
288 | } | |
1b13c4f6 | 289 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 290 | return 8; |
1b13c4f6 | 291 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
292 | return 4; |
293 | } | |
294 | ||
71b8ef93 | 295 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 296 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 297 | "info" field is used for this purpose. |
5a89d8aa MS |
298 | |
299 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
300 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
301 | minimal symbol to mark it as a 16-bit function | |
302 | ||
f594e5e9 | 303 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 304 | |
5a89d8aa | 305 | static void |
6d82d43b AC |
306 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
307 | { | |
308 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
309 | { | |
310 | MSYMBOL_INFO (msym) = (char *) | |
311 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
312 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
313 | } | |
5a89d8aa MS |
314 | } |
315 | ||
71b8ef93 MS |
316 | static int |
317 | msymbol_is_special (struct minimal_symbol *msym) | |
318 | { | |
319 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
320 | } | |
321 | ||
88658117 AC |
322 | /* XFER a value from the big/little/left end of the register. |
323 | Depending on the size of the value it might occupy the entire | |
324 | register or just part of it. Make an allowance for this, aligning | |
325 | things accordingly. */ | |
326 | ||
327 | static void | |
328 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
329 | enum bfd_endian endian, bfd_byte * in, |
330 | const bfd_byte * out, int buf_offset) | |
88658117 | 331 | { |
88658117 | 332 | int reg_offset = 0; |
a4b8ebc8 | 333 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
334 | /* Need to transfer the left or right part of the register, based on |
335 | the targets byte order. */ | |
88658117 AC |
336 | switch (endian) |
337 | { | |
338 | case BFD_ENDIAN_BIG: | |
719ec221 | 339 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
340 | break; |
341 | case BFD_ENDIAN_LITTLE: | |
342 | reg_offset = 0; | |
343 | break; | |
6d82d43b | 344 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
345 | reg_offset = 0; |
346 | break; | |
347 | default: | |
348 | internal_error (__FILE__, __LINE__, "bad switch"); | |
349 | } | |
350 | if (mips_debug) | |
cb1d2653 AC |
351 | fprintf_unfiltered (gdb_stderr, |
352 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
353 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
354 | if (mips_debug && out != NULL) |
355 | { | |
356 | int i; | |
cb1d2653 | 357 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 358 | for (i = 0; i < length; i++) |
cb1d2653 | 359 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
360 | } |
361 | if (in != NULL) | |
6d82d43b AC |
362 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
363 | in + buf_offset); | |
88658117 | 364 | if (out != NULL) |
6d82d43b AC |
365 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
366 | out + buf_offset); | |
88658117 AC |
367 | if (mips_debug && in != NULL) |
368 | { | |
369 | int i; | |
cb1d2653 | 370 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 371 | for (i = 0; i < length; i++) |
cb1d2653 | 372 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
373 | } |
374 | if (mips_debug) | |
375 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
376 | } | |
377 | ||
dd824b04 DJ |
378 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
379 | compatiblity mode. A return value of 1 means that we have | |
380 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
381 | ||
382 | static int | |
383 | mips2_fp_compat (void) | |
384 | { | |
385 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
386 | meaningful. */ | |
6d82d43b AC |
387 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
388 | 4) | |
dd824b04 DJ |
389 | return 0; |
390 | ||
391 | #if 0 | |
392 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
393 | in all the places we deal with FP registers. PR gdb/413. */ | |
394 | /* Otherwise check the FR bit in the status register - it controls | |
395 | the FP compatiblity mode. If it is clear we are in compatibility | |
396 | mode. */ | |
397 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
398 | return 1; | |
399 | #endif | |
361d1df0 | 400 | |
dd824b04 DJ |
401 | return 0; |
402 | } | |
403 | ||
d929b26f | 404 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 405 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
406 | data allocated after the registers have run out. */ |
407 | ||
53904c9e | 408 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
409 | |
410 | static unsigned int | |
13326b4e | 411 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
412 | { |
413 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 414 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
415 | else if (mips_stack_argsize_string == size_64) |
416 | return 8; | |
6d82d43b | 417 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
418 | return 4; |
419 | } | |
420 | ||
7a292a7a | 421 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 422 | |
570b8f7c | 423 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
465f7520 | 424 | struct frame_info *); |
eec63939 AC |
425 | static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc, |
426 | CORE_ADDR *addrptr); | |
c906108c | 427 | |
a14ed312 | 428 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 429 | |
a14ed312 | 430 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 431 | |
a14ed312 | 432 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 433 | |
177f84a3 | 434 | static CORE_ADDR after_prologue (CORE_ADDR pc); |
c906108c | 435 | |
67b2c998 DJ |
436 | static struct type *mips_float_register_type (void); |
437 | static struct type *mips_double_register_type (void); | |
438 | ||
acdb74a0 AC |
439 | /* The list of available "set mips " and "show mips " commands */ |
440 | ||
441 | static struct cmd_list_element *setmipscmdlist = NULL; | |
442 | static struct cmd_list_element *showmipscmdlist = NULL; | |
443 | ||
5e2e9765 KB |
444 | /* Integer registers 0 thru 31 are handled explicitly by |
445 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
446 | are listed in the followign tables. */ |
447 | ||
6d82d43b AC |
448 | enum |
449 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
450 | |
451 | /* Generic MIPS. */ | |
452 | ||
453 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
454 | "sr", "lo", "hi", "bad", "cause", "pc", |
455 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
456 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
457 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
458 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
459 | "fsr", "fir", "" /*"fp" */ , "", | |
460 | "", "", "", "", "", "", "", "", | |
461 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
462 | }; |
463 | ||
464 | /* Names of IDT R3041 registers. */ | |
465 | ||
466 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
467 | "sr", "lo", "hi", "bad", "cause", "pc", |
468 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
469 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
470 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
471 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
472 | "fsr", "fir", "", /*"fp" */ "", | |
473 | "", "", "bus", "ccfg", "", "", "", "", | |
474 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
475 | }; |
476 | ||
477 | /* Names of tx39 registers. */ | |
478 | ||
479 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
480 | "sr", "lo", "hi", "bad", "cause", "pc", |
481 | "", "", "", "", "", "", "", "", | |
482 | "", "", "", "", "", "", "", "", | |
483 | "", "", "", "", "", "", "", "", | |
484 | "", "", "", "", "", "", "", "", | |
485 | "", "", "", "", | |
486 | "", "", "", "", "", "", "", "", | |
487 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
488 | }; |
489 | ||
490 | /* Names of IRIX registers. */ | |
491 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
492 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
493 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
494 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
495 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
496 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
497 | }; |
498 | ||
cce74817 | 499 | |
5e2e9765 | 500 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 501 | static const char * |
5e2e9765 | 502 | mips_register_name (int regno) |
cce74817 | 503 | { |
691c0433 | 504 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
505 | /* GPR names for all ABIs other than n32/n64. */ |
506 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
507 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
508 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
509 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
510 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
511 | }; |
512 | ||
513 | /* GPR names for n32 and n64 ABIs. */ | |
514 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
515 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
516 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
517 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
518 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
519 | }; |
520 | ||
521 | enum mips_abi abi = mips_abi (current_gdbarch); | |
522 | ||
a4b8ebc8 AC |
523 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
524 | don't make the raw register names visible. */ | |
525 | int rawnum = regno % NUM_REGS; | |
526 | if (regno < NUM_REGS) | |
527 | return ""; | |
528 | ||
5e2e9765 KB |
529 | /* The MIPS integer registers are always mapped from 0 to 31. The |
530 | names of the registers (which reflects the conventions regarding | |
531 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 532 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
533 | { |
534 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 535 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 536 | else |
a4b8ebc8 | 537 | return mips_gpr_names[rawnum]; |
5e2e9765 | 538 | } |
a4b8ebc8 | 539 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
540 | { |
541 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
542 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
543 | } | |
5e2e9765 KB |
544 | else |
545 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 546 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 547 | } |
5e2e9765 | 548 | |
a4b8ebc8 | 549 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 550 | |
a4b8ebc8 AC |
551 | static int |
552 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
553 | struct reggroup *reggroup) | |
554 | { | |
555 | int vector_p; | |
556 | int float_p; | |
557 | int raw_p; | |
558 | int rawnum = regnum % NUM_REGS; | |
559 | int pseudo = regnum / NUM_REGS; | |
560 | if (reggroup == all_reggroup) | |
561 | return pseudo; | |
562 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
563 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
564 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
565 | (gdbarch), as not all architectures are multi-arch. */ | |
566 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 567 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
568 | return 0; |
569 | if (reggroup == float_reggroup) | |
570 | return float_p && pseudo; | |
571 | if (reggroup == vector_reggroup) | |
572 | return vector_p && pseudo; | |
573 | if (reggroup == general_reggroup) | |
574 | return (!vector_p && !float_p) && pseudo; | |
575 | /* Save the pseudo registers. Need to make certain that any code | |
576 | extracting register values from a saved register cache also uses | |
577 | pseudo registers. */ | |
578 | if (reggroup == save_reggroup) | |
579 | return raw_p && pseudo; | |
580 | /* Restore the same pseudo register. */ | |
581 | if (reggroup == restore_reggroup) | |
582 | return raw_p && pseudo; | |
6d82d43b | 583 | return 0; |
a4b8ebc8 AC |
584 | } |
585 | ||
586 | /* Map the symbol table registers which live in the range [1 * | |
587 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 588 | registers. Take care of alignment and size problems. */ |
c5aa993b | 589 | |
a4b8ebc8 AC |
590 | static void |
591 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
592 | int cookednum, void *buf) | |
593 | { | |
47ebcfbe | 594 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 595 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 596 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 597 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
598 | else if (register_size (gdbarch, rawnum) > |
599 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
600 | { |
601 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
602 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
603 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
604 | else | |
605 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
606 | } | |
607 | else | |
608 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
609 | } |
610 | ||
611 | static void | |
6d82d43b AC |
612 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
613 | struct regcache *regcache, int cookednum, | |
614 | const void *buf) | |
a4b8ebc8 | 615 | { |
47ebcfbe | 616 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 617 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 618 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 619 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
620 | else if (register_size (gdbarch, rawnum) > |
621 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
622 | { |
623 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
624 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
625 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
626 | else | |
627 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
628 | } | |
629 | else | |
630 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 631 | } |
c5aa993b | 632 | |
c906108c | 633 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 634 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
635 | |
636 | /* Heuristic_proc_start may hunt through the text section for a long | |
637 | time across a 2400 baud serial line. Allows the user to limit this | |
638 | search. */ | |
639 | ||
640 | static unsigned int heuristic_fence_post = 0; | |
641 | ||
c5aa993b JM |
642 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
643 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
644 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
645 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
646 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
647 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
648 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
649 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
650 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
651 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
652 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
653 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
654 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
655 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
656 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
657 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
658 | ||
46cd78fb | 659 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
660 | register N. NOTE: This defines the pseudo register type so need to |
661 | rebuild the architecture vector. */ | |
43e526b9 JM |
662 | |
663 | static int mips64_transfers_32bit_regs_p = 0; | |
664 | ||
719ec221 AC |
665 | static void |
666 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
667 | struct cmd_list_element *c) | |
43e526b9 | 668 | { |
719ec221 AC |
669 | struct gdbarch_info info; |
670 | gdbarch_info_init (&info); | |
671 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
672 | instead of relying on globals. Doing that would let generic code | |
673 | handle the search for this specific architecture. */ | |
674 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 675 | { |
719ec221 AC |
676 | mips64_transfers_32bit_regs_p = 0; |
677 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 678 | } |
a4b8ebc8 AC |
679 | } |
680 | ||
47ebcfbe | 681 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 682 | |
ff2e87ac AC |
683 | static int |
684 | mips_convert_register_p (int regnum, struct type *type) | |
685 | { | |
686 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 687 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
688 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
689 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 690 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
691 | } |
692 | ||
42c466d7 | 693 | static void |
ff2e87ac AC |
694 | mips_register_to_value (struct frame_info *frame, int regnum, |
695 | struct type *type, void *to) | |
102182a9 | 696 | { |
7f5f525d AC |
697 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
698 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
699 | } |
700 | ||
42c466d7 | 701 | static void |
ff2e87ac AC |
702 | mips_value_to_register (struct frame_info *frame, int regnum, |
703 | struct type *type, const void *from) | |
102182a9 | 704 | { |
ff2e87ac AC |
705 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
706 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
707 | } |
708 | ||
a4b8ebc8 AC |
709 | /* Return the GDB type object for the "standard" data type of data in |
710 | register REG. */ | |
78fde5f8 KB |
711 | |
712 | static struct type * | |
a4b8ebc8 AC |
713 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
714 | { | |
5ef80fb0 | 715 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
716 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
717 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 718 | { |
5ef80fb0 | 719 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 720 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
721 | switch (gdbarch_byte_order (gdbarch)) |
722 | { | |
723 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 724 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
725 | return builtin_type_ieee_single_big; |
726 | else | |
727 | return builtin_type_ieee_double_big; | |
728 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 729 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
730 | return builtin_type_ieee_single_little; |
731 | else | |
732 | return builtin_type_ieee_double_little; | |
733 | case BFD_ENDIAN_UNKNOWN: | |
734 | default: | |
735 | internal_error (__FILE__, __LINE__, "bad switch"); | |
736 | } | |
a6425924 | 737 | } |
d5ac5a39 AC |
738 | else if (regnum < NUM_REGS) |
739 | { | |
740 | /* The raw or ISA registers. These are all sized according to | |
741 | the ISA regsize. */ | |
742 | if (mips_isa_regsize (gdbarch) == 4) | |
743 | return builtin_type_int32; | |
744 | else | |
745 | return builtin_type_int64; | |
746 | } | |
78fde5f8 | 747 | else |
d5ac5a39 AC |
748 | { |
749 | /* The cooked or ABI registers. These are sized according to | |
750 | the ABI (with a few complications). */ | |
751 | if (regnum >= (NUM_REGS | |
752 | + mips_regnum (current_gdbarch)->fp_control_status) | |
753 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
754 | /* The pseudo/cooked view of the embedded registers is always | |
755 | 32-bit. The raw view is handled below. */ | |
756 | return builtin_type_int32; | |
757 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
758 | /* The target, while possibly using a 64-bit register buffer, | |
759 | is only transfering 32-bits of each integer register. | |
760 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
761 | return builtin_type_int32; | |
762 | else if (mips_abi_regsize (gdbarch) == 4) | |
763 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
764 | 32- or 64-bit). */ | |
765 | return builtin_type_int32; | |
766 | else | |
767 | /* 64-bit ABI. */ | |
768 | return builtin_type_int64; | |
769 | } | |
78fde5f8 KB |
770 | } |
771 | ||
bcb0cc15 MS |
772 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
773 | ||
774 | static CORE_ADDR | |
775 | mips_read_sp (void) | |
776 | { | |
f10683bb | 777 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
778 | } |
779 | ||
c906108c | 780 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 781 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
782 | |
783 | static int | |
480d3dd2 | 784 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
785 | { |
786 | switch (mask_address_var) | |
787 | { | |
7f19b9a2 | 788 | case AUTO_BOOLEAN_TRUE: |
4014092b | 789 | return 1; |
7f19b9a2 | 790 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
791 | return 0; |
792 | break; | |
7f19b9a2 | 793 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 794 | return tdep->default_mask_address_p; |
4014092b | 795 | default: |
6d82d43b | 796 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 797 | return -1; |
361d1df0 | 798 | } |
4014092b AC |
799 | } |
800 | ||
801 | static void | |
e9e68a56 | 802 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 803 | { |
480d3dd2 | 804 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
805 | switch (mask_address_var) |
806 | { | |
7f19b9a2 | 807 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
808 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
809 | break; | |
7f19b9a2 | 810 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
811 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
812 | break; | |
7f19b9a2 | 813 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
814 | printf_filtered |
815 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
816 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
817 | break; |
818 | default: | |
6d82d43b | 819 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 820 | break; |
361d1df0 | 821 | } |
4014092b | 822 | } |
c906108c | 823 | |
c906108c SS |
824 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
825 | ||
826 | static int | |
827 | pc_is_mips16 (bfd_vma memaddr) | |
828 | { | |
829 | struct minimal_symbol *sym; | |
830 | ||
831 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 832 | if (is_mips16_addr (memaddr)) |
c906108c SS |
833 | return 1; |
834 | ||
835 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
836 | the high bit of the info field. Use this to decide if the function is | |
837 | MIPS16 or normal MIPS. */ | |
838 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
839 | if (sym) | |
71b8ef93 | 840 | return msymbol_is_special (sym); |
c906108c SS |
841 | else |
842 | return 0; | |
843 | } | |
844 | ||
b2fa5097 | 845 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
846 | all registers should be sign extended for simplicity? */ |
847 | ||
848 | static CORE_ADDR | |
39f77062 | 849 | mips_read_pc (ptid_t ptid) |
6c997a34 | 850 | { |
b6cb9035 AC |
851 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
852 | } | |
853 | ||
58dfe9ff AC |
854 | static CORE_ADDR |
855 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
856 | { | |
edfae063 AC |
857 | return frame_unwind_register_signed (next_frame, |
858 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
859 | } | |
860 | ||
861 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
862 | dummy frame. The frame ID's base needs to match the TOS value | |
863 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
864 | breakpoint. */ | |
865 | ||
866 | static struct frame_id | |
867 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
868 | { | |
f10683bb | 869 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 870 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
871 | } |
872 | ||
b6cb9035 AC |
873 | static void |
874 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
875 | { | |
876 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 877 | } |
c906108c SS |
878 | |
879 | /* This returns the PC of the first inst after the prologue. If we can't | |
880 | find the prologue, then return 0. */ | |
881 | ||
882 | static CORE_ADDR | |
177f84a3 | 883 | after_prologue (CORE_ADDR pc) |
c906108c | 884 | { |
177f84a3 | 885 | mips_extra_func_info_t proc_desc; |
c906108c SS |
886 | struct symtab_and_line sal; |
887 | CORE_ADDR func_addr, func_end; | |
283be873 AC |
888 | CORE_ADDR startaddr = 0; |
889 | ||
890 | /* Pass a NULL next_frame to heuristic_proc_desc. We should not | |
891 | attempt to read the stack pointer from the current machine state, | |
892 | because the current machine state has nothing to do with the | |
893 | information we need from the proc_desc; and the process may or | |
894 | may not exist right now. */ | |
895 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
896 | if (proc_desc) | |
897 | { | |
898 | /* IF this is the topmost frame AND (this proc does not have | |
899 | debugging information OR the PC is in the procedure prologue) | |
900 | THEN create a "heuristic" proc_desc (by analyzing the actual | |
901 | code) to replace the "official" proc_desc. */ | |
902 | struct symtab_and_line val; | |
903 | struct symbol *proc_symbol = | |
904 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); | |
905 | ||
906 | if (proc_symbol) | |
907 | { | |
908 | val = find_pc_line (BLOCK_START | |
909 | (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); | |
910 | val.pc = val.end ? val.end : pc; | |
911 | } | |
912 | if (!proc_symbol || pc < val.pc) | |
913 | { | |
914 | mips_extra_func_info_t found_heuristic = | |
915 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), pc, NULL); | |
916 | if (found_heuristic) | |
917 | proc_desc = found_heuristic; | |
918 | } | |
919 | } | |
920 | else | |
921 | { | |
922 | if (startaddr == 0) | |
923 | startaddr = heuristic_proc_start (pc); | |
c906108c | 924 | |
283be873 AC |
925 | proc_desc = heuristic_proc_desc (startaddr, pc, NULL); |
926 | } | |
c906108c SS |
927 | |
928 | if (proc_desc) | |
929 | { | |
930 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 931 | strongly suspect that frameless always means prologueless... */ |
f10683bb | 932 | if (PROC_FRAME_REG (proc_desc) == MIPS_SP_REGNUM |
c906108c SS |
933 | && PROC_FRAME_OFFSET (proc_desc) == 0) |
934 | return 0; | |
935 | } | |
936 | ||
937 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
938 | return 0; /* Unknown */ | |
939 | ||
940 | sal = find_pc_line (func_addr, 0); | |
941 | ||
942 | if (sal.end < func_end) | |
943 | return sal.end; | |
944 | ||
945 | /* The line after the prologue is after the end of the function. In this | |
946 | case, tell the caller to find the prologue the hard way. */ | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
952 | set the appropriate bit in the general register mask or float register mask | |
953 | to indicate which register is saved. This is a helper function | |
954 | for mips_find_saved_regs. */ | |
955 | ||
956 | static void | |
acdb74a0 AC |
957 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
958 | unsigned long *float_mask) | |
c906108c SS |
959 | { |
960 | int reg; | |
961 | ||
6d82d43b | 962 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
c906108c SS |
963 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
964 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
965 | { | |
966 | /* It might be possible to use the instruction to | |
c5aa993b JM |
967 | find the offset, rather than the code below which |
968 | is based on things being in a certain order in the | |
969 | frame, but figuring out what the instruction's offset | |
970 | is relative to might be a little tricky. */ | |
c906108c SS |
971 | reg = (inst & 0x001f0000) >> 16; |
972 | *gen_mask |= (1 << reg); | |
973 | } | |
974 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
6d82d43b | 975 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
c5aa993b | 976 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
c906108c SS |
977 | |
978 | { | |
979 | reg = ((inst & 0x001f0000) >> 16); | |
980 | *float_mask |= (1 << reg); | |
981 | } | |
982 | } | |
983 | ||
984 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
985 | set the appropriate bit in the general register or float register mask | |
986 | to indicate which register is saved. This is a helper function | |
987 | for mips_find_saved_regs. */ | |
988 | ||
989 | static void | |
acdb74a0 | 990 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 991 | { |
c5aa993b | 992 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
993 | { |
994 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
995 | *gen_mask |= (1 << reg); | |
996 | } | |
c5aa993b | 997 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
998 | { |
999 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1000 | *gen_mask |= (1 << reg); | |
1001 | } | |
c5aa993b | 1002 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
1003 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
1004 | *gen_mask |= (1 << RA_REGNUM); | |
1005 | } | |
1006 | ||
1007 | ||
1008 | /* Fetch and return instruction from the specified location. If the PC | |
1009 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1010 | ||
1011 | static t_inst | |
acdb74a0 | 1012 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
1013 | { |
1014 | char buf[MIPS_INSTLEN]; | |
1015 | int instlen; | |
1016 | int status; | |
1017 | ||
1018 | if (pc_is_mips16 (addr)) | |
1019 | { | |
1020 | instlen = MIPS16_INSTLEN; | |
95404a3e | 1021 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1022 | } |
1023 | else | |
c5aa993b | 1024 | instlen = MIPS_INSTLEN; |
1f602b35 | 1025 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
1026 | if (status) |
1027 | memory_error (status, addr); | |
1028 | return extract_unsigned_integer (buf, instlen); | |
1029 | } | |
1030 | ||
edfae063 AC |
1031 | static ULONGEST |
1032 | mips16_fetch_instruction (CORE_ADDR addr) | |
1033 | { | |
1034 | char buf[MIPS_INSTLEN]; | |
1035 | int instlen; | |
1036 | int status; | |
1037 | ||
1038 | instlen = MIPS16_INSTLEN; | |
1039 | addr = unmake_mips16_addr (addr); | |
1f602b35 | 1040 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
1041 | if (status) |
1042 | memory_error (status, addr); | |
1043 | return extract_unsigned_integer (buf, instlen); | |
1044 | } | |
1045 | ||
1046 | static ULONGEST | |
1047 | mips32_fetch_instruction (CORE_ADDR addr) | |
1048 | { | |
1049 | char buf[MIPS_INSTLEN]; | |
1050 | int instlen; | |
1051 | int status; | |
1052 | instlen = MIPS_INSTLEN; | |
1f602b35 | 1053 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
edfae063 AC |
1054 | if (status) |
1055 | memory_error (status, addr); | |
1056 | return extract_unsigned_integer (buf, instlen); | |
1057 | } | |
1058 | ||
c906108c SS |
1059 | |
1060 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
1061 | #define mips32_op(x) (x >> 26) |
1062 | #define itype_op(x) (x >> 26) | |
1063 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1064 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1065 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1066 | |
e135b889 DJ |
1067 | #define jtype_op(x) (x >> 26) |
1068 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1069 | |
e135b889 DJ |
1070 | #define rtype_op(x) (x >> 26) |
1071 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1072 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1073 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1074 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1075 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
1076 | |
1077 | static CORE_ADDR | |
c5aa993b JM |
1078 | mips32_relative_offset (unsigned long inst) |
1079 | { | |
1080 | long x; | |
1081 | x = itype_immediate (inst); | |
1082 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1083 | { |
c5aa993b | 1084 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1085 | } |
c5aa993b JM |
1086 | x = x << 2; |
1087 | return x; | |
c906108c SS |
1088 | } |
1089 | ||
1090 | /* Determine whate to set a single step breakpoint while considering | |
1091 | branch prediction */ | |
5a89d8aa | 1092 | static CORE_ADDR |
c5aa993b JM |
1093 | mips32_next_pc (CORE_ADDR pc) |
1094 | { | |
1095 | unsigned long inst; | |
1096 | int op; | |
1097 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1098 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1099 | { |
e135b889 | 1100 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1101 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1102 | { |
e135b889 | 1103 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1104 | switch (op) |
1105 | { | |
e135b889 DJ |
1106 | case 0: /* BEQL */ |
1107 | goto equal_branch; | |
1108 | case 1: /* BNEL */ | |
1109 | goto neq_branch; | |
1110 | case 2: /* BLEZL */ | |
1111 | goto less_branch; | |
1112 | case 3: /* BGTZ */ | |
1113 | goto greater_branch; | |
c5aa993b JM |
1114 | default: |
1115 | pc += 4; | |
c906108c SS |
1116 | } |
1117 | } | |
e135b889 | 1118 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1119 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1120 | { |
1121 | int tf = itype_rt (inst) & 0x01; | |
1122 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1123 | int fcrcs = |
1124 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1125 | fp_control_status); | |
e135b889 DJ |
1126 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1127 | ||
1128 | if (((cond >> cnum) & 0x01) == tf) | |
1129 | pc += mips32_relative_offset (inst) + 4; | |
1130 | else | |
1131 | pc += 8; | |
1132 | } | |
c5aa993b JM |
1133 | else |
1134 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1135 | } |
1136 | else | |
c5aa993b JM |
1137 | { /* This gets way messy */ |
1138 | ||
c906108c | 1139 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1140 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1141 | { |
c5aa993b JM |
1142 | case 0: /* SPECIAL */ |
1143 | op = rtype_funct (inst); | |
1144 | switch (op) | |
1145 | { | |
1146 | case 8: /* JR */ | |
1147 | case 9: /* JALR */ | |
6c997a34 AC |
1148 | /* Set PC to that address */ |
1149 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1150 | break; |
1151 | default: | |
1152 | pc += 4; | |
1153 | } | |
1154 | ||
6d82d43b | 1155 | break; /* end SPECIAL */ |
c5aa993b | 1156 | case 1: /* REGIMM */ |
c906108c | 1157 | { |
e135b889 DJ |
1158 | op = itype_rt (inst); /* branch condition */ |
1159 | switch (op) | |
c906108c | 1160 | { |
c5aa993b | 1161 | case 0: /* BLTZ */ |
e135b889 DJ |
1162 | case 2: /* BLTZL */ |
1163 | case 16: /* BLTZAL */ | |
c5aa993b | 1164 | case 18: /* BLTZALL */ |
c906108c | 1165 | less_branch: |
6c997a34 | 1166 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1167 | pc += mips32_relative_offset (inst) + 4; |
1168 | else | |
1169 | pc += 8; /* after the delay slot */ | |
1170 | break; | |
e135b889 | 1171 | case 1: /* BGEZ */ |
c5aa993b JM |
1172 | case 3: /* BGEZL */ |
1173 | case 17: /* BGEZAL */ | |
1174 | case 19: /* BGEZALL */ | |
6c997a34 | 1175 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1176 | pc += mips32_relative_offset (inst) + 4; |
1177 | else | |
1178 | pc += 8; /* after the delay slot */ | |
1179 | break; | |
e135b889 | 1180 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1181 | default: |
1182 | pc += 4; | |
c906108c SS |
1183 | } |
1184 | } | |
6d82d43b | 1185 | break; /* end REGIMM */ |
c5aa993b JM |
1186 | case 2: /* J */ |
1187 | case 3: /* JAL */ | |
1188 | { | |
1189 | unsigned long reg; | |
1190 | reg = jtype_target (inst) << 2; | |
e135b889 | 1191 | /* Upper four bits get never changed... */ |
c5aa993b | 1192 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1193 | } |
c5aa993b JM |
1194 | break; |
1195 | /* FIXME case JALX : */ | |
1196 | { | |
1197 | unsigned long reg; | |
1198 | reg = jtype_target (inst) << 2; | |
1199 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1200 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1201 | } | |
c5aa993b | 1202 | break; /* The new PC will be alternate mode */ |
e135b889 | 1203 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1204 | equal_branch: |
6c997a34 AC |
1205 | if (read_signed_register (itype_rs (inst)) == |
1206 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1207 | pc += mips32_relative_offset (inst) + 4; |
1208 | else | |
1209 | pc += 8; | |
1210 | break; | |
e135b889 | 1211 | case 5: /* BNE, BNEL */ |
c5aa993b | 1212 | neq_branch: |
6c997a34 | 1213 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1214 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1215 | pc += mips32_relative_offset (inst) + 4; |
1216 | else | |
1217 | pc += 8; | |
1218 | break; | |
e135b889 | 1219 | case 6: /* BLEZ, BLEZL */ |
6c997a34 | 1220 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
1221 | pc += mips32_relative_offset (inst) + 4; |
1222 | else | |
1223 | pc += 8; | |
1224 | break; | |
1225 | case 7: | |
e135b889 DJ |
1226 | default: |
1227 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 1228 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
1229 | pc += mips32_relative_offset (inst) + 4; |
1230 | else | |
1231 | pc += 8; | |
1232 | break; | |
c5aa993b JM |
1233 | } /* switch */ |
1234 | } /* else */ | |
1235 | return pc; | |
1236 | } /* mips32_next_pc */ | |
c906108c SS |
1237 | |
1238 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1239 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1240 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1241 | We dont want to set a single step instruction on the extend instruction | |
1242 | either. | |
c5aa993b | 1243 | */ |
c906108c SS |
1244 | |
1245 | /* Lots of mips16 instruction formats */ | |
1246 | /* Predicting jumps requires itype,ritype,i8type | |
1247 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1248 | */ |
c906108c SS |
1249 | enum mips16_inst_fmts |
1250 | { | |
c5aa993b JM |
1251 | itype, /* 0 immediate 5,10 */ |
1252 | ritype, /* 1 5,3,8 */ | |
1253 | rrtype, /* 2 5,3,3,5 */ | |
1254 | rritype, /* 3 5,3,3,5 */ | |
1255 | rrrtype, /* 4 5,3,3,3,2 */ | |
1256 | rriatype, /* 5 5,3,3,1,4 */ | |
1257 | shifttype, /* 6 5,3,3,3,2 */ | |
1258 | i8type, /* 7 5,3,8 */ | |
1259 | i8movtype, /* 8 5,3,3,5 */ | |
1260 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1261 | i64type, /* 10 5,3,8 */ | |
1262 | ri64type, /* 11 5,3,3,5 */ | |
1263 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1264 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1265 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1266 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1267 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1268 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1269 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1270 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1271 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1272 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1273 | }; | |
12f02c2a AC |
1274 | /* I am heaping all the fields of the formats into one structure and |
1275 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1276 | struct upk_mips16 |
6d82d43b AC |
1277 | { |
1278 | CORE_ADDR offset; | |
1279 | unsigned int regx; /* Function in i8 type */ | |
1280 | unsigned int regy; | |
1281 | }; | |
c906108c SS |
1282 | |
1283 | ||
12f02c2a AC |
1284 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1285 | for the bits which make up the immediatate extension. */ | |
c906108c | 1286 | |
12f02c2a AC |
1287 | static CORE_ADDR |
1288 | extended_offset (unsigned int extension) | |
c906108c | 1289 | { |
12f02c2a | 1290 | CORE_ADDR value; |
c5aa993b JM |
1291 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1292 | value = value << 6; | |
1293 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1294 | value = value << 5; | |
1295 | value |= extension & 0x01f; /* extract 4:0 */ | |
1296 | return value; | |
c906108c SS |
1297 | } |
1298 | ||
1299 | /* Only call this function if you know that this is an extendable | |
1300 | instruction, It wont malfunction, but why make excess remote memory references? | |
1301 | If the immediate operands get sign extended or somthing, do it after | |
1302 | the extension is performed. | |
c5aa993b | 1303 | */ |
c906108c SS |
1304 | /* FIXME: Every one of these cases needs to worry about sign extension |
1305 | when the offset is to be used in relative addressing */ | |
1306 | ||
1307 | ||
12f02c2a | 1308 | static unsigned int |
c5aa993b | 1309 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1310 | { |
c5aa993b JM |
1311 | char buf[8]; |
1312 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1313 | target_read_memory (pc, buf, 2); | |
1314 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1315 | } |
1316 | ||
1317 | static void | |
c5aa993b | 1318 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1319 | unsigned int extension, |
1320 | unsigned int inst, | |
6d82d43b | 1321 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1322 | { |
12f02c2a AC |
1323 | CORE_ADDR offset; |
1324 | int regx; | |
1325 | int regy; | |
1326 | switch (insn_format) | |
c906108c | 1327 | { |
c5aa993b | 1328 | case itype: |
c906108c | 1329 | { |
12f02c2a AC |
1330 | CORE_ADDR value; |
1331 | if (extension) | |
c5aa993b JM |
1332 | { |
1333 | value = extended_offset (extension); | |
1334 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1335 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1336 | } |
1337 | else | |
c5aa993b | 1338 | { |
12f02c2a | 1339 | value = inst & 0x7ff; |
c5aa993b | 1340 | /* FIXME : Consider sign extension */ |
c906108c | 1341 | } |
12f02c2a AC |
1342 | offset = value; |
1343 | regx = -1; | |
1344 | regy = -1; | |
c906108c | 1345 | } |
c5aa993b JM |
1346 | break; |
1347 | case ritype: | |
1348 | case i8type: | |
1349 | { /* A register identifier and an offset */ | |
c906108c SS |
1350 | /* Most of the fields are the same as I type but the |
1351 | immediate value is of a different length */ | |
12f02c2a AC |
1352 | CORE_ADDR value; |
1353 | if (extension) | |
c906108c | 1354 | { |
c5aa993b JM |
1355 | value = extended_offset (extension); |
1356 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1357 | value |= inst & 0xff; /* eleven bits from instruction */ |
1358 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1359 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1360 | { | |
1361 | value &= ~0x3fff; /* remove the sign bit */ | |
1362 | value = -value; | |
c906108c SS |
1363 | } |
1364 | } | |
c5aa993b JM |
1365 | else |
1366 | { | |
12f02c2a AC |
1367 | value = inst & 0xff; /* 8 bits */ |
1368 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1369 | /* FIXME: Do sign extension , this format needs it */ |
1370 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1371 | { | |
1372 | value &= 0xef; /* remove the sign bit */ | |
1373 | value = -value; | |
1374 | } | |
c5aa993b | 1375 | } |
12f02c2a AC |
1376 | offset = value; |
1377 | regy = -1; | |
c5aa993b | 1378 | break; |
c906108c | 1379 | } |
c5aa993b | 1380 | case jalxtype: |
c906108c | 1381 | { |
c5aa993b | 1382 | unsigned long value; |
12f02c2a AC |
1383 | unsigned int nexthalf; |
1384 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1385 | value = value << 16; |
1386 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1387 | value |= nexthalf; | |
12f02c2a AC |
1388 | offset = value; |
1389 | regx = -1; | |
1390 | regy = -1; | |
c5aa993b | 1391 | break; |
c906108c SS |
1392 | } |
1393 | default: | |
6d82d43b | 1394 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1395 | } |
12f02c2a AC |
1396 | upk->offset = offset; |
1397 | upk->regx = regx; | |
1398 | upk->regy = regy; | |
c906108c SS |
1399 | } |
1400 | ||
1401 | ||
c5aa993b JM |
1402 | static CORE_ADDR |
1403 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1404 | { |
c5aa993b | 1405 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1406 | } |
1407 | ||
12f02c2a AC |
1408 | static CORE_ADDR |
1409 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1410 | unsigned int extension, unsigned int insn) |
c906108c | 1411 | { |
12f02c2a AC |
1412 | int op = (insn >> 11); |
1413 | switch (op) | |
c906108c | 1414 | { |
6d82d43b | 1415 | case 2: /* Branch */ |
12f02c2a AC |
1416 | { |
1417 | CORE_ADDR offset; | |
1418 | struct upk_mips16 upk; | |
1419 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1420 | offset = upk.offset; | |
1421 | if (offset & 0x800) | |
1422 | { | |
1423 | offset &= 0xeff; | |
1424 | offset = -offset; | |
1425 | } | |
1426 | pc += (offset << 1) + 2; | |
1427 | break; | |
1428 | } | |
6d82d43b | 1429 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1430 | { |
1431 | struct upk_mips16 upk; | |
1432 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1433 | pc = add_offset_16 (pc, upk.offset); | |
1434 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1435 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1436 | else | |
1437 | pc |= 0x01; | |
1438 | break; | |
1439 | } | |
6d82d43b | 1440 | case 4: /* beqz */ |
12f02c2a AC |
1441 | { |
1442 | struct upk_mips16 upk; | |
1443 | int reg; | |
1444 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1445 | reg = read_signed_register (upk.regx); | |
1446 | if (reg == 0) | |
1447 | pc += (upk.offset << 1) + 2; | |
1448 | else | |
1449 | pc += 2; | |
1450 | break; | |
1451 | } | |
6d82d43b | 1452 | case 5: /* bnez */ |
12f02c2a AC |
1453 | { |
1454 | struct upk_mips16 upk; | |
1455 | int reg; | |
1456 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1457 | reg = read_signed_register (upk.regx); | |
1458 | if (reg != 0) | |
1459 | pc += (upk.offset << 1) + 2; | |
1460 | else | |
1461 | pc += 2; | |
1462 | break; | |
1463 | } | |
6d82d43b | 1464 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1465 | { |
1466 | struct upk_mips16 upk; | |
1467 | int reg; | |
1468 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1469 | /* upk.regx contains the opcode */ | |
1470 | reg = read_signed_register (24); /* Test register is 24 */ | |
1471 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1472 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1473 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1474 | pc += (upk.offset << 1) + 2; | |
1475 | else | |
1476 | pc += 2; | |
1477 | break; | |
1478 | } | |
6d82d43b | 1479 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1480 | { |
1481 | struct upk_mips16 upk; | |
1482 | /* upk.fmt = rrtype; */ | |
1483 | op = insn & 0x1f; | |
1484 | if (op == 0) | |
c5aa993b | 1485 | { |
12f02c2a AC |
1486 | int reg; |
1487 | upk.regx = (insn >> 8) & 0x07; | |
1488 | upk.regy = (insn >> 5) & 0x07; | |
1489 | switch (upk.regy) | |
c5aa993b | 1490 | { |
12f02c2a AC |
1491 | case 0: |
1492 | reg = upk.regx; | |
1493 | break; | |
1494 | case 1: | |
1495 | reg = 31; | |
6d82d43b | 1496 | break; /* Function return instruction */ |
12f02c2a AC |
1497 | case 2: |
1498 | reg = upk.regx; | |
1499 | break; | |
1500 | default: | |
1501 | reg = 31; | |
6d82d43b | 1502 | break; /* BOGUS Guess */ |
c906108c | 1503 | } |
12f02c2a | 1504 | pc = read_signed_register (reg); |
c906108c | 1505 | } |
12f02c2a | 1506 | else |
c5aa993b | 1507 | pc += 2; |
12f02c2a AC |
1508 | break; |
1509 | } | |
1510 | case 30: | |
1511 | /* This is an instruction extension. Fetch the real instruction | |
1512 | (which follows the extension) and decode things based on | |
1513 | that. */ | |
1514 | { | |
1515 | pc += 2; | |
1516 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1517 | break; | |
1518 | } | |
1519 | default: | |
1520 | { | |
1521 | pc += 2; | |
1522 | break; | |
1523 | } | |
c906108c | 1524 | } |
c5aa993b | 1525 | return pc; |
12f02c2a | 1526 | } |
c906108c | 1527 | |
5a89d8aa | 1528 | static CORE_ADDR |
12f02c2a AC |
1529 | mips16_next_pc (CORE_ADDR pc) |
1530 | { | |
1531 | unsigned int insn = fetch_mips_16 (pc); | |
1532 | return extended_mips16_next_pc (pc, 0, insn); | |
1533 | } | |
1534 | ||
1535 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1536 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1537 | It works by decoding the current instruction and predicting where a |
1538 | branch will go. This isnt hard because all the data is available. | |
1539 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1540 | CORE_ADDR |
1541 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1542 | { |
c5aa993b JM |
1543 | if (pc & 0x01) |
1544 | return mips16_next_pc (pc); | |
1545 | else | |
1546 | return mips32_next_pc (pc); | |
12f02c2a | 1547 | } |
c906108c | 1548 | |
edfae063 AC |
1549 | struct mips_frame_cache |
1550 | { | |
1551 | CORE_ADDR base; | |
1552 | struct trad_frame_saved_reg *saved_regs; | |
1553 | }; | |
1554 | ||
1555 | ||
1556 | static struct mips_frame_cache * | |
1557 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1558 | { | |
0d5febcc | 1559 | CORE_ADDR startaddr = 0; |
edfae063 AC |
1560 | mips_extra_func_info_t proc_desc; |
1561 | struct mips_frame_cache *cache; | |
1562 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1563 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1564 | /* r0 bit means kernel trap */ | |
1565 | int kernel_trap; | |
1566 | /* What registers have been saved? Bitmasks. */ | |
1567 | unsigned long gen_mask, float_mask; | |
1568 | ||
1569 | if ((*this_cache) != NULL) | |
1570 | return (*this_cache); | |
1571 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1572 | (*this_cache) = cache; | |
1573 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1574 | ||
1575 | /* Get the mdebug proc descriptor. */ | |
0d5febcc AC |
1576 | proc_desc = non_heuristic_proc_desc (frame_pc_unwind (next_frame), |
1577 | &startaddr); | |
1578 | /* Must be true. This is only called when the sniffer detected a | |
1579 | proc descriptor. */ | |
1580 | gdb_assert (proc_desc != NULL); | |
edfae063 AC |
1581 | |
1582 | /* Extract the frame's base. */ | |
1583 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1584 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1585 | ||
1586 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1587 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1588 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1589 | ||
9733cfe1 AC |
1590 | /* Must be true. The in_prologue case is left for the heuristic |
1591 | unwinder. This is always used on kernel traps. */ | |
1592 | gdb_assert (!in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1593 | || kernel_trap); | |
edfae063 AC |
1594 | |
1595 | /* Fill in the offsets for the registers which gen_mask says were | |
1596 | saved. */ | |
1597 | { | |
4fbbbd07 | 1598 | CORE_ADDR reg_position = (cache->base + PROC_REG_OFFSET (proc_desc)); |
edfae063 | 1599 | int ireg; |
4fbbbd07 | 1600 | |
edfae063 AC |
1601 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
1602 | if (gen_mask & 0x80000000) | |
1603 | { | |
1604 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1605 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1606 | } |
1607 | } | |
1608 | ||
1609 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1610 | order of that normally used by gcc. Therefore, we have to fetch | |
1611 | the first instruction of the function, and if it's an entry | |
1612 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1613 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1614 | { | |
1615 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1616 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1617 | /* entry */ | |
1618 | { | |
1619 | int reg; | |
1620 | int sreg_count = (inst >> 6) & 3; | |
1621 | ||
1622 | /* Check if the ra register was pushed on the stack. */ | |
1623 | CORE_ADDR reg_position = (cache->base | |
1624 | + PROC_REG_OFFSET (proc_desc)); | |
1625 | if (inst & 0x20) | |
13326b4e | 1626 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1627 | |
1628 | /* Check if the s0 and s1 registers were pushed on the | |
1629 | stack. */ | |
1630 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1631 | check. */ | |
1632 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1633 | { | |
1634 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1635 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1636 | } |
1637 | } | |
1638 | } | |
1639 | ||
1640 | /* Fill in the offsets for the registers which float_mask says were | |
1641 | saved. */ | |
1642 | { | |
1643 | CORE_ADDR reg_position = (cache->base | |
1644 | + PROC_FREG_OFFSET (proc_desc)); | |
1645 | int ireg; | |
1646 | /* Fill in the offsets for the float registers which float_mask | |
1647 | says were saved. */ | |
1648 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1649 | if (float_mask & 0x80000000) | |
1650 | { | |
13326b4e | 1651 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1652 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1653 | { | |
1654 | /* On a big endian 32 bit ABI, floating point registers | |
1655 | are paired to form doubles such that the most | |
1656 | significant part is in $f[N+1] and the least | |
1657 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1658 | registers are also spilled as a pair and stored as a | |
1659 | double. | |
1660 | ||
1661 | When little-endian the least significant part is | |
1662 | stored first leading to the memory order $f[N] and | |
1663 | then $f[N+1]. | |
1664 | ||
1665 | Unfortunately, when big-endian the most significant | |
1666 | part of the double is stored first, and the least | |
1667 | significant is stored second. This leads to the | |
1668 | registers being ordered in memory as firt $f[N+1] and | |
1669 | then $f[N]. | |
1670 | ||
1671 | For the big-endian case make certain that the | |
1672 | addresses point at the correct (swapped) locations | |
1673 | $f[N] and $f[N+1] pair (keep in mind that | |
1674 | reg_position is decremented each time through the | |
1675 | loop). */ | |
1676 | if ((ireg & 1)) | |
1677 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1678 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1679 | else |
1680 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1681 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1682 | } |
1683 | else | |
1684 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1685 | .addr = reg_position; | |
13326b4e | 1686 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1687 | } |
1688 | ||
1689 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1690 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1691 | } | |
1692 | ||
1693 | /* SP_REGNUM, contains the value and not the address. */ | |
f10683bb | 1694 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); |
edfae063 AC |
1695 | |
1696 | return (*this_cache); | |
1697 | } | |
1698 | ||
1699 | static void | |
1700 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1701 | struct frame_id *this_id) | |
1702 | { | |
1703 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1704 | this_cache); | |
1705 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1706 | } | |
1707 | ||
1708 | static void | |
1709 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1710 | void **this_cache, | |
1711 | int regnum, int *optimizedp, | |
1712 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1713 | int *realnump, void *valuep) | |
1714 | { | |
1715 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1716 | this_cache); | |
1f67027d AC |
1717 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
1718 | optimizedp, lvalp, addrp, realnump, valuep); | |
edfae063 AC |
1719 | } |
1720 | ||
1721 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1722 | { | |
1723 | NORMAL_FRAME, | |
1724 | mips_mdebug_frame_this_id, | |
1725 | mips_mdebug_frame_prev_register | |
1726 | }; | |
1727 | ||
1728 | static const struct frame_unwind * | |
1729 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1730 | { | |
eec63939 AC |
1731 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1732 | CORE_ADDR startaddr = 0; | |
1733 | mips_extra_func_info_t proc_desc; | |
1734 | int kernel_trap; | |
1735 | ||
1736 | /* Only use the mdebug frame unwinder on mdebug frames where all the | |
1737 | registers have been saved. Leave hard cases such as no mdebug or | |
1738 | in prologue for the heuristic unwinders. */ | |
1739 | ||
1740 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1741 | if (proc_desc == NULL) | |
1742 | return NULL; | |
1743 | ||
1744 | /* Not sure exactly what kernel_trap means, but if it means the | |
1745 | kernel saves the registers without a prologue doing it, we better | |
1746 | not examine the prologue to see whether registers have been saved | |
1747 | yet. */ | |
1748 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1749 | if (kernel_trap) | |
1750 | return &mips_mdebug_frame_unwind; | |
1751 | ||
1752 | /* In any frame other than the innermost or a frame interrupted by a | |
1753 | signal, we assume that all registers have been saved. This | |
1754 | assumes that all register saves in a function happen before the | |
1755 | first function call. */ | |
1756 | if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc))) | |
1757 | return &mips_mdebug_frame_unwind; | |
1758 | ||
1759 | return NULL; | |
edfae063 AC |
1760 | } |
1761 | ||
1762 | static CORE_ADDR | |
1763 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1764 | void **this_cache) | |
1765 | { | |
1766 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1767 | this_cache); | |
1768 | return info->base; | |
1769 | } | |
1770 | ||
1771 | static const struct frame_base mips_mdebug_frame_base = { | |
1772 | &mips_mdebug_frame_unwind, | |
1773 | mips_mdebug_frame_base_address, | |
1774 | mips_mdebug_frame_base_address, | |
1775 | mips_mdebug_frame_base_address | |
1776 | }; | |
1777 | ||
1778 | static const struct frame_base * | |
1779 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1780 | { | |
eec63939 AC |
1781 | if (mips_mdebug_frame_sniffer (next_frame) != NULL) |
1782 | return &mips_mdebug_frame_base; | |
1783 | else | |
1784 | return NULL; | |
1785 | } | |
1786 | ||
45c9dd44 AC |
1787 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1788 | Procedures that use the 32-bit instruction set are handled by the | |
1789 | mips_insn32 unwinder. */ | |
1790 | ||
eec63939 | 1791 | static struct mips_frame_cache * |
45c9dd44 | 1792 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 AC |
1793 | { |
1794 | mips_extra_func_info_t proc_desc; | |
1795 | struct mips_frame_cache *cache; | |
1796 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1797 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1798 | /* r0 bit means kernel trap */ | |
1799 | int kernel_trap; | |
1800 | /* What registers have been saved? Bitmasks. */ | |
1801 | unsigned long gen_mask, float_mask; | |
1802 | ||
1803 | if ((*this_cache) != NULL) | |
1804 | return (*this_cache); | |
1805 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1806 | (*this_cache) = cache; | |
1807 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1808 | ||
0d5febcc AC |
1809 | /* Synthesize a proc descriptor. */ |
1810 | { | |
1811 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1812 | CORE_ADDR start_addr; | |
eec63939 | 1813 | |
0d5febcc AC |
1814 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1815 | if (start_addr == 0) | |
1816 | start_addr = heuristic_proc_start (pc); | |
1817 | ||
1818 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame); | |
1819 | } | |
1820 | ||
eec63939 AC |
1821 | /* Extract the frame's base. */ |
1822 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1823 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1824 | ||
1825 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1826 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1827 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1828 | ||
1829 | /* In any frame other than the innermost or a frame interrupted by a | |
1830 | signal, we assume that all registers have been saved. This | |
1831 | assumes that all register saves in a function happen before the | |
1832 | first function call. */ | |
1833 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1834 | /* Not sure exactly what kernel_trap means, but if it means the | |
1835 | kernel saves the registers without a prologue doing it, we | |
1836 | better not examine the prologue to see whether registers | |
1837 | have been saved yet. */ | |
1838 | && !kernel_trap) | |
1839 | { | |
1840 | /* We need to figure out whether the registers that the | |
1841 | proc_desc claims are saved have been saved yet. */ | |
1842 | ||
1843 | CORE_ADDR addr; | |
1844 | ||
1845 | /* Bitmasks; set if we have found a save for the register. */ | |
1846 | unsigned long gen_save_found = 0; | |
1847 | unsigned long float_save_found = 0; | |
1848 | int mips16; | |
1849 | ||
1850 | /* If the address is odd, assume this is MIPS16 code. */ | |
1851 | addr = PROC_LOW_ADDR (proc_desc); | |
1852 | mips16 = pc_is_mips16 (addr); | |
1853 | ||
1854 | /* Scan through this function's instructions preceding the | |
1855 | current PC, and look for those that save registers. */ | |
1856 | while (addr < frame_pc_unwind (next_frame)) | |
1857 | { | |
1858 | if (mips16) | |
1859 | { | |
1860 | mips16_decode_reg_save (mips16_fetch_instruction (addr), | |
1861 | &gen_save_found); | |
1862 | addr += MIPS16_INSTLEN; | |
1863 | } | |
1864 | else | |
1865 | { | |
1866 | mips32_decode_reg_save (mips32_fetch_instruction (addr), | |
1867 | &gen_save_found, &float_save_found); | |
1868 | addr += MIPS_INSTLEN; | |
1869 | } | |
1870 | } | |
1871 | gen_mask = gen_save_found; | |
1872 | float_mask = float_save_found; | |
1873 | } | |
1874 | ||
1875 | /* Fill in the offsets for the registers which gen_mask says were | |
1876 | saved. */ | |
1877 | { | |
1878 | CORE_ADDR reg_position = (cache->base | |
1879 | + PROC_REG_OFFSET (proc_desc)); | |
1880 | int ireg; | |
1881 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
1882 | if (gen_mask & 0x80000000) | |
1883 | { | |
1884 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
1885 | reg_position -= mips_abi_regsize (gdbarch); | |
1886 | } | |
1887 | } | |
1888 | ||
1889 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1890 | order of that normally used by gcc. Therefore, we have to fetch | |
1891 | the first instruction of the function, and if it's an entry | |
1892 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
1893 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1894 | { | |
1895 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1896 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1897 | /* entry */ | |
1898 | { | |
1899 | int reg; | |
1900 | int sreg_count = (inst >> 6) & 3; | |
1901 | ||
1902 | /* Check if the ra register was pushed on the stack. */ | |
1903 | CORE_ADDR reg_position = (cache->base | |
1904 | + PROC_REG_OFFSET (proc_desc)); | |
1905 | if (inst & 0x20) | |
1906 | reg_position -= mips_abi_regsize (gdbarch); | |
1907 | ||
1908 | /* Check if the s0 and s1 registers were pushed on the | |
1909 | stack. */ | |
1910 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1911 | check. */ | |
1912 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1913 | { | |
1914 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
1915 | reg_position -= mips_abi_regsize (gdbarch); | |
1916 | } | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | /* Fill in the offsets for the registers which float_mask says were | |
1921 | saved. */ | |
1922 | { | |
1923 | CORE_ADDR reg_position = (cache->base | |
1924 | + PROC_FREG_OFFSET (proc_desc)); | |
1925 | int ireg; | |
1926 | /* Fill in the offsets for the float registers which float_mask | |
1927 | says were saved. */ | |
1928 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1929 | if (float_mask & 0x80000000) | |
1930 | { | |
1931 | if (mips_abi_regsize (gdbarch) == 4 | |
1932 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1933 | { | |
1934 | /* On a big endian 32 bit ABI, floating point registers | |
1935 | are paired to form doubles such that the most | |
1936 | significant part is in $f[N+1] and the least | |
1937 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1938 | registers are also spilled as a pair and stored as a | |
1939 | double. | |
1940 | ||
1941 | When little-endian the least significant part is | |
1942 | stored first leading to the memory order $f[N] and | |
1943 | then $f[N+1]. | |
1944 | ||
1945 | Unfortunately, when big-endian the most significant | |
1946 | part of the double is stored first, and the least | |
1947 | significant is stored second. This leads to the | |
1948 | registers being ordered in memory as firt $f[N+1] and | |
1949 | then $f[N]. | |
1950 | ||
1951 | For the big-endian case make certain that the | |
1952 | addresses point at the correct (swapped) locations | |
1953 | $f[N] and $f[N+1] pair (keep in mind that | |
1954 | reg_position is decremented each time through the | |
1955 | loop). */ | |
1956 | if ((ireg & 1)) | |
1957 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1958 | .addr = reg_position - mips_abi_regsize (gdbarch); | |
1959 | else | |
1960 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1961 | .addr = reg_position + mips_abi_regsize (gdbarch); | |
1962 | } | |
1963 | else | |
1964 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1965 | .addr = reg_position; | |
1966 | reg_position -= mips_abi_regsize (gdbarch); | |
1967 | } | |
1968 | ||
1969 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
1970 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
1971 | } | |
1972 | ||
1973 | /* SP_REGNUM, contains the value and not the address. */ | |
1974 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
1975 | ||
1976 | return (*this_cache); | |
1977 | } | |
1978 | ||
1979 | static void | |
45c9dd44 | 1980 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
1981 | struct frame_id *this_id) |
1982 | { | |
45c9dd44 | 1983 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1984 | this_cache); |
1985 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1986 | } | |
1987 | ||
1988 | static void | |
45c9dd44 | 1989 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1990 | void **this_cache, |
1991 | int regnum, int *optimizedp, | |
1992 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1993 | int *realnump, void *valuep) | |
1994 | { | |
45c9dd44 | 1995 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
1996 | this_cache); |
1997 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1998 | optimizedp, lvalp, addrp, realnump, valuep); | |
1999 | } | |
2000 | ||
45c9dd44 | 2001 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2002 | { |
2003 | NORMAL_FRAME, | |
45c9dd44 AC |
2004 | mips_insn16_frame_this_id, |
2005 | mips_insn16_frame_prev_register | |
eec63939 AC |
2006 | }; |
2007 | ||
2008 | static const struct frame_unwind * | |
45c9dd44 | 2009 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2010 | { |
2011 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2012 | if (pc_is_mips16 (pc)) | |
45c9dd44 | 2013 | return &mips_insn16_frame_unwind; |
eec63939 AC |
2014 | return NULL; |
2015 | } | |
2016 | ||
2017 | static CORE_ADDR | |
45c9dd44 | 2018 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
2019 | void **this_cache) |
2020 | { | |
45c9dd44 | 2021 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
eec63939 AC |
2022 | this_cache); |
2023 | return info->base; | |
2024 | } | |
2025 | ||
45c9dd44 | 2026 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2027 | { |
45c9dd44 AC |
2028 | &mips_insn16_frame_unwind, |
2029 | mips_insn16_frame_base_address, | |
2030 | mips_insn16_frame_base_address, | |
2031 | mips_insn16_frame_base_address | |
eec63939 AC |
2032 | }; |
2033 | ||
2034 | static const struct frame_base * | |
45c9dd44 | 2035 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2036 | { |
45c9dd44 AC |
2037 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
2038 | return &mips_insn16_frame_base; | |
eec63939 AC |
2039 | else |
2040 | return NULL; | |
2041 | } | |
2042 | ||
45c9dd44 AC |
2043 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2044 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2045 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2046 | unwinder. */ | |
2047 | ||
eec63939 | 2048 | static struct mips_frame_cache * |
45c9dd44 | 2049 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) |
eec63939 AC |
2050 | { |
2051 | mips_extra_func_info_t proc_desc; | |
2052 | struct mips_frame_cache *cache; | |
2053 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2054 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2055 | /* r0 bit means kernel trap */ | |
2056 | int kernel_trap; | |
2057 | /* What registers have been saved? Bitmasks. */ | |
2058 | unsigned long gen_mask, float_mask; | |
2059 | ||
2060 | if ((*this_cache) != NULL) | |
2061 | return (*this_cache); | |
2062 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2063 | (*this_cache) = cache; | |
2064 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2065 | ||
a343eb3c JB |
2066 | /* Synthesize a proc descriptor. */ |
2067 | { | |
2068 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2069 | CORE_ADDR start_addr; | |
2070 | ||
2071 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2072 | if (start_addr == 0) | |
2073 | start_addr = heuristic_proc_start (pc); | |
2074 | ||
465f7520 | 2075 | proc_desc = heuristic_proc_desc (start_addr, pc, next_frame); |
a343eb3c JB |
2076 | } |
2077 | ||
eec63939 AC |
2078 | if (proc_desc == NULL) |
2079 | /* I'm not sure how/whether this can happen. Normally when we | |
2080 | can't find a proc_desc, we "synthesize" one using | |
2081 | heuristic_proc_desc and set the saved_regs right away. */ | |
2082 | return cache; | |
2083 | ||
2084 | /* Extract the frame's base. */ | |
2085 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
2086 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
2087 | ||
2088 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
2089 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
2090 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
2091 | ||
2092 | /* In any frame other than the innermost or a frame interrupted by a | |
2093 | signal, we assume that all registers have been saved. This | |
2094 | assumes that all register saves in a function happen before the | |
2095 | first function call. */ | |
2096 | if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
2097 | /* Not sure exactly what kernel_trap means, but if it means the | |
2098 | kernel saves the registers without a prologue doing it, we | |
2099 | better not examine the prologue to see whether registers | |
2100 | have been saved yet. */ | |
2101 | && !kernel_trap) | |
2102 | { | |
2103 | /* We need to figure out whether the registers that the | |
2104 | proc_desc claims are saved have been saved yet. */ | |
2105 | ||
2106 | CORE_ADDR addr; | |
2107 | ||
2108 | /* Bitmasks; set if we have found a save for the register. */ | |
2109 | unsigned long gen_save_found = 0; | |
2110 | unsigned long float_save_found = 0; | |
eec63939 | 2111 | |
eec63939 | 2112 | addr = PROC_LOW_ADDR (proc_desc); |
eec63939 AC |
2113 | |
2114 | /* Scan through this function's instructions preceding the | |
2115 | current PC, and look for those that save registers. */ | |
2116 | while (addr < frame_pc_unwind (next_frame)) | |
2117 | { | |
8ac2e020 JB |
2118 | mips32_decode_reg_save (mips32_fetch_instruction (addr), |
2119 | &gen_save_found, &float_save_found); | |
2120 | addr += MIPS_INSTLEN; | |
eec63939 AC |
2121 | } |
2122 | gen_mask = gen_save_found; | |
2123 | float_mask = float_save_found; | |
2124 | } | |
2125 | ||
2126 | /* Fill in the offsets for the registers which gen_mask says were | |
2127 | saved. */ | |
2128 | { | |
2129 | CORE_ADDR reg_position = (cache->base | |
2130 | + PROC_REG_OFFSET (proc_desc)); | |
2131 | int ireg; | |
2132 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) | |
2133 | if (gen_mask & 0x80000000) | |
2134 | { | |
2135 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
2136 | reg_position -= mips_abi_regsize (gdbarch); | |
2137 | } | |
2138 | } | |
2139 | ||
eec63939 AC |
2140 | /* Fill in the offsets for the registers which float_mask says were |
2141 | saved. */ | |
2142 | { | |
8ac2e020 | 2143 | CORE_ADDR reg_position = (cache->base + PROC_FREG_OFFSET (proc_desc)); |
eec63939 | 2144 | int ireg; |
8ac2e020 | 2145 | |
eec63939 AC |
2146 | /* Fill in the offsets for the float registers which float_mask |
2147 | says were saved. */ | |
2148 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
2149 | if (float_mask & 0x80000000) | |
2150 | { | |
8ac2e020 JB |
2151 | const int regno = |
2152 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg; | |
2153 | ||
eec63939 AC |
2154 | if (mips_abi_regsize (gdbarch) == 4 |
2155 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2156 | { | |
2157 | /* On a big endian 32 bit ABI, floating point registers | |
2158 | are paired to form doubles such that the most | |
2159 | significant part is in $f[N+1] and the least | |
2160 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
2161 | registers are also spilled as a pair and stored as a | |
2162 | double. | |
2163 | ||
2164 | When little-endian the least significant part is | |
2165 | stored first leading to the memory order $f[N] and | |
2166 | then $f[N+1]. | |
2167 | ||
2168 | Unfortunately, when big-endian the most significant | |
2169 | part of the double is stored first, and the least | |
2170 | significant is stored second. This leads to the | |
2171 | registers being ordered in memory as firt $f[N+1] and | |
2172 | then $f[N]. | |
2173 | ||
2174 | For the big-endian case make certain that the | |
2175 | addresses point at the correct (swapped) locations | |
2176 | $f[N] and $f[N+1] pair (keep in mind that | |
2177 | reg_position is decremented each time through the | |
2178 | loop). */ | |
2179 | if ((ireg & 1)) | |
8ac2e020 JB |
2180 | cache->saved_regs[regno].addr = |
2181 | reg_position - mips_abi_regsize (gdbarch); | |
eec63939 | 2182 | else |
8ac2e020 JB |
2183 | cache->saved_regs[regno].addr = |
2184 | reg_position + mips_abi_regsize (gdbarch); | |
eec63939 AC |
2185 | } |
2186 | else | |
8ac2e020 | 2187 | cache->saved_regs[regno].addr = reg_position; |
eec63939 AC |
2188 | reg_position -= mips_abi_regsize (gdbarch); |
2189 | } | |
2190 | ||
2191 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
2192 | = cache->saved_regs[NUM_REGS + RA_REGNUM]; | |
2193 | } | |
2194 | ||
2195 | /* SP_REGNUM, contains the value and not the address. */ | |
2196 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
2197 | ||
2198 | return (*this_cache); | |
2199 | } | |
2200 | ||
2201 | static void | |
45c9dd44 | 2202 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, |
eec63939 AC |
2203 | struct frame_id *this_id) |
2204 | { | |
45c9dd44 | 2205 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2206 | this_cache); |
2207 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2208 | } | |
2209 | ||
2210 | static void | |
45c9dd44 | 2211 | mips_insn32_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
2212 | void **this_cache, |
2213 | int regnum, int *optimizedp, | |
2214 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2215 | int *realnump, void *valuep) | |
2216 | { | |
45c9dd44 | 2217 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2218 | this_cache); |
2219 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2220 | optimizedp, lvalp, addrp, realnump, valuep); | |
2221 | } | |
2222 | ||
45c9dd44 | 2223 | static const struct frame_unwind mips_insn32_frame_unwind = |
eec63939 AC |
2224 | { |
2225 | NORMAL_FRAME, | |
45c9dd44 AC |
2226 | mips_insn32_frame_this_id, |
2227 | mips_insn32_frame_prev_register | |
eec63939 AC |
2228 | }; |
2229 | ||
2230 | static const struct frame_unwind * | |
45c9dd44 | 2231 | mips_insn32_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2232 | { |
2233 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2234 | if (! pc_is_mips16 (pc)) | |
45c9dd44 | 2235 | return &mips_insn32_frame_unwind; |
eec63939 AC |
2236 | return NULL; |
2237 | } | |
2238 | ||
2239 | static CORE_ADDR | |
45c9dd44 | 2240 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
eec63939 AC |
2241 | void **this_cache) |
2242 | { | |
45c9dd44 | 2243 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
eec63939 AC |
2244 | this_cache); |
2245 | return info->base; | |
2246 | } | |
2247 | ||
45c9dd44 | 2248 | static const struct frame_base mips_insn32_frame_base = |
eec63939 | 2249 | { |
45c9dd44 AC |
2250 | &mips_insn32_frame_unwind, |
2251 | mips_insn32_frame_base_address, | |
2252 | mips_insn32_frame_base_address, | |
2253 | mips_insn32_frame_base_address | |
eec63939 AC |
2254 | }; |
2255 | ||
2256 | static const struct frame_base * | |
45c9dd44 | 2257 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2258 | { |
45c9dd44 AC |
2259 | if (mips_insn32_frame_sniffer (next_frame) != NULL) |
2260 | return &mips_insn32_frame_base; | |
eec63939 AC |
2261 | else |
2262 | return NULL; | |
2263 | } | |
2264 | ||
2265 | static struct trad_frame_cache * | |
2266 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2267 | { | |
2268 | CORE_ADDR pc; | |
2269 | CORE_ADDR start_addr; | |
2270 | CORE_ADDR stack_addr; | |
2271 | struct trad_frame_cache *this_trad_cache; | |
2272 | ||
2273 | if ((*this_cache) != NULL) | |
2274 | return (*this_cache); | |
2275 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2276 | (*this_cache) = this_trad_cache; | |
2277 | ||
2278 | /* The return address is in the link register. */ | |
2279 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, RA_REGNUM); | |
2280 | ||
2281 | /* Frame ID, since it's a frameless / stackless function, no stack | |
2282 | space is allocated and SP on entry is the current SP. */ | |
2283 | pc = frame_pc_unwind (next_frame); | |
2284 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2285 | stack_addr = frame_unwind_register_signed (next_frame, SP_REGNUM); | |
2286 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); | |
2287 | ||
2288 | /* Assume that the frame's base is the same as the | |
2289 | stack-pointer. */ | |
2290 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
2291 | ||
2292 | return this_trad_cache; | |
2293 | } | |
2294 | ||
2295 | static void | |
2296 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2297 | struct frame_id *this_id) | |
2298 | { | |
2299 | struct trad_frame_cache *this_trad_cache | |
2300 | = mips_stub_frame_cache (next_frame, this_cache); | |
2301 | trad_frame_get_id (this_trad_cache, this_id); | |
2302 | } | |
2303 | ||
2304 | static void | |
2305 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2306 | void **this_cache, | |
2307 | int regnum, int *optimizedp, | |
2308 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2309 | int *realnump, void *valuep) | |
2310 | { | |
2311 | struct trad_frame_cache *this_trad_cache | |
2312 | = mips_stub_frame_cache (next_frame, this_cache); | |
2313 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2314 | lvalp, addrp, realnump, valuep); | |
2315 | } | |
2316 | ||
2317 | static const struct frame_unwind mips_stub_frame_unwind = | |
2318 | { | |
2319 | NORMAL_FRAME, | |
2320 | mips_stub_frame_this_id, | |
2321 | mips_stub_frame_prev_register | |
2322 | }; | |
2323 | ||
2324 | static const struct frame_unwind * | |
2325 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2326 | { | |
2327 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2328 | if (in_plt_section (pc, NULL)) | |
2329 | return &mips_stub_frame_unwind; | |
2330 | else | |
2331 | return NULL; | |
2332 | } | |
2333 | ||
2334 | static CORE_ADDR | |
2335 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2336 | void **this_cache) | |
2337 | { | |
2338 | struct trad_frame_cache *this_trad_cache | |
2339 | = mips_stub_frame_cache (next_frame, this_cache); | |
2340 | return trad_frame_get_this_base (this_trad_cache); | |
2341 | } | |
2342 | ||
2343 | static const struct frame_base mips_stub_frame_base = | |
2344 | { | |
2345 | &mips_stub_frame_unwind, | |
2346 | mips_stub_frame_base_address, | |
2347 | mips_stub_frame_base_address, | |
2348 | mips_stub_frame_base_address | |
2349 | }; | |
2350 | ||
2351 | static const struct frame_base * | |
2352 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2353 | { | |
2354 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2355 | return &mips_stub_frame_base; | |
2356 | else | |
2357 | return NULL; | |
edfae063 AC |
2358 | } |
2359 | ||
c906108c | 2360 | static CORE_ADDR |
acdb74a0 | 2361 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c | 2362 | { |
a4b8ebc8 AC |
2363 | /* Always a pseudo. */ |
2364 | gdb_assert (regno >= NUM_REGS); | |
f796e4be | 2365 | if (fi == NULL) |
c906108c | 2366 | { |
a4b8ebc8 AC |
2367 | LONGEST val; |
2368 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2369 | return val; | |
f796e4be | 2370 | } |
f10683bb MH |
2371 | else if ((regno % NUM_REGS) == MIPS_SP_REGNUM) |
2372 | /* MIPS_SP_REGNUM is special, its value is stored in saved_regs. | |
a4b8ebc8 AC |
2373 | In fact, it is so special that it can even only be fetched |
2374 | using a raw register number! Once this code as been converted | |
2375 | to frame-unwind the problem goes away. */ | |
2376 | return frame_unwind_register_signed (fi, regno % NUM_REGS); | |
f796e4be | 2377 | else |
a4b8ebc8 | 2378 | return frame_unwind_register_signed (fi, regno); |
64159455 | 2379 | |
c906108c SS |
2380 | } |
2381 | ||
2382 | /* mips_addr_bits_remove - remove useless address bits */ | |
2383 | ||
875e1767 | 2384 | static CORE_ADDR |
acdb74a0 | 2385 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 2386 | { |
480d3dd2 | 2387 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
6d82d43b | 2388 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
8fa9cfa1 AC |
2389 | /* This hack is a work-around for existing boards using PMON, the |
2390 | simulator, and any other 64-bit targets that doesn't have true | |
2391 | 64-bit addressing. On these targets, the upper 32 bits of | |
2392 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2393 | likely to have been sign extended to all 1s by instruction | |
2394 | sequences that load 32-bit addresses. For example, a typical | |
2395 | piece of code that loads an address is this: | |
2396 | ||
2397 | lui $r2, <upper 16 bits> | |
2398 | ori $r2, <lower 16 bits> | |
2399 | ||
2400 | But the lui sign-extends the value such that the upper 32 bits | |
2401 | may be all 1s. The workaround is simply to mask off these | |
2402 | bits. In the future, gcc may be changed to support true 64-bit | |
2403 | addressing, and this masking will have to be disabled. */ | |
2404 | return addr &= 0xffffffffUL; | |
2405 | else | |
2406 | return addr; | |
c906108c SS |
2407 | } |
2408 | ||
9022177c DJ |
2409 | /* mips_software_single_step() is called just before we want to resume |
2410 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 2411 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
2412 | the target of the coming instruction and breakpoint it. |
2413 | ||
2414 | single_step is also called just after the inferior stops. If we had | |
2415 | set up a simulated single-step, we undo our damage. */ | |
2416 | ||
2417 | void | |
2418 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
2419 | { | |
2420 | static CORE_ADDR next_pc; | |
2421 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2422 | static binsn_quantum break_mem; | |
2423 | CORE_ADDR pc; | |
2424 | ||
2425 | if (insert_breakpoints_p) | |
2426 | { | |
b6cb9035 | 2427 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
9022177c DJ |
2428 | next_pc = mips_next_pc (pc); |
2429 | ||
2430 | target_insert_breakpoint (next_pc, break_mem); | |
2431 | } | |
2432 | else | |
2433 | target_remove_breakpoint (next_pc, break_mem); | |
2434 | } | |
2435 | ||
c906108c | 2436 | static struct mips_extra_func_info temp_proc_desc; |
fe29b929 KB |
2437 | |
2438 | /* This hack will go away once the get_prev_frame() code has been | |
2439 | modified to set the frame's type first. That is BEFORE init extra | |
2440 | frame info et.al. is called. This is because it will become | |
2441 | possible to skip the init extra info call for sigtramp and dummy | |
2442 | frames. */ | |
2443 | static CORE_ADDR *temp_saved_regs; | |
c906108c | 2444 | |
e0f7ec59 AC |
2445 | /* Set a register's saved stack address in temp_saved_regs. If an |
2446 | address has already been set for this register, do nothing; this | |
2447 | way we will only recognize the first save of a given register in a | |
a4b8ebc8 AC |
2448 | function prologue. |
2449 | ||
2450 | For simplicity, save the address in both [0 .. NUM_REGS) and | |
2451 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
2452 | is used as it is only second range (the ABI instead of ISA | |
2453 | registers) that comes into play when finding saved registers in a | |
2454 | frame. */ | |
c906108c SS |
2455 | |
2456 | static void | |
e0f7ec59 | 2457 | set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) |
c906108c | 2458 | { |
e0f7ec59 | 2459 | if (saved_regs[regno] == 0) |
a4b8ebc8 AC |
2460 | { |
2461 | saved_regs[regno + 0 * NUM_REGS] = offset; | |
2462 | saved_regs[regno + 1 * NUM_REGS] = offset; | |
2463 | } | |
c906108c SS |
2464 | } |
2465 | ||
2466 | ||
2467 | /* Test whether the PC points to the return instruction at the | |
2468 | end of a function. */ | |
2469 | ||
c5aa993b | 2470 | static int |
acdb74a0 | 2471 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
2472 | { |
2473 | if (pc_is_mips16 (pc)) | |
2474 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
2475 | generates a "jr $ra"; other times it generates code to load | |
2476 | the return address from the stack to an accessible register (such | |
2477 | as $a3), then a "jr" using that register. This second case | |
2478 | is almost impossible to distinguish from an indirect jump | |
2479 | used for switch statements, so we don't even try. */ | |
2480 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2481 | else | |
2482 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2483 | } | |
2484 | ||
2485 | ||
2486 | /* This fencepost looks highly suspicious to me. Removing it also | |
2487 | seems suspicious as it could affect remote debugging across serial | |
2488 | lines. */ | |
2489 | ||
2490 | static CORE_ADDR | |
acdb74a0 | 2491 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 2492 | { |
c5aa993b JM |
2493 | CORE_ADDR start_pc; |
2494 | CORE_ADDR fence; | |
2495 | int instlen; | |
2496 | int seen_adjsp = 0; | |
c906108c | 2497 | |
c5aa993b JM |
2498 | pc = ADDR_BITS_REMOVE (pc); |
2499 | start_pc = pc; | |
2500 | fence = start_pc - heuristic_fence_post; | |
2501 | if (start_pc == 0) | |
2502 | return 0; | |
c906108c | 2503 | |
6d82d43b | 2504 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
c5aa993b | 2505 | fence = VM_MIN_ADDRESS; |
c906108c | 2506 | |
c5aa993b | 2507 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 2508 | |
c5aa993b JM |
2509 | /* search back for previous return */ |
2510 | for (start_pc -= instlen;; start_pc -= instlen) | |
2511 | if (start_pc < fence) | |
2512 | { | |
2513 | /* It's not clear to me why we reach this point when | |
c0236d92 | 2514 | stop_soon, but with this test, at least we |
c5aa993b JM |
2515 | don't print out warnings for every child forked (eg, on |
2516 | decstation). 22apr93 rich@cygnus.com. */ | |
c0236d92 | 2517 | if (stop_soon == NO_STOP_QUIETLY) |
c906108c | 2518 | { |
c5aa993b JM |
2519 | static int blurb_printed = 0; |
2520 | ||
dc305454 MS |
2521 | warning ("GDB can't find the start of the function at 0x%s.", |
2522 | paddr_nz (pc)); | |
c5aa993b JM |
2523 | |
2524 | if (!blurb_printed) | |
c906108c | 2525 | { |
c5aa993b JM |
2526 | /* This actually happens frequently in embedded |
2527 | development, when you first connect to a board | |
2528 | and your stack pointer and pc are nowhere in | |
2529 | particular. This message needs to give people | |
2530 | in that situation enough information to | |
2531 | determine that it's no big deal. */ | |
2532 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
2533 | GDB is unable to find the start of the function at 0x%s\n\ |
2534 | and thus can't determine the size of that function's stack frame.\n\ | |
2535 | This means that GDB may be unable to access that stack frame, or\n\ | |
2536 | the frames below it.\n\ | |
2537 | This problem is most likely caused by an invalid program counter or\n\ | |
2538 | stack pointer.\n\ | |
2539 | However, if you think GDB should simply search farther back\n\ | |
2540 | from 0x%s for code which looks like the beginning of a\n\ | |
2541 | function, you can increase the range of the search using the `set\n\ | |
6d82d43b | 2542 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); |
c5aa993b | 2543 | blurb_printed = 1; |
c906108c | 2544 | } |
c906108c SS |
2545 | } |
2546 | ||
c5aa993b JM |
2547 | return 0; |
2548 | } | |
2549 | else if (pc_is_mips16 (start_pc)) | |
2550 | { | |
2551 | unsigned short inst; | |
2552 | ||
2553 | /* On MIPS16, any one of the following is likely to be the | |
2554 | start of a function: | |
2555 | entry | |
2556 | addiu sp,-n | |
2557 | daddiu sp,-n | |
2558 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2559 | inst = mips_fetch_instruction (start_pc); | |
2560 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2561 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2562 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2563 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2564 | break; | |
2565 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2566 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2567 | seen_adjsp = 1; | |
2568 | else | |
2569 | seen_adjsp = 0; | |
2570 | } | |
2571 | else if (mips_about_to_return (start_pc)) | |
2572 | { | |
2573 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
2574 | break; | |
2575 | } | |
2576 | ||
c5aa993b | 2577 | return start_pc; |
c906108c SS |
2578 | } |
2579 | ||
2580 | /* Fetch the immediate value from a MIPS16 instruction. | |
2581 | If the previous instruction was an EXTEND, use it to extend | |
2582 | the upper bits of the immediate value. This is a helper function | |
2583 | for mips16_heuristic_proc_desc. */ | |
2584 | ||
2585 | static int | |
acdb74a0 AC |
2586 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
2587 | unsigned short inst, /* current instruction */ | |
6d82d43b AC |
2588 | int nbits, /* number of bits in imm field */ |
2589 | int scale, /* scale factor to be applied to imm */ | |
2590 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
2591 | { |
2592 | int offset; | |
2593 | ||
2594 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
2595 | { | |
2596 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 2597 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
2598 | offset = 0 - (0x10000 - (offset & 0xffff)); |
2599 | return offset | (inst & 0x1f); | |
2600 | } | |
2601 | else | |
2602 | { | |
2603 | int max_imm = 1 << nbits; | |
2604 | int mask = max_imm - 1; | |
2605 | int sign_bit = max_imm >> 1; | |
2606 | ||
2607 | offset = inst & mask; | |
2608 | if (is_signed && (offset & sign_bit)) | |
2609 | offset = 0 - (max_imm - offset); | |
2610 | return offset * scale; | |
2611 | } | |
2612 | } | |
2613 | ||
2614 | ||
2615 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
2616 | stream from start_pc to limit_pc. */ | |
2617 | ||
2618 | static void | |
acdb74a0 AC |
2619 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2620 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2621 | { |
2622 | CORE_ADDR cur_pc; | |
2623 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
2624 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
2625 | unsigned inst = 0; /* current instruction */ | |
2626 | unsigned entry_inst = 0; /* the entry instruction */ | |
2627 | int reg, offset; | |
480d3dd2 | 2628 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 2629 | |
c5aa993b JM |
2630 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
2631 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
2632 | |
2633 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
2634 | { | |
2635 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2636 | the immediate offset extension from it in mips16_get_imm. */ | |
2637 | prev_inst = inst; | |
2638 | ||
2639 | /* Fetch and decode the instruction. */ | |
2640 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 2641 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
6d82d43b | 2642 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
c906108c SS |
2643 | { |
2644 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
2645 | if (offset < 0) /* negative stack adjustment? */ |
2646 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
2647 | else |
2648 | /* Exit loop if a positive stack adjustment is found, which | |
2649 | usually means that the stack cleanup code in the function | |
2650 | epilogue is reached. */ | |
2651 | break; | |
2652 | } | |
2653 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2654 | { | |
2655 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2656 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 2657 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2658 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2659 | } |
2660 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2661 | { | |
2662 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2663 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2664 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
e0f7ec59 | 2665 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
c906108c SS |
2666 | } |
2667 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2668 | { | |
2669 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 2670 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2671 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c SS |
2672 | } |
2673 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2674 | { | |
2675 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 2676 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
e0f7ec59 | 2677 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
c906108c | 2678 | } |
c5aa993b | 2679 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
2680 | { |
2681 | frame_addr = sp; | |
2682 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2683 | } | |
2684 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2685 | { | |
2686 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2687 | frame_addr = sp + offset; | |
2688 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
2689 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
2690 | } | |
2691 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2692 | { | |
2693 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
2694 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2695 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2696 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c SS |
2697 | } |
2698 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2699 | { | |
2700 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
2701 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 2702 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2703 | set_reg_offset (temp_saved_regs, reg, frame_addr + offset); |
c906108c | 2704 | } |
c5aa993b JM |
2705 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
2706 | entry_inst = inst; /* save for later processing */ | |
c906108c | 2707 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 2708 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
2709 | } |
2710 | ||
c5aa993b JM |
2711 | /* The entry instruction is typically the first instruction in a function, |
2712 | and it stores registers at offsets relative to the value of the old SP | |
2713 | (before the prologue). But the value of the sp parameter to this | |
2714 | function is the new SP (after the prologue has been executed). So we | |
2715 | can't calculate those offsets until we've seen the entire prologue, | |
2716 | and can calculate what the old SP must have been. */ | |
2717 | if (entry_inst != 0) | |
2718 | { | |
2719 | int areg_count = (entry_inst >> 8) & 7; | |
2720 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 2721 | |
c5aa993b JM |
2722 | /* The entry instruction always subtracts 32 from the SP. */ |
2723 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 2724 | |
c5aa993b JM |
2725 | /* Now we can calculate what the SP must have been at the |
2726 | start of the function prologue. */ | |
2727 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 2728 | |
c5aa993b JM |
2729 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
2730 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2731 | { | |
2732 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2733 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
13326b4e | 2734 | offset += mips_abi_regsize (current_gdbarch); |
c5aa993b | 2735 | } |
c906108c | 2736 | |
c5aa993b JM |
2737 | /* Check if the ra register was pushed on the stack. */ |
2738 | offset = -4; | |
2739 | if (entry_inst & 0x20) | |
2740 | { | |
2741 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
e0f7ec59 | 2742 | set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); |
13326b4e | 2743 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b | 2744 | } |
c906108c | 2745 | |
c5aa993b JM |
2746 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
2747 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2748 | { | |
2749 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
e0f7ec59 | 2750 | set_reg_offset (temp_saved_regs, reg, sp + offset); |
13326b4e | 2751 | offset -= mips_abi_regsize (current_gdbarch); |
c5aa993b JM |
2752 | } |
2753 | } | |
c906108c SS |
2754 | } |
2755 | ||
2756 | static void | |
fba45db2 KB |
2757 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2758 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
2759 | { |
2760 | CORE_ADDR cur_pc; | |
c5aa993b | 2761 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 2762 | restart: |
fe29b929 | 2763 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
cce74817 | 2764 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 2765 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
2766 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
2767 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
2768 | { | |
2769 | unsigned long inst, high_word, low_word; | |
2770 | int reg; | |
2771 | ||
2772 | /* Fetch the instruction. */ | |
2773 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
2774 | ||
2775 | /* Save some code by pre-extracting some useful fields. */ | |
2776 | high_word = (inst >> 16) & 0xffff; | |
2777 | low_word = inst & 0xffff; | |
2778 | reg = high_word & 0x1f; | |
2779 | ||
c5aa993b | 2780 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
2781 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2782 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2783 | { | |
2784 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 2785 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
2786 | else |
2787 | /* Exit loop if a positive stack adjustment is found, which | |
2788 | usually means that the stack cleanup code in the function | |
2789 | epilogue is reached. */ | |
2790 | break; | |
2791 | } | |
2792 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2793 | { | |
c5aa993b | 2794 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2795 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c SS |
2796 | } |
2797 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2798 | { | |
d5ac5a39 AC |
2799 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and |
2800 | $ra. */ | |
c5aa993b | 2801 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
d5ac5a39 | 2802 | set_reg_offset (temp_saved_regs, reg, sp + low_word); |
c906108c | 2803 | } |
c5aa993b | 2804 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
2805 | { |
2806 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
2807 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
2808 | frame_addr = sp + low_word; | |
f10683bb | 2809 | else if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM) |
c906108c SS |
2810 | { |
2811 | unsigned alloca_adjust; | |
2812 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2813 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2814 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
c906108c SS |
2815 | if (alloca_adjust > 0) |
2816 | { | |
2817 | /* FP > SP + frame_size. This may be because | |
2818 | * of an alloca or somethings similar. | |
2819 | * Fix sp to "pre-alloca" value, and try again. | |
2820 | */ | |
2821 | sp += alloca_adjust; | |
2822 | goto restart; | |
2823 | } | |
2824 | } | |
2825 | } | |
c5aa993b JM |
2826 | /* move $30,$sp. With different versions of gas this will be either |
2827 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2828 | Accept any one of these. */ | |
c906108c SS |
2829 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
2830 | { | |
2831 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
f10683bb | 2832 | if (PROC_FRAME_REG (&temp_proc_desc) == MIPS_SP_REGNUM) |
c906108c SS |
2833 | { |
2834 | unsigned alloca_adjust; | |
2835 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
a4b8ebc8 | 2836 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); |
c5aa993b | 2837 | alloca_adjust = (unsigned) (frame_addr - sp); |
c906108c SS |
2838 | if (alloca_adjust > 0) |
2839 | { | |
2840 | /* FP > SP + frame_size. This may be because | |
2841 | * of an alloca or somethings similar. | |
2842 | * Fix sp to "pre-alloca" value, and try again. | |
2843 | */ | |
2844 | sp += alloca_adjust; | |
2845 | goto restart; | |
2846 | } | |
2847 | } | |
2848 | } | |
c5aa993b | 2849 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 2850 | { |
c5aa993b | 2851 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
e0f7ec59 | 2852 | set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); |
c906108c SS |
2853 | } |
2854 | } | |
2855 | } | |
2856 | ||
2857 | static mips_extra_func_info_t | |
acdb74a0 | 2858 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
465f7520 | 2859 | struct frame_info *next_frame) |
c906108c | 2860 | { |
479412cd DJ |
2861 | CORE_ADDR sp; |
2862 | ||
465f7520 AC |
2863 | /* Can be called when there's no process, and hence when there's no |
2864 | NEXT_FRAME. */ | |
2865 | if (next_frame != NULL) | |
f10683bb | 2866 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); |
479412cd DJ |
2867 | else |
2868 | sp = 0; | |
c906108c | 2869 | |
c5aa993b JM |
2870 | if (start_pc == 0) |
2871 | return NULL; | |
2872 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
fe29b929 | 2873 | temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
3758ac48 | 2874 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c | 2875 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
f10683bb | 2876 | PROC_FRAME_REG (&temp_proc_desc) = MIPS_SP_REGNUM; |
c906108c SS |
2877 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; |
2878 | ||
2879 | if (start_pc + 200 < limit_pc) | |
2880 | limit_pc = start_pc + 200; | |
2881 | if (pc_is_mips16 (start_pc)) | |
2882 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2883 | else | |
2884 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2885 | return &temp_proc_desc; | |
2886 | } | |
2887 | ||
6c0d6680 DJ |
2888 | struct mips_objfile_private |
2889 | { | |
2890 | bfd_size_type size; | |
2891 | char *contents; | |
2892 | }; | |
2893 | ||
2894 | /* Global used to communicate between non_heuristic_proc_desc and | |
2895 | compare_pdr_entries within qsort (). */ | |
2896 | static bfd *the_bfd; | |
2897 | ||
2898 | static int | |
2899 | compare_pdr_entries (const void *a, const void *b) | |
2900 | { | |
2901 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2902 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2903 | ||
2904 | if (lhs < rhs) | |
2905 | return -1; | |
2906 | else if (lhs == rhs) | |
2907 | return 0; | |
2908 | else | |
2909 | return 1; | |
2910 | } | |
2911 | ||
c906108c | 2912 | static mips_extra_func_info_t |
acdb74a0 | 2913 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2914 | { |
2915 | CORE_ADDR startaddr; | |
2916 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2917 | struct block *b = block_for_pc (pc); |
c906108c | 2918 | struct symbol *sym; |
6c0d6680 DJ |
2919 | struct obj_section *sec; |
2920 | struct mips_objfile_private *priv; | |
2921 | ||
c906108c SS |
2922 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
2923 | if (addrptr) | |
2924 | *addrptr = startaddr; | |
6c0d6680 DJ |
2925 | |
2926 | priv = NULL; | |
2927 | ||
2928 | sec = find_pc_section (pc); | |
2929 | if (sec != NULL) | |
c906108c | 2930 | { |
8d5f9dcb | 2931 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2932 | |
2933 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2934 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2935 | |
2936 | the_bfd = sec->objfile->obfd; | |
2937 | if (priv == NULL | |
2938 | && (the_bfd->format == bfd_object | |
2939 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2940 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2941 | { | |
2942 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2943 | This means that we should not bother with this method on 64-bit | |
2944 | targets (until that is fixed). */ | |
2945 | ||
8b92e4d5 | 2946 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2947 | sizeof (struct mips_objfile_private)); |
2948 | priv->size = 0; | |
8d5f9dcb | 2949 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2950 | } |
2951 | else if (priv == NULL) | |
2952 | { | |
2953 | asection *bfdsec; | |
2954 | ||
8b92e4d5 | 2955 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2956 | sizeof (struct mips_objfile_private)); |
2957 | ||
2958 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2959 | if (bfdsec != NULL) | |
2960 | { | |
2961 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2962 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2963 | priv->size); |
2964 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2965 | priv->contents, 0, priv->size); | |
2966 | ||
2967 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2968 | presence of multiple code sections (and other corner cases) |
2969 | it can become unsorted. Sort it so that we can use a faster | |
2970 | binary search. */ | |
2971 | qsort (priv->contents, priv->size / 32, 32, | |
2972 | compare_pdr_entries); | |
6c0d6680 DJ |
2973 | } |
2974 | else | |
2975 | priv->size = 0; | |
2976 | ||
8d5f9dcb | 2977 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2978 | } |
2979 | the_bfd = NULL; | |
2980 | ||
2981 | if (priv->size != 0) | |
2982 | { | |
2983 | int low, mid, high; | |
2984 | char *ptr; | |
34fcf120 | 2985 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2986 | |
2987 | low = 0; | |
2988 | high = priv->size / 32; | |
2989 | ||
34fcf120 DJ |
2990 | /* We've found a .pdr section describing this objfile. We want to |
2991 | find the entry which describes this code address. The .pdr | |
2992 | information is not very descriptive; we have only a function | |
2993 | start address. We have to look for the closest entry, because | |
2994 | the local symbol at the beginning of this function may have | |
2995 | been stripped - so if we ask the symbol table for the start | |
2996 | address we may get a preceding global function. */ | |
2997 | ||
2998 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
2999 | do |
3000 | { | |
6c0d6680 DJ |
3001 | mid = (low + high) / 2; |
3002 | ||
3003 | ptr = priv->contents + mid * 32; | |
3004 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
3005 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
3006 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
3007 | |
3008 | if (pdr_pc > pc) | |
6c0d6680 DJ |
3009 | high = mid; |
3010 | else | |
3011 | low = mid + 1; | |
3012 | } | |
3013 | while (low != high); | |
3014 | ||
34fcf120 DJ |
3015 | /* Both low and high point one past the PDR of interest. If |
3016 | both are zero, that means this PC is before any region | |
3017 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
3018 | greater than PC. */ | |
3019 | if (low > 0) | |
3020 | { | |
3021 | ptr = priv->contents + (low - 1) * 32; | |
3022 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
3023 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
3024 | SECT_OFF_TEXT (sec->objfile)); | |
3025 | } | |
3026 | ||
3027 | /* We don't have a range, so we have no way to know for sure | |
3028 | whether we're in the correct PDR or a PDR for a preceding | |
3029 | function and the current function was a stripped local | |
3030 | symbol. But if the PDR's PC is at least as great as the | |
3031 | best guess from the symbol table, assume that it does cover | |
3032 | the right area; if a .pdr section is present at all then | |
3033 | nearly every function will have an entry. The biggest exception | |
3034 | will be the dynamic linker stubs; conveniently these are | |
3035 | placed before .text instead of after. */ | |
3036 | ||
3037 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
3038 | { |
3039 | struct symbol *sym = find_pc_function (pc); | |
3040 | ||
34fcf120 DJ |
3041 | if (addrptr) |
3042 | *addrptr = pdr_pc; | |
3043 | ||
6c0d6680 DJ |
3044 | /* Fill in what we need of the proc_desc. */ |
3045 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 3046 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 3047 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 3048 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
3049 | |
3050 | /* Only used for dummy frames. */ | |
3051 | PROC_HIGH_ADDR (proc_desc) = 0; | |
3052 | ||
3053 | PROC_FRAME_OFFSET (proc_desc) | |
3054 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
3055 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3056 | ptr + 24); | |
3057 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
3058 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3059 | ptr + 4); | |
3060 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3061 | ptr + 12); | |
3062 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3063 | ptr + 8); | |
3064 | PROC_FREG_OFFSET (proc_desc) | |
3065 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
3066 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
3067 | ptr + 28); | |
3068 | proc_desc->pdr.isym = (long) sym; | |
3069 | ||
3070 | return proc_desc; | |
3071 | } | |
3072 | } | |
c906108c SS |
3073 | } |
3074 | ||
6c0d6680 DJ |
3075 | if (b == NULL) |
3076 | return NULL; | |
3077 | ||
3078 | if (startaddr > BLOCK_START (b)) | |
3079 | { | |
3080 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
3081 | print_frame_info. It might be better to move this check into |
3082 | symbol reading. */ | |
6c0d6680 DJ |
3083 | return NULL; |
3084 | } | |
3085 | ||
176620f1 | 3086 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 3087 | |
c906108c SS |
3088 | /* If we never found a PDR for this function in symbol reading, then |
3089 | examine prologues to find the information. */ | |
3090 | if (sym) | |
3091 | { | |
3092 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
3093 | if (PROC_FRAME_REG (proc_desc) == -1) | |
3094 | return NULL; | |
3095 | else | |
3096 | return proc_desc; | |
3097 | } | |
3098 | else | |
3099 | return NULL; | |
3100 | } | |
3101 | ||
c906108c SS |
3102 | /* MIPS stack frames are almost impenetrable. When execution stops, |
3103 | we basically have to look at symbol information for the function | |
3104 | that we stopped in, which tells us *which* register (if any) is | |
3105 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 3106 | the frame itself is at. |
c906108c SS |
3107 | |
3108 | This presents a problem when trying to examine a stack in memory | |
3109 | (that isn't executing at the moment), using the "frame" command. We | |
3110 | don't have a PC, nor do we have any registers except SP. | |
3111 | ||
3112 | This routine takes two arguments, SP and PC, and tries to make the | |
3113 | cached frames look as if these two arguments defined a frame on the | |
3114 | cache. This allows the rest of info frame to extract the important | |
3115 | arguments without difficulty. */ | |
3116 | ||
3117 | struct frame_info * | |
acdb74a0 | 3118 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
3119 | { |
3120 | if (argc != 2) | |
3121 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
3122 | ||
3123 | return create_new_frame (argv[0], argv[1]); | |
3124 | } | |
3125 | ||
f09ded24 AC |
3126 | /* According to the current ABI, should the type be passed in a |
3127 | floating-point register (assuming that there is space)? When there | |
3128 | is no FPU, FP are not even considered as possibile candidates for | |
3129 | FP registers and, consequently this returns false - forces FP | |
3130 | arguments into integer registers. */ | |
3131 | ||
3132 | static int | |
3133 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
3134 | { | |
3135 | return ((typecode == TYPE_CODE_FLT | |
3136 | || (MIPS_EABI | |
6d82d43b AC |
3137 | && (typecode == TYPE_CODE_STRUCT |
3138 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
3139 | && TYPE_NFIELDS (arg_type) == 1 |
3140 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 3141 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
3142 | } |
3143 | ||
49e790b0 DJ |
3144 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
3145 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
3146 | ||
3147 | static int | |
3148 | mips_type_needs_double_align (struct type *type) | |
3149 | { | |
3150 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 3151 | |
49e790b0 DJ |
3152 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
3153 | return 1; | |
3154 | else if (typecode == TYPE_CODE_STRUCT) | |
3155 | { | |
3156 | if (TYPE_NFIELDS (type) < 1) | |
3157 | return 0; | |
3158 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
3159 | } | |
3160 | else if (typecode == TYPE_CODE_UNION) | |
3161 | { | |
361d1df0 | 3162 | int i, n; |
49e790b0 DJ |
3163 | |
3164 | n = TYPE_NFIELDS (type); | |
3165 | for (i = 0; i < n; i++) | |
3166 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
3167 | return 1; | |
3168 | return 0; | |
3169 | } | |
3170 | return 0; | |
3171 | } | |
3172 | ||
dc604539 AC |
3173 | /* Adjust the address downward (direction of stack growth) so that it |
3174 | is correctly aligned for a new stack frame. */ | |
3175 | static CORE_ADDR | |
3176 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
3177 | { | |
5b03f266 | 3178 | return align_down (addr, 16); |
dc604539 AC |
3179 | } |
3180 | ||
6d82d43b AC |
3181 | /* Determine how a return value is stored within the MIPS register |
3182 | file, given the return type `valtype'. */ | |
3183 | ||
3184 | struct return_value_word | |
3185 | { | |
3186 | int len; | |
3187 | int reg; | |
3188 | int reg_offset; | |
3189 | int buf_offset; | |
3190 | }; | |
3191 | ||
3192 | static void | |
3193 | return_value_location (struct type *valtype, | |
3194 | struct return_value_word *hi, | |
3195 | struct return_value_word *lo) | |
3196 | { | |
3197 | int len = TYPE_LENGTH (valtype); | |
3198 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3199 | ||
3200 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
3201 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
3202 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
3203 | { | |
ceae6e75 | 3204 | if (mips_abi_regsize (current_gdbarch) < 8 && len == 8) |
6d82d43b AC |
3205 | { |
3206 | /* We need to break a 64bit float in two 32 bit halves and | |
ceae6e75 | 3207 | spread them across a floating-point register pair. */ |
6d82d43b AC |
3208 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
3209 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
3210 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3211 | && register_size (current_gdbarch, | |
3212 | mips_regnum (current_gdbarch)-> | |
3213 | fp0) == 8) ? 4 : 0); | |
3214 | hi->reg_offset = lo->reg_offset; | |
3215 | lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; | |
3216 | hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; | |
3217 | lo->len = 4; | |
3218 | hi->len = 4; | |
3219 | } | |
3220 | else | |
3221 | { | |
3222 | /* The floating point value fits in a single floating-point | |
3223 | register. */ | |
3224 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3225 | && register_size (current_gdbarch, | |
3226 | mips_regnum (current_gdbarch)-> | |
3227 | fp0) == 8 | |
3228 | && len == 4) ? 4 : 0); | |
3229 | lo->reg = mips_regnum (current_gdbarch)->fp0; | |
3230 | lo->len = len; | |
3231 | lo->buf_offset = 0; | |
3232 | hi->len = 0; | |
3233 | hi->reg_offset = 0; | |
3234 | hi->buf_offset = 0; | |
3235 | hi->reg = 0; | |
3236 | } | |
3237 | } | |
3238 | else | |
3239 | { | |
3240 | /* Locate a result possibly spread across two registers. */ | |
3241 | int regnum = 2; | |
3242 | lo->reg = regnum + 0; | |
3243 | hi->reg = regnum + 1; | |
3244 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3245 | && len < mips_abi_regsize (current_gdbarch)) |
6d82d43b AC |
3246 | { |
3247 | /* "un-left-justify" the value in the low register */ | |
13326b4e | 3248 | lo->reg_offset = mips_abi_regsize (current_gdbarch) - len; |
6d82d43b AC |
3249 | lo->len = len; |
3250 | hi->reg_offset = 0; | |
3251 | hi->len = 0; | |
3252 | } | |
13326b4e AC |
3253 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_abi_regsize (current_gdbarch) /* odd-size structs */ |
3254 | && len < mips_abi_regsize (current_gdbarch) * 2 | |
6d82d43b AC |
3255 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
3256 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
3257 | { | |
3258 | /* "un-left-justify" the value spread across two registers. */ | |
13326b4e AC |
3259 | lo->reg_offset = 2 * mips_abi_regsize (current_gdbarch) - len; |
3260 | lo->len = mips_abi_regsize (current_gdbarch) - lo->reg_offset; | |
6d82d43b AC |
3261 | hi->reg_offset = 0; |
3262 | hi->len = len - lo->len; | |
3263 | } | |
3264 | else | |
3265 | { | |
3266 | /* Only perform a partial copy of the second register. */ | |
3267 | lo->reg_offset = 0; | |
3268 | hi->reg_offset = 0; | |
13326b4e | 3269 | if (len > mips_abi_regsize (current_gdbarch)) |
6d82d43b | 3270 | { |
13326b4e AC |
3271 | lo->len = mips_abi_regsize (current_gdbarch); |
3272 | hi->len = len - mips_abi_regsize (current_gdbarch); | |
6d82d43b AC |
3273 | } |
3274 | else | |
3275 | { | |
3276 | lo->len = len; | |
3277 | hi->len = 0; | |
3278 | } | |
3279 | } | |
3280 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3281 | && register_size (current_gdbarch, regnum) == 8 | |
13326b4e | 3282 | && mips_abi_regsize (current_gdbarch) == 4) |
6d82d43b AC |
3283 | { |
3284 | /* Account for the fact that only the least-signficant part | |
3285 | of the register is being used */ | |
3286 | lo->reg_offset += 4; | |
3287 | hi->reg_offset += 4; | |
3288 | } | |
3289 | lo->buf_offset = 0; | |
3290 | hi->buf_offset = lo->len; | |
3291 | } | |
3292 | } | |
3293 | ||
3294 | /* Should call_function allocate stack space for a struct return? */ | |
3295 | ||
3296 | static int | |
3297 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) | |
3298 | { | |
3299 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
13326b4e | 3300 | return (TYPE_LENGTH (type) > 2 * mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3301 | } |
3302 | ||
3303 | /* Should call_function pass struct by reference? | |
3304 | For each architecture, structs are passed either by | |
3305 | value or by reference, depending on their size. */ | |
3306 | ||
3307 | static int | |
3308 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
3309 | { | |
3310 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
3311 | int len = TYPE_LENGTH (check_typedef (type)); | |
3312 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3313 | ||
3314 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
13326b4e | 3315 | return (len > mips_abi_regsize (current_gdbarch)); |
6d82d43b AC |
3316 | |
3317 | return 0; | |
3318 | } | |
3319 | ||
f7ab6ec6 | 3320 | static CORE_ADDR |
7d9b040b | 3321 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3322 | struct regcache *regcache, CORE_ADDR bp_addr, |
3323 | int nargs, struct value **args, CORE_ADDR sp, | |
3324 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
3325 | { |
3326 | int argreg; | |
3327 | int float_argreg; | |
3328 | int argnum; | |
3329 | int len = 0; | |
3330 | int stack_offset = 0; | |
480d3dd2 | 3331 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3332 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 3333 | |
25ab4790 AC |
3334 | /* For shared libraries, "t9" needs to point at the function |
3335 | address. */ | |
3336 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3337 | ||
3338 | /* Set the return address register to point to the entry point of | |
3339 | the program, where a breakpoint lies in wait. */ | |
3340 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3341 | ||
c906108c | 3342 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
3343 | are properly aligned. The stack has to be at least 64-bit |
3344 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3345 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3346 | aligned, so we round to this widest known alignment. */ | |
3347 | ||
5b03f266 AC |
3348 | sp = align_down (sp, 16); |
3349 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 3350 | |
46e0f506 | 3351 | /* Now make space on the stack for the args. We allocate more |
c906108c | 3352 | than necessary for EABI, because the first few arguments are |
46e0f506 | 3353 | passed in registers, but that's OK. */ |
c906108c | 3354 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 3355 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3356 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3357 | sp -= align_up (len, 16); |
c906108c | 3358 | |
9ace0497 | 3359 | if (mips_debug) |
6d82d43b | 3360 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3361 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
3362 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 3363 | |
c906108c SS |
3364 | /* Initialize the integer and float register pointers. */ |
3365 | argreg = A0_REGNUM; | |
56cea623 | 3366 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 3367 | |
46e0f506 | 3368 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 3369 | if (struct_return) |
9ace0497 AC |
3370 | { |
3371 | if (mips_debug) | |
3372 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3373 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3374 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
3375 | write_register (argreg++, struct_addr); |
3376 | } | |
c906108c SS |
3377 | |
3378 | /* Now load as many as possible of the first arguments into | |
3379 | registers, and push the rest onto the stack. Loop thru args | |
3380 | from first to last. */ | |
3381 | for (argnum = 0; argnum < nargs; argnum++) | |
3382 | { | |
3383 | char *val; | |
d9d9c31f | 3384 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 3385 | struct value *arg = args[argnum]; |
c906108c SS |
3386 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
3387 | int len = TYPE_LENGTH (arg_type); | |
3388 | enum type_code typecode = TYPE_CODE (arg_type); | |
3389 | ||
9ace0497 AC |
3390 | if (mips_debug) |
3391 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3392 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3393 | argnum + 1, len, (int) typecode); |
9ace0497 | 3394 | |
c906108c | 3395 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3396 | reference. */ |
13326b4e | 3397 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 3398 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3399 | { |
13326b4e | 3400 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 3401 | VALUE_ADDRESS (arg)); |
c906108c | 3402 | typecode = TYPE_CODE_PTR; |
13326b4e | 3403 | len = mips_abi_regsize (gdbarch); |
c906108c | 3404 | val = valbuf; |
9ace0497 AC |
3405 | if (mips_debug) |
3406 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3407 | } |
3408 | else | |
c5aa993b | 3409 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
3410 | |
3411 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3412 | even-numbered floating point register. Round the FP register |
3413 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3414 | left. Non MIPS_EABI targets also pass the FP in the integer |
3415 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3416 | if (mips_abi_regsize (gdbarch) < 8 |
3417 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
3418 | { |
3419 | if ((float_argreg & 1)) | |
3420 | float_argreg++; | |
3421 | } | |
c906108c SS |
3422 | |
3423 | /* Floating point arguments passed in registers have to be | |
3424 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3425 | are passed in register pairs; the even register gets |
3426 | the low word, and the odd register gets the high word. | |
3427 | On non-EABI processors, the first two floating point arguments are | |
3428 | also copied to general registers, because MIPS16 functions | |
3429 | don't use float registers for arguments. This duplication of | |
3430 | arguments in general registers can't hurt non-MIPS16 functions | |
3431 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3432 | /* MIPS_EABI squeezes a struct that contains a single floating |
3433 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3434 | stack. */ |
f09ded24 AC |
3435 | if (fp_register_arg_p (typecode, arg_type) |
3436 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 3437 | { |
ceae6e75 | 3438 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 3439 | { |
d7449b42 | 3440 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
3441 | unsigned long regval; |
3442 | ||
3443 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 3444 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 3445 | if (mips_debug) |
acdb74a0 | 3446 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3447 | float_argreg, phex (regval, 4)); |
c906108c | 3448 | write_register (float_argreg++, regval); |
c906108c SS |
3449 | |
3450 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 3451 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 3452 | if (mips_debug) |
acdb74a0 | 3453 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3454 | float_argreg, phex (regval, 4)); |
c906108c | 3455 | write_register (float_argreg++, regval); |
c906108c SS |
3456 | } |
3457 | else | |
3458 | { | |
3459 | /* This is a floating point value that fits entirely | |
3460 | in a single register. */ | |
53a5351d | 3461 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3462 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
3463 | LONGEST regval = extract_unsigned_integer (val, len); |
3464 | if (mips_debug) | |
acdb74a0 | 3465 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3466 | float_argreg, phex (regval, len)); |
c906108c | 3467 | write_register (float_argreg++, regval); |
c906108c SS |
3468 | } |
3469 | } | |
3470 | else | |
3471 | { | |
3472 | /* Copy the argument to general registers or the stack in | |
3473 | register-sized pieces. Large arguments are split between | |
3474 | registers and stack. */ | |
4246e332 | 3475 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3476 | mips_abi_regsize() are treated specially: Irix cc passes |
3477 | them in registers where gcc sometimes puts them on the | |
3478 | stack. For maximum compatibility, we will put them in | |
3479 | both places. */ | |
13326b4e AC |
3480 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3481 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 3482 | |
f09ded24 | 3483 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3484 | register are only written to memory. */ |
c906108c SS |
3485 | while (len > 0) |
3486 | { | |
ebafbe83 | 3487 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3488 | int stack_used_p = 0; |
13326b4e AC |
3489 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3490 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 3491 | |
acdb74a0 AC |
3492 | if (mips_debug) |
3493 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3494 | partial_len); | |
3495 | ||
566f0f7a | 3496 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3497 | if (argreg > MIPS_LAST_ARG_REGNUM |
3498 | || odd_sized_struct | |
3499 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3500 | { |
c906108c SS |
3501 | /* Should shorter than int integer values be |
3502 | promoted to int before being stored? */ | |
c906108c | 3503 | int longword_offset = 0; |
9ace0497 | 3504 | CORE_ADDR addr; |
566f0f7a | 3505 | stack_used_p = 1; |
d7449b42 | 3506 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3507 | { |
13326b4e | 3508 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3509 | && (typecode == TYPE_CODE_INT |
3510 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3511 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3512 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
3513 | else if ((typecode == TYPE_CODE_STRUCT |
3514 | || typecode == TYPE_CODE_UNION) | |
3515 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
3516 | < mips_stack_argsize (gdbarch))) |
3517 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 3518 | } |
c5aa993b | 3519 | |
9ace0497 AC |
3520 | if (mips_debug) |
3521 | { | |
cb3d25d1 MS |
3522 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3523 | paddr_nz (stack_offset)); | |
3524 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3525 | paddr_nz (longword_offset)); | |
9ace0497 | 3526 | } |
361d1df0 | 3527 | |
9ace0497 AC |
3528 | addr = sp + stack_offset + longword_offset; |
3529 | ||
3530 | if (mips_debug) | |
3531 | { | |
3532 | int i; | |
6d82d43b | 3533 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3534 | paddr_nz (addr)); |
9ace0497 AC |
3535 | for (i = 0; i < partial_len; i++) |
3536 | { | |
6d82d43b | 3537 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3538 | val[i] & 0xff); |
9ace0497 AC |
3539 | } |
3540 | } | |
3541 | write_memory (addr, val, partial_len); | |
c906108c SS |
3542 | } |
3543 | ||
f09ded24 AC |
3544 | /* Note!!! This is NOT an else clause. Odd sized |
3545 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3546 | arguments will not. */ |
566f0f7a | 3547 | /* Write this portion of the argument to a general |
6d82d43b | 3548 | purpose register. */ |
f09ded24 AC |
3549 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3550 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3551 | { |
6d82d43b AC |
3552 | LONGEST regval = |
3553 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3554 | |
9ace0497 | 3555 | if (mips_debug) |
acdb74a0 | 3556 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3557 | argreg, |
6d82d43b | 3558 | phex (regval, |
13326b4e | 3559 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3560 | write_register (argreg, regval); |
3561 | argreg++; | |
c906108c | 3562 | } |
c5aa993b | 3563 | |
c906108c SS |
3564 | len -= partial_len; |
3565 | val += partial_len; | |
3566 | ||
566f0f7a | 3567 | /* Compute the the offset into the stack at which we |
6d82d43b | 3568 | will copy the next parameter. |
566f0f7a | 3569 | |
566f0f7a | 3570 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3571 | only needs to be adjusted when it has been used. */ |
c906108c | 3572 | |
46e0f506 | 3573 | if (stack_used_p) |
480d3dd2 | 3574 | stack_offset += align_up (partial_len, |
13326b4e | 3575 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3576 | } |
3577 | } | |
9ace0497 AC |
3578 | if (mips_debug) |
3579 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3580 | } |
3581 | ||
f10683bb | 3582 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3583 | |
0f71a2f6 JM |
3584 | /* Return adjusted stack pointer. */ |
3585 | return sp; | |
3586 | } | |
3587 | ||
6d82d43b AC |
3588 | /* Given a return value in `regbuf' with a type `valtype', extract and |
3589 | copy its value into `valbuf'. */ | |
3590 | ||
3591 | static void | |
3592 | mips_eabi_extract_return_value (struct type *valtype, | |
3593 | char regbuf[], char *valbuf) | |
3594 | { | |
3595 | struct return_value_word lo; | |
3596 | struct return_value_word hi; | |
3597 | return_value_location (valtype, &hi, &lo); | |
3598 | ||
3599 | memcpy (valbuf + lo.buf_offset, | |
3600 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
3601 | lo.reg_offset, lo.len); | |
3602 | ||
3603 | if (hi.len > 0) | |
3604 | memcpy (valbuf + hi.buf_offset, | |
3605 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
3606 | hi.reg_offset, hi.len); | |
3607 | } | |
3608 | ||
3609 | /* Given a return value in `valbuf' with a type `valtype', write it's | |
3610 | value into the appropriate register. */ | |
3611 | ||
3612 | static void | |
3613 | mips_eabi_store_return_value (struct type *valtype, char *valbuf) | |
3614 | { | |
3615 | char raw_buffer[MAX_REGISTER_SIZE]; | |
3616 | struct return_value_word lo; | |
3617 | struct return_value_word hi; | |
3618 | return_value_location (valtype, &hi, &lo); | |
3619 | ||
3620 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3621 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
3622 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
3623 | raw_buffer, register_size (current_gdbarch, | |
3624 | lo.reg)); | |
3625 | ||
3626 | if (hi.len > 0) | |
3627 | { | |
3628 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
3629 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
3630 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
3631 | raw_buffer, | |
3632 | register_size (current_gdbarch, | |
3633 | hi.reg)); | |
3634 | } | |
3635 | } | |
3636 | ||
3637 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3638 | |
f7ab6ec6 | 3639 | static CORE_ADDR |
7d9b040b | 3640 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3641 | struct regcache *regcache, CORE_ADDR bp_addr, |
3642 | int nargs, struct value **args, CORE_ADDR sp, | |
3643 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3644 | { |
3645 | int argreg; | |
3646 | int float_argreg; | |
3647 | int argnum; | |
3648 | int len = 0; | |
3649 | int stack_offset = 0; | |
480d3dd2 | 3650 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3651 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3652 | |
25ab4790 AC |
3653 | /* For shared libraries, "t9" needs to point at the function |
3654 | address. */ | |
3655 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3656 | ||
3657 | /* Set the return address register to point to the entry point of | |
3658 | the program, where a breakpoint lies in wait. */ | |
3659 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3660 | ||
cb3d25d1 MS |
3661 | /* First ensure that the stack and structure return address (if any) |
3662 | are properly aligned. The stack has to be at least 64-bit | |
3663 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3664 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3665 | aligned, so we round to this widest known alignment. */ | |
3666 | ||
5b03f266 AC |
3667 | sp = align_down (sp, 16); |
3668 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3669 | |
3670 | /* Now make space on the stack for the args. */ | |
3671 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3672 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3673 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3674 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3675 | |
3676 | if (mips_debug) | |
6d82d43b | 3677 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3678 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3679 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3680 | |
3681 | /* Initialize the integer and float register pointers. */ | |
3682 | argreg = A0_REGNUM; | |
56cea623 | 3683 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3684 | |
46e0f506 | 3685 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3686 | if (struct_return) |
3687 | { | |
3688 | if (mips_debug) | |
3689 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3690 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3691 | argreg, paddr_nz (struct_addr)); |
3692 | write_register (argreg++, struct_addr); | |
3693 | } | |
3694 | ||
3695 | /* Now load as many as possible of the first arguments into | |
3696 | registers, and push the rest onto the stack. Loop thru args | |
3697 | from first to last. */ | |
3698 | for (argnum = 0; argnum < nargs; argnum++) | |
3699 | { | |
3700 | char *val; | |
cb3d25d1 MS |
3701 | struct value *arg = args[argnum]; |
3702 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3703 | int len = TYPE_LENGTH (arg_type); | |
3704 | enum type_code typecode = TYPE_CODE (arg_type); | |
3705 | ||
3706 | if (mips_debug) | |
3707 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3708 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3709 | argnum + 1, len, (int) typecode); |
3710 | ||
3711 | val = (char *) VALUE_CONTENTS (arg); | |
3712 | ||
3713 | if (fp_register_arg_p (typecode, arg_type) | |
3714 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3715 | { | |
3716 | /* This is a floating point value that fits entirely | |
3717 | in a single register. */ | |
3718 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3719 | above to ensure that it is even register aligned. */ | |
3720 | LONGEST regval = extract_unsigned_integer (val, len); | |
3721 | if (mips_debug) | |
3722 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3723 | float_argreg, phex (regval, len)); | |
3724 | write_register (float_argreg++, regval); | |
3725 | ||
3726 | if (mips_debug) | |
3727 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3728 | argreg, phex (regval, len)); | |
3729 | write_register (argreg, regval); | |
3730 | argreg += 1; | |
3731 | } | |
3732 | else | |
3733 | { | |
3734 | /* Copy the argument to general registers or the stack in | |
3735 | register-sized pieces. Large arguments are split between | |
3736 | registers and stack. */ | |
4246e332 | 3737 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3738 | mips_abi_regsize() are treated specially: Irix cc passes |
3739 | them in registers where gcc sometimes puts them on the | |
3740 | stack. For maximum compatibility, we will put them in | |
3741 | both places. */ | |
13326b4e AC |
3742 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3743 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3744 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3745 | register are only written to memory. */ |
cb3d25d1 MS |
3746 | while (len > 0) |
3747 | { | |
3748 | /* Rememer if the argument was written to the stack. */ | |
3749 | int stack_used_p = 0; | |
13326b4e AC |
3750 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3751 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3752 | |
3753 | if (mips_debug) | |
3754 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3755 | partial_len); | |
3756 | ||
3757 | /* Write this portion of the argument to the stack. */ | |
3758 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3759 | || odd_sized_struct | |
3760 | || fp_register_arg_p (typecode, arg_type)) | |
3761 | { | |
3762 | /* Should shorter than int integer values be | |
3763 | promoted to int before being stored? */ | |
3764 | int longword_offset = 0; | |
3765 | CORE_ADDR addr; | |
3766 | stack_used_p = 1; | |
3767 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3768 | { | |
13326b4e | 3769 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3770 | && (typecode == TYPE_CODE_INT |
3771 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3772 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3773 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3774 | } |
3775 | ||
3776 | if (mips_debug) | |
3777 | { | |
3778 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3779 | paddr_nz (stack_offset)); | |
3780 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3781 | paddr_nz (longword_offset)); | |
3782 | } | |
3783 | ||
3784 | addr = sp + stack_offset + longword_offset; | |
3785 | ||
3786 | if (mips_debug) | |
3787 | { | |
3788 | int i; | |
6d82d43b | 3789 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3790 | paddr_nz (addr)); |
3791 | for (i = 0; i < partial_len; i++) | |
3792 | { | |
6d82d43b | 3793 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3794 | val[i] & 0xff); |
3795 | } | |
3796 | } | |
3797 | write_memory (addr, val, partial_len); | |
3798 | } | |
3799 | ||
3800 | /* Note!!! This is NOT an else clause. Odd sized | |
3801 | structs may go thru BOTH paths. Floating point | |
3802 | arguments will not. */ | |
3803 | /* Write this portion of the argument to a general | |
6d82d43b | 3804 | purpose register. */ |
cb3d25d1 MS |
3805 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3806 | && !fp_register_arg_p (typecode, arg_type)) | |
3807 | { | |
6d82d43b AC |
3808 | LONGEST regval = |
3809 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3810 | |
3811 | /* A non-floating-point argument being passed in a | |
3812 | general register. If a struct or union, and if | |
3813 | the remaining length is smaller than the register | |
3814 | size, we have to adjust the register value on | |
3815 | big endian targets. | |
3816 | ||
3817 | It does not seem to be necessary to do the | |
3818 | same for integral types. | |
3819 | ||
3820 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3821 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3822 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3823 | part of storing the argument in a register a |
3824 | register (the left shift isn't generated when | |
1b13c4f6 | 3825 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3826 | it is quite possible that this is GCC |
3827 | contradicting the LE/O32 ABI, GDB has not been | |
3828 | adjusted to accommodate this. Either someone | |
3829 | needs to demonstrate that the LE/O32 ABI | |
3830 | specifies such a left shift OR this new ABI gets | |
3831 | identified as such and GDB gets tweaked | |
3832 | accordingly. */ | |
cb3d25d1 MS |
3833 | |
3834 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3835 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3836 | && (typecode == TYPE_CODE_STRUCT || |
3837 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3838 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3839 | TARGET_CHAR_BIT); |
3840 | ||
3841 | if (mips_debug) | |
3842 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3843 | argreg, | |
6d82d43b | 3844 | phex (regval, |
13326b4e | 3845 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3846 | write_register (argreg, regval); |
3847 | argreg++; | |
3848 | } | |
3849 | ||
3850 | len -= partial_len; | |
3851 | val += partial_len; | |
3852 | ||
3853 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3854 | will copy the next parameter. |
cb3d25d1 MS |
3855 | |
3856 | In N32 (N64?), the stack_offset only needs to be | |
3857 | adjusted when it has been used. */ | |
3858 | ||
3859 | if (stack_used_p) | |
480d3dd2 | 3860 | stack_offset += align_up (partial_len, |
13326b4e | 3861 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3862 | } |
3863 | } | |
3864 | if (mips_debug) | |
3865 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3866 | } | |
3867 | ||
f10683bb | 3868 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3869 | |
cb3d25d1 MS |
3870 | /* Return adjusted stack pointer. */ |
3871 | return sp; | |
3872 | } | |
3873 | ||
6d82d43b AC |
3874 | static enum return_value_convention |
3875 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3876 | struct type *type, struct regcache *regcache, | |
3877 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3878 | { |
6d82d43b AC |
3879 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3880 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3881 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3882 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3883 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3884 | return RETURN_VALUE_STRUCT_CONVENTION; |
3885 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3886 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3887 | { | |
3888 | /* A floating-point value belongs in the least significant part | |
3889 | of FP0. */ | |
3890 | if (mips_debug) | |
3891 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3892 | mips_xfer_register (regcache, | |
3893 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3894 | TYPE_LENGTH (type), | |
3895 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3896 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3897 | } | |
3898 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3899 | && TYPE_NFIELDS (type) <= 2 | |
3900 | && TYPE_NFIELDS (type) >= 1 | |
3901 | && ((TYPE_NFIELDS (type) == 1 | |
3902 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3903 | == TYPE_CODE_FLT)) | |
3904 | || (TYPE_NFIELDS (type) == 2 | |
3905 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3906 | == TYPE_CODE_FLT) | |
3907 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3908 | == TYPE_CODE_FLT))) | |
3909 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3910 | { | |
3911 | /* A struct that contains one or two floats. Each value is part | |
3912 | in the least significant part of their floating point | |
3913 | register.. */ | |
6d82d43b AC |
3914 | int regnum; |
3915 | int field; | |
3916 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3917 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3918 | { | |
3919 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3920 | / TARGET_CHAR_BIT); | |
3921 | if (mips_debug) | |
3922 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3923 | offset); | |
3924 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3925 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3926 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3927 | } | |
3928 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3929 | } | |
3930 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3931 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3932 | { | |
3933 | /* A structure or union. Extract the left justified value, | |
3934 | regardless of the byte order. I.e. DO NOT USE | |
3935 | mips_xfer_lower. */ | |
3936 | int offset; | |
3937 | int regnum; | |
3938 | for (offset = 0, regnum = V0_REGNUM; | |
3939 | offset < TYPE_LENGTH (type); | |
3940 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3941 | { | |
3942 | int xfer = register_size (current_gdbarch, regnum); | |
3943 | if (offset + xfer > TYPE_LENGTH (type)) | |
3944 | xfer = TYPE_LENGTH (type) - offset; | |
3945 | if (mips_debug) | |
3946 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3947 | offset, xfer, regnum); | |
3948 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3949 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3950 | } | |
3951 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3952 | } | |
3953 | else | |
3954 | { | |
3955 | /* A scalar extract each part but least-significant-byte | |
3956 | justified. */ | |
3957 | int offset; | |
3958 | int regnum; | |
3959 | for (offset = 0, regnum = V0_REGNUM; | |
3960 | offset < TYPE_LENGTH (type); | |
3961 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3962 | { | |
3963 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3964 | if (offset + xfer > TYPE_LENGTH (type)) |
3965 | xfer = TYPE_LENGTH (type) - offset; | |
3966 | if (mips_debug) | |
3967 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3968 | offset, xfer, regnum); | |
3969 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3970 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3971 | } | |
3972 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3973 | } | |
3974 | } | |
3975 | ||
3976 | /* O32 ABI stuff. */ | |
3977 | ||
3978 | static CORE_ADDR | |
7d9b040b | 3979 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3980 | struct regcache *regcache, CORE_ADDR bp_addr, |
3981 | int nargs, struct value **args, CORE_ADDR sp, | |
3982 | int struct_return, CORE_ADDR struct_addr) | |
3983 | { | |
3984 | int argreg; | |
3985 | int float_argreg; | |
3986 | int argnum; | |
3987 | int len = 0; | |
3988 | int stack_offset = 0; | |
3989 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3990 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3991 | |
3992 | /* For shared libraries, "t9" needs to point at the function | |
3993 | address. */ | |
3994 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
3995 | ||
3996 | /* Set the return address register to point to the entry point of | |
3997 | the program, where a breakpoint lies in wait. */ | |
3998 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
3999 | ||
4000 | /* First ensure that the stack and structure return address (if any) | |
4001 | are properly aligned. The stack has to be at least 64-bit | |
4002 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
4003 | aligned. For n32 and n64, stack frames need to be 128-bit |
4004 | aligned, so we round to this widest known alignment. */ | |
4005 | ||
5b03f266 AC |
4006 | sp = align_down (sp, 16); |
4007 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
4008 | |
4009 | /* Now make space on the stack for the args. */ | |
4010 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4011 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4012 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4013 | sp -= align_up (len, 16); |
ebafbe83 MS |
4014 | |
4015 | if (mips_debug) | |
6d82d43b | 4016 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4017 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
4018 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
4019 | |
4020 | /* Initialize the integer and float register pointers. */ | |
4021 | argreg = A0_REGNUM; | |
56cea623 | 4022 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 4023 | |
bcb0cc15 | 4024 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
4025 | if (struct_return) |
4026 | { | |
4027 | if (mips_debug) | |
4028 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4029 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
4030 | argreg, paddr_nz (struct_addr)); |
4031 | write_register (argreg++, struct_addr); | |
13326b4e | 4032 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
4033 | } |
4034 | ||
4035 | /* Now load as many as possible of the first arguments into | |
4036 | registers, and push the rest onto the stack. Loop thru args | |
4037 | from first to last. */ | |
4038 | for (argnum = 0; argnum < nargs; argnum++) | |
4039 | { | |
4040 | char *val; | |
ebafbe83 MS |
4041 | struct value *arg = args[argnum]; |
4042 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4043 | int len = TYPE_LENGTH (arg_type); | |
4044 | enum type_code typecode = TYPE_CODE (arg_type); | |
4045 | ||
4046 | if (mips_debug) | |
4047 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4048 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
4049 | argnum + 1, len, (int) typecode); |
4050 | ||
4051 | val = (char *) VALUE_CONTENTS (arg); | |
4052 | ||
4053 | /* 32-bit ABIs always start floating point arguments in an | |
4054 | even-numbered floating point register. Round the FP register | |
4055 | up before the check to see if there are any FP registers | |
4056 | left. O32/O64 targets also pass the FP in the integer | |
4057 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4058 | if (mips_abi_regsize (gdbarch) < 8 |
4059 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
4060 | { |
4061 | if ((float_argreg & 1)) | |
4062 | float_argreg++; | |
4063 | } | |
4064 | ||
4065 | /* Floating point arguments passed in registers have to be | |
4066 | treated specially. On 32-bit architectures, doubles | |
4067 | are passed in register pairs; the even register gets | |
4068 | the low word, and the odd register gets the high word. | |
4069 | On O32/O64, the first two floating point arguments are | |
4070 | also copied to general registers, because MIPS16 functions | |
4071 | don't use float registers for arguments. This duplication of | |
4072 | arguments in general registers can't hurt non-MIPS16 functions | |
4073 | because those registers are normally skipped. */ | |
4074 | ||
4075 | if (fp_register_arg_p (typecode, arg_type) | |
4076 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4077 | { | |
ceae6e75 | 4078 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
4079 | { |
4080 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4081 | unsigned long regval; | |
4082 | ||
4083 | /* Write the low word of the double to the even register(s). */ | |
4084 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4085 | if (mips_debug) | |
4086 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4087 | float_argreg, phex (regval, 4)); | |
4088 | write_register (float_argreg++, regval); | |
4089 | if (mips_debug) | |
4090 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4091 | argreg, phex (regval, 4)); | |
4092 | write_register (argreg++, regval); | |
4093 | ||
4094 | /* Write the high word of the double to the odd register(s). */ | |
4095 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4096 | if (mips_debug) | |
4097 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4098 | float_argreg, phex (regval, 4)); | |
4099 | write_register (float_argreg++, regval); | |
4100 | ||
4101 | if (mips_debug) | |
4102 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4103 | argreg, phex (regval, 4)); | |
4104 | write_register (argreg++, regval); | |
4105 | } | |
4106 | else | |
4107 | { | |
4108 | /* This is a floating point value that fits entirely | |
4109 | in a single register. */ | |
4110 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4111 | above to ensure that it is even register aligned. */ |
46cac009 AC |
4112 | LONGEST regval = extract_unsigned_integer (val, len); |
4113 | if (mips_debug) | |
4114 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4115 | float_argreg, phex (regval, len)); | |
4116 | write_register (float_argreg++, regval); | |
4117 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4118 | registers for each argument. The below is (my |
4119 | guess) to ensure that the corresponding integer | |
4120 | register has reserved the same space. */ | |
46cac009 AC |
4121 | if (mips_debug) |
4122 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4123 | argreg, phex (regval, len)); | |
4124 | write_register (argreg, regval); | |
ceae6e75 | 4125 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
4126 | } |
4127 | /* Reserve space for the FP register. */ | |
13326b4e | 4128 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
4129 | } |
4130 | else | |
4131 | { | |
4132 | /* Copy the argument to general registers or the stack in | |
4133 | register-sized pieces. Large arguments are split between | |
4134 | registers and stack. */ | |
4246e332 | 4135 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4136 | mips_abi_regsize() are treated specially: Irix cc passes |
4137 | them in registers where gcc sometimes puts them on the | |
4138 | stack. For maximum compatibility, we will put them in | |
4139 | both places. */ | |
13326b4e AC |
4140 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4141 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
4142 | /* Structures should be aligned to eight bytes (even arg registers) |
4143 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4144 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
4145 | && mips_type_needs_double_align (arg_type)) |
4146 | { | |
4147 | if ((argreg & 1)) | |
6d82d43b | 4148 | argreg++; |
46cac009 AC |
4149 | } |
4150 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4151 | register are only written to memory. */ |
46cac009 AC |
4152 | while (len > 0) |
4153 | { | |
4154 | /* Remember if the argument was written to the stack. */ | |
4155 | int stack_used_p = 0; | |
13326b4e AC |
4156 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4157 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
4158 | |
4159 | if (mips_debug) | |
4160 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4161 | partial_len); | |
4162 | ||
4163 | /* Write this portion of the argument to the stack. */ | |
4164 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4165 | || odd_sized_struct | |
4166 | || fp_register_arg_p (typecode, arg_type)) | |
4167 | { | |
4168 | /* Should shorter than int integer values be | |
4169 | promoted to int before being stored? */ | |
4170 | int longword_offset = 0; | |
4171 | CORE_ADDR addr; | |
4172 | stack_used_p = 1; | |
4173 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4174 | { | |
13326b4e | 4175 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4176 | && (typecode == TYPE_CODE_INT |
4177 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4178 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4179 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
4180 | } |
4181 | ||
4182 | if (mips_debug) | |
4183 | { | |
4184 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4185 | paddr_nz (stack_offset)); | |
4186 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4187 | paddr_nz (longword_offset)); | |
4188 | } | |
4189 | ||
4190 | addr = sp + stack_offset + longword_offset; | |
4191 | ||
4192 | if (mips_debug) | |
4193 | { | |
4194 | int i; | |
6d82d43b | 4195 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
4196 | paddr_nz (addr)); |
4197 | for (i = 0; i < partial_len; i++) | |
4198 | { | |
6d82d43b | 4199 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
4200 | val[i] & 0xff); |
4201 | } | |
4202 | } | |
4203 | write_memory (addr, val, partial_len); | |
4204 | } | |
4205 | ||
4206 | /* Note!!! This is NOT an else clause. Odd sized | |
4207 | structs may go thru BOTH paths. Floating point | |
4208 | arguments will not. */ | |
4209 | /* Write this portion of the argument to a general | |
6d82d43b | 4210 | purpose register. */ |
46cac009 AC |
4211 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4212 | && !fp_register_arg_p (typecode, arg_type)) | |
4213 | { | |
4214 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4215 | /* Value may need to be sign extended, because |
1b13c4f6 | 4216 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
4217 | |
4218 | /* A non-floating-point argument being passed in a | |
4219 | general register. If a struct or union, and if | |
4220 | the remaining length is smaller than the register | |
4221 | size, we have to adjust the register value on | |
4222 | big endian targets. | |
4223 | ||
4224 | It does not seem to be necessary to do the | |
4225 | same for integral types. | |
4226 | ||
4227 | Also don't do this adjustment on O64 binaries. | |
4228 | ||
4229 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4230 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4231 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
4232 | part of storing the argument in a register a |
4233 | register (the left shift isn't generated when | |
1b13c4f6 | 4234 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4235 | it is quite possible that this is GCC |
4236 | contradicting the LE/O32 ABI, GDB has not been | |
4237 | adjusted to accommodate this. Either someone | |
4238 | needs to demonstrate that the LE/O32 ABI | |
4239 | specifies such a left shift OR this new ABI gets | |
4240 | identified as such and GDB gets tweaked | |
4241 | accordingly. */ | |
4242 | ||
13326b4e | 4243 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 4244 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4245 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
4246 | && (typecode == TYPE_CODE_STRUCT || |
4247 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4248 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
4249 | TARGET_CHAR_BIT); |
4250 | ||
4251 | if (mips_debug) | |
4252 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4253 | argreg, | |
6d82d43b | 4254 | phex (regval, |
13326b4e | 4255 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
4256 | write_register (argreg, regval); |
4257 | argreg++; | |
4258 | ||
4259 | /* Prevent subsequent floating point arguments from | |
4260 | being passed in floating point registers. */ | |
4261 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4262 | } | |
4263 | ||
4264 | len -= partial_len; | |
4265 | val += partial_len; | |
4266 | ||
4267 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4268 | will copy the next parameter. |
46cac009 | 4269 | |
6d82d43b AC |
4270 | In older ABIs, the caller reserved space for |
4271 | registers that contained arguments. This was loosely | |
4272 | refered to as their "home". Consequently, space is | |
4273 | always allocated. */ | |
46cac009 | 4274 | |
480d3dd2 | 4275 | stack_offset += align_up (partial_len, |
13326b4e | 4276 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
4277 | } |
4278 | } | |
4279 | if (mips_debug) | |
4280 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4281 | } | |
4282 | ||
f10683bb | 4283 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4284 | |
46cac009 AC |
4285 | /* Return adjusted stack pointer. */ |
4286 | return sp; | |
4287 | } | |
4288 | ||
6d82d43b AC |
4289 | static enum return_value_convention |
4290 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
4291 | struct regcache *regcache, | |
4292 | void *readbuf, const void *writebuf) | |
4293 | { | |
4294 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4295 | ||
4296 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4297 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4298 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4299 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4300 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4301 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4302 | { | |
4303 | /* A single-precision floating-point value. It fits in the | |
4304 | least significant part of FP0. */ | |
4305 | if (mips_debug) | |
4306 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4307 | mips_xfer_register (regcache, | |
4308 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
4309 | TYPE_LENGTH (type), | |
4310 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4311 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4312 | } | |
4313 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4314 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4315 | { | |
4316 | /* A double-precision floating-point value. The most | |
4317 | significant part goes in FP1, and the least significant in | |
4318 | FP0. */ | |
4319 | if (mips_debug) | |
4320 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4321 | switch (TARGET_BYTE_ORDER) | |
4322 | { | |
4323 | case BFD_ENDIAN_LITTLE: | |
4324 | mips_xfer_register (regcache, | |
4325 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4326 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4327 | mips_xfer_register (regcache, | |
4328 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4329 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4330 | break; | |
4331 | case BFD_ENDIAN_BIG: | |
4332 | mips_xfer_register (regcache, | |
4333 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4334 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
4335 | mips_xfer_register (regcache, | |
4336 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
4337 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
4338 | break; | |
4339 | default: | |
4340 | internal_error (__FILE__, __LINE__, "bad switch"); | |
4341 | } | |
4342 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4343 | } | |
4344 | #if 0 | |
4345 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4346 | && TYPE_NFIELDS (type) <= 2 | |
4347 | && TYPE_NFIELDS (type) >= 1 | |
4348 | && ((TYPE_NFIELDS (type) == 1 | |
4349 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4350 | == TYPE_CODE_FLT)) | |
4351 | || (TYPE_NFIELDS (type) == 2 | |
4352 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4353 | == TYPE_CODE_FLT) | |
4354 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4355 | == TYPE_CODE_FLT))) | |
4356 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4357 | { | |
4358 | /* A struct that contains one or two floats. Each value is part | |
4359 | in the least significant part of their floating point | |
4360 | register.. */ | |
4361 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
4362 | int regnum; | |
4363 | int field; | |
4364 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
4365 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
4366 | { | |
4367 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4368 | / TARGET_CHAR_BIT); | |
4369 | if (mips_debug) | |
4370 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4371 | offset); | |
4372 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
4373 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4374 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4375 | } | |
4376 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4377 | } | |
4378 | #endif | |
4379 | #if 0 | |
4380 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4381 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4382 | { | |
4383 | /* A structure or union. Extract the left justified value, | |
4384 | regardless of the byte order. I.e. DO NOT USE | |
4385 | mips_xfer_lower. */ | |
4386 | int offset; | |
4387 | int regnum; | |
4388 | for (offset = 0, regnum = V0_REGNUM; | |
4389 | offset < TYPE_LENGTH (type); | |
4390 | offset += register_size (current_gdbarch, regnum), regnum++) | |
4391 | { | |
4392 | int xfer = register_size (current_gdbarch, regnum); | |
4393 | if (offset + xfer > TYPE_LENGTH (type)) | |
4394 | xfer = TYPE_LENGTH (type) - offset; | |
4395 | if (mips_debug) | |
4396 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4397 | offset, xfer, regnum); | |
4398 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4399 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
4400 | } | |
4401 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4402 | } | |
4403 | #endif | |
4404 | else | |
4405 | { | |
4406 | /* A scalar extract each part but least-significant-byte | |
4407 | justified. o32 thinks registers are 4 byte, regardless of | |
4408 | the ISA. mips_stack_argsize controls this. */ | |
4409 | int offset; | |
4410 | int regnum; | |
4411 | for (offset = 0, regnum = V0_REGNUM; | |
4412 | offset < TYPE_LENGTH (type); | |
13326b4e | 4413 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 4414 | { |
13326b4e | 4415 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
4416 | if (offset + xfer > TYPE_LENGTH (type)) |
4417 | xfer = TYPE_LENGTH (type) - offset; | |
4418 | if (mips_debug) | |
4419 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4420 | offset, xfer, regnum); | |
4421 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4422 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4423 | } | |
4424 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4425 | } | |
4426 | } | |
4427 | ||
4428 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4429 | ABI. */ | |
46cac009 AC |
4430 | |
4431 | static CORE_ADDR | |
7d9b040b | 4432 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4433 | struct regcache *regcache, CORE_ADDR bp_addr, |
4434 | int nargs, | |
4435 | struct value **args, CORE_ADDR sp, | |
4436 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4437 | { |
4438 | int argreg; | |
4439 | int float_argreg; | |
4440 | int argnum; | |
4441 | int len = 0; | |
4442 | int stack_offset = 0; | |
480d3dd2 | 4443 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 4444 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4445 | |
25ab4790 AC |
4446 | /* For shared libraries, "t9" needs to point at the function |
4447 | address. */ | |
4448 | regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); | |
4449 | ||
4450 | /* Set the return address register to point to the entry point of | |
4451 | the program, where a breakpoint lies in wait. */ | |
4452 | regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); | |
4453 | ||
46cac009 AC |
4454 | /* First ensure that the stack and structure return address (if any) |
4455 | are properly aligned. The stack has to be at least 64-bit | |
4456 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4457 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4458 | aligned, so we round to this widest known alignment. */ | |
4459 | ||
5b03f266 AC |
4460 | sp = align_down (sp, 16); |
4461 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4462 | |
4463 | /* Now make space on the stack for the args. */ | |
4464 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4465 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4466 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4467 | sp -= align_up (len, 16); |
46cac009 AC |
4468 | |
4469 | if (mips_debug) | |
6d82d43b | 4470 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4471 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
4472 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
4473 | |
4474 | /* Initialize the integer and float register pointers. */ | |
4475 | argreg = A0_REGNUM; | |
56cea623 | 4476 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4477 | |
4478 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4479 | if (struct_return) | |
4480 | { | |
4481 | if (mips_debug) | |
4482 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4483 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4484 | argreg, paddr_nz (struct_addr)); |
4485 | write_register (argreg++, struct_addr); | |
13326b4e | 4486 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
4487 | } |
4488 | ||
4489 | /* Now load as many as possible of the first arguments into | |
4490 | registers, and push the rest onto the stack. Loop thru args | |
4491 | from first to last. */ | |
4492 | for (argnum = 0; argnum < nargs; argnum++) | |
4493 | { | |
4494 | char *val; | |
46cac009 AC |
4495 | struct value *arg = args[argnum]; |
4496 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4497 | int len = TYPE_LENGTH (arg_type); | |
4498 | enum type_code typecode = TYPE_CODE (arg_type); | |
4499 | ||
4500 | if (mips_debug) | |
4501 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4502 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4503 | argnum + 1, len, (int) typecode); |
4504 | ||
4505 | val = (char *) VALUE_CONTENTS (arg); | |
4506 | ||
4507 | /* 32-bit ABIs always start floating point arguments in an | |
4508 | even-numbered floating point register. Round the FP register | |
4509 | up before the check to see if there are any FP registers | |
4510 | left. O32/O64 targets also pass the FP in the integer | |
4511 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4512 | if (mips_abi_regsize (gdbarch) < 8 |
4513 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
4514 | { |
4515 | if ((float_argreg & 1)) | |
4516 | float_argreg++; | |
4517 | } | |
4518 | ||
4519 | /* Floating point arguments passed in registers have to be | |
4520 | treated specially. On 32-bit architectures, doubles | |
4521 | are passed in register pairs; the even register gets | |
4522 | the low word, and the odd register gets the high word. | |
4523 | On O32/O64, the first two floating point arguments are | |
4524 | also copied to general registers, because MIPS16 functions | |
4525 | don't use float registers for arguments. This duplication of | |
4526 | arguments in general registers can't hurt non-MIPS16 functions | |
4527 | because those registers are normally skipped. */ | |
4528 | ||
4529 | if (fp_register_arg_p (typecode, arg_type) | |
4530 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4531 | { | |
ceae6e75 | 4532 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
4533 | { |
4534 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4535 | unsigned long regval; | |
4536 | ||
4537 | /* Write the low word of the double to the even register(s). */ | |
4538 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4539 | if (mips_debug) | |
4540 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4541 | float_argreg, phex (regval, 4)); | |
4542 | write_register (float_argreg++, regval); | |
4543 | if (mips_debug) | |
4544 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4545 | argreg, phex (regval, 4)); | |
4546 | write_register (argreg++, regval); | |
4547 | ||
4548 | /* Write the high word of the double to the odd register(s). */ | |
4549 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4550 | if (mips_debug) | |
4551 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4552 | float_argreg, phex (regval, 4)); | |
4553 | write_register (float_argreg++, regval); | |
4554 | ||
4555 | if (mips_debug) | |
4556 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4557 | argreg, phex (regval, 4)); | |
4558 | write_register (argreg++, regval); | |
4559 | } | |
4560 | else | |
4561 | { | |
4562 | /* This is a floating point value that fits entirely | |
4563 | in a single register. */ | |
4564 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4565 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4566 | LONGEST regval = extract_unsigned_integer (val, len); |
4567 | if (mips_debug) | |
4568 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4569 | float_argreg, phex (regval, len)); | |
4570 | write_register (float_argreg++, regval); | |
4571 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4572 | registers for each argument. The below is (my |
4573 | guess) to ensure that the corresponding integer | |
4574 | register has reserved the same space. */ | |
ebafbe83 MS |
4575 | if (mips_debug) |
4576 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4577 | argreg, phex (regval, len)); | |
4578 | write_register (argreg, regval); | |
ceae6e75 | 4579 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4580 | } |
4581 | /* Reserve space for the FP register. */ | |
13326b4e | 4582 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4583 | } |
4584 | else | |
4585 | { | |
4586 | /* Copy the argument to general registers or the stack in | |
4587 | register-sized pieces. Large arguments are split between | |
4588 | registers and stack. */ | |
4246e332 | 4589 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4590 | mips_abi_regsize() are treated specially: Irix cc passes |
4591 | them in registers where gcc sometimes puts them on the | |
4592 | stack. For maximum compatibility, we will put them in | |
4593 | both places. */ | |
13326b4e AC |
4594 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4595 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4596 | /* Structures should be aligned to eight bytes (even arg registers) |
4597 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4598 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4599 | && mips_type_needs_double_align (arg_type)) |
4600 | { | |
4601 | if ((argreg & 1)) | |
6d82d43b | 4602 | argreg++; |
ebafbe83 MS |
4603 | } |
4604 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4605 | register are only written to memory. */ |
ebafbe83 MS |
4606 | while (len > 0) |
4607 | { | |
4608 | /* Remember if the argument was written to the stack. */ | |
4609 | int stack_used_p = 0; | |
13326b4e AC |
4610 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4611 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4612 | |
4613 | if (mips_debug) | |
4614 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4615 | partial_len); | |
4616 | ||
4617 | /* Write this portion of the argument to the stack. */ | |
4618 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4619 | || odd_sized_struct | |
4620 | || fp_register_arg_p (typecode, arg_type)) | |
4621 | { | |
4622 | /* Should shorter than int integer values be | |
4623 | promoted to int before being stored? */ | |
4624 | int longword_offset = 0; | |
4625 | CORE_ADDR addr; | |
4626 | stack_used_p = 1; | |
4627 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4628 | { | |
13326b4e | 4629 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4630 | && (typecode == TYPE_CODE_INT |
4631 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4632 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4633 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4634 | } |
4635 | ||
4636 | if (mips_debug) | |
4637 | { | |
4638 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4639 | paddr_nz (stack_offset)); | |
4640 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4641 | paddr_nz (longword_offset)); | |
4642 | } | |
4643 | ||
4644 | addr = sp + stack_offset + longword_offset; | |
4645 | ||
4646 | if (mips_debug) | |
4647 | { | |
4648 | int i; | |
6d82d43b | 4649 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4650 | paddr_nz (addr)); |
4651 | for (i = 0; i < partial_len; i++) | |
4652 | { | |
6d82d43b | 4653 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4654 | val[i] & 0xff); |
4655 | } | |
4656 | } | |
4657 | write_memory (addr, val, partial_len); | |
4658 | } | |
4659 | ||
4660 | /* Note!!! This is NOT an else clause. Odd sized | |
4661 | structs may go thru BOTH paths. Floating point | |
4662 | arguments will not. */ | |
4663 | /* Write this portion of the argument to a general | |
6d82d43b | 4664 | purpose register. */ |
ebafbe83 MS |
4665 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4666 | && !fp_register_arg_p (typecode, arg_type)) | |
4667 | { | |
4668 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4669 | /* Value may need to be sign extended, because |
1b13c4f6 | 4670 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4671 | |
4672 | /* A non-floating-point argument being passed in a | |
4673 | general register. If a struct or union, and if | |
4674 | the remaining length is smaller than the register | |
4675 | size, we have to adjust the register value on | |
4676 | big endian targets. | |
4677 | ||
4678 | It does not seem to be necessary to do the | |
4679 | same for integral types. | |
4680 | ||
4681 | Also don't do this adjustment on O64 binaries. | |
4682 | ||
4683 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4684 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4685 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4686 | part of storing the argument in a register a |
4687 | register (the left shift isn't generated when | |
1b13c4f6 | 4688 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4689 | it is quite possible that this is GCC |
4690 | contradicting the LE/O32 ABI, GDB has not been | |
4691 | adjusted to accommodate this. Either someone | |
4692 | needs to demonstrate that the LE/O32 ABI | |
4693 | specifies such a left shift OR this new ABI gets | |
4694 | identified as such and GDB gets tweaked | |
4695 | accordingly. */ | |
4696 | ||
13326b4e | 4697 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4698 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4699 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4700 | && (typecode == TYPE_CODE_STRUCT || |
4701 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4702 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4703 | TARGET_CHAR_BIT); |
4704 | ||
4705 | if (mips_debug) | |
4706 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4707 | argreg, | |
6d82d43b | 4708 | phex (regval, |
13326b4e | 4709 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4710 | write_register (argreg, regval); |
4711 | argreg++; | |
4712 | ||
4713 | /* Prevent subsequent floating point arguments from | |
4714 | being passed in floating point registers. */ | |
4715 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4716 | } | |
4717 | ||
4718 | len -= partial_len; | |
4719 | val += partial_len; | |
4720 | ||
4721 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4722 | will copy the next parameter. |
ebafbe83 | 4723 | |
6d82d43b AC |
4724 | In older ABIs, the caller reserved space for |
4725 | registers that contained arguments. This was loosely | |
4726 | refered to as their "home". Consequently, space is | |
4727 | always allocated. */ | |
ebafbe83 | 4728 | |
480d3dd2 | 4729 | stack_offset += align_up (partial_len, |
13326b4e | 4730 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4731 | } |
4732 | } | |
4733 | if (mips_debug) | |
4734 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4735 | } | |
4736 | ||
f10683bb | 4737 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4738 | |
ebafbe83 MS |
4739 | /* Return adjusted stack pointer. */ |
4740 | return sp; | |
4741 | } | |
4742 | ||
f7ab6ec6 | 4743 | static void |
6d82d43b AC |
4744 | mips_o64_extract_return_value (struct type *valtype, |
4745 | char regbuf[], char *valbuf) | |
c906108c | 4746 | { |
6d82d43b AC |
4747 | struct return_value_word lo; |
4748 | struct return_value_word hi; | |
4749 | return_value_location (valtype, &hi, &lo); | |
c906108c | 4750 | |
6d82d43b AC |
4751 | memcpy (valbuf + lo.buf_offset, |
4752 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + | |
4753 | lo.reg_offset, lo.len); | |
4754 | ||
4755 | if (hi.len > 0) | |
4756 | memcpy (valbuf + hi.buf_offset, | |
4757 | regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + | |
4758 | hi.reg_offset, hi.len); | |
4759 | } | |
4760 | ||
4761 | static void | |
4762 | mips_o64_store_return_value (struct type *valtype, char *valbuf) | |
4763 | { | |
4764 | char raw_buffer[MAX_REGISTER_SIZE]; | |
4765 | struct return_value_word lo; | |
4766 | struct return_value_word hi; | |
4767 | return_value_location (valtype, &hi, &lo); | |
4768 | ||
4769 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4770 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4771 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), | |
4772 | raw_buffer, register_size (current_gdbarch, | |
4773 | lo.reg)); | |
4774 | ||
4775 | if (hi.len > 0) | |
4776 | { | |
4777 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4778 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4779 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), | |
4780 | raw_buffer, | |
4781 | register_size (current_gdbarch, | |
4782 | hi.reg)); | |
4783 | } | |
4784 | } | |
4785 | ||
dd824b04 DJ |
4786 | /* Floating point register management. |
4787 | ||
4788 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4789 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4790 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4791 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4792 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4793 | double precision floats into two 32-bit chunks and store them in | |
4794 | consecutive fp regs. To display 64-bit floats stored in this | |
4795 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4796 | Throw in user-configurable endianness and you have a real mess. | |
4797 | ||
4798 | The way this works is: | |
4799 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4800 | double-precision value will be split across two logical registers. | |
4801 | The lower-numbered logical register will hold the low-order bits, | |
4802 | regardless of the processor's endianness. | |
4803 | - If we are on a 64-bit processor, and we are looking for a | |
4804 | single-precision value, it will be in the low ordered bits | |
4805 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4806 | save slot in memory. | |
4807 | - If we are in 64-bit mode, everything is straightforward. | |
4808 | ||
4809 | Note that this code only deals with "live" registers at the top of the | |
4810 | stack. We will attempt to deal with saved registers later, when | |
4811 | the raw/cooked register interface is in place. (We need a general | |
4812 | interface that can deal with dynamic saved register sizes -- fp | |
4813 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4814 | and below). */ | |
4815 | ||
67b2c998 DJ |
4816 | static struct type * |
4817 | mips_float_register_type (void) | |
4818 | { | |
361d1df0 | 4819 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4820 | return builtin_type_ieee_single_big; |
4821 | else | |
4822 | return builtin_type_ieee_single_little; | |
4823 | } | |
4824 | ||
4825 | static struct type * | |
4826 | mips_double_register_type (void) | |
4827 | { | |
361d1df0 | 4828 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4829 | return builtin_type_ieee_double_big; |
4830 | else | |
4831 | return builtin_type_ieee_double_little; | |
4832 | } | |
4833 | ||
dd824b04 DJ |
4834 | /* Copy a 32-bit single-precision value from the current frame |
4835 | into rare_buffer. */ | |
4836 | ||
4837 | static void | |
e11c53d2 AC |
4838 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4839 | char *rare_buffer) | |
dd824b04 | 4840 | { |
719ec221 | 4841 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4842 | char *raw_buffer = alloca (raw_size); |
4843 | ||
e11c53d2 | 4844 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4845 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4846 | if (raw_size == 8) | |
4847 | { | |
4848 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4849 | 32 bits. */ |
dd824b04 DJ |
4850 | int offset; |
4851 | ||
4852 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4853 | offset = 4; | |
4854 | else | |
4855 | offset = 0; | |
4856 | ||
4857 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4858 | } | |
4859 | else | |
4860 | { | |
4861 | memcpy (rare_buffer, raw_buffer, 4); | |
4862 | } | |
4863 | } | |
4864 | ||
4865 | /* Copy a 64-bit double-precision value from the current frame into | |
4866 | rare_buffer. This may include getting half of it from the next | |
4867 | register. */ | |
4868 | ||
4869 | static void | |
e11c53d2 AC |
4870 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4871 | char *rare_buffer) | |
dd824b04 | 4872 | { |
719ec221 | 4873 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4874 | |
4875 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4876 | { | |
4877 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4878 | all 64 bits. */ |
e11c53d2 | 4879 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4880 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4881 | } | |
4882 | else | |
4883 | { | |
56cea623 | 4884 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4885 | internal_error (__FILE__, __LINE__, |
4886 | "mips_read_fp_register_double: bad access to " | |
4887 | "odd-numbered FP register"); | |
4888 | ||
4889 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4890 | each register. */ |
dd824b04 DJ |
4891 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4892 | { | |
e11c53d2 AC |
4893 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4894 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4895 | } |
361d1df0 | 4896 | else |
dd824b04 | 4897 | { |
e11c53d2 AC |
4898 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4899 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4900 | } |
4901 | } | |
4902 | } | |
4903 | ||
c906108c | 4904 | static void |
e11c53d2 AC |
4905 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4906 | int regnum) | |
c5aa993b | 4907 | { /* do values for FP (float) regs */ |
dd824b04 | 4908 | char *raw_buffer; |
3903d437 AC |
4909 | double doub, flt1; /* doubles extracted from raw hex data */ |
4910 | int inv1, inv2; | |
c5aa993b | 4911 | |
6d82d43b AC |
4912 | raw_buffer = |
4913 | (char *) alloca (2 * | |
4914 | register_size (current_gdbarch, | |
4915 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4916 | |
e11c53d2 AC |
4917 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4918 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4919 | ""); | |
f0ef6b29 | 4920 | |
719ec221 | 4921 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4922 | { |
f0ef6b29 KB |
4923 | /* 4-byte registers: Print hex and floating. Also print even |
4924 | numbered registers as doubles. */ | |
e11c53d2 | 4925 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4926 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4927 | |
6d82d43b AC |
4928 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4929 | file); | |
dd824b04 | 4930 | |
e11c53d2 | 4931 | fprintf_filtered (file, " flt: "); |
1adad886 | 4932 | if (inv1) |
e11c53d2 | 4933 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4934 | else |
e11c53d2 | 4935 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4936 | |
f0ef6b29 KB |
4937 | if (regnum % 2 == 0) |
4938 | { | |
e11c53d2 | 4939 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4940 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4941 | &inv2); |
1adad886 | 4942 | |
e11c53d2 | 4943 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4944 | if (inv2) |
e11c53d2 | 4945 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4946 | else |
e11c53d2 | 4947 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4948 | } |
c906108c SS |
4949 | } |
4950 | else | |
dd824b04 | 4951 | { |
f0ef6b29 | 4952 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4953 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4954 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4955 | |
e11c53d2 | 4956 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4957 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4958 | ||
361d1df0 | 4959 | |
6d82d43b AC |
4960 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4961 | file); | |
f0ef6b29 | 4962 | |
e11c53d2 | 4963 | fprintf_filtered (file, " flt: "); |
1adad886 | 4964 | if (inv1) |
e11c53d2 | 4965 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4966 | else |
e11c53d2 | 4967 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4968 | |
e11c53d2 | 4969 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4970 | if (inv2) |
e11c53d2 | 4971 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4972 | else |
e11c53d2 | 4973 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4974 | } |
4975 | } | |
4976 | ||
4977 | static void | |
e11c53d2 AC |
4978 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4979 | int regnum, int all) | |
f0ef6b29 | 4980 | { |
a4b8ebc8 | 4981 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4982 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4983 | int offset; |
1adad886 | 4984 | |
a4b8ebc8 | 4985 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4986 | { |
e11c53d2 | 4987 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4988 | return; |
4989 | } | |
4990 | ||
4991 | /* Get the data in raw format. */ | |
e11c53d2 | 4992 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4993 | { |
e11c53d2 | 4994 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4995 | return; |
c906108c | 4996 | } |
f0ef6b29 | 4997 | |
e11c53d2 | 4998 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4999 | |
5000 | /* The problem with printing numeric register names (r26, etc.) is that | |
5001 | the user can't use them on input. Probably the best solution is to | |
5002 | fix it so that either the numeric or the funky (a2, etc.) names | |
5003 | are accepted on input. */ | |
5004 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 5005 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 5006 | else |
e11c53d2 | 5007 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
5008 | |
5009 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
5010 | offset = |
5011 | register_size (current_gdbarch, | |
5012 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
5013 | else |
5014 | offset = 0; | |
5015 | ||
6d82d43b AC |
5016 | print_scalar_formatted (raw_buffer + offset, |
5017 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
5018 | file); | |
c906108c SS |
5019 | } |
5020 | ||
f0ef6b29 KB |
5021 | /* Replacement for generic do_registers_info. |
5022 | Print regs in pretty columns. */ | |
5023 | ||
5024 | static int | |
e11c53d2 AC |
5025 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
5026 | int regnum) | |
f0ef6b29 | 5027 | { |
e11c53d2 AC |
5028 | fprintf_filtered (file, " "); |
5029 | mips_print_fp_register (file, frame, regnum); | |
5030 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
5031 | return regnum + 1; |
5032 | } | |
5033 | ||
5034 | ||
c906108c SS |
5035 | /* Print a row's worth of GP (int) registers, with name labels above */ |
5036 | ||
5037 | static int | |
e11c53d2 | 5038 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 5039 | int start_regnum) |
c906108c | 5040 | { |
a4b8ebc8 | 5041 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 5042 | /* do values for GP (int) regs */ |
d9d9c31f | 5043 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 5044 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 5045 | int col, byte; |
a4b8ebc8 | 5046 | int regnum; |
c906108c SS |
5047 | |
5048 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 5049 | fprintf_filtered (file, " "); |
a4b8ebc8 | 5050 | for (col = 0, regnum = start_regnum; |
6d82d43b | 5051 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
5052 | { |
5053 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 5054 | continue; /* unused register */ |
6d82d43b AC |
5055 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5056 | TYPE_CODE_FLT) | |
c5aa993b | 5057 | break; /* end the row: reached FP register */ |
6d82d43b | 5058 | fprintf_filtered (file, |
d5ac5a39 | 5059 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 5060 | REGISTER_NAME (regnum)); |
c906108c SS |
5061 | col++; |
5062 | } | |
a4b8ebc8 | 5063 | /* print the R0 to R31 names */ |
20e6603c AC |
5064 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
5065 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
5066 | else | |
5067 | fprintf_filtered (file, "\n "); | |
c906108c | 5068 | |
c906108c | 5069 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 5070 | for (col = 0, regnum = start_regnum; |
6d82d43b | 5071 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
5072 | { |
5073 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 5074 | continue; /* unused register */ |
6d82d43b AC |
5075 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5076 | TYPE_CODE_FLT) | |
c5aa993b | 5077 | break; /* end row: reached FP register */ |
c906108c | 5078 | /* OK: get the data in raw format. */ |
e11c53d2 | 5079 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
5080 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
5081 | /* pad small registers */ | |
4246e332 | 5082 | for (byte = 0; |
d5ac5a39 | 5083 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 5084 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
5085 | printf_filtered (" "); |
5086 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 5087 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
5088 | for (byte = |
5089 | register_size (current_gdbarch, | |
5090 | regnum) - register_size (current_gdbarch, regnum); | |
5091 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 5092 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 5093 | else |
c73e8f27 | 5094 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 5095 | byte >= 0; byte--) |
e11c53d2 AC |
5096 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
5097 | fprintf_filtered (file, " "); | |
c906108c SS |
5098 | col++; |
5099 | } | |
c5aa993b | 5100 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 5101 | fprintf_filtered (file, "\n"); |
c906108c SS |
5102 | |
5103 | return regnum; | |
5104 | } | |
5105 | ||
5106 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
5107 | ||
bf1f5b4c | 5108 | static void |
e11c53d2 AC |
5109 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
5110 | struct frame_info *frame, int regnum, int all) | |
c906108c | 5111 | { |
c5aa993b | 5112 | if (regnum != -1) /* do one specified register */ |
c906108c | 5113 | { |
a4b8ebc8 | 5114 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
5115 | if (*(REGISTER_NAME (regnum)) == '\0') |
5116 | error ("Not a valid register for the current processor type"); | |
5117 | ||
e11c53d2 AC |
5118 | mips_print_register (file, frame, regnum, 0); |
5119 | fprintf_filtered (file, "\n"); | |
c906108c | 5120 | } |
c5aa993b JM |
5121 | else |
5122 | /* do all (or most) registers */ | |
c906108c | 5123 | { |
a4b8ebc8 AC |
5124 | regnum = NUM_REGS; |
5125 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 5126 | { |
6d82d43b AC |
5127 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
5128 | TYPE_CODE_FLT) | |
e11c53d2 AC |
5129 | { |
5130 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
5131 | regnum = print_fp_register_row (file, frame, regnum); | |
5132 | else | |
5133 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
5134 | } | |
c906108c | 5135 | else |
e11c53d2 | 5136 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
5137 | } |
5138 | } | |
5139 | } | |
5140 | ||
c906108c SS |
5141 | /* Is this a branch with a delay slot? */ |
5142 | ||
a14ed312 | 5143 | static int is_delayed (unsigned long); |
c906108c SS |
5144 | |
5145 | static int | |
acdb74a0 | 5146 | is_delayed (unsigned long insn) |
c906108c SS |
5147 | { |
5148 | int i; | |
5149 | for (i = 0; i < NUMOPCODES; ++i) | |
5150 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
5151 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
5152 | break; | |
5153 | return (i < NUMOPCODES | |
5154 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
5155 | | INSN_COND_BRANCH_DELAY | |
5156 | | INSN_COND_BRANCH_LIKELY))); | |
5157 | } | |
5158 | ||
5159 | int | |
acdb74a0 | 5160 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
5161 | { |
5162 | char buf[MIPS_INSTLEN]; | |
5163 | ||
5164 | /* There is no branch delay slot on MIPS16. */ | |
5165 | if (pc_is_mips16 (pc)) | |
5166 | return 0; | |
5167 | ||
5168 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
5169 | /* If error reading memory, guess that it is not a delayed branch. */ | |
5170 | return 0; | |
6d82d43b AC |
5171 | return is_delayed ((unsigned long) |
5172 | extract_unsigned_integer (buf, MIPS_INSTLEN)); | |
c906108c SS |
5173 | } |
5174 | ||
c906108c SS |
5175 | /* Skip the PC past function prologue instructions (32-bit version). |
5176 | This is a helper function for mips_skip_prologue. */ | |
5177 | ||
5178 | static CORE_ADDR | |
f7b9e9fc | 5179 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 5180 | { |
c5aa993b JM |
5181 | t_inst inst; |
5182 | CORE_ADDR end_pc; | |
5183 | int seen_sp_adjust = 0; | |
5184 | int load_immediate_bytes = 0; | |
5185 | ||
74da7425 AC |
5186 | /* Find an upper bound on the prologue. */ |
5187 | end_pc = skip_prologue_using_sal (pc); | |
5188 | if (end_pc == 0) | |
6d82d43b | 5189 | end_pc = pc + 100; /* Magic. */ |
74da7425 | 5190 | |
c5aa993b JM |
5191 | /* Skip the typical prologue instructions. These are the stack adjustment |
5192 | instruction and the instructions that save registers on the stack | |
5193 | or in the gcc frame. */ | |
74da7425 | 5194 | for (; pc < end_pc; pc += MIPS_INSTLEN) |
c5aa993b JM |
5195 | { |
5196 | unsigned long high_word; | |
c906108c | 5197 | |
c5aa993b JM |
5198 | inst = mips_fetch_instruction (pc); |
5199 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 5200 | |
c5aa993b JM |
5201 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
5202 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
5203 | seen_sp_adjust = 1; | |
5204 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
5205 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
5206 | seen_sp_adjust = 1; | |
5207 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
5208 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
5209 | && (inst & 0x001F0000)) /* reg != $zero */ | |
5210 | continue; | |
5211 | ||
5212 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
5213 | continue; | |
5214 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
5215 | /* sx reg,n($s8) */ | |
5216 | continue; /* reg != $zero */ | |
5217 | ||
5218 | /* move $s8,$sp. With different versions of gas this will be either | |
5219 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
5220 | Accept any one of these. */ | |
5221 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
5222 | continue; | |
5223 | ||
5224 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
5225 | continue; | |
6d82d43b AC |
5226 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
5227 | continue; | |
5228 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
5229 | continue; | |
5230 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
5231 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
5232 | continue; | |
5233 | /* The following instructions load $at or $t0 with an immediate | |
5234 | value in preparation for a stack adjustment via | |
5235 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
5236 | a local variable, so we accept them only before a stack adjustment | |
5237 | instruction was seen. */ | |
5238 | else if (!seen_sp_adjust) | |
cb1d2653 | 5239 | { |
6d82d43b AC |
5240 | if (high_word == 0x3c01 || /* lui $at,n */ |
5241 | high_word == 0x3c08) /* lui $t0,n */ | |
5242 | { | |
5243 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
5244 | continue; | |
5245 | } | |
5246 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
5247 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
5248 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
5249 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
5250 | { | |
5251 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
5252 | continue; | |
5253 | } | |
5254 | else | |
5255 | break; | |
cb1d2653 | 5256 | } |
6d82d43b AC |
5257 | else |
5258 | break; | |
46cac009 | 5259 | } |
6d82d43b AC |
5260 | |
5261 | /* In a frameless function, we might have incorrectly | |
5262 | skipped some load immediate instructions. Undo the skipping | |
5263 | if the load immediate was not followed by a stack adjustment. */ | |
5264 | if (load_immediate_bytes && !seen_sp_adjust) | |
5265 | pc -= load_immediate_bytes; | |
5266 | return pc; | |
46cac009 AC |
5267 | } |
5268 | ||
6d82d43b AC |
5269 | /* Skip the PC past function prologue instructions (16-bit version). |
5270 | This is a helper function for mips_skip_prologue. */ | |
cb1d2653 | 5271 | |
6d82d43b AC |
5272 | static CORE_ADDR |
5273 | mips16_skip_prologue (CORE_ADDR pc) | |
c906108c | 5274 | { |
6d82d43b AC |
5275 | CORE_ADDR end_pc; |
5276 | int extend_bytes = 0; | |
5277 | int prev_extend_bytes; | |
5278 | ||
5279 | /* Table of instructions likely to be found in a function prologue. */ | |
5280 | static struct | |
5281 | { | |
5282 | unsigned short inst; | |
5283 | unsigned short mask; | |
5284 | } | |
5285 | table[] = | |
5286 | { | |
7a292a7a | 5287 | { |
6d82d43b AC |
5288 | 0x6300, 0xff00} |
5289 | , /* addiu $sp,offset */ | |
88658117 | 5290 | { |
6d82d43b AC |
5291 | 0xfb00, 0xff00} |
5292 | , /* daddiu $sp,offset */ | |
88658117 | 5293 | { |
6d82d43b AC |
5294 | 0xd000, 0xf800} |
5295 | , /* sw reg,n($sp) */ | |
5296 | { | |
5297 | 0xf900, 0xff00} | |
5298 | , /* sd reg,n($sp) */ | |
5299 | { | |
5300 | 0x6200, 0xff00} | |
5301 | , /* sw $ra,n($sp) */ | |
5302 | { | |
5303 | 0xfa00, 0xff00} | |
5304 | , /* sd $ra,n($sp) */ | |
5305 | { | |
5306 | 0x673d, 0xffff} | |
5307 | , /* move $s1,sp */ | |
5308 | { | |
5309 | 0xd980, 0xff80} | |
5310 | , /* sw $a0-$a3,n($s1) */ | |
5311 | { | |
5312 | 0x6704, 0xff1c} | |
5313 | , /* move reg,$a0-$a3 */ | |
5314 | { | |
5315 | 0xe809, 0xf81f} | |
5316 | , /* entry pseudo-op */ | |
5317 | { | |
5318 | 0x0100, 0xff00} | |
5319 | , /* addiu $s1,$sp,n */ | |
5320 | { | |
5321 | 0, 0} /* end of table marker */ | |
5322 | }; | |
5323 | ||
5324 | /* Find an upper bound on the prologue. */ | |
5325 | end_pc = skip_prologue_using_sal (pc); | |
5326 | if (end_pc == 0) | |
5327 | end_pc = pc + 100; /* Magic. */ | |
5328 | ||
5329 | /* Skip the typical prologue instructions. These are the stack adjustment | |
5330 | instruction and the instructions that save registers on the stack | |
5331 | or in the gcc frame. */ | |
5332 | for (; pc < end_pc; pc += MIPS16_INSTLEN) | |
5333 | { | |
5334 | unsigned short inst; | |
5335 | int i; | |
5336 | ||
5337 | inst = mips_fetch_instruction (pc); | |
5338 | ||
5339 | /* Normally we ignore an extend instruction. However, if it is | |
5340 | not followed by a valid prologue instruction, we must adjust | |
5341 | the pc back over the extend so that it won't be considered | |
5342 | part of the prologue. */ | |
5343 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
88658117 | 5344 | { |
6d82d43b AC |
5345 | extend_bytes = MIPS16_INSTLEN; |
5346 | continue; | |
88658117 | 5347 | } |
6d82d43b AC |
5348 | prev_extend_bytes = extend_bytes; |
5349 | extend_bytes = 0; | |
5350 | ||
5351 | /* Check for other valid prologue instructions besides extend. */ | |
5352 | for (i = 0; table[i].mask != 0; i++) | |
5353 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
5354 | break; | |
5355 | if (table[i].mask != 0) /* it was in table? */ | |
5356 | continue; /* ignore it */ | |
5357 | else | |
5358 | /* non-prologue */ | |
88658117 | 5359 | { |
6d82d43b AC |
5360 | /* Return the current pc, adjusted backwards by 2 if |
5361 | the previous instruction was an extend. */ | |
5362 | return pc - prev_extend_bytes; | |
88658117 AC |
5363 | } |
5364 | } | |
6d82d43b AC |
5365 | return pc; |
5366 | } | |
5367 | ||
5368 | /* To skip prologues, I use this predicate. Returns either PC itself | |
5369 | if the code at PC does not look like a function prologue; otherwise | |
5370 | returns an address that (if we're lucky) follows the prologue. If | |
5371 | LENIENT, then we must skip everything which is involved in setting | |
5372 | up the frame (it's OK to skip more, just so long as we don't skip | |
5373 | anything which might clobber the registers which are being saved. | |
5374 | We must skip more in the case where part of the prologue is in the | |
5375 | delay slot of a non-prologue instruction). */ | |
5376 | ||
5377 | static CORE_ADDR | |
5378 | mips_skip_prologue (CORE_ADDR pc) | |
5379 | { | |
5380 | /* See if we can determine the end of the prologue via the symbol table. | |
5381 | If so, then return either PC, or the PC after the prologue, whichever | |
5382 | is greater. */ | |
5383 | ||
177f84a3 | 5384 | CORE_ADDR post_prologue_pc = after_prologue (pc); |
6d82d43b AC |
5385 | |
5386 | if (post_prologue_pc != 0) | |
5387 | return max (pc, post_prologue_pc); | |
5388 | ||
5389 | /* Can't determine prologue from the symbol table, need to examine | |
5390 | instructions. */ | |
5391 | ||
5392 | if (pc_is_mips16 (pc)) | |
5393 | return mips16_skip_prologue (pc); | |
5394 | else | |
5395 | return mips32_skip_prologue (pc); | |
88658117 AC |
5396 | } |
5397 | ||
a5ea2558 AC |
5398 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
5399 | used for all MIPS-specific commands. */ | |
5400 | ||
a5ea2558 | 5401 | static void |
acdb74a0 | 5402 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5403 | { |
5404 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5405 | } | |
5406 | ||
a5ea2558 | 5407 | static void |
acdb74a0 | 5408 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5409 | { |
6d82d43b AC |
5410 | printf_unfiltered |
5411 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5412 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5413 | } | |
5414 | ||
c906108c SS |
5415 | /* Commands to show/set the MIPS FPU type. */ |
5416 | ||
c906108c | 5417 | static void |
acdb74a0 | 5418 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5419 | { |
c906108c SS |
5420 | char *fpu; |
5421 | switch (MIPS_FPU_TYPE) | |
5422 | { | |
5423 | case MIPS_FPU_SINGLE: | |
5424 | fpu = "single-precision"; | |
5425 | break; | |
5426 | case MIPS_FPU_DOUBLE: | |
5427 | fpu = "double-precision"; | |
5428 | break; | |
5429 | case MIPS_FPU_NONE: | |
5430 | fpu = "absent (none)"; | |
5431 | break; | |
93d56215 AC |
5432 | default: |
5433 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
5434 | } |
5435 | if (mips_fpu_type_auto) | |
6d82d43b AC |
5436 | printf_unfiltered |
5437 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5438 | fpu); | |
c906108c | 5439 | else |
6d82d43b AC |
5440 | printf_unfiltered |
5441 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5442 | } |
5443 | ||
5444 | ||
c906108c | 5445 | static void |
acdb74a0 | 5446 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5447 | { |
6d82d43b AC |
5448 | printf_unfiltered |
5449 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5450 | show_mipsfpu_command (args, from_tty); |
5451 | } | |
5452 | ||
c906108c | 5453 | static void |
acdb74a0 | 5454 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5455 | { |
8d5838b5 AC |
5456 | struct gdbarch_info info; |
5457 | gdbarch_info_init (&info); | |
c906108c SS |
5458 | mips_fpu_type = MIPS_FPU_SINGLE; |
5459 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5460 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5461 | instead of relying on globals. Doing that would let generic code | |
5462 | handle the search for this specific architecture. */ | |
5463 | if (!gdbarch_update_p (info)) | |
5464 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5465 | } |
5466 | ||
c906108c | 5467 | static void |
acdb74a0 | 5468 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5469 | { |
8d5838b5 AC |
5470 | struct gdbarch_info info; |
5471 | gdbarch_info_init (&info); | |
c906108c SS |
5472 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5473 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5474 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5475 | instead of relying on globals. Doing that would let generic code | |
5476 | handle the search for this specific architecture. */ | |
5477 | if (!gdbarch_update_p (info)) | |
5478 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5479 | } |
5480 | ||
c906108c | 5481 | static void |
acdb74a0 | 5482 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5483 | { |
8d5838b5 AC |
5484 | struct gdbarch_info info; |
5485 | gdbarch_info_init (&info); | |
c906108c SS |
5486 | mips_fpu_type = MIPS_FPU_NONE; |
5487 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5488 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5489 | instead of relying on globals. Doing that would let generic code | |
5490 | handle the search for this specific architecture. */ | |
5491 | if (!gdbarch_update_p (info)) | |
5492 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
5493 | } |
5494 | ||
c906108c | 5495 | static void |
acdb74a0 | 5496 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5497 | { |
5498 | mips_fpu_type_auto = 1; | |
5499 | } | |
5500 | ||
c906108c | 5501 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5502 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5503 | the relevant processor still exists (it dates back to '94) and | |
5504 | secondly this is not the way to do this. The processor type should | |
5505 | be set by forcing an architecture change. */ | |
c906108c | 5506 | |
691c0433 AC |
5507 | void |
5508 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5509 | { |
691c0433 | 5510 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5511 | CORE_ADDR prid; |
5512 | ||
5513 | prid = read_register (PRID_REGNUM); | |
5514 | ||
5515 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 5516 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5517 | } |
5518 | ||
5519 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5520 | callable as an sfunc. */ | |
5521 | ||
5522 | static void | |
acdb74a0 AC |
5523 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5524 | struct cmd_list_element *c) | |
c906108c SS |
5525 | { |
5526 | reinit_frame_cache (); | |
5527 | } | |
5528 | ||
a89aa300 AC |
5529 | static int |
5530 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5531 | { |
e5ab0dce | 5532 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
5533 | mips_extra_func_info_t proc_desc; |
5534 | ||
5535 | /* Search for the function containing this address. Set the low bit | |
5536 | of the address when searching, in case we were given an even address | |
5537 | that is the start of a 16-bit function. If we didn't do this, | |
5538 | the search would fail because the symbol table says the function | |
5539 | starts at an odd address, i.e. 1 byte past the given address. */ | |
5540 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 5541 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
5542 | |
5543 | /* Make an attempt to determine if this is a 16-bit function. If | |
5544 | the procedure descriptor exists and the address therein is odd, | |
5545 | it's definitely a 16-bit function. Otherwise, we have to just | |
5546 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
5547 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5548 | disassembler needs to be able to locally determine the ISA, and | |
5549 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5550 | work. */ | |
c906108c | 5551 | if (proc_desc) |
d31431ed AC |
5552 | { |
5553 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
6d82d43b | 5554 | info->mach = bfd_mach_mips16; |
d31431ed | 5555 | } |
c906108c | 5556 | else |
d31431ed AC |
5557 | { |
5558 | if (pc_is_mips16 (memaddr)) | |
6d82d43b AC |
5559 | info->mach = bfd_mach_mips16; |
5560 | } | |
c906108c SS |
5561 | |
5562 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5563 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5564 | |
e5ab0dce | 5565 | /* Set the disassembler options. */ |
6d82d43b | 5566 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
5567 | { |
5568 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 5569 | register names from libopcodes. */ |
e5ab0dce AC |
5570 | if (tdep->mips_abi == MIPS_ABI_N32) |
5571 | info->disassembler_options = "gpr-names=n32"; | |
5572 | else | |
5573 | info->disassembler_options = "gpr-names=64"; | |
5574 | info->flavour = bfd_target_elf_flavour; | |
5575 | } | |
5576 | else | |
5577 | /* This string is not recognized explicitly by the disassembler, | |
5578 | but it tells the disassembler to not try to guess the ABI from | |
5579 | the bfd elf headers, such that, if the user overrides the ABI | |
5580 | of a program linked as NewABI, the disassembly will follow the | |
5581 | register naming conventions specified by the user. */ | |
5582 | info->disassembler_options = "gpr-names=32"; | |
5583 | ||
c906108c | 5584 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 5585 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5586 | return print_insn_big_mips (memaddr, info); |
5587 | else | |
5588 | return print_insn_little_mips (memaddr, info); | |
5589 | } | |
5590 | ||
c906108c SS |
5591 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
5592 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
5593 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
5594 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5595 | (if necessary) to point to the actual memory location where the | |
5596 | breakpoint should be inserted. */ | |
5597 | ||
f7ab6ec6 | 5598 | static const unsigned char * |
6d82d43b | 5599 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5600 | { |
d7449b42 | 5601 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
5602 | { |
5603 | if (pc_is_mips16 (*pcptr)) | |
5604 | { | |
6d82d43b | 5605 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5606 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5607 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5608 | return mips16_big_breakpoint; |
5609 | } | |
5610 | else | |
5611 | { | |
aaab4dba AC |
5612 | /* The IDT board uses an unusual breakpoint value, and |
5613 | sometimes gets confused when it sees the usual MIPS | |
5614 | breakpoint instruction. */ | |
6d82d43b AC |
5615 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5616 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5617 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5618 | |
c5aa993b | 5619 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5620 | |
5621 | if (strcmp (target_shortname, "mips") == 0) | |
5622 | return idt_big_breakpoint; | |
5623 | else if (strcmp (target_shortname, "ddb") == 0 | |
5624 | || strcmp (target_shortname, "pmon") == 0 | |
5625 | || strcmp (target_shortname, "lsi") == 0) | |
5626 | return pmon_big_breakpoint; | |
5627 | else | |
5628 | return big_breakpoint; | |
5629 | } | |
5630 | } | |
5631 | else | |
5632 | { | |
5633 | if (pc_is_mips16 (*pcptr)) | |
5634 | { | |
6d82d43b | 5635 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5636 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5637 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5638 | return mips16_little_breakpoint; |
5639 | } | |
5640 | else | |
5641 | { | |
6d82d43b AC |
5642 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5643 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5644 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5645 | |
c5aa993b | 5646 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5647 | |
5648 | if (strcmp (target_shortname, "mips") == 0) | |
5649 | return idt_little_breakpoint; | |
5650 | else if (strcmp (target_shortname, "ddb") == 0 | |
5651 | || strcmp (target_shortname, "pmon") == 0 | |
5652 | || strcmp (target_shortname, "lsi") == 0) | |
5653 | return pmon_little_breakpoint; | |
5654 | else | |
5655 | return little_breakpoint; | |
5656 | } | |
5657 | } | |
5658 | } | |
5659 | ||
5660 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5661 | PC, which is either the callee or the caller. There are several | |
5662 | cases which must be handled: | |
5663 | ||
5664 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5665 | target PC is in $31 ($ra). |
c906108c | 5666 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5667 | and the target PC is in $2. |
c906108c | 5668 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5669 | before the jal instruction, this is effectively a call stub |
5670 | and the the target PC is in $2. Otherwise this is effectively | |
5671 | a return stub and the target PC is in $18. | |
c906108c SS |
5672 | |
5673 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
5674 | gory details. | |
5675 | ||
5676 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 5677 | */ |
c906108c | 5678 | |
757a7cc6 | 5679 | static CORE_ADDR |
acdb74a0 | 5680 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
5681 | { |
5682 | char *name; | |
5683 | CORE_ADDR start_addr; | |
5684 | ||
5685 | /* Find the starting address and name of the function containing the PC. */ | |
5686 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5687 | return 0; | |
5688 | ||
5689 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5690 | target PC is in $31 ($ra). */ | |
5691 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5692 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 5693 | return read_signed_register (RA_REGNUM); |
c906108c SS |
5694 | |
5695 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5696 | { | |
5697 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5698 | and the target PC is in $2. */ | |
5699 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5700 | return read_signed_register (2); |
c906108c SS |
5701 | |
5702 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5703 | before the jal instruction, this is effectively a call stub |
5704 | and the the target PC is in $2. Otherwise this is effectively | |
5705 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5706 | else if (name[19] == 's' || name[19] == 'd') |
5707 | { | |
5708 | if (pc == start_addr) | |
5709 | { | |
5710 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5711 | stub. Such a stub for a function bar might have a name |
5712 | like __fn_stub_bar, and might look like this: | |
5713 | mfc1 $4,$f13 | |
5714 | mfc1 $5,$f12 | |
5715 | mfc1 $6,$f15 | |
5716 | mfc1 $7,$f14 | |
5717 | la $1,bar (becomes a lui/addiu pair) | |
5718 | jr $1 | |
5719 | So scan down to the lui/addi and extract the target | |
5720 | address from those two instructions. */ | |
c906108c | 5721 | |
6c997a34 | 5722 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5723 | t_inst inst; |
5724 | int i; | |
5725 | ||
5726 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5727 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5728 | 0) | |
c906108c SS |
5729 | return target_pc; |
5730 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5731 | && strcmp (name, "etext") != 0 | |
5732 | && strcmp (name, "_etext") != 0) | |
5733 | return target_pc; | |
5734 | ||
5735 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5736 | The limit on the search is arbitrarily set to 20 |
5737 | instructions. FIXME. */ | |
c906108c SS |
5738 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
5739 | { | |
c5aa993b JM |
5740 | inst = mips_fetch_instruction (target_pc); |
5741 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5742 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5743 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5744 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5745 | } |
5746 | ||
5747 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5748 | return target_pc; | |
5749 | } | |
5750 | else | |
5751 | /* This is the 'return' part of a call stub. The return | |
5752 | address is in $r18. */ | |
6c997a34 | 5753 | return read_signed_register (18); |
c906108c SS |
5754 | } |
5755 | } | |
c5aa993b | 5756 | return 0; /* not a stub */ |
c906108c SS |
5757 | } |
5758 | ||
5759 | ||
5760 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5761 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5762 | ||
757a7cc6 | 5763 | static int |
acdb74a0 | 5764 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5765 | { |
5766 | CORE_ADDR start_addr; | |
5767 | ||
5768 | /* Find the starting address of the function containing the PC. If the | |
5769 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5770 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5771 | 0) | |
c906108c SS |
5772 | return 0; |
5773 | ||
5774 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5775 | { | |
5776 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5777 | if (name[19] >= '0' && name[19] <= '9') | |
5778 | return 1; | |
5779 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5780 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5781 | else if (name[19] == 's' || name[19] == 'd') |
5782 | return pc == start_addr; | |
5783 | } | |
5784 | ||
c5aa993b | 5785 | return 0; /* not a stub */ |
c906108c SS |
5786 | } |
5787 | ||
5788 | ||
5789 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
5790 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
5791 | ||
e41b17f0 | 5792 | static int |
acdb74a0 | 5793 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5794 | { |
5795 | CORE_ADDR start_addr; | |
5796 | ||
5797 | /* Find the starting address of the function containing the PC. */ | |
5798 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5799 | return 0; | |
5800 | ||
5801 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5802 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5803 | || strcmp (name, "__mips16_ret_df") == 0) | |
5804 | return 1; | |
5805 | ||
5806 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5807 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5808 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5809 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5810 | return 1; |
5811 | ||
c5aa993b | 5812 | return 0; /* not a stub */ |
c906108c SS |
5813 | } |
5814 | ||
5815 | ||
a53c66de AC |
5816 | /* Return non-zero if the PC is in a library helper function that |
5817 | should be ignored. This implements the | |
5818 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
5819 | |
5820 | int | |
acdb74a0 | 5821 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5822 | { |
5823 | char *name; | |
5824 | ||
5825 | /* Find the starting address and name of the function containing the PC. */ | |
5826 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5827 | return 0; | |
5828 | ||
5829 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5830 | that we want to ignore. */ | |
5831 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5832 | || strcmp (name, "__mips16_ret_df") == 0); | |
5833 | } | |
5834 | ||
5835 | ||
a4b8ebc8 AC |
5836 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5837 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5838 | |
5839 | static int | |
5840 | mips_stab_reg_to_regnum (int num) | |
5841 | { | |
a4b8ebc8 | 5842 | int regnum; |
2f38ef89 | 5843 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5844 | regnum = num; |
2f38ef89 | 5845 | else if (num >= 38 && num < 70) |
56cea623 | 5846 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5847 | else if (num == 70) |
56cea623 | 5848 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5849 | else if (num == 71) |
56cea623 | 5850 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5851 | else |
a4b8ebc8 AC |
5852 | /* This will hopefully (eventually) provoke a warning. Should |
5853 | we be calling complaint() here? */ | |
5854 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5855 | return NUM_REGS + regnum; | |
88c72b7d AC |
5856 | } |
5857 | ||
2f38ef89 | 5858 | |
a4b8ebc8 AC |
5859 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5860 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5861 | |
5862 | static int | |
2f38ef89 | 5863 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5864 | { |
a4b8ebc8 | 5865 | int regnum; |
2f38ef89 | 5866 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5867 | regnum = num; |
2f38ef89 | 5868 | else if (num >= 32 && num < 64) |
56cea623 | 5869 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5870 | else if (num == 64) |
56cea623 | 5871 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5872 | else if (num == 65) |
56cea623 | 5873 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5874 | else |
a4b8ebc8 AC |
5875 | /* This will hopefully (eventually) provoke a warning. Should we |
5876 | be calling complaint() here? */ | |
5877 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5878 | return NUM_REGS + regnum; | |
5879 | } | |
5880 | ||
5881 | static int | |
5882 | mips_register_sim_regno (int regnum) | |
5883 | { | |
5884 | /* Only makes sense to supply raw registers. */ | |
5885 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5886 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5887 | decide if it is valid. Should instead define a standard sim/gdb | |
5888 | register numbering scheme. */ | |
5889 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5890 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5891 | return regnum; | |
5892 | else | |
6d82d43b | 5893 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5894 | } |
5895 | ||
2f38ef89 | 5896 | |
fc0c74b1 AC |
5897 | /* Convert an integer into an address. By first converting the value |
5898 | into a pointer and then extracting it signed, the address is | |
5899 | guarenteed to be correctly sign extended. */ | |
5900 | ||
5901 | static CORE_ADDR | |
5902 | mips_integer_to_address (struct type *type, void *buf) | |
5903 | { | |
5904 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5905 | LONGEST val = unpack_long (type, buf); | |
5906 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5907 | return extract_signed_integer (tmp, | |
5908 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5909 | } | |
5910 | ||
caaa3122 DJ |
5911 | static void |
5912 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5913 | { | |
5914 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5915 | const char *name = bfd_get_section_name (abfd, sect); | |
5916 | ||
5917 | if (*abip != MIPS_ABI_UNKNOWN) | |
5918 | return; | |
5919 | ||
5920 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5921 | return; | |
5922 | ||
5923 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5924 | *abip = MIPS_ABI_O32; | |
5925 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5926 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5927 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5928 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5929 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5930 | *abip = MIPS_ABI_O64; | |
5931 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5932 | *abip = MIPS_ABI_EABI32; | |
5933 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5934 | *abip = MIPS_ABI_EABI64; | |
5935 | else | |
5936 | warning ("unsupported ABI %s.", name + 8); | |
5937 | } | |
5938 | ||
2e4ebe70 DJ |
5939 | static enum mips_abi |
5940 | global_mips_abi (void) | |
5941 | { | |
5942 | int i; | |
5943 | ||
5944 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5945 | if (mips_abi_strings[i] == mips_abi_string) | |
5946 | return (enum mips_abi) i; | |
5947 | ||
6d82d43b | 5948 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5949 | } |
5950 | ||
c2d11a7d | 5951 | static struct gdbarch * |
6d82d43b | 5952 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5953 | { |
c2d11a7d JM |
5954 | struct gdbarch *gdbarch; |
5955 | struct gdbarch_tdep *tdep; | |
5956 | int elf_flags; | |
2e4ebe70 | 5957 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5958 | int num_regs; |
8d5838b5 | 5959 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5960 | |
ec03c1ac AC |
5961 | /* First of all, extract the elf_flags, if available. */ |
5962 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5963 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5964 | else if (arches != NULL) |
5965 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5966 | else |
5967 | elf_flags = 0; | |
5968 | if (gdbarch_debug) | |
5969 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5970 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5971 | |
102182a9 | 5972 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5973 | switch ((elf_flags & EF_MIPS_ABI)) |
5974 | { | |
5975 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5976 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5977 | break; |
5978 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5979 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5980 | break; |
5981 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5982 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5983 | break; |
5984 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5985 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5986 | break; |
5987 | default: | |
acdb74a0 | 5988 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5989 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5990 | else |
ec03c1ac | 5991 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5992 | break; |
5993 | } | |
acdb74a0 | 5994 | |
caaa3122 | 5995 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5996 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5997 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5998 | |
dc305454 | 5999 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
6000 | MIPS architecture (if there is one). */ |
6001 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
6002 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 6003 | |
32a6503c | 6004 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 6005 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
6006 | && info.bfd_arch_info != NULL |
6007 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6008 | { | |
6009 | switch (info.bfd_arch_info->mach) | |
6010 | { | |
6011 | case bfd_mach_mips3900: | |
ec03c1ac | 6012 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
6013 | break; |
6014 | case bfd_mach_mips4100: | |
6015 | case bfd_mach_mips5000: | |
ec03c1ac | 6016 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 6017 | break; |
1d06468c EZ |
6018 | case bfd_mach_mips8000: |
6019 | case bfd_mach_mips10000: | |
32a6503c KB |
6020 | /* On Irix, ELF64 executables use the N64 ABI. The |
6021 | pseudo-sections which describe the ABI aren't present | |
6022 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
6023 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
6024 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 6025 | found_abi = MIPS_ABI_N64; |
28d169de | 6026 | else |
ec03c1ac | 6027 | found_abi = MIPS_ABI_N32; |
1d06468c | 6028 | break; |
bf64bfd6 AC |
6029 | } |
6030 | } | |
2e4ebe70 | 6031 | |
ec03c1ac AC |
6032 | if (gdbarch_debug) |
6033 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
6034 | found_abi); | |
6035 | ||
6036 | /* What has the user specified from the command line? */ | |
6037 | wanted_abi = global_mips_abi (); | |
6038 | if (gdbarch_debug) | |
6039 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
6040 | wanted_abi); | |
2e4ebe70 DJ |
6041 | |
6042 | /* Now that we have found what the ABI for this binary would be, | |
6043 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
6044 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
6045 | mips_abi = wanted_abi; | |
ec03c1ac AC |
6046 | else if (found_abi != MIPS_ABI_UNKNOWN) |
6047 | mips_abi = found_abi; | |
6048 | else | |
6049 | mips_abi = MIPS_ABI_O32; | |
6050 | if (gdbarch_debug) | |
6051 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
6052 | mips_abi); | |
2e4ebe70 | 6053 | |
ec03c1ac | 6054 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 6055 | if (gdbarch_debug) |
ec03c1ac AC |
6056 | fprintf_unfiltered (gdb_stdlog, |
6057 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
6058 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 6059 | |
8d5838b5 AC |
6060 | /* Determine the MIPS FPU type. */ |
6061 | if (!mips_fpu_type_auto) | |
6062 | fpu_type = mips_fpu_type; | |
6063 | else if (info.bfd_arch_info != NULL | |
6064 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6065 | switch (info.bfd_arch_info->mach) | |
6066 | { | |
6067 | case bfd_mach_mips3900: | |
6068 | case bfd_mach_mips4100: | |
6069 | case bfd_mach_mips4111: | |
a9d61c86 | 6070 | case bfd_mach_mips4120: |
8d5838b5 AC |
6071 | fpu_type = MIPS_FPU_NONE; |
6072 | break; | |
6073 | case bfd_mach_mips4650: | |
6074 | fpu_type = MIPS_FPU_SINGLE; | |
6075 | break; | |
6076 | default: | |
6077 | fpu_type = MIPS_FPU_DOUBLE; | |
6078 | break; | |
6079 | } | |
6080 | else if (arches != NULL) | |
6081 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
6082 | else | |
6083 | fpu_type = MIPS_FPU_DOUBLE; | |
6084 | if (gdbarch_debug) | |
6085 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6086 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 6087 | |
c2d11a7d JM |
6088 | /* try to find a pre-existing architecture */ |
6089 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
6090 | arches != NULL; | |
6091 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6092 | { | |
6093 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 6094 | using. */ |
9103eae0 | 6095 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 6096 | continue; |
9103eae0 | 6097 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 6098 | continue; |
719ec221 AC |
6099 | /* Need to be pedantic about which register virtual size is |
6100 | used. */ | |
6101 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
6102 | != mips64_transfers_32bit_regs_p) | |
6103 | continue; | |
8d5838b5 AC |
6104 | /* Be pedantic about which FPU is selected. */ |
6105 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
6106 | continue; | |
4be87837 | 6107 | return arches->gdbarch; |
c2d11a7d JM |
6108 | } |
6109 | ||
102182a9 | 6110 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
6111 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
6112 | gdbarch = gdbarch_alloc (&info, tdep); | |
6113 | tdep->elf_flags = elf_flags; | |
719ec221 | 6114 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
6115 | tdep->found_abi = found_abi; |
6116 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 6117 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 6118 | |
102182a9 | 6119 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6120 | set_gdbarch_short_bit (gdbarch, 16); |
6121 | set_gdbarch_int_bit (gdbarch, 32); | |
6122 | set_gdbarch_float_bit (gdbarch, 32); | |
6123 | set_gdbarch_double_bit (gdbarch, 64); | |
6124 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6125 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6126 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6127 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6128 | |
6d82d43b | 6129 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6130 | mips_elf_make_msymbol_special); |
6131 | ||
16e109ca | 6132 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 6133 | { |
16e109ca | 6134 | const char **reg_names; |
56cea623 AC |
6135 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
6136 | struct mips_regnum); | |
56cea623 AC |
6137 | if (info.osabi == GDB_OSABI_IRIX) |
6138 | { | |
6139 | regnum->fp0 = 32; | |
6140 | regnum->pc = 64; | |
6141 | regnum->cause = 65; | |
6142 | regnum->badvaddr = 66; | |
6143 | regnum->hi = 67; | |
6144 | regnum->lo = 68; | |
6145 | regnum->fp_control_status = 69; | |
6146 | regnum->fp_implementation_revision = 70; | |
6147 | num_regs = 71; | |
16e109ca | 6148 | reg_names = mips_irix_reg_names; |
56cea623 AC |
6149 | } |
6150 | else | |
6151 | { | |
6152 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6153 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6154 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6155 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6156 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6157 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6158 | regnum->fp_control_status = 70; | |
6159 | regnum->fp_implementation_revision = 71; | |
6160 | num_regs = 90; | |
16e109ca AC |
6161 | if (info.bfd_arch_info != NULL |
6162 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6163 | reg_names = mips_tx39_reg_names; | |
6164 | else | |
6165 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
6166 | } |
6167 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
6168 | replaced by read_pc? */ | |
f10683bb MH |
6169 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
6170 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
6171 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6172 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6173 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
6174 | set_gdbarch_register_name (gdbarch, mips_register_name); |
6175 | tdep->mips_processor_reg_names = reg_names; | |
6176 | tdep->regnum = regnum; | |
56cea623 | 6177 | } |
fe29b929 | 6178 | |
0dadbba0 | 6179 | switch (mips_abi) |
c2d11a7d | 6180 | { |
0dadbba0 | 6181 | case MIPS_ABI_O32: |
25ab4790 | 6182 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6183 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
acdb74a0 | 6184 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 6185 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6186 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6187 | set_gdbarch_long_bit (gdbarch, 32); |
6188 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6189 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6190 | break; | |
0dadbba0 | 6191 | case MIPS_ABI_O64: |
25ab4790 | 6192 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
6d82d43b AC |
6193 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6194 | mips_o64_store_return_value); | |
6195 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6196 | mips_o64_extract_return_value); | |
acdb74a0 | 6197 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
56cea623 | 6198 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6199 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6200 | set_gdbarch_long_bit (gdbarch, 32); |
6201 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6202 | set_gdbarch_long_long_bit (gdbarch, 64); | |
b5622e8d | 6203 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
c2d11a7d | 6204 | break; |
0dadbba0 | 6205 | case MIPS_ABI_EABI32: |
25ab4790 | 6206 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
6207 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6208 | mips_eabi_store_return_value); | |
6209 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6210 | mips_eabi_extract_return_value); | |
acdb74a0 | 6211 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6212 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6213 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6214 | set_gdbarch_long_bit (gdbarch, 32); |
6215 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6216 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
6217 | set_gdbarch_deprecated_reg_struct_has_addr |
6218 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 6219 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 6220 | break; |
0dadbba0 | 6221 | case MIPS_ABI_EABI64: |
25ab4790 | 6222 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
6d82d43b AC |
6223 | set_gdbarch_deprecated_store_return_value (gdbarch, |
6224 | mips_eabi_store_return_value); | |
6225 | set_gdbarch_deprecated_extract_return_value (gdbarch, | |
6226 | mips_eabi_extract_return_value); | |
acdb74a0 | 6227 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6228 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6229 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6230 | set_gdbarch_long_bit (gdbarch, 64); |
6231 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6232 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2110b94f MK |
6233 | set_gdbarch_deprecated_reg_struct_has_addr |
6234 | (gdbarch, mips_eabi_reg_struct_has_addr); | |
b5622e8d | 6235 | set_gdbarch_deprecated_use_struct_convention (gdbarch, mips_eabi_use_struct_convention); |
c2d11a7d | 6236 | break; |
0dadbba0 | 6237 | case MIPS_ABI_N32: |
25ab4790 | 6238 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6239 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
acdb74a0 | 6240 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6241 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6242 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6243 | set_gdbarch_long_bit (gdbarch, 32); |
6244 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6245 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
6246 | set_gdbarch_long_double_bit (gdbarch, 128); |
6247 | set_gdbarch_long_double_format (gdbarch, | |
6248 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
6249 | break; |
6250 | case MIPS_ABI_N64: | |
25ab4790 | 6251 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6252 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
28d169de | 6253 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
56cea623 | 6254 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6255 | tdep->default_mask_address_p = 0; |
6256 | set_gdbarch_long_bit (gdbarch, 64); | |
6257 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6258 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
6259 | set_gdbarch_long_double_bit (gdbarch, 128); |
6260 | set_gdbarch_long_double_format (gdbarch, | |
6261 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 6262 | break; |
c2d11a7d | 6263 | default: |
6d82d43b | 6264 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
6265 | } |
6266 | ||
a5ea2558 AC |
6267 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6268 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6269 | comment: | |
6270 | ||
6271 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6272 | flag in object files because to do so would make it impossible to | |
102182a9 | 6273 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6274 | unnecessarily restrictive. |
361d1df0 | 6275 | |
a5ea2558 AC |
6276 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6277 | but to set this flag before gcc is built with such multilibs will | |
6278 | break too many systems.'' | |
6279 | ||
6280 | But even more unhelpfully, the default linker output target for | |
6281 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6282 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6283 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6284 | this flag to detect 32-bit mode would do the wrong thing given |
6285 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6286 | as 32-bit programs by default. */ |
a5ea2558 | 6287 | |
6c997a34 | 6288 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6289 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 6290 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 6291 | |
102182a9 MS |
6292 | /* Add/remove bits from an address. The MIPS needs be careful to |
6293 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6294 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6295 | ||
58dfe9ff AC |
6296 | /* Unwind the frame. */ |
6297 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 6298 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 6299 | |
102182a9 | 6300 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6301 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6302 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6303 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6304 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
6305 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6306 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
6307 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6308 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6309 | |
c2d11a7d JM |
6310 | /* MIPS version of CALL_DUMMY */ |
6311 | ||
9710e734 AC |
6312 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6313 | replaced by a command, and all targets will default to on stack | |
6314 | (regardless of the stack's execute status). */ | |
6315 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6316 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6317 | |
87783b8b AC |
6318 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6319 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6320 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6321 | ||
f7b9e9fc AC |
6322 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6323 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6324 | |
6325 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6326 | |
fc0c74b1 AC |
6327 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6328 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6329 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6330 | |
a4b8ebc8 | 6331 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6332 | |
e11c53d2 | 6333 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6334 | |
e5ab0dce AC |
6335 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
6336 | ||
3a3bc038 AC |
6337 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
6338 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
6339 | need to all be folded into the target vector. Since they are | |
6340 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
6341 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
6342 | is sitting on? */ | |
6343 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6344 | ||
757a7cc6 MS |
6345 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); |
6346 | ||
6de918a6 DJ |
6347 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
6348 | to support MIPS16. This is a bad thing. Make sure not to do it | |
6349 | if we have an OS ABI that actually supports shared libraries, since | |
6350 | shared library support is more important. If we have an OS someday | |
6351 | that supports both shared libraries and MIPS16, we'll have to find | |
6352 | a better place for these. */ | |
6353 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
6354 | { | |
6355 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
6356 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
6357 | } | |
6358 | ||
6359 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
6360 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 6361 | |
5792a79b | 6362 | /* Unwind the frame. */ |
eec63939 | 6363 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
5792a79b | 6364 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
45c9dd44 AC |
6365 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
6366 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 6367 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
5792a79b | 6368 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); |
45c9dd44 AC |
6369 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6370 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6371 | |
4b9b3959 AC |
6372 | return gdbarch; |
6373 | } | |
6374 | ||
2e4ebe70 | 6375 | static void |
6d82d43b | 6376 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6377 | { |
6378 | struct gdbarch_info info; | |
6379 | ||
6380 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6381 | mips_gdbarch_init will take care of the rest. */ | |
6382 | gdbarch_info_init (&info); | |
6383 | gdbarch_update_p (info); | |
6384 | } | |
6385 | ||
ad188201 KB |
6386 | /* Print out which MIPS ABI is in use. */ |
6387 | ||
6388 | static void | |
6389 | show_mips_abi (char *ignore_args, int from_tty) | |
6390 | { | |
6391 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
6392 | printf_filtered |
6393 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
6394 | else |
6395 | { | |
6396 | enum mips_abi global_abi = global_mips_abi (); | |
6397 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
6398 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
6399 | ||
6400 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
6401 | printf_filtered |
6402 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
6403 | actual_abi_str); | |
ad188201 | 6404 | else if (global_abi == actual_abi) |
6d82d43b AC |
6405 | printf_filtered |
6406 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6407 | actual_abi_str); | |
ad188201 KB |
6408 | else |
6409 | { | |
6410 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
6411 | printf_filtered |
6412 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6413 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
6414 | } |
6415 | } | |
6416 | } | |
6417 | ||
4b9b3959 AC |
6418 | static void |
6419 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
6420 | { | |
6421 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
6422 | if (tdep != NULL) | |
c2d11a7d | 6423 | { |
acdb74a0 AC |
6424 | int ef_mips_arch; |
6425 | int ef_mips_32bitmode; | |
6426 | /* determine the ISA */ | |
6427 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
6428 | { | |
6429 | case E_MIPS_ARCH_1: | |
6430 | ef_mips_arch = 1; | |
6431 | break; | |
6432 | case E_MIPS_ARCH_2: | |
6433 | ef_mips_arch = 2; | |
6434 | break; | |
6435 | case E_MIPS_ARCH_3: | |
6436 | ef_mips_arch = 3; | |
6437 | break; | |
6438 | case E_MIPS_ARCH_4: | |
93d56215 | 6439 | ef_mips_arch = 4; |
acdb74a0 AC |
6440 | break; |
6441 | default: | |
93d56215 | 6442 | ef_mips_arch = 0; |
acdb74a0 AC |
6443 | break; |
6444 | } | |
6445 | /* determine the size of a pointer */ | |
6446 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
6447 | fprintf_unfiltered (file, |
6448 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6449 | tdep->elf_flags); |
4b9b3959 | 6450 | fprintf_unfiltered (file, |
acdb74a0 AC |
6451 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6452 | ef_mips_32bitmode); | |
6453 | fprintf_unfiltered (file, | |
6454 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6455 | ef_mips_arch); | |
6456 | fprintf_unfiltered (file, | |
6457 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6458 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6459 | fprintf_unfiltered (file, |
6460 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6461 | mips_mask_address_p (tdep), |
4014092b | 6462 | tdep->default_mask_address_p); |
c2d11a7d | 6463 | } |
4b9b3959 AC |
6464 | fprintf_unfiltered (file, |
6465 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6466 | MIPS_DEFAULT_FPU_TYPE, | |
6467 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6468 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6469 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6470 | : "???")); | |
6d82d43b | 6471 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
6472 | fprintf_unfiltered (file, |
6473 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
6474 | MIPS_FPU_TYPE, | |
6475 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6476 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6477 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6478 | : "???")); | |
4b9b3959 | 6479 | fprintf_unfiltered (file, |
480d3dd2 | 6480 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 6481 | mips_stack_argsize (current_gdbarch)); |
6d82d43b | 6482 | fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); |
2475bac3 AC |
6483 | fprintf_unfiltered (file, |
6484 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 6485 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
6486 | fprintf_unfiltered (file, |
6487 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
6488 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
6489 | fprintf_unfiltered (file, |
6490 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
6491 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
6492 | fprintf_unfiltered (file, | |
6493 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
6494 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
6495 | fprintf_unfiltered (file, |
6496 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
6497 | FIRST_EMBED_REGNUM); | |
2475bac3 | 6498 | fprintf_unfiltered (file, |
a53c66de AC |
6499 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
6500 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
6501 | fprintf_unfiltered (file, |
6502 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
6503 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
6504 | fprintf_unfiltered (file, | |
6505 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
6506 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
6507 | fprintf_unfiltered (file, |
6508 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
6509 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
6510 | #ifdef MACHINE_CPROC_FP_OFFSET |
6511 | fprintf_unfiltered (file, | |
6512 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
6513 | MACHINE_CPROC_FP_OFFSET); | |
6514 | #endif | |
6515 | #ifdef MACHINE_CPROC_PC_OFFSET | |
6516 | fprintf_unfiltered (file, | |
6517 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
6518 | MACHINE_CPROC_PC_OFFSET); | |
6519 | #endif | |
6520 | #ifdef MACHINE_CPROC_SP_OFFSET | |
6521 | fprintf_unfiltered (file, | |
6522 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
6523 | MACHINE_CPROC_SP_OFFSET); | |
6524 | #endif | |
2475bac3 AC |
6525 | fprintf_unfiltered (file, |
6526 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
6527 | MIPS16_INSTLEN); | |
6d82d43b | 6528 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
6529 | fprintf_unfiltered (file, |
6530 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
6531 | fprintf_unfiltered (file, | |
6d82d43b | 6532 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); |
2475bac3 | 6533 | fprintf_unfiltered (file, |
acdb74a0 AC |
6534 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
6535 | MIPS_LAST_ARG_REGNUM, | |
6536 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 | 6537 | fprintf_unfiltered (file, |
6d82d43b | 6538 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 6539 | fprintf_unfiltered (file, |
1b13c4f6 | 6540 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 6541 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 6542 | fprintf_unfiltered (file, |
6d82d43b | 6543 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
6544 | fprintf_unfiltered (file, |
6545 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
6546 | fprintf_unfiltered (file, | |
6547 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
6548 | fprintf_unfiltered (file, | |
6549 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
6550 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
6551 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
6552 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
6553 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
6554 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
6555 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
6556 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
6557 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
6558 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
6559 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
6560 | fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); | |
2475bac3 AC |
6561 | #ifdef SAVED_BYTES |
6562 | fprintf_unfiltered (file, | |
6d82d43b | 6563 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
6564 | #endif |
6565 | #ifdef SAVED_FP | |
6d82d43b | 6566 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
6567 | #endif |
6568 | #ifdef SAVED_PC | |
6d82d43b | 6569 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
6570 | #endif |
6571 | fprintf_unfiltered (file, | |
6572 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
6573 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
6574 | fprintf_unfiltered (file, | |
6575 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
2475bac3 AC |
6576 | fprintf_unfiltered (file, |
6577 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
6578 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
6579 | fprintf_unfiltered (file, | |
6580 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
6581 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
6582 | fprintf_unfiltered (file, | |
b0ed3589 AC |
6583 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
6584 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
6585 | fprintf_unfiltered (file, |
6586 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
6587 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
6588 | #ifdef STACK_END_ADDR | |
6589 | fprintf_unfiltered (file, | |
6590 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
6591 | STACK_END_ADDR); | |
6592 | #endif | |
6593 | fprintf_unfiltered (file, | |
6594 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
6595 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
6596 | fprintf_unfiltered (file, | |
6597 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
6598 | STEP_SKIPS_DELAY_P); | |
6599 | fprintf_unfiltered (file, | |
6600 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
6601 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
6d82d43b | 6602 | fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); |
2475bac3 AC |
6603 | fprintf_unfiltered (file, |
6604 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
6605 | fprintf_unfiltered (file, | |
6606 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
6607 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
6608 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
6609 | fprintf_unfiltered (file, |
6610 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
6611 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
2475bac3 AC |
6612 | #ifdef TRACE_CLEAR |
6613 | fprintf_unfiltered (file, | |
6614 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
6615 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
6616 | #endif | |
6617 | #ifdef TRACE_FLAVOR | |
6618 | fprintf_unfiltered (file, | |
6d82d43b | 6619 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
6620 | #endif |
6621 | #ifdef TRACE_FLAVOR_SIZE | |
6622 | fprintf_unfiltered (file, | |
6623 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
6624 | TRACE_FLAVOR_SIZE); | |
6625 | #endif | |
6626 | #ifdef TRACE_SET | |
6627 | fprintf_unfiltered (file, | |
6628 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 6629 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 6630 | #endif |
2475bac3 AC |
6631 | #ifdef UNUSED_REGNUM |
6632 | fprintf_unfiltered (file, | |
6d82d43b | 6633 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 6634 | #endif |
6d82d43b | 6635 | fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); |
2475bac3 AC |
6636 | fprintf_unfiltered (file, |
6637 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6638 | (long) VM_MIN_ADDRESS); | |
2475bac3 | 6639 | fprintf_unfiltered (file, |
6d82d43b | 6640 | "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); |
2475bac3 | 6641 | fprintf_unfiltered (file, |
6d82d43b | 6642 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); |
c2d11a7d JM |
6643 | } |
6644 | ||
6d82d43b | 6645 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6646 | |
c906108c | 6647 | void |
acdb74a0 | 6648 | _initialize_mips_tdep (void) |
c906108c SS |
6649 | { |
6650 | static struct cmd_list_element *mipsfpulist = NULL; | |
6651 | struct cmd_list_element *c; | |
6652 | ||
6d82d43b | 6653 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6654 | if (MIPS_ABI_LAST + 1 |
6655 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6656 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6657 | ||
4b9b3959 | 6658 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6659 | |
8d5f9dcb DJ |
6660 | mips_pdr_data = register_objfile_data (); |
6661 | ||
a5ea2558 AC |
6662 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6663 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6664 | "Various MIPS specific commands.", | |
6665 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6666 | ||
6667 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6668 | "Various MIPS specific commands.", | |
6669 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6670 | ||
6671 | /* Allow the user to override the saved register size. */ | |
cb1a6d5f AC |
6672 | deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", |
6673 | class_obscure, | |
6674 | size_enums, | |
6675 | &mips_abi_regsize_string, "\ | |
a5ea2558 AC |
6676 | Set size of general purpose registers saved on the stack.\n\ |
6677 | This option can be set to one of:\n\ | |
6678 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6679 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6680 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6681 | saved GP register size from information contained in the executable.\n\ | |
6d82d43b | 6682 | (default: auto)", &setmipscmdlist), &showmipscmdlist); |
a5ea2558 | 6683 | |
d929b26f | 6684 | /* Allow the user to override the argument stack size. */ |
cb1a6d5f AC |
6685 | deprecated_add_show_from_set |
6686 | (add_set_enum_cmd ("stack-arg-size", | |
6687 | class_obscure, | |
6688 | size_enums, | |
6689 | &mips_stack_argsize_string, "\ | |
d929b26f AC |
6690 | Set the amount of stack space reserved for each argument.\n\ |
6691 | This option can be set to one of:\n\ | |
6692 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6693 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6694 | auto - Allow GDB to determine the correct setting from the current\n\ | |
cb1a6d5f AC |
6695 | target and executable (default)", &setmipscmdlist), |
6696 | &showmipscmdlist); | |
d929b26f | 6697 | |
2e4ebe70 DJ |
6698 | /* Allow the user to override the ABI. */ |
6699 | c = add_set_enum_cmd | |
6700 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6701 | "Set the ABI used by this program.\n" | |
6702 | "This option can be set to one of:\n" | |
6703 | " auto - the default ABI associated with the current binary\n" | |
6704 | " o32\n" | |
6d82d43b | 6705 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6706 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6707 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6708 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6709 | |
c906108c SS |
6710 | /* Let the user turn off floating point and set the fence post for |
6711 | heuristic_proc_start. */ | |
6712 | ||
6713 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6714 | "Set use of MIPS floating-point coprocessor.", | |
6715 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6716 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6717 | "Select single-precision MIPS floating-point coprocessor.", | |
6718 | &mipsfpulist); | |
6719 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6720 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6721 | &mipsfpulist); |
6722 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6723 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6724 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6725 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6726 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6727 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6728 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6729 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6730 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6731 | "Select MIPS floating-point coprocessor automatically.", | |
6732 | &mipsfpulist); | |
6733 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6734 | "Show current use of MIPS floating-point coprocessor target.", | |
6735 | &showlist); | |
6736 | ||
c906108c SS |
6737 | /* We really would like to have both "0" and "unlimited" work, but |
6738 | command.c doesn't deal with that. So make it a var_zinteger | |
6739 | because the user can always use "999999" or some such for unlimited. */ | |
6740 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
6d82d43b | 6741 | (char *) &heuristic_fence_post, "\ |
c906108c SS |
6742 | Set the distance searched for the start of a function.\n\ |
6743 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
6744 | program for the start of a function. This command sets the distance of the\n\ | |
6d82d43b | 6745 | search. The only need to set it is when debugging a stripped executable.", &setlist); |
c906108c SS |
6746 | /* We need to throw away the frame cache when we set this, since it |
6747 | might change our ability to get backtraces. */ | |
9f60d481 | 6748 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
cb1a6d5f | 6749 | deprecated_add_show_from_set (c, &showlist); |
c906108c SS |
6750 | |
6751 | /* Allow the user to control whether the upper bits of 64-bit | |
6752 | addresses should be zeroed. */ | |
e9e68a56 | 6753 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
6754 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
6755 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
6756 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
6757 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 6758 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 6759 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6760 | |
6761 | /* Allow the user to control the size of 32 bit registers within the | |
6762 | raw remote packet. */ | |
b3f42336 AC |
6763 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6764 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
6765 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
6766 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
6767 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6768 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6769 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
6770 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
6771 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
6772 | |
6773 | /* Debug this files internals. */ | |
cb1a6d5f AC |
6774 | deprecated_add_show_from_set |
6775 | (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
6776 | &mips_debug, "Set mips debugging.\n\ | |
6777 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
6778 | &showdebuglist); | |
c906108c | 6779 | } |