2003-09-28 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / mips-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
bf64bfd6 2
cda5a58a 3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
1e698235 4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
bf64bfd6 5
c906108c
SS
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8
c5aa993b 9 This file is part of GDB.
c906108c 10
c5aa993b
JM
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
c906108c 15
c5aa993b
JM
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
c906108c 20
c5aa993b
JM
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
c906108c
SS
25
26#include "defs.h"
27#include "gdb_string.h"
5e2e9765 28#include "gdb_assert.h"
c906108c
SS
29#include "frame.h"
30#include "inferior.h"
31#include "symtab.h"
32#include "value.h"
33#include "gdbcmd.h"
34#include "language.h"
35#include "gdbcore.h"
36#include "symfile.h"
37#include "objfiles.h"
38#include "gdbtypes.h"
39#include "target.h"
28d069e6 40#include "arch-utils.h"
4e052eda 41#include "regcache.h"
70f80edf 42#include "osabi.h"
d1973055 43#include "mips-tdep.h"
fe898f56 44#include "block.h"
a4b8ebc8 45#include "reggroups.h"
c906108c 46#include "opcode/mips.h"
c2d11a7d
JM
47#include "elf/mips.h"
48#include "elf-bfd.h"
2475bac3 49#include "symcat.h"
a4b8ebc8 50#include "sim-regno.h"
a89aa300 51#include "dis-asm.h"
c906108c 52
e0f7ec59 53static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
5bbcb741 54static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
e0f7ec59 55
dd824b04
DJ
56/* A useful bit in the CP0 status register (PS_REGNUM). */
57/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58#define ST0_FR (1 << 26)
59
b0069a17
AC
60/* The sizes of floating point registers. */
61
62enum
63{
64 MIPS_FPU_SINGLE_REGSIZE = 4,
65 MIPS_FPU_DOUBLE_REGSIZE = 8
66};
67
0dadbba0 68
2e4ebe70
DJ
69static const char *mips_abi_string;
70
71static const char *mips_abi_strings[] = {
72 "auto",
73 "n32",
74 "o32",
28d169de 75 "n64",
2e4ebe70
DJ
76 "o64",
77 "eabi32",
78 "eabi64",
79 NULL
80};
81
cce74817 82struct frame_extra_info
c5aa993b
JM
83 {
84 mips_extra_func_info_t proc_desc;
85 int num_args;
86 };
cce74817 87
d929b26f
AC
88/* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
90 them. */
91
53904c9e
AC
92static const char size_auto[] = "auto";
93static const char size_32[] = "32";
94static const char size_64[] = "64";
d929b26f 95
53904c9e 96static const char *size_enums[] = {
d929b26f
AC
97 size_auto,
98 size_32,
99 size_64,
a5ea2558
AC
100 0
101};
102
7a292a7a
SS
103/* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
c906108c
SS
106
107enum mips_fpu_type
c5aa993b
JM
108 {
109 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE /* No floating point. */
112 };
c906108c
SS
113
114#ifndef MIPS_DEFAULT_FPU_TYPE
115#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
116#endif
117static int mips_fpu_type_auto = 1;
118static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
7a292a7a 119
9ace0497 120static int mips_debug = 0;
7a292a7a 121
c2d11a7d
JM
122/* MIPS specific per-architecture information */
123struct gdbarch_tdep
124 {
125 /* from the elf header */
126 int elf_flags;
70f80edf 127
c2d11a7d 128 /* mips options */
0dadbba0 129 enum mips_abi mips_abi;
2e4ebe70 130 enum mips_abi found_abi;
c2d11a7d
JM
131 enum mips_fpu_type mips_fpu_type;
132 int mips_last_arg_regnum;
133 int mips_last_fp_arg_regnum;
a5ea2558 134 int mips_default_saved_regsize;
c2d11a7d 135 int mips_fp_register_double;
d929b26f 136 int mips_default_stack_argsize;
5213ab06 137 int gdb_target_is_mips64;
4014092b 138 int default_mask_address_p;
c2d11a7d
JM
139 };
140
0dadbba0 141#define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
216a600b 142 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
c2d11a7d 143
c2d11a7d 144#define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
c2d11a7d 145
c2d11a7d 146#define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
c2d11a7d 147
c2d11a7d 148#define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
c2d11a7d 149
d929b26f
AC
150/* Return the currently configured (or set) saved register size. */
151
a5ea2558 152#define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
c2d11a7d 153
53904c9e 154static const char *mips_saved_regsize_string = size_auto;
d929b26f
AC
155
156#define MIPS_SAVED_REGSIZE (mips_saved_regsize())
157
95404a3e
AC
158/* MIPS16 function addresses are odd (bit 0 is set). Here are some
159 functions to test, set, or clear bit 0 of addresses. */
160
161static CORE_ADDR
162is_mips16_addr (CORE_ADDR addr)
163{
164 return ((addr) & 1);
165}
166
167static CORE_ADDR
168make_mips16_addr (CORE_ADDR addr)
169{
170 return ((addr) | 1);
171}
172
173static CORE_ADDR
174unmake_mips16_addr (CORE_ADDR addr)
175{
176 return ((addr) & ~1);
177}
178
22540ece
AC
179/* Return the contents of register REGNUM as a signed integer. */
180
181static LONGEST
182read_signed_register (int regnum)
183{
184 void *buf = alloca (REGISTER_RAW_SIZE (regnum));
185 deprecated_read_register_gen (regnum, buf);
186 return (extract_signed_integer (buf, REGISTER_RAW_SIZE (regnum)));
187}
188
189static LONGEST
190read_signed_register_pid (int regnum, ptid_t ptid)
191{
192 ptid_t save_ptid;
193 LONGEST retval;
194
195 if (ptid_equal (ptid, inferior_ptid))
196 return read_signed_register (regnum);
197
198 save_ptid = inferior_ptid;
199
200 inferior_ptid = ptid;
201
202 retval = read_signed_register (regnum);
203
204 inferior_ptid = save_ptid;
205
206 return retval;
207}
208
d1973055
KB
209/* Return the MIPS ABI associated with GDBARCH. */
210enum mips_abi
211mips_abi (struct gdbarch *gdbarch)
212{
213 return gdbarch_tdep (gdbarch)->mips_abi;
214}
215
d929b26f 216static unsigned int
acdb74a0 217mips_saved_regsize (void)
d929b26f
AC
218{
219 if (mips_saved_regsize_string == size_auto)
220 return MIPS_DEFAULT_SAVED_REGSIZE;
221 else if (mips_saved_regsize_string == size_64)
222 return 8;
223 else /* if (mips_saved_regsize_string == size_32) */
224 return 4;
225}
226
71b8ef93 227/* Functions for setting and testing a bit in a minimal symbol that
5a89d8aa
MS
228 marks it as 16-bit function. The MSB of the minimal symbol's
229 "info" field is used for this purpose. This field is already
230 being used to store the symbol size, so the assumption is
231 that the symbol size cannot exceed 2^31.
232
233 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
234 i.e. refers to a 16-bit function, and sets a "special" bit in a
235 minimal symbol to mark it as a 16-bit function
236
237 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
238 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
239 the "info" field with the "special" bit masked out */
240
5a89d8aa
MS
241static void
242mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
243{
244 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
245 {
246 MSYMBOL_INFO (msym) = (char *)
247 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
248 SYMBOL_VALUE_ADDRESS (msym) |= 1;
249 }
250}
251
71b8ef93
MS
252static int
253msymbol_is_special (struct minimal_symbol *msym)
254{
255 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
256}
257
258static long
259msymbol_size (struct minimal_symbol *msym)
260{
261 return ((long) MSYMBOL_INFO (msym) & 0x7fffffff);
262}
263
88658117
AC
264/* XFER a value from the big/little/left end of the register.
265 Depending on the size of the value it might occupy the entire
266 register or just part of it. Make an allowance for this, aligning
267 things accordingly. */
268
269static void
270mips_xfer_register (struct regcache *regcache, int reg_num, int length,
271 enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
272 int buf_offset)
273{
d9d9c31f 274 bfd_byte reg[MAX_REGISTER_SIZE];
88658117 275 int reg_offset = 0;
a4b8ebc8 276 gdb_assert (reg_num >= NUM_REGS);
cb1d2653
AC
277 /* Need to transfer the left or right part of the register, based on
278 the targets byte order. */
88658117
AC
279 switch (endian)
280 {
281 case BFD_ENDIAN_BIG:
282 reg_offset = REGISTER_RAW_SIZE (reg_num) - length;
283 break;
284 case BFD_ENDIAN_LITTLE:
285 reg_offset = 0;
286 break;
287 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
288 reg_offset = 0;
289 break;
290 default:
291 internal_error (__FILE__, __LINE__, "bad switch");
292 }
293 if (mips_debug)
cb1d2653
AC
294 fprintf_unfiltered (gdb_stderr,
295 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
296 reg_num, reg_offset, buf_offset, length);
88658117
AC
297 if (mips_debug && out != NULL)
298 {
299 int i;
cb1d2653 300 fprintf_unfiltered (gdb_stdlog, "out ");
88658117 301 for (i = 0; i < length; i++)
cb1d2653 302 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
88658117
AC
303 }
304 if (in != NULL)
a4b8ebc8 305 regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
88658117 306 if (out != NULL)
a4b8ebc8 307 regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
88658117
AC
308 if (mips_debug && in != NULL)
309 {
310 int i;
cb1d2653 311 fprintf_unfiltered (gdb_stdlog, "in ");
88658117 312 for (i = 0; i < length; i++)
cb1d2653 313 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
88658117
AC
314 }
315 if (mips_debug)
316 fprintf_unfiltered (gdb_stdlog, "\n");
317}
318
dd824b04
DJ
319/* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
320 compatiblity mode. A return value of 1 means that we have
321 physical 64-bit registers, but should treat them as 32-bit registers. */
322
323static int
324mips2_fp_compat (void)
325{
326 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
327 meaningful. */
328 if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
329 return 0;
330
331#if 0
332 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
333 in all the places we deal with FP registers. PR gdb/413. */
334 /* Otherwise check the FR bit in the status register - it controls
335 the FP compatiblity mode. If it is clear we are in compatibility
336 mode. */
337 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
338 return 1;
339#endif
361d1df0 340
dd824b04
DJ
341 return 0;
342}
343
c2d11a7d
JM
344/* Indicate that the ABI makes use of double-precision registers
345 provided by the FPU (rather than combining pairs of registers to
346 form double-precision values). Do not use "TARGET_IS_MIPS64" to
347 determine if the ABI is using double-precision registers. See also
348 MIPS_FPU_TYPE. */
c2d11a7d 349#define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
c2d11a7d 350
d929b26f
AC
351/* The amount of space reserved on the stack for registers. This is
352 different to MIPS_SAVED_REGSIZE as it determines the alignment of
353 data allocated after the registers have run out. */
354
0dadbba0 355#define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
d929b26f
AC
356
357#define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
358
53904c9e 359static const char *mips_stack_argsize_string = size_auto;
d929b26f
AC
360
361static unsigned int
362mips_stack_argsize (void)
363{
364 if (mips_stack_argsize_string == size_auto)
365 return MIPS_DEFAULT_STACK_ARGSIZE;
366 else if (mips_stack_argsize_string == size_64)
367 return 8;
368 else /* if (mips_stack_argsize_string == size_32) */
369 return 4;
370}
371
5213ab06 372#define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
c2d11a7d 373
92e1c15c 374#define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
92e1c15c 375
7a292a7a 376#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
c906108c 377
570b8f7c
AC
378static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
379 struct frame_info *, int);
c906108c 380
a14ed312 381static CORE_ADDR heuristic_proc_start (CORE_ADDR);
c906108c 382
a14ed312 383static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
c906108c 384
5a89d8aa 385static int mips_set_processor_type (char *);
c906108c 386
a14ed312 387static void mips_show_processor_type_command (char *, int);
c906108c 388
a14ed312 389static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
c906108c 390
570b8f7c
AC
391static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
392 struct frame_info *next_frame,
393 int cur_frame);
c906108c 394
a14ed312
KB
395static CORE_ADDR after_prologue (CORE_ADDR pc,
396 mips_extra_func_info_t proc_desc);
c906108c 397
67b2c998
DJ
398static struct type *mips_float_register_type (void);
399static struct type *mips_double_register_type (void);
400
c906108c
SS
401/* This value is the model of MIPS in use. It is derived from the value
402 of the PrID register. */
403
404char *mips_processor_type;
405
406char *tmp_mips_processor_type;
407
acdb74a0
AC
408/* The list of available "set mips " and "show mips " commands */
409
410static struct cmd_list_element *setmipscmdlist = NULL;
411static struct cmd_list_element *showmipscmdlist = NULL;
412
c906108c
SS
413/* A set of original names, to be used when restoring back to generic
414 registers from a specific set. */
5e2e9765 415static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
c906108c 416
5e2e9765
KB
417/* Integer registers 0 thru 31 are handled explicitly by
418 mips_register_name(). Processor specific registers 32 and above
419 are listed in the sets of register names assigned to
420 mips_processor_reg_names. */
421static char **mips_processor_reg_names = mips_generic_reg_names;
cce74817 422
5e2e9765 423/* Return the name of the register corresponding to REGNO. */
5a89d8aa 424static const char *
5e2e9765 425mips_register_name (int regno)
cce74817 426{
5e2e9765
KB
427 /* GPR names for all ABIs other than n32/n64. */
428 static char *mips_gpr_names[] = {
429 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
430 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
431 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
432 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
433 };
434
435 /* GPR names for n32 and n64 ABIs. */
436 static char *mips_n32_n64_gpr_names[] = {
437 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
438 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
439 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
440 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
441 };
442
443 enum mips_abi abi = mips_abi (current_gdbarch);
444
a4b8ebc8
AC
445 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
446 don't make the raw register names visible. */
447 int rawnum = regno % NUM_REGS;
448 if (regno < NUM_REGS)
449 return "";
450
5e2e9765
KB
451 /* The MIPS integer registers are always mapped from 0 to 31. The
452 names of the registers (which reflects the conventions regarding
453 register use) vary depending on the ABI. */
a4b8ebc8 454 if (0 <= rawnum && rawnum < 32)
5e2e9765
KB
455 {
456 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
a4b8ebc8 457 return mips_n32_n64_gpr_names[rawnum];
5e2e9765 458 else
a4b8ebc8 459 return mips_gpr_names[rawnum];
5e2e9765 460 }
a4b8ebc8
AC
461 else if (32 <= rawnum && rawnum < NUM_REGS)
462 return mips_processor_reg_names[rawnum - 32];
5e2e9765
KB
463 else
464 internal_error (__FILE__, __LINE__,
a4b8ebc8 465 "mips_register_name: bad register number %d", rawnum);
cce74817 466}
5e2e9765 467
9846de1b 468/* *INDENT-OFF* */
c906108c
SS
469/* Names of IDT R3041 registers. */
470
471char *mips_r3041_reg_names[] = {
c906108c
SS
472 "sr", "lo", "hi", "bad", "cause","pc",
473 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
474 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
475 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
476 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
a094c6fb 477 "fsr", "fir", "",/*"fp"*/ "",
c906108c
SS
478 "", "", "bus", "ccfg", "", "", "", "",
479 "", "", "port", "cmp", "", "", "epc", "prid",
480};
481
482/* Names of IDT R3051 registers. */
483
484char *mips_r3051_reg_names[] = {
c906108c
SS
485 "sr", "lo", "hi", "bad", "cause","pc",
486 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
487 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
488 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
489 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
a094c6fb 490 "fsr", "fir", ""/*"fp"*/, "",
c906108c
SS
491 "inx", "rand", "elo", "", "ctxt", "", "", "",
492 "", "", "ehi", "", "", "", "epc", "prid",
493};
494
495/* Names of IDT R3081 registers. */
496
497char *mips_r3081_reg_names[] = {
c906108c
SS
498 "sr", "lo", "hi", "bad", "cause","pc",
499 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
500 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
501 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
502 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
a094c6fb 503 "fsr", "fir", ""/*"fp"*/, "",
c906108c
SS
504 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
505 "", "", "ehi", "", "", "", "epc", "prid",
506};
507
508/* Names of LSI 33k registers. */
509
510char *mips_lsi33k_reg_names[] = {
c906108c
SS
511 "epc", "hi", "lo", "sr", "cause","badvaddr",
512 "dcic", "bpc", "bda", "", "", "", "", "",
513 "", "", "", "", "", "", "", "",
514 "", "", "", "", "", "", "", "",
515 "", "", "", "", "", "", "", "",
516 "", "", "", "",
517 "", "", "", "", "", "", "", "",
518 "", "", "", "", "", "", "", "",
519};
520
521struct {
522 char *name;
523 char **regnames;
524} mips_processor_type_table[] = {
525 { "generic", mips_generic_reg_names },
526 { "r3041", mips_r3041_reg_names },
527 { "r3051", mips_r3051_reg_names },
528 { "r3071", mips_r3081_reg_names },
529 { "r3081", mips_r3081_reg_names },
530 { "lsi33k", mips_lsi33k_reg_names },
531 { NULL, NULL }
532};
9846de1b 533/* *INDENT-ON* */
c906108c 534
a4b8ebc8 535/* Return the groups that a MIPS register can be categorised into. */
c5aa993b 536
a4b8ebc8
AC
537static int
538mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
539 struct reggroup *reggroup)
540{
541 int vector_p;
542 int float_p;
543 int raw_p;
544 int rawnum = regnum % NUM_REGS;
545 int pseudo = regnum / NUM_REGS;
546 if (reggroup == all_reggroup)
547 return pseudo;
548 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
549 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
550 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
551 (gdbarch), as not all architectures are multi-arch. */
552 raw_p = rawnum < NUM_REGS;
553 if (REGISTER_NAME (regnum) == NULL
554 || REGISTER_NAME (regnum)[0] == '\0')
555 return 0;
556 if (reggroup == float_reggroup)
557 return float_p && pseudo;
558 if (reggroup == vector_reggroup)
559 return vector_p && pseudo;
560 if (reggroup == general_reggroup)
561 return (!vector_p && !float_p) && pseudo;
562 /* Save the pseudo registers. Need to make certain that any code
563 extracting register values from a saved register cache also uses
564 pseudo registers. */
565 if (reggroup == save_reggroup)
566 return raw_p && pseudo;
567 /* Restore the same pseudo register. */
568 if (reggroup == restore_reggroup)
569 return raw_p && pseudo;
570 return 0;
571}
572
573/* Map the symbol table registers which live in the range [1 *
574 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
575 registers. */
c5aa993b 576
a4b8ebc8
AC
577static void
578mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
579 int cookednum, void *buf)
580{
581 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
582 return regcache_raw_read (regcache, cookednum % NUM_REGS, buf);
583}
584
585static void
586mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
587 int cookednum, const void *buf)
588{
589 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
590 return regcache_raw_write (regcache, cookednum % NUM_REGS, buf);
591}
c5aa993b 592
c906108c 593/* Table to translate MIPS16 register field to actual register number. */
c5aa993b
JM
594static int mips16_to_32_reg[8] =
595{16, 17, 2, 3, 4, 5, 6, 7};
c906108c
SS
596
597/* Heuristic_proc_start may hunt through the text section for a long
598 time across a 2400 baud serial line. Allows the user to limit this
599 search. */
600
601static unsigned int heuristic_fence_post = 0;
602
c5aa993b
JM
603#define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
604#define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
c906108c
SS
605#define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
606#define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
607#define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
608#define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
609#define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
610#define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
611#define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
612#define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
6c0d6680
DJ
613/* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
614 this will corrupt pdr.iline. Fortunately we don't use it. */
c906108c
SS
615#define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
616#define _PROC_MAGIC_ 0x0F0F0F0F
617#define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
618#define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
619
620struct linked_proc_info
c5aa993b
JM
621 {
622 struct mips_extra_func_info info;
623 struct linked_proc_info *next;
624 }
625 *linked_proc_desc_table = NULL;
c906108c 626
cce74817 627void
acdb74a0 628mips_print_extra_frame_info (struct frame_info *fi)
cce74817
JM
629{
630 if (fi
da50a4b7
AC
631 && get_frame_extra_info (fi)
632 && get_frame_extra_info (fi)->proc_desc
633 && get_frame_extra_info (fi)->proc_desc->pdr.framereg < NUM_REGS)
d4f3574e 634 printf_filtered (" frame pointer is at %s+%s\n",
da50a4b7
AC
635 REGISTER_NAME (get_frame_extra_info (fi)->proc_desc->pdr.framereg),
636 paddr_d (get_frame_extra_info (fi)->proc_desc->pdr.frameoffset));
cce74817 637}
c906108c 638
46cd78fb
AC
639/* Number of bytes of storage in the actual machine representation for
640 register N. NOTE: This indirectly defines the register size
a4b8ebc8 641 transfered by the GDB protocol. */
43e526b9
JM
642
643static int mips64_transfers_32bit_regs_p = 0;
644
f7ab6ec6 645static int
a4b8ebc8 646mips_register_raw_size (int regnum)
43e526b9 647{
a4b8ebc8
AC
648 gdb_assert (regnum >= 0);
649 if (regnum < NUM_REGS)
650 {
651 /* For compatibility with old code, implemnt the broken register raw
652 size map for the raw registers.
653
654 NOTE: cagney/2003-06-15: This is so bogus. The register's
655 raw size is changing according to the ABI
656 (FP_REGISTER_DOUBLE). Also, GDB's protocol is defined by a
62700349 657 combination of REGISTER_RAW_SIZE and DEPRECATED_REGISTER_BYTE. */
a4b8ebc8
AC
658 if (mips64_transfers_32bit_regs_p)
659 return REGISTER_VIRTUAL_SIZE (regnum);
660 else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32
661 && FP_REGISTER_DOUBLE)
662 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
663 registers. */
664 return 8;
665 else
666 return MIPS_REGSIZE;
667 }
668 else if (regnum < 2 * NUM_REGS)
669 {
670 /* For the moment map [NUM_REGS .. 2*NUM_REGS) onto the same raw
671 registers, but always return the virtual size. */
672 int rawnum = regnum % NUM_REGS;
5bbcb741 673 return TYPE_LENGTH (gdbarch_register_type (current_gdbarch, rawnum));
a4b8ebc8 674 }
43e526b9 675 else
a4b8ebc8
AC
676 internal_error (__FILE__, __LINE__, "Register %d out of range", regnum);
677}
678
679/* Register offset in a buffer for each register.
680
681 FIXME: cagney/2003-06-15: This is so bogus. Instead REGISTER_TYPE
682 should strictly return the layout of the buffer. Unfortunatly
683 remote.c and the MIPS have come to rely on a custom layout that
684 doesn't 1:1 map onto the register type. */
685
686static int
687mips_register_byte (int regnum)
688{
689 gdb_assert (regnum >= 0);
690 if (regnum < NUM_REGS)
691 /* Pick up the relevant per-tm file register byte method. */
692 return MIPS_REGISTER_BYTE (regnum);
693 else if (regnum < 2 * NUM_REGS)
694 {
695 int reg;
696 int byte;
697 /* Start with the end of the raw register buffer - assum that
698 MIPS_REGISTER_BYTE (NUM_REGS) returns that end. */
699 byte = MIPS_REGISTER_BYTE (NUM_REGS);
700 /* Add space for all the proceeding registers based on their
701 real size. */
702 for (reg = NUM_REGS; reg < regnum; reg++)
5bbcb741
JB
703 byte += TYPE_LENGTH (gdbarch_register_type (current_gdbarch,
704 (reg % NUM_REGS)));
a4b8ebc8
AC
705 return byte;
706 }
707 else
708 internal_error (__FILE__, __LINE__, "Register %d out of range", regnum);
43e526b9
JM
709}
710
46cd78fb
AC
711/* Convert between RAW and VIRTUAL registers. The RAW register size
712 defines the remote-gdb packet. */
713
d05285fa 714static int
acdb74a0 715mips_register_convertible (int reg_nr)
43e526b9
JM
716{
717 if (mips64_transfers_32bit_regs_p)
718 return 0;
719 else
720 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
721}
722
d05285fa 723static void
acdb74a0
AC
724mips_register_convert_to_virtual (int n, struct type *virtual_type,
725 char *raw_buf, char *virt_buf)
43e526b9 726{
d7449b42 727 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
43e526b9
JM
728 memcpy (virt_buf,
729 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
730 TYPE_LENGTH (virtual_type));
731 else
732 memcpy (virt_buf,
733 raw_buf,
734 TYPE_LENGTH (virtual_type));
735}
736
d05285fa 737static void
acdb74a0 738mips_register_convert_to_raw (struct type *virtual_type, int n,
781a750d 739 const char *virt_buf, char *raw_buf)
43e526b9
JM
740{
741 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
d7449b42 742 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
43e526b9
JM
743 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
744 virt_buf,
745 TYPE_LENGTH (virtual_type));
746 else
747 memcpy (raw_buf,
748 virt_buf,
749 TYPE_LENGTH (virtual_type));
750}
751
ff2e87ac
AC
752static int
753mips_convert_register_p (int regnum, struct type *type)
754{
755 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
756 && REGISTER_RAW_SIZE (regnum) == 4
757 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
758 && TYPE_CODE(type) == TYPE_CODE_FLT
759 && TYPE_LENGTH(type) == 8);
760}
761
42c466d7 762static void
ff2e87ac
AC
763mips_register_to_value (struct frame_info *frame, int regnum,
764 struct type *type, void *to)
102182a9 765{
ff2e87ac
AC
766 frame_read_register (frame, regnum + 0, (char *) to + 4);
767 frame_read_register (frame, regnum + 1, (char *) to + 0);
102182a9
MS
768}
769
42c466d7 770static void
ff2e87ac
AC
771mips_value_to_register (struct frame_info *frame, int regnum,
772 struct type *type, const void *from)
102182a9 773{
ff2e87ac
AC
774 put_frame_register (frame, regnum + 0, (const char *) from + 4);
775 put_frame_register (frame, regnum + 1, (const char *) from + 0);
102182a9
MS
776}
777
a4b8ebc8
AC
778/* Return the GDB type object for the "standard" data type of data in
779 register REG. */
78fde5f8
KB
780
781static struct type *
a4b8ebc8
AC
782mips_register_type (struct gdbarch *gdbarch, int regnum)
783{
784 /* For moment, map [NUM_REGS .. 2*NUM_REGS) onto the same raw
785 registers. Even return the same type. */
786 int rawnum = regnum % NUM_REGS;
787 gdb_assert (rawnum >= 0 && rawnum < NUM_REGS);
788#ifdef MIPS_REGISTER_TYPE
789 return MIPS_REGISTER_TYPE (rawnum);
790#else
791 if (FP0_REGNUM <= rawnum && rawnum < FP0_REGNUM + 32)
a6425924
KB
792 {
793 /* Floating point registers... */
794 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
795 return builtin_type_ieee_double_big;
796 else
797 return builtin_type_ieee_double_little;
798 }
a4b8ebc8 799 else if (rawnum == PS_REGNUM /* CR */)
78fde5f8 800 return builtin_type_uint32;
a4b8ebc8 801 else if (FCRCS_REGNUM <= rawnum && rawnum <= LAST_EMBED_REGNUM)
78fde5f8
KB
802 return builtin_type_uint32;
803 else
804 {
a6425924
KB
805 /* Everything else...
806 Return type appropriate for width of register. */
807 if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64))
808 return builtin_type_uint64;
78fde5f8 809 else
a6425924 810 return builtin_type_uint32;
78fde5f8 811 }
a4b8ebc8 812#endif
78fde5f8
KB
813}
814
bcb0cc15
MS
815/* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
816
817static CORE_ADDR
818mips_read_sp (void)
819{
e227b13c 820 return read_signed_register (SP_REGNUM);
bcb0cc15
MS
821}
822
c906108c 823/* Should the upper word of 64-bit addresses be zeroed? */
7f19b9a2 824enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
4014092b
AC
825
826static int
827mips_mask_address_p (void)
828{
829 switch (mask_address_var)
830 {
7f19b9a2 831 case AUTO_BOOLEAN_TRUE:
4014092b 832 return 1;
7f19b9a2 833 case AUTO_BOOLEAN_FALSE:
4014092b
AC
834 return 0;
835 break;
7f19b9a2 836 case AUTO_BOOLEAN_AUTO:
92e1c15c 837 return MIPS_DEFAULT_MASK_ADDRESS_P;
4014092b 838 default:
8e65ff28
AC
839 internal_error (__FILE__, __LINE__,
840 "mips_mask_address_p: bad switch");
4014092b 841 return -1;
361d1df0 842 }
4014092b
AC
843}
844
845static void
e9e68a56 846show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
4014092b
AC
847{
848 switch (mask_address_var)
849 {
7f19b9a2 850 case AUTO_BOOLEAN_TRUE:
4014092b
AC
851 printf_filtered ("The 32 bit mips address mask is enabled\n");
852 break;
7f19b9a2 853 case AUTO_BOOLEAN_FALSE:
4014092b
AC
854 printf_filtered ("The 32 bit mips address mask is disabled\n");
855 break;
7f19b9a2 856 case AUTO_BOOLEAN_AUTO:
4014092b
AC
857 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
858 mips_mask_address_p () ? "enabled" : "disabled");
859 break;
860 default:
8e65ff28
AC
861 internal_error (__FILE__, __LINE__,
862 "show_mask_address: bad switch");
4014092b 863 break;
361d1df0 864 }
4014092b 865}
c906108c
SS
866
867/* Should call_function allocate stack space for a struct return? */
cb811fe7 868
f7ab6ec6 869static int
cb811fe7 870mips_eabi_use_struct_convention (int gcc_p, struct type *type)
c906108c 871{
cb811fe7
MS
872 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
873}
874
f7ab6ec6 875static int
cb811fe7
MS
876mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
877{
b78bcb18 878 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
cb811fe7
MS
879}
880
8b389c40
MS
881/* Should call_function pass struct by reference?
882 For each architecture, structs are passed either by
883 value or by reference, depending on their size. */
884
885static int
886mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
887{
888 enum type_code typecode = TYPE_CODE (check_typedef (type));
889 int len = TYPE_LENGTH (check_typedef (type));
890
891 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
892 return (len > MIPS_SAVED_REGSIZE);
893
894 return 0;
895}
896
897static int
898mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
899{
900 return 0; /* Assumption: N32/N64 never passes struct by ref. */
901}
902
f7ab6ec6 903static int
8b389c40
MS
904mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
905{
906 return 0; /* Assumption: O32/O64 never passes struct by ref. */
907}
908
c906108c
SS
909/* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
910
911static int
912pc_is_mips16 (bfd_vma memaddr)
913{
914 struct minimal_symbol *sym;
915
916 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
95404a3e 917 if (is_mips16_addr (memaddr))
c906108c
SS
918 return 1;
919
920 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
921 the high bit of the info field. Use this to decide if the function is
922 MIPS16 or normal MIPS. */
923 sym = lookup_minimal_symbol_by_pc (memaddr);
924 if (sym)
71b8ef93 925 return msymbol_is_special (sym);
c906108c
SS
926 else
927 return 0;
928}
929
6c997a34
AC
930/* MIPS believes that the PC has a sign extended value. Perhaphs the
931 all registers should be sign extended for simplicity? */
932
933static CORE_ADDR
39f77062 934mips_read_pc (ptid_t ptid)
6c997a34 935{
39f77062 936 return read_signed_register_pid (PC_REGNUM, ptid);
6c997a34 937}
c906108c
SS
938
939/* This returns the PC of the first inst after the prologue. If we can't
940 find the prologue, then return 0. */
941
942static CORE_ADDR
acdb74a0
AC
943after_prologue (CORE_ADDR pc,
944 mips_extra_func_info_t proc_desc)
c906108c
SS
945{
946 struct symtab_and_line sal;
947 CORE_ADDR func_addr, func_end;
948
479412cd
DJ
949 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
950 to read the stack pointer from the current machine state, because
951 the current machine state has nothing to do with the information
952 we need from the proc_desc; and the process may or may not exist
953 right now. */
c906108c 954 if (!proc_desc)
479412cd 955 proc_desc = find_proc_desc (pc, NULL, 0);
c906108c
SS
956
957 if (proc_desc)
958 {
959 /* If function is frameless, then we need to do it the hard way. I
c5aa993b 960 strongly suspect that frameless always means prologueless... */
c906108c
SS
961 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
962 && PROC_FRAME_OFFSET (proc_desc) == 0)
963 return 0;
964 }
965
966 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
967 return 0; /* Unknown */
968
969 sal = find_pc_line (func_addr, 0);
970
971 if (sal.end < func_end)
972 return sal.end;
973
974 /* The line after the prologue is after the end of the function. In this
975 case, tell the caller to find the prologue the hard way. */
976
977 return 0;
978}
979
980/* Decode a MIPS32 instruction that saves a register in the stack, and
981 set the appropriate bit in the general register mask or float register mask
982 to indicate which register is saved. This is a helper function
983 for mips_find_saved_regs. */
984
985static void
acdb74a0
AC
986mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
987 unsigned long *float_mask)
c906108c
SS
988{
989 int reg;
990
991 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
992 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
993 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
994 {
995 /* It might be possible to use the instruction to
c5aa993b
JM
996 find the offset, rather than the code below which
997 is based on things being in a certain order in the
998 frame, but figuring out what the instruction's offset
999 is relative to might be a little tricky. */
c906108c
SS
1000 reg = (inst & 0x001f0000) >> 16;
1001 *gen_mask |= (1 << reg);
1002 }
1003 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
c5aa993b
JM
1004 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
1005 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
c906108c
SS
1006
1007 {
1008 reg = ((inst & 0x001f0000) >> 16);
1009 *float_mask |= (1 << reg);
1010 }
1011}
1012
1013/* Decode a MIPS16 instruction that saves a register in the stack, and
1014 set the appropriate bit in the general register or float register mask
1015 to indicate which register is saved. This is a helper function
1016 for mips_find_saved_regs. */
1017
1018static void
acdb74a0 1019mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
c906108c 1020{
c5aa993b 1021 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
c906108c
SS
1022 {
1023 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1024 *gen_mask |= (1 << reg);
1025 }
c5aa993b 1026 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
c906108c
SS
1027 {
1028 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1029 *gen_mask |= (1 << reg);
1030 }
c5aa993b 1031 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
c906108c
SS
1032 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1033 *gen_mask |= (1 << RA_REGNUM);
1034}
1035
1036
1037/* Fetch and return instruction from the specified location. If the PC
1038 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1039
1040static t_inst
acdb74a0 1041mips_fetch_instruction (CORE_ADDR addr)
c906108c
SS
1042{
1043 char buf[MIPS_INSTLEN];
1044 int instlen;
1045 int status;
1046
1047 if (pc_is_mips16 (addr))
1048 {
1049 instlen = MIPS16_INSTLEN;
95404a3e 1050 addr = unmake_mips16_addr (addr);
c906108c
SS
1051 }
1052 else
c5aa993b 1053 instlen = MIPS_INSTLEN;
c906108c
SS
1054 status = read_memory_nobpt (addr, buf, instlen);
1055 if (status)
1056 memory_error (status, addr);
1057 return extract_unsigned_integer (buf, instlen);
1058}
1059
1060
1061/* These the fields of 32 bit mips instructions */
e135b889
DJ
1062#define mips32_op(x) (x >> 26)
1063#define itype_op(x) (x >> 26)
1064#define itype_rs(x) ((x >> 21) & 0x1f)
c906108c 1065#define itype_rt(x) ((x >> 16) & 0x1f)
e135b889 1066#define itype_immediate(x) (x & 0xffff)
c906108c 1067
e135b889
DJ
1068#define jtype_op(x) (x >> 26)
1069#define jtype_target(x) (x & 0x03ffffff)
c906108c 1070
e135b889
DJ
1071#define rtype_op(x) (x >> 26)
1072#define rtype_rs(x) ((x >> 21) & 0x1f)
1073#define rtype_rt(x) ((x >> 16) & 0x1f)
1074#define rtype_rd(x) ((x >> 11) & 0x1f)
1075#define rtype_shamt(x) ((x >> 6) & 0x1f)
1076#define rtype_funct(x) (x & 0x3f)
c906108c
SS
1077
1078static CORE_ADDR
c5aa993b
JM
1079mips32_relative_offset (unsigned long inst)
1080{
1081 long x;
1082 x = itype_immediate (inst);
1083 if (x & 0x8000) /* sign bit set */
c906108c 1084 {
c5aa993b 1085 x |= 0xffff0000; /* sign extension */
c906108c 1086 }
c5aa993b
JM
1087 x = x << 2;
1088 return x;
c906108c
SS
1089}
1090
1091/* Determine whate to set a single step breakpoint while considering
1092 branch prediction */
5a89d8aa 1093static CORE_ADDR
c5aa993b
JM
1094mips32_next_pc (CORE_ADDR pc)
1095{
1096 unsigned long inst;
1097 int op;
1098 inst = mips_fetch_instruction (pc);
e135b889 1099 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
c5aa993b 1100 {
e135b889
DJ
1101 if (itype_op (inst) >> 2 == 5)
1102 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
c5aa993b 1103 {
e135b889 1104 op = (itype_op (inst) & 0x03);
c906108c
SS
1105 switch (op)
1106 {
e135b889
DJ
1107 case 0: /* BEQL */
1108 goto equal_branch;
1109 case 1: /* BNEL */
1110 goto neq_branch;
1111 case 2: /* BLEZL */
1112 goto less_branch;
1113 case 3: /* BGTZ */
1114 goto greater_branch;
c5aa993b
JM
1115 default:
1116 pc += 4;
c906108c
SS
1117 }
1118 }
e135b889
DJ
1119 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1120 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1121 {
1122 int tf = itype_rt (inst) & 0x01;
1123 int cnum = itype_rt (inst) >> 2;
1124 int fcrcs = read_signed_register (FCRCS_REGNUM);
1125 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1126
1127 if (((cond >> cnum) & 0x01) == tf)
1128 pc += mips32_relative_offset (inst) + 4;
1129 else
1130 pc += 8;
1131 }
c5aa993b
JM
1132 else
1133 pc += 4; /* Not a branch, next instruction is easy */
c906108c
SS
1134 }
1135 else
c5aa993b
JM
1136 { /* This gets way messy */
1137
c906108c 1138 /* Further subdivide into SPECIAL, REGIMM and other */
e135b889 1139 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
c906108c 1140 {
c5aa993b
JM
1141 case 0: /* SPECIAL */
1142 op = rtype_funct (inst);
1143 switch (op)
1144 {
1145 case 8: /* JR */
1146 case 9: /* JALR */
6c997a34
AC
1147 /* Set PC to that address */
1148 pc = read_signed_register (rtype_rs (inst));
c5aa993b
JM
1149 break;
1150 default:
1151 pc += 4;
1152 }
1153
e135b889 1154 break; /* end SPECIAL */
c5aa993b 1155 case 1: /* REGIMM */
c906108c 1156 {
e135b889
DJ
1157 op = itype_rt (inst); /* branch condition */
1158 switch (op)
c906108c 1159 {
c5aa993b 1160 case 0: /* BLTZ */
e135b889
DJ
1161 case 2: /* BLTZL */
1162 case 16: /* BLTZAL */
c5aa993b 1163 case 18: /* BLTZALL */
c906108c 1164 less_branch:
6c997a34 1165 if (read_signed_register (itype_rs (inst)) < 0)
c5aa993b
JM
1166 pc += mips32_relative_offset (inst) + 4;
1167 else
1168 pc += 8; /* after the delay slot */
1169 break;
e135b889 1170 case 1: /* BGEZ */
c5aa993b
JM
1171 case 3: /* BGEZL */
1172 case 17: /* BGEZAL */
1173 case 19: /* BGEZALL */
c906108c 1174 greater_equal_branch:
6c997a34 1175 if (read_signed_register (itype_rs (inst)) >= 0)
c5aa993b
JM
1176 pc += mips32_relative_offset (inst) + 4;
1177 else
1178 pc += 8; /* after the delay slot */
1179 break;
e135b889 1180 /* All of the other instructions in the REGIMM category */
c5aa993b
JM
1181 default:
1182 pc += 4;
c906108c
SS
1183 }
1184 }
e135b889 1185 break; /* end REGIMM */
c5aa993b
JM
1186 case 2: /* J */
1187 case 3: /* JAL */
1188 {
1189 unsigned long reg;
1190 reg = jtype_target (inst) << 2;
e135b889 1191 /* Upper four bits get never changed... */
c5aa993b 1192 pc = reg + ((pc + 4) & 0xf0000000);
c906108c 1193 }
c5aa993b
JM
1194 break;
1195 /* FIXME case JALX : */
1196 {
1197 unsigned long reg;
1198 reg = jtype_target (inst) << 2;
1199 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
c906108c
SS
1200 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1201 }
c5aa993b 1202 break; /* The new PC will be alternate mode */
e135b889 1203 case 4: /* BEQ, BEQL */
c5aa993b 1204 equal_branch:
6c997a34
AC
1205 if (read_signed_register (itype_rs (inst)) ==
1206 read_signed_register (itype_rt (inst)))
c5aa993b
JM
1207 pc += mips32_relative_offset (inst) + 4;
1208 else
1209 pc += 8;
1210 break;
e135b889 1211 case 5: /* BNE, BNEL */
c5aa993b 1212 neq_branch:
6c997a34 1213 if (read_signed_register (itype_rs (inst)) !=
e135b889 1214 read_signed_register (itype_rt (inst)))
c5aa993b
JM
1215 pc += mips32_relative_offset (inst) + 4;
1216 else
1217 pc += 8;
1218 break;
e135b889 1219 case 6: /* BLEZ, BLEZL */
c906108c 1220 less_zero_branch:
6c997a34 1221 if (read_signed_register (itype_rs (inst) <= 0))
c5aa993b
JM
1222 pc += mips32_relative_offset (inst) + 4;
1223 else
1224 pc += 8;
1225 break;
1226 case 7:
e135b889
DJ
1227 default:
1228 greater_branch: /* BGTZ, BGTZL */
6c997a34 1229 if (read_signed_register (itype_rs (inst) > 0))
c5aa993b
JM
1230 pc += mips32_relative_offset (inst) + 4;
1231 else
1232 pc += 8;
1233 break;
c5aa993b
JM
1234 } /* switch */
1235 } /* else */
1236 return pc;
1237} /* mips32_next_pc */
c906108c
SS
1238
1239/* Decoding the next place to set a breakpoint is irregular for the
e26cc349 1240 mips 16 variant, but fortunately, there fewer instructions. We have to cope
c906108c
SS
1241 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1242 We dont want to set a single step instruction on the extend instruction
1243 either.
c5aa993b 1244 */
c906108c
SS
1245
1246/* Lots of mips16 instruction formats */
1247/* Predicting jumps requires itype,ritype,i8type
1248 and their extensions extItype,extritype,extI8type
c5aa993b 1249 */
c906108c
SS
1250enum mips16_inst_fmts
1251{
c5aa993b
JM
1252 itype, /* 0 immediate 5,10 */
1253 ritype, /* 1 5,3,8 */
1254 rrtype, /* 2 5,3,3,5 */
1255 rritype, /* 3 5,3,3,5 */
1256 rrrtype, /* 4 5,3,3,3,2 */
1257 rriatype, /* 5 5,3,3,1,4 */
1258 shifttype, /* 6 5,3,3,3,2 */
1259 i8type, /* 7 5,3,8 */
1260 i8movtype, /* 8 5,3,3,5 */
1261 i8mov32rtype, /* 9 5,3,5,3 */
1262 i64type, /* 10 5,3,8 */
1263 ri64type, /* 11 5,3,3,5 */
1264 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1265 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1266 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1267 extRRItype, /* 15 5,5,5,5,3,3,5 */
1268 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1269 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1270 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1271 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1272 extRi64type, /* 20 5,6,5,5,3,3,5 */
1273 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1274};
12f02c2a
AC
1275/* I am heaping all the fields of the formats into one structure and
1276 then, only the fields which are involved in instruction extension */
c906108c 1277struct upk_mips16
c5aa993b 1278 {
12f02c2a 1279 CORE_ADDR offset;
c5aa993b
JM
1280 unsigned int regx; /* Function in i8 type */
1281 unsigned int regy;
1282 };
c906108c
SS
1283
1284
12f02c2a
AC
1285/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1286 for the bits which make up the immediatate extension. */
c906108c 1287
12f02c2a
AC
1288static CORE_ADDR
1289extended_offset (unsigned int extension)
c906108c 1290{
12f02c2a 1291 CORE_ADDR value;
c5aa993b
JM
1292 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1293 value = value << 6;
1294 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1295 value = value << 5;
1296 value |= extension & 0x01f; /* extract 4:0 */
1297 return value;
c906108c
SS
1298}
1299
1300/* Only call this function if you know that this is an extendable
1301 instruction, It wont malfunction, but why make excess remote memory references?
1302 If the immediate operands get sign extended or somthing, do it after
1303 the extension is performed.
c5aa993b 1304 */
c906108c
SS
1305/* FIXME: Every one of these cases needs to worry about sign extension
1306 when the offset is to be used in relative addressing */
1307
1308
12f02c2a 1309static unsigned int
c5aa993b 1310fetch_mips_16 (CORE_ADDR pc)
c906108c 1311{
c5aa993b
JM
1312 char buf[8];
1313 pc &= 0xfffffffe; /* clear the low order bit */
1314 target_read_memory (pc, buf, 2);
1315 return extract_unsigned_integer (buf, 2);
c906108c
SS
1316}
1317
1318static void
c5aa993b 1319unpack_mips16 (CORE_ADDR pc,
12f02c2a
AC
1320 unsigned int extension,
1321 unsigned int inst,
1322 enum mips16_inst_fmts insn_format,
c5aa993b 1323 struct upk_mips16 *upk)
c906108c 1324{
12f02c2a
AC
1325 CORE_ADDR offset;
1326 int regx;
1327 int regy;
1328 switch (insn_format)
c906108c 1329 {
c5aa993b 1330 case itype:
c906108c 1331 {
12f02c2a
AC
1332 CORE_ADDR value;
1333 if (extension)
c5aa993b
JM
1334 {
1335 value = extended_offset (extension);
1336 value = value << 11; /* rom for the original value */
12f02c2a 1337 value |= inst & 0x7ff; /* eleven bits from instruction */
c906108c
SS
1338 }
1339 else
c5aa993b 1340 {
12f02c2a 1341 value = inst & 0x7ff;
c5aa993b 1342 /* FIXME : Consider sign extension */
c906108c 1343 }
12f02c2a
AC
1344 offset = value;
1345 regx = -1;
1346 regy = -1;
c906108c 1347 }
c5aa993b
JM
1348 break;
1349 case ritype:
1350 case i8type:
1351 { /* A register identifier and an offset */
c906108c
SS
1352 /* Most of the fields are the same as I type but the
1353 immediate value is of a different length */
12f02c2a
AC
1354 CORE_ADDR value;
1355 if (extension)
c906108c 1356 {
c5aa993b
JM
1357 value = extended_offset (extension);
1358 value = value << 8; /* from the original instruction */
12f02c2a
AC
1359 value |= inst & 0xff; /* eleven bits from instruction */
1360 regx = (extension >> 8) & 0x07; /* or i8 funct */
c5aa993b
JM
1361 if (value & 0x4000) /* test the sign bit , bit 26 */
1362 {
1363 value &= ~0x3fff; /* remove the sign bit */
1364 value = -value;
c906108c
SS
1365 }
1366 }
c5aa993b
JM
1367 else
1368 {
12f02c2a
AC
1369 value = inst & 0xff; /* 8 bits */
1370 regx = (inst >> 8) & 0x07; /* or i8 funct */
c5aa993b
JM
1371 /* FIXME: Do sign extension , this format needs it */
1372 if (value & 0x80) /* THIS CONFUSES ME */
1373 {
1374 value &= 0xef; /* remove the sign bit */
1375 value = -value;
1376 }
c5aa993b 1377 }
12f02c2a
AC
1378 offset = value;
1379 regy = -1;
c5aa993b 1380 break;
c906108c 1381 }
c5aa993b 1382 case jalxtype:
c906108c 1383 {
c5aa993b 1384 unsigned long value;
12f02c2a
AC
1385 unsigned int nexthalf;
1386 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
c5aa993b
JM
1387 value = value << 16;
1388 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1389 value |= nexthalf;
12f02c2a
AC
1390 offset = value;
1391 regx = -1;
1392 regy = -1;
c5aa993b 1393 break;
c906108c
SS
1394 }
1395 default:
8e65ff28
AC
1396 internal_error (__FILE__, __LINE__,
1397 "bad switch");
c906108c 1398 }
12f02c2a
AC
1399 upk->offset = offset;
1400 upk->regx = regx;
1401 upk->regy = regy;
c906108c
SS
1402}
1403
1404
c5aa993b
JM
1405static CORE_ADDR
1406add_offset_16 (CORE_ADDR pc, int offset)
c906108c 1407{
c5aa993b 1408 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
c906108c
SS
1409}
1410
12f02c2a
AC
1411static CORE_ADDR
1412extended_mips16_next_pc (CORE_ADDR pc,
1413 unsigned int extension,
1414 unsigned int insn)
c906108c 1415{
12f02c2a
AC
1416 int op = (insn >> 11);
1417 switch (op)
c906108c 1418 {
12f02c2a
AC
1419 case 2: /* Branch */
1420 {
1421 CORE_ADDR offset;
1422 struct upk_mips16 upk;
1423 unpack_mips16 (pc, extension, insn, itype, &upk);
1424 offset = upk.offset;
1425 if (offset & 0x800)
1426 {
1427 offset &= 0xeff;
1428 offset = -offset;
1429 }
1430 pc += (offset << 1) + 2;
1431 break;
1432 }
1433 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1434 {
1435 struct upk_mips16 upk;
1436 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1437 pc = add_offset_16 (pc, upk.offset);
1438 if ((insn >> 10) & 0x01) /* Exchange mode */
1439 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1440 else
1441 pc |= 0x01;
1442 break;
1443 }
1444 case 4: /* beqz */
1445 {
1446 struct upk_mips16 upk;
1447 int reg;
1448 unpack_mips16 (pc, extension, insn, ritype, &upk);
1449 reg = read_signed_register (upk.regx);
1450 if (reg == 0)
1451 pc += (upk.offset << 1) + 2;
1452 else
1453 pc += 2;
1454 break;
1455 }
1456 case 5: /* bnez */
1457 {
1458 struct upk_mips16 upk;
1459 int reg;
1460 unpack_mips16 (pc, extension, insn, ritype, &upk);
1461 reg = read_signed_register (upk.regx);
1462 if (reg != 0)
1463 pc += (upk.offset << 1) + 2;
1464 else
1465 pc += 2;
1466 break;
1467 }
1468 case 12: /* I8 Formats btez btnez */
1469 {
1470 struct upk_mips16 upk;
1471 int reg;
1472 unpack_mips16 (pc, extension, insn, i8type, &upk);
1473 /* upk.regx contains the opcode */
1474 reg = read_signed_register (24); /* Test register is 24 */
1475 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1476 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1477 /* pc = add_offset_16(pc,upk.offset) ; */
1478 pc += (upk.offset << 1) + 2;
1479 else
1480 pc += 2;
1481 break;
1482 }
1483 case 29: /* RR Formats JR, JALR, JALR-RA */
1484 {
1485 struct upk_mips16 upk;
1486 /* upk.fmt = rrtype; */
1487 op = insn & 0x1f;
1488 if (op == 0)
c5aa993b 1489 {
12f02c2a
AC
1490 int reg;
1491 upk.regx = (insn >> 8) & 0x07;
1492 upk.regy = (insn >> 5) & 0x07;
1493 switch (upk.regy)
c5aa993b 1494 {
12f02c2a
AC
1495 case 0:
1496 reg = upk.regx;
1497 break;
1498 case 1:
1499 reg = 31;
1500 break; /* Function return instruction */
1501 case 2:
1502 reg = upk.regx;
1503 break;
1504 default:
1505 reg = 31;
1506 break; /* BOGUS Guess */
c906108c 1507 }
12f02c2a 1508 pc = read_signed_register (reg);
c906108c 1509 }
12f02c2a 1510 else
c5aa993b 1511 pc += 2;
12f02c2a
AC
1512 break;
1513 }
1514 case 30:
1515 /* This is an instruction extension. Fetch the real instruction
1516 (which follows the extension) and decode things based on
1517 that. */
1518 {
1519 pc += 2;
1520 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1521 break;
1522 }
1523 default:
1524 {
1525 pc += 2;
1526 break;
1527 }
c906108c 1528 }
c5aa993b 1529 return pc;
12f02c2a 1530}
c906108c 1531
5a89d8aa 1532static CORE_ADDR
12f02c2a
AC
1533mips16_next_pc (CORE_ADDR pc)
1534{
1535 unsigned int insn = fetch_mips_16 (pc);
1536 return extended_mips16_next_pc (pc, 0, insn);
1537}
1538
1539/* The mips_next_pc function supports single_step when the remote
7e73cedf 1540 target monitor or stub is not developed enough to do a single_step.
12f02c2a
AC
1541 It works by decoding the current instruction and predicting where a
1542 branch will go. This isnt hard because all the data is available.
1543 The MIPS32 and MIPS16 variants are quite different */
c5aa993b
JM
1544CORE_ADDR
1545mips_next_pc (CORE_ADDR pc)
c906108c 1546{
c5aa993b
JM
1547 if (pc & 0x01)
1548 return mips16_next_pc (pc);
1549 else
1550 return mips32_next_pc (pc);
12f02c2a 1551}
c906108c 1552
e0f7ec59
AC
1553/* Set up the 'saved_regs' array. This is a data structure containing
1554 the addresses on the stack where each register has been saved, for
1555 each stack frame. Registers that have not been saved will have
1556 zero here. The stack pointer register is special: rather than the
1557 address where the stack register has been saved,
1558 saved_regs[SP_REGNUM] will have the actual value of the previous
1559 frame's stack register. */
c906108c 1560
d28e01f4 1561static void
acdb74a0 1562mips_find_saved_regs (struct frame_info *fci)
c906108c
SS
1563{
1564 int ireg;
c906108c
SS
1565 /* r0 bit means kernel trap */
1566 int kernel_trap;
1567 /* What registers have been saved? Bitmasks. */
1568 unsigned long gen_mask, float_mask;
1569 mips_extra_func_info_t proc_desc;
1570 t_inst inst;
e0f7ec59 1571 CORE_ADDR *saved_regs;
c906108c 1572
1b1d3794 1573 if (deprecated_get_frame_saved_regs (fci) != NULL)
e0f7ec59
AC
1574 return;
1575 saved_regs = frame_saved_regs_zalloc (fci);
c906108c
SS
1576
1577 /* If it is the frame for sigtramp, the saved registers are located
e0f7ec59
AC
1578 in a sigcontext structure somewhere on the stack. If the stack
1579 layout for sigtramp changes we might have to change these
1580 constants and the companion fixup_sigtramp in mdebugread.c */
c906108c 1581#ifndef SIGFRAME_BASE
e0f7ec59
AC
1582 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1583 above the sigtramp frame. */
c906108c
SS
1584#define SIGFRAME_BASE MIPS_REGSIZE
1585/* FIXME! Are these correct?? */
1586#define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1587#define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1588#define SIGFRAME_FPREGSAVE_OFF \
1589 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1590#endif
1591#ifndef SIGFRAME_REG_SIZE
e0f7ec59 1592 /* FIXME! Is this correct?? */
c906108c
SS
1593#define SIGFRAME_REG_SIZE MIPS_REGSIZE
1594#endif
5a203e44 1595 if ((get_frame_type (fci) == SIGTRAMP_FRAME))
c906108c
SS
1596 {
1597 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1598 {
e0f7ec59
AC
1599 CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF
1600 + ireg * SIGFRAME_REG_SIZE);
1601 set_reg_offset (saved_regs, ireg, reg_position);
c906108c
SS
1602 }
1603 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1604 {
e0f7ec59
AC
1605 CORE_ADDR reg_position = (get_frame_base (fci)
1606 + SIGFRAME_FPREGSAVE_OFF
1607 + ireg * SIGFRAME_REG_SIZE);
1608 set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position);
c906108c 1609 }
e0f7ec59
AC
1610
1611 set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF);
1612 /* SP_REGNUM, contains the value and not the address. */
1613 set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
c906108c
SS
1614 return;
1615 }
1616
da50a4b7 1617 proc_desc = get_frame_extra_info (fci)->proc_desc;
c906108c 1618 if (proc_desc == NULL)
e0f7ec59
AC
1619 /* I'm not sure how/whether this can happen. Normally when we
1620 can't find a proc_desc, we "synthesize" one using
1621 heuristic_proc_desc and set the saved_regs right away. */
c906108c
SS
1622 return;
1623
c5aa993b
JM
1624 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1625 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1626 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
c906108c 1627
e0f7ec59
AC
1628 if (/* In any frame other than the innermost or a frame interrupted
1629 by a signal, we assume that all registers have been saved.
1630 This assumes that all register saves in a function happen
1631 before the first function call. */
11c02a10
AC
1632 (get_next_frame (fci) == NULL
1633 || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME))
c906108c 1634
e0f7ec59 1635 /* In a dummy frame we know exactly where things are saved. */
c5aa993b 1636 && !PROC_DESC_IS_DUMMY (proc_desc)
c906108c 1637
e0f7ec59
AC
1638 /* Don't bother unless we are inside a function prologue.
1639 Outside the prologue, we know where everything is. */
c906108c 1640
50abf9e5 1641 && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc))
c906108c 1642
e0f7ec59
AC
1643 /* Not sure exactly what kernel_trap means, but if it means the
1644 kernel saves the registers without a prologue doing it, we
1645 better not examine the prologue to see whether registers
1646 have been saved yet. */
c5aa993b 1647 && !kernel_trap)
c906108c 1648 {
e0f7ec59
AC
1649 /* We need to figure out whether the registers that the
1650 proc_desc claims are saved have been saved yet. */
c906108c
SS
1651
1652 CORE_ADDR addr;
1653
1654 /* Bitmasks; set if we have found a save for the register. */
1655 unsigned long gen_save_found = 0;
1656 unsigned long float_save_found = 0;
1657 int instlen;
1658
1659 /* If the address is odd, assume this is MIPS16 code. */
1660 addr = PROC_LOW_ADDR (proc_desc);
1661 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1662
e0f7ec59
AC
1663 /* Scan through this function's instructions preceding the
1664 current PC, and look for those that save registers. */
50abf9e5 1665 while (addr < get_frame_pc (fci))
c906108c
SS
1666 {
1667 inst = mips_fetch_instruction (addr);
1668 if (pc_is_mips16 (addr))
1669 mips16_decode_reg_save (inst, &gen_save_found);
1670 else
1671 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1672 addr += instlen;
1673 }
1674 gen_mask = gen_save_found;
1675 float_mask = float_save_found;
1676 }
1677
e0f7ec59
AC
1678 /* Fill in the offsets for the registers which gen_mask says were
1679 saved. */
1680 {
1681 CORE_ADDR reg_position = (get_frame_base (fci)
1682 + PROC_REG_OFFSET (proc_desc));
1683 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1684 if (gen_mask & 0x80000000)
1685 {
1686 set_reg_offset (saved_regs, ireg, reg_position);
1687 reg_position -= MIPS_SAVED_REGSIZE;
1688 }
1689 }
c906108c 1690
e0f7ec59
AC
1691 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1692 order of that normally used by gcc. Therefore, we have to fetch
1693 the first instruction of the function, and if it's an entry
1694 instruction that saves $s0 or $s1, correct their saved addresses. */
c906108c
SS
1695 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1696 {
1697 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
e0f7ec59
AC
1698 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
1699 /* entry */
c906108c
SS
1700 {
1701 int reg;
1702 int sreg_count = (inst >> 6) & 3;
c5aa993b 1703
c906108c 1704 /* Check if the ra register was pushed on the stack. */
e0f7ec59
AC
1705 CORE_ADDR reg_position = (get_frame_base (fci)
1706 + PROC_REG_OFFSET (proc_desc));
c906108c 1707 if (inst & 0x20)
7a292a7a 1708 reg_position -= MIPS_SAVED_REGSIZE;
c906108c 1709
e0f7ec59
AC
1710 /* Check if the s0 and s1 registers were pushed on the
1711 stack. */
c5aa993b 1712 for (reg = 16; reg < sreg_count + 16; reg++)
c906108c 1713 {
e0f7ec59 1714 set_reg_offset (saved_regs, reg, reg_position);
7a292a7a 1715 reg_position -= MIPS_SAVED_REGSIZE;
c906108c
SS
1716 }
1717 }
1718 }
1719
e0f7ec59
AC
1720 /* Fill in the offsets for the registers which float_mask says were
1721 saved. */
1722 {
1723 CORE_ADDR reg_position = (get_frame_base (fci)
1724 + PROC_FREG_OFFSET (proc_desc));
6acdf5c7 1725
e0f7ec59
AC
1726 /* Fill in the offsets for the float registers which float_mask
1727 says were saved. */
1728 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1729 if (float_mask & 0x80000000)
1730 {
c57bb9fa
AC
1731 if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1732 {
1733 /* On a big endian 32 bit ABI, floating point registers
1734 are paired to form doubles such that the most
1735 significant part is in $f[N+1] and the least
1736 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1737 registers are also spilled as a pair and stored as a
1738 double.
1739
1740 When little-endian the least significant part is
1741 stored first leading to the memory order $f[N] and
1742 then $f[N+1].
1743
1744 Unfortunatly, when big-endian the most significant
1745 part of the double is stored first, and the least
1746 significant is stored second. This leads to the
1747 registers being ordered in memory as firt $f[N+1] and
1748 then $f[N].
1749
1750 For the big-endian case make certain that the
1751 addresses point at the correct (swapped) locations
1752 $f[N] and $f[N+1] pair (keep in mind that
1753 reg_position is decremented each time through the
1754 loop). */
1755 if ((ireg & 1))
1756 set_reg_offset (saved_regs, FP0_REGNUM + ireg,
1757 reg_position - MIPS_SAVED_REGSIZE);
1758 else
1759 set_reg_offset (saved_regs, FP0_REGNUM + ireg,
1760 reg_position + MIPS_SAVED_REGSIZE);
1761 }
1762 else
1763 set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position);
e0f7ec59
AC
1764 reg_position -= MIPS_SAVED_REGSIZE;
1765 }
c906108c 1766
e0f7ec59
AC
1767 set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]);
1768 }
d28e01f4 1769
e0f7ec59
AC
1770 /* SP_REGNUM, contains the value and not the address. */
1771 set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
d28e01f4
KB
1772}
1773
c906108c 1774static CORE_ADDR
acdb74a0 1775read_next_frame_reg (struct frame_info *fi, int regno)
c906108c 1776{
a4b8ebc8
AC
1777 /* Always a pseudo. */
1778 gdb_assert (regno >= NUM_REGS);
f796e4be 1779 if (fi == NULL)
c906108c 1780 {
a4b8ebc8
AC
1781 LONGEST val;
1782 regcache_cooked_read_signed (current_regcache, regno, &val);
1783 return val;
f796e4be 1784 }
a4b8ebc8
AC
1785 else if ((regno % NUM_REGS) == SP_REGNUM)
1786 /* The SP_REGNUM is special, its value is stored in saved_regs.
1787 In fact, it is so special that it can even only be fetched
1788 using a raw register number! Once this code as been converted
1789 to frame-unwind the problem goes away. */
1790 return frame_unwind_register_signed (fi, regno % NUM_REGS);
f796e4be 1791 else
a4b8ebc8 1792 return frame_unwind_register_signed (fi, regno);
64159455 1793
c906108c
SS
1794}
1795
1796/* mips_addr_bits_remove - remove useless address bits */
1797
875e1767 1798static CORE_ADDR
acdb74a0 1799mips_addr_bits_remove (CORE_ADDR addr)
c906108c 1800{
5213ab06
AC
1801 if (GDB_TARGET_IS_MIPS64)
1802 {
4014092b 1803 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
5213ab06
AC
1804 {
1805 /* This hack is a work-around for existing boards using
1806 PMON, the simulator, and any other 64-bit targets that
1807 doesn't have true 64-bit addressing. On these targets,
1808 the upper 32 bits of addresses are ignored by the
1809 hardware. Thus, the PC or SP are likely to have been
1810 sign extended to all 1s by instruction sequences that
1811 load 32-bit addresses. For example, a typical piece of
4014092b
AC
1812 code that loads an address is this:
1813 lui $r2, <upper 16 bits>
1814 ori $r2, <lower 16 bits>
1815 But the lui sign-extends the value such that the upper 32
1816 bits may be all 1s. The workaround is simply to mask off
1817 these bits. In the future, gcc may be changed to support
1818 true 64-bit addressing, and this masking will have to be
1819 disabled. */
5213ab06
AC
1820 addr &= (CORE_ADDR) 0xffffffff;
1821 }
1822 }
4014092b 1823 else if (mips_mask_address_p ())
5213ab06 1824 {
4014092b
AC
1825 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1826 masking off bits, instead, the actual target should be asking
1827 for the address to be converted to a valid pointer. */
5213ab06
AC
1828 /* Even when GDB is configured for some 32-bit targets
1829 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1830 so CORE_ADDR is 64 bits. So we still have to mask off
1831 useless bits from addresses. */
c5aa993b 1832 addr &= (CORE_ADDR) 0xffffffff;
c906108c 1833 }
c906108c
SS
1834 return addr;
1835}
1836
9022177c
DJ
1837/* mips_software_single_step() is called just before we want to resume
1838 the inferior, if we want to single-step it but there is no hardware
75c9abc6 1839 or kernel single-step support (MIPS on GNU/Linux for example). We find
9022177c
DJ
1840 the target of the coming instruction and breakpoint it.
1841
1842 single_step is also called just after the inferior stops. If we had
1843 set up a simulated single-step, we undo our damage. */
1844
1845void
1846mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1847{
1848 static CORE_ADDR next_pc;
1849 typedef char binsn_quantum[BREAKPOINT_MAX];
1850 static binsn_quantum break_mem;
1851 CORE_ADDR pc;
1852
1853 if (insert_breakpoints_p)
1854 {
1855 pc = read_register (PC_REGNUM);
1856 next_pc = mips_next_pc (pc);
1857
1858 target_insert_breakpoint (next_pc, break_mem);
1859 }
1860 else
1861 target_remove_breakpoint (next_pc, break_mem);
1862}
1863
97f46953 1864static CORE_ADDR
acdb74a0 1865mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
c906108c
SS
1866{
1867 CORE_ADDR pc, tmp;
1868
11c02a10 1869 pc = ((fromleaf)
6913c89a 1870 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev))
11c02a10 1871 : get_next_frame (prev)
8bedc050 1872 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
11c02a10 1873 : read_pc ());
5a89d8aa 1874 tmp = SKIP_TRAMPOLINE_CODE (pc);
97f46953 1875 return tmp ? tmp : pc;
c906108c
SS
1876}
1877
1878
f7ab6ec6 1879static CORE_ADDR
acdb74a0 1880mips_frame_saved_pc (struct frame_info *frame)
c906108c
SS
1881{
1882 CORE_ADDR saved_pc;
c906108c 1883
50abf9e5 1884 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
cedea778
AC
1885 {
1886 LONGEST tmp;
a4b8ebc8
AC
1887 /* Always unwind the cooked PC register value. */
1888 frame_unwind_signed_register (frame, NUM_REGS + PC_REGNUM, &tmp);
cedea778
AC
1889 saved_pc = tmp;
1890 }
c906108c 1891 else
a4b8ebc8
AC
1892 {
1893 mips_extra_func_info_t proc_desc
1894 = get_frame_extra_info (frame)->proc_desc;
1895 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1896 saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1897 else
1898 {
1899 /* We have to get the saved pc from the sigcontext if it is
1900 a signal handler frame. */
1901 int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM
1902 : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1903 saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg);
1904 }
1905 }
c906108c
SS
1906 return ADDR_BITS_REMOVE (saved_pc);
1907}
1908
1909static struct mips_extra_func_info temp_proc_desc;
fe29b929
KB
1910
1911/* This hack will go away once the get_prev_frame() code has been
1912 modified to set the frame's type first. That is BEFORE init extra
1913 frame info et.al. is called. This is because it will become
1914 possible to skip the init extra info call for sigtramp and dummy
1915 frames. */
1916static CORE_ADDR *temp_saved_regs;
c906108c 1917
e0f7ec59
AC
1918/* Set a register's saved stack address in temp_saved_regs. If an
1919 address has already been set for this register, do nothing; this
1920 way we will only recognize the first save of a given register in a
a4b8ebc8
AC
1921 function prologue.
1922
1923 For simplicity, save the address in both [0 .. NUM_REGS) and
1924 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1925 is used as it is only second range (the ABI instead of ISA
1926 registers) that comes into play when finding saved registers in a
1927 frame. */
c906108c
SS
1928
1929static void
e0f7ec59 1930set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset)
c906108c 1931{
e0f7ec59 1932 if (saved_regs[regno] == 0)
a4b8ebc8
AC
1933 {
1934 saved_regs[regno + 0 * NUM_REGS] = offset;
1935 saved_regs[regno + 1 * NUM_REGS] = offset;
1936 }
c906108c
SS
1937}
1938
1939
1940/* Test whether the PC points to the return instruction at the
1941 end of a function. */
1942
c5aa993b 1943static int
acdb74a0 1944mips_about_to_return (CORE_ADDR pc)
c906108c
SS
1945{
1946 if (pc_is_mips16 (pc))
1947 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1948 generates a "jr $ra"; other times it generates code to load
1949 the return address from the stack to an accessible register (such
1950 as $a3), then a "jr" using that register. This second case
1951 is almost impossible to distinguish from an indirect jump
1952 used for switch statements, so we don't even try. */
1953 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1954 else
1955 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1956}
1957
1958
1959/* This fencepost looks highly suspicious to me. Removing it also
1960 seems suspicious as it could affect remote debugging across serial
1961 lines. */
1962
1963static CORE_ADDR
acdb74a0 1964heuristic_proc_start (CORE_ADDR pc)
c906108c 1965{
c5aa993b
JM
1966 CORE_ADDR start_pc;
1967 CORE_ADDR fence;
1968 int instlen;
1969 int seen_adjsp = 0;
c906108c 1970
c5aa993b
JM
1971 pc = ADDR_BITS_REMOVE (pc);
1972 start_pc = pc;
1973 fence = start_pc - heuristic_fence_post;
1974 if (start_pc == 0)
1975 return 0;
c906108c 1976
c5aa993b
JM
1977 if (heuristic_fence_post == UINT_MAX
1978 || fence < VM_MIN_ADDRESS)
1979 fence = VM_MIN_ADDRESS;
c906108c 1980
c5aa993b 1981 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
c906108c 1982
c5aa993b
JM
1983 /* search back for previous return */
1984 for (start_pc -= instlen;; start_pc -= instlen)
1985 if (start_pc < fence)
1986 {
1987 /* It's not clear to me why we reach this point when
c0236d92 1988 stop_soon, but with this test, at least we
c5aa993b
JM
1989 don't print out warnings for every child forked (eg, on
1990 decstation). 22apr93 rich@cygnus.com. */
c0236d92 1991 if (stop_soon == NO_STOP_QUIETLY)
c906108c 1992 {
c5aa993b
JM
1993 static int blurb_printed = 0;
1994
1995 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1996 paddr_nz (pc));
1997
1998 if (!blurb_printed)
c906108c 1999 {
c5aa993b
JM
2000 /* This actually happens frequently in embedded
2001 development, when you first connect to a board
2002 and your stack pointer and pc are nowhere in
2003 particular. This message needs to give people
2004 in that situation enough information to
2005 determine that it's no big deal. */
2006 printf_filtered ("\n\
cd0fc7c3
SS
2007 GDB is unable to find the start of the function at 0x%s\n\
2008and thus can't determine the size of that function's stack frame.\n\
2009This means that GDB may be unable to access that stack frame, or\n\
2010the frames below it.\n\
2011 This problem is most likely caused by an invalid program counter or\n\
2012stack pointer.\n\
2013 However, if you think GDB should simply search farther back\n\
2014from 0x%s for code which looks like the beginning of a\n\
2015function, you can increase the range of the search using the `set\n\
2016heuristic-fence-post' command.\n",
c5aa993b
JM
2017 paddr_nz (pc), paddr_nz (pc));
2018 blurb_printed = 1;
c906108c 2019 }
c906108c
SS
2020 }
2021
c5aa993b
JM
2022 return 0;
2023 }
2024 else if (pc_is_mips16 (start_pc))
2025 {
2026 unsigned short inst;
2027
2028 /* On MIPS16, any one of the following is likely to be the
2029 start of a function:
2030 entry
2031 addiu sp,-n
2032 daddiu sp,-n
2033 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2034 inst = mips_fetch_instruction (start_pc);
2035 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2036 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2037 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2038 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2039 break;
2040 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2041 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2042 seen_adjsp = 1;
2043 else
2044 seen_adjsp = 0;
2045 }
2046 else if (mips_about_to_return (start_pc))
2047 {
2048 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
2049 break;
2050 }
2051
c5aa993b 2052 return start_pc;
c906108c
SS
2053}
2054
2055/* Fetch the immediate value from a MIPS16 instruction.
2056 If the previous instruction was an EXTEND, use it to extend
2057 the upper bits of the immediate value. This is a helper function
2058 for mips16_heuristic_proc_desc. */
2059
2060static int
acdb74a0
AC
2061mips16_get_imm (unsigned short prev_inst, /* previous instruction */
2062 unsigned short inst, /* current instruction */
2063 int nbits, /* number of bits in imm field */
2064 int scale, /* scale factor to be applied to imm */
2065 int is_signed) /* is the imm field signed? */
c906108c
SS
2066{
2067 int offset;
2068
2069 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2070 {
2071 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
c5aa993b 2072 if (offset & 0x8000) /* check for negative extend */
c906108c
SS
2073 offset = 0 - (0x10000 - (offset & 0xffff));
2074 return offset | (inst & 0x1f);
2075 }
2076 else
2077 {
2078 int max_imm = 1 << nbits;
2079 int mask = max_imm - 1;
2080 int sign_bit = max_imm >> 1;
2081
2082 offset = inst & mask;
2083 if (is_signed && (offset & sign_bit))
2084 offset = 0 - (max_imm - offset);
2085 return offset * scale;
2086 }
2087}
2088
2089
2090/* Fill in values in temp_proc_desc based on the MIPS16 instruction
2091 stream from start_pc to limit_pc. */
2092
2093static void
acdb74a0
AC
2094mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2095 struct frame_info *next_frame, CORE_ADDR sp)
c906108c
SS
2096{
2097 CORE_ADDR cur_pc;
2098 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
2099 unsigned short prev_inst = 0; /* saved copy of previous instruction */
2100 unsigned inst = 0; /* current instruction */
2101 unsigned entry_inst = 0; /* the entry instruction */
2102 int reg, offset;
2103
c5aa993b
JM
2104 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
2105 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
c906108c
SS
2106
2107 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
2108 {
2109 /* Save the previous instruction. If it's an EXTEND, we'll extract
2110 the immediate offset extension from it in mips16_get_imm. */
2111 prev_inst = inst;
2112
2113 /* Fetch and decode the instruction. */
2114 inst = (unsigned short) mips_fetch_instruction (cur_pc);
c5aa993b 2115 if ((inst & 0xff00) == 0x6300 /* addiu sp */
c906108c
SS
2116 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2117 {
2118 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
c5aa993b
JM
2119 if (offset < 0) /* negative stack adjustment? */
2120 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
c906108c
SS
2121 else
2122 /* Exit loop if a positive stack adjustment is found, which
2123 usually means that the stack cleanup code in the function
2124 epilogue is reached. */
2125 break;
2126 }
2127 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2128 {
2129 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2130 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
c5aa993b 2131 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
e0f7ec59 2132 set_reg_offset (temp_saved_regs, reg, sp + offset);
c906108c
SS
2133 }
2134 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2135 {
2136 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2137 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
c5aa993b 2138 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
e0f7ec59 2139 set_reg_offset (temp_saved_regs, reg, sp + offset);
c906108c
SS
2140 }
2141 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2142 {
2143 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
c5aa993b 2144 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
e0f7ec59 2145 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
c906108c
SS
2146 }
2147 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2148 {
2149 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
c5aa993b 2150 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
e0f7ec59 2151 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
c906108c 2152 }
c5aa993b 2153 else if (inst == 0x673d) /* move $s1, $sp */
c906108c
SS
2154 {
2155 frame_addr = sp;
2156 PROC_FRAME_REG (&temp_proc_desc) = 17;
2157 }
2158 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2159 {
2160 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2161 frame_addr = sp + offset;
2162 PROC_FRAME_REG (&temp_proc_desc) = 17;
2163 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
2164 }
2165 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2166 {
2167 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2168 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
c5aa993b 2169 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2170 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
c906108c
SS
2171 }
2172 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2173 {
2174 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2175 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
c5aa993b 2176 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2177 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
c906108c 2178 }
c5aa993b
JM
2179 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2180 entry_inst = inst; /* save for later processing */
c906108c 2181 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
c5aa993b 2182 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
c906108c
SS
2183 }
2184
c5aa993b
JM
2185 /* The entry instruction is typically the first instruction in a function,
2186 and it stores registers at offsets relative to the value of the old SP
2187 (before the prologue). But the value of the sp parameter to this
2188 function is the new SP (after the prologue has been executed). So we
2189 can't calculate those offsets until we've seen the entire prologue,
2190 and can calculate what the old SP must have been. */
2191 if (entry_inst != 0)
2192 {
2193 int areg_count = (entry_inst >> 8) & 7;
2194 int sreg_count = (entry_inst >> 6) & 3;
c906108c 2195
c5aa993b
JM
2196 /* The entry instruction always subtracts 32 from the SP. */
2197 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
c906108c 2198
c5aa993b
JM
2199 /* Now we can calculate what the SP must have been at the
2200 start of the function prologue. */
2201 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
c906108c 2202
c5aa993b
JM
2203 /* Check if a0-a3 were saved in the caller's argument save area. */
2204 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2205 {
2206 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2207 set_reg_offset (temp_saved_regs, reg, sp + offset);
c5aa993b
JM
2208 offset += MIPS_SAVED_REGSIZE;
2209 }
c906108c 2210
c5aa993b
JM
2211 /* Check if the ra register was pushed on the stack. */
2212 offset = -4;
2213 if (entry_inst & 0x20)
2214 {
2215 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
e0f7ec59 2216 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
c5aa993b
JM
2217 offset -= MIPS_SAVED_REGSIZE;
2218 }
c906108c 2219
c5aa993b
JM
2220 /* Check if the s0 and s1 registers were pushed on the stack. */
2221 for (reg = 16; reg < sreg_count + 16; reg++)
2222 {
2223 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2224 set_reg_offset (temp_saved_regs, reg, sp + offset);
c5aa993b
JM
2225 offset -= MIPS_SAVED_REGSIZE;
2226 }
2227 }
c906108c
SS
2228}
2229
2230static void
fba45db2
KB
2231mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2232 struct frame_info *next_frame, CORE_ADDR sp)
c906108c
SS
2233{
2234 CORE_ADDR cur_pc;
c5aa993b 2235 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
c906108c 2236restart:
fe29b929 2237 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
cce74817 2238 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
c5aa993b 2239 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
c906108c
SS
2240 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2241 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2242 {
2243 unsigned long inst, high_word, low_word;
2244 int reg;
2245
2246 /* Fetch the instruction. */
2247 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2248
2249 /* Save some code by pre-extracting some useful fields. */
2250 high_word = (inst >> 16) & 0xffff;
2251 low_word = inst & 0xffff;
2252 reg = high_word & 0x1f;
2253
c5aa993b 2254 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
c906108c
SS
2255 || high_word == 0x23bd /* addi $sp,$sp,-i */
2256 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2257 {
2258 if (low_word & 0x8000) /* negative stack adjustment? */
c5aa993b 2259 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
c906108c
SS
2260 else
2261 /* Exit loop if a positive stack adjustment is found, which
2262 usually means that the stack cleanup code in the function
2263 epilogue is reached. */
2264 break;
2265 }
2266 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2267 {
c5aa993b 2268 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2269 set_reg_offset (temp_saved_regs, reg, sp + low_word);
c906108c
SS
2270 }
2271 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2272 {
2273 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2274 but the register size used is only 32 bits. Make the address
2275 for the saved register point to the lower 32 bits. */
c5aa993b 2276 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2277 set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - MIPS_REGSIZE);
c906108c 2278 }
c5aa993b 2279 else if (high_word == 0x27be) /* addiu $30,$sp,size */
c906108c
SS
2280 {
2281 /* Old gcc frame, r30 is virtual frame pointer. */
c5aa993b
JM
2282 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2283 frame_addr = sp + low_word;
c906108c
SS
2284 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2285 {
2286 unsigned alloca_adjust;
2287 PROC_FRAME_REG (&temp_proc_desc) = 30;
a4b8ebc8 2288 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
c5aa993b 2289 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
c906108c
SS
2290 if (alloca_adjust > 0)
2291 {
2292 /* FP > SP + frame_size. This may be because
2293 * of an alloca or somethings similar.
2294 * Fix sp to "pre-alloca" value, and try again.
2295 */
2296 sp += alloca_adjust;
2297 goto restart;
2298 }
2299 }
2300 }
c5aa993b
JM
2301 /* move $30,$sp. With different versions of gas this will be either
2302 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2303 Accept any one of these. */
c906108c
SS
2304 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2305 {
2306 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2307 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2308 {
2309 unsigned alloca_adjust;
2310 PROC_FRAME_REG (&temp_proc_desc) = 30;
a4b8ebc8 2311 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
c5aa993b 2312 alloca_adjust = (unsigned) (frame_addr - sp);
c906108c
SS
2313 if (alloca_adjust > 0)
2314 {
2315 /* FP > SP + frame_size. This may be because
2316 * of an alloca or somethings similar.
2317 * Fix sp to "pre-alloca" value, and try again.
2318 */
2319 sp += alloca_adjust;
2320 goto restart;
2321 }
2322 }
2323 }
c5aa993b 2324 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
c906108c 2325 {
c5aa993b 2326 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
e0f7ec59 2327 set_reg_offset (temp_saved_regs, reg, frame_addr + low_word);
c906108c
SS
2328 }
2329 }
2330}
2331
2332static mips_extra_func_info_t
acdb74a0 2333heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
479412cd 2334 struct frame_info *next_frame, int cur_frame)
c906108c 2335{
479412cd
DJ
2336 CORE_ADDR sp;
2337
2338 if (cur_frame)
a4b8ebc8 2339 sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM);
479412cd
DJ
2340 else
2341 sp = 0;
c906108c 2342
c5aa993b
JM
2343 if (start_pc == 0)
2344 return NULL;
2345 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
fe29b929 2346 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
3758ac48 2347 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
c906108c
SS
2348 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2349 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2350 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2351
2352 if (start_pc + 200 < limit_pc)
2353 limit_pc = start_pc + 200;
2354 if (pc_is_mips16 (start_pc))
2355 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2356 else
2357 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2358 return &temp_proc_desc;
2359}
2360
6c0d6680
DJ
2361struct mips_objfile_private
2362{
2363 bfd_size_type size;
2364 char *contents;
2365};
2366
2367/* Global used to communicate between non_heuristic_proc_desc and
2368 compare_pdr_entries within qsort (). */
2369static bfd *the_bfd;
2370
2371static int
2372compare_pdr_entries (const void *a, const void *b)
2373{
2374 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2375 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2376
2377 if (lhs < rhs)
2378 return -1;
2379 else if (lhs == rhs)
2380 return 0;
2381 else
2382 return 1;
2383}
2384
c906108c 2385static mips_extra_func_info_t
acdb74a0 2386non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
c906108c
SS
2387{
2388 CORE_ADDR startaddr;
2389 mips_extra_func_info_t proc_desc;
c5aa993b 2390 struct block *b = block_for_pc (pc);
c906108c 2391 struct symbol *sym;
6c0d6680
DJ
2392 struct obj_section *sec;
2393 struct mips_objfile_private *priv;
2394
ae45cd16 2395 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
6c0d6680 2396 return NULL;
c906108c
SS
2397
2398 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2399 if (addrptr)
2400 *addrptr = startaddr;
6c0d6680
DJ
2401
2402 priv = NULL;
2403
2404 sec = find_pc_section (pc);
2405 if (sec != NULL)
c906108c 2406 {
6c0d6680
DJ
2407 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2408
2409 /* Search the ".pdr" section generated by GAS. This includes most of
2410 the information normally found in ECOFF PDRs. */
2411
2412 the_bfd = sec->objfile->obfd;
2413 if (priv == NULL
2414 && (the_bfd->format == bfd_object
2415 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2416 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2417 {
2418 /* Right now GAS only outputs the address as a four-byte sequence.
2419 This means that we should not bother with this method on 64-bit
2420 targets (until that is fixed). */
2421
2422 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2423 sizeof (struct mips_objfile_private));
2424 priv->size = 0;
2425 sec->objfile->obj_private = priv;
2426 }
2427 else if (priv == NULL)
2428 {
2429 asection *bfdsec;
2430
2431 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2432 sizeof (struct mips_objfile_private));
2433
2434 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2435 if (bfdsec != NULL)
2436 {
2437 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2438 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2439 priv->size);
2440 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2441 priv->contents, 0, priv->size);
2442
2443 /* In general, the .pdr section is sorted. However, in the
2444 presence of multiple code sections (and other corner cases)
2445 it can become unsorted. Sort it so that we can use a faster
2446 binary search. */
2447 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2448 }
2449 else
2450 priv->size = 0;
2451
2452 sec->objfile->obj_private = priv;
2453 }
2454 the_bfd = NULL;
2455
2456 if (priv->size != 0)
2457 {
2458 int low, mid, high;
2459 char *ptr;
2460
2461 low = 0;
2462 high = priv->size / 32;
2463
2464 do
2465 {
2466 CORE_ADDR pdr_pc;
2467
2468 mid = (low + high) / 2;
2469
2470 ptr = priv->contents + mid * 32;
2471 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2472 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2473 SECT_OFF_TEXT (sec->objfile));
2474 if (pdr_pc == startaddr)
2475 break;
2476 if (pdr_pc > startaddr)
2477 high = mid;
2478 else
2479 low = mid + 1;
2480 }
2481 while (low != high);
2482
2483 if (low != high)
2484 {
2485 struct symbol *sym = find_pc_function (pc);
2486
2487 /* Fill in what we need of the proc_desc. */
2488 proc_desc = (mips_extra_func_info_t)
2489 obstack_alloc (&sec->objfile->psymbol_obstack,
2490 sizeof (struct mips_extra_func_info));
2491 PROC_LOW_ADDR (proc_desc) = startaddr;
2492
2493 /* Only used for dummy frames. */
2494 PROC_HIGH_ADDR (proc_desc) = 0;
2495
2496 PROC_FRAME_OFFSET (proc_desc)
2497 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2498 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2499 ptr + 24);
2500 PROC_FRAME_ADJUST (proc_desc) = 0;
2501 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2502 ptr + 4);
2503 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2504 ptr + 12);
2505 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2506 ptr + 8);
2507 PROC_FREG_OFFSET (proc_desc)
2508 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2509 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2510 ptr + 28);
2511 proc_desc->pdr.isym = (long) sym;
2512
2513 return proc_desc;
2514 }
2515 }
c906108c
SS
2516 }
2517
6c0d6680
DJ
2518 if (b == NULL)
2519 return NULL;
2520
2521 if (startaddr > BLOCK_START (b))
2522 {
2523 /* This is the "pathological" case referred to in a comment in
2524 print_frame_info. It might be better to move this check into
2525 symbol reading. */
2526 return NULL;
2527 }
2528
176620f1 2529 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL);
6c0d6680 2530
c906108c
SS
2531 /* If we never found a PDR for this function in symbol reading, then
2532 examine prologues to find the information. */
2533 if (sym)
2534 {
2535 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2536 if (PROC_FRAME_REG (proc_desc) == -1)
2537 return NULL;
2538 else
2539 return proc_desc;
2540 }
2541 else
2542 return NULL;
2543}
2544
2545
2546static mips_extra_func_info_t
479412cd 2547find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
c906108c
SS
2548{
2549 mips_extra_func_info_t proc_desc;
4e0df2df 2550 CORE_ADDR startaddr = 0;
c906108c
SS
2551
2552 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2553
2554 if (proc_desc)
2555 {
2556 /* IF this is the topmost frame AND
2557 * (this proc does not have debugging information OR
2558 * the PC is in the procedure prologue)
2559 * THEN create a "heuristic" proc_desc (by analyzing
2560 * the actual code) to replace the "official" proc_desc.
2561 */
2562 if (next_frame == NULL)
2563 {
2564 struct symtab_and_line val;
2565 struct symbol *proc_symbol =
c86b5b38 2566 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
c906108c
SS
2567
2568 if (proc_symbol)
2569 {
2570 val = find_pc_line (BLOCK_START
c5aa993b 2571 (SYMBOL_BLOCK_VALUE (proc_symbol)),
c906108c
SS
2572 0);
2573 val.pc = val.end ? val.end : pc;
2574 }
2575 if (!proc_symbol || pc < val.pc)
2576 {
2577 mips_extra_func_info_t found_heuristic =
c86b5b38
MS
2578 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2579 pc, next_frame, cur_frame);
c906108c
SS
2580 if (found_heuristic)
2581 proc_desc = found_heuristic;
2582 }
2583 }
2584 }
2585 else
2586 {
2587 /* Is linked_proc_desc_table really necessary? It only seems to be used
c5aa993b
JM
2588 by procedure call dummys. However, the procedures being called ought
2589 to have their own proc_descs, and even if they don't,
2590 heuristic_proc_desc knows how to create them! */
c906108c 2591
aa1ee363 2592 struct linked_proc_info *link;
c906108c
SS
2593
2594 for (link = linked_proc_desc_table; link; link = link->next)
c5aa993b
JM
2595 if (PROC_LOW_ADDR (&link->info) <= pc
2596 && PROC_HIGH_ADDR (&link->info) > pc)
c906108c
SS
2597 return &link->info;
2598
2599 if (startaddr == 0)
2600 startaddr = heuristic_proc_start (pc);
2601
2602 proc_desc =
479412cd 2603 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
c906108c
SS
2604 }
2605 return proc_desc;
2606}
2607
2608static CORE_ADDR
acdb74a0
AC
2609get_frame_pointer (struct frame_info *frame,
2610 mips_extra_func_info_t proc_desc)
c906108c 2611{
a4b8ebc8 2612 return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
e227b13c
AC
2613 + PROC_FRAME_OFFSET (proc_desc)
2614 - PROC_FRAME_ADJUST (proc_desc));
c906108c
SS
2615}
2616
5a89d8aa 2617static mips_extra_func_info_t cached_proc_desc;
c906108c 2618
f7ab6ec6 2619static CORE_ADDR
acdb74a0 2620mips_frame_chain (struct frame_info *frame)
c906108c
SS
2621{
2622 mips_extra_func_info_t proc_desc;
2623 CORE_ADDR tmp;
8bedc050 2624 CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame);
c906108c 2625
627b3ba2 2626 if (saved_pc == 0 || deprecated_inside_entry_file (saved_pc))
c906108c
SS
2627 return 0;
2628
2629 /* Check if the PC is inside a call stub. If it is, fetch the
2630 PC of the caller of that stub. */
5a89d8aa 2631 if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0)
c906108c
SS
2632 saved_pc = tmp;
2633
ae45cd16 2634 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0))
cedea778
AC
2635 {
2636 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2637 is well, frame->frame the bottom of the current frame will
2638 contain that value. */
1e2330ba 2639 return get_frame_base (frame);
cedea778
AC
2640 }
2641
c906108c 2642 /* Look up the procedure descriptor for this PC. */
479412cd 2643 proc_desc = find_proc_desc (saved_pc, frame, 1);
c906108c
SS
2644 if (!proc_desc)
2645 return 0;
2646
2647 cached_proc_desc = proc_desc;
2648
2649 /* If no frame pointer and frame size is zero, we must be at end
2650 of stack (or otherwise hosed). If we don't check frame size,
2651 we loop forever if we see a zero size frame. */
2652 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2653 && PROC_FRAME_OFFSET (proc_desc) == 0
7807aa61
MS
2654 /* The previous frame from a sigtramp frame might be frameless
2655 and have frame size zero. */
5a203e44 2656 && !(get_frame_type (frame) == SIGTRAMP_FRAME)
cedea778
AC
2657 /* For a generic dummy frame, let get_frame_pointer() unwind a
2658 register value saved as part of the dummy frame call. */
50abf9e5 2659 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)))
c906108c
SS
2660 return 0;
2661 else
2662 return get_frame_pointer (frame, proc_desc);
2663}
2664
f7ab6ec6 2665static void
acdb74a0 2666mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
c906108c
SS
2667{
2668 int regnum;
f2c16bd6
KB
2669 mips_extra_func_info_t proc_desc;
2670
2671 if (get_frame_type (fci) == DUMMY_FRAME)
2672 return;
c906108c 2673
f796e4be
KB
2674 /* Use proc_desc calculated in frame_chain. When there is no
2675 next frame, i.e, get_next_frame (fci) == NULL, we call
2676 find_proc_desc () to calculate it, passing an explicit
2677 NULL as the frame parameter. */
f2c16bd6 2678 proc_desc =
11c02a10
AC
2679 get_next_frame (fci)
2680 ? cached_proc_desc
f796e4be
KB
2681 : find_proc_desc (get_frame_pc (fci),
2682 NULL /* i.e, get_next_frame (fci) */,
2683 1);
c906108c 2684
a00a19e9 2685 frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info));
cce74817 2686
7b5849cc 2687 deprecated_set_frame_saved_regs_hack (fci, NULL);
da50a4b7 2688 get_frame_extra_info (fci)->proc_desc =
c906108c
SS
2689 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2690 if (proc_desc)
2691 {
2692 /* Fixup frame-pointer - only needed for top frame */
2693 /* This may not be quite right, if proc has a real frame register.
c5aa993b
JM
2694 Get the value of the frame relative sp, procedure might have been
2695 interrupted by a signal at it's very start. */
50abf9e5 2696 if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc)
c906108c 2697 && !PROC_DESC_IS_DUMMY (proc_desc))
a4b8ebc8 2698 deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM));
50abf9e5 2699 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0))
cedea778
AC
2700 /* Do not ``fix'' fci->frame. It will have the value of the
2701 generic dummy frame's top-of-stack (since the draft
2702 fci->frame is obtained by returning the unwound stack
2703 pointer) and that is what we want. That way the fci->frame
2704 value will match the top-of-stack value that was saved as
2705 part of the dummy frames data. */
2706 /* Do nothing. */;
c906108c 2707 else
11c02a10 2708 deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc));
c906108c
SS
2709
2710 if (proc_desc == &temp_proc_desc)
2711 {
2712 char *name;
2713
2714 /* Do not set the saved registers for a sigtramp frame,
5a203e44
AC
2715 mips_find_saved_registers will do that for us. We can't
2716 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2717 yet set. */
2718 /* FIXME: cagney/2002-11-18: This problem will go away once
2719 frame.c:get_prev_frame() is modified to set the frame's
2720 type before calling functions like this. */
50abf9e5 2721 find_pc_partial_function (get_frame_pc (fci), &name,
c5aa993b 2722 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
50abf9e5 2723 if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name))
c906108c 2724 {
c5aa993b 2725 frame_saved_regs_zalloc (fci);
e0f7ec59
AC
2726 /* Set value of previous frame's stack pointer.
2727 Remember that saved_regs[SP_REGNUM] is special in
2728 that it contains the value of the stack pointer
2729 register. The other saved_regs values are addresses
2730 (in the inferior) at which a given register's value
2731 may be found. */
2732 set_reg_offset (temp_saved_regs, SP_REGNUM,
2733 get_frame_base (fci));
2734 set_reg_offset (temp_saved_regs, PC_REGNUM,
2735 temp_saved_regs[RA_REGNUM]);
1b1d3794 2736 memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs,
e0f7ec59 2737 SIZEOF_FRAME_SAVED_REGS);
c906108c
SS
2738 }
2739 }
2740
2741 /* hack: if argument regs are saved, guess these contain args */
cce74817 2742 /* assume we can't tell how many args for now */
da50a4b7 2743 get_frame_extra_info (fci)->num_args = -1;
c906108c
SS
2744 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2745 {
c5aa993b 2746 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
c906108c 2747 {
da50a4b7 2748 get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1;
c906108c
SS
2749 break;
2750 }
c5aa993b 2751 }
c906108c
SS
2752 }
2753}
2754
2755/* MIPS stack frames are almost impenetrable. When execution stops,
2756 we basically have to look at symbol information for the function
2757 that we stopped in, which tells us *which* register (if any) is
2758 the base of the frame pointer, and what offset from that register
361d1df0 2759 the frame itself is at.
c906108c
SS
2760
2761 This presents a problem when trying to examine a stack in memory
2762 (that isn't executing at the moment), using the "frame" command. We
2763 don't have a PC, nor do we have any registers except SP.
2764
2765 This routine takes two arguments, SP and PC, and tries to make the
2766 cached frames look as if these two arguments defined a frame on the
2767 cache. This allows the rest of info frame to extract the important
2768 arguments without difficulty. */
2769
2770struct frame_info *
acdb74a0 2771setup_arbitrary_frame (int argc, CORE_ADDR *argv)
c906108c
SS
2772{
2773 if (argc != 2)
2774 error ("MIPS frame specifications require two arguments: sp and pc");
2775
2776 return create_new_frame (argv[0], argv[1]);
2777}
2778
f09ded24
AC
2779/* According to the current ABI, should the type be passed in a
2780 floating-point register (assuming that there is space)? When there
2781 is no FPU, FP are not even considered as possibile candidates for
2782 FP registers and, consequently this returns false - forces FP
2783 arguments into integer registers. */
2784
2785static int
2786fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2787{
2788 return ((typecode == TYPE_CODE_FLT
2789 || (MIPS_EABI
2790 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2791 && TYPE_NFIELDS (arg_type) == 1
2792 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
c86b5b38 2793 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
f09ded24
AC
2794}
2795
49e790b0
DJ
2796/* On o32, argument passing in GPRs depends on the alignment of the type being
2797 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2798
2799static int
2800mips_type_needs_double_align (struct type *type)
2801{
2802 enum type_code typecode = TYPE_CODE (type);
361d1df0 2803
49e790b0
DJ
2804 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2805 return 1;
2806 else if (typecode == TYPE_CODE_STRUCT)
2807 {
2808 if (TYPE_NFIELDS (type) < 1)
2809 return 0;
2810 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2811 }
2812 else if (typecode == TYPE_CODE_UNION)
2813 {
361d1df0 2814 int i, n;
49e790b0
DJ
2815
2816 n = TYPE_NFIELDS (type);
2817 for (i = 0; i < n; i++)
2818 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2819 return 1;
2820 return 0;
2821 }
2822 return 0;
2823}
2824
dc604539
AC
2825/* Adjust the address downward (direction of stack growth) so that it
2826 is correctly aligned for a new stack frame. */
2827static CORE_ADDR
2828mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2829{
5b03f266 2830 return align_down (addr, 16);
dc604539
AC
2831}
2832
f7ab6ec6 2833static CORE_ADDR
25ab4790
AC
2834mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2835 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2836 struct value **args, CORE_ADDR sp, int struct_return,
2837 CORE_ADDR struct_addr)
c906108c
SS
2838{
2839 int argreg;
2840 int float_argreg;
2841 int argnum;
2842 int len = 0;
2843 int stack_offset = 0;
2844
25ab4790
AC
2845 /* For shared libraries, "t9" needs to point at the function
2846 address. */
2847 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2848
2849 /* Set the return address register to point to the entry point of
2850 the program, where a breakpoint lies in wait. */
2851 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2852
c906108c 2853 /* First ensure that the stack and structure return address (if any)
cb3d25d1
MS
2854 are properly aligned. The stack has to be at least 64-bit
2855 aligned even on 32-bit machines, because doubles must be 64-bit
2856 aligned. For n32 and n64, stack frames need to be 128-bit
2857 aligned, so we round to this widest known alignment. */
2858
5b03f266
AC
2859 sp = align_down (sp, 16);
2860 struct_addr = align_down (struct_addr, 16);
c5aa993b 2861
46e0f506 2862 /* Now make space on the stack for the args. We allocate more
c906108c 2863 than necessary for EABI, because the first few arguments are
46e0f506 2864 passed in registers, but that's OK. */
c906108c 2865 for (argnum = 0; argnum < nargs; argnum++)
5b03f266 2866 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
46e0f506 2867 MIPS_STACK_ARGSIZE);
5b03f266 2868 sp -= align_up (len, 16);
c906108c 2869
9ace0497 2870 if (mips_debug)
46e0f506 2871 fprintf_unfiltered (gdb_stdlog,
5b03f266
AC
2872 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2873 paddr_nz (sp), (long) align_up (len, 16));
9ace0497 2874
c906108c
SS
2875 /* Initialize the integer and float register pointers. */
2876 argreg = A0_REGNUM;
2877 float_argreg = FPA0_REGNUM;
2878
46e0f506 2879 /* The struct_return pointer occupies the first parameter-passing reg. */
c906108c 2880 if (struct_return)
9ace0497
AC
2881 {
2882 if (mips_debug)
2883 fprintf_unfiltered (gdb_stdlog,
25ab4790 2884 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
cb3d25d1 2885 argreg, paddr_nz (struct_addr));
9ace0497
AC
2886 write_register (argreg++, struct_addr);
2887 }
c906108c
SS
2888
2889 /* Now load as many as possible of the first arguments into
2890 registers, and push the rest onto the stack. Loop thru args
2891 from first to last. */
2892 for (argnum = 0; argnum < nargs; argnum++)
2893 {
2894 char *val;
d9d9c31f 2895 char valbuf[MAX_REGISTER_SIZE];
ea7c478f 2896 struct value *arg = args[argnum];
c906108c
SS
2897 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2898 int len = TYPE_LENGTH (arg_type);
2899 enum type_code typecode = TYPE_CODE (arg_type);
2900
9ace0497
AC
2901 if (mips_debug)
2902 fprintf_unfiltered (gdb_stdlog,
25ab4790 2903 "mips_eabi_push_dummy_call: %d len=%d type=%d",
acdb74a0 2904 argnum + 1, len, (int) typecode);
9ace0497 2905
c906108c 2906 /* The EABI passes structures that do not fit in a register by
46e0f506
MS
2907 reference. */
2908 if (len > MIPS_SAVED_REGSIZE
9ace0497 2909 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
c906108c 2910 {
fbd9dcd3 2911 store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
c906108c 2912 typecode = TYPE_CODE_PTR;
7a292a7a 2913 len = MIPS_SAVED_REGSIZE;
c906108c 2914 val = valbuf;
9ace0497
AC
2915 if (mips_debug)
2916 fprintf_unfiltered (gdb_stdlog, " push");
c906108c
SS
2917 }
2918 else
c5aa993b 2919 val = (char *) VALUE_CONTENTS (arg);
c906108c
SS
2920
2921 /* 32-bit ABIs always start floating point arguments in an
acdb74a0
AC
2922 even-numbered floating point register. Round the FP register
2923 up before the check to see if there are any FP registers
46e0f506
MS
2924 left. Non MIPS_EABI targets also pass the FP in the integer
2925 registers so also round up normal registers. */
acdb74a0
AC
2926 if (!FP_REGISTER_DOUBLE
2927 && fp_register_arg_p (typecode, arg_type))
2928 {
2929 if ((float_argreg & 1))
2930 float_argreg++;
2931 }
c906108c
SS
2932
2933 /* Floating point arguments passed in registers have to be
2934 treated specially. On 32-bit architectures, doubles
c5aa993b
JM
2935 are passed in register pairs; the even register gets
2936 the low word, and the odd register gets the high word.
2937 On non-EABI processors, the first two floating point arguments are
2938 also copied to general registers, because MIPS16 functions
2939 don't use float registers for arguments. This duplication of
2940 arguments in general registers can't hurt non-MIPS16 functions
2941 because those registers are normally skipped. */
1012bd0e
EZ
2942 /* MIPS_EABI squeezes a struct that contains a single floating
2943 point value into an FP register instead of pushing it onto the
46e0f506 2944 stack. */
f09ded24
AC
2945 if (fp_register_arg_p (typecode, arg_type)
2946 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
c906108c
SS
2947 {
2948 if (!FP_REGISTER_DOUBLE && len == 8)
2949 {
d7449b42 2950 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
c906108c
SS
2951 unsigned long regval;
2952
2953 /* Write the low word of the double to the even register(s). */
c5aa993b 2954 regval = extract_unsigned_integer (val + low_offset, 4);
9ace0497 2955 if (mips_debug)
acdb74a0 2956 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
9ace0497 2957 float_argreg, phex (regval, 4));
c906108c 2958 write_register (float_argreg++, regval);
c906108c
SS
2959
2960 /* Write the high word of the double to the odd register(s). */
c5aa993b 2961 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
9ace0497 2962 if (mips_debug)
acdb74a0 2963 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
9ace0497 2964 float_argreg, phex (regval, 4));
c906108c 2965 write_register (float_argreg++, regval);
c906108c
SS
2966 }
2967 else
2968 {
2969 /* This is a floating point value that fits entirely
2970 in a single register. */
53a5351d 2971 /* On 32 bit ABI's the float_argreg is further adjusted
46e0f506 2972 above to ensure that it is even register aligned. */
9ace0497
AC
2973 LONGEST regval = extract_unsigned_integer (val, len);
2974 if (mips_debug)
acdb74a0 2975 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
9ace0497 2976 float_argreg, phex (regval, len));
c906108c 2977 write_register (float_argreg++, regval);
c906108c
SS
2978 }
2979 }
2980 else
2981 {
2982 /* Copy the argument to general registers or the stack in
2983 register-sized pieces. Large arguments are split between
2984 registers and stack. */
2985 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2986 are treated specially: Irix cc passes them in registers
2987 where gcc sometimes puts them on the stack. For maximum
2988 compatibility, we will put them in both places. */
c5aa993b 2989 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
7a292a7a 2990 (len % MIPS_SAVED_REGSIZE != 0));
46e0f506 2991
f09ded24 2992 /* Note: Floating-point values that didn't fit into an FP
46e0f506 2993 register are only written to memory. */
c906108c
SS
2994 while (len > 0)
2995 {
ebafbe83 2996 /* Remember if the argument was written to the stack. */
566f0f7a 2997 int stack_used_p = 0;
46e0f506
MS
2998 int partial_len =
2999 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
c906108c 3000
acdb74a0
AC
3001 if (mips_debug)
3002 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3003 partial_len);
3004
566f0f7a 3005 /* Write this portion of the argument to the stack. */
f09ded24
AC
3006 if (argreg > MIPS_LAST_ARG_REGNUM
3007 || odd_sized_struct
3008 || fp_register_arg_p (typecode, arg_type))
c906108c 3009 {
c906108c
SS
3010 /* Should shorter than int integer values be
3011 promoted to int before being stored? */
c906108c 3012 int longword_offset = 0;
9ace0497 3013 CORE_ADDR addr;
566f0f7a 3014 stack_used_p = 1;
d7449b42 3015 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
7a292a7a 3016 {
d929b26f 3017 if (MIPS_STACK_ARGSIZE == 8 &&
7a292a7a
SS
3018 (typecode == TYPE_CODE_INT ||
3019 typecode == TYPE_CODE_PTR ||
3020 typecode == TYPE_CODE_FLT) && len <= 4)
d929b26f 3021 longword_offset = MIPS_STACK_ARGSIZE - len;
7a292a7a
SS
3022 else if ((typecode == TYPE_CODE_STRUCT ||
3023 typecode == TYPE_CODE_UNION) &&
d929b26f
AC
3024 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
3025 longword_offset = MIPS_STACK_ARGSIZE - len;
7a292a7a 3026 }
c5aa993b 3027
9ace0497
AC
3028 if (mips_debug)
3029 {
cb3d25d1
MS
3030 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3031 paddr_nz (stack_offset));
3032 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3033 paddr_nz (longword_offset));
9ace0497 3034 }
361d1df0 3035
9ace0497
AC
3036 addr = sp + stack_offset + longword_offset;
3037
3038 if (mips_debug)
3039 {
3040 int i;
cb3d25d1
MS
3041 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3042 paddr_nz (addr));
9ace0497
AC
3043 for (i = 0; i < partial_len; i++)
3044 {
cb3d25d1
MS
3045 fprintf_unfiltered (gdb_stdlog, "%02x",
3046 val[i] & 0xff);
9ace0497
AC
3047 }
3048 }
3049 write_memory (addr, val, partial_len);
c906108c
SS
3050 }
3051
f09ded24
AC
3052 /* Note!!! This is NOT an else clause. Odd sized
3053 structs may go thru BOTH paths. Floating point
46e0f506 3054 arguments will not. */
566f0f7a 3055 /* Write this portion of the argument to a general
46e0f506 3056 purpose register. */
f09ded24
AC
3057 if (argreg <= MIPS_LAST_ARG_REGNUM
3058 && !fp_register_arg_p (typecode, arg_type))
c906108c 3059 {
9ace0497 3060 LONGEST regval = extract_unsigned_integer (val, partial_len);
c906108c 3061
9ace0497 3062 if (mips_debug)
acdb74a0 3063 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
9ace0497
AC
3064 argreg,
3065 phex (regval, MIPS_SAVED_REGSIZE));
c906108c
SS
3066 write_register (argreg, regval);
3067 argreg++;
c906108c 3068 }
c5aa993b 3069
c906108c
SS
3070 len -= partial_len;
3071 val += partial_len;
3072
566f0f7a
AC
3073 /* Compute the the offset into the stack at which we
3074 will copy the next parameter.
3075
566f0f7a 3076 In the new EABI (and the NABI32), the stack_offset
46e0f506 3077 only needs to be adjusted when it has been used. */
c906108c 3078
46e0f506 3079 if (stack_used_p)
5b03f266 3080 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
c906108c
SS
3081 }
3082 }
9ace0497
AC
3083 if (mips_debug)
3084 fprintf_unfiltered (gdb_stdlog, "\n");
c906108c
SS
3085 }
3086
310e9b6a
AC
3087 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3088
0f71a2f6
JM
3089 /* Return adjusted stack pointer. */
3090 return sp;
3091}
3092
25ab4790 3093/* N32/N64 version of push_dummy_call. */
ebafbe83 3094
f7ab6ec6 3095static CORE_ADDR
25ab4790
AC
3096mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3097 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3098 struct value **args, CORE_ADDR sp, int struct_return,
3099 CORE_ADDR struct_addr)
cb3d25d1
MS
3100{
3101 int argreg;
3102 int float_argreg;
3103 int argnum;
3104 int len = 0;
3105 int stack_offset = 0;
3106
25ab4790
AC
3107 /* For shared libraries, "t9" needs to point at the function
3108 address. */
3109 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3110
3111 /* Set the return address register to point to the entry point of
3112 the program, where a breakpoint lies in wait. */
3113 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3114
cb3d25d1
MS
3115 /* First ensure that the stack and structure return address (if any)
3116 are properly aligned. The stack has to be at least 64-bit
3117 aligned even on 32-bit machines, because doubles must be 64-bit
3118 aligned. For n32 and n64, stack frames need to be 128-bit
3119 aligned, so we round to this widest known alignment. */
3120
5b03f266
AC
3121 sp = align_down (sp, 16);
3122 struct_addr = align_down (struct_addr, 16);
cb3d25d1
MS
3123
3124 /* Now make space on the stack for the args. */
3125 for (argnum = 0; argnum < nargs; argnum++)
5b03f266 3126 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
cb3d25d1 3127 MIPS_STACK_ARGSIZE);
5b03f266 3128 sp -= align_up (len, 16);
cb3d25d1
MS
3129
3130 if (mips_debug)
3131 fprintf_unfiltered (gdb_stdlog,
5b03f266
AC
3132 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3133 paddr_nz (sp), (long) align_up (len, 16));
cb3d25d1
MS
3134
3135 /* Initialize the integer and float register pointers. */
3136 argreg = A0_REGNUM;
3137 float_argreg = FPA0_REGNUM;
3138
46e0f506 3139 /* The struct_return pointer occupies the first parameter-passing reg. */
cb3d25d1
MS
3140 if (struct_return)
3141 {
3142 if (mips_debug)
3143 fprintf_unfiltered (gdb_stdlog,
25ab4790 3144 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
cb3d25d1
MS
3145 argreg, paddr_nz (struct_addr));
3146 write_register (argreg++, struct_addr);
3147 }
3148
3149 /* Now load as many as possible of the first arguments into
3150 registers, and push the rest onto the stack. Loop thru args
3151 from first to last. */
3152 for (argnum = 0; argnum < nargs; argnum++)
3153 {
3154 char *val;
d9d9c31f 3155 char valbuf[MAX_REGISTER_SIZE];
cb3d25d1
MS
3156 struct value *arg = args[argnum];
3157 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3158 int len = TYPE_LENGTH (arg_type);
3159 enum type_code typecode = TYPE_CODE (arg_type);
3160
3161 if (mips_debug)
3162 fprintf_unfiltered (gdb_stdlog,
25ab4790 3163 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
cb3d25d1
MS
3164 argnum + 1, len, (int) typecode);
3165
3166 val = (char *) VALUE_CONTENTS (arg);
3167
3168 if (fp_register_arg_p (typecode, arg_type)
3169 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3170 {
3171 /* This is a floating point value that fits entirely
3172 in a single register. */
3173 /* On 32 bit ABI's the float_argreg is further adjusted
3174 above to ensure that it is even register aligned. */
3175 LONGEST regval = extract_unsigned_integer (val, len);
3176 if (mips_debug)
3177 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3178 float_argreg, phex (regval, len));
3179 write_register (float_argreg++, regval);
3180
3181 if (mips_debug)
3182 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3183 argreg, phex (regval, len));
3184 write_register (argreg, regval);
3185 argreg += 1;
3186 }
3187 else
3188 {
3189 /* Copy the argument to general registers or the stack in
3190 register-sized pieces. Large arguments are split between
3191 registers and stack. */
3192 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3193 are treated specially: Irix cc passes them in registers
3194 where gcc sometimes puts them on the stack. For maximum
3195 compatibility, we will put them in both places. */
3196 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3197 (len % MIPS_SAVED_REGSIZE != 0));
3198 /* Note: Floating-point values that didn't fit into an FP
3199 register are only written to memory. */
3200 while (len > 0)
3201 {
3202 /* Rememer if the argument was written to the stack. */
3203 int stack_used_p = 0;
3204 int partial_len = len < MIPS_SAVED_REGSIZE ?
3205 len : MIPS_SAVED_REGSIZE;
3206
3207 if (mips_debug)
3208 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3209 partial_len);
3210
3211 /* Write this portion of the argument to the stack. */
3212 if (argreg > MIPS_LAST_ARG_REGNUM
3213 || odd_sized_struct
3214 || fp_register_arg_p (typecode, arg_type))
3215 {
3216 /* Should shorter than int integer values be
3217 promoted to int before being stored? */
3218 int longword_offset = 0;
3219 CORE_ADDR addr;
3220 stack_used_p = 1;
3221 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3222 {
3223 if (MIPS_STACK_ARGSIZE == 8 &&
3224 (typecode == TYPE_CODE_INT ||
3225 typecode == TYPE_CODE_PTR ||
3226 typecode == TYPE_CODE_FLT) && len <= 4)
3227 longword_offset = MIPS_STACK_ARGSIZE - len;
cb3d25d1
MS
3228 }
3229
3230 if (mips_debug)
3231 {
3232 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3233 paddr_nz (stack_offset));
3234 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3235 paddr_nz (longword_offset));
3236 }
3237
3238 addr = sp + stack_offset + longword_offset;
3239
3240 if (mips_debug)
3241 {
3242 int i;
3243 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3244 paddr_nz (addr));
3245 for (i = 0; i < partial_len; i++)
3246 {
3247 fprintf_unfiltered (gdb_stdlog, "%02x",
3248 val[i] & 0xff);
3249 }
3250 }
3251 write_memory (addr, val, partial_len);
3252 }
3253
3254 /* Note!!! This is NOT an else clause. Odd sized
3255 structs may go thru BOTH paths. Floating point
3256 arguments will not. */
3257 /* Write this portion of the argument to a general
3258 purpose register. */
3259 if (argreg <= MIPS_LAST_ARG_REGNUM
3260 && !fp_register_arg_p (typecode, arg_type))
3261 {
3262 LONGEST regval = extract_unsigned_integer (val, partial_len);
3263
3264 /* A non-floating-point argument being passed in a
3265 general register. If a struct or union, and if
3266 the remaining length is smaller than the register
3267 size, we have to adjust the register value on
3268 big endian targets.
3269
3270 It does not seem to be necessary to do the
3271 same for integral types.
3272
3273 cagney/2001-07-23: gdb/179: Also, GCC, when
3274 outputting LE O32 with sizeof (struct) <
3275 MIPS_SAVED_REGSIZE, generates a left shift as
3276 part of storing the argument in a register a
3277 register (the left shift isn't generated when
3278 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3279 is quite possible that this is GCC contradicting
3280 the LE/O32 ABI, GDB has not been adjusted to
3281 accommodate this. Either someone needs to
3282 demonstrate that the LE/O32 ABI specifies such a
3283 left shift OR this new ABI gets identified as
3284 such and GDB gets tweaked accordingly. */
3285
3286 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3287 && partial_len < MIPS_SAVED_REGSIZE
3288 && (typecode == TYPE_CODE_STRUCT ||
3289 typecode == TYPE_CODE_UNION))
3290 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3291 TARGET_CHAR_BIT);
3292
3293 if (mips_debug)
3294 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3295 argreg,
3296 phex (regval, MIPS_SAVED_REGSIZE));
3297 write_register (argreg, regval);
3298 argreg++;
3299 }
3300
3301 len -= partial_len;
3302 val += partial_len;
3303
3304 /* Compute the the offset into the stack at which we
3305 will copy the next parameter.
3306
3307 In N32 (N64?), the stack_offset only needs to be
3308 adjusted when it has been used. */
3309
3310 if (stack_used_p)
5b03f266 3311 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
cb3d25d1
MS
3312 }
3313 }
3314 if (mips_debug)
3315 fprintf_unfiltered (gdb_stdlog, "\n");
3316 }
3317
310e9b6a
AC
3318 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3319
cb3d25d1
MS
3320 /* Return adjusted stack pointer. */
3321 return sp;
3322}
3323
25ab4790 3324/* O32 version of push_dummy_call. */
ebafbe83 3325
46cac009 3326static CORE_ADDR
25ab4790
AC
3327mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3328 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3329 struct value **args, CORE_ADDR sp, int struct_return,
3330 CORE_ADDR struct_addr)
ebafbe83
MS
3331{
3332 int argreg;
3333 int float_argreg;
3334 int argnum;
3335 int len = 0;
3336 int stack_offset = 0;
ebafbe83 3337
25ab4790
AC
3338 /* For shared libraries, "t9" needs to point at the function
3339 address. */
3340 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3341
3342 /* Set the return address register to point to the entry point of
3343 the program, where a breakpoint lies in wait. */
3344 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3345
ebafbe83
MS
3346 /* First ensure that the stack and structure return address (if any)
3347 are properly aligned. The stack has to be at least 64-bit
3348 aligned even on 32-bit machines, because doubles must be 64-bit
3349 aligned. For n32 and n64, stack frames need to be 128-bit
3350 aligned, so we round to this widest known alignment. */
3351
5b03f266
AC
3352 sp = align_down (sp, 16);
3353 struct_addr = align_down (struct_addr, 16);
ebafbe83
MS
3354
3355 /* Now make space on the stack for the args. */
3356 for (argnum = 0; argnum < nargs; argnum++)
5b03f266 3357 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
ebafbe83 3358 MIPS_STACK_ARGSIZE);
5b03f266 3359 sp -= align_up (len, 16);
ebafbe83
MS
3360
3361 if (mips_debug)
3362 fprintf_unfiltered (gdb_stdlog,
5b03f266
AC
3363 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3364 paddr_nz (sp), (long) align_up (len, 16));
ebafbe83
MS
3365
3366 /* Initialize the integer and float register pointers. */
3367 argreg = A0_REGNUM;
3368 float_argreg = FPA0_REGNUM;
3369
bcb0cc15 3370 /* The struct_return pointer occupies the first parameter-passing reg. */
ebafbe83
MS
3371 if (struct_return)
3372 {
3373 if (mips_debug)
3374 fprintf_unfiltered (gdb_stdlog,
25ab4790 3375 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
ebafbe83
MS
3376 argreg, paddr_nz (struct_addr));
3377 write_register (argreg++, struct_addr);
3378 stack_offset += MIPS_STACK_ARGSIZE;
3379 }
3380
3381 /* Now load as many as possible of the first arguments into
3382 registers, and push the rest onto the stack. Loop thru args
3383 from first to last. */
3384 for (argnum = 0; argnum < nargs; argnum++)
3385 {
3386 char *val;
d9d9c31f 3387 char valbuf[MAX_REGISTER_SIZE];
ebafbe83
MS
3388 struct value *arg = args[argnum];
3389 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3390 int len = TYPE_LENGTH (arg_type);
3391 enum type_code typecode = TYPE_CODE (arg_type);
3392
3393 if (mips_debug)
3394 fprintf_unfiltered (gdb_stdlog,
25ab4790 3395 "mips_o32_push_dummy_call: %d len=%d type=%d",
46cac009
AC
3396 argnum + 1, len, (int) typecode);
3397
3398 val = (char *) VALUE_CONTENTS (arg);
3399
3400 /* 32-bit ABIs always start floating point arguments in an
3401 even-numbered floating point register. Round the FP register
3402 up before the check to see if there are any FP registers
3403 left. O32/O64 targets also pass the FP in the integer
3404 registers so also round up normal registers. */
3405 if (!FP_REGISTER_DOUBLE
3406 && fp_register_arg_p (typecode, arg_type))
3407 {
3408 if ((float_argreg & 1))
3409 float_argreg++;
3410 }
3411
3412 /* Floating point arguments passed in registers have to be
3413 treated specially. On 32-bit architectures, doubles
3414 are passed in register pairs; the even register gets
3415 the low word, and the odd register gets the high word.
3416 On O32/O64, the first two floating point arguments are
3417 also copied to general registers, because MIPS16 functions
3418 don't use float registers for arguments. This duplication of
3419 arguments in general registers can't hurt non-MIPS16 functions
3420 because those registers are normally skipped. */
3421
3422 if (fp_register_arg_p (typecode, arg_type)
3423 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3424 {
3425 if (!FP_REGISTER_DOUBLE && len == 8)
3426 {
3427 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3428 unsigned long regval;
3429
3430 /* Write the low word of the double to the even register(s). */
3431 regval = extract_unsigned_integer (val + low_offset, 4);
3432 if (mips_debug)
3433 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3434 float_argreg, phex (regval, 4));
3435 write_register (float_argreg++, regval);
3436 if (mips_debug)
3437 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3438 argreg, phex (regval, 4));
3439 write_register (argreg++, regval);
3440
3441 /* Write the high word of the double to the odd register(s). */
3442 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3443 if (mips_debug)
3444 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3445 float_argreg, phex (regval, 4));
3446 write_register (float_argreg++, regval);
3447
3448 if (mips_debug)
3449 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3450 argreg, phex (regval, 4));
3451 write_register (argreg++, regval);
3452 }
3453 else
3454 {
3455 /* This is a floating point value that fits entirely
3456 in a single register. */
3457 /* On 32 bit ABI's the float_argreg is further adjusted
3458 above to ensure that it is even register aligned. */
3459 LONGEST regval = extract_unsigned_integer (val, len);
3460 if (mips_debug)
3461 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3462 float_argreg, phex (regval, len));
3463 write_register (float_argreg++, regval);
3464 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3465 registers for each argument. The below is (my
3466 guess) to ensure that the corresponding integer
3467 register has reserved the same space. */
3468 if (mips_debug)
3469 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3470 argreg, phex (regval, len));
3471 write_register (argreg, regval);
3472 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3473 }
3474 /* Reserve space for the FP register. */
5b03f266 3475 stack_offset += align_up (len, MIPS_STACK_ARGSIZE);
46cac009
AC
3476 }
3477 else
3478 {
3479 /* Copy the argument to general registers or the stack in
3480 register-sized pieces. Large arguments are split between
3481 registers and stack. */
3482 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3483 are treated specially: Irix cc passes them in registers
3484 where gcc sometimes puts them on the stack. For maximum
3485 compatibility, we will put them in both places. */
3486 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3487 (len % MIPS_SAVED_REGSIZE != 0));
3488 /* Structures should be aligned to eight bytes (even arg registers)
3489 on MIPS_ABI_O32, if their first member has double precision. */
3490 if (MIPS_SAVED_REGSIZE < 8
3491 && mips_type_needs_double_align (arg_type))
3492 {
3493 if ((argreg & 1))
3494 argreg++;
3495 }
3496 /* Note: Floating-point values that didn't fit into an FP
3497 register are only written to memory. */
3498 while (len > 0)
3499 {
3500 /* Remember if the argument was written to the stack. */
3501 int stack_used_p = 0;
3502 int partial_len =
3503 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3504
3505 if (mips_debug)
3506 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3507 partial_len);
3508
3509 /* Write this portion of the argument to the stack. */
3510 if (argreg > MIPS_LAST_ARG_REGNUM
3511 || odd_sized_struct
3512 || fp_register_arg_p (typecode, arg_type))
3513 {
3514 /* Should shorter than int integer values be
3515 promoted to int before being stored? */
3516 int longword_offset = 0;
3517 CORE_ADDR addr;
3518 stack_used_p = 1;
3519 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3520 {
3521 if (MIPS_STACK_ARGSIZE == 8 &&
3522 (typecode == TYPE_CODE_INT ||
3523 typecode == TYPE_CODE_PTR ||
3524 typecode == TYPE_CODE_FLT) && len <= 4)
3525 longword_offset = MIPS_STACK_ARGSIZE - len;
3526 }
3527
3528 if (mips_debug)
3529 {
3530 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3531 paddr_nz (stack_offset));
3532 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3533 paddr_nz (longword_offset));
3534 }
3535
3536 addr = sp + stack_offset + longword_offset;
3537
3538 if (mips_debug)
3539 {
3540 int i;
3541 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3542 paddr_nz (addr));
3543 for (i = 0; i < partial_len; i++)
3544 {
3545 fprintf_unfiltered (gdb_stdlog, "%02x",
3546 val[i] & 0xff);
3547 }
3548 }
3549 write_memory (addr, val, partial_len);
3550 }
3551
3552 /* Note!!! This is NOT an else clause. Odd sized
3553 structs may go thru BOTH paths. Floating point
3554 arguments will not. */
3555 /* Write this portion of the argument to a general
3556 purpose register. */
3557 if (argreg <= MIPS_LAST_ARG_REGNUM
3558 && !fp_register_arg_p (typecode, arg_type))
3559 {
3560 LONGEST regval = extract_signed_integer (val, partial_len);
3561 /* Value may need to be sign extended, because
3562 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3563
3564 /* A non-floating-point argument being passed in a
3565 general register. If a struct or union, and if
3566 the remaining length is smaller than the register
3567 size, we have to adjust the register value on
3568 big endian targets.
3569
3570 It does not seem to be necessary to do the
3571 same for integral types.
3572
3573 Also don't do this adjustment on O64 binaries.
3574
3575 cagney/2001-07-23: gdb/179: Also, GCC, when
3576 outputting LE O32 with sizeof (struct) <
3577 MIPS_SAVED_REGSIZE, generates a left shift as
3578 part of storing the argument in a register a
3579 register (the left shift isn't generated when
3580 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3581 is quite possible that this is GCC contradicting
3582 the LE/O32 ABI, GDB has not been adjusted to
3583 accommodate this. Either someone needs to
3584 demonstrate that the LE/O32 ABI specifies such a
3585 left shift OR this new ABI gets identified as
3586 such and GDB gets tweaked accordingly. */
3587
3588 if (MIPS_SAVED_REGSIZE < 8
3589 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3590 && partial_len < MIPS_SAVED_REGSIZE
3591 && (typecode == TYPE_CODE_STRUCT ||
3592 typecode == TYPE_CODE_UNION))
3593 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3594 TARGET_CHAR_BIT);
3595
3596 if (mips_debug)
3597 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3598 argreg,
3599 phex (regval, MIPS_SAVED_REGSIZE));
3600 write_register (argreg, regval);
3601 argreg++;
3602
3603 /* Prevent subsequent floating point arguments from
3604 being passed in floating point registers. */
3605 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3606 }
3607
3608 len -= partial_len;
3609 val += partial_len;
3610
3611 /* Compute the the offset into the stack at which we
3612 will copy the next parameter.
3613
3614 In older ABIs, the caller reserved space for
3615 registers that contained arguments. This was loosely
3616 refered to as their "home". Consequently, space is
3617 always allocated. */
3618
5b03f266 3619 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
46cac009
AC
3620 }
3621 }
3622 if (mips_debug)
3623 fprintf_unfiltered (gdb_stdlog, "\n");
3624 }
3625
310e9b6a
AC
3626 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3627
46cac009
AC
3628 /* Return adjusted stack pointer. */
3629 return sp;
3630}
3631
25ab4790 3632/* O64 version of push_dummy_call. */
46cac009
AC
3633
3634static CORE_ADDR
25ab4790
AC
3635mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3636 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3637 struct value **args, CORE_ADDR sp, int struct_return,
3638 CORE_ADDR struct_addr)
46cac009
AC
3639{
3640 int argreg;
3641 int float_argreg;
3642 int argnum;
3643 int len = 0;
3644 int stack_offset = 0;
3645
25ab4790
AC
3646 /* For shared libraries, "t9" needs to point at the function
3647 address. */
3648 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3649
3650 /* Set the return address register to point to the entry point of
3651 the program, where a breakpoint lies in wait. */
3652 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3653
46cac009
AC
3654 /* First ensure that the stack and structure return address (if any)
3655 are properly aligned. The stack has to be at least 64-bit
3656 aligned even on 32-bit machines, because doubles must be 64-bit
3657 aligned. For n32 and n64, stack frames need to be 128-bit
3658 aligned, so we round to this widest known alignment. */
3659
5b03f266
AC
3660 sp = align_down (sp, 16);
3661 struct_addr = align_down (struct_addr, 16);
46cac009
AC
3662
3663 /* Now make space on the stack for the args. */
3664 for (argnum = 0; argnum < nargs; argnum++)
5b03f266 3665 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
46cac009 3666 MIPS_STACK_ARGSIZE);
5b03f266 3667 sp -= align_up (len, 16);
46cac009
AC
3668
3669 if (mips_debug)
3670 fprintf_unfiltered (gdb_stdlog,
5b03f266
AC
3671 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3672 paddr_nz (sp), (long) align_up (len, 16));
46cac009
AC
3673
3674 /* Initialize the integer and float register pointers. */
3675 argreg = A0_REGNUM;
3676 float_argreg = FPA0_REGNUM;
3677
3678 /* The struct_return pointer occupies the first parameter-passing reg. */
3679 if (struct_return)
3680 {
3681 if (mips_debug)
3682 fprintf_unfiltered (gdb_stdlog,
25ab4790 3683 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
46cac009
AC
3684 argreg, paddr_nz (struct_addr));
3685 write_register (argreg++, struct_addr);
3686 stack_offset += MIPS_STACK_ARGSIZE;
3687 }
3688
3689 /* Now load as many as possible of the first arguments into
3690 registers, and push the rest onto the stack. Loop thru args
3691 from first to last. */
3692 for (argnum = 0; argnum < nargs; argnum++)
3693 {
3694 char *val;
d9d9c31f 3695 char valbuf[MAX_REGISTER_SIZE];
46cac009
AC
3696 struct value *arg = args[argnum];
3697 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3698 int len = TYPE_LENGTH (arg_type);
3699 enum type_code typecode = TYPE_CODE (arg_type);
3700
3701 if (mips_debug)
3702 fprintf_unfiltered (gdb_stdlog,
25ab4790 3703 "mips_o64_push_dummy_call: %d len=%d type=%d",
ebafbe83
MS
3704 argnum + 1, len, (int) typecode);
3705
3706 val = (char *) VALUE_CONTENTS (arg);
3707
3708 /* 32-bit ABIs always start floating point arguments in an
3709 even-numbered floating point register. Round the FP register
3710 up before the check to see if there are any FP registers
3711 left. O32/O64 targets also pass the FP in the integer
3712 registers so also round up normal registers. */
3713 if (!FP_REGISTER_DOUBLE
3714 && fp_register_arg_p (typecode, arg_type))
3715 {
3716 if ((float_argreg & 1))
3717 float_argreg++;
3718 }
3719
3720 /* Floating point arguments passed in registers have to be
3721 treated specially. On 32-bit architectures, doubles
3722 are passed in register pairs; the even register gets
3723 the low word, and the odd register gets the high word.
3724 On O32/O64, the first two floating point arguments are
3725 also copied to general registers, because MIPS16 functions
3726 don't use float registers for arguments. This duplication of
3727 arguments in general registers can't hurt non-MIPS16 functions
3728 because those registers are normally skipped. */
3729
3730 if (fp_register_arg_p (typecode, arg_type)
3731 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3732 {
3733 if (!FP_REGISTER_DOUBLE && len == 8)
3734 {
3735 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3736 unsigned long regval;
3737
3738 /* Write the low word of the double to the even register(s). */
3739 regval = extract_unsigned_integer (val + low_offset, 4);
3740 if (mips_debug)
3741 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3742 float_argreg, phex (regval, 4));
3743 write_register (float_argreg++, regval);
3744 if (mips_debug)
3745 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3746 argreg, phex (regval, 4));
3747 write_register (argreg++, regval);
3748
3749 /* Write the high word of the double to the odd register(s). */
3750 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3751 if (mips_debug)
3752 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3753 float_argreg, phex (regval, 4));
3754 write_register (float_argreg++, regval);
3755
3756 if (mips_debug)
3757 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3758 argreg, phex (regval, 4));
3759 write_register (argreg++, regval);
3760 }
3761 else
3762 {
3763 /* This is a floating point value that fits entirely
3764 in a single register. */
3765 /* On 32 bit ABI's the float_argreg is further adjusted
3766 above to ensure that it is even register aligned. */
3767 LONGEST regval = extract_unsigned_integer (val, len);
3768 if (mips_debug)
3769 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3770 float_argreg, phex (regval, len));
3771 write_register (float_argreg++, regval);
3772 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3773 registers for each argument. The below is (my
3774 guess) to ensure that the corresponding integer
3775 register has reserved the same space. */
3776 if (mips_debug)
3777 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3778 argreg, phex (regval, len));
3779 write_register (argreg, regval);
3780 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3781 }
3782 /* Reserve space for the FP register. */
5b03f266 3783 stack_offset += align_up (len, MIPS_STACK_ARGSIZE);
ebafbe83
MS
3784 }
3785 else
3786 {
3787 /* Copy the argument to general registers or the stack in
3788 register-sized pieces. Large arguments are split between
3789 registers and stack. */
3790 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3791 are treated specially: Irix cc passes them in registers
3792 where gcc sometimes puts them on the stack. For maximum
3793 compatibility, we will put them in both places. */
3794 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3795 (len % MIPS_SAVED_REGSIZE != 0));
3796 /* Structures should be aligned to eight bytes (even arg registers)
3797 on MIPS_ABI_O32, if their first member has double precision. */
3798 if (MIPS_SAVED_REGSIZE < 8
3799 && mips_type_needs_double_align (arg_type))
3800 {
3801 if ((argreg & 1))
3802 argreg++;
3803 }
3804 /* Note: Floating-point values that didn't fit into an FP
3805 register are only written to memory. */
3806 while (len > 0)
3807 {
3808 /* Remember if the argument was written to the stack. */
3809 int stack_used_p = 0;
3810 int partial_len =
3811 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3812
3813 if (mips_debug)
3814 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3815 partial_len);
3816
3817 /* Write this portion of the argument to the stack. */
3818 if (argreg > MIPS_LAST_ARG_REGNUM
3819 || odd_sized_struct
3820 || fp_register_arg_p (typecode, arg_type))
3821 {
3822 /* Should shorter than int integer values be
3823 promoted to int before being stored? */
3824 int longword_offset = 0;
3825 CORE_ADDR addr;
3826 stack_used_p = 1;
3827 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3828 {
3829 if (MIPS_STACK_ARGSIZE == 8 &&
3830 (typecode == TYPE_CODE_INT ||
3831 typecode == TYPE_CODE_PTR ||
3832 typecode == TYPE_CODE_FLT) && len <= 4)
3833 longword_offset = MIPS_STACK_ARGSIZE - len;
3834 }
3835
3836 if (mips_debug)
3837 {
3838 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3839 paddr_nz (stack_offset));
3840 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3841 paddr_nz (longword_offset));
3842 }
3843
3844 addr = sp + stack_offset + longword_offset;
3845
3846 if (mips_debug)
3847 {
3848 int i;
3849 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3850 paddr_nz (addr));
3851 for (i = 0; i < partial_len; i++)
3852 {
3853 fprintf_unfiltered (gdb_stdlog, "%02x",
3854 val[i] & 0xff);
3855 }
3856 }
3857 write_memory (addr, val, partial_len);
3858 }
3859
3860 /* Note!!! This is NOT an else clause. Odd sized
3861 structs may go thru BOTH paths. Floating point
3862 arguments will not. */
3863 /* Write this portion of the argument to a general
3864 purpose register. */
3865 if (argreg <= MIPS_LAST_ARG_REGNUM
3866 && !fp_register_arg_p (typecode, arg_type))
3867 {
3868 LONGEST regval = extract_signed_integer (val, partial_len);
3869 /* Value may need to be sign extended, because
3870 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3871
3872 /* A non-floating-point argument being passed in a
3873 general register. If a struct or union, and if
3874 the remaining length is smaller than the register
3875 size, we have to adjust the register value on
3876 big endian targets.
3877
3878 It does not seem to be necessary to do the
3879 same for integral types.
3880
3881 Also don't do this adjustment on O64 binaries.
3882
3883 cagney/2001-07-23: gdb/179: Also, GCC, when
3884 outputting LE O32 with sizeof (struct) <
3885 MIPS_SAVED_REGSIZE, generates a left shift as
3886 part of storing the argument in a register a
3887 register (the left shift isn't generated when
3888 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3889 is quite possible that this is GCC contradicting
3890 the LE/O32 ABI, GDB has not been adjusted to
3891 accommodate this. Either someone needs to
3892 demonstrate that the LE/O32 ABI specifies such a
3893 left shift OR this new ABI gets identified as
3894 such and GDB gets tweaked accordingly. */
3895
3896 if (MIPS_SAVED_REGSIZE < 8
3897 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3898 && partial_len < MIPS_SAVED_REGSIZE
3899 && (typecode == TYPE_CODE_STRUCT ||
3900 typecode == TYPE_CODE_UNION))
3901 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3902 TARGET_CHAR_BIT);
3903
3904 if (mips_debug)
3905 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3906 argreg,
3907 phex (regval, MIPS_SAVED_REGSIZE));
3908 write_register (argreg, regval);
3909 argreg++;
3910
3911 /* Prevent subsequent floating point arguments from
3912 being passed in floating point registers. */
3913 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3914 }
3915
3916 len -= partial_len;
3917 val += partial_len;
3918
3919 /* Compute the the offset into the stack at which we
3920 will copy the next parameter.
3921
3922 In older ABIs, the caller reserved space for
3923 registers that contained arguments. This was loosely
3924 refered to as their "home". Consequently, space is
3925 always allocated. */
3926
5b03f266 3927 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
ebafbe83
MS
3928 }
3929 }
3930 if (mips_debug)
3931 fprintf_unfiltered (gdb_stdlog, "\n");
3932 }
3933
310e9b6a
AC
3934 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3935
ebafbe83
MS
3936 /* Return adjusted stack pointer. */
3937 return sp;
3938}
3939
f7ab6ec6 3940static void
acdb74a0 3941mips_pop_frame (void)
c906108c 3942{
52f0bd74 3943 int regnum;
c906108c 3944 struct frame_info *frame = get_current_frame ();
c193f6ac 3945 CORE_ADDR new_sp = get_frame_base (frame);
e227b13c 3946 mips_extra_func_info_t proc_desc;
c906108c 3947
50abf9e5 3948 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
cedea778
AC
3949 {
3950 generic_pop_dummy_frame ();
3951 flush_cached_frames ();
3952 return;
3953 }
3954
e227b13c 3955 proc_desc = get_frame_extra_info (frame)->proc_desc;
8bedc050 3956 write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame));
e0f7ec59 3957 mips_find_saved_regs (frame);
c906108c 3958 for (regnum = 0; regnum < NUM_REGS; regnum++)
21f87145 3959 if (regnum != SP_REGNUM && regnum != PC_REGNUM
1b1d3794 3960 && deprecated_get_frame_saved_regs (frame)[regnum])
21f87145
MS
3961 {
3962 /* Floating point registers must not be sign extended,
3963 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3964
3965 if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32)
3966 write_register (regnum,
1b1d3794 3967 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum],
21f87145
MS
3968 MIPS_SAVED_REGSIZE));
3969 else
3970 write_register (regnum,
1b1d3794 3971 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
21f87145
MS
3972 MIPS_SAVED_REGSIZE));
3973 }
757a7cc6 3974
c906108c
SS
3975 write_register (SP_REGNUM, new_sp);
3976 flush_cached_frames ();
3977
c5aa993b 3978 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
c906108c
SS
3979 {
3980 struct linked_proc_info *pi_ptr, *prev_ptr;
3981
3982 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3983 pi_ptr != NULL;
3984 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3985 {
3986 if (&pi_ptr->info == proc_desc)
3987 break;
3988 }
3989
3990 if (pi_ptr == NULL)
3991 error ("Can't locate dummy extra frame info\n");
3992
3993 if (prev_ptr != NULL)
3994 prev_ptr->next = pi_ptr->next;
3995 else
3996 linked_proc_desc_table = pi_ptr->next;
3997
b8c9b27d 3998 xfree (pi_ptr);
c906108c
SS
3999
4000 write_register (HI_REGNUM,
c5aa993b 4001 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
7a292a7a 4002 MIPS_SAVED_REGSIZE));
c906108c 4003 write_register (LO_REGNUM,
c5aa993b 4004 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
7a292a7a 4005 MIPS_SAVED_REGSIZE));
c906108c
SS
4006 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
4007 write_register (FCRCS_REGNUM,
c5aa993b 4008 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
7a292a7a 4009 MIPS_SAVED_REGSIZE));
c906108c
SS
4010 }
4011}
4012
dd824b04
DJ
4013/* Floating point register management.
4014
4015 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4016 64bit operations, these early MIPS cpus treat fp register pairs
4017 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4018 registers and offer a compatibility mode that emulates the MIPS2 fp
4019 model. When operating in MIPS2 fp compat mode, later cpu's split
4020 double precision floats into two 32-bit chunks and store them in
4021 consecutive fp regs. To display 64-bit floats stored in this
4022 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4023 Throw in user-configurable endianness and you have a real mess.
4024
4025 The way this works is:
4026 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4027 double-precision value will be split across two logical registers.
4028 The lower-numbered logical register will hold the low-order bits,
4029 regardless of the processor's endianness.
4030 - If we are on a 64-bit processor, and we are looking for a
4031 single-precision value, it will be in the low ordered bits
4032 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4033 save slot in memory.
4034 - If we are in 64-bit mode, everything is straightforward.
4035
4036 Note that this code only deals with "live" registers at the top of the
4037 stack. We will attempt to deal with saved registers later, when
4038 the raw/cooked register interface is in place. (We need a general
4039 interface that can deal with dynamic saved register sizes -- fp
4040 regs could be 32 bits wide in one frame and 64 on the frame above
4041 and below). */
4042
67b2c998
DJ
4043static struct type *
4044mips_float_register_type (void)
4045{
361d1df0 4046 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
67b2c998
DJ
4047 return builtin_type_ieee_single_big;
4048 else
4049 return builtin_type_ieee_single_little;
4050}
4051
4052static struct type *
4053mips_double_register_type (void)
4054{
361d1df0 4055 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
67b2c998
DJ
4056 return builtin_type_ieee_double_big;
4057 else
4058 return builtin_type_ieee_double_little;
4059}
4060
dd824b04
DJ
4061/* Copy a 32-bit single-precision value from the current frame
4062 into rare_buffer. */
4063
4064static void
e11c53d2
AC
4065mips_read_fp_register_single (struct frame_info *frame, int regno,
4066 char *rare_buffer)
dd824b04
DJ
4067{
4068 int raw_size = REGISTER_RAW_SIZE (regno);
4069 char *raw_buffer = alloca (raw_size);
4070
e11c53d2 4071 if (!frame_register_read (frame, regno, raw_buffer))
dd824b04
DJ
4072 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4073 if (raw_size == 8)
4074 {
4075 /* We have a 64-bit value for this register. Find the low-order
4076 32 bits. */
4077 int offset;
4078
4079 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4080 offset = 4;
4081 else
4082 offset = 0;
4083
4084 memcpy (rare_buffer, raw_buffer + offset, 4);
4085 }
4086 else
4087 {
4088 memcpy (rare_buffer, raw_buffer, 4);
4089 }
4090}
4091
4092/* Copy a 64-bit double-precision value from the current frame into
4093 rare_buffer. This may include getting half of it from the next
4094 register. */
4095
4096static void
e11c53d2
AC
4097mips_read_fp_register_double (struct frame_info *frame, int regno,
4098 char *rare_buffer)
dd824b04
DJ
4099{
4100 int raw_size = REGISTER_RAW_SIZE (regno);
4101
4102 if (raw_size == 8 && !mips2_fp_compat ())
4103 {
4104 /* We have a 64-bit value for this register, and we should use
4105 all 64 bits. */
e11c53d2 4106 if (!frame_register_read (frame, regno, rare_buffer))
dd824b04
DJ
4107 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4108 }
4109 else
4110 {
4111 if ((regno - FP0_REGNUM) & 1)
4112 internal_error (__FILE__, __LINE__,
4113 "mips_read_fp_register_double: bad access to "
4114 "odd-numbered FP register");
4115
4116 /* mips_read_fp_register_single will find the correct 32 bits from
4117 each register. */
4118 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4119 {
e11c53d2
AC
4120 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4121 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
dd824b04 4122 }
361d1df0 4123 else
dd824b04 4124 {
e11c53d2
AC
4125 mips_read_fp_register_single (frame, regno, rare_buffer);
4126 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
dd824b04
DJ
4127 }
4128 }
4129}
4130
c906108c 4131static void
e11c53d2
AC
4132mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4133 int regnum)
c5aa993b 4134{ /* do values for FP (float) regs */
dd824b04 4135 char *raw_buffer;
c906108c 4136 double doub, flt1, flt2; /* doubles extracted from raw hex data */
f0ef6b29 4137 int inv1, inv2, namelen;
c5aa993b 4138
dd824b04 4139 raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
c906108c 4140
e11c53d2
AC
4141 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
4142 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
4143 "");
f0ef6b29 4144
dd824b04 4145 if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
c906108c 4146 {
f0ef6b29
KB
4147 /* 4-byte registers: Print hex and floating. Also print even
4148 numbered registers as doubles. */
e11c53d2 4149 mips_read_fp_register_single (frame, regnum, raw_buffer);
67b2c998 4150 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
c5aa993b 4151
e11c53d2 4152 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file);
dd824b04 4153
e11c53d2 4154 fprintf_filtered (file, " flt: ");
1adad886 4155 if (inv1)
e11c53d2 4156 fprintf_filtered (file, " <invalid float> ");
1adad886 4157 else
e11c53d2 4158 fprintf_filtered (file, "%-17.9g", flt1);
1adad886 4159
f0ef6b29
KB
4160 if (regnum % 2 == 0)
4161 {
e11c53d2 4162 mips_read_fp_register_double (frame, regnum, raw_buffer);
f0ef6b29
KB
4163 doub = unpack_double (mips_double_register_type (), raw_buffer,
4164 &inv2);
1adad886 4165
e11c53d2 4166 fprintf_filtered (file, " dbl: ");
f0ef6b29 4167 if (inv2)
e11c53d2 4168 fprintf_filtered (file, "<invalid double>");
f0ef6b29 4169 else
e11c53d2 4170 fprintf_filtered (file, "%-24.17g", doub);
f0ef6b29 4171 }
c906108c
SS
4172 }
4173 else
dd824b04 4174 {
f0ef6b29 4175 /* Eight byte registers: print each one as hex, float and double. */
e11c53d2 4176 mips_read_fp_register_single (frame, regnum, raw_buffer);
2f38ef89 4177 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
c906108c 4178
e11c53d2 4179 mips_read_fp_register_double (frame, regnum, raw_buffer);
f0ef6b29
KB
4180 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4181
361d1df0 4182
e11c53d2 4183 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file);
f0ef6b29 4184
e11c53d2 4185 fprintf_filtered (file, " flt: ");
1adad886 4186 if (inv1)
e11c53d2 4187 fprintf_filtered (file, "<invalid float>");
1adad886 4188 else
e11c53d2 4189 fprintf_filtered (file, "%-17.9g", flt1);
1adad886 4190
e11c53d2 4191 fprintf_filtered (file, " dbl: ");
f0ef6b29 4192 if (inv2)
e11c53d2 4193 fprintf_filtered (file, "<invalid double>");
1adad886 4194 else
e11c53d2 4195 fprintf_filtered (file, "%-24.17g", doub);
f0ef6b29
KB
4196 }
4197}
4198
4199static void
e11c53d2
AC
4200mips_print_register (struct ui_file *file, struct frame_info *frame,
4201 int regnum, int all)
f0ef6b29 4202{
a4b8ebc8 4203 struct gdbarch *gdbarch = get_frame_arch (frame);
d9d9c31f 4204 char raw_buffer[MAX_REGISTER_SIZE];
f0ef6b29 4205 int offset;
1adad886 4206
a4b8ebc8 4207 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
f0ef6b29 4208 {
e11c53d2 4209 mips_print_fp_register (file, frame, regnum);
f0ef6b29
KB
4210 return;
4211 }
4212
4213 /* Get the data in raw format. */
e11c53d2 4214 if (!frame_register_read (frame, regnum, raw_buffer))
f0ef6b29 4215 {
e11c53d2 4216 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
f0ef6b29 4217 return;
c906108c 4218 }
f0ef6b29 4219
e11c53d2 4220 fputs_filtered (REGISTER_NAME (regnum), file);
f0ef6b29
KB
4221
4222 /* The problem with printing numeric register names (r26, etc.) is that
4223 the user can't use them on input. Probably the best solution is to
4224 fix it so that either the numeric or the funky (a2, etc.) names
4225 are accepted on input. */
4226 if (regnum < MIPS_NUMREGS)
e11c53d2 4227 fprintf_filtered (file, "(r%d): ", regnum);
f0ef6b29 4228 else
e11c53d2 4229 fprintf_filtered (file, ": ");
f0ef6b29
KB
4230
4231 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4232 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4233 else
4234 offset = 0;
4235
a4b8ebc8 4236 print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum),
e11c53d2 4237 'x', 0, file);
c906108c
SS
4238}
4239
f0ef6b29
KB
4240/* Replacement for generic do_registers_info.
4241 Print regs in pretty columns. */
4242
4243static int
e11c53d2
AC
4244print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4245 int regnum)
f0ef6b29 4246{
e11c53d2
AC
4247 fprintf_filtered (file, " ");
4248 mips_print_fp_register (file, frame, regnum);
4249 fprintf_filtered (file, "\n");
f0ef6b29
KB
4250 return regnum + 1;
4251}
4252
4253
c906108c
SS
4254/* Print a row's worth of GP (int) registers, with name labels above */
4255
4256static int
e11c53d2 4257print_gp_register_row (struct ui_file *file, struct frame_info *frame,
a4b8ebc8 4258 int start_regnum)
c906108c 4259{
a4b8ebc8 4260 struct gdbarch *gdbarch = get_frame_arch (frame);
c906108c 4261 /* do values for GP (int) regs */
d9d9c31f 4262 char raw_buffer[MAX_REGISTER_SIZE];
c906108c
SS
4263 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
4264 int col, byte;
a4b8ebc8 4265 int regnum;
c906108c
SS
4266
4267 /* For GP registers, we print a separate row of names above the vals */
e11c53d2 4268 fprintf_filtered (file, " ");
a4b8ebc8
AC
4269 for (col = 0, regnum = start_regnum;
4270 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS;
4271 regnum++)
c906108c
SS
4272 {
4273 if (*REGISTER_NAME (regnum) == '\0')
c5aa993b 4274 continue; /* unused register */
a4b8ebc8 4275 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
c5aa993b 4276 break; /* end the row: reached FP register */
e11c53d2
AC
4277 fprintf_filtered (file, MIPS_REGSIZE == 8 ? "%17s" : "%9s",
4278 REGISTER_NAME (regnum));
c906108c
SS
4279 col++;
4280 }
a4b8ebc8 4281 /* print the R0 to R31 names */
20e6603c
AC
4282 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4283 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4284 else
4285 fprintf_filtered (file, "\n ");
c906108c 4286
c906108c 4287 /* now print the values in hex, 4 or 8 to the row */
a4b8ebc8
AC
4288 for (col = 0, regnum = start_regnum;
4289 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS;
4290 regnum++)
c906108c
SS
4291 {
4292 if (*REGISTER_NAME (regnum) == '\0')
c5aa993b 4293 continue; /* unused register */
a4b8ebc8 4294 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
c5aa993b 4295 break; /* end row: reached FP register */
c906108c 4296 /* OK: get the data in raw format. */
e11c53d2 4297 if (!frame_register_read (frame, regnum, raw_buffer))
c906108c
SS
4298 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4299 /* pad small registers */
43e526b9 4300 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
c906108c
SS
4301 printf_filtered (" ");
4302 /* Now print the register value in hex, endian order. */
d7449b42 4303 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
43e526b9
JM
4304 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
4305 byte < REGISTER_RAW_SIZE (regnum);
4306 byte++)
e11c53d2 4307 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
c906108c 4308 else
43e526b9
JM
4309 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
4310 byte >= 0;
4311 byte--)
e11c53d2
AC
4312 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4313 fprintf_filtered (file, " ");
c906108c
SS
4314 col++;
4315 }
c5aa993b 4316 if (col > 0) /* ie. if we actually printed anything... */
e11c53d2 4317 fprintf_filtered (file, "\n");
c906108c
SS
4318
4319 return regnum;
4320}
4321
4322/* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4323
bf1f5b4c 4324static void
e11c53d2
AC
4325mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4326 struct frame_info *frame, int regnum, int all)
c906108c 4327{
c5aa993b 4328 if (regnum != -1) /* do one specified register */
c906108c 4329 {
a4b8ebc8 4330 gdb_assert (regnum >= NUM_REGS);
c906108c
SS
4331 if (*(REGISTER_NAME (regnum)) == '\0')
4332 error ("Not a valid register for the current processor type");
4333
e11c53d2
AC
4334 mips_print_register (file, frame, regnum, 0);
4335 fprintf_filtered (file, "\n");
c906108c 4336 }
c5aa993b
JM
4337 else
4338 /* do all (or most) registers */
c906108c 4339 {
a4b8ebc8
AC
4340 regnum = NUM_REGS;
4341 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
c906108c 4342 {
a4b8ebc8 4343 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
e11c53d2
AC
4344 {
4345 if (all) /* true for "INFO ALL-REGISTERS" command */
4346 regnum = print_fp_register_row (file, frame, regnum);
4347 else
4348 regnum += MIPS_NUMREGS; /* skip floating point regs */
4349 }
c906108c 4350 else
e11c53d2 4351 regnum = print_gp_register_row (file, frame, regnum);
c906108c
SS
4352 }
4353 }
4354}
4355
c906108c
SS
4356/* Is this a branch with a delay slot? */
4357
a14ed312 4358static int is_delayed (unsigned long);
c906108c
SS
4359
4360static int
acdb74a0 4361is_delayed (unsigned long insn)
c906108c
SS
4362{
4363 int i;
4364 for (i = 0; i < NUMOPCODES; ++i)
4365 if (mips_opcodes[i].pinfo != INSN_MACRO
4366 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4367 break;
4368 return (i < NUMOPCODES
4369 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4370 | INSN_COND_BRANCH_DELAY
4371 | INSN_COND_BRANCH_LIKELY)));
4372}
4373
4374int
acdb74a0 4375mips_step_skips_delay (CORE_ADDR pc)
c906108c
SS
4376{
4377 char buf[MIPS_INSTLEN];
4378
4379 /* There is no branch delay slot on MIPS16. */
4380 if (pc_is_mips16 (pc))
4381 return 0;
4382
4383 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4384 /* If error reading memory, guess that it is not a delayed branch. */
4385 return 0;
c5aa993b 4386 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
c906108c
SS
4387}
4388
4389
4390/* Skip the PC past function prologue instructions (32-bit version).
4391 This is a helper function for mips_skip_prologue. */
4392
4393static CORE_ADDR
f7b9e9fc 4394mips32_skip_prologue (CORE_ADDR pc)
c906108c 4395{
c5aa993b
JM
4396 t_inst inst;
4397 CORE_ADDR end_pc;
4398 int seen_sp_adjust = 0;
4399 int load_immediate_bytes = 0;
4400
4401 /* Skip the typical prologue instructions. These are the stack adjustment
4402 instruction and the instructions that save registers on the stack
4403 or in the gcc frame. */
4404 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
4405 {
4406 unsigned long high_word;
c906108c 4407
c5aa993b
JM
4408 inst = mips_fetch_instruction (pc);
4409 high_word = (inst >> 16) & 0xffff;
c906108c 4410
c5aa993b
JM
4411 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4412 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4413 seen_sp_adjust = 1;
4414 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4415 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4416 seen_sp_adjust = 1;
4417 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4418 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4419 && (inst & 0x001F0000)) /* reg != $zero */
4420 continue;
4421
4422 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4423 continue;
4424 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4425 /* sx reg,n($s8) */
4426 continue; /* reg != $zero */
4427
4428 /* move $s8,$sp. With different versions of gas this will be either
4429 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4430 Accept any one of these. */
4431 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4432 continue;
4433
4434 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4435 continue;
4436 else if (high_word == 0x3c1c) /* lui $gp,n */
4437 continue;
4438 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4439 continue;
4440 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4441 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4442 continue;
4443 /* The following instructions load $at or $t0 with an immediate
4444 value in preparation for a stack adjustment via
4445 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4446 a local variable, so we accept them only before a stack adjustment
4447 instruction was seen. */
4448 else if (!seen_sp_adjust)
4449 {
4450 if (high_word == 0x3c01 || /* lui $at,n */
4451 high_word == 0x3c08) /* lui $t0,n */
4452 {
4453 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4454 continue;
4455 }
4456 else if (high_word == 0x3421 || /* ori $at,$at,n */
4457 high_word == 0x3508 || /* ori $t0,$t0,n */
4458 high_word == 0x3401 || /* ori $at,$zero,n */
4459 high_word == 0x3408) /* ori $t0,$zero,n */
4460 {
4461 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4462 continue;
4463 }
4464 else
4465 break;
4466 }
4467 else
4468 break;
c906108c
SS
4469 }
4470
c5aa993b
JM
4471 /* In a frameless function, we might have incorrectly
4472 skipped some load immediate instructions. Undo the skipping
4473 if the load immediate was not followed by a stack adjustment. */
4474 if (load_immediate_bytes && !seen_sp_adjust)
4475 pc -= load_immediate_bytes;
4476 return pc;
c906108c
SS
4477}
4478
4479/* Skip the PC past function prologue instructions (16-bit version).
4480 This is a helper function for mips_skip_prologue. */
4481
4482static CORE_ADDR
f7b9e9fc 4483mips16_skip_prologue (CORE_ADDR pc)
c906108c 4484{
c5aa993b
JM
4485 CORE_ADDR end_pc;
4486 int extend_bytes = 0;
4487 int prev_extend_bytes;
c906108c 4488
c5aa993b
JM
4489 /* Table of instructions likely to be found in a function prologue. */
4490 static struct
c906108c
SS
4491 {
4492 unsigned short inst;
4493 unsigned short mask;
c5aa993b
JM
4494 }
4495 table[] =
4496 {
c906108c 4497 {
c5aa993b
JM
4498 0x6300, 0xff00
4499 }
4500 , /* addiu $sp,offset */
4501 {
4502 0xfb00, 0xff00
4503 }
4504 , /* daddiu $sp,offset */
4505 {
4506 0xd000, 0xf800
4507 }
4508 , /* sw reg,n($sp) */
4509 {
4510 0xf900, 0xff00
4511 }
4512 , /* sd reg,n($sp) */
4513 {
4514 0x6200, 0xff00
4515 }
4516 , /* sw $ra,n($sp) */
4517 {
4518 0xfa00, 0xff00
4519 }
4520 , /* sd $ra,n($sp) */
4521 {
4522 0x673d, 0xffff
4523 }
4524 , /* move $s1,sp */
4525 {
4526 0xd980, 0xff80
4527 }
4528 , /* sw $a0-$a3,n($s1) */
4529 {
4530 0x6704, 0xff1c
4531 }
4532 , /* move reg,$a0-$a3 */
4533 {
4534 0xe809, 0xf81f
4535 }
4536 , /* entry pseudo-op */
4537 {
4538 0x0100, 0xff00
4539 }
4540 , /* addiu $s1,$sp,n */
4541 {
4542 0, 0
4543 } /* end of table marker */
4544 };
4545
4546 /* Skip the typical prologue instructions. These are the stack adjustment
4547 instruction and the instructions that save registers on the stack
4548 or in the gcc frame. */
4549 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
4550 {
4551 unsigned short inst;
4552 int i;
c906108c 4553
c5aa993b 4554 inst = mips_fetch_instruction (pc);
c906108c 4555
c5aa993b
JM
4556 /* Normally we ignore an extend instruction. However, if it is
4557 not followed by a valid prologue instruction, we must adjust
4558 the pc back over the extend so that it won't be considered
4559 part of the prologue. */
4560 if ((inst & 0xf800) == 0xf000) /* extend */
4561 {
4562 extend_bytes = MIPS16_INSTLEN;
4563 continue;
4564 }
4565 prev_extend_bytes = extend_bytes;
4566 extend_bytes = 0;
c906108c 4567
c5aa993b
JM
4568 /* Check for other valid prologue instructions besides extend. */
4569 for (i = 0; table[i].mask != 0; i++)
4570 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4571 break;
4572 if (table[i].mask != 0) /* it was in table? */
4573 continue; /* ignore it */
4574 else
4575 /* non-prologue */
4576 {
4577 /* Return the current pc, adjusted backwards by 2 if
4578 the previous instruction was an extend. */
4579 return pc - prev_extend_bytes;
4580 }
c906108c
SS
4581 }
4582 return pc;
4583}
4584
4585/* To skip prologues, I use this predicate. Returns either PC itself
4586 if the code at PC does not look like a function prologue; otherwise
4587 returns an address that (if we're lucky) follows the prologue. If
4588 LENIENT, then we must skip everything which is involved in setting
4589 up the frame (it's OK to skip more, just so long as we don't skip
4590 anything which might clobber the registers which are being saved.
4591 We must skip more in the case where part of the prologue is in the
4592 delay slot of a non-prologue instruction). */
4593
f7ab6ec6 4594static CORE_ADDR
f7b9e9fc 4595mips_skip_prologue (CORE_ADDR pc)
c906108c
SS
4596{
4597 /* See if we can determine the end of the prologue via the symbol table.
4598 If so, then return either PC, or the PC after the prologue, whichever
4599 is greater. */
4600
4601 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4602
4603 if (post_prologue_pc != 0)
4604 return max (pc, post_prologue_pc);
4605
4606 /* Can't determine prologue from the symbol table, need to examine
4607 instructions. */
4608
4609 if (pc_is_mips16 (pc))
f7b9e9fc 4610 return mips16_skip_prologue (pc);
c906108c 4611 else
f7b9e9fc 4612 return mips32_skip_prologue (pc);
c906108c 4613}
c906108c 4614
7a292a7a
SS
4615/* Determine how a return value is stored within the MIPS register
4616 file, given the return type `valtype'. */
4617
4618struct return_value_word
4619{
4620 int len;
4621 int reg;
4622 int reg_offset;
4623 int buf_offset;
4624};
4625
7a292a7a 4626static void
acdb74a0
AC
4627return_value_location (struct type *valtype,
4628 struct return_value_word *hi,
4629 struct return_value_word *lo)
7a292a7a
SS
4630{
4631 int len = TYPE_LENGTH (valtype);
c5aa993b 4632
7a292a7a
SS
4633 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4634 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4635 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4636 {
4637 if (!FP_REGISTER_DOUBLE && len == 8)
4638 {
4639 /* We need to break a 64bit float in two 32 bit halves and
c5aa993b 4640 spread them across a floating-point register pair. */
d7449b42
AC
4641 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4642 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4643 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
7a292a7a
SS
4644 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
4645 ? 4 : 0);
4646 hi->reg_offset = lo->reg_offset;
4647 lo->reg = FP0_REGNUM + 0;
4648 hi->reg = FP0_REGNUM + 1;
4649 lo->len = 4;
4650 hi->len = 4;
4651 }
4652 else
4653 {
4654 /* The floating point value fits in a single floating-point
c5aa993b 4655 register. */
d7449b42 4656 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
7a292a7a
SS
4657 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
4658 && len == 4)
4659 ? 4 : 0);
4660 lo->reg = FP0_REGNUM;
4661 lo->len = len;
4662 lo->buf_offset = 0;
4663 hi->len = 0;
4664 hi->reg_offset = 0;
4665 hi->buf_offset = 0;
4666 hi->reg = 0;
4667 }
4668 }
4669 else
4670 {
4671 /* Locate a result possibly spread across two registers. */
4672 int regnum = 2;
4673 lo->reg = regnum + 0;
4674 hi->reg = regnum + 1;
d7449b42 4675 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
7a292a7a
SS
4676 && len < MIPS_SAVED_REGSIZE)
4677 {
bf1f5b4c
MS
4678 /* "un-left-justify" the value in the low register */
4679 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
bcb0cc15 4680 lo->len = len;
bf1f5b4c 4681 hi->reg_offset = 0;
7a292a7a
SS
4682 hi->len = 0;
4683 }
d7449b42 4684 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
7a292a7a
SS
4685 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4686 && len < MIPS_SAVED_REGSIZE * 2
4687 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4688 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4689 {
4690 /* "un-left-justify" the value spread across two registers. */
4691 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4692 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4693 hi->reg_offset = 0;
4694 hi->len = len - lo->len;
4695 }
4696 else
4697 {
4698 /* Only perform a partial copy of the second register. */
4699 lo->reg_offset = 0;
4700 hi->reg_offset = 0;
4701 if (len > MIPS_SAVED_REGSIZE)
4702 {
4703 lo->len = MIPS_SAVED_REGSIZE;
4704 hi->len = len - MIPS_SAVED_REGSIZE;
4705 }
4706 else
4707 {
4708 lo->len = len;
4709 hi->len = 0;
4710 }
4711 }
d7449b42 4712 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
7a292a7a
SS
4713 && REGISTER_RAW_SIZE (regnum) == 8
4714 && MIPS_SAVED_REGSIZE == 4)
4715 {
4716 /* Account for the fact that only the least-signficant part
c5aa993b 4717 of the register is being used */
7a292a7a
SS
4718 lo->reg_offset += 4;
4719 hi->reg_offset += 4;
4720 }
4721 lo->buf_offset = 0;
4722 hi->buf_offset = lo->len;
4723 }
4724}
4725
4726/* Given a return value in `regbuf' with a type `valtype', extract and
4727 copy its value into `valbuf'. */
4728
46cac009
AC
4729static void
4730mips_eabi_extract_return_value (struct type *valtype,
b8b527c5 4731 char regbuf[],
46cac009
AC
4732 char *valbuf)
4733{
4734 struct return_value_word lo;
4735 struct return_value_word hi;
4736 return_value_location (valtype, &hi, &lo);
4737
4738 memcpy (valbuf + lo.buf_offset,
62700349 4739 regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset,
46cac009
AC
4740 lo.len);
4741
4742 if (hi.len > 0)
4743 memcpy (valbuf + hi.buf_offset,
62700349 4744 regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset,
46cac009
AC
4745 hi.len);
4746}
4747
46cac009
AC
4748static void
4749mips_o64_extract_return_value (struct type *valtype,
b8b527c5 4750 char regbuf[],
46cac009
AC
4751 char *valbuf)
4752{
4753 struct return_value_word lo;
4754 struct return_value_word hi;
4755 return_value_location (valtype, &hi, &lo);
4756
4757 memcpy (valbuf + lo.buf_offset,
62700349 4758 regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset,
46cac009
AC
4759 lo.len);
4760
4761 if (hi.len > 0)
4762 memcpy (valbuf + hi.buf_offset,
62700349 4763 regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset,
46cac009
AC
4764 hi.len);
4765}
4766
7a292a7a
SS
4767/* Given a return value in `valbuf' with a type `valtype', write it's
4768 value into the appropriate register. */
4769
46cac009
AC
4770static void
4771mips_eabi_store_return_value (struct type *valtype, char *valbuf)
4772{
d9d9c31f 4773 char raw_buffer[MAX_REGISTER_SIZE];
46cac009
AC
4774 struct return_value_word lo;
4775 struct return_value_word hi;
4776 return_value_location (valtype, &hi, &lo);
4777
4778 memset (raw_buffer, 0, sizeof (raw_buffer));
4779 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
62700349 4780 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer,
73937e03 4781 REGISTER_RAW_SIZE (lo.reg));
46cac009
AC
4782
4783 if (hi.len > 0)
4784 {
4785 memset (raw_buffer, 0, sizeof (raw_buffer));
4786 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
62700349 4787 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer,
73937e03 4788 REGISTER_RAW_SIZE (hi.reg));
46cac009
AC
4789 }
4790}
4791
4792static void
cb1d2653 4793mips_o64_store_return_value (struct type *valtype, char *valbuf)
46cac009 4794{
d9d9c31f 4795 char raw_buffer[MAX_REGISTER_SIZE];
46cac009
AC
4796 struct return_value_word lo;
4797 struct return_value_word hi;
4798 return_value_location (valtype, &hi, &lo);
4799
4800 memset (raw_buffer, 0, sizeof (raw_buffer));
4801 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
62700349 4802 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer,
73937e03 4803 REGISTER_RAW_SIZE (lo.reg));
46cac009
AC
4804
4805 if (hi.len > 0)
4806 {
4807 memset (raw_buffer, 0, sizeof (raw_buffer));
4808 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
62700349 4809 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer,
73937e03 4810 REGISTER_RAW_SIZE (hi.reg));
46cac009
AC
4811 }
4812}
4813
cb1d2653
AC
4814/* O32 ABI stuff. */
4815
46cac009 4816static void
cb1d2653
AC
4817mips_o32_xfer_return_value (struct type *type,
4818 struct regcache *regcache,
4819 bfd_byte *in, const bfd_byte *out)
46cac009 4820{
cb1d2653
AC
4821 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4822 if (TYPE_CODE (type) == TYPE_CODE_FLT
4823 && TYPE_LENGTH (type) == 4
4824 && tdep->mips_fpu_type != MIPS_FPU_NONE)
46cac009 4825 {
cb1d2653
AC
4826 /* A single-precision floating-point value. It fits in the
4827 least significant part of FP0. */
4828 if (mips_debug)
4829 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
a4b8ebc8 4830 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM, TYPE_LENGTH (type),
cb1d2653
AC
4831 TARGET_BYTE_ORDER, in, out, 0);
4832 }
4833 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4834 && TYPE_LENGTH (type) == 8
4835 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4836 {
a4b8ebc8
AC
4837 /* A double-precision floating-point value. The most
4838 significant part goes in FP1, and the least significant in
4839 FP0. */
cb1d2653 4840 if (mips_debug)
a4b8ebc8 4841 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
cb1d2653
AC
4842 switch (TARGET_BYTE_ORDER)
4843 {
4844 case BFD_ENDIAN_LITTLE:
a4b8ebc8 4845 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 0, 4,
cb1d2653 4846 TARGET_BYTE_ORDER, in, out, 0);
a4b8ebc8 4847 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 1, 4,
cb1d2653
AC
4848 TARGET_BYTE_ORDER, in, out, 4);
4849 break;
4850 case BFD_ENDIAN_BIG:
a4b8ebc8 4851 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 1, 4,
cb1d2653 4852 TARGET_BYTE_ORDER, in, out, 0);
a4b8ebc8 4853 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 0, 4,
cb1d2653
AC
4854 TARGET_BYTE_ORDER, in, out, 4);
4855 break;
4856 default:
4857 internal_error (__FILE__, __LINE__, "bad switch");
4858 }
4859 }
4860#if 0
4861 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4862 && TYPE_NFIELDS (type) <= 2
4863 && TYPE_NFIELDS (type) >= 1
4864 && ((TYPE_NFIELDS (type) == 1
4865 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4866 == TYPE_CODE_FLT))
4867 || (TYPE_NFIELDS (type) == 2
4868 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4869 == TYPE_CODE_FLT)
4870 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4871 == TYPE_CODE_FLT)))
4872 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4873 {
4874 /* A struct that contains one or two floats. Each value is part
4875 in the least significant part of their floating point
4876 register.. */
d9d9c31f 4877 bfd_byte reg[MAX_REGISTER_SIZE];
cb1d2653
AC
4878 int regnum;
4879 int field;
4880 for (field = 0, regnum = FP0_REGNUM;
4881 field < TYPE_NFIELDS (type);
4882 field++, regnum += 2)
4883 {
4884 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4885 / TARGET_CHAR_BIT);
4886 if (mips_debug)
4887 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
a4b8ebc8
AC
4888 mips_xfer_register (regcache, NUM_REGS + regnum,
4889 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
cb1d2653
AC
4890 TARGET_BYTE_ORDER, in, out, offset);
4891 }
4892 }
4893#endif
4894#if 0
4895 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4896 || TYPE_CODE (type) == TYPE_CODE_UNION)
4897 {
4898 /* A structure or union. Extract the left justified value,
4899 regardless of the byte order. I.e. DO NOT USE
4900 mips_xfer_lower. */
4901 int offset;
4902 int regnum;
4903 for (offset = 0, regnum = V0_REGNUM;
4904 offset < TYPE_LENGTH (type);
4905 offset += REGISTER_RAW_SIZE (regnum), regnum++)
4906 {
4907 int xfer = REGISTER_RAW_SIZE (regnum);
4908 if (offset + xfer > TYPE_LENGTH (type))
4909 xfer = TYPE_LENGTH (type) - offset;
4910 if (mips_debug)
4911 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4912 offset, xfer, regnum);
a4b8ebc8
AC
4913 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
4914 BFD_ENDIAN_UNKNOWN, in, out, offset);
cb1d2653
AC
4915 }
4916 }
4917#endif
4918 else
4919 {
4920 /* A scalar extract each part but least-significant-byte
4921 justified. o32 thinks registers are 4 byte, regardless of
4922 the ISA. mips_stack_argsize controls this. */
4923 int offset;
4924 int regnum;
4925 for (offset = 0, regnum = V0_REGNUM;
4926 offset < TYPE_LENGTH (type);
4927 offset += mips_stack_argsize (), regnum++)
4928 {
4929 int xfer = mips_stack_argsize ();
4930 int pos = 0;
4931 if (offset + xfer > TYPE_LENGTH (type))
4932 xfer = TYPE_LENGTH (type) - offset;
4933 if (mips_debug)
4934 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4935 offset, xfer, regnum);
a4b8ebc8
AC
4936 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
4937 TARGET_BYTE_ORDER, in, out, offset);
cb1d2653 4938 }
46cac009
AC
4939 }
4940}
4941
cb1d2653
AC
4942static void
4943mips_o32_extract_return_value (struct type *type,
4944 struct regcache *regcache,
ebba8386 4945 void *valbuf)
cb1d2653
AC
4946{
4947 mips_o32_xfer_return_value (type, regcache, valbuf, NULL);
4948}
4949
4950static void
4951mips_o32_store_return_value (struct type *type, char *valbuf)
4952{
4953 mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf);
4954}
4955
4956/* N32/N44 ABI stuff. */
4957
46cac009 4958static void
88658117
AC
4959mips_n32n64_xfer_return_value (struct type *type,
4960 struct regcache *regcache,
4961 bfd_byte *in, const bfd_byte *out)
c906108c 4962{
88658117
AC
4963 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4964 if (TYPE_CODE (type) == TYPE_CODE_FLT
4965 && tdep->mips_fpu_type != MIPS_FPU_NONE)
7a292a7a 4966 {
88658117
AC
4967 /* A floating-point value belongs in the least significant part
4968 of FP0. */
4969 if (mips_debug)
4970 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
a4b8ebc8 4971 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM, TYPE_LENGTH (type),
88658117
AC
4972 TARGET_BYTE_ORDER, in, out, 0);
4973 }
4974 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4975 && TYPE_NFIELDS (type) <= 2
4976 && TYPE_NFIELDS (type) >= 1
4977 && ((TYPE_NFIELDS (type) == 1
4978 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4979 == TYPE_CODE_FLT))
4980 || (TYPE_NFIELDS (type) == 2
4981 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4982 == TYPE_CODE_FLT)
4983 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4984 == TYPE_CODE_FLT)))
4985 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4986 {
4987 /* A struct that contains one or two floats. Each value is part
4988 in the least significant part of their floating point
4989 register.. */
d9d9c31f 4990 bfd_byte reg[MAX_REGISTER_SIZE];
88658117
AC
4991 int regnum;
4992 int field;
4993 for (field = 0, regnum = FP0_REGNUM;
4994 field < TYPE_NFIELDS (type);
4995 field++, regnum += 2)
4996 {
4997 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4998 / TARGET_CHAR_BIT);
4999 if (mips_debug)
5000 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
a4b8ebc8
AC
5001 mips_xfer_register (regcache, NUM_REGS + regnum,
5002 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
88658117
AC
5003 TARGET_BYTE_ORDER, in, out, offset);
5004 }
7a292a7a 5005 }
88658117
AC
5006 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
5007 || TYPE_CODE (type) == TYPE_CODE_UNION)
5008 {
5009 /* A structure or union. Extract the left justified value,
5010 regardless of the byte order. I.e. DO NOT USE
5011 mips_xfer_lower. */
5012 int offset;
5013 int regnum;
5014 for (offset = 0, regnum = V0_REGNUM;
5015 offset < TYPE_LENGTH (type);
5016 offset += REGISTER_RAW_SIZE (regnum), regnum++)
5017 {
5018 int xfer = REGISTER_RAW_SIZE (regnum);
5019 if (offset + xfer > TYPE_LENGTH (type))
5020 xfer = TYPE_LENGTH (type) - offset;
5021 if (mips_debug)
5022 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
5023 offset, xfer, regnum);
a4b8ebc8
AC
5024 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
5025 BFD_ENDIAN_UNKNOWN, in, out, offset);
88658117
AC
5026 }
5027 }
5028 else
5029 {
5030 /* A scalar extract each part but least-significant-byte
5031 justified. */
5032 int offset;
5033 int regnum;
5034 for (offset = 0, regnum = V0_REGNUM;
5035 offset < TYPE_LENGTH (type);
5036 offset += REGISTER_RAW_SIZE (regnum), regnum++)
5037 {
5038 int xfer = REGISTER_RAW_SIZE (regnum);
5039 int pos = 0;
5040 if (offset + xfer > TYPE_LENGTH (type))
5041 xfer = TYPE_LENGTH (type) - offset;
5042 if (mips_debug)
5043 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
5044 offset, xfer, regnum);
a4b8ebc8
AC
5045 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
5046 TARGET_BYTE_ORDER, in, out, offset);
88658117
AC
5047 }
5048 }
5049}
5050
5051static void
5052mips_n32n64_extract_return_value (struct type *type,
5053 struct regcache *regcache,
ebba8386 5054 void *valbuf)
88658117
AC
5055{
5056 mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL);
5057}
5058
5059static void
5060mips_n32n64_store_return_value (struct type *type, char *valbuf)
5061{
5062 mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf);
c906108c
SS
5063}
5064
2f1488ce 5065static CORE_ADDR
6672060b 5066mips_extract_struct_value_address (struct regcache *regcache)
2f1488ce
MS
5067{
5068 /* FIXME: This will only work at random. The caller passes the
5069 struct_return address in V0, but it is not preserved. It may
5070 still be there, or this may be a random value. */
77d8f2b4
MS
5071 LONGEST val;
5072
5073 regcache_cooked_read_signed (regcache, V0_REGNUM, &val);
6672060b 5074 return val;
2f1488ce
MS
5075}
5076
c906108c
SS
5077/* Exported procedure: Is PC in the signal trampoline code */
5078
102182a9
MS
5079static int
5080mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
c906108c
SS
5081{
5082 if (sigtramp_address == 0)
5083 fixup_sigtramp ();
5084 return (pc >= sigtramp_address && pc < sigtramp_end);
5085}
5086
a5ea2558
AC
5087/* Root of all "set mips "/"show mips " commands. This will eventually be
5088 used for all MIPS-specific commands. */
5089
a5ea2558 5090static void
acdb74a0 5091show_mips_command (char *args, int from_tty)
a5ea2558
AC
5092{
5093 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
5094}
5095
a5ea2558 5096static void
acdb74a0 5097set_mips_command (char *args, int from_tty)
a5ea2558
AC
5098{
5099 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5100 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
5101}
5102
c906108c
SS
5103/* Commands to show/set the MIPS FPU type. */
5104
c906108c 5105static void
acdb74a0 5106show_mipsfpu_command (char *args, int from_tty)
c906108c 5107{
c906108c
SS
5108 char *fpu;
5109 switch (MIPS_FPU_TYPE)
5110 {
5111 case MIPS_FPU_SINGLE:
5112 fpu = "single-precision";
5113 break;
5114 case MIPS_FPU_DOUBLE:
5115 fpu = "double-precision";
5116 break;
5117 case MIPS_FPU_NONE:
5118 fpu = "absent (none)";
5119 break;
93d56215
AC
5120 default:
5121 internal_error (__FILE__, __LINE__, "bad switch");
c906108c
SS
5122 }
5123 if (mips_fpu_type_auto)
5124 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5125 fpu);
5126 else
5127 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5128 fpu);
5129}
5130
5131
c906108c 5132static void
acdb74a0 5133set_mipsfpu_command (char *args, int from_tty)
c906108c
SS
5134{
5135 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5136 show_mipsfpu_command (args, from_tty);
5137}
5138
c906108c 5139static void
acdb74a0 5140set_mipsfpu_single_command (char *args, int from_tty)
c906108c
SS
5141{
5142 mips_fpu_type = MIPS_FPU_SINGLE;
5143 mips_fpu_type_auto = 0;
9e364162 5144 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
c906108c
SS
5145}
5146
c906108c 5147static void
acdb74a0 5148set_mipsfpu_double_command (char *args, int from_tty)
c906108c
SS
5149{
5150 mips_fpu_type = MIPS_FPU_DOUBLE;
5151 mips_fpu_type_auto = 0;
9e364162 5152 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
c906108c
SS
5153}
5154
c906108c 5155static void
acdb74a0 5156set_mipsfpu_none_command (char *args, int from_tty)
c906108c
SS
5157{
5158 mips_fpu_type = MIPS_FPU_NONE;
5159 mips_fpu_type_auto = 0;
9e364162 5160 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
c906108c
SS
5161}
5162
c906108c 5163static void
acdb74a0 5164set_mipsfpu_auto_command (char *args, int from_tty)
c906108c
SS
5165{
5166 mips_fpu_type_auto = 1;
5167}
5168
5169/* Command to set the processor type. */
5170
5171void
acdb74a0 5172mips_set_processor_type_command (char *args, int from_tty)
c906108c
SS
5173{
5174 int i;
5175
5176 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
5177 {
5178 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5179 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5180 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
5181
5182 /* Restore the value. */
4fcf66da 5183 tmp_mips_processor_type = xstrdup (mips_processor_type);
c906108c
SS
5184
5185 return;
5186 }
c5aa993b 5187
c906108c
SS
5188 if (!mips_set_processor_type (tmp_mips_processor_type))
5189 {
5190 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
5191 /* Restore its value. */
4fcf66da 5192 tmp_mips_processor_type = xstrdup (mips_processor_type);
c906108c
SS
5193 }
5194}
5195
5196static void
acdb74a0 5197mips_show_processor_type_command (char *args, int from_tty)
c906108c
SS
5198{
5199}
5200
5201/* Modify the actual processor type. */
5202
5a89d8aa 5203static int
acdb74a0 5204mips_set_processor_type (char *str)
c906108c 5205{
1012bd0e 5206 int i;
c906108c
SS
5207
5208 if (str == NULL)
5209 return 0;
5210
5211 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5212 {
5213 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
5214 {
5215 mips_processor_type = str;
cce74817 5216 mips_processor_reg_names = mips_processor_type_table[i].regnames;
c906108c 5217 return 1;
c906108c
SS
5218 /* FIXME tweak fpu flag too */
5219 }
5220 }
5221
5222 return 0;
5223}
5224
5225/* Attempt to identify the particular processor model by reading the
5226 processor id. */
5227
5228char *
acdb74a0 5229mips_read_processor_type (void)
c906108c
SS
5230{
5231 CORE_ADDR prid;
5232
5233 prid = read_register (PRID_REGNUM);
5234
5235 if ((prid & ~0xf) == 0x700)
c5aa993b 5236 return savestring ("r3041", strlen ("r3041"));
c906108c
SS
5237
5238 return NULL;
5239}
5240
5241/* Just like reinit_frame_cache, but with the right arguments to be
5242 callable as an sfunc. */
5243
5244static void
acdb74a0
AC
5245reinit_frame_cache_sfunc (char *args, int from_tty,
5246 struct cmd_list_element *c)
c906108c
SS
5247{
5248 reinit_frame_cache ();
5249}
5250
a89aa300
AC
5251static int
5252gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
c906108c 5253{
e5ab0dce 5254 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS
5255 mips_extra_func_info_t proc_desc;
5256
5257 /* Search for the function containing this address. Set the low bit
5258 of the address when searching, in case we were given an even address
5259 that is the start of a 16-bit function. If we didn't do this,
5260 the search would fail because the symbol table says the function
5261 starts at an odd address, i.e. 1 byte past the given address. */
5262 memaddr = ADDR_BITS_REMOVE (memaddr);
95404a3e 5263 proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL);
c906108c
SS
5264
5265 /* Make an attempt to determine if this is a 16-bit function. If
5266 the procedure descriptor exists and the address therein is odd,
5267 it's definitely a 16-bit function. Otherwise, we have to just
5268 guess that if the address passed in is odd, it's 16-bits. */
d31431ed
AC
5269 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5270 disassembler needs to be able to locally determine the ISA, and
5271 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5272 work. */
c906108c 5273 if (proc_desc)
d31431ed
AC
5274 {
5275 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
5276 info->mach = bfd_mach_mips16;
5277 }
c906108c 5278 else
d31431ed
AC
5279 {
5280 if (pc_is_mips16 (memaddr))
5281 info->mach = bfd_mach_mips16;
5282 }
c906108c
SS
5283
5284 /* Round down the instruction address to the appropriate boundary. */
65c11066 5285 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
c5aa993b 5286
e5ab0dce
AC
5287 /* Set the disassembler options. */
5288 if (tdep->mips_abi == MIPS_ABI_N32
5289 || tdep->mips_abi == MIPS_ABI_N64)
5290 {
5291 /* Set up the disassembler info, so that we get the right
5292 register names from libopcodes. */
5293 if (tdep->mips_abi == MIPS_ABI_N32)
5294 info->disassembler_options = "gpr-names=n32";
5295 else
5296 info->disassembler_options = "gpr-names=64";
5297 info->flavour = bfd_target_elf_flavour;
5298 }
5299 else
5300 /* This string is not recognized explicitly by the disassembler,
5301 but it tells the disassembler to not try to guess the ABI from
5302 the bfd elf headers, such that, if the user overrides the ABI
5303 of a program linked as NewABI, the disassembly will follow the
5304 register naming conventions specified by the user. */
5305 info->disassembler_options = "gpr-names=32";
5306
c906108c 5307 /* Call the appropriate disassembler based on the target endian-ness. */
d7449b42 5308 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS
5309 return print_insn_big_mips (memaddr, info);
5310 else
5311 return print_insn_little_mips (memaddr, info);
5312}
5313
c906108c
SS
5314/* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5315 counter value to determine whether a 16- or 32-bit breakpoint should be
5316 used. It returns a pointer to a string of bytes that encode a breakpoint
5317 instruction, stores the length of the string to *lenptr, and adjusts pc
5318 (if necessary) to point to the actual memory location where the
5319 breakpoint should be inserted. */
5320
f7ab6ec6 5321static const unsigned char *
acdb74a0 5322mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
c906108c 5323{
d7449b42 5324 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS
5325 {
5326 if (pc_is_mips16 (*pcptr))
5327 {
aaab4dba 5328 static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5};
95404a3e 5329 *pcptr = unmake_mips16_addr (*pcptr);
c5aa993b 5330 *lenptr = sizeof (mips16_big_breakpoint);
c906108c
SS
5331 return mips16_big_breakpoint;
5332 }
5333 else
5334 {
aaab4dba
AC
5335 /* The IDT board uses an unusual breakpoint value, and
5336 sometimes gets confused when it sees the usual MIPS
5337 breakpoint instruction. */
5338 static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd};
5339 static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd};
5340 static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd};
c906108c 5341
c5aa993b 5342 *lenptr = sizeof (big_breakpoint);
c906108c
SS
5343
5344 if (strcmp (target_shortname, "mips") == 0)
5345 return idt_big_breakpoint;
5346 else if (strcmp (target_shortname, "ddb") == 0
5347 || strcmp (target_shortname, "pmon") == 0
5348 || strcmp (target_shortname, "lsi") == 0)
5349 return pmon_big_breakpoint;
5350 else
5351 return big_breakpoint;
5352 }
5353 }
5354 else
5355 {
5356 if (pc_is_mips16 (*pcptr))
5357 {
aaab4dba 5358 static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8};
95404a3e 5359 *pcptr = unmake_mips16_addr (*pcptr);
c5aa993b 5360 *lenptr = sizeof (mips16_little_breakpoint);
c906108c
SS
5361 return mips16_little_breakpoint;
5362 }
5363 else
5364 {
aaab4dba
AC
5365 static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0};
5366 static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0};
5367 static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0};
c906108c 5368
c5aa993b 5369 *lenptr = sizeof (little_breakpoint);
c906108c
SS
5370
5371 if (strcmp (target_shortname, "mips") == 0)
5372 return idt_little_breakpoint;
5373 else if (strcmp (target_shortname, "ddb") == 0
5374 || strcmp (target_shortname, "pmon") == 0
5375 || strcmp (target_shortname, "lsi") == 0)
5376 return pmon_little_breakpoint;
5377 else
5378 return little_breakpoint;
5379 }
5380 }
5381}
5382
5383/* If PC is in a mips16 call or return stub, return the address of the target
5384 PC, which is either the callee or the caller. There are several
5385 cases which must be handled:
5386
5387 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
c5aa993b 5388 target PC is in $31 ($ra).
c906108c 5389 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
c5aa993b 5390 and the target PC is in $2.
c906108c 5391 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
c5aa993b
JM
5392 before the jal instruction, this is effectively a call stub
5393 and the the target PC is in $2. Otherwise this is effectively
5394 a return stub and the target PC is in $18.
c906108c
SS
5395
5396 See the source code for the stubs in gcc/config/mips/mips16.S for
5397 gory details.
5398
5399 This function implements the SKIP_TRAMPOLINE_CODE macro.
c5aa993b 5400 */
c906108c 5401
757a7cc6 5402static CORE_ADDR
acdb74a0 5403mips_skip_stub (CORE_ADDR pc)
c906108c
SS
5404{
5405 char *name;
5406 CORE_ADDR start_addr;
5407
5408 /* Find the starting address and name of the function containing the PC. */
5409 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5410 return 0;
5411
5412 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5413 target PC is in $31 ($ra). */
5414 if (strcmp (name, "__mips16_ret_sf") == 0
5415 || strcmp (name, "__mips16_ret_df") == 0)
6c997a34 5416 return read_signed_register (RA_REGNUM);
c906108c
SS
5417
5418 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5419 {
5420 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5421 and the target PC is in $2. */
5422 if (name[19] >= '0' && name[19] <= '9')
6c997a34 5423 return read_signed_register (2);
c906108c
SS
5424
5425 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
c5aa993b
JM
5426 before the jal instruction, this is effectively a call stub
5427 and the the target PC is in $2. Otherwise this is effectively
5428 a return stub and the target PC is in $18. */
c906108c
SS
5429 else if (name[19] == 's' || name[19] == 'd')
5430 {
5431 if (pc == start_addr)
5432 {
5433 /* Check if the target of the stub is a compiler-generated
c5aa993b
JM
5434 stub. Such a stub for a function bar might have a name
5435 like __fn_stub_bar, and might look like this:
5436 mfc1 $4,$f13
5437 mfc1 $5,$f12
5438 mfc1 $6,$f15
5439 mfc1 $7,$f14
5440 la $1,bar (becomes a lui/addiu pair)
5441 jr $1
5442 So scan down to the lui/addi and extract the target
5443 address from those two instructions. */
c906108c 5444
6c997a34 5445 CORE_ADDR target_pc = read_signed_register (2);
c906108c
SS
5446 t_inst inst;
5447 int i;
5448
5449 /* See if the name of the target function is __fn_stub_*. */
5450 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
5451 return target_pc;
5452 if (strncmp (name, "__fn_stub_", 10) != 0
5453 && strcmp (name, "etext") != 0
5454 && strcmp (name, "_etext") != 0)
5455 return target_pc;
5456
5457 /* Scan through this _fn_stub_ code for the lui/addiu pair.
c5aa993b
JM
5458 The limit on the search is arbitrarily set to 20
5459 instructions. FIXME. */
c906108c
SS
5460 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5461 {
c5aa993b
JM
5462 inst = mips_fetch_instruction (target_pc);
5463 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5464 pc = (inst << 16) & 0xffff0000; /* high word */
5465 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5466 return pc | (inst & 0xffff); /* low word */
c906108c
SS
5467 }
5468
5469 /* Couldn't find the lui/addui pair, so return stub address. */
5470 return target_pc;
5471 }
5472 else
5473 /* This is the 'return' part of a call stub. The return
5474 address is in $r18. */
6c997a34 5475 return read_signed_register (18);
c906108c
SS
5476 }
5477 }
c5aa993b 5478 return 0; /* not a stub */
c906108c
SS
5479}
5480
5481
5482/* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5483 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5484
757a7cc6 5485static int
acdb74a0 5486mips_in_call_stub (CORE_ADDR pc, char *name)
c906108c
SS
5487{
5488 CORE_ADDR start_addr;
5489
5490 /* Find the starting address of the function containing the PC. If the
5491 caller didn't give us a name, look it up at the same time. */
5492 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
5493 return 0;
5494
5495 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5496 {
5497 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5498 if (name[19] >= '0' && name[19] <= '9')
5499 return 1;
5500 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
c5aa993b 5501 before the jal instruction, this is effectively a call stub. */
c906108c
SS
5502 else if (name[19] == 's' || name[19] == 'd')
5503 return pc == start_addr;
5504 }
5505
c5aa993b 5506 return 0; /* not a stub */
c906108c
SS
5507}
5508
5509
5510/* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5511 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5512
e41b17f0 5513static int
acdb74a0 5514mips_in_return_stub (CORE_ADDR pc, char *name)
c906108c
SS
5515{
5516 CORE_ADDR start_addr;
5517
5518 /* Find the starting address of the function containing the PC. */
5519 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5520 return 0;
5521
5522 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5523 if (strcmp (name, "__mips16_ret_sf") == 0
5524 || strcmp (name, "__mips16_ret_df") == 0)
5525 return 1;
5526
5527 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
c5aa993b 5528 i.e. after the jal instruction, this is effectively a return stub. */
c906108c
SS
5529 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5530 && (name[19] == 's' || name[19] == 'd')
5531 && pc != start_addr)
5532 return 1;
5533
c5aa993b 5534 return 0; /* not a stub */
c906108c
SS
5535}
5536
5537
5538/* Return non-zero if the PC is in a library helper function that should
5539 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5540
5541int
acdb74a0 5542mips_ignore_helper (CORE_ADDR pc)
c906108c
SS
5543{
5544 char *name;
5545
5546 /* Find the starting address and name of the function containing the PC. */
5547 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5548 return 0;
5549
5550 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5551 that we want to ignore. */
5552 return (strcmp (name, "__mips16_ret_sf") == 0
5553 || strcmp (name, "__mips16_ret_df") == 0);
5554}
5555
5556
47a8d4ba
AC
5557/* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5558 the register stored on the stack (32) is different to its real raw
5559 size (64). The below ensures that registers are fetched from the
5560 stack using their ABI size and then stored into the RAW_BUFFER
5561 using their raw size.
5562
5563 The alternative to adding this function would be to add an ABI
5564 macro - REGISTER_STACK_SIZE(). */
5565
5566static void
acdb74a0 5567mips_get_saved_register (char *raw_buffer,
795e1e11 5568 int *optimizedp,
acdb74a0
AC
5569 CORE_ADDR *addrp,
5570 struct frame_info *frame,
5571 int regnum,
795e1e11 5572 enum lval_type *lvalp)
47a8d4ba 5573{
795e1e11
AC
5574 CORE_ADDR addrx;
5575 enum lval_type lvalx;
5576 int optimizedx;
6e51443a 5577 int realnumx;
47a8d4ba 5578
a4b8ebc8
AC
5579 /* Always a pseudo. */
5580 gdb_assert (regnum >= NUM_REGS);
47a8d4ba 5581
795e1e11
AC
5582 /* Make certain that all needed parameters are present. */
5583 if (addrp == NULL)
5584 addrp = &addrx;
5585 if (lvalp == NULL)
5586 lvalp = &lvalx;
5587 if (optimizedp == NULL)
5588 optimizedp = &optimizedx;
a4b8ebc8
AC
5589
5590 if ((regnum % NUM_REGS) == SP_REGNUM)
5591 /* The SP_REGNUM is special, its value is stored in saved_regs.
5592 In fact, it is so special that it can even only be fetched
5593 using a raw register number! Once this code as been converted
5594 to frame-unwind the problem goes away. */
5595 frame_register_unwind (deprecated_get_next_frame_hack (frame),
5596 regnum % NUM_REGS, optimizedp, lvalp, addrp,
5597 &realnumx, raw_buffer);
5598 else
5599 /* Get it from the next frame. */
5600 frame_register_unwind (deprecated_get_next_frame_hack (frame),
5601 regnum, optimizedp, lvalp, addrp,
5602 &realnumx, raw_buffer);
47a8d4ba 5603}
2acceee2 5604
f7b9e9fc
AC
5605/* Immediately after a function call, return the saved pc.
5606 Can't always go through the frames for this because on some machines
5607 the new frame is not set up until the new function executes
5608 some instructions. */
5609
5610static CORE_ADDR
5611mips_saved_pc_after_call (struct frame_info *frame)
5612{
6c997a34 5613 return read_signed_register (RA_REGNUM);
f7b9e9fc
AC
5614}
5615
5616
a4b8ebc8
AC
5617/* Convert a dbx stab register number (from `r' declaration) to a GDB
5618 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
88c72b7d
AC
5619
5620static int
5621mips_stab_reg_to_regnum (int num)
5622{
a4b8ebc8 5623 int regnum;
2f38ef89 5624 if (num >= 0 && num < 32)
a4b8ebc8 5625 regnum = num;
2f38ef89 5626 else if (num >= 38 && num < 70)
a4b8ebc8 5627 regnum = num + FP0_REGNUM - 38;
040b99fd 5628 else if (num == 70)
a4b8ebc8 5629 regnum = HI_REGNUM;
040b99fd 5630 else if (num == 71)
a4b8ebc8 5631 regnum = LO_REGNUM;
2f38ef89 5632 else
a4b8ebc8
AC
5633 /* This will hopefully (eventually) provoke a warning. Should
5634 we be calling complaint() here? */
5635 return NUM_REGS + NUM_PSEUDO_REGS;
5636 return NUM_REGS + regnum;
88c72b7d
AC
5637}
5638
2f38ef89 5639
a4b8ebc8
AC
5640/* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5641 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
88c72b7d
AC
5642
5643static int
2f38ef89 5644mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
88c72b7d 5645{
a4b8ebc8 5646 int regnum;
2f38ef89 5647 if (num >= 0 && num < 32)
a4b8ebc8 5648 regnum = num;
2f38ef89 5649 else if (num >= 32 && num < 64)
a4b8ebc8 5650 regnum = num + FP0_REGNUM - 32;
040b99fd 5651 else if (num == 64)
a4b8ebc8 5652 regnum = HI_REGNUM;
040b99fd 5653 else if (num == 65)
a4b8ebc8 5654 regnum = LO_REGNUM;
2f38ef89 5655 else
a4b8ebc8
AC
5656 /* This will hopefully (eventually) provoke a warning. Should we
5657 be calling complaint() here? */
5658 return NUM_REGS + NUM_PSEUDO_REGS;
5659 return NUM_REGS + regnum;
5660}
5661
5662static int
5663mips_register_sim_regno (int regnum)
5664{
5665 /* Only makes sense to supply raw registers. */
5666 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
5667 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5668 decide if it is valid. Should instead define a standard sim/gdb
5669 register numbering scheme. */
5670 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
5671 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
5672 return regnum;
5673 else
5674 return LEGACY_SIM_REGNO_IGNORE;
88c72b7d
AC
5675}
5676
2f38ef89 5677
fc0c74b1
AC
5678/* Convert an integer into an address. By first converting the value
5679 into a pointer and then extracting it signed, the address is
5680 guarenteed to be correctly sign extended. */
5681
5682static CORE_ADDR
5683mips_integer_to_address (struct type *type, void *buf)
5684{
5685 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5686 LONGEST val = unpack_long (type, buf);
5687 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5688 return extract_signed_integer (tmp,
5689 TYPE_LENGTH (builtin_type_void_data_ptr));
5690}
5691
caaa3122
DJ
5692static void
5693mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5694{
5695 enum mips_abi *abip = (enum mips_abi *) obj;
5696 const char *name = bfd_get_section_name (abfd, sect);
5697
5698 if (*abip != MIPS_ABI_UNKNOWN)
5699 return;
5700
5701 if (strncmp (name, ".mdebug.", 8) != 0)
5702 return;
5703
5704 if (strcmp (name, ".mdebug.abi32") == 0)
5705 *abip = MIPS_ABI_O32;
5706 else if (strcmp (name, ".mdebug.abiN32") == 0)
5707 *abip = MIPS_ABI_N32;
62a49b2c 5708 else if (strcmp (name, ".mdebug.abi64") == 0)
e3bddbfa 5709 *abip = MIPS_ABI_N64;
caaa3122
DJ
5710 else if (strcmp (name, ".mdebug.abiO64") == 0)
5711 *abip = MIPS_ABI_O64;
5712 else if (strcmp (name, ".mdebug.eabi32") == 0)
5713 *abip = MIPS_ABI_EABI32;
5714 else if (strcmp (name, ".mdebug.eabi64") == 0)
5715 *abip = MIPS_ABI_EABI64;
5716 else
5717 warning ("unsupported ABI %s.", name + 8);
5718}
5719
2e4ebe70
DJ
5720static enum mips_abi
5721global_mips_abi (void)
5722{
5723 int i;
5724
5725 for (i = 0; mips_abi_strings[i] != NULL; i++)
5726 if (mips_abi_strings[i] == mips_abi_string)
5727 return (enum mips_abi) i;
5728
5729 internal_error (__FILE__, __LINE__,
5730 "unknown ABI string");
5731}
5732
c2d11a7d 5733static struct gdbarch *
acdb74a0
AC
5734mips_gdbarch_init (struct gdbarch_info info,
5735 struct gdbarch_list *arches)
c2d11a7d 5736{
c2d11a7d
JM
5737 struct gdbarch *gdbarch;
5738 struct gdbarch_tdep *tdep;
5739 int elf_flags;
2e4ebe70 5740 enum mips_abi mips_abi, found_abi, wanted_abi;
a4b8ebc8 5741 int num_regs;
c2d11a7d 5742
70f80edf
JT
5743 elf_flags = 0;
5744
5745 if (info.abfd)
5746 {
5747 /* First of all, extract the elf_flags, if available. */
5748 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5749 elf_flags = elf_elfheader (info.abfd)->e_flags;
70f80edf 5750 }
c2d11a7d 5751
102182a9 5752 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
0dadbba0
AC
5753 switch ((elf_flags & EF_MIPS_ABI))
5754 {
5755 case E_MIPS_ABI_O32:
5756 mips_abi = MIPS_ABI_O32;
5757 break;
5758 case E_MIPS_ABI_O64:
5759 mips_abi = MIPS_ABI_O64;
5760 break;
5761 case E_MIPS_ABI_EABI32:
5762 mips_abi = MIPS_ABI_EABI32;
5763 break;
5764 case E_MIPS_ABI_EABI64:
4a7f7ba8 5765 mips_abi = MIPS_ABI_EABI64;
0dadbba0
AC
5766 break;
5767 default:
acdb74a0
AC
5768 if ((elf_flags & EF_MIPS_ABI2))
5769 mips_abi = MIPS_ABI_N32;
5770 else
5771 mips_abi = MIPS_ABI_UNKNOWN;
0dadbba0
AC
5772 break;
5773 }
acdb74a0 5774
caaa3122
DJ
5775 /* GCC creates a pseudo-section whose name describes the ABI. */
5776 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5777 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
5778
2e4ebe70
DJ
5779 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5780 Use the ABI from the last architecture if there is one. */
5781 if (info.abfd == NULL && arches != NULL)
5782 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5783
32a6503c 5784 /* Try the architecture for any hint of the correct ABI. */
bf64bfd6
AC
5785 if (mips_abi == MIPS_ABI_UNKNOWN
5786 && info.bfd_arch_info != NULL
5787 && info.bfd_arch_info->arch == bfd_arch_mips)
5788 {
5789 switch (info.bfd_arch_info->mach)
5790 {
5791 case bfd_mach_mips3900:
5792 mips_abi = MIPS_ABI_EABI32;
5793 break;
5794 case bfd_mach_mips4100:
5795 case bfd_mach_mips5000:
5796 mips_abi = MIPS_ABI_EABI64;
5797 break;
1d06468c
EZ
5798 case bfd_mach_mips8000:
5799 case bfd_mach_mips10000:
32a6503c
KB
5800 /* On Irix, ELF64 executables use the N64 ABI. The
5801 pseudo-sections which describe the ABI aren't present
5802 on IRIX. (Even for executables created by gcc.) */
28d169de
KB
5803 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5804 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5805 mips_abi = MIPS_ABI_N64;
5806 else
5807 mips_abi = MIPS_ABI_N32;
1d06468c 5808 break;
bf64bfd6
AC
5809 }
5810 }
2e4ebe70 5811
2e4ebe70
DJ
5812 if (mips_abi == MIPS_ABI_UNKNOWN)
5813 mips_abi = MIPS_ABI_O32;
5814
5815 /* Now that we have found what the ABI for this binary would be,
5816 check whether the user is overriding it. */
5817 found_abi = mips_abi;
5818 wanted_abi = global_mips_abi ();
5819 if (wanted_abi != MIPS_ABI_UNKNOWN)
5820 mips_abi = wanted_abi;
5821
4b9b3959
AC
5822 if (gdbarch_debug)
5823 {
5824 fprintf_unfiltered (gdb_stdlog,
9ace0497 5825 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4b9b3959 5826 elf_flags);
4b9b3959
AC
5827 fprintf_unfiltered (gdb_stdlog,
5828 "mips_gdbarch_init: mips_abi = %d\n",
5829 mips_abi);
2e4ebe70
DJ
5830 fprintf_unfiltered (gdb_stdlog,
5831 "mips_gdbarch_init: found_mips_abi = %d\n",
5832 found_abi);
4b9b3959 5833 }
0dadbba0 5834
c2d11a7d
JM
5835 /* try to find a pre-existing architecture */
5836 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5837 arches != NULL;
5838 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5839 {
5840 /* MIPS needs to be pedantic about which ABI the object is
102182a9 5841 using. */
9103eae0 5842 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
c2d11a7d 5843 continue;
9103eae0 5844 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
0dadbba0 5845 continue;
4be87837 5846 return arches->gdbarch;
c2d11a7d
JM
5847 }
5848
102182a9 5849 /* Need a new architecture. Fill in a target specific vector. */
c2d11a7d
JM
5850 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5851 gdbarch = gdbarch_alloc (&info, tdep);
5852 tdep->elf_flags = elf_flags;
5853
102182a9 5854 /* Initially set everything according to the default ABI/ISA. */
c2d11a7d
JM
5855 set_gdbarch_short_bit (gdbarch, 16);
5856 set_gdbarch_int_bit (gdbarch, 32);
5857 set_gdbarch_float_bit (gdbarch, 32);
5858 set_gdbarch_double_bit (gdbarch, 64);
5859 set_gdbarch_long_double_bit (gdbarch, 64);
9c04cab7 5860 set_gdbarch_deprecated_register_raw_size (gdbarch, mips_register_raw_size);
a4b8ebc8
AC
5861 set_gdbarch_deprecated_register_byte (gdbarch, mips_register_byte);
5862 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5863 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5864 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
2e4ebe70 5865 tdep->found_abi = found_abi;
0dadbba0 5866 tdep->mips_abi = mips_abi;
1d06468c 5867
f7ab6ec6
MS
5868 set_gdbarch_elf_make_msymbol_special (gdbarch,
5869 mips_elf_make_msymbol_special);
5870
a4b8ebc8 5871
4be87837 5872 if (info.osabi == GDB_OSABI_IRIX)
a4b8ebc8 5873 num_regs = 71;
fe29b929 5874 else
a4b8ebc8
AC
5875 num_regs = 90;
5876 set_gdbarch_num_regs (gdbarch, num_regs);
5877 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
fe29b929 5878
0dadbba0 5879 switch (mips_abi)
c2d11a7d 5880 {
0dadbba0 5881 case MIPS_ABI_O32:
25ab4790 5882 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
ebba8386 5883 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value);
cb1d2653 5884 set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value);
a5ea2558 5885 tdep->mips_default_saved_regsize = 4;
0dadbba0 5886 tdep->mips_default_stack_argsize = 4;
c2d11a7d 5887 tdep->mips_fp_register_double = 0;
acdb74a0
AC
5888 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5889 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5213ab06 5890 tdep->gdb_target_is_mips64 = 0;
4014092b 5891 tdep->default_mask_address_p = 0;
c2d11a7d
JM
5892 set_gdbarch_long_bit (gdbarch, 32);
5893 set_gdbarch_ptr_bit (gdbarch, 32);
5894 set_gdbarch_long_long_bit (gdbarch, 64);
2110b94f
MK
5895 set_gdbarch_deprecated_reg_struct_has_addr
5896 (gdbarch, mips_o32_reg_struct_has_addr);
cb811fe7 5897 set_gdbarch_use_struct_convention (gdbarch,
1fd35568 5898 always_use_struct_convention);
c2d11a7d 5899 break;
0dadbba0 5900 case MIPS_ABI_O64:
25ab4790 5901 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
ebba8386 5902 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value);
46cac009 5903 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
a5ea2558 5904 tdep->mips_default_saved_regsize = 8;
0dadbba0 5905 tdep->mips_default_stack_argsize = 8;
c2d11a7d 5906 tdep->mips_fp_register_double = 1;
acdb74a0
AC
5907 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5908 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5213ab06 5909 tdep->gdb_target_is_mips64 = 1;
361d1df0 5910 tdep->default_mask_address_p = 0;
c2d11a7d
JM
5911 set_gdbarch_long_bit (gdbarch, 32);
5912 set_gdbarch_ptr_bit (gdbarch, 32);
5913 set_gdbarch_long_long_bit (gdbarch, 64);
2110b94f
MK
5914 set_gdbarch_deprecated_reg_struct_has_addr
5915 (gdbarch, mips_o32_reg_struct_has_addr);
b060cbea 5916 set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention);
c2d11a7d 5917 break;
0dadbba0 5918 case MIPS_ABI_EABI32:
25ab4790 5919 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
ebba8386 5920 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
46cac009 5921 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
a5ea2558 5922 tdep->mips_default_saved_regsize = 4;
0dadbba0 5923 tdep->mips_default_stack_argsize = 4;
c2d11a7d 5924 tdep->mips_fp_register_double = 0;
acdb74a0
AC
5925 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5926 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5213ab06 5927 tdep->gdb_target_is_mips64 = 0;
4014092b 5928 tdep->default_mask_address_p = 0;
c2d11a7d
JM
5929 set_gdbarch_long_bit (gdbarch, 32);
5930 set_gdbarch_ptr_bit (gdbarch, 32);
5931 set_gdbarch_long_long_bit (gdbarch, 64);
2110b94f
MK
5932 set_gdbarch_deprecated_reg_struct_has_addr
5933 (gdbarch, mips_eabi_reg_struct_has_addr);
cb811fe7
MS
5934 set_gdbarch_use_struct_convention (gdbarch,
5935 mips_eabi_use_struct_convention);
c2d11a7d 5936 break;
0dadbba0 5937 case MIPS_ABI_EABI64:
25ab4790 5938 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
ebba8386 5939 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
46cac009 5940 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
a5ea2558 5941 tdep->mips_default_saved_regsize = 8;
0dadbba0 5942 tdep->mips_default_stack_argsize = 8;
c2d11a7d 5943 tdep->mips_fp_register_double = 1;
acdb74a0
AC
5944 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5945 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5213ab06 5946 tdep->gdb_target_is_mips64 = 1;
4014092b 5947 tdep->default_mask_address_p = 0;
c2d11a7d
JM
5948 set_gdbarch_long_bit (gdbarch, 64);
5949 set_gdbarch_ptr_bit (gdbarch, 64);
5950 set_gdbarch_long_long_bit (gdbarch, 64);
2110b94f
MK
5951 set_gdbarch_deprecated_reg_struct_has_addr
5952 (gdbarch, mips_eabi_reg_struct_has_addr);
cb811fe7
MS
5953 set_gdbarch_use_struct_convention (gdbarch,
5954 mips_eabi_use_struct_convention);
c2d11a7d 5955 break;
0dadbba0 5956 case MIPS_ABI_N32:
25ab4790 5957 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
ebba8386 5958 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
88658117 5959 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
63db5580 5960 tdep->mips_default_saved_regsize = 8;
0dadbba0
AC
5961 tdep->mips_default_stack_argsize = 8;
5962 tdep->mips_fp_register_double = 1;
acdb74a0
AC
5963 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5964 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
6acdf5c7 5965 tdep->gdb_target_is_mips64 = 1;
4014092b 5966 tdep->default_mask_address_p = 0;
0dadbba0
AC
5967 set_gdbarch_long_bit (gdbarch, 32);
5968 set_gdbarch_ptr_bit (gdbarch, 32);
5969 set_gdbarch_long_long_bit (gdbarch, 64);
cb811fe7
MS
5970 set_gdbarch_use_struct_convention (gdbarch,
5971 mips_n32n64_use_struct_convention);
2110b94f
MK
5972 set_gdbarch_deprecated_reg_struct_has_addr
5973 (gdbarch, mips_n32n64_reg_struct_has_addr);
28d169de
KB
5974 break;
5975 case MIPS_ABI_N64:
25ab4790 5976 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
ebba8386 5977 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
88658117 5978 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
28d169de
KB
5979 tdep->mips_default_saved_regsize = 8;
5980 tdep->mips_default_stack_argsize = 8;
5981 tdep->mips_fp_register_double = 1;
5982 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5983 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
28d169de
KB
5984 tdep->gdb_target_is_mips64 = 1;
5985 tdep->default_mask_address_p = 0;
5986 set_gdbarch_long_bit (gdbarch, 64);
5987 set_gdbarch_ptr_bit (gdbarch, 64);
5988 set_gdbarch_long_long_bit (gdbarch, 64);
cb811fe7
MS
5989 set_gdbarch_use_struct_convention (gdbarch,
5990 mips_n32n64_use_struct_convention);
2110b94f
MK
5991 set_gdbarch_deprecated_reg_struct_has_addr
5992 (gdbarch, mips_n32n64_reg_struct_has_addr);
0dadbba0 5993 break;
c2d11a7d 5994 default:
2e4ebe70
DJ
5995 internal_error (__FILE__, __LINE__,
5996 "unknown ABI in switch");
c2d11a7d
JM
5997 }
5998
a5ea2558
AC
5999 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6000 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6001 comment:
6002
6003 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6004 flag in object files because to do so would make it impossible to
102182a9 6005 link with libraries compiled without "-gp32". This is
a5ea2558 6006 unnecessarily restrictive.
361d1df0 6007
a5ea2558
AC
6008 We could solve this problem by adding "-gp32" multilibs to gcc,
6009 but to set this flag before gcc is built with such multilibs will
6010 break too many systems.''
6011
6012 But even more unhelpfully, the default linker output target for
6013 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6014 for 64-bit programs - you need to change the ABI to change this,
102182a9 6015 and not all gcc targets support that currently. Therefore using
a5ea2558
AC
6016 this flag to detect 32-bit mode would do the wrong thing given
6017 the current gcc - it would make GDB treat these 64-bit programs
102182a9 6018 as 32-bit programs by default. */
a5ea2558 6019
c2d11a7d
JM
6020 /* enable/disable the MIPS FPU */
6021 if (!mips_fpu_type_auto)
6022 tdep->mips_fpu_type = mips_fpu_type;
6023 else if (info.bfd_arch_info != NULL
6024 && info.bfd_arch_info->arch == bfd_arch_mips)
6025 switch (info.bfd_arch_info->mach)
6026 {
b0069a17 6027 case bfd_mach_mips3900:
c2d11a7d 6028 case bfd_mach_mips4100:
ed9a39eb 6029 case bfd_mach_mips4111:
c2d11a7d
JM
6030 tdep->mips_fpu_type = MIPS_FPU_NONE;
6031 break;
bf64bfd6
AC
6032 case bfd_mach_mips4650:
6033 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
6034 break;
c2d11a7d
JM
6035 default:
6036 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
6037 break;
6038 }
6039 else
6040 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
6041
6042 /* MIPS version of register names. NOTE: At present the MIPS
6043 register name management is part way between the old -
77949794 6044 #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr).
102182a9 6045 Further work on it is required. */
c2d11a7d 6046 set_gdbarch_register_name (gdbarch, mips_register_name);
6c997a34 6047 set_gdbarch_read_pc (gdbarch, mips_read_pc);
c2d11a7d 6048 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
0ba6dca9 6049 set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
bcb0cc15 6050 set_gdbarch_read_sp (gdbarch, mips_read_sp);
c2d11a7d 6051
102182a9
MS
6052 /* Add/remove bits from an address. The MIPS needs be careful to
6053 ensure that all 32 bit addresses are sign extended to 64 bits. */
875e1767
AC
6054 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
6055
10312cc4 6056 /* There's a mess in stack frame creation. See comments in
2ca6c561
AC
6057 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6058 set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
10312cc4 6059
102182a9 6060 /* Map debug register numbers onto internal register numbers. */
88c72b7d 6061 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
2f38ef89
KB
6062 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6063 set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6064 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
a4b8ebc8 6065 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
88c72b7d 6066
c2d11a7d 6067 /* Initialize a frame */
e0f7ec59 6068 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs);
e9582e71 6069 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
c2d11a7d
JM
6070
6071 /* MIPS version of CALL_DUMMY */
6072
9710e734
AC
6073 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6074 replaced by a command, and all targets will default to on stack
6075 (regardless of the stack's execute status). */
6076 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
749b82f6 6077 set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame);
dc604539 6078 set_gdbarch_frame_align (gdbarch, mips_frame_align);
a59fe496 6079 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
781a750d
AC
6080 set_gdbarch_deprecated_register_convertible (gdbarch, mips_register_convertible);
6081 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, mips_register_convert_to_virtual);
6082 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, mips_register_convert_to_raw);
d05285fa 6083
618ce49f 6084 set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain);
b5d1566e
MS
6085 set_gdbarch_frameless_function_invocation (gdbarch,
6086 generic_frameless_function_invocation_not);
8bedc050 6087 set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc);
b5d1566e
MS
6088 set_gdbarch_frame_args_skip (gdbarch, 0);
6089
129c1cd6 6090 set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register);
c2d11a7d 6091
f7b9e9fc
AC
6092 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6093 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
6094 set_gdbarch_decr_pc_after_break (gdbarch, 0);
f7b9e9fc
AC
6095
6096 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
6913c89a 6097 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
f7b9e9fc 6098
fc0c74b1
AC
6099 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
6100 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
6101 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
70f80edf 6102
102182a9
MS
6103 set_gdbarch_function_start_offset (gdbarch, 0);
6104
a4b8ebc8 6105 set_gdbarch_register_type (gdbarch, mips_register_type);
78fde5f8 6106
e11c53d2 6107 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
102182a9 6108 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
bf1f5b4c 6109
e5ab0dce
AC
6110 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
6111
3a3bc038
AC
6112 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6113 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6114 need to all be folded into the target vector. Since they are
6115 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6116 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6117 is sitting on? */
6118 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6119
70f80edf 6120 /* Hook in OS ABI-specific overrides, if they have been registered. */
4be87837 6121 gdbarch_init_osabi (info, gdbarch);
70f80edf 6122
2f1488ce
MS
6123 set_gdbarch_extract_struct_value_address (gdbarch,
6124 mips_extract_struct_value_address);
757a7cc6
MS
6125
6126 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
6127
6128 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
e41b17f0 6129 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
757a7cc6 6130
4b9b3959
AC
6131 return gdbarch;
6132}
6133
2e4ebe70
DJ
6134static void
6135mips_abi_update (char *ignore_args, int from_tty,
6136 struct cmd_list_element *c)
6137{
6138 struct gdbarch_info info;
6139
6140 /* Force the architecture to update, and (if it's a MIPS architecture)
6141 mips_gdbarch_init will take care of the rest. */
6142 gdbarch_info_init (&info);
6143 gdbarch_update_p (info);
6144}
6145
ad188201
KB
6146/* Print out which MIPS ABI is in use. */
6147
6148static void
6149show_mips_abi (char *ignore_args, int from_tty)
6150{
6151 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
6152 printf_filtered (
6153 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6154 else
6155 {
6156 enum mips_abi global_abi = global_mips_abi ();
6157 enum mips_abi actual_abi = mips_abi (current_gdbarch);
6158 const char *actual_abi_str = mips_abi_strings[actual_abi];
6159
6160 if (global_abi == MIPS_ABI_UNKNOWN)
6161 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6162 actual_abi_str);
6163 else if (global_abi == actual_abi)
6164 printf_filtered (
6165 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6166 actual_abi_str);
6167 else
6168 {
6169 /* Probably shouldn't happen... */
6170 printf_filtered (
6171 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6172 actual_abi_str,
6173 mips_abi_strings[global_abi]);
6174 }
6175 }
6176}
6177
4b9b3959
AC
6178static void
6179mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
6180{
6181 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
6182 if (tdep != NULL)
c2d11a7d 6183 {
acdb74a0
AC
6184 int ef_mips_arch;
6185 int ef_mips_32bitmode;
6186 /* determine the ISA */
6187 switch (tdep->elf_flags & EF_MIPS_ARCH)
6188 {
6189 case E_MIPS_ARCH_1:
6190 ef_mips_arch = 1;
6191 break;
6192 case E_MIPS_ARCH_2:
6193 ef_mips_arch = 2;
6194 break;
6195 case E_MIPS_ARCH_3:
6196 ef_mips_arch = 3;
6197 break;
6198 case E_MIPS_ARCH_4:
93d56215 6199 ef_mips_arch = 4;
acdb74a0
AC
6200 break;
6201 default:
93d56215 6202 ef_mips_arch = 0;
acdb74a0
AC
6203 break;
6204 }
6205 /* determine the size of a pointer */
6206 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
4b9b3959
AC
6207 fprintf_unfiltered (file,
6208 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
0dadbba0 6209 tdep->elf_flags);
4b9b3959 6210 fprintf_unfiltered (file,
acdb74a0
AC
6211 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6212 ef_mips_32bitmode);
6213 fprintf_unfiltered (file,
6214 "mips_dump_tdep: ef_mips_arch = %d\n",
6215 ef_mips_arch);
6216 fprintf_unfiltered (file,
6217 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6218 tdep->mips_abi,
2e4ebe70 6219 mips_abi_strings[tdep->mips_abi]);
4014092b
AC
6220 fprintf_unfiltered (file,
6221 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6222 mips_mask_address_p (),
6223 tdep->default_mask_address_p);
c2d11a7d 6224 }
4b9b3959
AC
6225 fprintf_unfiltered (file,
6226 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6227 FP_REGISTER_DOUBLE);
6228 fprintf_unfiltered (file,
6229 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6230 MIPS_DEFAULT_FPU_TYPE,
6231 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6232 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6233 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6234 : "???"));
6235 fprintf_unfiltered (file,
6236 "mips_dump_tdep: MIPS_EABI = %d\n",
6237 MIPS_EABI);
6238 fprintf_unfiltered (file,
acdb74a0
AC
6239 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6240 MIPS_LAST_FP_ARG_REGNUM,
6241 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
4b9b3959
AC
6242 fprintf_unfiltered (file,
6243 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6244 MIPS_FPU_TYPE,
6245 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6246 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6247 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6248 : "???"));
6249 fprintf_unfiltered (file,
6250 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6251 MIPS_DEFAULT_SAVED_REGSIZE);
4b9b3959
AC
6252 fprintf_unfiltered (file,
6253 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6254 FP_REGISTER_DOUBLE);
4b9b3959
AC
6255 fprintf_unfiltered (file,
6256 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6257 MIPS_DEFAULT_STACK_ARGSIZE);
6258 fprintf_unfiltered (file,
6259 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6260 MIPS_STACK_ARGSIZE);
6261 fprintf_unfiltered (file,
6262 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6263 MIPS_REGSIZE);
2475bac3
AC
6264 fprintf_unfiltered (file,
6265 "mips_dump_tdep: A0_REGNUM = %d\n",
6266 A0_REGNUM);
6267 fprintf_unfiltered (file,
6268 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6269 XSTRING (ADDR_BITS_REMOVE(ADDR)));
6270 fprintf_unfiltered (file,
6271 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6272 XSTRING (ATTACH_DETACH));
6273 fprintf_unfiltered (file,
6274 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6275 BADVADDR_REGNUM);
2475bac3
AC
6276 fprintf_unfiltered (file,
6277 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6278 CAUSE_REGNUM);
2475bac3
AC
6279 fprintf_unfiltered (file,
6280 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6281 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
6282 fprintf_unfiltered (file,
6283 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6284 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
2475bac3
AC
6285 fprintf_unfiltered (file,
6286 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6287 FCRCS_REGNUM);
6288 fprintf_unfiltered (file,
6289 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6290 FCRIR_REGNUM);
6291 fprintf_unfiltered (file,
6292 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6293 FIRST_EMBED_REGNUM);
6294 fprintf_unfiltered (file,
6295 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6296 FPA0_REGNUM);
6297 fprintf_unfiltered (file,
6298 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6299 GDB_TARGET_IS_MIPS64);
2475bac3
AC
6300 fprintf_unfiltered (file,
6301 "mips_dump_tdep: HI_REGNUM = %d\n",
6302 HI_REGNUM);
2475bac3
AC
6303 fprintf_unfiltered (file,
6304 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6305 XSTRING (IGNORE_HELPER_CALL (PC)));
2475bac3
AC
6306 fprintf_unfiltered (file,
6307 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6308 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
6309 fprintf_unfiltered (file,
6310 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6311 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
2475bac3
AC
6312 fprintf_unfiltered (file,
6313 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6314 LAST_EMBED_REGNUM);
2475bac3
AC
6315 fprintf_unfiltered (file,
6316 "mips_dump_tdep: LO_REGNUM = %d\n",
6317 LO_REGNUM);
6318#ifdef MACHINE_CPROC_FP_OFFSET
6319 fprintf_unfiltered (file,
6320 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6321 MACHINE_CPROC_FP_OFFSET);
6322#endif
6323#ifdef MACHINE_CPROC_PC_OFFSET
6324 fprintf_unfiltered (file,
6325 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6326 MACHINE_CPROC_PC_OFFSET);
6327#endif
6328#ifdef MACHINE_CPROC_SP_OFFSET
6329 fprintf_unfiltered (file,
6330 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6331 MACHINE_CPROC_SP_OFFSET);
6332#endif
2475bac3
AC
6333 fprintf_unfiltered (file,
6334 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6335 MIPS16_INSTLEN);
2475bac3
AC
6336 fprintf_unfiltered (file,
6337 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6338 fprintf_unfiltered (file,
6339 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6340 fprintf_unfiltered (file,
6341 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6342 MIPS_INSTLEN);
6343 fprintf_unfiltered (file,
acdb74a0
AC
6344 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6345 MIPS_LAST_ARG_REGNUM,
6346 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
2475bac3
AC
6347 fprintf_unfiltered (file,
6348 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6349 MIPS_NUMREGS);
6350 fprintf_unfiltered (file,
6351 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6352 fprintf_unfiltered (file,
6353 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6354 MIPS_SAVED_REGSIZE);
2475bac3
AC
6355 fprintf_unfiltered (file,
6356 "mips_dump_tdep: OP_LDFPR = used?\n");
6357 fprintf_unfiltered (file,
6358 "mips_dump_tdep: OP_LDGPR = used?\n");
2475bac3
AC
6359 fprintf_unfiltered (file,
6360 "mips_dump_tdep: PRID_REGNUM = %d\n",
6361 PRID_REGNUM);
6362 fprintf_unfiltered (file,
6363 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6364 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
6365 fprintf_unfiltered (file,
6366 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6367 fprintf_unfiltered (file,
6368 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6369 fprintf_unfiltered (file,
6370 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6371 fprintf_unfiltered (file,
6372 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6373 fprintf_unfiltered (file,
6374 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6375 fprintf_unfiltered (file,
6376 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6377 fprintf_unfiltered (file,
6378 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6379 fprintf_unfiltered (file,
6380 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6381 fprintf_unfiltered (file,
6382 "mips_dump_tdep: PROC_PC_REG = function?\n");
6383 fprintf_unfiltered (file,
6384 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6385 fprintf_unfiltered (file,
6386 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6387 fprintf_unfiltered (file,
6388 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6389 fprintf_unfiltered (file,
6390 "mips_dump_tdep: PS_REGNUM = %d\n",
6391 PS_REGNUM);
2475bac3
AC
6392 fprintf_unfiltered (file,
6393 "mips_dump_tdep: RA_REGNUM = %d\n",
6394 RA_REGNUM);
2475bac3
AC
6395#ifdef SAVED_BYTES
6396 fprintf_unfiltered (file,
6397 "mips_dump_tdep: SAVED_BYTES = %d\n",
6398 SAVED_BYTES);
6399#endif
6400#ifdef SAVED_FP
6401 fprintf_unfiltered (file,
6402 "mips_dump_tdep: SAVED_FP = %d\n",
6403 SAVED_FP);
6404#endif
6405#ifdef SAVED_PC
6406 fprintf_unfiltered (file,
6407 "mips_dump_tdep: SAVED_PC = %d\n",
6408 SAVED_PC);
6409#endif
6410 fprintf_unfiltered (file,
6411 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6412 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6413 fprintf_unfiltered (file,
6414 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6415 fprintf_unfiltered (file,
6416 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6417 SIGFRAME_BASE);
6418 fprintf_unfiltered (file,
6419 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6420 SIGFRAME_FPREGSAVE_OFF);
6421 fprintf_unfiltered (file,
6422 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6423 SIGFRAME_PC_OFF);
6424 fprintf_unfiltered (file,
6425 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6426 SIGFRAME_REGSAVE_OFF);
6427 fprintf_unfiltered (file,
6428 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6429 SIGFRAME_REG_SIZE);
6430 fprintf_unfiltered (file,
6431 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6432 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6433 fprintf_unfiltered (file,
6434 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6435 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6436 fprintf_unfiltered (file,
b0ed3589
AC
6437 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6438 SOFTWARE_SINGLE_STEP_P ());
2475bac3
AC
6439 fprintf_unfiltered (file,
6440 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6441 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6442#ifdef STACK_END_ADDR
6443 fprintf_unfiltered (file,
6444 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6445 STACK_END_ADDR);
6446#endif
6447 fprintf_unfiltered (file,
6448 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6449 XSTRING (STEP_SKIPS_DELAY (PC)));
6450 fprintf_unfiltered (file,
6451 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6452 STEP_SKIPS_DELAY_P);
6453 fprintf_unfiltered (file,
6454 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6455 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6456 fprintf_unfiltered (file,
6457 "mips_dump_tdep: T9_REGNUM = %d\n",
6458 T9_REGNUM);
6459 fprintf_unfiltered (file,
6460 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6461 fprintf_unfiltered (file,
6462 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6463 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
6464 fprintf_unfiltered (file,
6465 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6466 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
2475bac3
AC
6467#ifdef TRACE_CLEAR
6468 fprintf_unfiltered (file,
6469 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6470 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6471#endif
6472#ifdef TRACE_FLAVOR
6473 fprintf_unfiltered (file,
6474 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6475 TRACE_FLAVOR);
6476#endif
6477#ifdef TRACE_FLAVOR_SIZE
6478 fprintf_unfiltered (file,
6479 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6480 TRACE_FLAVOR_SIZE);
6481#endif
6482#ifdef TRACE_SET
6483 fprintf_unfiltered (file,
6484 "mips_dump_tdep: TRACE_SET # %s\n",
6485 XSTRING (TRACE_SET (X,STATE)));
6486#endif
2475bac3
AC
6487#ifdef UNUSED_REGNUM
6488 fprintf_unfiltered (file,
6489 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6490 UNUSED_REGNUM);
6491#endif
6492 fprintf_unfiltered (file,
6493 "mips_dump_tdep: V0_REGNUM = %d\n",
6494 V0_REGNUM);
6495 fprintf_unfiltered (file,
6496 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6497 (long) VM_MIN_ADDRESS);
6498#ifdef VX_NUM_REGS
6499 fprintf_unfiltered (file,
6500 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6501 VX_NUM_REGS);
6502#endif
6503 fprintf_unfiltered (file,
6504 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6505 ZERO_REGNUM);
6506 fprintf_unfiltered (file,
6507 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6508 _PROC_MAGIC_);
c2d11a7d
JM
6509}
6510
a78f21af
AC
6511extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6512
c906108c 6513void
acdb74a0 6514_initialize_mips_tdep (void)
c906108c
SS
6515{
6516 static struct cmd_list_element *mipsfpulist = NULL;
6517 struct cmd_list_element *c;
6518
2e4ebe70
DJ
6519 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
6520 if (MIPS_ABI_LAST + 1
6521 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6522 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6523
4b9b3959 6524 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
c906108c 6525
a5ea2558
AC
6526 /* Add root prefix command for all "set mips"/"show mips" commands */
6527 add_prefix_cmd ("mips", no_class, set_mips_command,
6528 "Various MIPS specific commands.",
6529 &setmipscmdlist, "set mips ", 0, &setlist);
6530
6531 add_prefix_cmd ("mips", no_class, show_mips_command,
6532 "Various MIPS specific commands.",
6533 &showmipscmdlist, "show mips ", 0, &showlist);
6534
6535 /* Allow the user to override the saved register size. */
6536 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
1ed2a135
AC
6537 class_obscure,
6538 size_enums,
6539 &mips_saved_regsize_string, "\
a5ea2558
AC
6540Set size of general purpose registers saved on the stack.\n\
6541This option can be set to one of:\n\
6542 32 - Force GDB to treat saved GP registers as 32-bit\n\
6543 64 - Force GDB to treat saved GP registers as 64-bit\n\
6544 auto - Allow GDB to use the target's default setting or autodetect the\n\
6545 saved GP register size from information contained in the executable.\n\
6546 (default: auto)",
1ed2a135 6547 &setmipscmdlist),
a5ea2558
AC
6548 &showmipscmdlist);
6549
d929b26f
AC
6550 /* Allow the user to override the argument stack size. */
6551 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6552 class_obscure,
6553 size_enums,
1ed2a135 6554 &mips_stack_argsize_string, "\
d929b26f
AC
6555Set the amount of stack space reserved for each argument.\n\
6556This option can be set to one of:\n\
6557 32 - Force GDB to allocate 32-bit chunks per argument\n\
6558 64 - Force GDB to allocate 64-bit chunks per argument\n\
6559 auto - Allow GDB to determine the correct setting from the current\n\
6560 target and executable (default)",
6561 &setmipscmdlist),
6562 &showmipscmdlist);
6563
2e4ebe70
DJ
6564 /* Allow the user to override the ABI. */
6565 c = add_set_enum_cmd
6566 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6567 "Set the ABI used by this program.\n"
6568 "This option can be set to one of:\n"
6569 " auto - the default ABI associated with the current binary\n"
6570 " o32\n"
6571 " o64\n"
6572 " n32\n"
f3a7b3a5 6573 " n64\n"
2e4ebe70
DJ
6574 " eabi32\n"
6575 " eabi64",
6576 &setmipscmdlist);
2e4ebe70 6577 set_cmd_sfunc (c, mips_abi_update);
ad188201
KB
6578 add_cmd ("abi", class_obscure, show_mips_abi,
6579 "Show ABI in use by MIPS target", &showmipscmdlist);
2e4ebe70 6580
c906108c
SS
6581 /* Let the user turn off floating point and set the fence post for
6582 heuristic_proc_start. */
6583
6584 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6585 "Set use of MIPS floating-point coprocessor.",
6586 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6587 add_cmd ("single", class_support, set_mipsfpu_single_command,
6588 "Select single-precision MIPS floating-point coprocessor.",
6589 &mipsfpulist);
6590 add_cmd ("double", class_support, set_mipsfpu_double_command,
8e1a459b 6591 "Select double-precision MIPS floating-point coprocessor.",
c906108c
SS
6592 &mipsfpulist);
6593 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6594 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6595 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6596 add_cmd ("none", class_support, set_mipsfpu_none_command,
6597 "Select no MIPS floating-point coprocessor.",
6598 &mipsfpulist);
6599 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6600 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6601 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6602 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6603 "Select MIPS floating-point coprocessor automatically.",
6604 &mipsfpulist);
6605 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6606 "Show current use of MIPS floating-point coprocessor target.",
6607 &showlist);
6608
c906108c
SS
6609 /* We really would like to have both "0" and "unlimited" work, but
6610 command.c doesn't deal with that. So make it a var_zinteger
6611 because the user can always use "999999" or some such for unlimited. */
6612 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6613 (char *) &heuristic_fence_post,
6614 "\
6615Set the distance searched for the start of a function.\n\
6616If you are debugging a stripped executable, GDB needs to search through the\n\
6617program for the start of a function. This command sets the distance of the\n\
6618search. The only need to set it is when debugging a stripped executable.",
6619 &setlist);
6620 /* We need to throw away the frame cache when we set this, since it
6621 might change our ability to get backtraces. */
9f60d481 6622 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
c906108c
SS
6623 add_show_from_set (c, &showlist);
6624
6625 /* Allow the user to control whether the upper bits of 64-bit
6626 addresses should be zeroed. */
e9e68a56
AC
6627 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6628Set zeroing of upper 32 bits of 64-bit addresses.\n\
6629Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6630allow GDB to determine the correct value.\n", "\
6631Show zeroing of upper 32 bits of 64-bit addresses.",
6632 NULL, show_mask_address,
6633 &setmipscmdlist, &showmipscmdlist);
43e526b9
JM
6634
6635 /* Allow the user to control the size of 32 bit registers within the
6636 raw remote packet. */
6637 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6638 class_obscure,
6639 var_boolean,
6640 (char *)&mips64_transfers_32bit_regs_p, "\
6641Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6642Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6643that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
664464 bits for others. Use \"off\" to disable compatibility mode",
6645 &setlist),
6646 &showlist);
9ace0497
AC
6647
6648 /* Debug this files internals. */
6649 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6650 &mips_debug, "Set mips debugging.\n\
6651When non-zero, mips specific debugging is enabled.", &setdebuglist),
6652 &showdebuglist);
c906108c 6653}
This page took 0.82308 seconds and 4 git commands to generate.